[PowerPC] Add the Power10 LXVKQ instrution.

[stefanp]

Summary

Add the Power 10 instruction LXVKQ.

This patch was taken from an original patch by: Yi-Hong Lyu

[lei]

LGTM, just a minor comment.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

1697 ↗

(On Diff #400614)

Any reason why we don't want this in the existing IsISA3_1 section on line 1898?

[stefanp]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

1697 ↗

(On Diff #400614)

Any reason why we don't want this in the existing IsISA3_1 section on line 1898?

It was separate in the original patch so I just left it where the original patch put it. There is no reason not to move it so I'll move it down.

[stefanp]

Rebased the patch.
Moved the def for LXVKQ lower down.

llvm/lib/Target/PowerPC/P10InstrResources.td

def : InstRW<[P10W_PM_4C, P10W_DISP_ANY],
     VSPLTISW, V_SETALLONES, V_SETALLONESB, V_SETALLONESH
 )>;
 
 // 4 Cycles Permute operations, 1 input operands
 def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read],
       (instrs
     LVSL,
     LVSR,
+    LXVKQ,
     MFVSRLD,
     MTVSRWS,
     VCLZLSBB,
     VCTZLSBB,
     VGBBD,
     VPRTYBQ,
     VSPLTISB,
     VSPLTISH,

llvm/lib/Target/PowerPC/PPCInstrP10.td

class XForm_AT3<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
   let Inst{6-8}  = AT;
   let Inst{9-10}  = 0;
   let Inst{11-15} = xo2;
   let Inst{16-20} = 0;
   let Inst{21-30} = xo;
   let Inst{31} = 0;
 }
 
+// X-Form: [ PO T EO UIM XO TX ]
+class XForm_XT6_IMM5<bits<6> opcode, bits<5> eo, bits<10> xo, dag OOL, dag IOL,
+                     string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bits<5> UIM;
+
+  let Pattern = pattern;
+
+  let Inst{6-10} = XT{4-0};
+  let Inst{11-15} = eo;
+  let Inst{16-20} = UIM;
+  let Inst{21-30} = xo;
+  let Inst{31} = XT{5};
+}
+
 class XX3Form_AT3_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
                            string asmstr, InstrItinClass itin,
                            list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<3> AT;
   bits<6> XA;
   bits<6> XB;
 
let Predicates = [IsISA3_1] in {
   def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>;
   def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>;
   def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>;
   def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>;
   def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>;
   def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>;
   def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>;
   def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;
+  def LXVKQ : XForm_XT6_IMM5<60, 31, 360, (outs vsrc:$XT), (ins u5imm:$UIM),
+                             "lxvkq $XT, $UIM", IIC_VecGeneral, []>;
 }
 
 let Predicates = [IsISA3_1, HasVSX] in {
   def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>;
   def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>;
   def XSMAXCQP : X_VT5_VA5_VB5<63, 676, "xsmaxcqp",
                                [(set f128:$vT, (PPCxsmaxc f128:$vA, f128:$vB))]>;
   def XSMINCQP : X_VT5_VA5_VB5<63, 740, "xsmincqp",

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt

 0x7c 0x41 0x21 0xb8
 
 # CHECK: vgnb 1, 2, 2
 0x10 0x22 0x14 0xcc
 
 # CHECK: xxeval 32, 1, 2, 3, 2
 0x05 0x00 0x00 0x02 0x88 0x01 0x10 0xd1
 
+# CHECK: lxvkq 63, 31
+0xf3 0xff 0xfa 0xd1
+
 # CHECK: vclzdm 1, 2, 3
 0x10 0x22 0x1f 0x84
 
 # CHECK: vctzdm 1, 2, 3
 0x10 0x22 0x1f 0xc4
 
 # CHECK: cntlzdm 1, 3, 2
 0x7c 0x61 0x10 0x76

llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s

 # CHECK-BE: vgnb 1, 2, 2                          # encoding: [0x10,0x22,0x14,0xcc]
 # CHECK-LE: vgnb 1, 2, 2                          # encoding: [0xcc,0x14,0x22,0x10]
             vgnb 1, 2, 2
 # CHECK-BE: xxeval 32, 1, 2, 3, 2                 # encoding: [0x05,0x00,0x00,0x02,
 # CHECK-BE-SAME:                                               0x88,0x01,0x10,0xd1]
 # CHECK-LE: xxeval 32, 1, 2, 3, 2                 # encoding: [0x02,0x00,0x00,0x05,
 # CHECK-LE-SAME:                                               0xd1,0x10,0x01,0x88]
             xxeval 32, 1, 2, 3, 2
+# CHECK-BE: lxvkq 63, 31                          # encoding: [0xf3,0xff,0xfa,0xd1]
+# CHECK-LE: lxvkq 63, 31                          # encoding: [0xd1,0xfa,0xff,0xf3]
+            lxvkq 63, 31
 # CHECK-BE: vclzdm 1, 2, 3                        # encoding: [0x10,0x22,0x1f,0x84]
 # CHECK-LE: vclzdm 1, 2, 3                        # encoding: [0x84,0x1f,0x22,0x10]
             vclzdm 1, 2, 3
 # CHECK-BE: vctzdm 1, 2, 3                        # encoding: [0x10,0x22,0x1f,0xc4]
 # CHECK-LE: vctzdm 1, 2, 3                        # encoding: [0xc4,0x1f,0x22,0x10]
             vctzdm 1, 2, 3
 # CHECK-BE: cntlzdm 1, 3, 2                       # encoding: [0x7c,0x61,0x10,0x76]
 # CHECK-LE: cntlzdm 1, 3, 2                       # encoding: [0x76,0x10,0x61,0x7c]