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Differential D117311

[RISCV] Add CSRs defined in the recently ratified Sstc extension
ClosedPublic

Authored by asb on Jan 14 2022, 6:54 AM.

Details

Reviewers
craig.topper
luismarques
kito-cheng
Commits
rG0ee679e22cfb: [RISCV] Add CSRs defined in the recently ratified Sstc extension
Summary

The 'RISC-V "stimecmp / vstimecmp" Extension' was ratified at the end of
last year though hasn't yet been integrated in the main specification
documents (see
https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions).

RISC-V "stimecmp / vstimecmp" Extension
https://github.com/riscv/riscv-time-compare/releases/download/v0.5.4/Sstc.pdf.

Diff Detail

Event Timeline

asb created this revision.Jan 14 2022, 6:54 AM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 25 others. · View Herald TranscriptJan 14 2022, 6:54 AM
asb requested review of this revision.Jan 14 2022, 6:54 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 14 2022, 6:54 AM
Herald added a subscriber: MaskRay. · View Herald Transcript
asb added a parent revision: D117310: [RISCV] Add CSRs defined in the recently ratified Smstateen extension.Jan 14 2022, 6:54 AM
Harbormaster completed remote builds in B143375: Diff 399977.Jan 14 2022, 8:07 AM
craig.topper accepted this revision.Jan 14 2022, 12:20 PM

LGTM

This revision is now accepted and ready to land.Jan 14 2022, 12:20 PM
Closed by commit rG0ee679e22cfb: [RISCV] Add CSRs defined in the recently ratified Sstc extension (authored by asb). · Explain WhyJan 15 2022, 12:36 AM
This revision was automatically updated to reflect the committed changes.
asb added a commit: rG0ee679e22cfb: [RISCV] Add CSRs defined in the recently ratified Sstc extension.
MaskRay added a comment.Jan 15 2022, 12:38 AM
This comment was removed by MaskRay.

Revision Contents

Diff 400259

llvm/lib/Target/RISCV/RISCVSystemOperands.td

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// Supervisor Trap Setup // Supervisor Trap Setup
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : SysReg<"sstatus", 0x100>; def : SysReg<"sstatus", 0x100>;
def : SysReg<"sedeleg", 0x102>; def : SysReg<"sedeleg", 0x102>;
def : SysReg<"sideleg", 0x103>; def : SysReg<"sideleg", 0x103>;
def : SysReg<"sie", 0x104>; def : SysReg<"sie", 0x104>;
def : SysReg<"stvec", 0x105>; def : SysReg<"stvec", 0x105>;
def : SysReg<"scounteren", 0x106>; def : SysReg<"scounteren", 0x106>;
def : SysReg<"stimecmp", 0x14D>;
let isRV32Only = 1 in
def : SysReg<"stimecmph", 0x15D>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Supervisor Configuration // Supervisor Configuration
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : SysReg<"senvcfg", 0x10A>; def : SysReg<"senvcfg", 0x10A>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
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def : SysReg<"vsstatus", 0x200>; def : SysReg<"vsstatus", 0x200>;
def : SysReg<"vsie", 0x204>; def : SysReg<"vsie", 0x204>;
def : SysReg<"vstvec", 0x205>; def : SysReg<"vstvec", 0x205>;
def : SysReg<"vsscratch", 0x240>; def : SysReg<"vsscratch", 0x240>;
def : SysReg<"vsepc", 0x241>; def : SysReg<"vsepc", 0x241>;
def : SysReg<"vscause", 0x242>; def : SysReg<"vscause", 0x242>;
def : SysReg<"vstval", 0x243>; def : SysReg<"vstval", 0x243>;
def : SysReg<"vsip", 0x244>; def : SysReg<"vsip", 0x244>;
def : SysReg<"vstimecmp", 0x24D>;
let isRV32Only = 1 in
def : SysReg<"vstimecmph", 0x25D>;
def : SysReg<"vsatp", 0x280>; def : SysReg<"vsatp", 0x280>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Machine Information Registers // Machine Information Registers
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : SysReg<"mvendorid", 0xF11>; def : SysReg<"mvendorid", 0xF11>;
def : SysReg<"marchid", 0xF12>; def : SysReg<"marchid", 0xF12>;
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llvm/test/MC/RISCV/hypervisor-csr-names.s

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# CHECK-INST: csrrs t2, vsip, zero # CHECK-INST: csrrs t2, vsip, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x24] # CHECK-ENC: encoding: [0xf3,0x23,0x40,0x24]
# CHECK-INST-ALIAS: csrr t2, vsip # CHECK-INST-ALIAS: csrr t2, vsip
# name # name
csrrs t1, vsip, zero csrrs t1, vsip, zero
# uimm12 # uimm12
csrrs t2, 0x244, zero csrrs t2, 0x244, zero
# vstimecmp
# name
# CHECK-INST: csrrs t1, vstimecmp, zero
# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x24]
# CHECK-INST-ALIAS: csrr t1, vstimecmp
# uimm12
# CHECK-INST: csrrs t2, vstimecmp, zero
# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x24]
# CHECK-INST-ALIAS: csrr t2, vstimecmp
# name
csrrs t1, vstimecmp, zero
# uimm12
csrrs t2, 0x24D, zero
# vsatp # vsatp
# name # name
# CHECK-INST: csrrs t1, vsatp, zero # CHECK-INST: csrrs t1, vsatp, zero
# CHECK-ENC: encoding: [0x73,0x23,0x00,0x28] # CHECK-ENC: encoding: [0x73,0x23,0x00,0x28]
# CHECK-INST-ALIAS: csrr t1, vsatp # CHECK-INST-ALIAS: csrr t1, vsatp
# uimm12 # uimm12
# CHECK-INST: csrrs t2, vsatp, zero # CHECK-INST: csrrs t2, vsatp, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x28] # CHECK-ENC: encoding: [0xf3,0x23,0x00,0x28]
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llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s

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# CHECK-INST: csrrs t2, htimedeltah, zero # CHECK-INST: csrrs t2, htimedeltah, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x61] # CHECK-ENC: encoding: [0xf3,0x23,0x50,0x61]
# CHECK-INST-ALIAS: csrr t2, htimedeltah # CHECK-INST-ALIAS: csrr t2, htimedeltah
# name # name
csrrs t1, htimedeltah, zero csrrs t1, htimedeltah, zero
# uimm12 # uimm12
csrrs t2, 0x615, zero csrrs t2, 0x615, zero
################################
# Virtual Supervisor Registers
################################
# vstimecmph
# name
# CHECK-INST: csrrs t1, vstimecmph, zero
# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x25]
# CHECK-INST-ALIAS: csrr t1, vstimecmph
# uimm12
# CHECK-INST: csrrs t2, vstimecmph, zero
# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x25]
# CHECK-INST-ALIAS: csrr t2, vstimecmph
# name
csrrs t1, vstimecmph, zero
# uimm12
csrrs t2, 0x25D, zero
######################################### #########################################
# State Enable Extension (Smstateen) # State Enable Extension (Smstateen)
######################################### #########################################
# hstateen0h # hstateen0h
# name # name
# CHECK-INST: csrrs t1, hstateen0h, zero # CHECK-INST: csrrs t1, hstateen0h, zero
# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x61] # CHECK-ENC: encoding: [0x73,0x23,0xc0,0x61]
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llvm/test/MC/RISCV/rv32-only-csr-names.s

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csrrs t1, mstateen1h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, mstateen1h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, mstateen3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, mstateen3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, mstateen3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, mstateen3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, hstateen0h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, hstateen0h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, hstateen1h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, hstateen1h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, hstateen3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, hstateen3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, hstateen3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, hstateen3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, stimecmph, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, vstimecmph, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled

llvm/test/MC/RISCV/rv32-supervisor-csr-names.s

  • This file was added.
# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
# RUN: | llvm-objdump -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
##################################
# Supervisor Trap Setup
##################################
# stimecmph
# name
# CHECK-INST: csrrs t1, stimecmph, zero
# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x15]
# CHECK-INST-ALIAS: csrr t1, stimecmph
# uimm12
# CHECK-INST: csrrs t2, stimecmph, zero
# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x15]
# CHECK-INST-ALIAS: csrr t2, stimecmph
# name
csrrs t1, stimecmph, zero
# uimm12
csrrs t2, 0x15D, zero

llvm/test/MC/RISCV/supervisor-csr-names.s

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# CHECK-INST: csrrs t2, scounteren, zero # CHECK-INST: csrrs t2, scounteren, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x10] # CHECK-ENC: encoding: [0xf3,0x23,0x60,0x10]
# CHECK-INST-ALIAS: csrr t2, scounteren # CHECK-INST-ALIAS: csrr t2, scounteren
# name # name
csrrs t1, scounteren, zero csrrs t1, scounteren, zero
# uimm12 # uimm12
csrrs t2, 0x106, zero csrrs t2, 0x106, zero
# stimecmp
# name
# CHECK-INST: csrrs t1, stimecmp, zero
# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x14]
# CHECK-INST-ALIAS: csrr t1, stimecmp
# uimm12
# CHECK-INST: csrrs t2, stimecmp, zero
# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x14]
# CHECK-INST-ALIAS: csrr t2, stimecmp
# name
csrrs t1, stimecmp, zero
# uimm12
csrrs t2, 0x14D, zero
################################## ##################################
# Supervisor Configuration # Supervisor Configuration
################################## ##################################
# senvcfg # senvcfg
# name # name
# CHECK-INST: csrrs t1, senvcfg, zero # CHECK-INST: csrrs t1, senvcfg, zero
# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x10] # CHECK-ENC: encoding: [0x73,0x23,0xa0,0x10]
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