[RISCV] Optimize some special mul operation in Zba extension

[Jimerlife]

Summary

Optimized (mul x, 27), (mul x, 45), (mul x, 81) in previous patterns may has some problem. Cannot generate two same assembly SH3ADD x, x after isel, so I removed those groups patterns and add some mul optimization which referred to before optimization.

Before:
(mul x, 27) -> (SH1ADD (SH3ADD x, x), (SH3ADD x, x))
(mul x, 45) -> (SH2ADD (SH3ADD x, x), (SH3ADD x, x))
(mul x, 81) -> (SH3ADD (SH3ADD x, x), (SH3ADD x, x))

My Add:
(mul x, 23) -> (SH2ADD (SH2ADD x, x), (SH1ADD x, x))
(mul x, 43) -> (SH3ADD (SH2ADD x, x), (SH1ADD x, x))
(mul x, 39) -> (SH2ADD (SH3ADD x, x), (SH1ADD x, x))
(mul x, 75) -> (SH3ADD (SH3ADD x, x), (SH1ADD x, x))
(mul x, 77) -> (SH3ADD (SH3ADD x, x), (SH2ADD x, x))

[craig.topper]

I don't understand the problem with 27, 45, and 81. There shouldn't be a problem generating two same instructions. X86 does it in multiple places. Can you explain more?

[craig.topper]

The new patterns with 3 instructions might not be profitable for my company's CPUs.

[Jimerlife]

There is no problem with 27, 45, 81. I will abandon this revision.

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

 def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 37)),
           (SH2ADD (SH3ADD GPR:$r, GPR:$r), GPR:$r)>;
 def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 25)),
           (SH3ADD (SH1ADD GPR:$r, GPR:$r), GPR:$r)>;
 def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 41)),
           (SH3ADD (SH2ADD GPR:$r, GPR:$r), GPR:$r)>;
 def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 73)),
           (SH3ADD (SH3ADD GPR:$r, GPR:$r), GPR:$r)>;
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 27)),
-          (SH1ADD (SH3ADD GPR:$r, GPR:$r), (SH3ADD GPR:$r, GPR:$r))>;
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 45)),
-          (SH2ADD (SH3ADD GPR:$r, GPR:$r), (SH3ADD GPR:$r, GPR:$r))>;
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 81)),
-          (SH3ADD (SH3ADD GPR:$r, GPR:$r), (SH3ADD GPR:$r, GPR:$r))>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 23)),
+          (SH2ADD (SH2ADD GPR:$r, GPR:$r), (SH1ADD GPR:$r, GPR:$r))>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 43)),
+          (SH3ADD (SH2ADD GPR:$r, GPR:$r), (SH1ADD GPR:$r, GPR:$r))>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 39)),
+          (SH2ADD (SH3ADD GPR:$r, GPR:$r), (SH1ADD GPR:$r, GPR:$r))>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 75)),
+          (SH3ADD (SH3ADD GPR:$r, GPR:$r), (SH1ADD GPR:$r, GPR:$r))>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 77)),
+          (SH3ADD (SH3ADD GPR:$r, GPR:$r), (SH2ADD GPR:$r, GPR:$r))>;
 } // Predicates = [HasStdExtZba]
 
 let Predicates = [HasStdExtZba, IsRV64] in {
 def : Pat<(i64 (shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt)),
           (SLLIUW GPR:$rs1, uimm5:$shamt)>;
 def : Pat<(i64 (add (and GPR:$rs1, 0xFFFFFFFF), non_imm12:$rs2)),
           (ADDUW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(i64 (and GPR:$rs, 0xFFFFFFFF)), (ADDUW GPR:$rs, X0)>;

llvm/test/CodeGen/RISCV/rv64zba.ll

 ; RV64ZBA:       # %bb.0:
 ; RV64ZBA-NEXT:    sh3add a1, a0, a0
 ; RV64ZBA-NEXT:    sh3add a0, a1, a0
 ; RV64ZBA-NEXT:    ret
   %c = mul i64 %a, 73
   ret i64 %c
 }
 
-define i64 @mul27(i64 %a) {
-; RV64I-LABEL: mul27:
+define i64 @mul23(i64 %a) {
+; RV64I-LABEL: mul23:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, 27
+; RV64I-NEXT:    li a1, 23
 ; RV64I-NEXT:    mul a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBA-LABEL: mul27:
+; RV64ZBA-LABEL: mul23:
 ; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    sh3add a0, a0, a0
-; RV64ZBA-NEXT:    sh1add a0, a0, a0
+; RV64ZBA-NEXT:    sh1add a1, a0, a0
+; RV64ZBA-NEXT:    sh2add a0, a0, a0
+; RV64ZBA-NEXT:    sh2add a0, a0, a1
 ; RV64ZBA-NEXT:    ret
-  %c = mul i64 %a, 27
+  %c = mul i64 %a, 23
   ret i64 %c
 }
 
-define i64 @mul45(i64 %a) {
-; RV64I-LABEL: mul45:
+define i64 @mul43(i64 %a) {
+; RV64I-LABEL: mul43:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, 45
+; RV64I-NEXT:    li a1, 43
 ; RV64I-NEXT:    mul a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBA-LABEL: mul45:
+; RV64ZBA-LABEL: mul43:
 ; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    sh3add a0, a0, a0
+; RV64ZBA-NEXT:    sh1add a1, a0, a0
 ; RV64ZBA-NEXT:    sh2add a0, a0, a0
+; RV64ZBA-NEXT:    sh3add a0, a0, a1
 ; RV64ZBA-NEXT:    ret
-  %c = mul i64 %a, 45
+  %c = mul i64 %a, 43
   ret i64 %c
 }
 
-define i64 @mul81(i64 %a) {
-; RV64I-LABEL: mul81:
+define i64 @mul39(i64 %a) {
+; RV64I-LABEL: mul39:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, 81
+; RV64I-NEXT:    li a1, 39
 ; RV64I-NEXT:    mul a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBA-LABEL: mul81:
+; RV64ZBA-LABEL: mul39:
 ; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    sh1add a1, a0, a0
 ; RV64ZBA-NEXT:    sh3add a0, a0, a0
+; RV64ZBA-NEXT:    sh2add a0, a0, a1
+; RV64ZBA-NEXT:    ret
+  %c = mul i64 %a, 39
+  ret i64 %c
+}
+
+define i64 @mul75(i64 %a) {
+; RV64I-LABEL: mul75:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a1, 75
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64ZBA-LABEL: mul75:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    sh1add a1, a0, a0
+; RV64ZBA-NEXT:    sh3add a0, a0, a0
+; RV64ZBA-NEXT:    sh3add a0, a0, a1
+; RV64ZBA-NEXT:    ret
+  %c = mul i64 %a, 75
+  ret i64 %c
+}
+
+define i64 @mul77(i64 %a) {
+; RV64I-LABEL: mul77:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a1, 77
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64ZBA-LABEL: mul77:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    sh2add a1, a0, a0
 ; RV64ZBA-NEXT:    sh3add a0, a0, a0
+; RV64ZBA-NEXT:    sh3add a0, a0, a1
 ; RV64ZBA-NEXT:    ret
-  %c = mul i64 %a, 81
+  %c = mul i64 %a, 77
   ret i64 %c
 }
 
 define i64 @mul4098(i64 %a) {
 ; RV64I-LABEL: mul4098:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1
 ; RV64I-NEXT:    addiw a1, a1, 2