[RISCV] Remove stale references to experimental-b. NFC

[asb]

LGTM, modulo a slight error in the find and replace for the test comments.

llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll

171–172

"Bitmanip extensions extension" => "Bitmanip extensions" or "the Bitmanip extensions"

(Same for other instances of this replacement).

[craig.topper]

llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll

171–172

Guess I should have read the whole sentence

[craig.topper]

Address comment

llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll

 ; RV32ZBP-LABEL: rol_i32:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    rol a0, a0, a1
 ; RV32ZBP-NEXT:    ret
   %or = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %b)
   ret i32 %or
 }
 
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
 
 declare i64 @llvm.fshl.i64(i64, i64, i64)
 
 define i64 @rol_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: rol_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a3, a2, 5
 ; RV32I-NEXT:    andi a3, a3, 1

 ; RV32ZBP-LABEL: ror_i32:
 ; RV32ZBP:       # %bb.0:
 ; RV32ZBP-NEXT:    ror a0, a0, a1
 ; RV32ZBP-NEXT:    ret
   %or = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %b)
   ret i32 %or
 }
 
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
 
 declare i64 @llvm.fshr.i64(i64, i64, i64)
 
 define i64 @ror_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: ror_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    andi a4, a2, 32
 ; RV32I-NEXT:    mv a3, a0

llvm/test/CodeGen/RISCV/rv32zbb.ll

 ; RV32ZBB-NEXT:    ret
   %cmp = icmp slt i32 %a, %b
   %cond = select i1 %cmp, i32 %a, i32 %b
   ret i32 %cond
 }
 
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
 
 define i64 @min_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: min_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    beq a1, a3, .LBB11_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    slt a4, a1, a3
 ; RV32I-NEXT:    beqz a4, .LBB11_3

 ; RV32ZBB-NEXT:    ret
   %cmp = icmp sgt i32 %a, %b
   %cond = select i1 %cmp, i32 %a, i32 %b
   ret i32 %cond
 }
 
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
 
 define i64 @max_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: max_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    beq a1, a3, .LBB13_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    slt a4, a3, a1
 ; RV32I-NEXT:    beqz a4, .LBB13_3

 ; RV32ZBB-NEXT:    ret
   %cmp = icmp ult i32 %a, %b
   %cond = select i1 %cmp, i32 %a, i32 %b
   ret i32 %cond
 }
 
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
 
 define i64 @minu_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: minu_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    beq a1, a3, .LBB15_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a4, a1, a3
 ; RV32I-NEXT:    beqz a4, .LBB15_3

 ; RV32ZBB-NEXT:    ret
   %cmp = icmp ugt i32 %a, %b
   %cond = select i1 %cmp, i32 %a, i32 %b
   ret i32 %cond
 }
 
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
 
 define i64 @maxu_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: maxu_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    beq a1, a3, .LBB17_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a4, a3, a1
 ; RV32I-NEXT:    beqz a4, .LBB17_3

llvm/test/CodeGen/RISCV/rv32zbp.ll

; RV32ZBP-NEXT:    ret
   %shl = and i32 %a, 65535
   %shl1 = shl i32 %b, 16
   %or = or i32 %shl1, %shl
   ret i32 %or
 }
 
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
 
 define i64 @pack_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: pack_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBP-LABEL: pack_i64:
; RV32ZBP-NEXT:    ret
   %shr = lshr i32 %a, 16
   %shr1 = and i32 %b, -65536
   %or = or i32 %shr1, %shr
   ret i32 %or
 }
 
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
 
 define i64 @packu_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: packu_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    ret
 ;

llvm/test/CodeGen/RISCV/rv32zbs.ll

 ; RV32ZBS-NEXT:    bset a0, zero, a0
 ; RV32ZBS-NEXT:    ret
   %shl = shl i32 1, %a
   ret i32 %shl
 }
 
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
 
 define i64 @bset_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: bset_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a3, 1
 ; RV32I-NEXT:    sll a2, a3, a2
 ; RV32I-NEXT:    srai a3, a2, 31
 ; RV32I-NEXT:    or a0, a2, a0
; RV32ZBS-NEXT:    ret
   %and = and i32 %b, 31
   %shl = shl nuw i32 1, %and
   %xor = xor i32 %shl, %a
   ret i32 %xor
 }
 
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
 
 define i64 @binv_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: binv_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a3, 1
 ; RV32I-NEXT:    sll a2, a3, a2
 ; RV32I-NEXT:    srai a3, a2, 31
 ; RV32I-NEXT:    xor a0, a2, a0

 ; RV32ZBS-NEXT:    ret
   %shr = lshr i32 %a, %b
   %and1 = and i32 %shr, 1
   ret i32 %and1
 }
 
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions suitable for this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
 
 define i64 @bext_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: bext_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    andi a3, a2, 63
 ; RV32I-NEXT:    addi a4, a3, -32
 ; RV32I-NEXT:    bltz a4, .LBB12_2
 ; RV32I-NEXT:  # %bb.1:

llvm/test/CodeGen/RISCV/rv32zbt.ll

 ; RV32ZBT-NEXT:    ret
   %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
   ret i32 %1
 }
 
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet an efficient pattern-matching with bit manipulation
 ; instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions that can match more efficiently this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions that can match more efficiently this pattern.
 
 declare i64 @llvm.fshl.i64(i64, i64, i64)
 
 define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV32I-LABEL: fshl_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a5, a4, 5
 ; RV32I-NEXT:    andi a5, a5, 1

 ; RV32ZBT-NEXT:    ret
   %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
   ret i32 %1
 }
 
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet an efficient pattern-matching with bit manipulation
 ; instructions on RV32.
-; This test is presented here in case future expansions of the experimental-b
-; extension introduce instructions that can match more efficiently this pattern.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions that can match more efficiently this pattern.
 
 declare i64 @llvm.fshr.i64(i64, i64, i64)
 
 define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV32I-LABEL: fshr_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    andi a5, a4, 32
 ; RV32I-NEXT:    beqz a5, .LBB15_2

llvm/test/MC/RISCV/rv32zba-invalid.s

-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zba < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zba < %s 2>&1 | FileCheck %s
 
 # Too few operands
 sh1add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 sh2add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 sh3add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 slli.uw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
 add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
 sh1add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
 sh2add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
 sh3add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set

llvm/test/MC/RISCV/rv32zbb-invalid.s

-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zbb < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zbb < %s 2>&1 | FileCheck %s
 
 # Too many operands
 clz t0, t1, t2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 # Too many operands
 ctz t0, t1, t2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 # Too many operands
 cpop t0, t1, t2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
 # Too many operands

llvm/test/MC/RISCV/rv32zbbp-invalid.s

-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zbb,experimental-zbp < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zbb,+experimental-zbp < %s 2>&1 | FileCheck %s
 
 # Too few operands
 andn t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 orn t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 xnor t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands

llvm/test/MC/RISCV/rv32zbc-invalid.s

-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zbc < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zbc < %s 2>&1 | FileCheck %s
 
 # Too few operands
 clmul t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 clmulr t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 clmulh t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv32zbe-invalid.s

-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbe < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbe < %s 2>&1 | FileCheck %s
 
 # Too few operands
 bdecompress t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 bcompress t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 bdecompressw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
 bcompressw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set

llvm/test/MC/RISCV/rv32zbf-invalid.s

-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbf < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbf < %s 2>&1 | FileCheck %s
 
 # Too few operands
 bfp t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 bfpw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set

llvm/test/MC/RISCV/rv32zbp-invalid.s

-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbp < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbp < %s 2>&1 | FileCheck %s
 
 # Too few operands
 gorc t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 grev t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 gorci t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range

llvm/test/MC/RISCV/rv32zbr-invalid.s

-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbr < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbr < %s 2>&1 | FileCheck %s
 
 # Too many operands
 crc32.b t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
 # Too many operands
 crc32.h t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
 # Too many operands
 crc32.w t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
 # Too many operands
 crc32c.b t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
 # Too many operands
 crc32c.h t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
 # Too many operands
 crc32c.w t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
 crc32.d t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
 crc32c.d t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set

llvm/test/MC/RISCV/rv32zbs-invalid.s

-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zbs < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zbs < %s 2>&1 | FileCheck %s
 
 # Too few operands
 bclr t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 bset t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 binv t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands

llvm/test/MC/RISCV/rv32zbt-invalid.s

-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbt < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbt < %s 2>&1 | FileCheck %s
 
 # Too few operands
 cmix t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 cmov t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 fsl t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands

llvm/test/MC/RISCV/rv64zba-invalid.s

-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,zba < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zba < %s 2>&1 | FileCheck %s
 
 # Too few operands
 slli.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
 slli.uw t0, t1, 64 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
 slli.uw t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
 # Too few operands
 add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 sh1add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 sh2add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 sh3add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64zbb-invalid.s

-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,zbb < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zbb < %s 2>&1 | FileCheck %s
 
 # Too many operands
 clzw t0, t1, t2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
 # Too many operands
 ctzw t0, t1, t2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
 # Too many operands
 cpopw t0, t1, t2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction

llvm/test/MC/RISCV/rv64zbbp-invalid.s

-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,zbb,experimental-zbp < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zbb,+experimental-zbp < %s 2>&1 | FileCheck %s
 
 # Too few operands
 rolw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 rorw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 roriw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
 roriw t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
 roriw t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
 # Too few operands
 packw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 packuw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64zbe-invalid.s

-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbe < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbe < %s 2>&1 | FileCheck %s
 
 # Too few operands
 bdecompressw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 bcompressw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64zbf-invalid.s

-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbf < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbf < %s 2>&1 | FileCheck %s
 
 # Too few operands
 bfpw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64zbm-invalid.s

-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbm < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbm < %s 2>&1 | FileCheck %s
 
 # Too many operands
 bmatflip t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
 # Too few operands
 bmator t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 bmatxor t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64zbp-invalid.s

-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbp < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbp < %s 2>&1 | FileCheck %s
 
 # Too few operands
 gorcw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 grevw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 gorciw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range

llvm/test/MC/RISCV/rv64zbr-invalid.s

-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbr < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbr < %s 2>&1 | FileCheck %s
 
 # Too many operands
 crc32.d t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
 # Too many operands
 crc32c.d t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction

llvm/test/MC/RISCV/rv64zbt-invalid.s

-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbt < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbt < %s 2>&1 | FileCheck %s
 
 # Too few operands
 fslw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 fsrw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
 fsriw t0, t1, t2, 32 # CHECK: :[[@LINE]]:19: error: immediate must be an integer in the range [0, 31]
 fsriw t0, t1, t2, -1 # CHECK: :[[@LINE]]:19: error: immediate must be an integer in the range [0, 31]