[PowerPC] Add assembly comments for instructions that use the vector registers.

[stefanp]

Summary

A number of register types overlap with the vector registers. When reading the
assembly it is not immediately obvious what vector registers overlap with what
other registers. This patch aims to add a comment to show which VSR registers
are used or defined for each instruction.

[amyk]

nit: The description has regsiter a number of times, please update it to register

This a ver useful patch. Thanks Stefan! I have a question (might be silly but...), if verbose asm is enabled by default, does it require an update to more than the two test cases that you've updated in this patch?
(I guess what I am getting at here is if verbose asm is enabled by default, I would have expected a whole bunch of other tests to also require updating, but I may be misunderstanding here.)

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstComments.cpp

22

124

[stefanp]

Updated a couple of comments.

[stefanp]

In D116743#3227465, @amyk wrote:

nit: The description has regsiter a number of times, please update it to register

This a ver useful patch. Thanks Stefan! I have a question (might be silly but...), if verbose asm is enabled by default, does it require an update to more than the two test cases that you've updated in this patch?
(I guess what I am getting at here is if verbose asm is enabled by default, I would have expected a whole bunch of other tests to also require updating, but I may be misunderstanding here.)

For some reason I always seem to typo the word register. Not sure why... Anyway, thank you for finding them.

Not a silly question at all!
Initially I thought that I didn't need to update the tests because I wan't changing code and the CHECK/CHECK-NEXT lines don't really care that there are comments that come after the instructions. This is true in most cases but there are tests that already have a comment after the instruction line (for example # 8-byte Folded Spill) and in those cases by adding a second comment I'm adding a new line and the CHECK-NEXT lines don't work anymore. Anyway, I'm going to update those tests now.

[stefanp]

Updated a whole set of tests that now have additional comments.

[amyk]

In D116743#3250956, @stefanp wrote:

In D116743#3227465, @amyk wrote:

nit: The description has regsiter a number of times, please update it to register

This a ver useful patch. Thanks Stefan! I have a question (might be silly but...), if verbose asm is enabled by default, does it require an update to more than the two test cases that you've updated in this patch?
(I guess what I am getting at here is if verbose asm is enabled by default, I would have expected a whole bunch of other tests to also require updating, but I may be misunderstanding here.)

For some reason I always seem to typo the word register. Not sure why... Anyway, thank you for finding them.

Not a silly question at all!
Initially I thought that I didn't need to update the tests because I wan't changing code and the CHECK/CHECK-NEXT lines don't really care that there are comments that come after the instructions. This is true in most cases but there are tests that already have a comment after the instruction line (for example # 8-byte Folded Spill) and in those cases by adding a second comment I'm adding a new line and the CHECK-NEXT lines don't work anymore. Anyway, I'm going to update those tests now.

Thanks for addressing the comment, Stefan!
I think overall, it LGTM.

[lei]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstComments.cpp

33–40

This seems like something that can be useful in other implementations.
Wondering if it's better is we define functions such as isRegInClass(), isVecReg() similar to what's defined in PPCVSXSwapRemoval.cpp but have it as part of class PPCRegisterInfo. Currently I see diff implementation of similar checks in various classes.

113

Wondering why this is not implemented as part of the PPCInstPrinter class since it's only ever used for printing PPC instructions.

156

This bool return value seem to have no uses.

llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll

152 ↗

(On Diff #400954)

Seems Vec Uses: contain duplicate input for the same vector?

Vec Uses: V3(VSR35)V3(VSR35)

[lei]

Not a silly question at all!
Initially I thought that I didn't need to update the tests because I wan't changing code and the CHECK/CHECK-NEXT lines don't really care that there are comments that come after the instructions. This is true in most cases but there are tests that already have a comment after the instruction line (for example # 8-byte Folded Spill) and in those cases by adding a second comment I'm adding a new line and the CHECK-NEXT lines don't work anymore. Anyway, I'm going to update those tests now.

Is it possible to append to the comment line instead of adding a new comment line below it? Not a huge deal but thought maybe it would look cleaner to have all comments on the same line. Or at least indented to indicate it's part of the previous line?

[stefanp]

I have not had time to do this and the priority of this work is very low so I don't see myself getting back to it.
As a result, I'm going to abandon this patch.

llvm/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt

 add_llvm_component_library(LLVMPowerPCDesc
   PPCAsmBackend.cpp
   PPCInstPrinter.cpp
+  PPCInstComments.cpp
   PPCMCTargetDesc.cpp
   PPCMCAsmInfo.cpp
   PPCMCCodeEmitter.cpp
   PPCMCExpr.cpp
   PPCPredicates.cpp
   PPCELFObjectWriter.cpp
   PPCXCOFFObjectWriter.cpp
   PPCELFStreamer.cpp

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstComments.h

+//=- PPCInstComments.h - Generate verbose-asm comments for instrs -*- C++ -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This defines functionality used to emit comments about PPC instructions to
+// an output stream for -fverbose-asm.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCINSTCOMMENTS_H
+#define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCINSTCOMMENTS_H
+
+namespace llvm {
+
+class MCInst;
+class MCInstrInfo;
+class raw_ostream;
+bool EmitAnyPPCInstComments(const MCInst *MI, raw_ostream &OS,
+                            const MCInstrInfo &MCII);
+} // namespace llvm
+
+#endif

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstComments.cpp

+//===-- PPCInstComments.cpp - Generate verbose-asm comments for instrs ----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This defines functionality used to emit comments about PPC instructions to
+// an output stream for -fverbose-asm.
+//
+//===----------------------------------------------------------------------===//
+
+#include "PPCInstComments.h"
+#include "PPCInstrInfo.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+// hasVectorRegs return a pair of booleans if MI uses or defines any regiers
+// that overlap with the vector registers.
+static std::pair<bool, bool> hasVectorRegs(const MCInst *MI, unsigned NumDefs) {
+  std::pair<bool, bool> HasVecUseOrDef{false, false};
+  for (unsigned OpNumber = 0; OpNumber < MI->size(); ++OpNumber) {
+    const MCOperand &Operand = MI->getOperand(OpNumber);
+    if (!Operand.isReg())
+      continue;
+
+    unsigned RegNumber = Operand.getReg();
+    if ((RegNumber >= PPC::F0 && RegNumber <= PPC::F31) ||
+        (RegNumber >= PPC::VF0 && RegNumber <= PPC::VF31) ||
+        (RegNumber >= PPC::V0 && RegNumber <= PPC::V31) ||
+        (RegNumber >= PPC::VSL0 && RegNumber <= PPC::VSL31) ||
+        (RegNumber >= PPC::VSX32 && RegNumber <= PPC::VSX63) ||
+        (RegNumber >= PPC::VSRp0 && RegNumber <= PPC::VSRp31) ||
+        (RegNumber >= PPC::ACC0 && RegNumber <= PPC::ACC7) ||
+        (RegNumber >= PPC::UACC0 && RegNumber <= PPC::UACC7)) {
+      // second is true if this is a def.
+      if (OpNumber < NumDefs)
+        HasVecUseOrDef.second = true;
+      else
+        HasVecUseOrDef.first = true;
+    }
+  }
+  return HasVecUseOrDef;
+}
+
+// Print the full register name along with the VSR register(s) it overlaps.
+// Returns true if something was printed to the stream.
+static bool printFullReg(unsigned RegNumber, raw_ostream &OS) {
+  if (RegNumber >= PPC::F0 && RegNumber <= PPC::F31) {
+    OS << "F" << RegNumber - PPC::F0 << "(VSR" << RegNumber - PPC::F0 << ")";
+    return true;
+  }
+
+  if (RegNumber >= PPC::VF0 && RegNumber <= PPC::VF31) {
+    OS << "VF" << RegNumber - PPC::VF0 << "(VSR" << RegNumber - PPC::VF0 << ")";
+    return true;
+  }
+
+  if (RegNumber >= PPC::V0 && RegNumber <= PPC::V31) {
+    OS << "V" << RegNumber - PPC::V0 << "(VSR" << RegNumber - PPC::V0 + 32
+       << ")";
+    return true;
+  }
+
+  if (RegNumber >= PPC::VSL0 && RegNumber <= PPC::VSL31) {
+    OS << "VSL" << RegNumber - PPC::VSL0 << "(VSR" << RegNumber - PPC::VSL0
+       << ")";
+    return true;
+  }
+
+  if (RegNumber >= PPC::VSX32 && RegNumber <= PPC::VSX63) {
+    OS << "VSX" << RegNumber - PPC::VSX32 + 32 << "(VSR"
+       << RegNumber - PPC::VSX32 + 32 << ")";
+    return true;
+  }
+
+  if (RegNumber >= PPC::VSRp0 && RegNumber <= PPC::VSRp31) {
+    OS << "VSRp" << RegNumber - PPC::VSRp0 << "(VSR"
+       << (RegNumber - PPC::VSRp0) * 2 << ","
+       << "VSR" << (RegNumber - PPC::VSRp0) * 2 + 1 << ")";
+    return true;
+  }
+
+  if (RegNumber >= PPC::ACC0 && RegNumber <= PPC::ACC7) {
+    OS << "ACC" << RegNumber - PPC::ACC0 << "(VSR"
+       << (RegNumber - PPC::ACC0) * 4 << ","
+       << "VSR" << (RegNumber - PPC::ACC0) * 4 + 1 << ","
+       << "VSR" << (RegNumber - PPC::ACC0) * 4 + 2 << ","
+       << "VSR" << (RegNumber - PPC::ACC0) * 4 + 3 << ")";
+    return true;
+  }
+
+  if (RegNumber >= PPC::UACC0 && RegNumber <= PPC::UACC7) {
+    OS << "UACC" << RegNumber - PPC::UACC0 << "(VSR"
+       << (RegNumber - PPC::UACC0) * 4 << ","
+       << "VSR" << (RegNumber - PPC::UACC0) * 4 + 1 << ","
+       << "VSR" << (RegNumber - PPC::UACC0) * 4 + 2 << ","
+       << "VSR" << (RegNumber - PPC::UACC0) * 4 + 3 << ")";
+    return true;
+  }
+  return false;
+}
+
+/// EmitAnyPPCInstComments - This function decodes PowerPC instructions and
+/// prints newline terminated strings to the specified string if desired. This
+/// information is shown in disassembly dumps when verbose assembly is enabled.
+/// Returns true if comments were added and false otherwise.
+bool llvm::EmitAnyPPCInstComments(const MCInst *MI, raw_ostream &OS,
+                                  const MCInstrInfo &MCII) {
+  bool HaveComment = false;
+  // If there are no operands exit early.
+  if (MI->size() == 0)
+    return false;
+
+  const MCInstrDesc &MCDesc = MCII.get(MI->getOpcode());
+  unsigned NumDefs = MCDesc.getNumDefs();
+
+  std::pair<bool, bool> HasVecUseOrDef = hasVectorRegs(MI, NumDefs);
+
+  // If the intruction has no vector regsiters we don't really care.
+  if (!HasVecUseOrDef.first && !HasVecUseOrDef.second)
+    return false;
+
+  unsigned OpNumber = 0;
+  // Print out vector defs if any exist.
+  if (HasVecUseOrDef.second) {
+    OS << "Vec Defs: ";
+    for (OpNumber = 0; OpNumber < NumDefs; ++OpNumber) {
+      const MCOperand &Operand = MI->getOperand(OpNumber);
+      if (!Operand.isReg())
+        continue;
+      HaveComment = printFullReg(Operand.getReg(), OS);
+    }
+    // If vector uses exist add a tab to separate the uses and defs.
+    if (HasVecUseOrDef.first)
+      OS << "\t";
+  }
+
+  // Print out vector uses if any exist.
+  if (HasVecUseOrDef.first) {
+    OS << "Vec Uses: ";
+    for (OpNumber = NumDefs; OpNumber < MI->size(); ++OpNumber) {
+      const MCOperand &Operand = MI->getOperand(OpNumber);
+      if (!Operand.isReg())
+        continue;
+      HaveComment = printFullReg(Operand.getReg(), OS);
+    }
+  }
+  OS << "\n";
+
+  return HaveComment;
+}

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This class prints an PPC MCInst to a .s file.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/PPCInstPrinter.h"
+#include "MCTargetDesc/PPCInstComments.h"
 #include "MCTargetDesc/PPCMCTargetDesc.h"
 #include "MCTargetDesc/PPCPredicates.h"
 #include "PPCInstrInfo.h"
 #include "llvm/CodeGen/TargetOpcodes.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"

 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
   const char *RegName = getRegisterName(RegNo);
   OS << RegName;
 }
 
 void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
                                StringRef Annot, const MCSubtargetInfo &STI,
                                raw_ostream &O) {
+  // Print comments if verbose assembly is enabled.
+  if (CommentStream)
+    EmitAnyPPCInstComments(MI, (*CommentStream), MII);
+
   // Customize printing of the addis instruction on AIX. When an operand is a
   // symbol reference, the instruction syntax is changed to look like a load
   // operation, i.e:
   //     Transform:  addis $rD, $rA, $src --> addis $rD, $src($rA).
   if (TT.isOSAIX() &&
       (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
       MI->getOperand(2).isExpr()) {
     assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&

llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll

 ; This test also checks that the paired vector intrinsics are available even
 ; when MMA is disabled.
 
 ; assemble_pair
 declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
 define void @ass_pair(<256 x i1>* %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: ass_pair:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmr v3, v2
-; CHECK-NEXT:    stxv v2, 16(r3)
-; CHECK-NEXT:    stxv v3, 0(r3)
+; CHECK-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    stxv v2, 16(r3) # Vec Uses: V2(VSR34)
+; CHECK-NEXT:    stxv v3, 0(r3) # Vec Uses: V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: ass_pair:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    vmr v3, v2
-; CHECK-NOMMA-NEXT:    stxv v2, 16(r3)
-; CHECK-NOMMA-NEXT:    stxv v3, 0(r3)
+; CHECK-NOMMA-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NOMMA-NEXT:    stxv v2, 16(r3) # Vec Uses: V2(VSR34)
+; CHECK-NOMMA-NEXT:    stxv v3, 0(r3) # Vec Uses: V3(VSR35)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: ass_pair:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vmr v3, v2
-; CHECK-BE-NEXT:    stxv v2, 16(r3)
-; CHECK-BE-NEXT:    stxv v2, 0(r3)
+; CHECK-BE-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-NEXT:    stxv v2, 16(r3) # Vec Uses: V2(VSR34)
+; CHECK-BE-NEXT:    stxv v2, 0(r3) # Vec Uses: V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: ass_pair:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    vmr v3, v2
-; CHECK-BE-NOMMA-NEXT:    stxv v2, 16(r3)
-; CHECK-BE-NOMMA-NEXT:    stxv v2, 0(r3)
+; CHECK-BE-NOMMA-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-NOMMA-NEXT:    stxv v2, 16(r3) # Vec Uses: V2(VSR34)
+; CHECK-BE-NOMMA-NEXT:    stxv v2, 0(r3) # Vec Uses: V2(VSR34)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc, <16 x i8> %vc)
   store <256 x i1> %0, <256 x i1>* %ptr, align 32
   ret void
 }
 
 ; disassemble_pair
 declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)
 define void @disass_pair(<256 x i1>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3) {
 ; CHECK-LABEL: disass_pair:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv v3, 0(r3)
-; CHECK-NEXT:    lxv v2, 16(r3)
-; CHECK-NEXT:    stxv v3, 0(r4)
-; CHECK-NEXT:    stxv v2, 0(r5)
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    lxv v2, 16(r3) # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    stxv v3, 0(r4) # Vec Uses: V3(VSR35)
+; CHECK-NEXT:    stxv v2, 0(r5) # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: disass_pair:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    lxv v3, 0(r3)
-; CHECK-NOMMA-NEXT:    lxv v2, 16(r3)
-; CHECK-NOMMA-NEXT:    stxv v3, 0(r4)
-; CHECK-NOMMA-NEXT:    stxv v2, 0(r5)
+; CHECK-NOMMA-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
+; CHECK-NOMMA-NEXT:    lxv v2, 16(r3) # Vec Defs: V2(VSR34)
+; CHECK-NOMMA-NEXT:    stxv v3, 0(r4) # Vec Uses: V3(VSR35)
+; CHECK-NOMMA-NEXT:    stxv v2, 0(r5) # Vec Uses: V2(VSR34)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: disass_pair:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv v3, 16(r3)
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    stxv v2, 0(r4)
-; CHECK-BE-NEXT:    stxv v3, 0(r5)
+; CHECK-BE-NEXT:    lxv v3, 16(r3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
+; CHECK-BE-NEXT:    stxv v2, 0(r4) # Vec Uses: V2(VSR34)
+; CHECK-BE-NEXT:    stxv v3, 0(r5) # Vec Uses: V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: disass_pair:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    lxv v3, 16(r3)
-; CHECK-BE-NOMMA-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NOMMA-NEXT:    stxv v2, 0(r4)
-; CHECK-BE-NOMMA-NEXT:    stxv v3, 0(r5)
+; CHECK-BE-NOMMA-NEXT:    lxv v3, 16(r3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NOMMA-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
+; CHECK-BE-NOMMA-NEXT:    stxv v2, 0(r4) # Vec Uses: V2(VSR34)
+; CHECK-BE-NOMMA-NEXT:    stxv v3, 0(r5) # Vec Uses: V3(VSR35)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = load <256 x i1>, <256 x i1>* %ptr1, align 32
   %1 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> %0)
   %2 = extractvalue { <16 x i8>, <16 x i8> } %1, 0
   %3 = extractvalue { <16 x i8>, <16 x i8> } %1, 1
   store <16 x i8> %2, <16 x i8>* %ptr2, align 16
   store <16 x i8> %3, <16 x i8>* %ptr3, align 16
   ret void
 }
 
 define void @test_ldst_1(<256 x i1>* %vpp, <256 x i1>* %vp2) {
 ; CHECK-LABEL: test_ldst_1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxvp vsp34, 0(r3)
-; CHECK-NEXT:    stxvp vsp34, 0(r4)
+; CHECK-NEXT:    lxvp vsp34, 0(r3) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    stxvp vsp34, 0(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_1:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    lxvp vsp34, 0(r3)
-; CHECK-NOMMA-NEXT:    stxvp vsp34, 0(r4)
+; CHECK-NOMMA-NEXT:    lxvp vsp34, 0(r3) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NOMMA-NEXT:    stxvp vsp34, 0(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_1:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxvp vsp34, 0(r3)
-; CHECK-BE-NEXT:    stxvp vsp34, 0(r4)
+; CHECK-BE-NEXT:    lxvp vsp34, 0(r3) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NEXT:    stxvp vsp34, 0(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_1:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    lxvp vsp34, 0(r3)
-; CHECK-BE-NOMMA-NEXT:    stxvp vsp34, 0(r4)
+; CHECK-BE-NOMMA-NEXT:    lxvp vsp34, 0(r3) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NOMMA-NEXT:    stxvp vsp34, 0(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %0)
   %2 = bitcast <256 x i1>* %vp2 to i8*
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, i8* %2)
   ret void
 }
 
 declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*)
 declare void @llvm.ppc.vsx.stxvp(<256 x i1>, i8*)
 
 define void @test_ldst_2(<256 x i1>* %vpp, i64 %offset, <256 x i1>* %vp2)  {
 ; CHECK-LABEL: test_ldst_2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxvpx vsp34, r3, r4
-; CHECK-NEXT:    stxvpx vsp34, r5, r4
+; CHECK-NEXT:    lxvpx vsp34, r3, r4 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    stxvpx vsp34, r5, r4 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_2:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    lxvpx vsp34, r3, r4
-; CHECK-NOMMA-NEXT:    stxvpx vsp34, r5, r4
+; CHECK-NOMMA-NEXT:    lxvpx vsp34, r3, r4 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NOMMA-NEXT:    stxvpx vsp34, r5, r4 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_2:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxvpx vsp34, r3, r4
-; CHECK-BE-NEXT:    stxvpx vsp34, r5, r4
+; CHECK-BE-NEXT:    lxvpx vsp34, r3, r4 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NEXT:    stxvpx vsp34, r5, r4 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_2:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    lxvpx vsp34, r3, r4
-; CHECK-BE-NOMMA-NEXT:    stxvpx vsp34, r5, r4
+; CHECK-BE-NOMMA-NEXT:    lxvpx vsp34, r3, r4 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NOMMA-NEXT:    stxvpx vsp34, r5, r4 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = getelementptr i8, i8* %0, i64 %offset
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = bitcast <256 x i1>* %vp2 to i8*
   %4 = getelementptr i8, i8* %3, i64 %offset
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }
 
 define void @test_ldst_3(<256 x i1>* %vpp, <256 x i1>* %vp2)  {
 ; CHECK-LABEL: test_ldst_3:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxvp vsp34, 18(r3), 0
-; CHECK-NEXT:    pstxvp vsp34, 18(r4), 0
+; CHECK-NEXT:    plxvp vsp34, 18(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    pstxvp vsp34, 18(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_3:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    plxvp vsp34, 18(r3), 0
-; CHECK-NOMMA-NEXT:    pstxvp vsp34, 18(r4), 0
+; CHECK-NOMMA-NEXT:    plxvp vsp34, 18(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NOMMA-NEXT:    pstxvp vsp34, 18(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_3:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    plxvp vsp34, 18(r3), 0
-; CHECK-BE-NEXT:    pstxvp vsp34, 18(r4), 0
+; CHECK-BE-NEXT:    plxvp vsp34, 18(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NEXT:    pstxvp vsp34, 18(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_3:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 18(r3), 0
-; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 18(r4), 0
+; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 18(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 18(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = getelementptr i8, i8* %0, i64 18
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = bitcast <256 x i1>* %vp2 to i8*
   %4 = getelementptr i8, i8* %3, i64 18
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }
 
 define void @test_ldst_4(<256 x i1>* %vpp, <256 x i1>* %vp2)  {
 ; CHECK-LABEL: test_ldst_4:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxvp vsp34, 1(r3), 0
-; CHECK-NEXT:    pstxvp vsp34, 1(r4), 0
+; CHECK-NEXT:    plxvp vsp34, 1(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    pstxvp vsp34, 1(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_4:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    plxvp vsp34, 1(r3), 0
-; CHECK-NOMMA-NEXT:    pstxvp vsp34, 1(r4), 0
+; CHECK-NOMMA-NEXT:    plxvp vsp34, 1(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NOMMA-NEXT:    pstxvp vsp34, 1(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_4:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    plxvp vsp34, 1(r3), 0
-; CHECK-BE-NEXT:    pstxvp vsp34, 1(r4), 0
+; CHECK-BE-NEXT:    plxvp vsp34, 1(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NEXT:    pstxvp vsp34, 1(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_4:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 1(r3), 0
-; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 1(r4), 0
+; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 1(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 1(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = getelementptr i8, i8* %0, i64 1
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = bitcast <256 x i1>* %vp2 to i8*
   %4 = getelementptr i8, i8* %3, i64 1
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }
 
 define void @test_ldst_5(<256 x i1>* %vpp, <256 x i1>* %vp2)  {
 ; CHECK-LABEL: test_ldst_5:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxvp vsp34, 42(r3), 0
-; CHECK-NEXT:    pstxvp vsp34, 42(r4), 0
+; CHECK-NEXT:    plxvp vsp34, 42(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    pstxvp vsp34, 42(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_5:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    plxvp vsp34, 42(r3), 0
-; CHECK-NOMMA-NEXT:    pstxvp vsp34, 42(r4), 0
+; CHECK-NOMMA-NEXT:    plxvp vsp34, 42(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NOMMA-NEXT:    pstxvp vsp34, 42(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_5:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    plxvp vsp34, 42(r3), 0
-; CHECK-BE-NEXT:    pstxvp vsp34, 42(r4), 0
+; CHECK-BE-NEXT:    plxvp vsp34, 42(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NEXT:    pstxvp vsp34, 42(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_5:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 42(r3), 0
-; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 42(r4), 0
+; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 42(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 42(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = getelementptr i8, i8* %0, i64 42
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = bitcast <256 x i1>* %vp2 to i8*
   %4 = getelementptr i8, i8* %3, i64 42
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }
 
 define void @test_ldst_6(<256 x i1>* %vpp, <256 x i1>* %vp2)  {
 ; CHECK-LABEL: test_ldst_6:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxvp vsp34, 4096(r3)
-; CHECK-NEXT:    stxvp vsp34, 4096(r4)
+; CHECK-NEXT:    lxvp vsp34, 4096(r3) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    stxvp vsp34, 4096(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_6:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    lxvp vsp34, 4096(r3)
-; CHECK-NOMMA-NEXT:    stxvp vsp34, 4096(r4)
+; CHECK-NOMMA-NEXT:    lxvp vsp34, 4096(r3) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NOMMA-NEXT:    stxvp vsp34, 4096(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_6:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxvp vsp34, 4096(r3)
-; CHECK-BE-NEXT:    stxvp vsp34, 4096(r4)
+; CHECK-BE-NEXT:    lxvp vsp34, 4096(r3) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NEXT:    stxvp vsp34, 4096(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_6:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    lxvp vsp34, 4096(r3)
-; CHECK-BE-NOMMA-NEXT:    stxvp vsp34, 4096(r4)
+; CHECK-BE-NOMMA-NEXT:    lxvp vsp34, 4096(r3) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NOMMA-NEXT:    stxvp vsp34, 4096(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = getelementptr <256 x i1>, <256 x i1>* %vpp, i64 128
   %1 = bitcast <256 x i1>* %0 to i8*
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = getelementptr <256 x i1>, <256 x i1>* %vp2, i64 128
   %4 = bitcast <256 x i1>* %3 to i8*
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }
 
 define void @test_ldst_7(<256 x i1>* %vpp, <256 x i1>* %vp2)  {
 ; FIXME: A prefixed load (plxvp) is expected here as the offset in this
 ; test case is a constant that fits within 34-bits.
 ; CHECK-LABEL: test_ldst_7:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxvp vsp34, 32799(r3), 0
-; CHECK-NEXT:    pstxvp vsp34, 32799(r4), 0
+; CHECK-NEXT:    plxvp vsp34, 32799(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    pstxvp vsp34, 32799(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_7:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    plxvp vsp34, 32799(r3), 0
-; CHECK-NOMMA-NEXT:    pstxvp vsp34, 32799(r4), 0
+; CHECK-NOMMA-NEXT:    plxvp vsp34, 32799(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NOMMA-NEXT:    pstxvp vsp34, 32799(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_7:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    plxvp vsp34, 32799(r3), 0
-; CHECK-BE-NEXT:    pstxvp vsp34, 32799(r4), 0
+; CHECK-BE-NEXT:    plxvp vsp34, 32799(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NEXT:    pstxvp vsp34, 32799(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_7:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 32799(r3), 0
-; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 32799(r4), 0
+; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 32799(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 32799(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = getelementptr i8, i8* %0, i64 32799
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = bitcast <256 x i1>* %vp2 to i8*
   %4 = getelementptr i8, i8* %3, i64 32799
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }

llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
 ; RUN:    | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:     -ppc-track-subreg-liveness < %s | FileCheck %s --check-prefix=TRACKLIVE
 
 %0 = type <{ double }>
 %1 = type <{ double }>
 
 define void @acc_regalloc(i32* %arg, [0 x %0]* %arg1, [0 x %1]* %arg2) local_unnamed_addr {
 ; CHECK-LABEL: acc_regalloc:
 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    lxv v4, 0(0)
-; CHECK-NEXT:    xxlxor v0, v0, v0
-; CHECK-NEXT:    xxlxor v1, v1, v1
-; CHECK-NEXT:    xxlxor v2, v2, v2
+; CHECK-NEXT:    lxv v4, 0(0) # Vec Defs: V4(VSR36)
+; CHECK-NEXT:    xxlxor v0, v0, v0 # Vec Defs: V0(VSR32)
+; CHECK-NEXT:    xxlxor v1, v1, v1 # Vec Defs: V1(VSR33)
+; CHECK-NEXT:    xxlxor v2, v2, v2 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    li r6, 1
 ; CHECK-NEXT:    li r4, 16
 ; CHECK-NEXT:    stfd f14, -144(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F14(VSR14)
 ; CHECK-NEXT:    stfd f15, -136(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F15(VSR15)
 ; CHECK-NEXT:    extswsli r3, r3, 3
-; CHECK-NEXT:    xvmaddadp v1, v4, v1
-; CHECK-NEXT:    lxvdsx v5, 0, r3
-; CHECK-NEXT:    xvmaddadp v0, v5, v0
+; CHECK-NEXT:    xvmaddadp v1, v4, v1 # Vec Defs: V1(VSR33) Vec Uses: V1(VSR33)V4(VSR36)V1(VSR33)
+; CHECK-NEXT:    lxvdsx v5, 0, r3 # Vec Defs: V5(VSR37)
+; CHECK-NEXT:    xvmaddadp v0, v5, v0 # Vec Defs: V0(VSR32) Vec Uses: V0(VSR32)V5(VSR37)V0(VSR32)
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_1: # %bb9
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    addi r6, r6, 2
-; CHECK-NEXT:    lxv vs0, 16(0)
-; CHECK-NEXT:    lxv vs1, -64(r5)
-; CHECK-NEXT:    xxlxor v7, v7, v7
-; CHECK-NEXT:    vmr v9, v0
-; CHECK-NEXT:    xxlxor v10, v10, v10
+; CHECK-NEXT:    lxv vs0, 16(0) # Vec Defs: VSL0(VSR0)
+; CHECK-NEXT:    lxv vs1, -64(r5) # Vec Defs: VSL1(VSR1)
+; CHECK-NEXT:    xxlxor v7, v7, v7 # Vec Defs: V7(VSR39)
+; CHECK-NEXT:    vmr v9, v0 # Vec Defs: V9(VSR41) Vec Uses: V0(VSR32)V0(VSR32)
+; CHECK-NEXT:    xxlxor v10, v10, v10 # Vec Defs: V10(VSR42)
 ; CHECK-NEXT:    mulld r6, r6, r3
-; CHECK-NEXT:    xvmaddadp v7, vs0, v5
-; CHECK-NEXT:    xvmuldp v6, vs0, v2
-; CHECK-NEXT:    lxv vs0, -16(r5)
-; CHECK-NEXT:    xvmaddadp v9, vs1, v2
-; CHECK-NEXT:    xxlxor v8, v8, v8
-; CHECK-NEXT:    xvmaddadp v7, v2, v2
-; CHECK-NEXT:    xvmaddadp v6, v2, v2
-; CHECK-NEXT:    lxvdsx v14, r6, r4
+; CHECK-NEXT:    xvmaddadp v7, vs0, v5 # Vec Defs: V7(VSR39) Vec Uses: V7(VSR39)VSL0(VSR0)V5(VSR37)
+; CHECK-NEXT:    xvmuldp v6, vs0, v2 # Vec Defs: V6(VSR38) Vec Uses: VSL0(VSR0)V2(VSR34)
+; CHECK-NEXT:    lxv vs0, -16(r5) # Vec Defs: VSL0(VSR0)
+; CHECK-NEXT:    xvmaddadp v9, vs1, v2 # Vec Defs: V9(VSR41) Vec Uses: V9(VSR41)VSL1(VSR1)V2(VSR34)
+; CHECK-NEXT:    xxlxor v8, v8, v8 # Vec Defs: V8(VSR40)
+; CHECK-NEXT:    xvmaddadp v7, v2, v2 # Vec Defs: V7(VSR39) Vec Uses: V7(VSR39)V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    xvmaddadp v6, v2, v2 # Vec Defs: V6(VSR38) Vec Uses: V6(VSR38)V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    lxvdsx v14, r6, r4 # Vec Defs: V14(VSR46)
 ; CHECK-NEXT:    li r6, 0
-; CHECK-NEXT:    xvmaddadp v8, vs1, v8
-; CHECK-NEXT:    xvmaddadp v10, vs0, v10
-; CHECK-NEXT:    xvmuldp v3, vs1, v14
-; CHECK-NEXT:    xvmuldp v11, vs0, v14
-; CHECK-NEXT:    xvmuldp vs5, v14, v2
-; CHECK-NEXT:    xvmuldp v13, v4, v14
-; CHECK-NEXT:    xxlor vs0, v2, v2
-; CHECK-NEXT:    vmr v12, v2
-; CHECK-NEXT:    xxlor vs14, v10, v10
-; CHECK-NEXT:    xxlor vs4, v2, v2
+; CHECK-NEXT:    xvmaddadp v8, vs1, v8 # Vec Defs: V8(VSR40) Vec Uses: V8(VSR40)VSL1(VSR1)V8(VSR40)
+; CHECK-NEXT:    xvmaddadp v10, vs0, v10 # Vec Defs: V10(VSR42) Vec Uses: V10(VSR42)VSL0(VSR0)V10(VSR42)
+; CHECK-NEXT:    xvmuldp v3, vs1, v14 # Vec Defs: V3(VSR35) Vec Uses: VSL1(VSR1)V14(VSR46)
+; CHECK-NEXT:    xvmuldp v11, vs0, v14 # Vec Defs: V11(VSR43) Vec Uses: VSL0(VSR0)V14(VSR46)
+; CHECK-NEXT:    xvmuldp vs5, v14, v2 # Vec Defs: VSL5(VSR5) Vec Uses: V14(VSR46)V2(VSR34)
+; CHECK-NEXT:    xvmuldp v13, v4, v14 # Vec Defs: V13(VSR45) Vec Uses: V4(VSR36)V14(VSR46)
+; CHECK-NEXT:    xxlor vs0, v2, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    vmr v12, v2 # Vec Defs: V12(VSR44) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    xxlor vs14, v10, v10 # Vec Defs: VSL14(VSR14) Vec Uses: V10(VSR42)V10(VSR42)
+; CHECK-NEXT:    xxlor vs4, v2, v2 # Vec Defs: VSL4(VSR4) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    # kill: def $vsrp2 killed $vsrp2 def $uacc1
-; CHECK-NEXT:    xxlor vs6, v6, v6
-; CHECK-NEXT:    xxlor vs7, v7, v7
-; CHECK-NEXT:    xxlor vs8, v12, v12
-; CHECK-NEXT:    xxlor vs9, v13, v13
-; CHECK-NEXT:    vmr v12, v1
-; CHECK-NEXT:    xxlor vs1, v3, v3
-; CHECK-NEXT:    xxlor vs2, v8, v8
-; CHECK-NEXT:    xxlor vs3, v9, v9
-; CHECK-NEXT:    xxlor vs15, v11, v11
-; CHECK-NEXT:    vmr v10, v2
-; CHECK-NEXT:    xxlor vs10, v12, v12
-; CHECK-NEXT:    xxlor vs11, v13, v13
-; CHECK-NEXT:    xxmtacc acc1
-; CHECK-NEXT:    xxlor vs12, v10, v10
-; CHECK-NEXT:    xxlor vs13, v11, v11
-; CHECK-NEXT:    xxmtacc acc0
-; CHECK-NEXT:    xxmtacc acc2
-; CHECK-NEXT:    xxmtacc acc3
-; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; CHECK-NEXT:    xxmfacc acc0
-; CHECK-NEXT:    xxmfacc acc1
-; CHECK-NEXT:    xxmfacc acc2
-; CHECK-NEXT:    xxmfacc acc3
-; CHECK-NEXT:    stxv vs1, 0(r3)
-; CHECK-NEXT:    stxv vs9, 32(r3)
-; CHECK-NEXT:    stxv vs4, 16(0)
-; CHECK-NEXT:    stxv vs12, 48(0)
+; CHECK-NEXT:    xxlor vs6, v6, v6 # Vec Defs: VSL6(VSR6) Vec Uses: V6(VSR38)V6(VSR38)
+; CHECK-NEXT:    xxlor vs7, v7, v7 # Vec Defs: VSL7(VSR7) Vec Uses: V7(VSR39)V7(VSR39)
+; CHECK-NEXT:    xxlor vs8, v12, v12 # Vec Defs: VSL8(VSR8) Vec Uses: V12(VSR44)V12(VSR44)
+; CHECK-NEXT:    xxlor vs9, v13, v13 # Vec Defs: VSL9(VSR9) Vec Uses: V13(VSR45)V13(VSR45)
+; CHECK-NEXT:    vmr v12, v1 # Vec Defs: V12(VSR44) Vec Uses: V1(VSR33)V1(VSR33)
+; CHECK-NEXT:    xxlor vs1, v3, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    xxlor vs2, v8, v8 # Vec Defs: VSL2(VSR2) Vec Uses: V8(VSR40)V8(VSR40)
+; CHECK-NEXT:    xxlor vs3, v9, v9 # Vec Defs: VSL3(VSR3) Vec Uses: V9(VSR41)V9(VSR41)
+; CHECK-NEXT:    xxlor vs15, v11, v11 # Vec Defs: VSL15(VSR15) Vec Uses: V11(VSR43)V11(VSR43)
+; CHECK-NEXT:    vmr v10, v2 # Vec Defs: V10(VSR42) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    xxlor vs10, v12, v12 # Vec Defs: VSL10(VSR10) Vec Uses: V12(VSR44)V12(VSR44)
+; CHECK-NEXT:    xxlor vs11, v13, v13 # Vec Defs: VSL11(VSR11) Vec Uses: V13(VSR45)V13(VSR45)
+; CHECK-NEXT:    xxmtacc acc1 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)
+; CHECK-NEXT:    xxlor vs12, v10, v10 # Vec Defs: VSL12(VSR12) Vec Uses: V10(VSR42)V10(VSR42)
+; CHECK-NEXT:    xxlor vs13, v11, v11 # Vec Defs: VSL13(VSR13) Vec Uses: V11(VSR43)V11(VSR43)
+; CHECK-NEXT:    xxmtacc acc0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)
+; CHECK-NEXT:    xxmtacc acc2 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)
+; CHECK-NEXT:    xxmtacc acc3 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xxmfacc acc0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)
+; CHECK-NEXT:    xxmfacc acc1 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)
+; CHECK-NEXT:    xxmfacc acc2 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)
+; CHECK-NEXT:    xxmfacc acc3 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)
+; CHECK-NEXT:    stxv vs1, 0(r3) # Vec Uses: VSL1(VSR1)
+; CHECK-NEXT:    stxv vs9, 32(r3) # Vec Uses: VSL9(VSR9)
+; CHECK-NEXT:    stxv vs4, 16(0) # Vec Uses: VSL4(VSR4)
+; CHECK-NEXT:    stxv vs12, 48(0) # Vec Uses: VSL12(VSR12)
 ; CHECK-NEXT:    b .LBB0_1
 ;
 ; TRACKLIVE-LABEL: acc_regalloc:
 ; TRACKLIVE:       # %bb.0: # %bb
 ; TRACKLIVE-NEXT:    lwz r3, 0(r3)
-; TRACKLIVE-NEXT:    lxv v4, 0(0)
-; TRACKLIVE-NEXT:    xxlxor v0, v0, v0
-; TRACKLIVE-NEXT:    xxlxor v1, v1, v1
-; TRACKLIVE-NEXT:    xxlxor v2, v2, v2
+; TRACKLIVE-NEXT:    lxv v4, 0(0) # Vec Defs: V4(VSR36)
+; TRACKLIVE-NEXT:    xxlxor v0, v0, v0 # Vec Defs: V0(VSR32)
+; TRACKLIVE-NEXT:    xxlxor v1, v1, v1 # Vec Defs: V1(VSR33)
+; TRACKLIVE-NEXT:    xxlxor v2, v2, v2 # Vec Defs: V2(VSR34)
 ; TRACKLIVE-NEXT:    li r6, 1
 ; TRACKLIVE-NEXT:    li r4, 16
 ; TRACKLIVE-NEXT:    stfd f14, -144(r1) # 8-byte Folded Spill
+; TRACKLIVE-NEXT:    # Vec Uses: F14(VSR14)
 ; TRACKLIVE-NEXT:    stfd f15, -136(r1) # 8-byte Folded Spill
+; TRACKLIVE-NEXT:    # Vec Uses: F15(VSR15)
 ; TRACKLIVE-NEXT:    extswsli r3, r3, 3
-; TRACKLIVE-NEXT:    xvmaddadp v1, v4, v1
-; TRACKLIVE-NEXT:    lxvdsx v5, 0, r3
-; TRACKLIVE-NEXT:    xvmaddadp v0, v5, v0
+; TRACKLIVE-NEXT:    xvmaddadp v1, v4, v1 # Vec Defs: V1(VSR33) Vec Uses: V1(VSR33)V4(VSR36)V1(VSR33)
+; TRACKLIVE-NEXT:    lxvdsx v5, 0, r3 # Vec Defs: V5(VSR37)
+; TRACKLIVE-NEXT:    xvmaddadp v0, v5, v0 # Vec Defs: V0(VSR32) Vec Uses: V0(VSR32)V5(VSR37)V0(VSR32)
 ; TRACKLIVE-NEXT:    .p2align 4
 ; TRACKLIVE-NEXT:  .LBB0_1: # %bb9
 ; TRACKLIVE-NEXT:    #
 ; TRACKLIVE-NEXT:    addi r6, r6, 2
-; TRACKLIVE-NEXT:    lxv vs0, 16(0)
-; TRACKLIVE-NEXT:    lxv vs1, -64(r5)
-; TRACKLIVE-NEXT:    xxlxor vs7, vs7, vs7
-; TRACKLIVE-NEXT:    xxlor vs3, v0, v0
-; TRACKLIVE-NEXT:    xxlxor vs2, vs2, vs2
-; TRACKLIVE-NEXT:    xxlxor vs12, vs12, vs12
+; TRACKLIVE-NEXT:    lxv vs0, 16(0) # Vec Defs: VSL0(VSR0)
+; TRACKLIVE-NEXT:    lxv vs1, -64(r5) # Vec Defs: VSL1(VSR1)
+; TRACKLIVE-NEXT:    xxlxor vs7, vs7, vs7 # Vec Defs: VSL7(VSR7)
+; TRACKLIVE-NEXT:    xxlor vs3, v0, v0 # Vec Defs: VSL3(VSR3) Vec Uses: V0(VSR32)V0(VSR32)
+; TRACKLIVE-NEXT:    xxlxor vs2, vs2, vs2 # Vec Defs: VSL2(VSR2)
+; TRACKLIVE-NEXT:    xxlxor vs12, vs12, vs12 # Vec Defs: VSL12(VSR12)
 ; TRACKLIVE-NEXT:    mulld r6, r6, r3
-; TRACKLIVE-NEXT:    xxlor vs10, v2, v2
-; TRACKLIVE-NEXT:    xxlor vs4, v2, v2
-; TRACKLIVE-NEXT:    xxlor vs8, vs10, vs10
-; TRACKLIVE-NEXT:    xxlor vs10, v1, v1
-; TRACKLIVE-NEXT:    xvmaddadp vs7, vs0, v5
-; TRACKLIVE-NEXT:    xvmuldp vs6, vs0, v2
-; TRACKLIVE-NEXT:    lxv vs0, -16(r5)
-; TRACKLIVE-NEXT:    xvmaddadp vs3, vs1, v2
-; TRACKLIVE-NEXT:    xvmaddadp vs2, vs1, vs2
-; TRACKLIVE-NEXT:    lxvdsx v6, r6, r4
+; TRACKLIVE-NEXT:    xxlor vs10, v2, v2 # Vec Defs: VSL10(VSR10) Vec Uses: V2(VSR34)V2(VSR34)
+; TRACKLIVE-NEXT:    xxlor vs4, v2, v2 # Vec Defs: VSL4(VSR4) Vec Uses: V2(VSR34)V2(VSR34)
+; TRACKLIVE-NEXT:    xxlor vs8, vs10, vs10 # Vec Defs: VSL8(VSR8) Vec Uses: VSL10(VSR10)VSL10(VSR10)
+; TRACKLIVE-NEXT:    xxlor vs10, v1, v1 # Vec Defs: VSL10(VSR10) Vec Uses: V1(VSR33)V1(VSR33)
+; TRACKLIVE-NEXT:    xvmaddadp vs7, vs0, v5 # Vec Defs: VSL7(VSR7) Vec Uses: VSL7(VSR7)VSL0(VSR0)V5(VSR37)
+; TRACKLIVE-NEXT:    xvmuldp vs6, vs0, v2 # Vec Defs: VSL6(VSR6) Vec Uses: VSL0(VSR0)V2(VSR34)
+; TRACKLIVE-NEXT:    lxv vs0, -16(r5) # Vec Defs: VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvmaddadp vs3, vs1, v2 # Vec Defs: VSL3(VSR3) Vec Uses: VSL3(VSR3)VSL1(VSR1)V2(VSR34)
+; TRACKLIVE-NEXT:    xvmaddadp vs2, vs1, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL2(VSR2)VSL1(VSR1)VSL2(VSR2)
+; TRACKLIVE-NEXT:    lxvdsx v6, r6, r4 # Vec Defs: V6(VSR38)
 ; TRACKLIVE-NEXT:    li r6, 0
-; TRACKLIVE-NEXT:    xvmaddadp vs7, v2, v2
-; TRACKLIVE-NEXT:    xvmaddadp vs6, v2, v2
-; TRACKLIVE-NEXT:    xvmaddadp vs12, vs0, vs12
-; TRACKLIVE-NEXT:    xvmuldp v3, vs1, v6
-; TRACKLIVE-NEXT:    xvmuldp vs11, v4, v6
-; TRACKLIVE-NEXT:    xvmuldp vs13, vs0, v6
-; TRACKLIVE-NEXT:    xvmuldp vs5, v6, v2
-; TRACKLIVE-NEXT:    xxlor vs0, v2, v2
-; TRACKLIVE-NEXT:    xxlor vs14, vs12, vs12
-; TRACKLIVE-NEXT:    xxlor vs12, v2, v2
-; TRACKLIVE-NEXT:    xxlor vs1, v3, v3
-; TRACKLIVE-NEXT:    xxlor vs9, vs11, vs11
-; TRACKLIVE-NEXT:    xxlor vs15, vs13, vs13
-; TRACKLIVE-NEXT:    xxmtacc acc1
-; TRACKLIVE-NEXT:    xxmtacc acc0
-; TRACKLIVE-NEXT:    xxmtacc acc2
-; TRACKLIVE-NEXT:    xxmtacc acc3
-; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; TRACKLIVE-NEXT:    xxmfacc acc0
-; TRACKLIVE-NEXT:    xxmfacc acc1
-; TRACKLIVE-NEXT:    xxmfacc acc2
-; TRACKLIVE-NEXT:    xxmfacc acc3
-; TRACKLIVE-NEXT:    stxv vs1, 0(r3)
-; TRACKLIVE-NEXT:    stxv vs9, 32(r3)
-; TRACKLIVE-NEXT:    stxv vs4, 16(0)
-; TRACKLIVE-NEXT:    stxv vs12, 48(0)
+; TRACKLIVE-NEXT:    xvmaddadp vs7, v2, v2 # Vec Defs: VSL7(VSR7) Vec Uses: VSL7(VSR7)V2(VSR34)V2(VSR34)
+; TRACKLIVE-NEXT:    xvmaddadp vs6, v2, v2 # Vec Defs: VSL6(VSR6) Vec Uses: VSL6(VSR6)V2(VSR34)V2(VSR34)
+; TRACKLIVE-NEXT:    xvmaddadp vs12, vs0, vs12 # Vec Defs: VSL12(VSR12) Vec Uses: VSL12(VSR12)VSL0(VSR0)VSL12(VSR12)
+; TRACKLIVE-NEXT:    xvmuldp v3, vs1, v6 # Vec Defs: V3(VSR35) Vec Uses: VSL1(VSR1)V6(VSR38)
+; TRACKLIVE-NEXT:    xvmuldp vs11, v4, v6 # Vec Defs: VSL11(VSR11) Vec Uses: V4(VSR36)V6(VSR38)
+; TRACKLIVE-NEXT:    xvmuldp vs13, vs0, v6 # Vec Defs: VSL13(VSR13) Vec Uses: VSL0(VSR0)V6(VSR38)
+; TRACKLIVE-NEXT:    xvmuldp vs5, v6, v2 # Vec Defs: VSL5(VSR5) Vec Uses: V6(VSR38)V2(VSR34)
+; TRACKLIVE-NEXT:    xxlor vs0, v2, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; TRACKLIVE-NEXT:    xxlor vs14, vs12, vs12 # Vec Defs: VSL14(VSR14) Vec Uses: VSL12(VSR12)VSL12(VSR12)
+; TRACKLIVE-NEXT:    xxlor vs12, v2, v2 # Vec Defs: VSL12(VSR12) Vec Uses: V2(VSR34)V2(VSR34)
+; TRACKLIVE-NEXT:    xxlor vs1, v3, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; TRACKLIVE-NEXT:    xxlor vs9, vs11, vs11 # Vec Defs: VSL9(VSR9) Vec Uses: VSL11(VSR11)VSL11(VSR11)
+; TRACKLIVE-NEXT:    xxlor vs15, vs13, vs13 # Vec Defs: VSL15(VSR15) Vec Uses: VSL13(VSR13)VSL13(VSR13)
+; TRACKLIVE-NEXT:    xxmtacc acc1 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)
+; TRACKLIVE-NEXT:    xxmtacc acc0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)
+; TRACKLIVE-NEXT:    xxmtacc acc2 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)
+; TRACKLIVE-NEXT:    xxmtacc acc3 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)
+; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xxmfacc acc0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)
+; TRACKLIVE-NEXT:    xxmfacc acc1 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)
+; TRACKLIVE-NEXT:    xxmfacc acc2 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)
+; TRACKLIVE-NEXT:    xxmfacc acc3 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)
+; TRACKLIVE-NEXT:    stxv vs1, 0(r3) # Vec Uses: VSL1(VSR1)
+; TRACKLIVE-NEXT:    stxv vs9, 32(r3) # Vec Uses: VSL9(VSR9)
+; TRACKLIVE-NEXT:    stxv vs4, 16(0) # Vec Uses: VSL4(VSR4)
+; TRACKLIVE-NEXT:    stxv vs12, 48(0) # Vec Uses: VSL12(VSR12)
 ; TRACKLIVE-NEXT:    b .LBB0_1
 bb:
   %i = load i32, i32* %arg, align 4
   %i3 = sext i32 %i to i64
   %i4 = shl nsw i64 %i3, 3
   %i5 = bitcast [0 x %0]* %arg1 to i8*
   %i6 = getelementptr i8, i8* %i5, i64 undef
   %i7 = getelementptr [0 x %1], [0 x %1]* %arg2, i64 0, i64 -8