[PowerPC] Add assembly comments for instructions that use the vector registers.

[stefanp]

Summary

A number of register types overlap with the vector registers. When reading the
assembly it is not immediately obvious what vector registers overlap with what
other registers. This patch aims to add a comment to show which VSR registers
are used or defined for each instruction.

[amyk]

nit: The description has regsiter a number of times, please update it to register

This a ver useful patch. Thanks Stefan! I have a question (might be silly but...), if verbose asm is enabled by default, does it require an update to more than the two test cases that you've updated in this patch?
(I guess what I am getting at here is if verbose asm is enabled by default, I would have expected a whole bunch of other tests to also require updating, but I may be misunderstanding here.)

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstComments.cpp

23

125

[stefanp]

Updated a couple of comments.

[stefanp]

In D116743#3227465, @amyk wrote:

nit: The description has regsiter a number of times, please update it to register

This a ver useful patch. Thanks Stefan! I have a question (might be silly but...), if verbose asm is enabled by default, does it require an update to more than the two test cases that you've updated in this patch?
(I guess what I am getting at here is if verbose asm is enabled by default, I would have expected a whole bunch of other tests to also require updating, but I may be misunderstanding here.)

For some reason I always seem to typo the word register. Not sure why... Anyway, thank you for finding them.

Not a silly question at all!
Initially I thought that I didn't need to update the tests because I wan't changing code and the CHECK/CHECK-NEXT lines don't really care that there are comments that come after the instructions. This is true in most cases but there are tests that already have a comment after the instruction line (for example # 8-byte Folded Spill) and in those cases by adding a second comment I'm adding a new line and the CHECK-NEXT lines don't work anymore. Anyway, I'm going to update those tests now.

[stefanp]

Updated a whole set of tests that now have additional comments.

[amyk]

In D116743#3250956, @stefanp wrote:

In D116743#3227465, @amyk wrote:

nit: The description has regsiter a number of times, please update it to register

This a ver useful patch. Thanks Stefan! I have a question (might be silly but...), if verbose asm is enabled by default, does it require an update to more than the two test cases that you've updated in this patch?
(I guess what I am getting at here is if verbose asm is enabled by default, I would have expected a whole bunch of other tests to also require updating, but I may be misunderstanding here.)

For some reason I always seem to typo the word register. Not sure why... Anyway, thank you for finding them.

Not a silly question at all!
Initially I thought that I didn't need to update the tests because I wan't changing code and the CHECK/CHECK-NEXT lines don't really care that there are comments that come after the instructions. This is true in most cases but there are tests that already have a comment after the instruction line (for example # 8-byte Folded Spill) and in those cases by adding a second comment I'm adding a new line and the CHECK-NEXT lines don't work anymore. Anyway, I'm going to update those tests now.

Thanks for addressing the comment, Stefan!
I think overall, it LGTM.

[lei]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstComments.cpp

32–39

This seems like something that can be useful in other implementations.
Wondering if it's better is we define functions such as isRegInClass(), isVecReg() similar to what's defined in PPCVSXSwapRemoval.cpp but have it as part of class PPCRegisterInfo. Currently I see diff implementation of similar checks in various classes.

112

Wondering why this is not implemented as part of the PPCInstPrinter class since it's only ever used for printing PPC instructions.

155

This bool return value seem to have no uses.

llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll

152

Seems Vec Uses: contain duplicate input for the same vector?

Vec Uses: V3(VSR35)V3(VSR35)

[lei]

Not a silly question at all!
Initially I thought that I didn't need to update the tests because I wan't changing code and the CHECK/CHECK-NEXT lines don't really care that there are comments that come after the instructions. This is true in most cases but there are tests that already have a comment after the instruction line (for example # 8-byte Folded Spill) and in those cases by adding a second comment I'm adding a new line and the CHECK-NEXT lines don't work anymore. Anyway, I'm going to update those tests now.

Is it possible to append to the comment line instead of adding a new comment line below it? Not a huge deal but thought maybe it would look cleaner to have all comments on the same line. Or at least indented to indicate it's part of the previous line?

[stefanp]

I have not had time to do this and the priority of this work is very low so I don't see myself getting back to it.
As a result, I'm going to abandon this patch.

llvm/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt

 add_llvm_component_library(LLVMPowerPCDesc
   PPCAsmBackend.cpp
   PPCInstPrinter.cpp
+  PPCInstComments.cpp
   PPCMCTargetDesc.cpp
   PPCMCAsmInfo.cpp
   PPCMCCodeEmitter.cpp
   PPCMCExpr.cpp
   PPCPredicates.cpp
   PPCELFObjectWriter.cpp
   PPCXCOFFObjectWriter.cpp
   PPCELFStreamer.cpp

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstComments.h

+//=- PPCInstComments.h - Generate verbose-asm comments for instrs -*- C++ -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This defines functionality used to emit comments about PPC instructions to
+// an output stream for -fverbose-asm.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCINSTCOMMENTS_H
+#define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCINSTCOMMENTS_H
+
+namespace llvm {
+
+class MCInst;
+class MCInstrInfo;
+class raw_ostream;
+bool EmitAnyPPCInstComments(const MCInst *MI, raw_ostream &OS,
+                            const MCInstrInfo &MCII);
+} // namespace llvm
+
+#endif

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstComments.cpp

+//===-- PPCInstComments.cpp - Generate verbose-asm comments for instrs ----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This defines functionality used to emit comments about PPC instructions to
+// an output stream for -fverbose-asm.
+//
+//===----------------------------------------------------------------------===//
+
+#include "PPCInstComments.h"
+#include "PPCInstrInfo.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+// hasVectorRegs return a pair of booleans if MI uses or defines any registers
+// that overlap with the vector registers.
+static std::pair<bool, bool> hasVectorRegs(const MCInst *MI, unsigned NumDefs) {
+  std::pair<bool, bool> HasVecUseOrDef{false, false};
+  for (unsigned OpNumber = 0; OpNumber < MI->size(); ++OpNumber) {
+    const MCOperand &Operand = MI->getOperand(OpNumber);
+    if (!Operand.isReg())
+      continue;
+
+    unsigned RegNumber = Operand.getReg();
+    if ((RegNumber >= PPC::F0 && RegNumber <= PPC::F31) ||
+        (RegNumber >= PPC::VF0 && RegNumber <= PPC::VF31) ||
+        (RegNumber >= PPC::V0 && RegNumber <= PPC::V31) ||
+        (RegNumber >= PPC::VSL0 && RegNumber <= PPC::VSL31) ||
+        (RegNumber >= PPC::VSX32 && RegNumber <= PPC::VSX63) ||
+        (RegNumber >= PPC::VSRp0 && RegNumber <= PPC::VSRp31) ||
+        (RegNumber >= PPC::ACC0 && RegNumber <= PPC::ACC7) ||
+        (RegNumber >= PPC::UACC0 && RegNumber <= PPC::UACC7)) {
+      // second is true if this is a def.
+      if (OpNumber < NumDefs)
+        HasVecUseOrDef.second = true;
+      else
+        HasVecUseOrDef.first = true;
+    }
+  }
+  return HasVecUseOrDef;
+}
+
+// Print the full register name along with the VSR register(s) it overlaps.
+// Returns true if something was printed to the stream.
+static bool printFullReg(unsigned RegNumber, raw_ostream &OS) {
+  if (RegNumber >= PPC::F0 && RegNumber <= PPC::F31) {
+    OS << "F" << RegNumber - PPC::F0 << "(VSR" << RegNumber - PPC::F0 << ")";
+    return true;
+  }
+
+  if (RegNumber >= PPC::VF0 && RegNumber <= PPC::VF31) {
+    OS << "VF" << RegNumber - PPC::VF0 << "(VSR" << RegNumber - PPC::VF0 << ")";
+    return true;
+  }
+
+  if (RegNumber >= PPC::V0 && RegNumber <= PPC::V31) {
+    OS << "V" << RegNumber - PPC::V0 << "(VSR" << RegNumber - PPC::V0 + 32
+       << ")";
+    return true;
+  }
+
+  if (RegNumber >= PPC::VSL0 && RegNumber <= PPC::VSL31) {
+    OS << "VSL" << RegNumber - PPC::VSL0 << "(VSR" << RegNumber - PPC::VSL0
+       << ")";
+    return true;
+  }
+
+  if (RegNumber >= PPC::VSX32 && RegNumber <= PPC::VSX63) {
+    OS << "VSX" << RegNumber - PPC::VSX32 + 32 << "(VSR"
+       << RegNumber - PPC::VSX32 + 32 << ")";
+    return true;
+  }
+
+  if (RegNumber >= PPC::VSRp0 && RegNumber <= PPC::VSRp31) {
+    OS << "VSRp" << RegNumber - PPC::VSRp0 << "(VSR"
+       << (RegNumber - PPC::VSRp0) * 2 << ","
+       << "VSR" << (RegNumber - PPC::VSRp0) * 2 + 1 << ")";
+    return true;
+  }
+
+  if (RegNumber >= PPC::ACC0 && RegNumber <= PPC::ACC7) {
+    OS << "ACC" << RegNumber - PPC::ACC0 << "(VSR"
+       << (RegNumber - PPC::ACC0) * 4 << ","
+       << "VSR" << (RegNumber - PPC::ACC0) * 4 + 1 << ","
+       << "VSR" << (RegNumber - PPC::ACC0) * 4 + 2 << ","
+       << "VSR" << (RegNumber - PPC::ACC0) * 4 + 3 << ")";
+    return true;
+  }
+
+  if (RegNumber >= PPC::UACC0 && RegNumber <= PPC::UACC7) {
+    OS << "UACC" << RegNumber - PPC::UACC0 << "(VSR"
+       << (RegNumber - PPC::UACC0) * 4 << ","
+       << "VSR" << (RegNumber - PPC::UACC0) * 4 + 1 << ","
+       << "VSR" << (RegNumber - PPC::UACC0) * 4 + 2 << ","
+       << "VSR" << (RegNumber - PPC::UACC0) * 4 + 3 << ")";
+    return true;
+  }
+  return false;
+}
+
+/// EmitAnyPPCInstComments - This function decodes PowerPC instructions and
+/// prints newline terminated strings to the specified string if desired. This
+/// information is shown in disassembly dumps when verbose assembly is enabled.
+/// Returns true if comments were added and false otherwise.
+bool llvm::EmitAnyPPCInstComments(const MCInst *MI, raw_ostream &OS,
+                                  const MCInstrInfo &MCII) {
+  bool HaveComment = false;
+  // If there are no operands exit early.
+  if (MI->size() == 0)
+    return false;
+
+  const MCInstrDesc &MCDesc = MCII.get(MI->getOpcode());
+  unsigned NumDefs = MCDesc.getNumDefs();
+
+  std::pair<bool, bool> HasVecUseOrDef = hasVectorRegs(MI, NumDefs);
+
+  // If the instruction has no vector registers we don't really care.
+  if (!HasVecUseOrDef.first && !HasVecUseOrDef.second)
+    return false;
+
+  unsigned OpNumber = 0;
+  // Print out vector defs if any exist.
+  if (HasVecUseOrDef.second) {
+    OS << "Vec Defs: ";
+    for (OpNumber = 0; OpNumber < NumDefs; ++OpNumber) {
+      const MCOperand &Operand = MI->getOperand(OpNumber);
+      if (!Operand.isReg())
+        continue;
+      HaveComment = printFullReg(Operand.getReg(), OS);
+    }
+    // If vector uses exist add a tab to separate the uses and defs.
+    if (HasVecUseOrDef.first)
+      OS << "\t";
+  }
+
+  // Print out vector uses if any exist.
+  if (HasVecUseOrDef.first) {
+    OS << "Vec Uses: ";
+    for (OpNumber = NumDefs; OpNumber < MI->size(); ++OpNumber) {
+      const MCOperand &Operand = MI->getOperand(OpNumber);
+      if (!Operand.isReg())
+        continue;
+      HaveComment = printFullReg(Operand.getReg(), OS);
+    }
+  }
+  OS << "\n";
+
+  return HaveComment;
+}

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This class prints an PPC MCInst to a .s file.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/PPCInstPrinter.h"
+#include "MCTargetDesc/PPCInstComments.h"
 #include "MCTargetDesc/PPCMCTargetDesc.h"
 #include "MCTargetDesc/PPCPredicates.h"
 #include "PPCInstrInfo.h"
 #include "llvm/CodeGen/TargetOpcodes.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"

 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
   const char *RegName = getRegisterName(RegNo);
   OS << RegName;
 }
 
 void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
                                StringRef Annot, const MCSubtargetInfo &STI,
                                raw_ostream &O) {
+  // Print comments if verbose assembly is enabled.
+  if (CommentStream)
+    EmitAnyPPCInstComments(MI, (*CommentStream), MII);
+
   // Customize printing of the addis instruction on AIX. When an operand is a
   // symbol reference, the instruction syntax is changed to look like a load
   // operation, i.e:
   //     Transform:  addis $rD, $rA, $src --> addis $rD, $src($rA).
   if (TT.isOSAIX() &&
       (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
       MI->getOperand(2).isExpr()) {
     assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&

llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o - | FileCheck %s
 
 define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
 ; CHECK-LABEL: __fixunstfdi:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stw 0, 4(1)
 ; CHECK-NEXT:    stwu 1, -464(1)
 ; CHECK-NEXT:    mfcr 12
 ; CHECK-NEXT:    stw 29, 412(1) # 4-byte Folded Spill
 ; CHECK-NEXT:    lis 3, .LCPI0_0@ha
 ; CHECK-NEXT:    stw 30, 416(1) # 4-byte Folded Spill
 ; CHECK-NEXT:    stw 12, 408(1)
-; CHECK-NEXT:    stfd 2, 376(1)
+; CHECK-NEXT:    stfd 2, 376(1) # Vec Uses: F2(VSR2)
 ; CHECK-NEXT:    lwz 4, 380(1)
 ; CHECK-NEXT:    stfd 27, 424(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F27(VSR27)
 ; CHECK-NEXT:    stw 4, 396(1)
 ; CHECK-NEXT:    lwz 4, 376(1)
-; CHECK-NEXT:    lfs 27, .LCPI0_0@l(3)
-; CHECK-NEXT:    stfd 1, 384(1)
+; CHECK-NEXT:    lfs 27, .LCPI0_0@l(3) # Vec Defs: F27(VSR27)
+; CHECK-NEXT:    stfd 1, 384(1) # Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    stw 4, 392(1)
-; CHECK-NEXT:    fcmpu 0, 2, 27
+; CHECK-NEXT:    fcmpu 0, 2, 27 # Vec Uses: F2(VSR2)F27(VSR27)
 ; CHECK-NEXT:    lwz 4, 388(1)
-; CHECK-NEXT:    fcmpu 1, 1, 27
+; CHECK-NEXT:    fcmpu 1, 1, 27 # Vec Uses: F1(VSR1)F27(VSR27)
 ; CHECK-NEXT:    lwz 3, 384(1)
 ; CHECK-NEXT:    crand 20, 6, 0
 ; CHECK-NEXT:    cror 20, 4, 20
 ; CHECK-NEXT:    stfd 28, 432(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F28(VSR28)
 ; CHECK-NEXT:    stfd 29, 440(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F29(VSR29)
 ; CHECK-NEXT:    stfd 30, 448(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F30(VSR30)
 ; CHECK-NEXT:    stfd 31, 456(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F31(VSR31)
 ; CHECK-NEXT:    stw 4, 404(1)
 ; CHECK-NEXT:    stw 3, 400(1)
 ; CHECK-NEXT:    bc 4, 20, .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %bb5
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    li 4, 0
 ; CHECK-NEXT:    b .LBB0_17
 ; CHECK-NEXT:  .LBB0_2: # %bb1
-; CHECK-NEXT:    lfd 0, 400(1)
+; CHECK-NEXT:    lfd 0, 400(1) # Vec Defs: F0(VSR0)
 ; CHECK-NEXT:    lis 3, 15856
 ; CHECK-NEXT:    stw 3, 336(1)
 ; CHECK-NEXT:    li 29, 0
-; CHECK-NEXT:    stfd 0, 304(1)
+; CHECK-NEXT:    stfd 0, 304(1) # Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    lwz 3, 308(1)
-; CHECK-NEXT:    lfd 1, 392(1)
+; CHECK-NEXT:    lfd 1, 392(1) # Vec Defs: F1(VSR1)
 ; CHECK-NEXT:    stw 3, 324(1)
 ; CHECK-NEXT:    lwz 3, 304(1)
-; CHECK-NEXT:    stfd 1, 296(1)
+; CHECK-NEXT:    stfd 1, 296(1) # Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    stw 3, 320(1)
 ; CHECK-NEXT:    lwz 3, 300(1)
 ; CHECK-NEXT:    stw 29, 340(1)
 ; CHECK-NEXT:    stw 3, 316(1)
 ; CHECK-NEXT:    lwz 3, 296(1)
 ; CHECK-NEXT:    stw 29, 332(1)
 ; CHECK-NEXT:    stw 3, 312(1)
 ; CHECK-NEXT:    stw 29, 328(1)
-; CHECK-NEXT:    lfd 31, 320(1)
-; CHECK-NEXT:    lfd 30, 312(1)
-; CHECK-NEXT:    lfd 3, 336(1)
-; CHECK-NEXT:    fmr 1, 31
-; CHECK-NEXT:    lfd 4, 328(1)
-; CHECK-NEXT:    fmr 2, 30
+; CHECK-NEXT:    lfd 31, 320(1) # Vec Defs: F31(VSR31)
+; CHECK-NEXT:    lfd 30, 312(1) # Vec Defs: F30(VSR30)
+; CHECK-NEXT:    lfd 3, 336(1) # Vec Defs: F3(VSR3)
+; CHECK-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
+; CHECK-NEXT:    lfd 4, 328(1) # Vec Defs: F4(VSR4)
+; CHECK-NEXT:    fmr 2, 30 # Vec Defs: F2(VSR2) Vec Uses: F30(VSR30)
 ; CHECK-NEXT:    bl __gcc_qmul
 ; CHECK-NEXT:    lis 3, 16864
-; CHECK-NEXT:    stfd 1, 280(1)
-; CHECK-NEXT:    fmr 29, 1
+; CHECK-NEXT:    stfd 1, 280(1) # Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 29, 1 # Vec Defs: F29(VSR29) Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    stw 3, 368(1)
-; CHECK-NEXT:    fmr 28, 2
+; CHECK-NEXT:    fmr 28, 2 # Vec Defs: F28(VSR28) Vec Uses: F2(VSR2)
 ; CHECK-NEXT:    lwz 3, 284(1)
-; CHECK-NEXT:    stfd 2, 288(1)
+; CHECK-NEXT:    stfd 2, 288(1) # Vec Uses: F2(VSR2)
 ; CHECK-NEXT:    stw 3, 356(1)
 ; CHECK-NEXT:    lwz 3, 280(1)
 ; CHECK-NEXT:    stw 29, 372(1)
 ; CHECK-NEXT:    stw 3, 352(1)
 ; CHECK-NEXT:    lwz 3, 292(1)
 ; CHECK-NEXT:    stw 29, 364(1)
 ; CHECK-NEXT:    stw 3, 348(1)
 ; CHECK-NEXT:    lwz 3, 288(1)
 ; CHECK-NEXT:    stw 29, 360(1)
 ; CHECK-NEXT:    stw 3, 344(1)
-; CHECK-NEXT:    lfd 3, 368(1)
-; CHECK-NEXT:    lfd 4, 360(1)
-; CHECK-NEXT:    lfd 1, 352(1)
-; CHECK-NEXT:    lfd 2, 344(1)
+; CHECK-NEXT:    lfd 3, 368(1) # Vec Defs: F3(VSR3)
+; CHECK-NEXT:    lfd 4, 360(1) # Vec Defs: F4(VSR4)
+; CHECK-NEXT:    lfd 1, 352(1) # Vec Defs: F1(VSR1)
+; CHECK-NEXT:    lfd 2, 344(1) # Vec Defs: F2(VSR2)
 ; CHECK-NEXT:    bl __gcc_qsub
-; CHECK-NEXT:    mffs 0
+; CHECK-NEXT:    mffs 0 # Vec Defs: F0(VSR0)
 ; CHECK-NEXT:    mtfsb1 31
 ; CHECK-NEXT:    mtfsb0 30
-; CHECK-NEXT:    fadd 1, 2, 1
-; CHECK-NEXT:    mtfsf 1, 0
-; CHECK-NEXT:    fctiwz 0, 1
-; CHECK-NEXT:    stfd 0, 160(1)
-; CHECK-NEXT:    mffs 0
+; CHECK-NEXT:    fadd 1, 2, 1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; CHECK-NEXT:    mtfsf 1, 0 # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    fctiwz 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    stfd 0, 160(1) # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    mffs 0 # Vec Defs: F0(VSR0)
 ; CHECK-NEXT:    mtfsb1 31
 ; CHECK-NEXT:    lis 3, .LCPI0_1@ha
 ; CHECK-NEXT:    mtfsb0 30
-; CHECK-NEXT:    fadd 1, 28, 29
-; CHECK-NEXT:    mtfsf 1, 0
-; CHECK-NEXT:    lfs 0, .LCPI0_1@l(3)
-; CHECK-NEXT:    fctiwz 1, 1
-; CHECK-NEXT:    stfd 1, 152(1)
-; CHECK-NEXT:    fcmpu 0, 28, 27
+; CHECK-NEXT:    fadd 1, 28, 29 # Vec Defs: F1(VSR1) Vec Uses: F28(VSR28)F29(VSR29)
+; CHECK-NEXT:    mtfsf 1, 0 # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    lfs 0, .LCPI0_1@l(3) # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    fctiwz 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    stfd 1, 152(1) # Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fcmpu 0, 28, 27 # Vec Uses: F28(VSR28)F27(VSR27)
 ; CHECK-NEXT:    lwz 3, 164(1)
-; CHECK-NEXT:    fcmpu 1, 29, 0
+; CHECK-NEXT:    fcmpu 1, 29, 0 # Vec Uses: F29(VSR29)F0(VSR0)
 ; CHECK-NEXT:    lwz 4, 156(1)
 ; CHECK-NEXT:    crandc 20, 6, 0
 ; CHECK-NEXT:    cror 20, 5, 20
 ; CHECK-NEXT:    addis 3, 3, -32768
 ; CHECK-NEXT:    bc 12, 20, .LBB0_4
 ; CHECK-NEXT:  # %bb.3: # %bb1
 ; CHECK-NEXT:    ori 30, 4, 0
 ; CHECK-NEXT:    b .LBB0_5
 ; CHECK-NEXT:  .LBB0_4: # %bb1
 ; CHECK-NEXT:    addi 30, 3, 0
 ; CHECK-NEXT:  .LBB0_5: # %bb1
 ; CHECK-NEXT:    li 4, 0
 ; CHECK-NEXT:    mr 3, 30
 ; CHECK-NEXT:    bl __floatditf
 ; CHECK-NEXT:    lis 3, 17392
-; CHECK-NEXT:    stfd 1, 208(1)
-; CHECK-NEXT:    fmr 29, 1
+; CHECK-NEXT:    stfd 1, 208(1) # Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 29, 1 # Vec Defs: F29(VSR29) Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    stw 3, 240(1)
-; CHECK-NEXT:    fmr 28, 2
+; CHECK-NEXT:    fmr 28, 2 # Vec Defs: F28(VSR28) Vec Uses: F2(VSR2)
 ; CHECK-NEXT:    lwz 3, 212(1)
 ; CHECK-NEXT:    cmpwi 2, 30, 0
-; CHECK-NEXT:    stfd 2, 200(1)
+; CHECK-NEXT:    stfd 2, 200(1) # Vec Uses: F2(VSR2)
 ; CHECK-NEXT:    stw 3, 228(1)
 ; CHECK-NEXT:    lwz 3, 208(1)
 ; CHECK-NEXT:    stw 29, 244(1)
 ; CHECK-NEXT:    stw 3, 224(1)
 ; CHECK-NEXT:    lwz 3, 204(1)
 ; CHECK-NEXT:    stw 29, 236(1)
 ; CHECK-NEXT:    stw 3, 220(1)
 ; CHECK-NEXT:    lwz 3, 200(1)
 ; CHECK-NEXT:    stw 29, 232(1)
 ; CHECK-NEXT:    stw 3, 216(1)
-; CHECK-NEXT:    lfd 3, 240(1)
-; CHECK-NEXT:    lfd 4, 232(1)
-; CHECK-NEXT:    lfd 1, 224(1)
-; CHECK-NEXT:    lfd 2, 216(1)
+; CHECK-NEXT:    lfd 3, 240(1) # Vec Defs: F3(VSR3)
+; CHECK-NEXT:    lfd 4, 232(1) # Vec Defs: F4(VSR4)
+; CHECK-NEXT:    lfd 1, 224(1) # Vec Defs: F1(VSR1)
+; CHECK-NEXT:    lfd 2, 216(1) # Vec Defs: F2(VSR2)
 ; CHECK-NEXT:    bl __gcc_qadd
 ; CHECK-NEXT:    blt 2, .LBB0_7
 ; CHECK-NEXT:  # %bb.6: # %bb1
-; CHECK-NEXT:    fmr 2, 28
+; CHECK-NEXT:    fmr 2, 28 # Vec Defs: F2(VSR2) Vec Uses: F28(VSR28)
 ; CHECK-NEXT:  .LBB0_7: # %bb1
 ; CHECK-NEXT:    blt 2, .LBB0_9
 ; CHECK-NEXT:  # %bb.8: # %bb1
-; CHECK-NEXT:    fmr 1, 29
+; CHECK-NEXT:    fmr 1, 29 # Vec Defs: F1(VSR1) Vec Uses: F29(VSR29)
 ; CHECK-NEXT:  .LBB0_9: # %bb1
-; CHECK-NEXT:    stfd 1, 184(1)
-; CHECK-NEXT:    fmr 1, 31
+; CHECK-NEXT:    stfd 1, 184(1) # Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; CHECK-NEXT:    lwz 3, 188(1)
-; CHECK-NEXT:    stfd 2, 192(1)
-; CHECK-NEXT:    fmr 2, 30
+; CHECK-NEXT:    stfd 2, 192(1) # Vec Uses: F2(VSR2)
+; CHECK-NEXT:    fmr 2, 30 # Vec Defs: F2(VSR2) Vec Uses: F30(VSR30)
 ; CHECK-NEXT:    stw 3, 260(1)
 ; CHECK-NEXT:    lwz 3, 184(1)
 ; CHECK-NEXT:    stw 3, 256(1)
 ; CHECK-NEXT:    lwz 3, 196(1)
-; CHECK-NEXT:    lfd 3, 256(1)
+; CHECK-NEXT:    lfd 3, 256(1) # Vec Defs: F3(VSR3)
 ; CHECK-NEXT:    stw 3, 252(1)
 ; CHECK-NEXT:    lwz 3, 192(1)
 ; CHECK-NEXT:    stw 3, 248(1)
-; CHECK-NEXT:    lfd 4, 248(1)
+; CHECK-NEXT:    lfd 4, 248(1) # Vec Defs: F4(VSR4)
 ; CHECK-NEXT:    bl __gcc_qsub
-; CHECK-NEXT:    stfd 2, 176(1)
-; CHECK-NEXT:    fcmpu 1, 2, 27
+; CHECK-NEXT:    stfd 2, 176(1) # Vec Uses: F2(VSR2)
+; CHECK-NEXT:    fcmpu 1, 2, 27 # Vec Uses: F2(VSR2)F27(VSR27)
 ; CHECK-NEXT:    lwz 3, 180(1)
-; CHECK-NEXT:    fcmpu 0, 1, 27
-; CHECK-NEXT:    stfd 1, 168(1)
+; CHECK-NEXT:    fcmpu 0, 1, 27 # Vec Uses: F1(VSR1)F27(VSR27)
+; CHECK-NEXT:    stfd 1, 168(1) # Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    crandc 20, 2, 4
 ; CHECK-NEXT:    stw 3, 268(1)
 ; CHECK-NEXT:    lwz 3, 176(1)
 ; CHECK-NEXT:    stw 3, 264(1)
 ; CHECK-NEXT:    lwz 3, 172(1)
-; CHECK-NEXT:    lfd 30, 264(1)
+; CHECK-NEXT:    lfd 30, 264(1) # Vec Defs: F30(VSR30)
 ; CHECK-NEXT:    stw 3, 276(1)
 ; CHECK-NEXT:    lwz 3, 168(1)
 ; CHECK-NEXT:    stw 3, 272(1)
-; CHECK-NEXT:    lfd 31, 272(1)
+; CHECK-NEXT:    lfd 31, 272(1) # Vec Defs: F31(VSR31)
 ; CHECK-NEXT:    bc 12, 20, .LBB0_14
 ; CHECK-NEXT:  # %bb.10: # %bb1
 ; CHECK-NEXT:    cror 20, 1, 3
 ; CHECK-NEXT:    bc 12, 20, .LBB0_14
 ; CHECK-NEXT:  # %bb.11: # %bb2
-; CHECK-NEXT:    fneg 29, 31
-; CHECK-NEXT:    stfd 29, 48(1)
+; CHECK-NEXT:    fneg 29, 31 # Vec Defs: F29(VSR29) Vec Uses: F31(VSR31)
+; CHECK-NEXT:    stfd 29, 48(1) # Vec Uses: F29(VSR29)
 ; CHECK-NEXT:    lis 3, 16864
 ; CHECK-NEXT:    stw 3, 80(1)
-; CHECK-NEXT:    fneg 28, 30
+; CHECK-NEXT:    fneg 28, 30 # Vec Defs: F28(VSR28) Vec Uses: F30(VSR30)
 ; CHECK-NEXT:    lwz 3, 52(1)
 ; CHECK-NEXT:    li 29, 0
-; CHECK-NEXT:    stfd 28, 40(1)
+; CHECK-NEXT:    stfd 28, 40(1) # Vec Uses: F28(VSR28)
 ; CHECK-NEXT:    stw 3, 68(1)
 ; CHECK-NEXT:    lwz 3, 48(1)
 ; CHECK-NEXT:    stw 29, 84(1)
 ; CHECK-NEXT:    stw 3, 64(1)
 ; CHECK-NEXT:    lwz 3, 44(1)
 ; CHECK-NEXT:    stw 29, 76(1)
 ; CHECK-NEXT:    stw 3, 60(1)
 ; CHECK-NEXT:    lwz 3, 40(1)
 ; CHECK-NEXT:    stw 29, 72(1)
 ; CHECK-NEXT:    stw 3, 56(1)
-; CHECK-NEXT:    lfd 3, 80(1)
-; CHECK-NEXT:    lfd 4, 72(1)
-; CHECK-NEXT:    lfd 1, 64(1)
-; CHECK-NEXT:    lfd 2, 56(1)
+; CHECK-NEXT:    lfd 3, 80(1) # Vec Defs: F3(VSR3)
+; CHECK-NEXT:    lfd 4, 72(1) # Vec Defs: F4(VSR4)
+; CHECK-NEXT:    lfd 1, 64(1) # Vec Defs: F1(VSR1)
+; CHECK-NEXT:    lfd 2, 56(1) # Vec Defs: F2(VSR2)
 ; CHECK-NEXT:    bl __gcc_qsub
-; CHECK-NEXT:    mffs 0
+; CHECK-NEXT:    mffs 0 # Vec Defs: F0(VSR0)
 ; CHECK-NEXT:    mtfsb1 31
 ; CHECK-NEXT:    mtfsb0 30
-; CHECK-NEXT:    fadd 1, 2, 1
-; CHECK-NEXT:    mtfsf 1, 0
-; CHECK-NEXT:    fctiwz 0, 1
-; CHECK-NEXT:    stfd 0, 32(1)
-; CHECK-NEXT:    mffs 0
+; CHECK-NEXT:    fadd 1, 2, 1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; CHECK-NEXT:    mtfsf 1, 0 # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    fctiwz 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    stfd 0, 32(1) # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    mffs 0 # Vec Defs: F0(VSR0)
 ; CHECK-NEXT:    mtfsb1 31
 ; CHECK-NEXT:    lis 3, .LCPI0_2@ha
-; CHECK-NEXT:    lfs 2, .LCPI0_2@l(3)
+; CHECK-NEXT:    lfs 2, .LCPI0_2@l(3) # Vec Defs: F2(VSR2)
 ; CHECK-NEXT:    mtfsb0 30
 ; CHECK-NEXT:    lis 3, .LCPI0_3@ha
-; CHECK-NEXT:    fadd 1, 28, 29
-; CHECK-NEXT:    mtfsf 1, 0
-; CHECK-NEXT:    lfs 0, .LCPI0_3@l(3)
-; CHECK-NEXT:    fctiwz 1, 1
-; CHECK-NEXT:    stfd 1, 24(1)
-; CHECK-NEXT:    fcmpu 0, 30, 2
+; CHECK-NEXT:    fadd 1, 28, 29 # Vec Defs: F1(VSR1) Vec Uses: F28(VSR28)F29(VSR29)
+; CHECK-NEXT:    mtfsf 1, 0 # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    lfs 0, .LCPI0_3@l(3) # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    fctiwz 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    stfd 1, 24(1) # Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fcmpu 0, 30, 2 # Vec Uses: F30(VSR30)F2(VSR2)
 ; CHECK-NEXT:    lwz 3, 36(1)
-; CHECK-NEXT:    fcmpu 1, 31, 0
+; CHECK-NEXT:    fcmpu 1, 31, 0 # Vec Uses: F31(VSR31)F0(VSR0)
 ; CHECK-NEXT:    lwz 4, 28(1)
 ; CHECK-NEXT:    crandc 20, 6, 1
 ; CHECK-NEXT:    cror 20, 4, 20
 ; CHECK-NEXT:    addis 3, 3, -32768
 ; CHECK-NEXT:    bc 12, 20, .LBB0_13
 ; CHECK-NEXT:  # %bb.12: # %bb2
 ; CHECK-NEXT:    ori 3, 4, 0
 ; CHECK-NEXT:    b .LBB0_13
 ; CHECK-NEXT:  .LBB0_13: # %bb2
 ; CHECK-NEXT:    subfic 4, 3, 0
 ; CHECK-NEXT:    subfe 3, 29, 30
 ; CHECK-NEXT:    b .LBB0_17
 ; CHECK-NEXT:  .LBB0_14: # %bb3
-; CHECK-NEXT:    stfd 31, 112(1)
+; CHECK-NEXT:    stfd 31, 112(1) # Vec Uses: F31(VSR31)
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    stw 3, 148(1)
 ; CHECK-NEXT:    lis 4, 16864
 ; CHECK-NEXT:    stw 3, 140(1)
 ; CHECK-NEXT:    stw 3, 136(1)
 ; CHECK-NEXT:    lwz 3, 116(1)
-; CHECK-NEXT:    stfd 30, 104(1)
+; CHECK-NEXT:    stfd 30, 104(1) # Vec Uses: F30(VSR30)
 ; CHECK-NEXT:    stw 3, 132(1)
 ; CHECK-NEXT:    lwz 3, 112(1)
 ; CHECK-NEXT:    stw 4, 144(1)
 ; CHECK-NEXT:    stw 3, 128(1)
 ; CHECK-NEXT:    lwz 3, 108(1)
-; CHECK-NEXT:    lfd 3, 144(1)
+; CHECK-NEXT:    lfd 3, 144(1) # Vec Defs: F3(VSR3)
 ; CHECK-NEXT:    stw 3, 124(1)
 ; CHECK-NEXT:    lwz 3, 104(1)
-; CHECK-NEXT:    lfd 4, 136(1)
+; CHECK-NEXT:    lfd 4, 136(1) # Vec Defs: F4(VSR4)
 ; CHECK-NEXT:    stw 3, 120(1)
-; CHECK-NEXT:    lfd 1, 128(1)
-; CHECK-NEXT:    lfd 2, 120(1)
+; CHECK-NEXT:    lfd 1, 128(1) # Vec Defs: F1(VSR1)
+; CHECK-NEXT:    lfd 2, 120(1) # Vec Defs: F2(VSR2)
 ; CHECK-NEXT:    bl __gcc_qsub
-; CHECK-NEXT:    mffs 0
+; CHECK-NEXT:    mffs 0 # Vec Defs: F0(VSR0)
 ; CHECK-NEXT:    mtfsb1 31
 ; CHECK-NEXT:    mtfsb0 30
-; CHECK-NEXT:    fadd 1, 2, 1
-; CHECK-NEXT:    mtfsf 1, 0
-; CHECK-NEXT:    fctiwz 0, 1
-; CHECK-NEXT:    stfd 0, 96(1)
-; CHECK-NEXT:    mffs 0
+; CHECK-NEXT:    fadd 1, 2, 1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; CHECK-NEXT:    mtfsf 1, 0 # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    fctiwz 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    stfd 0, 96(1) # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    mffs 0 # Vec Defs: F0(VSR0)
 ; CHECK-NEXT:    mtfsb1 31
 ; CHECK-NEXT:    lis 3, .LCPI0_0@ha
-; CHECK-NEXT:    lfs 1, .LCPI0_0@l(3)
+; CHECK-NEXT:    lfs 1, .LCPI0_0@l(3) # Vec Defs: F1(VSR1)
 ; CHECK-NEXT:    mtfsb0 30
 ; CHECK-NEXT:    lis 3, .LCPI0_1@ha
-; CHECK-NEXT:    fadd 2, 30, 31
-; CHECK-NEXT:    mtfsf 1, 0
-; CHECK-NEXT:    lfs 0, .LCPI0_1@l(3)
-; CHECK-NEXT:    fctiwz 2, 2
-; CHECK-NEXT:    stfd 2, 88(1)
-; CHECK-NEXT:    fcmpu 0, 30, 1
+; CHECK-NEXT:    fadd 2, 30, 31 # Vec Defs: F2(VSR2) Vec Uses: F30(VSR30)F31(VSR31)
+; CHECK-NEXT:    mtfsf 1, 0 # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    lfs 0, .LCPI0_1@l(3) # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    fctiwz 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; CHECK-NEXT:    stfd 2, 88(1) # Vec Uses: F2(VSR2)
+; CHECK-NEXT:    fcmpu 0, 30, 1 # Vec Uses: F30(VSR30)F1(VSR1)
 ; CHECK-NEXT:    lwz 3, 100(1)
-; CHECK-NEXT:    fcmpu 1, 31, 0
+; CHECK-NEXT:    fcmpu 1, 31, 0 # Vec Uses: F31(VSR31)F0(VSR0)
 ; CHECK-NEXT:    lwz 4, 92(1)
 ; CHECK-NEXT:    crandc 20, 6, 0
 ; CHECK-NEXT:    cror 20, 5, 20
 ; CHECK-NEXT:    addis 3, 3, -32768
 ; CHECK-NEXT:    bc 12, 20, .LBB0_15
 ; CHECK-NEXT:    b .LBB0_16
 ; CHECK-NEXT:  .LBB0_15: # %bb3
 ; CHECK-NEXT:    addi 4, 3, 0
 ; CHECK-NEXT:  .LBB0_16: # %bb3
 ; CHECK-NEXT:    mr 3, 30
 ; CHECK-NEXT:  .LBB0_17: # %bb5
 ; CHECK-NEXT:    lfd 31, 456(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F31(VSR31)
 ; CHECK-NEXT:    lfd 30, 448(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F30(VSR30)
 ; CHECK-NEXT:    lfd 29, 440(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F29(VSR29)
 ; CHECK-NEXT:    lfd 28, 432(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F28(VSR28)
 ; CHECK-NEXT:    lwz 12, 408(1)
 ; CHECK-NEXT:    lfd 27, 424(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F27(VSR27)
 ; CHECK-NEXT:    mtcrf 32, 12 # cr2
 ; CHECK-NEXT:    lwz 30, 416(1) # 4-byte Folded Reload
 ; CHECK-NEXT:    lwz 29, 412(1) # 4-byte Folded Reload
 ; CHECK-NEXT:    lwz 0, 468(1)
 ; CHECK-NEXT:    addi 1, 1, 464
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 entry:

llvm/test/CodeGen/PowerPC/CSR-fit.ll

 ; CHECK-PWR8-LABEL: caller2:
 ; CHECK-PWR8:       # %bb.0: # %entry
 ; CHECK-PWR8-NEXT:    mflr r0
 ; CHECK-PWR8-NEXT:    .cfi_def_cfa_offset 176
 ; CHECK-PWR8-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR8-NEXT:    .cfi_offset f14, -144
 ; CHECK-PWR8-NEXT:    .cfi_offset f15, -136
 ; CHECK-PWR8-NEXT:    stfd f14, -144(r1) # 8-byte Folded Spill
+; CHECK-PWR8-NEXT:    # Vec Uses: F14(VSR14)
 ; CHECK-PWR8-NEXT:    stfd f15, -136(r1) # 8-byte Folded Spill
+; CHECK-PWR8-NEXT:    # Vec Uses: F15(VSR15)
 ; CHECK-PWR8-NEXT:    std r0, 16(r1)
 ; CHECK-PWR8-NEXT:    stdu r1, -176(r1)
 ; CHECK-PWR8-NEXT:    #APP
 ; CHECK-PWR8-NEXT:    add r3, r3, r4
 ; CHECK-PWR8-NEXT:    #NO_APP
 ; CHECK-PWR8-NEXT:    extsw r3, r3
 ; CHECK-PWR8-NEXT:    bl callee
 ; CHECK-PWR8-NEXT:    nop
 ; CHECK-PWR8-NEXT:    addi r1, r1, 176
 ; CHECK-PWR8-NEXT:    ld r0, 16(r1)
 ; CHECK-PWR8-NEXT:    lfd f15, -136(r1) # 8-byte Folded Reload
+; CHECK-PWR8-NEXT:    # Vec Defs: F15(VSR15)
 ; CHECK-PWR8-NEXT:    lfd f14, -144(r1) # 8-byte Folded Reload
+; CHECK-PWR8-NEXT:    # Vec Defs: F14(VSR14)
 ; CHECK-PWR8-NEXT:    mtlr r0
 ; CHECK-PWR8-NEXT:    blr
 ;
 ; CHECK-PWR9-LABEL: caller2:
 ; CHECK-PWR9:       # %bb.0: # %entry
 ; CHECK-PWR9-NEXT:    mflr r0
 ; CHECK-PWR9-NEXT:    .cfi_def_cfa_offset 176
 ; CHECK-PWR9-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR9-NEXT:    .cfi_offset f14, -144
 ; CHECK-PWR9-NEXT:    .cfi_offset f15, -136
 ; CHECK-PWR9-NEXT:    stfd f14, -144(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F14(VSR14)
 ; CHECK-PWR9-NEXT:    stfd f15, -136(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F15(VSR15)
 ; CHECK-PWR9-NEXT:    std r0, 16(r1)
 ; CHECK-PWR9-NEXT:    stdu r1, -176(r1)
 ; CHECK-PWR9-NEXT:    #APP
 ; CHECK-PWR9-NEXT:    add r3, r3, r4
 ; CHECK-PWR9-NEXT:    #NO_APP
 ; CHECK-PWR9-NEXT:    extsw r3, r3
 ; CHECK-PWR9-NEXT:    bl callee
 ; CHECK-PWR9-NEXT:    nop
 ; CHECK-PWR9-NEXT:    addi r1, r1, 176
 ; CHECK-PWR9-NEXT:    ld r0, 16(r1)
 ; CHECK-PWR9-NEXT:    lfd f15, -136(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F15(VSR15)
 ; CHECK-PWR9-NEXT:    lfd f14, -144(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F14(VSR14)
 ; CHECK-PWR9-NEXT:    mtlr r0
 ; CHECK-PWR9-NEXT:    blr
 entry:
   %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{f14},~{f15}"(i32 %a, i32 %b)
   %call = tail call signext i32 @callee(i32 signext %0)
   ret i32 %call
 }
 
 define dso_local signext i32 @caller3(i32 signext %a, i32 signext %b) local_unnamed_addr {
 ; CHECK-PWR8-LABEL: caller3:
 ; CHECK-PWR8:       # %bb.0: # %entry
 ; CHECK-PWR8-NEXT:    mflr r0
 ; CHECK-PWR8-NEXT:    std r0, 16(r1)
 ; CHECK-PWR8-NEXT:    stdu r1, -240(r1)
 ; CHECK-PWR8-NEXT:    .cfi_def_cfa_offset 240
 ; CHECK-PWR8-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR8-NEXT:    .cfi_offset v20, -192
 ; CHECK-PWR8-NEXT:    .cfi_offset v21, -176
 ; CHECK-PWR8-NEXT:    li r5, 48
 ; CHECK-PWR8-NEXT:    stvx v20, r1, r5 # 16-byte Folded Spill
+; CHECK-PWR8-NEXT:    # Vec Uses: V20(VSR52)
 ; CHECK-PWR8-NEXT:    li r5, 64
 ; CHECK-PWR8-NEXT:    stvx v21, r1, r5 # 16-byte Folded Spill
+; CHECK-PWR8-NEXT:    # Vec Uses: V21(VSR53)
 ; CHECK-PWR8-NEXT:    #APP
 ; CHECK-PWR8-NEXT:    add r3, r3, r4
 ; CHECK-PWR8-NEXT:    #NO_APP
 ; CHECK-PWR8-NEXT:    extsw r3, r3
 ; CHECK-PWR8-NEXT:    bl callee
 ; CHECK-PWR8-NEXT:    nop
 ; CHECK-PWR8-NEXT:    li r4, 64
 ; CHECK-PWR8-NEXT:    lvx v21, r1, r4 # 16-byte Folded Reload
+; CHECK-PWR8-NEXT:    # Vec Defs: V21(VSR53)
 ; CHECK-PWR8-NEXT:    li r4, 48
 ; CHECK-PWR8-NEXT:    lvx v20, r1, r4 # 16-byte Folded Reload
+; CHECK-PWR8-NEXT:    # Vec Defs: V20(VSR52)
 ; CHECK-PWR8-NEXT:    addi r1, r1, 240
 ; CHECK-PWR8-NEXT:    ld r0, 16(r1)
 ; CHECK-PWR8-NEXT:    mtlr r0
 ; CHECK-PWR8-NEXT:    blr
 ;
 ; CHECK-PWR9-LABEL: caller3:
 ; CHECK-PWR9:       # %bb.0: # %entry
 ; CHECK-PWR9-NEXT:    mflr r0
 ; CHECK-PWR9-NEXT:    std r0, 16(r1)
 ; CHECK-PWR9-NEXT:    stdu r1, -224(r1)
 ; CHECK-PWR9-NEXT:    .cfi_def_cfa_offset 224
 ; CHECK-PWR9-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR9-NEXT:    .cfi_offset v20, -192
 ; CHECK-PWR9-NEXT:    .cfi_offset v21, -176
 ; CHECK-PWR9-NEXT:    stxv v20, 32(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V20(VSR52)
 ; CHECK-PWR9-NEXT:    stxv v21, 48(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V21(VSR53)
 ; CHECK-PWR9-NEXT:    #APP
 ; CHECK-PWR9-NEXT:    add r3, r3, r4
 ; CHECK-PWR9-NEXT:    #NO_APP
 ; CHECK-PWR9-NEXT:    extsw r3, r3
 ; CHECK-PWR9-NEXT:    bl callee
 ; CHECK-PWR9-NEXT:    nop
 ; CHECK-PWR9-NEXT:    lxv v21, 48(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V21(VSR53)
 ; CHECK-PWR9-NEXT:    lxv v20, 32(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V20(VSR52)
 ; CHECK-PWR9-NEXT:    addi r1, r1, 224
 ; CHECK-PWR9-NEXT:    ld r0, 16(r1)
 ; CHECK-PWR9-NEXT:    mtlr r0
 ; CHECK-PWR9-NEXT:    blr
 entry:
   %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{v20},~{v21}"(i32 %a, i32 %b)
   %call = tail call signext i32 @callee(i32 signext %0)
   ret i32 %call
 }
 
 define dso_local signext i32 @caller4(i32 signext %a, i32 signext %b) local_unnamed_addr {
 ; CHECK-PWR8-LABEL: caller4:
 ; CHECK-PWR8:       # %bb.0: # %entry
 ; CHECK-PWR8-NEXT:    mflr r0
 ; CHECK-PWR8-NEXT:    std r0, 16(r1)
 ; CHECK-PWR8-NEXT:    stdu r1, -240(r1)
 ; CHECK-PWR8-NEXT:    .cfi_def_cfa_offset 240
 ; CHECK-PWR8-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR8-NEXT:    .cfi_offset v20, -192
 ; CHECK-PWR8-NEXT:    .cfi_offset v21, -176
 ; CHECK-PWR8-NEXT:    li r5, 48
 ; CHECK-PWR8-NEXT:    stvx v20, r1, r5 # 16-byte Folded Spill
+; CHECK-PWR8-NEXT:    # Vec Uses: V20(VSR52)
 ; CHECK-PWR8-NEXT:    li r5, 64
 ; CHECK-PWR8-NEXT:    stvx v21, r1, r5 # 16-byte Folded Spill
+; CHECK-PWR8-NEXT:    # Vec Uses: V21(VSR53)
 ; CHECK-PWR8-NEXT:    #APP
 ; CHECK-PWR8-NEXT:    add r3, r3, r4
 ; CHECK-PWR8-NEXT:    #NO_APP
 ; CHECK-PWR8-NEXT:    extsw r3, r3
 ; CHECK-PWR8-NEXT:    bl callee
 ; CHECK-PWR8-NEXT:    nop
 ; CHECK-PWR8-NEXT:    li r4, 64
 ; CHECK-PWR8-NEXT:    lvx v21, r1, r4 # 16-byte Folded Reload
+; CHECK-PWR8-NEXT:    # Vec Defs: V21(VSR53)
 ; CHECK-PWR8-NEXT:    li r4, 48
 ; CHECK-PWR8-NEXT:    lvx v20, r1, r4 # 16-byte Folded Reload
+; CHECK-PWR8-NEXT:    # Vec Defs: V20(VSR52)
 ; CHECK-PWR8-NEXT:    addi r1, r1, 240
 ; CHECK-PWR8-NEXT:    ld r0, 16(r1)
 ; CHECK-PWR8-NEXT:    mtlr r0
 ; CHECK-PWR8-NEXT:    blr
 ;
 ; CHECK-PWR9-LABEL: caller4:
 ; CHECK-PWR9:       # %bb.0: # %entry
 ; CHECK-PWR9-NEXT:    mflr r0
 ; CHECK-PWR9-NEXT:    std r0, 16(r1)
 ; CHECK-PWR9-NEXT:    stdu r1, -224(r1)
 ; CHECK-PWR9-NEXT:    .cfi_def_cfa_offset 224
 ; CHECK-PWR9-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR9-NEXT:    .cfi_offset v20, -192
 ; CHECK-PWR9-NEXT:    .cfi_offset v21, -176
 ; CHECK-PWR9-NEXT:    stxv v20, 32(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V20(VSR52)
 ; CHECK-PWR9-NEXT:    stxv v21, 48(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V21(VSR53)
 ; CHECK-PWR9-NEXT:    #APP
 ; CHECK-PWR9-NEXT:    add r3, r3, r4
 ; CHECK-PWR9-NEXT:    #NO_APP
 ; CHECK-PWR9-NEXT:    extsw r3, r3
 ; CHECK-PWR9-NEXT:    bl callee
 ; CHECK-PWR9-NEXT:    nop
 ; CHECK-PWR9-NEXT:    lxv v21, 48(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V21(VSR53)
 ; CHECK-PWR9-NEXT:    lxv v20, 32(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V20(VSR52)
 ; CHECK-PWR9-NEXT:    addi r1, r1, 224
 ; CHECK-PWR9-NEXT:    ld r0, 16(r1)
 ; CHECK-PWR9-NEXT:    mtlr r0
 ; CHECK-PWR9-NEXT:    blr
 entry:
   %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{vs52},~{vs53}"(i32 %a, i32 %b)
   %call = tail call signext i32 @callee(i32 signext %0)
   ret i32 %call

 ; CHECK-PWR8-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR8-NEXT:    .cfi_offset r14, -288
 ; CHECK-PWR8-NEXT:    .cfi_offset f14, -144
 ; CHECK-PWR8-NEXT:    .cfi_offset v20, -480
 ; CHECK-PWR8-NEXT:    .cfi_offset v21, -464
 ; CHECK-PWR8-NEXT:    li r5, 48
 ; CHECK-PWR8-NEXT:    std r14, 240(r1) # 8-byte Folded Spill
 ; CHECK-PWR8-NEXT:    stfd f14, 384(r1) # 8-byte Folded Spill
+; CHECK-PWR8-NEXT:    # Vec Uses: F14(VSR14)
 ; CHECK-PWR8-NEXT:    stvx v20, r1, r5 # 16-byte Folded Spill
+; CHECK-PWR8-NEXT:    # Vec Uses: V20(VSR52)
 ; CHECK-PWR8-NEXT:    li r5, 64
 ; CHECK-PWR8-NEXT:    stvx v21, r1, r5 # 16-byte Folded Spill
+; CHECK-PWR8-NEXT:    # Vec Uses: V21(VSR53)
 ; CHECK-PWR8-NEXT:    #APP
 ; CHECK-PWR8-NEXT:    add r3, r3, r4
 ; CHECK-PWR8-NEXT:    #NO_APP
 ; CHECK-PWR8-NEXT:    extsw r3, r3
 ; CHECK-PWR8-NEXT:    bl callee
 ; CHECK-PWR8-NEXT:    nop
 ; CHECK-PWR8-NEXT:    li r4, 64
 ; CHECK-PWR8-NEXT:    lfd f14, 384(r1) # 8-byte Folded Reload
+; CHECK-PWR8-NEXT:    # Vec Defs: F14(VSR14)
 ; CHECK-PWR8-NEXT:    ld r14, 240(r1) # 8-byte Folded Reload
 ; CHECK-PWR8-NEXT:    lvx v21, r1, r4 # 16-byte Folded Reload
+; CHECK-PWR8-NEXT:    # Vec Defs: V21(VSR53)
 ; CHECK-PWR8-NEXT:    li r4, 48
 ; CHECK-PWR8-NEXT:    lvx v20, r1, r4 # 16-byte Folded Reload
+; CHECK-PWR8-NEXT:    # Vec Defs: V20(VSR52)
 ; CHECK-PWR8-NEXT:    addi r1, r1, 528
 ; CHECK-PWR8-NEXT:    ld r0, 16(r1)
 ; CHECK-PWR8-NEXT:    mtlr r0
 ; CHECK-PWR8-NEXT:    blr
 ;
 ; CHECK-PWR9-LABEL: caller_mixed:
 ; CHECK-PWR9:       # %bb.0: # %entry
 ; CHECK-PWR9-NEXT:    mflr r0
 ; CHECK-PWR9-NEXT:    std r0, 16(r1)
 ; CHECK-PWR9-NEXT:    stdu r1, -512(r1)
 ; CHECK-PWR9-NEXT:    .cfi_def_cfa_offset 512
 ; CHECK-PWR9-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR9-NEXT:    .cfi_offset r14, -288
 ; CHECK-PWR9-NEXT:    .cfi_offset f14, -144
 ; CHECK-PWR9-NEXT:    .cfi_offset v20, -480
 ; CHECK-PWR9-NEXT:    .cfi_offset v21, -464
 ; CHECK-PWR9-NEXT:    std r14, 224(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    stfd f14, 368(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F14(VSR14)
 ; CHECK-PWR9-NEXT:    stxv v20, 32(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V20(VSR52)
 ; CHECK-PWR9-NEXT:    stxv v21, 48(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V21(VSR53)
 ; CHECK-PWR9-NEXT:    #APP
 ; CHECK-PWR9-NEXT:    add r3, r3, r4
 ; CHECK-PWR9-NEXT:    #NO_APP
 ; CHECK-PWR9-NEXT:    extsw r3, r3
 ; CHECK-PWR9-NEXT:    bl callee
 ; CHECK-PWR9-NEXT:    nop
 ; CHECK-PWR9-NEXT:    lxv v21, 48(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V21(VSR53)
 ; CHECK-PWR9-NEXT:    lxv v20, 32(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V20(VSR52)
 ; CHECK-PWR9-NEXT:    lfd f14, 368(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F14(VSR14)
 ; CHECK-PWR9-NEXT:    ld r14, 224(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    addi r1, r1, 512
 ; CHECK-PWR9-NEXT:    ld r0, 16(r1)
 ; CHECK-PWR9-NEXT:    mtlr r0
 ; CHECK-PWR9-NEXT:    blr
 entry:
   %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{f14},~{v20},~{vs53}"(i32 %a, i32 %b)
   %call = tail call signext i32 @callee(i32 signext %0)
   ret i32 %call
 }
 
 

llvm/test/CodeGen/PowerPC/aix-framepointer-save-restore.ll

 ; AIX32:       # %bb.0: # %entry
 ; AIX32-NEXT:    mflr 0
 ; AIX32-NEXT:    stw 31, -12(1)
 ; AIX32-NEXT:    stw 0, 8(1)
 ; AIX32-NEXT:    stwu 1, -80(1)
 ; AIX32-NEXT:    slwi 3, 3, 2
 ; AIX32-NEXT:    mr 31, 1
 ; AIX32-NEXT:    stfd 31, 72(31) # 8-byte Folded Spill
-; AIX32-NEXT:    fmr 31, 1
+; AIX32-NEXT:    # Vec Uses: F31(VSR31)
+; AIX32-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
 ; AIX32-NEXT:    addi 3, 3, 15
 ; AIX32-NEXT:    addi 4, 31, 80
 ; AIX32-NEXT:    rlwinm 3, 3, 0, 0, 27
 ; AIX32-NEXT:    neg 3, 3
 ; AIX32-NEXT:    stwux 4, 1, 3
 ; AIX32-NEXT:    addi 3, 1, 64
 ; AIX32-NEXT:    bl .clobber[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    fmr 1, 31
+; AIX32-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; AIX32-NEXT:    lfd 31, 72(31) # 8-byte Folded Reload
+; AIX32-NEXT:    # Vec Defs: F31(VSR31)
 ; AIX32-NEXT:    lwz 1, 0(1)
 ; AIX32-NEXT:    lwz 0, 8(1)
 ; AIX32-NEXT:    mtlr 0
 ; AIX32-NEXT:    lwz 31, -12(1)
 ; AIX32-NEXT:    blr
 ;
 ; AIX64-LABEL: frameptr_only:
 ; AIX64:       # %bb.0: # %entry
 ; AIX64-NEXT:    mflr 0
 ; AIX64-NEXT:    std 31, -16(1)
 ; AIX64-NEXT:    std 0, 16(1)
 ; AIX64-NEXT:    stdu 1, -144(1)
 ; AIX64-NEXT:    rldic 3, 3, 2, 30
 ; AIX64-NEXT:    mr 31, 1
 ; AIX64-NEXT:    stfd 31, 136(31) # 8-byte Folded Spill
-; AIX64-NEXT:    fmr 31, 1
+; AIX64-NEXT:    # Vec Uses: F31(VSR31)
+; AIX64-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
 ; AIX64-NEXT:    addi 3, 3, 15
 ; AIX64-NEXT:    addi 4, 31, 144
 ; AIX64-NEXT:    rldicl 3, 3, 60, 4
 ; AIX64-NEXT:    rldicl 3, 3, 4, 29
 ; AIX64-NEXT:    neg 3, 3
 ; AIX64-NEXT:    stdux 4, 1, 3
 ; AIX64-NEXT:    addi 3, 1, 112
 ; AIX64-NEXT:    bl .clobber[PR]
 ; AIX64-NEXT:    nop
-; AIX64-NEXT:    fmr 1, 31
+; AIX64-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; AIX64-NEXT:    lfd 31, 136(31) # 8-byte Folded Reload
+; AIX64-NEXT:    # Vec Defs: F31(VSR31)
 ; AIX64-NEXT:    ld 1, 0(1)
 ; AIX64-NEXT:    ld 0, 16(1)
 ; AIX64-NEXT:    mtlr 0
 ; AIX64-NEXT:    ld 31, -16(1)
 ; AIX64-NEXT:    blr
 entry:
   %0 = alloca i32, i32 %n
   call void @clobber(i32* %0)

llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \
 ; RUN:   -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK-64,CHECK-64-OPT %s
 ; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \
 ; RUN:   -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK-64,CHECK-64-O0 %s
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc-ibm-aix-xcoff \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-32,CHECK-32-OPT
 ; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc-ibm-aix-xcoff \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-32,CHECK-32-O0
 
 ; The following testcases take one halfword element from the second vector and
 ; inserts it at various locations in the first vector
 define <8 x i16> @shuffle_vector_halfword_0_8(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_0_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-64-NEXT:    vinserth 2, 3, 0
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinserth 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_0_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-32-NEXT:    vinserth 2, 3, 0
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinserth 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_1_15(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_1_15:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-64-NEXT:    vinserth 2, 3, 2
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinserth 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_1_15:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-32-NEXT:    vinserth 2, 3, 2
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinserth 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 15, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_2_9(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_2_9:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-64-NEXT:    vinserth 2, 3, 4
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinserth 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_2_9:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-32-NEXT:    vinserth 2, 3, 4
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinserth 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 9, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_3_13(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_3_13:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-64-NEXT:    vinserth 2, 3, 6
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinserth 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_3_13:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-32-NEXT:    vinserth 2, 3, 6
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinserth 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_4_10(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_4_10:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-64-NEXT:    vinserth 2, 3, 8
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinserth 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_4_10:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-32-NEXT:    vinserth 2, 3, 8
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinserth 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_5_14(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_5_14:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-64-NEXT:    vinserth 2, 3, 10
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinserth 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_5_14:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-32-NEXT:    vinserth 2, 3, 10
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinserth 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 14, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_6_11(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_6_11:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vinserth 2, 3, 12
+; CHECK-64-NEXT:    vinserth 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_6_11:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vinserth 2, 3, 12
+; CHECK-32-NEXT:    vinserth 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 11, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_7_12(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_7_12:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-64-NEXT:    vinserth 2, 3, 14
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinserth 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_7_12:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-32-NEXT:    vinserth 2, 3, 14
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinserth 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 12>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_8_1(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_halfword_8_1:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 12
-; CHECK-64-OPT-NEXT:    vinserth 3, 2, 0
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinserth 3, 2, 0 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_halfword_8_1:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-64-O0-NEXT:    vinserth 2, 3, 0
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinserth 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_halfword_8_1:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 12
-; CHECK-32-OPT-NEXT:    vinserth 3, 2, 0
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinserth 3, 2, 0 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_halfword_8_1:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-32-O0-NEXT:    vinserth 2, 3, 0
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinserth 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
 
 ; The following testcases take one halfword element from the first vector and
 ; inserts it at various locations in the second vector
 define <8 x i16> @shuffle_vector_halfword_9_7(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_halfword_9_7:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 8
-; CHECK-64-OPT-NEXT:    vinserth 3, 2, 2
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinserth 3, 2, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_halfword_9_7:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-64-O0-NEXT:    vinserth 2, 3, 2
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinserth 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_halfword_9_7:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 8
-; CHECK-32-OPT-NEXT:    vinserth 3, 2, 2
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinserth 3, 2, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_halfword_9_7:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-32-O0-NEXT:    vinserth 2, 3, 2
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinserth 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_10_4(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_halfword_10_4:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 2
-; CHECK-64-OPT-NEXT:    vinserth 3, 2, 4
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinserth 3, 2, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_halfword_10_4:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-64-O0-NEXT:    vinserth 2, 3, 4
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinserth 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_halfword_10_4:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 2
-; CHECK-32-OPT-NEXT:    vinserth 3, 2, 4
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinserth 3, 2, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_halfword_10_4:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-32-O0-NEXT:    vinserth 2, 3, 4
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinserth 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 4, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_11_2(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_halfword_11_2:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 14
-; CHECK-64-OPT-NEXT:    vinserth 3, 2, 6
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinserth 3, 2, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_halfword_11_2:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-64-O0-NEXT:    vinserth 2, 3, 6
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinserth 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_halfword_11_2:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 14
-; CHECK-32-OPT-NEXT:    vinserth 3, 2, 6
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinserth 3, 2, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_halfword_11_2:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-32-O0-NEXT:    vinserth 2, 3, 6
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinserth 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 2, i32 12, i32 13, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_12_6(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_halfword_12_6:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 6
-; CHECK-64-OPT-NEXT:    vinserth 3, 2, 8
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinserth 3, 2, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_halfword_12_6:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-64-O0-NEXT:    vinserth 2, 3, 8
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinserth 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_halfword_12_6:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 6
-; CHECK-32-OPT-NEXT:    vinserth 3, 2, 8
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinserth 3, 2, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_halfword_12_6:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-32-O0-NEXT:    vinserth 2, 3, 8
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinserth 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 6, i32 13, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_13_3(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_halfword_13_3:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vinserth 3, 2, 10
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vinserth 3, 2, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_halfword_13_3:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vinserth 2, 3, 10
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vinserth 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_halfword_13_3:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vinserth 3, 2, 10
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vinserth 3, 2, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_halfword_13_3:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vinserth 2, 3, 10
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vinserth 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 3, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_14_5(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_halfword_14_5:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 4
-; CHECK-64-OPT-NEXT:    vinserth 3, 2, 12
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinserth 3, 2, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_halfword_14_5:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-64-O0-NEXT:    vinserth 2, 3, 12
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinserth 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_halfword_14_5:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 4
-; CHECK-32-OPT-NEXT:    vinserth 3, 2, 12
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinserth 3, 2, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_halfword_14_5:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-32-O0-NEXT:    vinserth 2, 3, 12
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinserth 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 5, i32 15>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_15_0(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_halfword_15_0:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 10
-; CHECK-64-OPT-NEXT:    vinserth 3, 2, 14
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinserth 3, 2, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_halfword_15_0:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-64-O0-NEXT:    vinserth 2, 3, 14
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinserth 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_halfword_15_0:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 10
-; CHECK-32-OPT-NEXT:    vinserth 3, 2, 14
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinserth 3, 2, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_halfword_15_0:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-32-O0-NEXT:    vinserth 2, 3, 14
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinserth 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>
   ret <8 x i16> %vecins
 }
 
 ; The following testcases use the same vector in both arguments of the
 ; shufflevector.  If halfword element 3 in BE mode(or 4 in LE mode) is the one
 ; we're attempting to insert, then we can use the vector insert instruction
 define <8 x i16> @shuffle_vector_halfword_0_4(<8 x i16> %a) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_0_4:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C0(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C0(2) # %const.0
+; CHECK-64-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-64-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_0_4:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C0(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C0(2) # %const.0
+; CHECK-32-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-32-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_1_3:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vinserth 2, 2, 2
+; CHECK-64-NEXT:    vinserth 2, 2, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_1_3:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vinserth 2, 2, 2
+; CHECK-32-NEXT:    vinserth 2, 2, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_2_3:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vinserth 2, 2, 4
+; CHECK-64-NEXT:    vinserth 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_2_3:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vinserth 2, 2, 4
+; CHECK-32-NEXT:    vinserth 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_3_4:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C1(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C1(2) # %const.0
+; CHECK-64-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-64-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_3_4:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C1(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C1(2) # %const.0
+; CHECK-32-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-32-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_4_3:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vinserth 2, 2, 8
+; CHECK-64-NEXT:    vinserth 2, 2, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_4_3:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vinserth 2, 2, 8
+; CHECK-32-NEXT:    vinserth 2, 2, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_5_3:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vinserth 2, 2, 10
+; CHECK-64-NEXT:    vinserth 2, 2, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_5_3:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vinserth 2, 2, 10
+; CHECK-32-NEXT:    vinserth 2, 2, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_6_4:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C2(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C2(2) # %const.0
+; CHECK-64-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-64-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_6_4:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C2(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C2(2) # %const.0
+; CHECK-32-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-32-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) {
 ; CHECK-64-LABEL: shuffle_vector_halfword_7_4:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C3(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C3(2) # %const.0
+; CHECK-64-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-64-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_7_4:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C3(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C3(2) # %const.0
+; CHECK-32-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-32-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4>
   ret <8 x i16> %vecins
 }
 
 ; The following testcases take one byte element from the second vector and
 ; inserts it at various locations in the first vector
 define <16 x i8> @shuffle_vector_byte_0_16(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-LABEL: shuffle_vector_byte_0_16:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 9
-; CHECK-64-NEXT:    vinsertb 2, 3, 0
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 9 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinsertb 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_0_16:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 9
-; CHECK-32-NEXT:    vinsertb 2, 3, 0
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 9 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinsertb 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_1_25(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-LABEL: shuffle_vector_byte_1_25:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-64-NEXT:    vinsertb 2, 3, 1
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinsertb 2, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_1_25:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-32-NEXT:    vinsertb 2, 3, 1
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinsertb 2, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 25, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_2_18(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-LABEL: shuffle_vector_byte_2_18:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 11
-; CHECK-64-NEXT:    vinsertb 2, 3, 2
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 11 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinsertb 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_2_18:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 11
-; CHECK-32-NEXT:    vinsertb 2, 3, 2
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 11 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinsertb 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 18, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_3_27(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-LABEL: shuffle_vector_byte_3_27:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-64-NEXT:    vinsertb 2, 3, 3
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinsertb 2, 3, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_3_27:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-32-NEXT:    vinsertb 2, 3, 3
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinsertb 2, 3, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 27, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_4_20(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-LABEL: shuffle_vector_byte_4_20:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 13
-; CHECK-64-NEXT:    vinsertb 2, 3, 4
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 13 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinsertb 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_4_20:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 13
-; CHECK-32-NEXT:    vinsertb 2, 3, 4
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 13 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinsertb 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_5_29(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-LABEL: shuffle_vector_byte_5_29:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-64-NEXT:    vinsertb 2, 3, 5
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinsertb 2, 3, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_5_29:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-32-NEXT:    vinsertb 2, 3, 5
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinsertb 2, 3, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 29, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_6_22(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-LABEL: shuffle_vector_byte_6_22:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 15
-; CHECK-64-NEXT:    vinsertb 2, 3, 6
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 15 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinsertb 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_6_22:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 15
-; CHECK-32-NEXT:    vinsertb 2, 3, 6
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 15 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinsertb 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 22, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_7_31(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-LABEL: shuffle_vector_byte_7_31:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-64-NEXT:    vinsertb 2, 3, 7
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinsertb 2, 3, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_7_31:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-32-NEXT:    vinsertb 2, 3, 7
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinsertb 2, 3, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 31, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_8_24(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-LABEL: shuffle_vector_byte_8_24:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 1
-; CHECK-64-NEXT:    vinsertb 2, 3, 8
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 1 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinsertb 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_8_24:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 1
-; CHECK-32-NEXT:    vinsertb 2, 3, 8
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 1 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinsertb 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_9_17(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-LABEL: shuffle_vector_byte_9_17:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-64-NEXT:    vinsertb 2, 3, 9
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinsertb 2, 3, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_9_17:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-32-NEXT:    vinsertb 2, 3, 9
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinsertb 2, 3, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 17, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_10_26(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-LABEL: shuffle_vector_byte_10_26:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 3
-; CHECK-64-NEXT:    vinsertb 2, 3, 10
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 3 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinsertb 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_10_26:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 3
-; CHECK-32-NEXT:    vinsertb 2, 3, 10
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 3 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinsertb 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 26, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_11_19(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-LABEL: shuffle_vector_byte_11_19:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-64-NEXT:    vinsertb 2, 3, 11
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinsertb 2, 3, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_11_19:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-32-NEXT:    vinsertb 2, 3, 11
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinsertb 2, 3, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 19, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_12_28(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-LABEL: shuffle_vector_byte_12_28:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 5
-; CHECK-64-NEXT:    vinsertb 2, 3, 12
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 5 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinsertb 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_12_28:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 5
-; CHECK-32-NEXT:    vinsertb 2, 3, 12
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 5 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinsertb 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 28, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_13_21(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-LABEL: shuffle_vector_byte_13_21:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-64-NEXT:    vinsertb 2, 3, 13
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinsertb 2, 3, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_13_21:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-32-NEXT:    vinsertb 2, 3, 13
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinsertb 2, 3, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 21, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_14_30(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-LABEL: shuffle_vector_byte_14_30:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vsldoi 3, 3, 3, 7
-; CHECK-64-NEXT:    vinsertb 2, 3, 14
+; CHECK-64-NEXT:    vsldoi 3, 3, 3, 7 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-NEXT:    vinsertb 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_14_30:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vsldoi 3, 3, 3, 7
-; CHECK-32-NEXT:    vinsertb 2, 3, 14
+; CHECK-32-NEXT:    vsldoi 3, 3, 3, 7 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-NEXT:    vinsertb 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 30, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_15_23(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-LABEL: shuffle_vector_byte_15_23:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vinsertb 2, 3, 15
+; CHECK-64-NEXT:    vinsertb 2, 3, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_15_23:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vinsertb 2, 3, 15
+; CHECK-32-NEXT:    vinsertb 2, 3, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 23>
   ret <16 x i8> %vecins
 }
 
 ; The following testcases take one byte element from the first vector and
 ; inserts it at various locations in the second vector
 define <16 x i8> @shuffle_vector_byte_16_8(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_16_8:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 1
-; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 0
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 0 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_byte_16_8:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 1
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 0
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 1 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_16_8:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 1
-; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 0
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 0 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_byte_16_8:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 1
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 0
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 1 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_17_1(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_17_1:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 10
-; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 1
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 1 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_byte_17_1:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 1
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_17_1:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 10
-; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 1
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 1 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_byte_17_1:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 1
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_18_10(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_18_10:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 3
-; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 2
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_byte_18_10:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 3
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 2
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 3 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_18_10:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 3
-; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 2
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_byte_18_10:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 3
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 2
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 3 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 10, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_19_3(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_19_3:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 12
-; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 3
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 3 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_byte_19_3:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 3
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_19_3:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 12
-; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 3
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 3 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_byte_19_3:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 3
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_20_12(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_20_12:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 5
-; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 4
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_byte_20_12:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 5
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 4
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 5 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_20_12:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 5
-; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 4
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_byte_20_12:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 5
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 4
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 5 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 12, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_21_5(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_21_5:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 14
-; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 5
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 5 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_byte_21_5:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 5
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_21_5:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 14
-; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 5
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 5 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_byte_21_5:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 5
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 5, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_22_14(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_22_14:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 7
-; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 6
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_byte_22_14:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 7
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 6
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 7 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_22_14:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 7
-; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 6
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_byte_22_14:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 7
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 6
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 7 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 14, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_23_7(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_23_7:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 7
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 7 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_byte_23_7:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 7
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_23_7:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 7
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 7 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_byte_23_7:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 7
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_24_0(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_24_0:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 9
-; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 8
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_byte_24_0:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 9
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 8
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 9 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_24_0:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 9
-; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 8
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_byte_24_0:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 9
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 8
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 9 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 0, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_25_9(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_25_9:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 2
-; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 9
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 9 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_byte_25_9:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 9
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_25_9:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 2
-; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 9
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 9 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_byte_25_9:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 9
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 9, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_26_2(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_26_2:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 11
-; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 10
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_byte_26_2:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 11
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 10
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 11 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_26_2:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 11
-; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 10
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_byte_26_2:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 11
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 10
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 11 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 2, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_27_11(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_27_11:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 4
-; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 11
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 11 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_byte_27_11:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 11
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_27_11:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 4
-; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 11
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 11 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_byte_27_11:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 11
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 11, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_28_4(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_28_4:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 13
-; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 12
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_byte_28_4:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 13
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 12
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 13 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_28_4:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 13
-; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 12
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_byte_28_4:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 13
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 12
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 13 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 4, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_29_13(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_29_13:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 6
-; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 13
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 13 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_byte_29_13:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 13
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_29_13:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 6
-; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 13
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 13 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_byte_29_13:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 13
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 13, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_30_6(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_30_6:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 15
-; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 14
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_byte_30_6:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 15
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 14
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 15 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_30_6:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 15
-; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 14
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_byte_30_6:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 15
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 14
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 15 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 6, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_31_15(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_31_15:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 8
-; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 15
-; CHECK-64-OPT-NEXT:    vmr 2, 3
+; CHECK-64-OPT-NEXT:    vsldoi 2, 2, 2, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vinsertb 3, 2, 15 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-64-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: shuffle_vector_byte_31_15:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-64-O0-NEXT:    vmr 3, 2
+; CHECK-64-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-64-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 15
+; CHECK-64-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-64-O0-NEXT:    vsldoi 3, 3, 3, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_31_15:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 8
-; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 15
-; CHECK-32-OPT-NEXT:    vmr 2, 3
+; CHECK-32-OPT-NEXT:    vsldoi 2, 2, 2, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vinsertb 3, 2, 15 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-32-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: shuffle_vector_byte_31_15:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-32-O0-NEXT:    vmr 3, 2
+; CHECK-32-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-32-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 15
+; CHECK-32-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-32-O0-NEXT:    vsldoi 3, 3, 3, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 15>
   ret <16 x i8> %vecins
 }
 
 ; The following testcases use the same vector in both arguments of the
 ; shufflevector.  If byte element 7 in BE mode(or 8 in LE mode) is the one
 ; we're attempting to insert, then we can use the vector insert instruction
 define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_0_7:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vinsertb 2, 2, 0
+; CHECK-64-NEXT:    vinsertb 2, 2, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_0_7:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vinsertb 2, 2, 0
+; CHECK-32-NEXT:    vinsertb 2, 2, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_1_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C4(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C4(2) # %const.0
+; CHECK-64-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-64-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_1_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C4(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C4(2) # %const.0
+; CHECK-32-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-32-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_2_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C5(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C5(2) # %const.0
+; CHECK-64-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-64-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_2_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C5(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C5(2) # %const.0
+; CHECK-32-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-32-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_3_7:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vinsertb 2, 2, 3
+; CHECK-64-NEXT:    vinsertb 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_3_7:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vinsertb 2, 2, 3
+; CHECK-32-NEXT:    vinsertb 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_4_7:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vinsertb 2, 2, 4
+; CHECK-64-NEXT:    vinsertb 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_4_7:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vinsertb 2, 2, 4
+; CHECK-32-NEXT:    vinsertb 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_5_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C6(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C6(2) # %const.0
+; CHECK-64-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-64-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_5_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C6(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C6(2) # %const.0
+; CHECK-32-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-32-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_6_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C7(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C7(2) # %const.0
+; CHECK-64-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-64-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_6_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C7(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C7(2) # %const.0
+; CHECK-32-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-32-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_7_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C8(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C8(2) # %const.0
+; CHECK-64-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-64-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_7_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C8(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C8(2) # %const.0
+; CHECK-32-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-32-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_8_7:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vinsertb 2, 2, 8
+; CHECK-64-NEXT:    vinsertb 2, 2, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_8_7:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vinsertb 2, 2, 8
+; CHECK-32-NEXT:    vinsertb 2, 2, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_9_7:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vinsertb 2, 2, 9
+; CHECK-64-NEXT:    vinsertb 2, 2, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_9_7:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vinsertb 2, 2, 9
+; CHECK-32-NEXT:    vinsertb 2, 2, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_10_7:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vinsertb 2, 2, 10
+; CHECK-64-NEXT:    vinsertb 2, 2, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_10_7:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vinsertb 2, 2, 10
+; CHECK-32-NEXT:    vinsertb 2, 2, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_11_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C9(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C9(2) # %const.0
+; CHECK-64-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-64-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_11_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C9(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C9(2) # %const.0
+; CHECK-32-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-32-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_12_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C10(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C10(2) # %const.0
+; CHECK-64-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-64-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_12_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C10(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C10(2) # %const.0
+; CHECK-32-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-32-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_13_7:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vinsertb 2, 2, 13
+; CHECK-64-NEXT:    vinsertb 2, 2, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_13_7:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vinsertb 2, 2, 13
+; CHECK-32-NEXT:    vinsertb 2, 2, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 7, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_14_7:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    vinsertb 2, 2, 14
+; CHECK-64-NEXT:    vinsertb 2, 2, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_14_7:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    vinsertb 2, 2, 14
+; CHECK-32-NEXT:    vinsertb 2, 2, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) {
 ; CHECK-64-LABEL: shuffle_vector_byte_15_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C11(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C11(2) # %const.0
+; CHECK-64-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-64-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_15_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C11(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C11(2) # %const.0
+; CHECK-32-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-32-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8>
   ret <16 x i8> %vecins
 }
 
 ; The following tests try to insert one halfword element into the vector.  We
 ; should always be using the 'vinserth' instruction.
 define <8 x i16> @insert_halfword_0(<8 x i16> %a, i16 %b) {
 ; CHECK-64-OPT-LABEL: insert_halfword_0:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinserth 2, 3, 0
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinserth 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_halfword_0:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinserth 2, 3, 0
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinserth 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_halfword_0:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinserth 2, 3, 0
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinserth 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_halfword_0:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinserth 2, 3, 0
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinserth 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <8 x i16> %a, i16 %b, i32 0
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @insert_halfword_1(<8 x i16> %a, i16 %b) {
 ; CHECK-64-OPT-LABEL: insert_halfword_1:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinserth 2, 3, 2
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinserth 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_halfword_1:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinserth 2, 3, 2
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinserth 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_halfword_1:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinserth 2, 3, 2
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinserth 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_halfword_1:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinserth 2, 3, 2
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinserth 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <8 x i16> %a, i16 %b, i32 1
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @insert_halfword_2(<8 x i16> %a, i16 %b) {
 ; CHECK-64-OPT-LABEL: insert_halfword_2:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinserth 2, 3, 4
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinserth 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_halfword_2:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinserth 2, 3, 4
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinserth 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_halfword_2:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinserth 2, 3, 4
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinserth 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_halfword_2:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinserth 2, 3, 4
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinserth 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <8 x i16> %a, i16 %b, i32 2
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @insert_halfword_3(<8 x i16> %a, i16 %b) {
 ; CHECK-64-OPT-LABEL: insert_halfword_3:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinserth 2, 3, 6
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinserth 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_halfword_3:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinserth 2, 3, 6
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinserth 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_halfword_3:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinserth 2, 3, 6
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinserth 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_halfword_3:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinserth 2, 3, 6
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinserth 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <8 x i16> %a, i16 %b, i32 3
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @insert_halfword_4(<8 x i16> %a, i16 %b) {
 ; CHECK-64-OPT-LABEL: insert_halfword_4:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinserth 2, 3, 8
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinserth 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_halfword_4:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinserth 2, 3, 8
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinserth 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_halfword_4:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinserth 2, 3, 8
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinserth 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_halfword_4:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinserth 2, 3, 8
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinserth 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <8 x i16> %a, i16 %b, i32 4
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @insert_halfword_5(<8 x i16> %a, i16 %b) {
 ; CHECK-64-OPT-LABEL: insert_halfword_5:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinserth 2, 3, 10
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinserth 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_halfword_5:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinserth 2, 3, 10
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinserth 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_halfword_5:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinserth 2, 3, 10
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinserth 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_halfword_5:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinserth 2, 3, 10
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinserth 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <8 x i16> %a, i16 %b, i32 5
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @insert_halfword_6(<8 x i16> %a, i16 %b) {
 ; CHECK-64-OPT-LABEL: insert_halfword_6:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinserth 2, 3, 12
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinserth 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_halfword_6:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinserth 2, 3, 12
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinserth 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_halfword_6:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinserth 2, 3, 12
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinserth 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_halfword_6:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinserth 2, 3, 12
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinserth 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <8 x i16> %a, i16 %b, i32 6
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @insert_halfword_7(<8 x i16> %a, i16 %b) {
 ; CHECK-64-OPT-LABEL: insert_halfword_7:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinserth 2, 3, 14
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinserth 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_halfword_7:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinserth 2, 3, 14
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinserth 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_halfword_7:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinserth 2, 3, 14
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinserth 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_halfword_7:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinserth 2, 3, 14
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinserth 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <8 x i16> %a, i16 %b, i32 7
   ret <8 x i16> %vecins
 }
 
 ; The following tests try to insert one byte element into the vector.  We
 ; should always be using the 'vinsertb' instruction.
 define <16 x i8> @insert_byte_0(<16 x i8> %a, i8 %b) {
 ; CHECK-64-OPT-LABEL: insert_byte_0:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 0
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_byte_0:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 0
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_byte_0:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 0
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_byte_0:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 0
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 0
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_1(<16 x i8> %a, i8 %b) {
 ; CHECK-64-OPT-LABEL: insert_byte_1:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 1
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_byte_1:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 1
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_byte_1:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 1
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_byte_1:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 1
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 1
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_2(<16 x i8> %a, i8 %b) {
 ; CHECK-64-OPT-LABEL: insert_byte_2:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 2
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_byte_2:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 2
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_byte_2:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 2
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_byte_2:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 2
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 2
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_3(<16 x i8> %a, i8 %b) {
 ; CHECK-64-OPT-LABEL: insert_byte_3:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 3
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_byte_3:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 3
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_byte_3:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 3
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_byte_3:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 3
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 3
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_4(<16 x i8> %a, i8 %b) {
 ; CHECK-64-OPT-LABEL: insert_byte_4:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 4
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_byte_4:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 4
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_byte_4:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 4
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_byte_4:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 4
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 4
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_5(<16 x i8> %a, i8 %b) {
 ; CHECK-64-OPT-LABEL: insert_byte_5:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 5
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_byte_5:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 5
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_byte_5:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 5
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_byte_5:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 5
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 5
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_6(<16 x i8> %a, i8 %b) {
 ; CHECK-64-OPT-LABEL: insert_byte_6:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 6
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_byte_6:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 6
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_byte_6:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 6
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_byte_6:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 6
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 6
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_7(<16 x i8> %a, i8 %b) {
 ; CHECK-64-OPT-LABEL: insert_byte_7:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 7
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_byte_7:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 7
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_byte_7:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 7
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_byte_7:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 7
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 7
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_8(<16 x i8> %a, i8 %b) {
 ; CHECK-64-OPT-LABEL: insert_byte_8:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 8
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_byte_8:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 8
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_byte_8:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 8
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_byte_8:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 8
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 8
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_9(<16 x i8> %a, i8 %b) {
 ; CHECK-64-OPT-LABEL: insert_byte_9:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 9
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_byte_9:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 9
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_byte_9:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 9
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_byte_9:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 9
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 9
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_10(<16 x i8> %a, i8 %b) {
 ; CHECK-64-OPT-LABEL: insert_byte_10:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 10
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_byte_10:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 10
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_byte_10:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 10
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_byte_10:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 10
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 10
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_11(<16 x i8> %a, i8 %b) {
 ; CHECK-64-OPT-LABEL: insert_byte_11:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 11
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_byte_11:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 11
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_byte_11:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 11
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_byte_11:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 11
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 11
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_12(<16 x i8> %a, i8 %b) {
 ; CHECK-64-OPT-LABEL: insert_byte_12:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 12
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_byte_12:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 12
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_byte_12:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 12
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_byte_12:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 12
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 12
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_13(<16 x i8> %a, i8 %b) {
 ; CHECK-64-OPT-LABEL: insert_byte_13:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 13
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_byte_13:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 13
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_byte_13:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 13
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_byte_13:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 13
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 13
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_14(<16 x i8> %a, i8 %b) {
 ; CHECK-64-OPT-LABEL: insert_byte_14:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 14
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_byte_14:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 14
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_byte_14:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 14
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_byte_14:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 14
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 14
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_15(<16 x i8> %a, i8 %b) {
 ; CHECK-64-OPT-LABEL: insert_byte_15:
 ; CHECK-64-OPT:       # %bb.0: # %entry
-; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 15
+; CHECK-64-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-64-OPT-NEXT:    vinsertb 2, 3, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-OPT-NEXT:    blr
 ;
 ; CHECK-64-O0-LABEL: insert_byte_15:
 ; CHECK-64-O0:       # %bb.0: # %entry
 ; CHECK-64-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
-; CHECK-64-O0-NEXT:    mtfprwz 0, 3
-; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-64-O0-NEXT:    vinsertb 2, 3, 15
+; CHECK-64-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-64-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-64-O0-NEXT:    vinsertb 2, 3, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-64-O0-NEXT:    blr
 ;
 ; CHECK-32-OPT-LABEL: insert_byte_15:
 ; CHECK-32-OPT:       # %bb.0: # %entry
-; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3
-; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 15
+; CHECK-32-OPT-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; CHECK-32-OPT-NEXT:    vinsertb 2, 3, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-OPT-NEXT:    blr
 ;
 ; CHECK-32-O0-LABEL: insert_byte_15:
 ; CHECK-32-O0:       # %bb.0: # %entry
 ; CHECK-32-O0-NEXT:    # kill: def $r4 killed $r3
-; CHECK-32-O0-NEXT:    mtfprwz 0, 3
-; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-32-O0-NEXT:    vinsertb 2, 3, 15
+; CHECK-32-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-32-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-32-O0-NEXT:    vinsertb 2, 3, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-32-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 15
   ret <16 x i8> %vecins
 }

llvm/test/CodeGen/PowerPC/constant-pool.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -target-abi=elfv2 -mtriple=powerpc64-- \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -target-abi=elfv2 -mtriple=powerpc64-- \
 ; RUN:   -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=CHECK-P9
 
  define float @FloatConstantPool() {
 ; CHECK-LABEL: FloatConstantPool:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxsplti32dx vs1, 0, 940572664
-; CHECK-NEXT:    xxsplti32dx vs1, 1, 1073741824
+; CHECK-NEXT:    xxsplti32dx vs1, 0, 940572664 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)
+; CHECK-NEXT:    xxsplti32dx vs1, 1, 1073741824 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)
 ; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: FloatConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-P9-NEXT:    lfs f1, .LCPI0_0@toc@l(r3)
+; CHECK-P9-NEXT:    lfs f1, .LCPI0_0@toc@l(r3) # Vec Defs: F1(VSR1)
 ; CHECK-P9-NEXT:    blr
 entry:
   ret float 0x380FFFF840000000
 }
 
  define double @DoubleConstantPool() {
 ; CHECK-LABEL: DoubleConstantPool:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxsplti32dx vs1, 0, 1048574
-; CHECK-NEXT:    xxsplti32dx vs1, 1, 780229072
+; CHECK-NEXT:    xxsplti32dx vs1, 0, 1048574 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)
+; CHECK-NEXT:    xxsplti32dx vs1, 1, 780229072 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)
 ; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: DoubleConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-P9-NEXT:    lfd f1, .LCPI1_0@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f1, .LCPI1_0@toc@l(r3) # Vec Defs: F1(VSR1)
 ; CHECK-P9-NEXT:    blr
 entry:
   ret double 2.225070e-308
 }
 
  define ppc_fp128 @LongDoubleConstantPool() {
 ; CHECK-LABEL: LongDoubleConstantPool:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxsplti32dx vs1, 0, 56623104
-; CHECK-NEXT:    xxsplti32dx vs2, 0, -2146625897
-; CHECK-NEXT:    xxsplti32dx vs1, 1, -609716532
-; CHECK-NEXT:    xxsplti32dx vs2, 1, 1339675259
+; CHECK-NEXT:    xxsplti32dx vs1, 0, 56623104 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)
+; CHECK-NEXT:    xxsplti32dx vs2, 0, -2146625897 # Vec Defs: VSL2(VSR2) Vec Uses: VSL2(VSR2)
+; CHECK-NEXT:    xxsplti32dx vs1, 1, -609716532 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)
+; CHECK-NEXT:    xxsplti32dx vs2, 1, 1339675259 # Vec Defs: VSL2(VSR2) Vec Uses: VSL2(VSR2)
 ; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: LongDoubleConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
-; CHECK-P9-NEXT:    lfd f1, .LCPI2_0@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f1, .LCPI2_0@toc@l(r3) # Vec Defs: F1(VSR1)
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI2_1@toc@ha
-; CHECK-P9-NEXT:    lfd f2, .LCPI2_1@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f2, .LCPI2_1@toc@l(r3) # Vec Defs: F2(VSR2)
 ; CHECK-P9-NEXT:    blr
 entry:
   ret ppc_fp128 0xM03600000DBA876CC800D16974FD9D27B
 }
 
  define fp128 @__Float128ConstantPool() {
 ; CHECK-LABEL: __Float128ConstantPool:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxv vs34, .LCPI3_0@PCREL(0), 1
+; CHECK-NEXT:    plxv vs34, .LCPI3_0@PCREL(0), 1 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: __Float128ConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-P9-NEXT:    lxv vs34, 0(r3)
+; CHECK-P9-NEXT:    lxv vs34, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-P9-NEXT:    blr
 entry:
   ret fp128 0xL00000000000000003C00FFFFC5D02B3A
 }
 
  define <16 x i8> @VectorCharConstantPool() {
 ; CHECK-LABEL: VectorCharConstantPool:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxv vs34, .LCPI4_0@PCREL(0), 1
+; CHECK-NEXT:    plxv vs34, .LCPI4_0@PCREL(0), 1 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: VectorCharConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-P9-NEXT:    lxv vs34, 0(r3)
+; CHECK-P9-NEXT:    lxv vs34, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-P9-NEXT:    blr
 entry:
   ret <16 x i8> <i8 -128, i8 -127, i8 -126, i8 -125, i8 -124, i8 -123, i8 -122, i8 -121, i8 -120, i8 -119, i8 -118, i8 -117, i8 -116, i8 -115, i8 -114, i8 -113>
 }
 
  define <8 x i16> @VectorShortConstantPool() {
 ; CHECK-LABEL: VectorShortConstantPool:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxv vs34, .LCPI5_0@PCREL(0), 1
+; CHECK-NEXT:    plxv vs34, .LCPI5_0@PCREL(0), 1 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: VectorShortConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-P9-NEXT:    lxv vs34, 0(r3)
+; CHECK-P9-NEXT:    lxv vs34, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-P9-NEXT:    blr
 entry:
   ret <8 x i16> <i16 -32768, i16 -32767, i16 -32766, i16 -32765, i16 -32764, i16 -32763, i16 -32762, i16 -32761>
 }
 
  define <4 x i32> @VectorIntConstantPool() {
 ; CHECK-LABEL: VectorIntConstantPool:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxv vs34, .LCPI6_0@PCREL(0), 1
+; CHECK-NEXT:    plxv vs34, .LCPI6_0@PCREL(0), 1 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: VectorIntConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI6_0@toc@l
-; CHECK-P9-NEXT:    lxv vs34, 0(r3)
+; CHECK-P9-NEXT:    lxv vs34, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-P9-NEXT:    blr
 entry:
   ret <4 x i32> <i32 -2147483648, i32 -2147483647, i32 -2147483646, i32 -2147483645>
 }
 
  define <2 x i64> @VectorLongLongConstantPool() {
 ; CHECK-LABEL: VectorLongLongConstantPool:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxv vs34, .LCPI7_0@PCREL(0), 1
+; CHECK-NEXT:    plxv vs34, .LCPI7_0@PCREL(0), 1 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: VectorLongLongConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI7_0@toc@l
-; CHECK-P9-NEXT:    lxv vs34, 0(r3)
+; CHECK-P9-NEXT:    lxv vs34, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-P9-NEXT:    blr
 entry:
   ret <2 x i64> <i64 -9223372036854775808, i64 -9223372036854775807>
 }
 
  define <1 x i128> @VectorInt128ConstantPool() {
 ; CHECK-LABEL: VectorInt128ConstantPool:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxv vs34, .LCPI8_0@PCREL(0), 1
+; CHECK-NEXT:    plxv vs34, .LCPI8_0@PCREL(0), 1 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: VectorInt128ConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI8_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI8_0@toc@l
-; CHECK-P9-NEXT:    lxv vs34, 0(r3)
+; CHECK-P9-NEXT:    lxv vs34, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-P9-NEXT:    blr
 entry:
   ret <1 x i128> <i128 -27670116110564327424>
 }
 
  define <4 x float> @VectorFloatConstantPool() {
 ; CHECK-LABEL: VectorFloatConstantPool:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxv vs34, .LCPI9_0@PCREL(0), 1
+; CHECK-NEXT:    plxv vs34, .LCPI9_0@PCREL(0), 1 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: VectorFloatConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI9_0@toc@l
-; CHECK-P9-NEXT:    lxv vs34, 0(r3)
+; CHECK-P9-NEXT:    lxv vs34, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-P9-NEXT:    blr
 entry:
   ret <4 x float> <float 0x380FFFF840000000, float 0x380FFF57C0000000, float 0x3843FFFB20000000, float 0x3843FF96C0000000>
 }
 
  define <2 x double> @VectorDoubleConstantPool() {
 ; CHECK-LABEL: VectorDoubleConstantPool:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxv vs34, .LCPI10_0@PCREL(0), 1
+; CHECK-NEXT:    plxv vs34, .LCPI10_0@PCREL(0), 1 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: VectorDoubleConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI10_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI10_0@toc@l
-; CHECK-P9-NEXT:    lxv vs34, 0(r3)
+; CHECK-P9-NEXT:    lxv vs34, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-P9-NEXT:    blr
 entry:
   ret <2 x double> <double 2.225070e-308, double 2.225000e-308>
 }
 
 define double @two_constants(double %a) {
 ; CHECK-LABEL: two_constants:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxsplti32dx vs0, 0, 1074446467
-; CHECK-NEXT:    xxsplti32dx vs0, 1, 309237645
-; CHECK-NEXT:    xsadddp f0, f1, f0
-; CHECK-NEXT:    xxsplti32dx vs1, 0, 1073922179
-; CHECK-NEXT:    xxsplti32dx vs1, 1, 309237645
-; CHECK-NEXT:    xsadddp f1, f0, f1
+; CHECK-NEXT:    xxsplti32dx vs0, 0, 1074446467 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)
+; CHECK-NEXT:    xxsplti32dx vs0, 1, 309237645 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)
+; CHECK-NEXT:    xsadddp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; CHECK-NEXT:    xxsplti32dx vs1, 0, 1073922179 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)
+; CHECK-NEXT:    xxsplti32dx vs1, 1, 309237645 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)
+; CHECK-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: two_constants:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI11_0@toc@ha
-; CHECK-P9-NEXT:    lfd f0, .LCPI11_0@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f0, .LCPI11_0@toc@l(r3) # Vec Defs: F0(VSR0)
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI11_1@toc@ha
-; CHECK-P9-NEXT:    xsadddp f0, f1, f0
-; CHECK-P9-NEXT:    lfd f1, .LCPI11_1@toc@l(r3)
-; CHECK-P9-NEXT:    xsadddp f1, f0, f1
+; CHECK-P9-NEXT:    xsadddp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; CHECK-P9-NEXT:    lfd f1, .LCPI11_1@toc@l(r3) # Vec Defs: F1(VSR1)
+; CHECK-P9-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = fadd double %a, 3.344000e+00
   %1 = fadd double %0, 2.344000e+00
   ret double %1
 }
 
 define double @two_constants_two_bb(i32 %m, double %a) {
 ; CHECK-LABEL: two_constants_two_bb:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmplwi r3, 0
 ; CHECK-NEXT:    beq cr0, .LBB12_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    xxsplti32dx vs1, 0, 1074935889
-; CHECK-NEXT:    xxsplti32dx vs1, 1, -343597384
+; CHECK-NEXT:    xxsplti32dx vs1, 0, 1074935889 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)
+; CHECK-NEXT:    xxsplti32dx vs1, 1, -343597384 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)
 ; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB12_2: # %if.end
-; CHECK-NEXT:    xxsplti32dx vs0, 0, 1076085391
-; CHECK-NEXT:    xxsplti32dx vs0, 1, 1546188227
-; CHECK-NEXT:    xsadddp f1, f1, f0
+; CHECK-NEXT:    xxsplti32dx vs0, 0, 1076085391 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)
+; CHECK-NEXT:    xxsplti32dx vs0, 1, 1546188227 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)
+; CHECK-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: two_constants_two_bb:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    cmplwi r3, 0
 ; CHECK-P9-NEXT:    beq cr0, .LBB12_2
 ; CHECK-P9-NEXT:  # %bb.1:
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI12_0@toc@ha
-; CHECK-P9-NEXT:    lfd f1, .LCPI12_0@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f1, .LCPI12_0@toc@l(r3) # Vec Defs: F1(VSR1)
 ; CHECK-P9-NEXT:    blr
 ; CHECK-P9-NEXT:  .LBB12_2: # %if.end
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI12_1@toc@ha
-; CHECK-P9-NEXT:    lfd f0, .LCPI12_1@toc@l(r3)
-; CHECK-P9-NEXT:    xsadddp f1, f1, f0
+; CHECK-P9-NEXT:    lfd f0, .LCPI12_1@toc@l(r3) # Vec Defs: F0(VSR0)
+; CHECK-P9-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; CHECK-P9-NEXT:    blr
 entry:
   %tobool.not = icmp eq i32 %m, 0
   br i1 %tobool.not, label %if.end, label %return
 
 if.end:
   %add = fadd double %a, 9.880000e+00
   br label %return
 
 return:
   %retval.0 = phi double [ %add, %if.end ], [ 4.555000e+00, %entry ]
   ret double %retval.0
 }
 
 define double @three_constants_f64(double %a, double %c) {
 ; CHECK-LABEL: three_constants_f64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxsplti32dx vs0, 0, 1074446467
-; CHECK-NEXT:    xxsplti32dx vs0, 1, 309237645
-; CHECK-NEXT:    xsadddp f0, f1, f0
-; CHECK-NEXT:    xxsplti32dx vs1, 0, 1073922179
-; CHECK-NEXT:    xxsplti32dx vs1, 1, 309237645
-; CHECK-NEXT:    xsadddp f0, f0, f1
-; CHECK-NEXT:    xxsplti32dx vs1, 0, 1073948393
-; CHECK-NEXT:    xxsplti32dx vs1, 1, 2027224564
-; CHECK-NEXT:    xsadddp f1, f0, f1
+; CHECK-NEXT:    xxsplti32dx vs0, 0, 1074446467 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)
+; CHECK-NEXT:    xxsplti32dx vs0, 1, 309237645 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)
+; CHECK-NEXT:    xsadddp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; CHECK-NEXT:    xxsplti32dx vs1, 0, 1073922179 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)
+; CHECK-NEXT:    xxsplti32dx vs1, 1, 309237645 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)
+; CHECK-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; CHECK-NEXT:    xxsplti32dx vs1, 0, 1073948393 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)
+; CHECK-NEXT:    xxsplti32dx vs1, 1, 2027224564 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)
+; CHECK-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: three_constants_f64:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI13_0@toc@ha
-; CHECK-P9-NEXT:    lfd f0, .LCPI13_0@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f0, .LCPI13_0@toc@l(r3) # Vec Defs: F0(VSR0)
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI13_1@toc@ha
-; CHECK-P9-NEXT:    xsadddp f0, f1, f0
-; CHECK-P9-NEXT:    lfd f1, .LCPI13_1@toc@l(r3)
+; CHECK-P9-NEXT:    xsadddp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; CHECK-P9-NEXT:    lfd f1, .LCPI13_1@toc@l(r3) # Vec Defs: F1(VSR1)
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI13_2@toc@ha
-; CHECK-P9-NEXT:    xsadddp f0, f0, f1
-; CHECK-P9-NEXT:    lfd f1, .LCPI13_2@toc@l(r3)
-; CHECK-P9-NEXT:    xsadddp f1, f0, f1
+; CHECK-P9-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; CHECK-P9-NEXT:    lfd f1, .LCPI13_2@toc@l(r3) # Vec Defs: F1(VSR1)
+; CHECK-P9-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = fadd double %a, 3.344000e+00
   %1 = fadd double %0, 2.344000e+00
   %2 = fadd double %1, 2.394000e+00
   ret double %2
 }
 
 define float @three_constants_f32(float %a, float %c) {
 ; CHECK-LABEL: three_constants_f32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxspltidp vs0, 1083294351
-; CHECK-NEXT:    xsaddsp f0, f1, f0
-; CHECK-NEXT:    xxspltidp vs1, 1083296911
-; CHECK-NEXT:    xsaddsp f0, f0, f1
-; CHECK-NEXT:    xxspltidp vs1, 1083292559
-; CHECK-NEXT:    xsaddsp f1, f0, f1
+; CHECK-NEXT:    xxspltidp vs0, 1083294351 # Vec Defs: VSL0(VSR0)
+; CHECK-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; CHECK-NEXT:    xxspltidp vs1, 1083296911 # Vec Defs: VSL1(VSR1)
+; CHECK-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; CHECK-NEXT:    xxspltidp vs1, 1083292559 # Vec Defs: VSL1(VSR1)
+; CHECK-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: three_constants_f32:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI14_0@toc@ha
-; CHECK-P9-NEXT:    lfs f0, .LCPI14_0@toc@l(r3)
+; CHECK-P9-NEXT:    lfs f0, .LCPI14_0@toc@l(r3) # Vec Defs: F0(VSR0)
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI14_1@toc@ha
-; CHECK-P9-NEXT:    xsaddsp f0, f1, f0
-; CHECK-P9-NEXT:    lfs f1, .LCPI14_1@toc@l(r3)
+; CHECK-P9-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; CHECK-P9-NEXT:    lfs f1, .LCPI14_1@toc@l(r3) # Vec Defs: F1(VSR1)
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI14_2@toc@ha
-; CHECK-P9-NEXT:    xsaddsp f0, f0, f1
-; CHECK-P9-NEXT:    lfs f1, .LCPI14_2@toc@l(r3)
-; CHECK-P9-NEXT:    xsaddsp f1, f0, f1
+; CHECK-P9-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; CHECK-P9-NEXT:    lfs f1, .LCPI14_2@toc@l(r3) # Vec Defs: F1(VSR1)
+; CHECK-P9-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = fadd float %a, 0x40123851E0000000
   %1 = fadd float %0, 0x40123991E0000000
   %2 = fadd float %1, 0x40123771E0000000
   ret float %2
 }
 
 define fp128 @three_constants_f128(fp128 %a, fp128 %c) {
 ; CHECK-LABEL: three_constants_f128:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxv vs35, .LCPI15_0@PCREL(0), 1
-; CHECK-NEXT:    xsaddqp v2, v2, v3
-; CHECK-NEXT:    plxv vs35, .LCPI15_1@PCREL(0), 1
-; CHECK-NEXT:    xsaddqp v2, v2, v3
-; CHECK-NEXT:    plxv vs35, .LCPI15_2@PCREL(0), 1
-; CHECK-NEXT:    xsaddqp v2, v2, v3
+; CHECK-NEXT:    plxv vs35, .LCPI15_0@PCREL(0), 1 # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-NEXT:    plxv vs35, .LCPI15_1@PCREL(0), 1 # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-NEXT:    plxv vs35, .LCPI15_2@PCREL(0), 1 # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: three_constants_f128:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI15_0@toc@l
-; CHECK-P9-NEXT:    lxv vs35, 0(r3)
+; CHECK-P9-NEXT:    lxv vs35, 0(r3) # Vec Defs: V3(VSR35)
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI15_1@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI15_1@toc@l
-; CHECK-P9-NEXT:    xsaddqp v2, v2, v3
-; CHECK-P9-NEXT:    lxv vs35, 0(r3)
+; CHECK-P9-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-P9-NEXT:    lxv vs35, 0(r3) # Vec Defs: V3(VSR35)
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI15_2@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI15_2@toc@l
-; CHECK-P9-NEXT:    xsaddqp v2, v2, v3
-; CHECK-P9-NEXT:    lxv vs35, 0(r3)
-; CHECK-P9-NEXT:    xsaddqp v2, v2, v3
+; CHECK-P9-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-P9-NEXT:    lxv vs35, 0(r3) # Vec Defs: V3(VSR35)
+; CHECK-P9-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = fadd fp128 %a, 0xL8000000000000000400123851EB851EB
   %1 = fadd fp128 %0, 0xL8000000000000000400123851EB991EB
   %2 = fadd fp128 %1, 0xL8000000000000000400123851EB771EB
   ret fp128 %2
 }
 
 define ppc_fp128 @three_constants_ppcf128(ppc_fp128 %a, ppc_fp128 %c) {
 ; CHECK-LABEL: three_constants_ppcf128:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -48(r1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    .cfi_offset v31, -16
-; CHECK-NEXT:    xxsplti32dx vs3, 0, 1074935889
-; CHECK-NEXT:    xxlxor f4, f4, f4
+; CHECK-NEXT:    xxsplti32dx vs3, 0, 1074935889 # Vec Defs: VSL3(VSR3) Vec Uses: VSL3(VSR3)
+; CHECK-NEXT:    xxlxor f4, f4, f4 # Vec Defs: F4(VSR4)
 ; CHECK-NEXT:    stxv vs63, 32(r1) # 16-byte Folded Spill
-; CHECK-NEXT:    xxsplti32dx vs63, 0, 1074935889
-; CHECK-NEXT:    xxsplti32dx vs3, 1, -343597384
+; CHECK-NEXT:    # Vec Uses: V31(VSR63)
+; CHECK-NEXT:    xxsplti32dx vs63, 0, 1074935889 # Vec Defs: V31(VSR63) Vec Uses: V31(VSR63)
+; CHECK-NEXT:    xxsplti32dx vs3, 1, -343597384 # Vec Defs: VSL3(VSR3) Vec Uses: VSL3(VSR3)
 ; CHECK-NEXT:    # kill: def $f3 killed $f3 killed $vsl3
 ; CHECK-NEXT:    bl __gcc_qadd@notoc
-; CHECK-NEXT:    xxsplti32dx vs3, 0, 1074935889
-; CHECK-NEXT:    xxlxor f4, f4, f4
-; CHECK-NEXT:    xxsplti32dx vs3, 1, -1719329096
+; CHECK-NEXT:    xxsplti32dx vs3, 0, 1074935889 # Vec Defs: VSL3(VSR3) Vec Uses: VSL3(VSR3)
+; CHECK-NEXT:    xxlxor f4, f4, f4 # Vec Defs: F4(VSR4)
+; CHECK-NEXT:    xxsplti32dx vs3, 1, -1719329096 # Vec Defs: VSL3(VSR3) Vec Uses: VSL3(VSR3)
 ; CHECK-NEXT:    # kill: def $f3 killed $f3 killed $vsl3
 ; CHECK-NEXT:    bl __gcc_qadd@notoc
-; CHECK-NEXT:    xxsplti32dx vs63, 1, 8724152
-; CHECK-NEXT:    xxlxor f4, f4, f4
-; CHECK-NEXT:    xscpsgndp f3, vs63, vs63
+; CHECK-NEXT:    xxsplti32dx vs63, 1, 8724152 # Vec Defs: V31(VSR63) Vec Uses: V31(VSR63)
+; CHECK-NEXT:    xxlxor f4, f4, f4 # Vec Defs: F4(VSR4)
+; CHECK-NEXT:    xscpsgndp f3, vs63, vs63 # Vec Defs: F3(VSR3) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; CHECK-NEXT:    bl __gcc_qadd@notoc
 ; CHECK-NEXT:    lxv vs63, 32(r1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-NEXT:    addi r1, r1, 48
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: three_constants_ppcf128:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mflr r0
 ; CHECK-P9-NEXT:    std r0, 16(r1)
 ; CHECK-P9-NEXT:    stdu r1, -32(r1)
 ; CHECK-P9-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P9-NEXT:    .cfi_offset lr, 16
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
-; CHECK-P9-NEXT:    xxlxor f4, f4, f4
-; CHECK-P9-NEXT:    lfd f3, .LCPI16_0@toc@l(r3)
+; CHECK-P9-NEXT:    xxlxor f4, f4, f4 # Vec Defs: F4(VSR4)
+; CHECK-P9-NEXT:    lfd f3, .LCPI16_0@toc@l(r3) # Vec Defs: F3(VSR3)
 ; CHECK-P9-NEXT:    bl __gcc_qadd
 ; CHECK-P9-NEXT:    nop
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI16_1@toc@ha
-; CHECK-P9-NEXT:    xxlxor f4, f4, f4
-; CHECK-P9-NEXT:    lfd f3, .LCPI16_1@toc@l(r3)
+; CHECK-P9-NEXT:    xxlxor f4, f4, f4 # Vec Defs: F4(VSR4)
+; CHECK-P9-NEXT:    lfd f3, .LCPI16_1@toc@l(r3) # Vec Defs: F3(VSR3)
 ; CHECK-P9-NEXT:    bl __gcc_qadd
 ; CHECK-P9-NEXT:    nop
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI16_2@toc@ha
-; CHECK-P9-NEXT:    xxlxor f4, f4, f4
-; CHECK-P9-NEXT:    lfd f3, .LCPI16_2@toc@l(r3)
+; CHECK-P9-NEXT:    xxlxor f4, f4, f4 # Vec Defs: F4(VSR4)
+; CHECK-P9-NEXT:    lfd f3, .LCPI16_2@toc@l(r3) # Vec Defs: F3(VSR3)
 ; CHECK-P9-NEXT:    bl __gcc_qadd
 ; CHECK-P9-NEXT:    nop
 ; CHECK-P9-NEXT:    addi r1, r1, 32
 ; CHECK-P9-NEXT:    ld r0, 16(r1)
 ; CHECK-P9-NEXT:    mtlr r0
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = fadd ppc_fp128 %a, 0xM40123851EB851EB80000000000000000
   %1 = fadd ppc_fp128 %0, 0xM4012385199851EB80000000000000000
   %2 = fadd ppc_fp128 %1, 0xM4012385100851EB80000000000000000
   ret ppc_fp128 %2
 }
 
 define <2 x double> @three_constants_vector(<2 x double> %a, <2 x double> %c) {
 ; CHECK-LABEL: three_constants_vector:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxv vs0, .LCPI17_0@PCREL(0), 1
-; CHECK-NEXT:    plxv vs2, .LCPI17_1@PCREL(0), 1
-; CHECK-NEXT:    xvadddp vs1, vs34, vs0
-; CHECK-NEXT:    xvadddp vs1, vs1, vs2
-; CHECK-NEXT:    xvadddp vs34, vs1, vs0
+; CHECK-NEXT:    plxv vs0, .LCPI17_0@PCREL(0), 1 # Vec Defs: VSL0(VSR0)
+; CHECK-NEXT:    plxv vs2, .LCPI17_1@PCREL(0), 1 # Vec Defs: VSL2(VSR2)
+; CHECK-NEXT:    xvadddp vs1, vs34, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)VSL0(VSR0)
+; CHECK-NEXT:    xvadddp vs1, vs1, vs2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)VSL2(VSR2)
+; CHECK-NEXT:    xvadddp vs34, vs1, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL1(VSR1)VSL0(VSR0)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: three_constants_vector:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI17_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI17_0@toc@l
-; CHECK-P9-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-NEXT:    lxv vs0, 0(r3) # Vec Defs: VSL0(VSR0)
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI17_1@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI17_1@toc@l
-; CHECK-P9-NEXT:    lxv vs2, 0(r3)
-; CHECK-P9-NEXT:    xvadddp vs1, vs34, vs0
-; CHECK-P9-NEXT:    xvadddp vs1, vs1, vs2
-; CHECK-P9-NEXT:    xvadddp vs34, vs1, vs0
+; CHECK-P9-NEXT:    lxv vs2, 0(r3) # Vec Defs: VSL2(VSR2)
+; CHECK-P9-NEXT:    xvadddp vs1, vs34, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)VSL0(VSR0)
+; CHECK-P9-NEXT:    xvadddp vs1, vs1, vs2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)VSL2(VSR2)
+; CHECK-P9-NEXT:    xvadddp vs34, vs1, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL1(VSR1)VSL0(VSR0)
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = fadd <2 x double> %a, <double 4.555000e+00, double 9.880000e+00>
   %1 = fadd <2 x double> %0, <double 4.555000e+00, double 9.980000e+00>
   %2 = fadd <2 x double> %1, <double 4.555000e+00, double 9.880000e+00>
   ret <2 x double> %2
 }

llvm/test/CodeGen/PowerPC/csr-save-restore-order.ll

 ; CHECK-PWR9-NEXT:    .cfi_offset v27, -368
 ; CHECK-PWR9-NEXT:    .cfi_offset v28, -352
 ; CHECK-PWR9-NEXT:    .cfi_offset v29, -336
 ; CHECK-PWR9-NEXT:    .cfi_offset v30, -320
 ; CHECK-PWR9-NEXT:    .cfi_offset v31, -304
 ; CHECK-PWR9-NEXT:    std r14, 240(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    std r15, 248(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    stxv v20, 48(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V20(VSR52)
 ; CHECK-PWR9-NEXT:    stxv v21, 64(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V21(VSR53)
 ; CHECK-PWR9-NEXT:    std r16, 256(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    stxv v22, 80(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V22(VSR54)
 ; CHECK-PWR9-NEXT:    std r17, 264(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    stxv v23, 96(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V23(VSR55)
 ; CHECK-PWR9-NEXT:    std r18, 272(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    std r19, 280(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    stxv v24, 112(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V24(VSR56)
 ; CHECK-PWR9-NEXT:    std r20, 288(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    stxv v25, 128(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V25(VSR57)
 ; CHECK-PWR9-NEXT:    std r21, 296(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    stxv v26, 144(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V26(VSR58)
 ; CHECK-PWR9-NEXT:    std r22, 304(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    std r23, 312(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    stxv v27, 160(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V27(VSR59)
 ; CHECK-PWR9-NEXT:    std r24, 320(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    stxv v28, 176(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V28(VSR60)
 ; CHECK-PWR9-NEXT:    std r25, 328(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    stxv v29, 192(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V29(VSR61)
 ; CHECK-PWR9-NEXT:    std r26, 336(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    std r27, 344(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    stxv v30, 208(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V30(VSR62)
 ; CHECK-PWR9-NEXT:    std r28, 352(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    stxv v31, 224(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: V31(VSR63)
 ; CHECK-PWR9-NEXT:    std r29, 360(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    std r30, 368(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    std r31, 376(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    stfd f14, 384(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F14(VSR14)
 ; CHECK-PWR9-NEXT:    stfd f15, 392(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F15(VSR15)
 ; CHECK-PWR9-NEXT:    stfd f16, 400(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F16(VSR16)
 ; CHECK-PWR9-NEXT:    stfd f17, 408(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F17(VSR17)
 ; CHECK-PWR9-NEXT:    stfd f18, 416(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F18(VSR18)
 ; CHECK-PWR9-NEXT:    stfd f19, 424(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F19(VSR19)
 ; CHECK-PWR9-NEXT:    stfd f20, 432(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F20(VSR20)
 ; CHECK-PWR9-NEXT:    stfd f21, 440(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F21(VSR21)
 ; CHECK-PWR9-NEXT:    stfd f22, 448(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F22(VSR22)
 ; CHECK-PWR9-NEXT:    stfd f23, 456(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F23(VSR23)
 ; CHECK-PWR9-NEXT:    stfd f24, 464(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F24(VSR24)
 ; CHECK-PWR9-NEXT:    stfd f25, 472(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F25(VSR25)
 ; CHECK-PWR9-NEXT:    stfd f26, 480(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F26(VSR26)
 ; CHECK-PWR9-NEXT:    stfd f27, 488(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F27(VSR27)
 ; CHECK-PWR9-NEXT:    stfd f28, 496(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F28(VSR28)
 ; CHECK-PWR9-NEXT:    stfd f29, 504(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F29(VSR29)
 ; CHECK-PWR9-NEXT:    stfd f30, 512(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F30(VSR30)
 ; CHECK-PWR9-NEXT:    stfd f31, 520(r1) # 8-byte Folded Spill
+; CHECK-PWR9-NEXT:    # Vec Uses: F31(VSR31)
 ; CHECK-PWR9-NEXT:    std r4, 40(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    std r3, 32(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    #APP
 ; CHECK-PWR9-NEXT:    nop
 ; CHECK-PWR9-NEXT:    #NO_APP
 ; CHECK-PWR9-NEXT:    ld r3, 40(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    ld r4, 32(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    lxv v31, 224(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-PWR9-NEXT:    lxv v30, 208(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V30(VSR62)
 ; CHECK-PWR9-NEXT:    add r3, r4, r3
 ; CHECK-PWR9-NEXT:    lxv v29, 192(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V29(VSR61)
 ; CHECK-PWR9-NEXT:    lxv v28, 176(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V28(VSR60)
 ; CHECK-PWR9-NEXT:    lxv v27, 160(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V27(VSR59)
 ; CHECK-PWR9-NEXT:    lxv v26, 144(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V26(VSR58)
 ; CHECK-PWR9-NEXT:    lxv v25, 128(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V25(VSR57)
 ; CHECK-PWR9-NEXT:    lxv v24, 112(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V24(VSR56)
 ; CHECK-PWR9-NEXT:    lxv v23, 96(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V23(VSR55)
 ; CHECK-PWR9-NEXT:    lxv v22, 80(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V22(VSR54)
 ; CHECK-PWR9-NEXT:    lxv v21, 64(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V21(VSR53)
 ; CHECK-PWR9-NEXT:    lxv v20, 48(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: V20(VSR52)
 ; CHECK-PWR9-NEXT:    lfd f31, 520(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F31(VSR31)
 ; CHECK-PWR9-NEXT:    lfd f30, 512(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F30(VSR30)
 ; CHECK-PWR9-NEXT:    lfd f29, 504(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F29(VSR29)
 ; CHECK-PWR9-NEXT:    lfd f28, 496(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F28(VSR28)
 ; CHECK-PWR9-NEXT:    lfd f27, 488(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F27(VSR27)
 ; CHECK-PWR9-NEXT:    ld r31, 376(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    ld r30, 368(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    ld r29, 360(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    ld r28, 352(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    lfd f26, 480(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F26(VSR26)
 ; CHECK-PWR9-NEXT:    ld r27, 344(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    ld r26, 336(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    ld r25, 328(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    lfd f25, 472(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F25(VSR25)
 ; CHECK-PWR9-NEXT:    ld r24, 320(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    ld r23, 312(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    ld r22, 304(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    lfd f24, 464(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F24(VSR24)
 ; CHECK-PWR9-NEXT:    ld r21, 296(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    ld r20, 288(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    ld r19, 280(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    lfd f23, 456(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F23(VSR23)
 ; CHECK-PWR9-NEXT:    ld r18, 272(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    ld r17, 264(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    ld r16, 256(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    lfd f22, 448(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F22(VSR22)
 ; CHECK-PWR9-NEXT:    ld r15, 248(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    ld r14, 240(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    lfd f21, 440(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F21(VSR21)
 ; CHECK-PWR9-NEXT:    lfd f20, 432(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F20(VSR20)
 ; CHECK-PWR9-NEXT:    lfd f19, 424(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F19(VSR19)
 ; CHECK-PWR9-NEXT:    lfd f18, 416(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F18(VSR18)
 ; CHECK-PWR9-NEXT:    lfd f17, 408(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F17(VSR17)
 ; CHECK-PWR9-NEXT:    lfd f16, 400(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F16(VSR16)
 ; CHECK-PWR9-NEXT:    lfd f15, 392(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F15(VSR15)
 ; CHECK-PWR9-NEXT:    lfd f14, 384(r1) # 8-byte Folded Reload
+; CHECK-PWR9-NEXT:    # Vec Defs: F14(VSR14)
 ; CHECK-PWR9-NEXT:    addi r1, r1, 528
 ; CHECK-PWR9-NEXT:    blr
 entry:
   tail call void asm sideeffect "nop", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31},~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() nounwind
   %result = add i64 %p1, %p2
   ret i64 %result
 }

llvm/test/CodeGen/PowerPC/f128-aggregates.ll

%struct.With9fp128params = type { fp128, fp128, fp128, fp128, fp128, fp128,
                                   fp128, fp128, fp128 }
 
 @a1 = local_unnamed_addr global [3 x fp128] zeroinitializer, align 16
 
 ; Function Attrs: norecurse nounwind readonly
 define fp128 @testArray_01(fp128* nocapture readonly %sa) {
 ; CHECK-LABEL: testArray_01:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv v2, 32(r3)
+; CHECK-NEXT:    lxv v2, 32(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testArray_01:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv v2, 32(r3)
+; CHECK-BE-NEXT:    lxv v2, 32(r3) # Vec Defs: V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testArray_01:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addi r3, r3, 32
-; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %arrayidx = getelementptr inbounds fp128, fp128* %sa, i64 2
   %0 = load fp128, fp128* %arrayidx, align 16
   ret fp128 %0
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define fp128 @testArray_02() {
 ; CHECK-LABEL: testArray_02:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-NEXT:    ld r3, .LC0@toc@l(r3)
-; CHECK-NEXT:    lxv v2, 32(r3)
+; CHECK-NEXT:    lxv v2, 32(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testArray_02:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; CHECK-BE-NEXT:    lxv v2, 32(r3)
+; CHECK-BE-NEXT:    lxv v2, 32(r3) # Vec Defs: V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testArray_02:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-P8-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-P8-NEXT:    addi r3, r3, 32
-; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %0 = load fp128, fp128* getelementptr inbounds ([3 x fp128], [3 x fp128]* @a1,
                                                   i64 0, i64 2), align 16
   ret fp128 %0
 }
 

 entry:
   ret fp128 %a.coerce
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @testStruct_02([8 x fp128] %a.coerce) {
 ; CHECK-LABEL: testStruct_02:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmr v2, v9
+; CHECK-NEXT:    vmr v2, v9 # Vec Defs: V2(VSR34) Vec Uses: V9(VSR41)V9(VSR41)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testStruct_02:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vmr v2, v9
+; CHECK-BE-NEXT:    vmr v2, v9 # Vec Defs: V2(VSR34) Vec Uses: V9(VSR41)V9(VSR41)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testStruct_02:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    vmr v2, v9
+; CHECK-P8-NEXT:    vmr v2, v9 # Vec Defs: V2(VSR34) Vec Uses: V9(VSR41)V9(VSR41)
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.7.extract = extractvalue [8 x fp128] %a.coerce, 7
   ret fp128 %a.coerce.fca.7.extract
 }
 
 ; Since we can only pass a max of 8 float128 value in VSX registers, ensure we
 ; store to stack if passing more.
 ; Function Attrs: norecurse nounwind readonly
 define fp128 @testStruct_03(%struct.With9fp128params* byval(%struct.With9fp128params) nocapture readonly align 16 %a) {
 ; CHECK-LABEL: testStruct_03:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv v2, 128(r1)
+; CHECK-NEXT:    lxv v2, 128(r1) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    std r3, 32(r1)
 ; CHECK-NEXT:    std r4, 40(r1)
 ; CHECK-NEXT:    std r5, 48(r1)
 ; CHECK-NEXT:    std r6, 56(r1)
 ; CHECK-NEXT:    std r7, 64(r1)
 ; CHECK-NEXT:    std r8, 72(r1)
 ; CHECK-NEXT:    std r9, 80(r1)
 ; CHECK-NEXT:    std r10, 88(r1)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testStruct_03:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv v2, 144(r1)
+; CHECK-BE-NEXT:    lxv v2, 144(r1) # Vec Defs: V2(VSR34)
 ; CHECK-BE-NEXT:    std r3, 48(r1)
 ; CHECK-BE-NEXT:    std r4, 56(r1)
 ; CHECK-BE-NEXT:    std r5, 64(r1)
 ; CHECK-BE-NEXT:    std r6, 72(r1)
 ; CHECK-BE-NEXT:    std r7, 80(r1)
 ; CHECK-BE-NEXT:    std r8, 88(r1)
 ; CHECK-BE-NEXT:    std r9, 96(r1)
 ; CHECK-BE-NEXT:    std r10, 104(r1)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testStruct_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    li r11, 96
 ; CHECK-P8-NEXT:    addi r12, r1, 32
 ; CHECK-P8-NEXT:    std r3, 32(r1)
 ; CHECK-P8-NEXT:    std r4, 40(r1)
 ; CHECK-P8-NEXT:    std r5, 48(r1)
 ; CHECK-P8-NEXT:    std r6, 56(r1)
-; CHECK-P8-NEXT:    lvx v2, r12, r11
+; CHECK-P8-NEXT:    lvx v2, r12, r11 # Vec Defs: V2(VSR34)
 ; CHECK-P8-NEXT:    std r7, 64(r1)
 ; CHECK-P8-NEXT:    std r8, 72(r1)
 ; CHECK-P8-NEXT:    std r9, 80(r1)
 ; CHECK-P8-NEXT:    std r10, 88(r1)
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a7 = getelementptr inbounds %struct.With9fp128params,
                                %struct.With9fp128params* %a, i64 0, i32 6
   %0 = load fp128, fp128* %a7, align 16
   ret fp128 %0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @testStruct_04([8 x fp128] %a.coerce) {
 ; CHECK-LABEL: testStruct_04:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmr v2, v5
+; CHECK-NEXT:    vmr v2, v5 # Vec Defs: V2(VSR34) Vec Uses: V5(VSR37)V5(VSR37)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testStruct_04:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vmr v2, v5
+; CHECK-BE-NEXT:    vmr v2, v5 # Vec Defs: V2(VSR34) Vec Uses: V5(VSR37)V5(VSR37)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testStruct_04:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    vmr v2, v5
+; CHECK-P8-NEXT:    vmr v2, v5 # Vec Defs: V2(VSR34) Vec Uses: V5(VSR37)V5(VSR37)
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.3.extract = extractvalue [8 x fp128] %a.coerce, 3
   ret fp128 %a.coerce.fca.3.extract
 }
 
 ; Function Attrs: norecurse nounwind readnone
entry:
   %a.coerce.fca.0.extract = extractvalue [3 x fp128] %a.coerce, 0
   ret fp128 %a.coerce.fca.0.extract
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @testHUnion_03([3 x fp128] %a.coerce) {
 ; CHECK-LABEL: testHUnion_03:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmr v2, v3
+; CHECK-NEXT:    vmr v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testHUnion_03:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vmr v2, v3
+; CHECK-BE-NEXT:    vmr v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testHUnion_03:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    vmr v2, v3
+; CHECK-P8-NEXT:    vmr v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.1.extract = extractvalue [3 x fp128] %a.coerce, 1
   ret fp128 %a.coerce.fca.1.extract
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @testHUnion_04([3 x fp128] %a.coerce) {
 ; CHECK-LABEL: testHUnion_04:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmr v2, v4
+; CHECK-NEXT:    vmr v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V4(VSR36)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testHUnion_04:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vmr v2, v4
+; CHECK-BE-NEXT:    vmr v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V4(VSR36)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testHUnion_04:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    vmr v2, v4
+; CHECK-P8-NEXT:    vmr v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V4(VSR36)
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.2.extract = extractvalue [3 x fp128] %a.coerce, 2
   ret fp128 %a.coerce.fca.2.extract
 }
 
 ; Testing mixed member aggregates.
 
 %struct.MixedC = type { i32, %struct.SA, float, [12 x i8] }
 %struct.SA = type { double, fp128, <4 x float> }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @testMixedAggregate([3 x i128] %a.coerce) {
 ; CHECK-LABEL: testMixedAggregate:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrdd v2, r8, r7
+; CHECK-NEXT:    mtvsrdd v2, r8, r7 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testMixedAggregate:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrdd v2, r8, r7
+; CHECK-BE-NEXT:    mtvsrdd v2, r8, r7 # Vec Defs: V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testMixedAggregate:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addi r3, r1, -16
 ; CHECK-P8-NEXT:    std r8, -8(r1)
 ; CHECK-P8-NEXT:    std r7, -16(r1)
-; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.2.extract = extractvalue [3 x i128] %a.coerce, 2
   %0 = bitcast i128 %a.coerce.fca.2.extract to fp128
   ret fp128 %0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @testMixedAggregate_02([4 x i128] %a.coerce) {
 ; CHECK-LABEL: testMixedAggregate_02:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrdd v2, r6, r5
+; CHECK-NEXT:    mtvsrdd v2, r6, r5 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testMixedAggregate_02:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrdd v2, r6, r5
+; CHECK-BE-NEXT:    mtvsrdd v2, r6, r5 # Vec Defs: V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testMixedAggregate_02:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addi r3, r1, -16
 ; CHECK-P8-NEXT:    std r6, -8(r1)
 ; CHECK-P8-NEXT:    std r5, -16(r1)
-; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.1.extract = extractvalue [4 x i128] %a.coerce, 1
   %0 = bitcast i128 %a.coerce.fca.1.extract to fp128
   ret fp128 %0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @testMixedAggregate_03([4 x i128] %sa.coerce) {
 ; CHECK-LABEL: testMixedAggregate_03:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwa v2, r3
-; CHECK-NEXT:    mtvsrdd v3, r6, r5
-; CHECK-NEXT:    xscvsdqp v2, v2
-; CHECK-NEXT:    xsaddqp v2, v3, v2
-; CHECK-NEXT:    mtvsrd v3, r10
-; CHECK-NEXT:    xscvsdqp v3, v3
-; CHECK-NEXT:    xsaddqp v2, v2, v3
+; CHECK-NEXT:    mtvsrwa v2, r3 # Vec Defs: VF2(VSR2)
+; CHECK-NEXT:    mtvsrdd v3, r6, r5 # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    xscvsdqp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: VF2(VSR2)
+; CHECK-NEXT:    xsaddqp v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-NEXT:    mtvsrd v3, r10 # Vec Defs: VF3(VSR3)
+; CHECK-NEXT:    xscvsdqp v3, v3 # Vec Defs: V3(VSR35) Vec Uses: VF3(VSR3)
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testMixedAggregate_03:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrwa v2, r4
-; CHECK-BE-NEXT:    mtvsrdd v3, r6, r5
-; CHECK-BE-NEXT:    xscvsdqp v2, v2
-; CHECK-BE-NEXT:    xsaddqp v2, v3, v2
-; CHECK-BE-NEXT:    mtvsrd v3, r9
-; CHECK-BE-NEXT:    xscvsdqp v3, v3
-; CHECK-BE-NEXT:    xsaddqp v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwa v2, r4 # Vec Defs: VF2(VSR2)
+; CHECK-BE-NEXT:    mtvsrdd v3, r6, r5 # Vec Defs: V3(VSR35)
+; CHECK-BE-NEXT:    xscvsdqp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: VF2(VSR2)
+; CHECK-BE-NEXT:    xsaddqp v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-NEXT:    mtvsrd v3, r9 # Vec Defs: VF3(VSR3)
+; CHECK-BE-NEXT:    xscvsdqp v3, v3 # Vec Defs: V3(VSR35) Vec Uses: VF3(VSR3)
+; CHECK-BE-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testMixedAggregate_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -96(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 96
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    .cfi_offset v31, -32
 ; CHECK-P8-NEXT:    li r4, 64
 ; CHECK-P8-NEXT:    std r30, 80(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    extsw r3, r3
 ; CHECK-P8-NEXT:    mr r30, r10
 ; CHECK-P8-NEXT:    stvx v31, r1, r4 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
 ; CHECK-P8-NEXT:    addi r4, r1, 48
 ; CHECK-P8-NEXT:    std r6, 56(r1)
 ; CHECK-P8-NEXT:    std r5, 48(r1)
-; CHECK-P8-NEXT:    lvx v31, 0, r4
+; CHECK-P8-NEXT:    lvx v31, 0, r4 # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    bl __floatsikf
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v2
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    mr r3, r30
-; CHECK-P8-NEXT:    vmr v31, v2
+; CHECK-P8-NEXT:    vmr v31, v2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-P8-NEXT:    bl __floatdikf
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v2
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r3, 64
 ; CHECK-P8-NEXT:    ld r30, 80(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    addi r1, r1, 96
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %sa.coerce.fca.0.extract = extractvalue [4 x i128] %sa.coerce, 0
   %sa.sroa.0.0.extract.trunc = trunc i128 %sa.coerce.fca.0.extract to i32
   %sa.coerce.fca.1.extract = extractvalue [4 x i128] %sa.coerce, 1

 
 
 ; Function Attrs: norecurse nounwind readonly
 define fp128 @testNestedAggregate(%struct.MixedC* byval(%struct.MixedC) nocapture readonly align 16 %a) {
 ; CHECK-LABEL: testNestedAggregate:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    std r8, 72(r1)
 ; CHECK-NEXT:    std r7, 64(r1)
-; CHECK-NEXT:    lxv v2, 64(r1)
+; CHECK-NEXT:    lxv v2, 64(r1) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    std r3, 32(r1)
 ; CHECK-NEXT:    std r4, 40(r1)
 ; CHECK-NEXT:    std r5, 48(r1)
 ; CHECK-NEXT:    std r6, 56(r1)
 ; CHECK-NEXT:    std r9, 80(r1)
 ; CHECK-NEXT:    std r10, 88(r1)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testNestedAggregate:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    std r8, 88(r1)
 ; CHECK-BE-NEXT:    std r7, 80(r1)
-; CHECK-BE-NEXT:    lxv v2, 80(r1)
+; CHECK-BE-NEXT:    lxv v2, 80(r1) # Vec Defs: V2(VSR34)
 ; CHECK-BE-NEXT:    std r3, 48(r1)
 ; CHECK-BE-NEXT:    std r4, 56(r1)
 ; CHECK-BE-NEXT:    std r5, 64(r1)
 ; CHECK-BE-NEXT:    std r6, 72(r1)
 ; CHECK-BE-NEXT:    std r9, 96(r1)
 ; CHECK-BE-NEXT:    std r10, 104(r1)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testNestedAggregate:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    li r11, 32
 ; CHECK-P8-NEXT:    std r8, 72(r1)
 ; CHECK-P8-NEXT:    std r7, 64(r1)
 ; CHECK-P8-NEXT:    std r9, 80(r1)
 ; CHECK-P8-NEXT:    std r10, 88(r1)
 ; CHECK-P8-NEXT:    addi r7, r1, 32
-; CHECK-P8-NEXT:    lvx v2, r7, r11
+; CHECK-P8-NEXT:    lvx v2, r7, r11 # Vec Defs: V2(VSR34)
 ; CHECK-P8-NEXT:    std r3, 32(r1)
 ; CHECK-P8-NEXT:    std r4, 40(r1)
 ; CHECK-P8-NEXT:    std r5, 48(r1)
 ; CHECK-P8-NEXT:    std r6, 56(r1)
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %c = getelementptr inbounds %struct.MixedC, %struct.MixedC* %a, i64 0, i32 1, i32 1
   %0 = load fp128, fp128* %c, align 16
   ret fp128 %0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @testUnion_01([1 x i128] %a.coerce) {
 ; CHECK-LABEL: testUnion_01:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrdd v2, r4, r3
+; CHECK-NEXT:    mtvsrdd v2, r4, r3 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testUnion_01:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrdd v2, r4, r3
+; CHECK-BE-NEXT:    mtvsrdd v2, r4, r3 # Vec Defs: V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testUnion_01:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addi r5, r1, -16
 ; CHECK-P8-NEXT:    std r4, -8(r1)
 ; CHECK-P8-NEXT:    std r3, -16(r1)
-; CHECK-P8-NEXT:    lvx v2, 0, r5
+; CHECK-P8-NEXT:    lvx v2, 0, r5 # Vec Defs: V2(VSR34)
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.0.extract = extractvalue [1 x i128] %a.coerce, 0
   %0 = bitcast i128 %a.coerce.fca.0.extract to fp128
   ret fp128 %0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @testUnion_02([1 x i128] %a.coerce) {
 ; CHECK-LABEL: testUnion_02:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrdd v2, r4, r3
+; CHECK-NEXT:    mtvsrdd v2, r4, r3 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testUnion_02:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrdd v2, r4, r3
+; CHECK-BE-NEXT:    mtvsrdd v2, r4, r3 # Vec Defs: V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testUnion_02:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addi r5, r1, -16
 ; CHECK-P8-NEXT:    std r4, -8(r1)
 ; CHECK-P8-NEXT:    std r3, -16(r1)
-; CHECK-P8-NEXT:    lvx v2, 0, r5
+; CHECK-P8-NEXT:    lvx v2, 0, r5 # Vec Defs: V2(VSR34)
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.0.extract = extractvalue [1 x i128] %a.coerce, 0
   %0 = bitcast i128 %a.coerce.fca.0.extract to fp128
   ret fp128 %0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @testUnion_03([4 x i128] %a.coerce) {
 ; CHECK-LABEL: testUnion_03:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrdd v2, r8, r7
+; CHECK-NEXT:    mtvsrdd v2, r8, r7 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testUnion_03:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrdd v2, r8, r7
+; CHECK-BE-NEXT:    mtvsrdd v2, r8, r7 # Vec Defs: V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testUnion_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addi r3, r1, -16
 ; CHECK-P8-NEXT:    std r8, -8(r1)
 ; CHECK-P8-NEXT:    std r7, -16(r1)
-; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.2.extract = extractvalue [4 x i128] %a.coerce, 2
   %0 = bitcast i128 %a.coerce.fca.2.extract to fp128
   ret fp128 %0
 }
 
 ; Function Attrs: nounwind
 define fp128 @sum_float128(i32 signext %count, ...) {
 ; CHECK-LABEL: sum_float128:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    std r4, 40(r1)
 ; CHECK-NEXT:    addis r4, r2, .LCPI17_0@toc@ha
 ; CHECK-NEXT:    cmpwi r3, 1
 ; CHECK-NEXT:    std r5, 48(r1)
 ; CHECK-NEXT:    addi r4, r4, .LCPI17_0@toc@l
 ; CHECK-NEXT:    std r6, 56(r1)
 ; CHECK-NEXT:    std r7, 64(r1)
 ; CHECK-NEXT:    std r8, 72(r1)
-; CHECK-NEXT:    lxv v2, 0(r4)
+; CHECK-NEXT:    lxv v2, 0(r4) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    std r9, 80(r1)
 ; CHECK-NEXT:    std r10, 88(r1)
 ; CHECK-NEXT:    bltlr cr0
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    addi r3, r1, 40
 ; CHECK-NEXT:    addi r4, r1, 72
-; CHECK-NEXT:    lxvx v3, 0, r3
+; CHECK-NEXT:    lxvx v3, 0, r3 # Vec Defs: V3(VSR35)
 ; CHECK-NEXT:    std r4, -8(r1)
-; CHECK-NEXT:    xsaddqp v2, v3, v2
-; CHECK-NEXT:    lxv v3, 16(r3)
-; CHECK-NEXT:    xsaddqp v2, v2, v3
+; CHECK-NEXT:    xsaddqp v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-NEXT:    lxv v3, 16(r3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: sum_float128:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    std r4, 56(r1)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI17_0@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    std r5, 64(r1)
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI17_0@toc@l
 ; CHECK-BE-NEXT:    std r6, 72(r1)
 ; CHECK-BE-NEXT:    std r7, 80(r1)
 ; CHECK-BE-NEXT:    std r8, 88(r1)
-; CHECK-BE-NEXT:    lxv v2, 0(r4)
+; CHECK-BE-NEXT:    lxv v2, 0(r4) # Vec Defs: V2(VSR34)
 ; CHECK-BE-NEXT:    std r9, 96(r1)
 ; CHECK-BE-NEXT:    std r10, 104(r1)
 ; CHECK-BE-NEXT:    bltlr cr0
 ; CHECK-BE-NEXT:  # %bb.1: # %if.end
 ; CHECK-BE-NEXT:    addi r3, r1, 56
 ; CHECK-BE-NEXT:    addi r4, r1, 88
-; CHECK-BE-NEXT:    lxvx v3, 0, r3
+; CHECK-BE-NEXT:    lxvx v3, 0, r3 # Vec Defs: V3(VSR35)
 ; CHECK-BE-NEXT:    std r4, -8(r1)
-; CHECK-BE-NEXT:    xsaddqp v2, v3, v2
-; CHECK-BE-NEXT:    lxv v3, 16(r3)
-; CHECK-BE-NEXT:    xsaddqp v2, v2, v3
+; CHECK-BE-NEXT:    xsaddqp v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-NEXT:    lxv v3, 16(r3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: sum_float128:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -64(r1)
 ; CHECK-P8-NEXT:    addis r11, r2, .LCPI17_0@toc@ha
 ; CHECK-P8-NEXT:    cmpwi r3, 1
 ; CHECK-P8-NEXT:    std r4, 104(r1)
 ; CHECK-P8-NEXT:    std r5, 112(r1)
 ; CHECK-P8-NEXT:    std r6, 120(r1)
 ; CHECK-P8-NEXT:    std r7, 128(r1)
 ; CHECK-P8-NEXT:    addi r3, r11, .LCPI17_0@toc@l
 ; CHECK-P8-NEXT:    std r8, 136(r1)
 ; CHECK-P8-NEXT:    std r9, 144(r1)
 ; CHECK-P8-NEXT:    std r10, 152(r1)
 ; CHECK-P8-NEXT:    blt cr0, .LBB17_2
 ; CHECK-P8-NEXT:  # %bb.1: # %if.end
 ; CHECK-P8-NEXT:    addi r30, r1, 104
-; CHECK-P8-NEXT:    lvx v3, 0, r3
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r30
-; CHECK-P8-NEXT:    xxswapd v2, vs0
+; CHECK-P8-NEXT:    lvx v3, 0, r3 # Vec Defs: V3(VSR35)
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r30 # Vec Defs: VSL0(VSR0)
+; CHECK-P8-NEXT:    xxswapd v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r3, 16
-; CHECK-P8-NEXT:    lxvd2x vs0, r30, r3
+; CHECK-P8-NEXT:    lxvd2x vs0, r30, r3 # Vec Defs: VSL0(VSR0)
 ; CHECK-P8-NEXT:    addi r3, r1, 136
 ; CHECK-P8-NEXT:    std r3, 40(r1)
-; CHECK-P8-NEXT:    xxswapd v3, vs0
+; CHECK-P8-NEXT:    xxswapd v3, vs0 # Vec Defs: V3(VSR35) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    b .LBB17_3
 ; CHECK-P8-NEXT:  .LBB17_2:
-; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-P8-NEXT:  .LBB17_3: # %cleanup
 ; CHECK-P8-NEXT:    addi r1, r1, 64
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %ap = alloca i8*, align 8

llvm/test/CodeGen/PowerPC/f128-compare.ll

 
 ; Function Attrs: noinline nounwind optnone
 define dso_local signext i32 @greater_qp() {
 ; CHECK-LABEL: greater_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-NEXT:    li r4, 1
 ; CHECK-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    addis r3, r2, b_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, b_qp@toc@l
-; CHECK-NEXT:    lxv v3, 0(r3)
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
 ; CHECK-NEXT:    li r3, 0
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    iselgt r3, r4, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: greater_qp:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-P8-NEXT:    addis r4, r2, b_qp@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, a_qp@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, b_qp@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r4 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    bl __gtkf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    extsw r3, r3
 ; CHECK-P8-NEXT:    neg r3, r3
 ; CHECK-P8-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp ogt fp128 %0, %1
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 ; Function Attrs: noinline nounwind optnone
 define dso_local signext i32 @less_qp() {
 ; CHECK-LABEL: less_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-NEXT:    li r4, 1
 ; CHECK-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    addis r3, r2, b_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, b_qp@toc@l
-; CHECK-NEXT:    lxv v3, 0(r3)
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
 ; CHECK-NEXT:    li r3, 0
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    isellt r3, r4, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: less_qp:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-P8-NEXT:    addis r4, r2, b_qp@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, a_qp@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, b_qp@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r4 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    bl __ltkf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp olt fp128 %0, %1
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 ; Function Attrs: noinline nounwind optnone
 define dso_local signext i32 @greater_eq_qp() {
 ; CHECK-LABEL: greater_eq_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    addis r3, r2, b_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, b_qp@toc@l
-; CHECK-NEXT:    lxv v3, 0(r3)
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
 ; CHECK-NEXT:    li r3, 1
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    cror 4*cr5+lt, un, lt
 ; CHECK-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: greater_eq_qp:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-P8-NEXT:    addis r4, r2, b_qp@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, a_qp@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, b_qp@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r4 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    bl __gekf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; CHECK-P8-NEXT:    xori r3, r3, 1
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp oge fp128 %0, %1
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 ; Function Attrs: noinline nounwind optnone
 define dso_local signext i32 @less_eq_qp() {
 ; CHECK-LABEL: less_eq_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    addis r3, r2, b_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, b_qp@toc@l
-; CHECK-NEXT:    lxv v3, 0(r3)
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
 ; CHECK-NEXT:    li r3, 1
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    cror 4*cr5+lt, un, gt
 ; CHECK-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: less_eq_qp:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-P8-NEXT:    addis r4, r2, b_qp@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, a_qp@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, b_qp@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r4 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    bl __lekf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    extsw r3, r3
 ; CHECK-P8-NEXT:    neg r3, r3
 ; CHECK-P8-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-P8-NEXT:    xori r3, r3, 1
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)

 
 ; Function Attrs: noinline nounwind optnone
 define dso_local signext i32 @equal_qp() {
 ; CHECK-LABEL: equal_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-NEXT:    li r4, 1
 ; CHECK-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    addis r3, r2, b_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, b_qp@toc@l
-; CHECK-NEXT:    lxv v3, 0(r3)
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
 ; CHECK-NEXT:    li r3, 0
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    iseleq r3, r4, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: equal_qp:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-P8-NEXT:    addis r4, r2, b_qp@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, a_qp@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, b_qp@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r4 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    bl __eqkf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    cntlzw r3, r3
 ; CHECK-P8-NEXT:    srwi r3, r3, 5
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp oeq fp128 %0, %1
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 ; Function Attrs: noinline nounwind optnone
 define dso_local signext i32 @not_greater_qp() {
 ; CHECK-LABEL: not_greater_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    addis r3, r2, b_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, b_qp@toc@l
-; CHECK-NEXT:    lxv v3, 0(r3)
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
 ; CHECK-NEXT:    li r3, 1
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    iselgt r3, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: not_greater_qp:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-P8-NEXT:    addis r4, r2, b_qp@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, a_qp@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, b_qp@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r4 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    bl __gtkf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    extsw r3, r3
 ; CHECK-P8-NEXT:    neg r3, r3
 ; CHECK-P8-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-P8-NEXT:    xori r3, r3, 1
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)

 }
 
 ; Function Attrs: noinline nounwind optnone
 define dso_local signext i32 @not_less_qp() {
 ; CHECK-LABEL: not_less_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    addis r3, r2, b_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, b_qp@toc@l
-; CHECK-NEXT:    lxv v3, 0(r3)
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
 ; CHECK-NEXT:    li r3, 1
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    isellt r3, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: not_less_qp:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-P8-NEXT:    addis r4, r2, b_qp@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, a_qp@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, b_qp@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r4 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    bl __ltkf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; CHECK-P8-NEXT:    xori r3, r3, 1
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp olt fp128 %0, %1
   %lnot = xor i1 %cmp, true
   %lnot.ext = zext i1 %lnot to i32
   ret i32 %lnot.ext
 }
 
 ; Function Attrs: noinline nounwind optnone
 define dso_local signext i32 @not_greater_eq_qp() {
 ; CHECK-LABEL: not_greater_eq_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    addis r3, r2, b_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, b_qp@toc@l
-; CHECK-NEXT:    lxv v3, 0(r3)
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
 ; CHECK-NEXT:    li r3, 1
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    crnor 4*cr5+lt, lt, un
 ; CHECK-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: not_greater_eq_qp:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-P8-NEXT:    addis r4, r2, b_qp@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, a_qp@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, b_qp@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r4 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    bl __gekf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp oge fp128 %0, %1
   %lnot = xor i1 %cmp, true
   %lnot.ext = zext i1 %lnot to i32
   ret i32 %lnot.ext
 }
 
 ; Function Attrs: noinline nounwind optnone
 define dso_local signext i32 @not_less_eq_qp() {
 ; CHECK-LABEL: not_less_eq_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    addis r3, r2, b_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, b_qp@toc@l
-; CHECK-NEXT:    lxv v3, 0(r3)
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
 ; CHECK-NEXT:    li r3, 1
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    crnor 4*cr5+lt, gt, un
 ; CHECK-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: not_less_eq_qp:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-P8-NEXT:    addis r4, r2, b_qp@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, a_qp@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, b_qp@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r4 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    bl __lekf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    extsw r3, r3
 ; CHECK-P8-NEXT:    neg r3, r3
 ; CHECK-P8-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp ole fp128 %0, %1
   %lnot = xor i1 %cmp, true
   %lnot.ext = zext i1 %lnot to i32
   ret i32 %lnot.ext
 }
 
 ; Function Attrs: noinline nounwind optnone
 define dso_local signext i32 @not_equal_qp() {
 ; CHECK-LABEL: not_equal_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    addis r3, r2, b_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, b_qp@toc@l
-; CHECK-NEXT:    lxv v3, 0(r3)
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
 ; CHECK-NEXT:    li r3, 1
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    iseleq r3, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: not_equal_qp:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-P8-NEXT:    addis r4, r2, b_qp@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, a_qp@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, b_qp@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r4 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    bl __nekf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    cntlzw r3, r3
 ; CHECK-P8-NEXT:    srwi r3, r3, 5
 ; CHECK-P8-NEXT:    xori r3, r3, 1
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp une fp128 %0, %1
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define fp128 @greater_sel_qp() {
 ; CHECK-LABEL: greater_sel_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    addis r3, r2, b_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, b_qp@toc@l
-; CHECK-NEXT:    lxv v3, 0(r3)
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    bgtlr cr0
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    vmr v2, v3
+; CHECK-NEXT:    vmr v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: greater_sel_qp:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -80(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset v30, -32
 ; CHECK-P8-NEXT:    .cfi_offset v31, -16
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    addis r4, r2, b_qp@toc@ha
 ; CHECK-P8-NEXT:    stvx v30, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V30(VSR62)
 ; CHECK-P8-NEXT:    li r3, 64
 ; CHECK-P8-NEXT:    addi r4, r4, b_qp@toc@l
 ; CHECK-P8-NEXT:    stvx v31, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
 ; CHECK-P8-NEXT:    addis r3, r2, a_qp@toc@ha
-; CHECK-P8-NEXT:    lvx v30, 0, r4
+; CHECK-P8-NEXT:    lvx v30, 0, r4 # Vec Defs: V30(VSR62)
 ; CHECK-P8-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-P8-NEXT:    lvx v31, 0, r3
-; CHECK-P8-NEXT:    vmr v3, v30
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    lvx v31, 0, r3 # Vec Defs: V31(VSR63)
+; CHECK-P8-NEXT:    vmr v3, v30 # Vec Defs: V3(VSR35) Vec Uses: V30(VSR62)V30(VSR62)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __gtkf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    cmpwi r3, 0
 ; CHECK-P8-NEXT:    bgt cr0, .LBB10_2
 ; CHECK-P8-NEXT:  # %bb.1: # %entry
-; CHECK-P8-NEXT:    vmr v31, v30
+; CHECK-P8-NEXT:    vmr v31, v30 # Vec Defs: V31(VSR63) Vec Uses: V30(VSR62)V30(VSR62)
 ; CHECK-P8-NEXT:  .LBB10_2: # %entry
 ; CHECK-P8-NEXT:    li r3, 64
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    lvx v30, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V30(VSR62)
 ; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp ogt fp128 %0, %1
   %cond = select i1 %cmp, fp128 %0, fp128 %1
   ret fp128 %cond
 }
 
 ; Function Attrs: noinline nounwind optnone
 define fp128 @less_sel_qp() {
 ; CHECK-LABEL: less_sel_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    addis r3, r2, b_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, b_qp@toc@l
-; CHECK-NEXT:    lxv v3, 0(r3)
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    bltlr cr0
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    vmr v2, v3
+; CHECK-NEXT:    vmr v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: less_sel_qp:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -80(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset v30, -32
 ; CHECK-P8-NEXT:    .cfi_offset v31, -16
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    addis r4, r2, b_qp@toc@ha
 ; CHECK-P8-NEXT:    stvx v30, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V30(VSR62)
 ; CHECK-P8-NEXT:    li r3, 64
 ; CHECK-P8-NEXT:    addi r4, r4, b_qp@toc@l
 ; CHECK-P8-NEXT:    stvx v31, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
 ; CHECK-P8-NEXT:    addis r3, r2, a_qp@toc@ha
-; CHECK-P8-NEXT:    lvx v30, 0, r4
+; CHECK-P8-NEXT:    lvx v30, 0, r4 # Vec Defs: V30(VSR62)
 ; CHECK-P8-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-P8-NEXT:    lvx v31, 0, r3
-; CHECK-P8-NEXT:    vmr v3, v30
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    lvx v31, 0, r3 # Vec Defs: V31(VSR63)
+; CHECK-P8-NEXT:    vmr v3, v30 # Vec Defs: V3(VSR35) Vec Uses: V30(VSR62)V30(VSR62)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __ltkf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    cmpwi r3, 0
 ; CHECK-P8-NEXT:    blt cr0, .LBB11_2
 ; CHECK-P8-NEXT:  # %bb.1: # %entry
-; CHECK-P8-NEXT:    vmr v31, v30
+; CHECK-P8-NEXT:    vmr v31, v30 # Vec Defs: V31(VSR63) Vec Uses: V30(VSR62)V30(VSR62)
 ; CHECK-P8-NEXT:  .LBB11_2: # %entry
 ; CHECK-P8-NEXT:    li r3, 64
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    lvx v30, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V30(VSR62)
 ; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp olt fp128 %0, %1
   %cond = select i1 %cmp, fp128 %0, fp128 %1
   ret fp128 %cond
 }
 
 ; Function Attrs: noinline nounwind optnone
 define fp128 @greater_eq_sel_qp() {
 ; CHECK-LABEL: greater_eq_sel_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    addis r3, r2, b_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, b_qp@toc@l
-; CHECK-NEXT:    lxv v3, 0(r3)
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    crnor 4*cr5+lt, un, lt
 ; CHECK-NEXT:    bclr 12, 4*cr5+lt, 0
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    vmr v2, v3
+; CHECK-NEXT:    vmr v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: greater_eq_sel_qp:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -80(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset v30, -32
 ; CHECK-P8-NEXT:    .cfi_offset v31, -16
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    addis r4, r2, b_qp@toc@ha
 ; CHECK-P8-NEXT:    stvx v30, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V30(VSR62)
 ; CHECK-P8-NEXT:    li r3, 64
 ; CHECK-P8-NEXT:    addi r4, r4, b_qp@toc@l
 ; CHECK-P8-NEXT:    stvx v31, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
 ; CHECK-P8-NEXT:    addis r3, r2, a_qp@toc@ha
-; CHECK-P8-NEXT:    lvx v30, 0, r4
+; CHECK-P8-NEXT:    lvx v30, 0, r4 # Vec Defs: V30(VSR62)
 ; CHECK-P8-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-P8-NEXT:    lvx v31, 0, r3
-; CHECK-P8-NEXT:    vmr v3, v30
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    lvx v31, 0, r3 # Vec Defs: V31(VSR63)
+; CHECK-P8-NEXT:    vmr v3, v30 # Vec Defs: V3(VSR35) Vec Uses: V30(VSR62)V30(VSR62)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __gekf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    cmpwi r3, -1
 ; CHECK-P8-NEXT:    bgt cr0, .LBB12_2
 ; CHECK-P8-NEXT:  # %bb.1: # %entry
-; CHECK-P8-NEXT:    vmr v31, v30
+; CHECK-P8-NEXT:    vmr v31, v30 # Vec Defs: V31(VSR63) Vec Uses: V30(VSR62)V30(VSR62)
 ; CHECK-P8-NEXT:  .LBB12_2: # %entry
 ; CHECK-P8-NEXT:    li r3, 64
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    lvx v30, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V30(VSR62)
 ; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp oge fp128 %0, %1
   %cond = select i1 %cmp, fp128 %0, fp128 %1
   ret fp128 %cond
 }
 
 ; Function Attrs: noinline nounwind optnone
 define fp128 @less_eq_sel_qp() {
 ; CHECK-LABEL: less_eq_sel_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    addis r3, r2, b_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, b_qp@toc@l
-; CHECK-NEXT:    lxv v3, 0(r3)
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    crnor 4*cr5+lt, un, gt
 ; CHECK-NEXT:    bclr 12, 4*cr5+lt, 0
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    vmr v2, v3
+; CHECK-NEXT:    vmr v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: less_eq_sel_qp:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -80(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset v30, -32
 ; CHECK-P8-NEXT:    .cfi_offset v31, -16
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    addis r4, r2, b_qp@toc@ha
 ; CHECK-P8-NEXT:    stvx v30, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V30(VSR62)
 ; CHECK-P8-NEXT:    li r3, 64
 ; CHECK-P8-NEXT:    addi r4, r4, b_qp@toc@l
 ; CHECK-P8-NEXT:    stvx v31, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
 ; CHECK-P8-NEXT:    addis r3, r2, a_qp@toc@ha
-; CHECK-P8-NEXT:    lvx v30, 0, r4
+; CHECK-P8-NEXT:    lvx v30, 0, r4 # Vec Defs: V30(VSR62)
 ; CHECK-P8-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-P8-NEXT:    lvx v31, 0, r3
-; CHECK-P8-NEXT:    vmr v3, v30
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    lvx v31, 0, r3 # Vec Defs: V31(VSR63)
+; CHECK-P8-NEXT:    vmr v3, v30 # Vec Defs: V3(VSR35) Vec Uses: V30(VSR62)V30(VSR62)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __lekf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    cmpwi r3, 1
 ; CHECK-P8-NEXT:    blt cr0, .LBB13_2
 ; CHECK-P8-NEXT:  # %bb.1: # %entry
-; CHECK-P8-NEXT:    vmr v31, v30
+; CHECK-P8-NEXT:    vmr v31, v30 # Vec Defs: V31(VSR63) Vec Uses: V30(VSR62)V30(VSR62)
 ; CHECK-P8-NEXT:  .LBB13_2: # %entry
 ; CHECK-P8-NEXT:    li r3, 64
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    lvx v30, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V30(VSR62)
 ; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp ole fp128 %0, %1
   %cond = select i1 %cmp, fp128 %0, fp128 %1
   ret fp128 %cond
 }
 
 ; Function Attrs: noinline nounwind optnone
 define fp128 @equal_sel_qp() {
 ; CHECK-LABEL: equal_sel_qp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, a_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    addis r3, r2, b_qp@toc@ha
 ; CHECK-NEXT:    addi r3, r3, b_qp@toc@l
-; CHECK-NEXT:    lxv v3, 0(r3)
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    beqlr cr0
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    vmr v2, v3
+; CHECK-NEXT:    vmr v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: equal_sel_qp:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -80(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset v30, -32
 ; CHECK-P8-NEXT:    .cfi_offset v31, -16
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    addis r4, r2, b_qp@toc@ha
 ; CHECK-P8-NEXT:    stvx v30, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V30(VSR62)
 ; CHECK-P8-NEXT:    li r3, 64
 ; CHECK-P8-NEXT:    addi r4, r4, b_qp@toc@l
 ; CHECK-P8-NEXT:    stvx v31, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
 ; CHECK-P8-NEXT:    addis r3, r2, a_qp@toc@ha
-; CHECK-P8-NEXT:    lvx v30, 0, r4
+; CHECK-P8-NEXT:    lvx v30, 0, r4 # Vec Defs: V30(VSR62)
 ; CHECK-P8-NEXT:    addi r3, r3, a_qp@toc@l
-; CHECK-P8-NEXT:    lvx v31, 0, r3
-; CHECK-P8-NEXT:    vmr v3, v30
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    lvx v31, 0, r3 # Vec Defs: V31(VSR63)
+; CHECK-P8-NEXT:    vmr v3, v30 # Vec Defs: V3(VSR35) Vec Uses: V30(VSR62)V30(VSR62)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __eqkf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    cmplwi r3, 0
 ; CHECK-P8-NEXT:    beq cr0, .LBB14_2
 ; CHECK-P8-NEXT:  # %bb.1: # %entry
-; CHECK-P8-NEXT:    vmr v31, v30
+; CHECK-P8-NEXT:    vmr v31, v30 # Vec Defs: V31(VSR63) Vec Uses: V30(VSR62)V30(VSR62)
 ; CHECK-P8-NEXT:  .LBB14_2: # %entry
 ; CHECK-P8-NEXT:    li r3, 64
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    lvx v30, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V30(VSR62)
 ; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp oeq fp128 %0, %1
   %cond = select i1 %cmp, fp128 %0, fp128 %1
   ret fp128 %cond
 }

llvm/test/CodeGen/PowerPC/f128-fma.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
 ; RUN:   -check-prefix=CHECK-P8
 
 define void @qpFmadd(fp128* nocapture readonly %a, fp128* nocapture %b,
 ; CHECK-LABEL: qpFmadd:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv v2, 0(r3)
-; CHECK-NEXT:    lxv v3, 0(r4)
-; CHECK-NEXT:    lxv v4, 0(r5)
-; CHECK-NEXT:    xsmaddqp v4, v2, v3
-; CHECK-NEXT:    stxv v4, 0(r6)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    lxv v3, 0(r4) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    lxv v4, 0(r5) # Vec Defs: V4(VSR36)
+; CHECK-NEXT:    xsmaddqp v4, v2, v3 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
+; CHECK-NEXT:    stxv v4, 0(r6) # Vec Uses: V4(VSR36)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpFmadd:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -80(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    .cfi_offset v31, -32
 ; CHECK-P8-NEXT:    li r7, 48
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r4 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    mr r30, r6
 ; CHECK-P8-NEXT:    stvx v31, r1, r7 # 16-byte Folded Spill
-; CHECK-P8-NEXT:    lvx v31, 0, r5
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
+; CHECK-P8-NEXT:    lvx v31, 0, r5 # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v31
+; CHECK-P8-NEXT:    vmr v3, v31 # Vec Defs: V3(VSR35) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r3, 48
-; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    stvx v2, 0, r30 # Vec Uses: V2(VSR34)
 ; CHECK-P8-NEXT:    ld r30, 64(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                    fp128* nocapture readonly %c, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %2 = load fp128, fp128* %c, align 16
   %madd = tail call fp128 @llvm.fmuladd.f128(fp128 %0, fp128 %1, fp128 %2)
   store fp128 %madd, fp128* %res, align 16
   ret void
 }
 declare fp128 @llvm.fmuladd.f128(fp128, fp128, fp128)
 
 ; Function Attrs: norecurse nounwind
 define void @qpFmadd_02(fp128* nocapture readonly %a,
 ; CHECK-LABEL: qpFmadd_02:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv v2, 0(r3)
-; CHECK-NEXT:    lxv v3, 0(r4)
-; CHECK-NEXT:    lxv v4, 0(r5)
-; CHECK-NEXT:    xsmaddqp v2, v3, v4
-; CHECK-NEXT:    stxv v2, 0(r6)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    lxv v3, 0(r4) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    lxv v4, 0(r5) # Vec Defs: V4(VSR36)
+; CHECK-NEXT:    xsmaddqp v2, v3, v4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)V4(VSR36)
+; CHECK-NEXT:    stxv v2, 0(r6) # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpFmadd_02:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -80(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    .cfi_offset v31, -32
 ; CHECK-P8-NEXT:    li r7, 48
-; CHECK-P8-NEXT:    lvx v2, 0, r4
-; CHECK-P8-NEXT:    lvx v3, 0, r5
+; CHECK-P8-NEXT:    lvx v2, 0, r4 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r5 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    mr r30, r6
 ; CHECK-P8-NEXT:    stvx v31, r1, r7 # 16-byte Folded Spill
-; CHECK-P8-NEXT:    lvx v31, 0, r3
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
+; CHECK-P8-NEXT:    lvx v31, 0, r3 # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v2
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r3, 48
-; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    stvx v2, 0, r30 # Vec Uses: V2(VSR34)
 ; CHECK-P8-NEXT:    ld r30, 64(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                         fp128* nocapture readonly %b,
                         fp128* nocapture readonly %c, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %2 = load fp128, fp128* %c, align 16
   %mul = fmul contract fp128 %1, %2
   %add = fadd contract fp128 %0, %mul
   store fp128 %add, fp128* %res, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind
 define void @qpFmadd_03(fp128* nocapture readonly %a,
 ; CHECK-LABEL: qpFmadd_03:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv v2, 0(r3)
-; CHECK-NEXT:    lxv v3, 0(r4)
-; CHECK-NEXT:    lxv v4, 0(r5)
-; CHECK-NEXT:    xsmaddqp v4, v2, v3
-; CHECK-NEXT:    stxv v4, 0(r6)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    lxv v3, 0(r4) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    lxv v4, 0(r5) # Vec Defs: V4(VSR36)
+; CHECK-NEXT:    xsmaddqp v4, v2, v3 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
+; CHECK-NEXT:    stxv v4, 0(r6) # Vec Uses: V4(VSR36)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpFmadd_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -64(r1)
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r4 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    mr r30, r6
 ; CHECK-P8-NEXT:    mr r29, r5
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    lvx v3, 0, r29
+; CHECK-P8-NEXT:    lvx v3, 0, r29 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    stvx v2, 0, r30 # Vec Uses: V2(VSR34)
 ; CHECK-P8-NEXT:    addi r1, r1, 64
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                         fp128* nocapture readonly %b,
                         fp128* nocapture readonly %c, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %mul = fmul contract fp128 %0, %1
   %2 = load fp128, fp128* %c, align 16
   %add = fadd contract fp128 %mul, %2
   store fp128 %add, fp128* %res, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind
 define void @qpFnmadd(fp128* nocapture readonly %a,
 ; CHECK-LABEL: qpFnmadd:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv v2, 0(r3)
-; CHECK-NEXT:    lxv v3, 0(r4)
-; CHECK-NEXT:    lxv v4, 0(r5)
-; CHECK-NEXT:    xsnmaddqp v2, v3, v4
-; CHECK-NEXT:    stxv v2, 0(r6)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    lxv v3, 0(r4) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    lxv v4, 0(r5) # Vec Defs: V4(VSR36)
+; CHECK-NEXT:    xsnmaddqp v2, v3, v4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)V4(VSR36)
+; CHECK-NEXT:    stxv v2, 0(r6) # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpFnmadd:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -96(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 96
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    .cfi_offset v31, -32
 ; CHECK-P8-NEXT:    li r7, 64
-; CHECK-P8-NEXT:    lvx v2, 0, r4
-; CHECK-P8-NEXT:    lvx v3, 0, r5
+; CHECK-P8-NEXT:    lvx v2, 0, r4 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r5 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    std r30, 80(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    mr r30, r6
 ; CHECK-P8-NEXT:    stvx v31, r1, r7 # 16-byte Folded Spill
-; CHECK-P8-NEXT:    lvx v31, 0, r3
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
+; CHECK-P8-NEXT:    lvx v31, 0, r3 # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v2
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r3, r1, 48
-; CHECK-P8-NEXT:    stvx v2, 0, r3
+; CHECK-P8-NEXT:    stvx v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-P8-NEXT:    lbz r4, 63(r1)
 ; CHECK-P8-NEXT:    xori r4, r4, 128
 ; CHECK-P8-NEXT:    stb r4, 63(r1)
-; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-P8-NEXT:    li r3, 64
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
-; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
+; CHECK-P8-NEXT:    stvx v2, 0, r30 # Vec Uses: V2(VSR34)
 ; CHECK-P8-NEXT:    ld r30, 80(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    addi r1, r1, 96
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                       fp128* nocapture readonly %b,
                       fp128* nocapture readonly %c, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %2 = load fp128, fp128* %c, align 16
   %mul = fmul contract fp128 %1, %2
   %add = fadd contract fp128 %0, %mul
   %sub = fsub fp128 0xL00000000000000008000000000000000, %add
   store fp128 %sub, fp128* %res, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind
 define void @qpFnmadd_02(fp128* nocapture readonly %a,
 ; CHECK-LABEL: qpFnmadd_02:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv v2, 0(r3)
-; CHECK-NEXT:    lxv v3, 0(r4)
-; CHECK-NEXT:    lxv v4, 0(r5)
-; CHECK-NEXT:    xsnmaddqp v4, v2, v3
-; CHECK-NEXT:    stxv v4, 0(r6)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    lxv v3, 0(r4) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    lxv v4, 0(r5) # Vec Defs: V4(VSR36)
+; CHECK-NEXT:    xsnmaddqp v4, v2, v3 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
+; CHECK-NEXT:    stxv v4, 0(r6) # Vec Uses: V4(VSR36)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpFnmadd_02:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -80(r1)
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r4 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    mr r30, r6
 ; CHECK-P8-NEXT:    mr r29, r5
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    lvx v3, 0, r29
+; CHECK-P8-NEXT:    lvx v3, 0, r29 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r3, r1, 32
-; CHECK-P8-NEXT:    stvx v2, 0, r3
+; CHECK-P8-NEXT:    stvx v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-P8-NEXT:    lbz r4, 47(r1)
 ; CHECK-P8-NEXT:    xori r4, r4, 128
 ; CHECK-P8-NEXT:    stb r4, 47(r1)
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    stvx v2, 0, r30 # Vec Uses: V2(VSR34)
 ; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                       fp128* nocapture readonly %b,
                       fp128* nocapture readonly %c, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %mul = fmul contract fp128 %0, %1
   %2 = load fp128, fp128* %c, align 16
   %add = fadd contract fp128 %mul, %2
   %sub = fsub fp128 0xL00000000000000008000000000000000, %add
   store fp128 %sub, fp128* %res, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind
 define void @qpFmsub(fp128* nocapture readonly %a,
 ; CHECK-LABEL: qpFmsub:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv v2, 0(r3)
-; CHECK-NEXT:    lxv v3, 0(r4)
-; CHECK-NEXT:    lxv v4, 0(r5)
-; CHECK-NEXT:    xsnmsubqp v2, v3, v4
-; CHECK-NEXT:    stxv v2, 0(r6)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    lxv v3, 0(r4) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    lxv v4, 0(r5) # Vec Defs: V4(VSR36)
+; CHECK-NEXT:    xsnmsubqp v2, v3, v4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)V4(VSR36)
+; CHECK-NEXT:    stxv v2, 0(r6) # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpFmsub:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -80(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    .cfi_offset v31, -32
 ; CHECK-P8-NEXT:    li r7, 48
-; CHECK-P8-NEXT:    lvx v2, 0, r4
-; CHECK-P8-NEXT:    lvx v3, 0, r5
+; CHECK-P8-NEXT:    lvx v2, 0, r4 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r5 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    mr r30, r6
 ; CHECK-P8-NEXT:    stvx v31, r1, r7 # 16-byte Folded Spill
-; CHECK-P8-NEXT:    lvx v31, 0, r3
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
+; CHECK-P8-NEXT:    lvx v31, 0, r3 # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v2
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __subkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r3, 48
-; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    stvx v2, 0, r30 # Vec Uses: V2(VSR34)
 ; CHECK-P8-NEXT:    ld r30, 64(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                       fp128* nocapture readonly %b,
                       fp128* nocapture readonly %c, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %2 = load fp128, fp128* %c, align 16
   %mul = fmul contract fp128 %1, %2
   %sub = fsub contract nsz fp128 %0, %mul
   store fp128 %sub, fp128* %res, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind
 define void @qpFmsub_02(fp128* nocapture readonly %a,
 ; CHECK-LABEL: qpFmsub_02:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv v2, 0(r3)
-; CHECK-NEXT:    lxv v3, 0(r4)
-; CHECK-NEXT:    lxv v4, 0(r5)
-; CHECK-NEXT:    xsmsubqp v4, v2, v3
-; CHECK-NEXT:    stxv v4, 0(r6)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    lxv v3, 0(r4) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    lxv v4, 0(r5) # Vec Defs: V4(VSR36)
+; CHECK-NEXT:    xsmsubqp v4, v2, v3 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
+; CHECK-NEXT:    stxv v4, 0(r6) # Vec Uses: V4(VSR36)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpFmsub_02:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -64(r1)
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r4 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    mr r30, r6
 ; CHECK-P8-NEXT:    mr r29, r5
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    lvx v3, 0, r29
+; CHECK-P8-NEXT:    lvx v3, 0, r29 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    bl __subkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    stvx v2, 0, r30 # Vec Uses: V2(VSR34)
 ; CHECK-P8-NEXT:    addi r1, r1, 64
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                       fp128* nocapture readonly %b,
                       fp128* nocapture readonly %c, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %mul = fmul contract fp128 %0, %1
   %2 = load fp128, fp128* %c, align 16
   %sub = fsub contract fp128 %mul, %2
   store fp128 %sub, fp128* %res, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind
 define void @qpFnmsub(fp128* nocapture readonly %a,
 ; CHECK-LABEL: qpFnmsub:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv v3, 0(r4)
-; CHECK-NEXT:    lxv v2, 0(r3)
-; CHECK-NEXT:    lxv v4, 0(r5)
-; CHECK-NEXT:    xsnegqp v3, v3
-; CHECK-NEXT:    xsnmaddqp v2, v3, v4
-; CHECK-NEXT:    stxv v2, 0(r6)
+; CHECK-NEXT:    lxv v3, 0(r4) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    lxv v4, 0(r5) # Vec Defs: V4(VSR36)
+; CHECK-NEXT:    xsnegqp v3, v3 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)
+; CHECK-NEXT:    xsnmaddqp v2, v3, v4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)V4(VSR36)
+; CHECK-NEXT:    stxv v2, 0(r6) # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpFnmsub:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -96(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 96
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    .cfi_offset v31, -32
 ; CHECK-P8-NEXT:    li r7, 64
-; CHECK-P8-NEXT:    lvx v2, 0, r4
-; CHECK-P8-NEXT:    lvx v3, 0, r5
+; CHECK-P8-NEXT:    lvx v2, 0, r4 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r5 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    std r30, 80(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    mr r30, r6
 ; CHECK-P8-NEXT:    stvx v31, r1, r7 # 16-byte Folded Spill
-; CHECK-P8-NEXT:    lvx v31, 0, r3
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
+; CHECK-P8-NEXT:    lvx v31, 0, r3 # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v2
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __subkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r3, r1, 48
-; CHECK-P8-NEXT:    stvx v2, 0, r3
+; CHECK-P8-NEXT:    stvx v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-P8-NEXT:    lbz r4, 63(r1)
 ; CHECK-P8-NEXT:    xori r4, r4, 128
 ; CHECK-P8-NEXT:    stb r4, 63(r1)
-; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-P8-NEXT:    li r3, 64
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
-; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
+; CHECK-P8-NEXT:    stvx v2, 0, r30 # Vec Uses: V2(VSR34)
 ; CHECK-P8-NEXT:    ld r30, 80(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    addi r1, r1, 96
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                       fp128* nocapture readonly %b,
                       fp128* nocapture readonly %c, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %2 = load fp128, fp128* %c, align 16
   %mul = fmul contract fp128 %1, %2
   %sub = fsub contract fp128 %0, %mul
   %sub1 = fsub fp128 0xL00000000000000008000000000000000, %sub
   store fp128 %sub1, fp128* %res, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind
 define void @qpFnmsub_02(fp128* nocapture readonly %a,
 ; CHECK-LABEL: qpFnmsub_02:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv v2, 0(r3)
-; CHECK-NEXT:    lxv v3, 0(r4)
-; CHECK-NEXT:    lxv v4, 0(r5)
-; CHECK-NEXT:    xsnmsubqp v4, v2, v3
-; CHECK-NEXT:    stxv v4, 0(r6)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    lxv v3, 0(r4) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    lxv v4, 0(r5) # Vec Defs: V4(VSR36)
+; CHECK-NEXT:    xsnmsubqp v4, v2, v3 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
+; CHECK-NEXT:    stxv v4, 0(r6) # Vec Uses: V4(VSR36)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpFnmsub_02:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -80(r1)
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    lvx v3, 0, r4 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    mr r30, r6
 ; CHECK-P8-NEXT:    mr r29, r5
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    lvx v3, 0, r29
+; CHECK-P8-NEXT:    lvx v3, 0, r29 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    bl __subkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r3, r1, 32
-; CHECK-P8-NEXT:    stvx v2, 0, r3
+; CHECK-P8-NEXT:    stvx v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-P8-NEXT:    lbz r4, 47(r1)
 ; CHECK-P8-NEXT:    xori r4, r4, 128
 ; CHECK-P8-NEXT:    stb r4, 47(r1)
-; CHECK-P8-NEXT:    lvx v2, 0, r3
-; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-P8-NEXT:    stvx v2, 0, r30 # Vec Uses: V2(VSR34)
 ; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                       fp128* nocapture readonly %b,
                       fp128* nocapture readonly %c, fp128* nocapture %res) {

llvm/test/CodeGen/PowerPC/f128-passByValue.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
 ; RUN:   -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s
 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
 ; RUN:   -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s \
 ; RUN:   -check-prefix=CHECK-P8
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @loadConstant() {
 ; CHECK-LABEL: loadConstant:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: loadConstant:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-P8-NEXT:    blr
   entry:
     ret fp128 0xL00000000000000004001400000000000
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @loadConstant2(fp128 %a, fp128 %b) {
 ; CHECK-LABEL: loadConstant2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xsaddqp v2, v2, v3
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; CHECK-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-NEXT:    lxv v3, 0(r3)
-; CHECK-NEXT:    xsaddqp v2, v2, v3
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: loadConstant2:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-P8-NEXT:    lvx v3, 0, r3
+; CHECK-P8-NEXT:    lvx v3, 0, r3 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
   entry:
     %add = fadd fp128 %a, %b
       %add1 = fadd fp128 %add, 0xL00000000000000004001400000000000
         ret fp128 %add1
 }
 
 ; Test passing float128 by value.
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @fp128Param(fp128 %a) {
 ; CHECK-LABEL: fp128Param:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xscvqpswz v2, v2
-; CHECK-NEXT:    mfvsrwz r3, v2
+; CHECK-NEXT:    xscvqpswz v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
+; CHECK-NEXT:    mfvsrwz r3, v2 # Vec Uses: VF2(VSR2)
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: fp128Param:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
entry:
   ret i32 %conv
 }
 
 ; Test float128 as return value.
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @fp128Return(fp128 %a, fp128 %b) {
 ; CHECK-LABEL: fp128Return:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xsaddqp v2, v2, v3
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: fp128Return:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32

 }
 
 ; array of float128 types
 ; Function Attrs: norecurse nounwind readonly
 define fp128 @fp128Array(fp128* nocapture readonly %farray,
 ; CHECK-LABEL: fp128Array:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sldi r4, r4, 4
-; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    add r3, r3, r4
-; CHECK-NEXT:    lxv v3, -16(r3)
-; CHECK-NEXT:    xsaddqp v2, v2, v3
+; CHECK-NEXT:    lxv v3, -16(r3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: fp128Array:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    sldi r4, r4, 4
-; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-P8-NEXT:    add r4, r3, r4
 ; CHECK-P8-NEXT:    addi r4, r4, -16
-; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v3, 0, r4 # Vec Defs: V3(VSR35)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                          i32 signext %loopcnt, fp128* nocapture readnone %sum) {
 entry:
   %0 = load fp128, fp128* %farray, align 16
   %sub = add nsw i32 %loopcnt, -1
   %idxprom = sext i32 %sub to i64
   %arrayidx1 = getelementptr inbounds fp128, fp128* %farray, i64 %idxprom
   %1 = load fp128, fp128* %arrayidx1, align 16
   %add = fadd fp128 %0, %1
   ret fp128 %add
 }
 
 ; Up to 12 qualified floating-point arguments can be passed in v2-v13.
 ; Function to test passing 13 float128 parameters.
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @maxVecParam(fp128 %p1, fp128 %p2, fp128 %p3, fp128 %p4, fp128 %p5,
 ; CHECK-LABEL: maxVecParam:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xsaddqp v2, v2, v3
-; CHECK-NEXT:    lxv v0, 224(r1)
-; CHECK-NEXT:    xsaddqp v2, v2, v4
-; CHECK-NEXT:    xsaddqp v2, v2, v5
-; CHECK-NEXT:    xsaddqp v2, v2, v6
-; CHECK-NEXT:    xsaddqp v2, v2, v7
-; CHECK-NEXT:    xsaddqp v2, v2, v8
-; CHECK-NEXT:    xsaddqp v2, v2, v9
-; CHECK-NEXT:    xsaddqp v2, v2, v10
-; CHECK-NEXT:    xsaddqp v2, v2, v11
-; CHECK-NEXT:    xsaddqp v2, v2, v12
-; CHECK-NEXT:    xsaddqp v2, v2, v13
-; CHECK-NEXT:    xssubqp v2, v2, v0
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-NEXT:    lxv v0, 224(r1) # Vec Defs: V0(VSR32)
+; CHECK-NEXT:    xsaddqp v2, v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
+; CHECK-NEXT:    xsaddqp v2, v2, v5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V5(VSR37)
+; CHECK-NEXT:    xsaddqp v2, v2, v6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V6(VSR38)
+; CHECK-NEXT:    xsaddqp v2, v2, v7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V7(VSR39)
+; CHECK-NEXT:    xsaddqp v2, v2, v8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V8(VSR40)
+; CHECK-NEXT:    xsaddqp v2, v2, v9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V9(VSR41)
+; CHECK-NEXT:    xsaddqp v2, v2, v10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V10(VSR42)
+; CHECK-NEXT:    xsaddqp v2, v2, v11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V11(VSR43)
+; CHECK-NEXT:    xsaddqp v2, v2, v12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V12(VSR44)
+; CHECK-NEXT:    xsaddqp v2, v2, v13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V13(VSR45)
+; CHECK-NEXT:    xssubqp v2, v2, v0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V0(VSR32)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: maxVecParam:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -224(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 224
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset v21, -176
 ; CHECK-P8-NEXT:    .cfi_offset v22, -160
 ; CHECK-P8-NEXT:    .cfi_offset v23, -144
 ; CHECK-P8-NEXT:    .cfi_offset v24, -128
 ; CHECK-P8-NEXT:    .cfi_offset v25, -112
 ; CHECK-P8-NEXT:    .cfi_offset v26, -96
 ; CHECK-P8-NEXT:    .cfi_offset v27, -80
 ; CHECK-P8-NEXT:    .cfi_offset v28, -64
 ; CHECK-P8-NEXT:    .cfi_offset v29, -48
 ; CHECK-P8-NEXT:    .cfi_offset v30, -32
 ; CHECK-P8-NEXT:    .cfi_offset v31, -16
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    stvx v21, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V21(VSR53)
 ; CHECK-P8-NEXT:    li r3, 64
-; CHECK-P8-NEXT:    vmr v21, v4
+; CHECK-P8-NEXT:    vmr v21, v4 # Vec Defs: V21(VSR53) Vec Uses: V4(VSR36)V4(VSR36)
 ; CHECK-P8-NEXT:    stvx v22, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V22(VSR54)
 ; CHECK-P8-NEXT:    li r3, 80
-; CHECK-P8-NEXT:    vmr v22, v5
+; CHECK-P8-NEXT:    vmr v22, v5 # Vec Defs: V22(VSR54) Vec Uses: V5(VSR37)V5(VSR37)
 ; CHECK-P8-NEXT:    stvx v23, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V23(VSR55)
 ; CHECK-P8-NEXT:    li r3, 96
-; CHECK-P8-NEXT:    vmr v23, v6
+; CHECK-P8-NEXT:    vmr v23, v6 # Vec Defs: V23(VSR55) Vec Uses: V6(VSR38)V6(VSR38)
 ; CHECK-P8-NEXT:    stvx v24, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V24(VSR56)
 ; CHECK-P8-NEXT:    li r3, 112
-; CHECK-P8-NEXT:    vmr v24, v7
+; CHECK-P8-NEXT:    vmr v24, v7 # Vec Defs: V24(VSR56) Vec Uses: V7(VSR39)V7(VSR39)
 ; CHECK-P8-NEXT:    stvx v25, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V25(VSR57)
 ; CHECK-P8-NEXT:    li r3, 128
-; CHECK-P8-NEXT:    vmr v25, v8
+; CHECK-P8-NEXT:    vmr v25, v8 # Vec Defs: V25(VSR57) Vec Uses: V8(VSR40)V8(VSR40)
 ; CHECK-P8-NEXT:    stvx v26, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V26(VSR58)
 ; CHECK-P8-NEXT:    li r3, 144
-; CHECK-P8-NEXT:    vmr v26, v9
+; CHECK-P8-NEXT:    vmr v26, v9 # Vec Defs: V26(VSR58) Vec Uses: V9(VSR41)V9(VSR41)
 ; CHECK-P8-NEXT:    stvx v27, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V27(VSR59)
 ; CHECK-P8-NEXT:    li r3, 160
-; CHECK-P8-NEXT:    vmr v27, v10
+; CHECK-P8-NEXT:    vmr v27, v10 # Vec Defs: V27(VSR59) Vec Uses: V10(VSR42)V10(VSR42)
 ; CHECK-P8-NEXT:    stvx v28, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V28(VSR60)
 ; CHECK-P8-NEXT:    li r3, 176
-; CHECK-P8-NEXT:    vmr v28, v11
+; CHECK-P8-NEXT:    vmr v28, v11 # Vec Defs: V28(VSR60) Vec Uses: V11(VSR43)V11(VSR43)
 ; CHECK-P8-NEXT:    stvx v29, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V29(VSR61)
 ; CHECK-P8-NEXT:    li r3, 192
 ; CHECK-P8-NEXT:    stvx v30, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V30(VSR62)
 ; CHECK-P8-NEXT:    li r3, 208
-; CHECK-P8-NEXT:    vmr v30, v12
+; CHECK-P8-NEXT:    vmr v30, v12 # Vec Defs: V30(VSR62) Vec Uses: V12(VSR44)V12(VSR44)
 ; CHECK-P8-NEXT:    stvx v31, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
 ; CHECK-P8-NEXT:    addi r3, r1, 448
-; CHECK-P8-NEXT:    vmr v31, v13
-; CHECK-P8-NEXT:    lvx v29, 0, r3
+; CHECK-P8-NEXT:    vmr v31, v13 # Vec Defs: V31(VSR63) Vec Uses: V13(VSR45)V13(VSR45)
+; CHECK-P8-NEXT:    lvx v29, 0, r3 # Vec Defs: V29(VSR61)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v21
+; CHECK-P8-NEXT:    vmr v3, v21 # Vec Defs: V3(VSR35) Vec Uses: V21(VSR53)V21(VSR53)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v22
+; CHECK-P8-NEXT:    vmr v3, v22 # Vec Defs: V3(VSR35) Vec Uses: V22(VSR54)V22(VSR54)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v23
+; CHECK-P8-NEXT:    vmr v3, v23 # Vec Defs: V3(VSR35) Vec Uses: V23(VSR55)V23(VSR55)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v24
+; CHECK-P8-NEXT:    vmr v3, v24 # Vec Defs: V3(VSR35) Vec Uses: V24(VSR56)V24(VSR56)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v25
+; CHECK-P8-NEXT:    vmr v3, v25 # Vec Defs: V3(VSR35) Vec Uses: V25(VSR57)V25(VSR57)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v26
+; CHECK-P8-NEXT:    vmr v3, v26 # Vec Defs: V3(VSR35) Vec Uses: V26(VSR58)V26(VSR58)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v27
+; CHECK-P8-NEXT:    vmr v3, v27 # Vec Defs: V3(VSR35) Vec Uses: V27(VSR59)V27(VSR59)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v28
+; CHECK-P8-NEXT:    vmr v3, v28 # Vec Defs: V3(VSR35) Vec Uses: V28(VSR60)V28(VSR60)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v30
+; CHECK-P8-NEXT:    vmr v3, v30 # Vec Defs: V3(VSR35) Vec Uses: V30(VSR62)V30(VSR62)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v31
+; CHECK-P8-NEXT:    vmr v3, v31 # Vec Defs: V3(VSR35) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v29
+; CHECK-P8-NEXT:    vmr v3, v29 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)V29(VSR61)
 ; CHECK-P8-NEXT:    bl __subkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r3, 208
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    li r3, 192
 ; CHECK-P8-NEXT:    lvx v30, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V30(VSR62)
 ; CHECK-P8-NEXT:    li r3, 176
 ; CHECK-P8-NEXT:    lvx v29, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V29(VSR61)
 ; CHECK-P8-NEXT:    li r3, 160
 ; CHECK-P8-NEXT:    lvx v28, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V28(VSR60)
 ; CHECK-P8-NEXT:    li r3, 144
 ; CHECK-P8-NEXT:    lvx v27, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V27(VSR59)
 ; CHECK-P8-NEXT:    li r3, 128
 ; CHECK-P8-NEXT:    lvx v26, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V26(VSR58)
 ; CHECK-P8-NEXT:    li r3, 112
 ; CHECK-P8-NEXT:    lvx v25, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V25(VSR57)
 ; CHECK-P8-NEXT:    li r3, 96
 ; CHECK-P8-NEXT:    lvx v24, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V24(VSR56)
 ; CHECK-P8-NEXT:    li r3, 80
 ; CHECK-P8-NEXT:    lvx v23, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V23(VSR55)
 ; CHECK-P8-NEXT:    li r3, 64
 ; CHECK-P8-NEXT:    lvx v22, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V22(VSR54)
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    lvx v21, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V21(VSR53)
 ; CHECK-P8-NEXT:    addi r1, r1, 224
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                           fp128 %p6, fp128 %p7, fp128 %p8, fp128 %p9, fp128 %p10,
                           fp128 %p11, fp128 %p12, fp128 %p13) {
 entry:
   %add = fadd fp128 %p1, %p2
entry:
   ret fp128 %sub
 }
 
 ; Passing a mix of float128 and other type parameters.
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @mixParam_01(fp128 %a, i32 signext %i, fp128 %b) {
 ; CHECK-LABEL: mixParam_01:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xsaddqp v2, v2, v3
-; CHECK-NEXT:    mtvsrwa v3, r5
-; CHECK-NEXT:    xscvsdqp v3, v3
-; CHECK-NEXT:    xsaddqp v2, v2, v3
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-NEXT:    mtvsrwa v3, r5 # Vec Defs: VF3(VSR3)
+; CHECK-NEXT:    xscvsdqp v3, v3 # Vec Defs: V3(VSR35) Vec Uses: VF3(VSR3)
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: mixParam_01:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -80(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    .cfi_offset v31, -32
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    mr r30, r5
 ; CHECK-P8-NEXT:    stvx v31, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    mr r3, r30
-; CHECK-P8-NEXT:    vmr v31, v2
+; CHECK-P8-NEXT:    vmr v31, v2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-P8-NEXT:    bl __floatsikf
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v2
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    ld r30, 64(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %add = fadd fp128 %a, %b
   %conv = sitofp i32 %i to fp128
   %add1 = fadd fp128 %add, %conv
   ret fp128 %add1
 }
 ; Function Attrs: norecurse nounwind readnone
 define fastcc fp128 @mixParam_01f(fp128 %a, i32 signext %i, fp128 %b) {
 ; CHECK-LABEL: mixParam_01f:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xsaddqp v2, v2, v3
-; CHECK-NEXT:    mtvsrwa v3, r3
-; CHECK-NEXT:    xscvsdqp v3, v3
-; CHECK-NEXT:    xsaddqp v2, v2, v3
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-NEXT:    mtvsrwa v3, r3 # Vec Defs: VF3(VSR3)
+; CHECK-NEXT:    xscvsdqp v3, v3 # Vec Defs: V3(VSR35) Vec Uses: VF3(VSR3)
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: mixParam_01f:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -80(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    .cfi_offset v31, -32
 ; CHECK-P8-NEXT:    li r4, 48
 ; CHECK-P8-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    mr r30, r3
 ; CHECK-P8-NEXT:    stvx v31, r1, r4 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    mr r3, r30
-; CHECK-P8-NEXT:    vmr v31, v2
+; CHECK-P8-NEXT:    vmr v31, v2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-P8-NEXT:    bl __floatsikf
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v2
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    ld r30, 64(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %add = fadd fp128 %a, %b
   %conv = sitofp i32 %i to fp128
   %add1 = fadd fp128 %add, %conv
   ret fp128 %add1
 }
 
 ; Function Attrs: norecurse nounwind
 define fp128 @mixParam_02(fp128 %p1, double %p2, i64* nocapture %p3,
 ; CHECK-LABEL: mixParam_02:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 96(r1)
 ; CHECK-NEXT:    add r4, r7, r9
-; CHECK-NEXT:    xscpsgndp v3, f1, f1
+; CHECK-NEXT:    xscpsgndp v3, f1, f1 # Vec Defs: VF3(VSR3) Vec Uses: F1(VSR1)F1(VSR1)
 ; CHECK-NEXT:    add r4, r4, r10
-; CHECK-NEXT:    xscvdpqp v3, v3
+; CHECK-NEXT:    xscvdpqp v3, v3 # Vec Defs: V3(VSR35) Vec Uses: VF3(VSR3)
 ; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    std r3, 0(r6)
-; CHECK-NEXT:    lxv v4, 0(r8)
-; CHECK-NEXT:    xsaddqp v2, v4, v2
-; CHECK-NEXT:    xsaddqp v2, v2, v3
+; CHECK-NEXT:    lxv v4, 0(r8) # Vec Defs: V4(VSR36)
+; CHECK-NEXT:    xsaddqp v2, v4, v2 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: mixParam_02:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -80(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset f31, -8
 ; CHECK-P8-NEXT:    .cfi_offset v31, -32
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    add r4, r7, r9
-; CHECK-P8-NEXT:    vmr v4, v2
+; CHECK-P8-NEXT:    vmr v4, v2 # Vec Defs: V4(VSR36) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-P8-NEXT:    stfd f31, 72(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: F31(VSR31)
 ; CHECK-P8-NEXT:    stvx v31, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
 ; CHECK-P8-NEXT:    lwz r3, 176(r1)
 ; CHECK-P8-NEXT:    add r4, r4, r10
-; CHECK-P8-NEXT:    fmr f31, f1
+; CHECK-P8-NEXT:    fmr f31, f1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
 ; CHECK-P8-NEXT:    add r3, r4, r3
 ; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    std r3, 0(r6)
-; CHECK-P8-NEXT:    lvx v3, 0, r8
-; CHECK-P8-NEXT:    vmr v2, v3
-; CHECK-P8-NEXT:    vmr v3, v4
+; CHECK-P8-NEXT:    lvx v3, 0, r8 # Vec Defs: V3(VSR35)
+; CHECK-P8-NEXT:    vmr v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-P8-NEXT:    vmr v3, v4 # Vec Defs: V3(VSR35) Vec Uses: V4(VSR36)V4(VSR36)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    fmr f1, f31
-; CHECK-P8-NEXT:    vmr v31, v2
+; CHECK-P8-NEXT:    fmr f1, f31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
+; CHECK-P8-NEXT:    vmr v31, v2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-P8-NEXT:    bl __extenddfkf2
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v2
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    lfd f31, 72(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: F31(VSR31)
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                           i16 signext %p4, fp128* nocapture readonly %p5,
                           i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) {
 entry:
   %conv = sext i16 %p4 to i32
entry:
   ret fp128 %add7
 }
 
 ; Function Attrs: norecurse nounwind
 define fastcc fp128 @mixParam_02f(fp128 %p1, double %p2, i64* nocapture %p3,
 ; CHECK-LABEL: mixParam_02f:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    add r4, r4, r6
-; CHECK-NEXT:    xscpsgndp v3, f1, f1
+; CHECK-NEXT:    xscpsgndp v3, f1, f1 # Vec Defs: VF3(VSR3) Vec Uses: F1(VSR1)F1(VSR1)
 ; CHECK-NEXT:    add r4, r4, r7
-; CHECK-NEXT:    xscvdpqp v3, v3
+; CHECK-NEXT:    xscvdpqp v3, v3 # Vec Defs: V3(VSR35) Vec Uses: VF3(VSR3)
 ; CHECK-NEXT:    add r4, r4, r8
 ; CHECK-NEXT:    clrldi r4, r4, 32
 ; CHECK-NEXT:    std r4, 0(r3)
-; CHECK-NEXT:    lxv v4, 0(r5)
-; CHECK-NEXT:    xsaddqp v2, v4, v2
-; CHECK-NEXT:    xsaddqp v2, v2, v3
+; CHECK-NEXT:    lxv v4, 0(r5) # Vec Defs: V4(VSR36)
+; CHECK-NEXT:    xsaddqp v2, v4, v2 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: mixParam_02f:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -80(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset f31, -8
 ; CHECK-P8-NEXT:    .cfi_offset v31, -32
 ; CHECK-P8-NEXT:    add r4, r4, r6
-; CHECK-P8-NEXT:    vmr v4, v2
+; CHECK-P8-NEXT:    vmr v4, v2 # Vec Defs: V4(VSR36) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-P8-NEXT:    li r9, 48
 ; CHECK-P8-NEXT:    stfd f31, 72(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: F31(VSR31)
 ; CHECK-P8-NEXT:    add r4, r4, r7
 ; CHECK-P8-NEXT:    stvx v31, r1, r9 # 16-byte Folded Spill
-; CHECK-P8-NEXT:    fmr f31, f1
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
+; CHECK-P8-NEXT:    fmr f31, f1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
 ; CHECK-P8-NEXT:    add r4, r4, r8
 ; CHECK-P8-NEXT:    clrldi r4, r4, 32
 ; CHECK-P8-NEXT:    std r4, 0(r3)
-; CHECK-P8-NEXT:    lvx v3, 0, r5
-; CHECK-P8-NEXT:    vmr v2, v3
-; CHECK-P8-NEXT:    vmr v3, v4
+; CHECK-P8-NEXT:    lvx v3, 0, r5 # Vec Defs: V3(VSR35)
+; CHECK-P8-NEXT:    vmr v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-P8-NEXT:    vmr v3, v4 # Vec Defs: V3(VSR35) Vec Uses: V4(VSR36)V4(VSR36)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    fmr f1, f31
-; CHECK-P8-NEXT:    vmr v31, v2
+; CHECK-P8-NEXT:    fmr f1, f31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
+; CHECK-P8-NEXT:    vmr v31, v2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-P8-NEXT:    bl __extenddfkf2
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v2
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r3, 48
 ; CHECK-P8-NEXT:    lfd f31, 72(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: F31(VSR31)
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                                   i16 signext %p4, fp128* nocapture readonly %p5,
                                   i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) {
 entry:
   %conv = sext i16 %p4 to i32

 }
 
 ; Passing a mix of float128 and vector parameters.
 ; Function Attrs: norecurse nounwind
 define void @mixParam_03(fp128 %f1, double* nocapture %d1, <4 x i32> %vec1,
 ; CHECK-LABEL: mixParam_03:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ld r3, 104(r1)
-; CHECK-NEXT:    stxv v2, 0(r9)
-; CHECK-NEXT:    stxv v3, 0(r3)
-; CHECK-NEXT:    mtvsrwa v3, r10
-; CHECK-NEXT:    lxv v2, 0(r9)
-; CHECK-NEXT:    xscvsdqp v3, v3
-; CHECK-NEXT:    xsaddqp v2, v2, v3
-; CHECK-NEXT:    xscvqpdp v2, v2
-; CHECK-NEXT:    stxsd v2, 0(r5)
+; CHECK-NEXT:    stxv v2, 0(r9) # Vec Uses: V2(VSR34)
+; CHECK-NEXT:    stxv v3, 0(r3) # Vec Uses: V3(VSR35)
+; CHECK-NEXT:    mtvsrwa v3, r10 # Vec Defs: VF3(VSR3)
+; CHECK-NEXT:    lxv v2, 0(r9) # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    xscvsdqp v3, v3 # Vec Defs: V3(VSR35) Vec Uses: VF3(VSR3)
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-NEXT:    xscvqpdp v2, v2 # Vec Defs: VF2(VSR2) Vec Uses: V2(VSR34)
+; CHECK-NEXT:    stxsd v2, 0(r5) # Vec Uses: VF2(VSR2)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: mixParam_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -80(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    .cfi_offset v31, -32
 ; CHECK-P8-NEXT:    ld r4, 184(r1)
 ; CHECK-P8-NEXT:    li r3, 48
-; CHECK-P8-NEXT:    stvx v2, 0, r9
+; CHECK-P8-NEXT:    stvx v2, 0, r9 # Vec Uses: V2(VSR34)
 ; CHECK-P8-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    mr r30, r5
 ; CHECK-P8-NEXT:    stvx v31, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
 ; CHECK-P8-NEXT:    mr r3, r10
-; CHECK-P8-NEXT:    stvx v3, 0, r4
-; CHECK-P8-NEXT:    lvx v31, 0, r9
+; CHECK-P8-NEXT:    stvx v3, 0, r4 # Vec Uses: V3(VSR35)
+; CHECK-P8-NEXT:    lvx v31, 0, r9 # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    bl __floatsikf
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v2
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __trunckfdf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r3, 48
-; CHECK-P8-NEXT:    stfd f1, 0(r30)
+; CHECK-P8-NEXT:    stfd f1, 0(r30) # Vec Uses: F1(VSR1)
 ; CHECK-P8-NEXT:    ld r30, 64(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                          fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1,
                          <4 x i32>* nocapture %vec2) {
 entry:
   store fp128 %f1, fp128* %f2, align 16
   store <4 x i32> %vec1, <4 x i32>* %vec2, align 16
   %0 = load fp128, fp128* %f2, align 16
   %conv = sitofp i32 %i1 to fp128
   %add = fadd fp128 %0, %conv
   %conv1 = fptrunc fp128 %add to double
   store double %conv1, double* %d1, align 8
   ret void
 }
 
 ; Function Attrs: norecurse nounwind
 define fastcc void @mixParam_03f(fp128 %f1, double* nocapture %d1, <4 x i32> %vec1,
 ; CHECK-LABEL: mixParam_03f:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    stxv v2, 0(r4)
-; CHECK-NEXT:    stxv v3, 0(r7)
-; CHECK-NEXT:    lxv v2, 0(r4)
-; CHECK-NEXT:    mtvsrwa v3, r5
-; CHECK-NEXT:    xscvsdqp v3, v3
-; CHECK-NEXT:    xsaddqp v2, v2, v3
-; CHECK-NEXT:    xscvqpdp v2, v2
-; CHECK-NEXT:    stxsd v2, 0(r3)
+; CHECK-NEXT:    stxv v2, 0(r4) # Vec Uses: V2(VSR34)
+; CHECK-NEXT:    stxv v3, 0(r7) # Vec Uses: V3(VSR35)
+; CHECK-NEXT:    lxv v2, 0(r4) # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    mtvsrwa v3, r5 # Vec Defs: VF3(VSR3)
+; CHECK-NEXT:    xscvsdqp v3, v3 # Vec Defs: V3(VSR35) Vec Uses: VF3(VSR3)
+; CHECK-NEXT:    xsaddqp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-NEXT:    xscvqpdp v2, v2 # Vec Defs: VF2(VSR2) Vec Uses: V2(VSR34)
+; CHECK-NEXT:    stxsd v2, 0(r3) # Vec Uses: VF2(VSR2)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: mixParam_03f:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -80(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    .cfi_offset v31, -32
 ; CHECK-P8-NEXT:    li r6, 48
-; CHECK-P8-NEXT:    stvx v2, 0, r4
-; CHECK-P8-NEXT:    stvx v3, 0, r7
+; CHECK-P8-NEXT:    stvx v2, 0, r4 # Vec Uses: V2(VSR34)
+; CHECK-P8-NEXT:    stvx v3, 0, r7 # Vec Uses: V3(VSR35)
 ; CHECK-P8-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    mr r30, r3
 ; CHECK-P8-NEXT:    mr r3, r5
 ; CHECK-P8-NEXT:    stvx v31, r1, r6 # 16-byte Folded Spill
-; CHECK-P8-NEXT:    lvx v31, 0, r4
+; CHECK-P8-NEXT:    # Vec Uses: V31(VSR63)
+; CHECK-P8-NEXT:    lvx v31, 0, r4 # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    bl __floatsikf
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    vmr v3, v2
-; CHECK-P8-NEXT:    vmr v2, v31
+; CHECK-P8-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-P8-NEXT:    vmr v2, v31 # Vec Defs: V2(VSR34) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __trunckfdf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r3, 48
-; CHECK-P8-NEXT:    stfd f1, 0(r30)
+; CHECK-P8-NEXT:    stfd f1, 0(r30) # Vec Uses: F1(VSR1)
 ; CHECK-P8-NEXT:    ld r30, 64(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                                  fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1,
                                  <4 x i32>* nocapture %vec2) {
 entry:
   store fp128 %f1, fp128* %f2, align 16

llvm/test/CodeGen/PowerPC/fminnum.ll

 define ppc_fp128 @test_fminl(ppc_fp128 %x, ppc_fp128 %y) {
 ; CHECK-LABEL: test_fminl:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stw 0, 4(1)
 ; CHECK-NEXT:    stwu 1, -112(1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 112
 ; CHECK-NEXT:    .cfi_offset lr, 4
-; CHECK-NEXT:    stfd 1, 40(1)
+; CHECK-NEXT:    stfd 1, 40(1) # Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    lwz 3, 44(1)
-; CHECK-NEXT:    stfd 2, 32(1)
+; CHECK-NEXT:    stfd 2, 32(1) # Vec Uses: F2(VSR2)
 ; CHECK-NEXT:    stw 3, 60(1)
 ; CHECK-NEXT:    lwz 3, 40(1)
-; CHECK-NEXT:    stfd 3, 72(1)
+; CHECK-NEXT:    stfd 3, 72(1) # Vec Uses: F3(VSR3)
 ; CHECK-NEXT:    stw 3, 56(1)
 ; CHECK-NEXT:    lwz 3, 36(1)
-; CHECK-NEXT:    stfd 4, 64(1)
+; CHECK-NEXT:    stfd 4, 64(1) # Vec Uses: F4(VSR4)
 ; CHECK-NEXT:    stw 3, 52(1)
 ; CHECK-NEXT:    lwz 3, 32(1)
-; CHECK-NEXT:    lfd 1, 56(1)
+; CHECK-NEXT:    lfd 1, 56(1) # Vec Defs: F1(VSR1)
 ; CHECK-NEXT:    stw 3, 48(1)
 ; CHECK-NEXT:    lwz 3, 76(1)
-; CHECK-NEXT:    lfd 2, 48(1)
+; CHECK-NEXT:    lfd 2, 48(1) # Vec Defs: F2(VSR2)
 ; CHECK-NEXT:    stw 3, 92(1)
 ; CHECK-NEXT:    lwz 3, 72(1)
 ; CHECK-NEXT:    stw 3, 88(1)
 ; CHECK-NEXT:    lwz 3, 68(1)
-; CHECK-NEXT:    lfd 3, 88(1)
+; CHECK-NEXT:    lfd 3, 88(1) # Vec Defs: F3(VSR3)
 ; CHECK-NEXT:    stw 3, 84(1)
 ; CHECK-NEXT:    lwz 3, 64(1)
 ; CHECK-NEXT:    stw 3, 80(1)
-; CHECK-NEXT:    lfd 4, 80(1)
+; CHECK-NEXT:    lfd 4, 80(1) # Vec Defs: F4(VSR4)
 ; CHECK-NEXT:    bl fminl
-; CHECK-NEXT:    stfd 1, 16(1)
+; CHECK-NEXT:    stfd 1, 16(1) # Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    lwz 3, 20(1)
-; CHECK-NEXT:    stfd 2, 24(1)
+; CHECK-NEXT:    stfd 2, 24(1) # Vec Uses: F2(VSR2)
 ; CHECK-NEXT:    stw 3, 108(1)
 ; CHECK-NEXT:    lwz 3, 16(1)
 ; CHECK-NEXT:    stw 3, 104(1)
 ; CHECK-NEXT:    lwz 3, 28(1)
-; CHECK-NEXT:    lfd 1, 104(1)
+; CHECK-NEXT:    lfd 1, 104(1) # Vec Defs: F1(VSR1)
 ; CHECK-NEXT:    stw 3, 100(1)
 ; CHECK-NEXT:    lwz 3, 24(1)
 ; CHECK-NEXT:    stw 3, 96(1)
-; CHECK-NEXT:    lfd 2, 96(1)
+; CHECK-NEXT:    lfd 2, 96(1) # Vec Defs: F2(VSR2)
 ; CHECK-NEXT:    lwz 0, 116(1)
 ; CHECK-NEXT:    addi 1, 1, 112
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
   %z = call ppc_fp128 @fminl(ppc_fp128 %x, ppc_fp128 %y) readnone
   ret ppc_fp128 %z
 }
 

 define ppc_fp128 @test_intrinsic_fmin_f128(ppc_fp128 %x, ppc_fp128 %y) {
 ; CHECK-LABEL: test_intrinsic_fmin_f128:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stw 0, 4(1)
 ; CHECK-NEXT:    stwu 1, -112(1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 112
 ; CHECK-NEXT:    .cfi_offset lr, 4
-; CHECK-NEXT:    stfd 1, 40(1)
+; CHECK-NEXT:    stfd 1, 40(1) # Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    lwz 3, 44(1)
-; CHECK-NEXT:    stfd 2, 32(1)
+; CHECK-NEXT:    stfd 2, 32(1) # Vec Uses: F2(VSR2)
 ; CHECK-NEXT:    stw 3, 60(1)
 ; CHECK-NEXT:    lwz 3, 40(1)
-; CHECK-NEXT:    stfd 3, 72(1)
+; CHECK-NEXT:    stfd 3, 72(1) # Vec Uses: F3(VSR3)
 ; CHECK-NEXT:    stw 3, 56(1)
 ; CHECK-NEXT:    lwz 3, 36(1)
-; CHECK-NEXT:    stfd 4, 64(1)
+; CHECK-NEXT:    stfd 4, 64(1) # Vec Uses: F4(VSR4)
 ; CHECK-NEXT:    stw 3, 52(1)
 ; CHECK-NEXT:    lwz 3, 32(1)
-; CHECK-NEXT:    lfd 1, 56(1)
+; CHECK-NEXT:    lfd 1, 56(1) # Vec Defs: F1(VSR1)
 ; CHECK-NEXT:    stw 3, 48(1)
 ; CHECK-NEXT:    lwz 3, 76(1)
-; CHECK-NEXT:    lfd 2, 48(1)
+; CHECK-NEXT:    lfd 2, 48(1) # Vec Defs: F2(VSR2)
 ; CHECK-NEXT:    stw 3, 92(1)
 ; CHECK-NEXT:    lwz 3, 72(1)
 ; CHECK-NEXT:    stw 3, 88(1)
 ; CHECK-NEXT:    lwz 3, 68(1)
-; CHECK-NEXT:    lfd 3, 88(1)
+; CHECK-NEXT:    lfd 3, 88(1) # Vec Defs: F3(VSR3)
 ; CHECK-NEXT:    stw 3, 84(1)
 ; CHECK-NEXT:    lwz 3, 64(1)
 ; CHECK-NEXT:    stw 3, 80(1)
-; CHECK-NEXT:    lfd 4, 80(1)
+; CHECK-NEXT:    lfd 4, 80(1) # Vec Defs: F4(VSR4)
 ; CHECK-NEXT:    bl fminl
-; CHECK-NEXT:    stfd 1, 16(1)
+; CHECK-NEXT:    stfd 1, 16(1) # Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    lwz 3, 20(1)
-; CHECK-NEXT:    stfd 2, 24(1)
+; CHECK-NEXT:    stfd 2, 24(1) # Vec Uses: F2(VSR2)
 ; CHECK-NEXT:    stw 3, 108(1)
 ; CHECK-NEXT:    lwz 3, 16(1)
 ; CHECK-NEXT:    stw 3, 104(1)
 ; CHECK-NEXT:    lwz 3, 28(1)
-; CHECK-NEXT:    lfd 1, 104(1)
+; CHECK-NEXT:    lfd 1, 104(1) # Vec Defs: F1(VSR1)
 ; CHECK-NEXT:    stw 3, 100(1)
 ; CHECK-NEXT:    lwz 3, 24(1)
 ; CHECK-NEXT:    stw 3, 96(1)
-; CHECK-NEXT:    lfd 2, 96(1)
+; CHECK-NEXT:    lfd 2, 96(1) # Vec Defs: F2(VSR2)
 ; CHECK-NEXT:    lwz 0, 116(1)
 ; CHECK-NEXT:    addi 1, 1, 112
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
   %z = call ppc_fp128 @llvm.minnum.ppcf128(ppc_fp128 %x, ppc_fp128 %y) readnone
   ret ppc_fp128 %z
 }
 
 define <2 x float> @test_intrinsic_fminf_v2f32(<2 x float> %x, <2 x float> %y) {
 ; CHECK-LABEL: test_intrinsic_fminf_v2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stw 0, 4(1)
 ; CHECK-NEXT:    stwu 1, -32(1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    .cfi_offset lr, 4
 ; CHECK-NEXT:    .cfi_offset f29, -24
 ; CHECK-NEXT:    .cfi_offset f30, -16
 ; CHECK-NEXT:    .cfi_offset f31, -8
 ; CHECK-NEXT:    stfd 30, 16(1) # 8-byte Folded Spill
-; CHECK-NEXT:    fmr 30, 2
-; CHECK-NEXT:    fmr 2, 3
+; CHECK-NEXT:    # Vec Uses: F30(VSR30)
+; CHECK-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
+; CHECK-NEXT:    fmr 2, 3 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)
 ; CHECK-NEXT:    stfd 29, 8(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F29(VSR29)
 ; CHECK-NEXT:    stfd 31, 24(1) # 8-byte Folded Spill
-; CHECK-NEXT:    fmr 31, 4
+; CHECK-NEXT:    # Vec Uses: F31(VSR31)
+; CHECK-NEXT:    fmr 31, 4 # Vec Defs: F31(VSR31) Vec Uses: F4(VSR4)
 ; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    fmr 29, 1
-; CHECK-NEXT:    fmr 1, 30
-; CHECK-NEXT:    fmr 2, 31
+; CHECK-NEXT:    fmr 29, 1 # Vec Defs: F29(VSR29) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
+; CHECK-NEXT:    fmr 2, 31 # Vec Defs: F2(VSR2) Vec Uses: F31(VSR31)
 ; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    fmr 2, 1
-; CHECK-NEXT:    fmr 1, 29
+; CHECK-NEXT:    fmr 2, 1 # Vec Defs: F2(VSR2) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 1, 29 # Vec Defs: F1(VSR1) Vec Uses: F29(VSR29)
 ; CHECK-NEXT:    lfd 31, 24(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F31(VSR31)
 ; CHECK-NEXT:    lfd 30, 16(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F30(VSR30)
 ; CHECK-NEXT:    lfd 29, 8(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F29(VSR29)
 ; CHECK-NEXT:    lwz 0, 36(1)
 ; CHECK-NEXT:    addi 1, 1, 32
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
   %z = call <2 x float> @llvm.minnum.v2f32(<2 x float> %x, <2 x float> %y) readnone
   ret <2 x float> %z
 }
 
 define <4 x float> @test_intrinsic_fmin_v4f32(<4 x float> %x, <4 x float> %y) {
 ; CHECK-LABEL: test_intrinsic_fmin_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stw 0, 4(1)
 ; CHECK-NEXT:    stwu 1, -64(1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-NEXT:    .cfi_offset lr, 4
 ; CHECK-NEXT:    .cfi_offset f25, -56
 ; CHECK-NEXT:    .cfi_offset f26, -48
 ; CHECK-NEXT:    .cfi_offset f27, -40
 ; CHECK-NEXT:    .cfi_offset f28, -32
 ; CHECK-NEXT:    .cfi_offset f29, -24
 ; CHECK-NEXT:    .cfi_offset f30, -16
 ; CHECK-NEXT:    .cfi_offset f31, -8
 ; CHECK-NEXT:    stfd 26, 16(1) # 8-byte Folded Spill
-; CHECK-NEXT:    fmr 26, 2
-; CHECK-NEXT:    fmr 2, 5
+; CHECK-NEXT:    # Vec Uses: F26(VSR26)
+; CHECK-NEXT:    fmr 26, 2 # Vec Defs: F26(VSR26) Vec Uses: F2(VSR2)
+; CHECK-NEXT:    fmr 2, 5 # Vec Defs: F2(VSR2) Vec Uses: F5(VSR5)
 ; CHECK-NEXT:    stfd 25, 8(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F25(VSR25)
 ; CHECK-NEXT:    stfd 27, 24(1) # 8-byte Folded Spill
-; CHECK-NEXT:    fmr 27, 3
+; CHECK-NEXT:    # Vec Uses: F27(VSR27)
+; CHECK-NEXT:    fmr 27, 3 # Vec Defs: F27(VSR27) Vec Uses: F3(VSR3)
 ; CHECK-NEXT:    stfd 28, 32(1) # 8-byte Folded Spill
-; CHECK-NEXT:    fmr 28, 4
+; CHECK-NEXT:    # Vec Uses: F28(VSR28)
+; CHECK-NEXT:    fmr 28, 4 # Vec Defs: F28(VSR28) Vec Uses: F4(VSR4)
 ; CHECK-NEXT:    stfd 29, 40(1) # 8-byte Folded Spill
-; CHECK-NEXT:    fmr 29, 6
+; CHECK-NEXT:    # Vec Uses: F29(VSR29)
+; CHECK-NEXT:    fmr 29, 6 # Vec Defs: F29(VSR29) Vec Uses: F6(VSR6)
 ; CHECK-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
-; CHECK-NEXT:    fmr 30, 7
+; CHECK-NEXT:    # Vec Uses: F30(VSR30)
+; CHECK-NEXT:    fmr 30, 7 # Vec Defs: F30(VSR30) Vec Uses: F7(VSR7)
 ; CHECK-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
-; CHECK-NEXT:    fmr 31, 8
+; CHECK-NEXT:    # Vec Uses: F31(VSR31)
+; CHECK-NEXT:    fmr 31, 8 # Vec Defs: F31(VSR31) Vec Uses: F8(VSR8)
 ; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    fmr 25, 1
-; CHECK-NEXT:    fmr 1, 26
-; CHECK-NEXT:    fmr 2, 29
-; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    fmr 29, 1
-; CHECK-NEXT:    fmr 1, 27
-; CHECK-NEXT:    fmr 2, 30
-; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    fmr 30, 1
-; CHECK-NEXT:    fmr 1, 28
-; CHECK-NEXT:    fmr 2, 31
-; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    fmr 4, 1
-; CHECK-NEXT:    fmr 1, 25
-; CHECK-NEXT:    fmr 2, 29
-; CHECK-NEXT:    fmr 3, 30
+; CHECK-NEXT:    fmr 25, 1 # Vec Defs: F25(VSR25) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 1, 26 # Vec Defs: F1(VSR1) Vec Uses: F26(VSR26)
+; CHECK-NEXT:    fmr 2, 29 # Vec Defs: F2(VSR2) Vec Uses: F29(VSR29)
+; CHECK-NEXT:    bl fminf
+; CHECK-NEXT:    fmr 29, 1 # Vec Defs: F29(VSR29) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 1, 27 # Vec Defs: F1(VSR1) Vec Uses: F27(VSR27)
+; CHECK-NEXT:    fmr 2, 30 # Vec Defs: F2(VSR2) Vec Uses: F30(VSR30)
+; CHECK-NEXT:    bl fminf
+; CHECK-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 1, 28 # Vec Defs: F1(VSR1) Vec Uses: F28(VSR28)
+; CHECK-NEXT:    fmr 2, 31 # Vec Defs: F2(VSR2) Vec Uses: F31(VSR31)
+; CHECK-NEXT:    bl fminf
+; CHECK-NEXT:    fmr 4, 1 # Vec Defs: F4(VSR4) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 1, 25 # Vec Defs: F1(VSR1) Vec Uses: F25(VSR25)
+; CHECK-NEXT:    fmr 2, 29 # Vec Defs: F2(VSR2) Vec Uses: F29(VSR29)
+; CHECK-NEXT:    fmr 3, 30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
 ; CHECK-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F31(VSR31)
 ; CHECK-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F30(VSR30)
 ; CHECK-NEXT:    lfd 29, 40(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F29(VSR29)
 ; CHECK-NEXT:    lfd 28, 32(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F28(VSR28)
 ; CHECK-NEXT:    lfd 27, 24(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F27(VSR27)
 ; CHECK-NEXT:    lfd 26, 16(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F26(VSR26)
 ; CHECK-NEXT:    lfd 25, 8(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F25(VSR25)
 ; CHECK-NEXT:    lwz 0, 68(1)
 ; CHECK-NEXT:    addi 1, 1, 64
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
   %z = call <4 x float> @llvm.minnum.v4f32(<4 x float> %x, <4 x float> %y) readnone
   ret <4 x float> %z
 }
 

 ; CHECK-NEXT:    .cfi_offset f25, -56
 ; CHECK-NEXT:    .cfi_offset f26, -48
 ; CHECK-NEXT:    .cfi_offset f27, -40
 ; CHECK-NEXT:    .cfi_offset f28, -32
 ; CHECK-NEXT:    .cfi_offset f29, -24
 ; CHECK-NEXT:    .cfi_offset f30, -16
 ; CHECK-NEXT:    .cfi_offset f31, -8
 ; CHECK-NEXT:    stfd 25, 72(1) # 8-byte Folded Spill
-; CHECK-NEXT:    fmr 25, 2
-; CHECK-NEXT:    lfs 2, 136(1)
+; CHECK-NEXT:    # Vec Uses: F25(VSR25)
+; CHECK-NEXT:    fmr 25, 2 # Vec Defs: F25(VSR25) Vec Uses: F2(VSR2)
+; CHECK-NEXT:    lfs 2, 136(1) # Vec Defs: F2(VSR2)
 ; CHECK-NEXT:    stfd 17, 8(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F17(VSR17)
 ; CHECK-NEXT:    stfd 18, 16(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F18(VSR18)
 ; CHECK-NEXT:    stfd 19, 24(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F19(VSR19)
 ; CHECK-NEXT:    stfd 20, 32(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F20(VSR20)
 ; CHECK-NEXT:    stfd 21, 40(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F21(VSR21)
 ; CHECK-NEXT:    stfd 22, 48(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F22(VSR22)
 ; CHECK-NEXT:    stfd 23, 56(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F23(VSR23)
 ; CHECK-NEXT:    stfd 24, 64(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F24(VSR24)
 ; CHECK-NEXT:    stfd 26, 80(1) # 8-byte Folded Spill
-; CHECK-NEXT:    fmr 26, 3
+; CHECK-NEXT:    # Vec Uses: F26(VSR26)
+; CHECK-NEXT:    fmr 26, 3 # Vec Defs: F26(VSR26) Vec Uses: F3(VSR3)
 ; CHECK-NEXT:    stfd 27, 88(1) # 8-byte Folded Spill
-; CHECK-NEXT:    fmr 27, 4
+; CHECK-NEXT:    # Vec Uses: F27(VSR27)
+; CHECK-NEXT:    fmr 27, 4 # Vec Defs: F27(VSR27) Vec Uses: F4(VSR4)
 ; CHECK-NEXT:    stfd 28, 96(1) # 8-byte Folded Spill
-; CHECK-NEXT:    fmr 28, 5
+; CHECK-NEXT:    # Vec Uses: F28(VSR28)
+; CHECK-NEXT:    fmr 28, 5 # Vec Defs: F28(VSR28) Vec Uses: F5(VSR5)
 ; CHECK-NEXT:    stfd 29, 104(1) # 8-byte Folded Spill
-; CHECK-NEXT:    fmr 29, 6
+; CHECK-NEXT:    # Vec Uses: F29(VSR29)
+; CHECK-NEXT:    fmr 29, 6 # Vec Defs: F29(VSR29) Vec Uses: F6(VSR6)
 ; CHECK-NEXT:    stfd 30, 112(1) # 8-byte Folded Spill
-; CHECK-NEXT:    fmr 30, 7
+; CHECK-NEXT:    # Vec Uses: F30(VSR30)
+; CHECK-NEXT:    fmr 30, 7 # Vec Defs: F30(VSR30) Vec Uses: F7(VSR7)
 ; CHECK-NEXT:    stfd 31, 120(1) # 8-byte Folded Spill
-; CHECK-NEXT:    fmr 31, 8
-; CHECK-NEXT:    lfs 24, 192(1)
-; CHECK-NEXT:    lfs 23, 184(1)
-; CHECK-NEXT:    lfs 22, 176(1)
-; CHECK-NEXT:    lfs 21, 168(1)
-; CHECK-NEXT:    lfs 20, 160(1)
-; CHECK-NEXT:    lfs 19, 152(1)
-; CHECK-NEXT:    lfs 18, 144(1)
-; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    fmr 17, 1
-; CHECK-NEXT:    fmr 1, 25
-; CHECK-NEXT:    fmr 2, 18
-; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    fmr 25, 1
-; CHECK-NEXT:    fmr 1, 26
-; CHECK-NEXT:    fmr 2, 19
-; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    fmr 26, 1
-; CHECK-NEXT:    fmr 1, 27
-; CHECK-NEXT:    fmr 2, 20
-; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    fmr 27, 1
-; CHECK-NEXT:    fmr 1, 28
-; CHECK-NEXT:    fmr 2, 21
-; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    fmr 28, 1
-; CHECK-NEXT:    fmr 1, 29
-; CHECK-NEXT:    fmr 2, 22
-; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    fmr 29, 1
-; CHECK-NEXT:    fmr 1, 30
-; CHECK-NEXT:    fmr 2, 23
-; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    fmr 30, 1
-; CHECK-NEXT:    fmr 1, 31
-; CHECK-NEXT:    fmr 2, 24
-; CHECK-NEXT:    bl fminf
-; CHECK-NEXT:    fmr 8, 1
-; CHECK-NEXT:    fmr 1, 17
-; CHECK-NEXT:    fmr 2, 25
-; CHECK-NEXT:    fmr 3, 26
-; CHECK-NEXT:    fmr 4, 27
-; CHECK-NEXT:    fmr 5, 28
-; CHECK-NEXT:    fmr 6, 29
-; CHECK-NEXT:    fmr 7, 30
+; CHECK-NEXT:    # Vec Uses: F31(VSR31)
+; CHECK-NEXT:    fmr 31, 8 # Vec Defs: F31(VSR31) Vec Uses: F8(VSR8)
+; CHECK-NEXT:    lfs 24, 192(1) # Vec Defs: F24(VSR24)
+; CHECK-NEXT:    lfs 23, 184(1) # Vec Defs: F23(VSR23)
+; CHECK-NEXT:    lfs 22, 176(1) # Vec Defs: F22(VSR22)
+; CHECK-NEXT:    lfs 21, 168(1) # Vec Defs: F21(VSR21)
+; CHECK-NEXT:    lfs 20, 160(1) # Vec Defs: F20(VSR20)
+; CHECK-NEXT:    lfs 19, 152(1) # Vec Defs: F19(VSR19)
+; CHECK-NEXT:    lfs 18, 144(1) # Vec Defs: F18(VSR18)
+; CHECK-NEXT:    bl fminf
+; CHECK-NEXT:    fmr 17, 1 # Vec Defs: F17(VSR17) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 1, 25 # Vec Defs: F1(VSR1) Vec Uses: F25(VSR25)
+; CHECK-NEXT:    fmr 2, 18 # Vec Defs: F2(VSR2) Vec Uses: F18(VSR18)
+; CHECK-NEXT:    bl fminf
+; CHECK-NEXT:    fmr 25, 1 # Vec Defs: F25(VSR25) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 1, 26 # Vec Defs: F1(VSR1) Vec Uses: F26(VSR26)
+; CHECK-NEXT:    fmr 2, 19 # Vec Defs: F2(VSR2) Vec Uses: F19(VSR19)
+; CHECK-NEXT:    bl fminf
+; CHECK-NEXT:    fmr 26, 1 # Vec Defs: F26(VSR26) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 1, 27 # Vec Defs: F1(VSR1) Vec Uses: F27(VSR27)
+; CHECK-NEXT:    fmr 2, 20 # Vec Defs: F2(VSR2) Vec Uses: F20(VSR20)
+; CHECK-NEXT:    bl fminf
+; CHECK-NEXT:    fmr 27, 1 # Vec Defs: F27(VSR27) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 1, 28 # Vec Defs: F1(VSR1) Vec Uses: F28(VSR28)
+; CHECK-NEXT:    fmr 2, 21 # Vec Defs: F2(VSR2) Vec Uses: F21(VSR21)
+; CHECK-NEXT:    bl fminf
+; CHECK-NEXT:    fmr 28, 1 # Vec Defs: F28(VSR28) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 1, 29 # Vec Defs: F1(VSR1) Vec Uses: F29(VSR29)
+; CHECK-NEXT:    fmr 2, 22 # Vec Defs: F2(VSR2) Vec Uses: F22(VSR22)
+; CHECK-NEXT:    bl fminf
+; CHECK-NEXT:    fmr 29, 1 # Vec Defs: F29(VSR29) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
+; CHECK-NEXT:    fmr 2, 23 # Vec Defs: F2(VSR2) Vec Uses: F23(VSR23)
+; CHECK-NEXT:    bl fminf
+; CHECK-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
+; CHECK-NEXT:    fmr 2, 24 # Vec Defs: F2(VSR2) Vec Uses: F24(VSR24)
+; CHECK-NEXT:    bl fminf
+; CHECK-NEXT:    fmr 8, 1 # Vec Defs: F8(VSR8) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    fmr 1, 17 # Vec Defs: F1(VSR1) Vec Uses: F17(VSR17)
+; CHECK-NEXT:    fmr 2, 25 # Vec Defs: F2(VSR2) Vec Uses: F25(VSR25)
+; CHECK-NEXT:    fmr 3, 26 # Vec Defs: F3(VSR3) Vec Uses: F26(VSR26)
+; CHECK-NEXT:    fmr 4, 27 # Vec Defs: F4(VSR4) Vec Uses: F27(VSR27)
+; CHECK-NEXT:    fmr 5, 28 # Vec Defs: F5(VSR5) Vec Uses: F28(VSR28)
+; CHECK-NEXT:    fmr 6, 29 # Vec Defs: F6(VSR6) Vec Uses: F29(VSR29)
+; CHECK-NEXT:    fmr 7, 30 # Vec Defs: F7(VSR7) Vec Uses: F30(VSR30)
 ; CHECK-NEXT:    lfd 31, 120(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F31(VSR31)
 ; CHECK-NEXT:    lfd 30, 112(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F30(VSR30)
 ; CHECK-NEXT:    lfd 29, 104(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F29(VSR29)
 ; CHECK-NEXT:    lfd 28, 96(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F28(VSR28)
 ; CHECK-NEXT:    lfd 27, 88(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F27(VSR27)
 ; CHECK-NEXT:    lfd 26, 80(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F26(VSR26)
 ; CHECK-NEXT:    lfd 25, 72(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F25(VSR25)
 ; CHECK-NEXT:    lfd 24, 64(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F24(VSR24)
 ; CHECK-NEXT:    lfd 23, 56(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F23(VSR23)
 ; CHECK-NEXT:    lfd 22, 48(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F22(VSR22)
 ; CHECK-NEXT:    lfd 21, 40(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F21(VSR21)
 ; CHECK-NEXT:    lfd 20, 32(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F20(VSR20)
 ; CHECK-NEXT:    lfd 19, 24(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F19(VSR19)
 ; CHECK-NEXT:    lfd 18, 16(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F18(VSR18)
 ; CHECK-NEXT:    lfd 17, 8(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F17(VSR17)
 ; CHECK-NEXT:    lwz 0, 132(1)
 ; CHECK-NEXT:    addi 1, 1, 128
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
   %z = call <8 x float> @llvm.minnum.v8f32(<8 x float> %x, <8 x float> %y) readnone
   ret <8 x float> %z
 }
 
 define ppc_fp128 @fminnum_const(ppc_fp128 %0) {
 ; CHECK-LABEL: fminnum_const:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stw 0, 4(1)
 ; CHECK-NEXT:    stwu 1, -96(1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 96
 ; CHECK-NEXT:    .cfi_offset lr, 4
-; CHECK-NEXT:    stfd 1, 40(1)
+; CHECK-NEXT:    stfd 1, 40(1) # Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    stw 3, 76(1)
 ; CHECK-NEXT:    lis 4, 16368
 ; CHECK-NEXT:    stw 3, 68(1)
 ; CHECK-NEXT:    stw 3, 64(1)
 ; CHECK-NEXT:    lwz 3, 44(1)
-; CHECK-NEXT:    stfd 2, 32(1)
+; CHECK-NEXT:    stfd 2, 32(1) # Vec Uses: F2(VSR2)
 ; CHECK-NEXT:    stw 3, 60(1)
 ; CHECK-NEXT:    lwz 3, 40(1)
 ; CHECK-NEXT:    stw 4, 72(1)
 ; CHECK-NEXT:    stw 3, 56(1)
 ; CHECK-NEXT:    lwz 3, 36(1)
-; CHECK-NEXT:    lfd 3, 72(1)
+; CHECK-NEXT:    lfd 3, 72(1) # Vec Defs: F3(VSR3)
 ; CHECK-NEXT:    stw 3, 52(1)
 ; CHECK-NEXT:    lwz 3, 32(1)
-; CHECK-NEXT:    lfd 4, 64(1)
+; CHECK-NEXT:    lfd 4, 64(1) # Vec Defs: F4(VSR4)
 ; CHECK-NEXT:    stw 3, 48(1)
-; CHECK-NEXT:    lfd 1, 56(1)
-; CHECK-NEXT:    lfd 2, 48(1)
+; CHECK-NEXT:    lfd 1, 56(1) # Vec Defs: F1(VSR1)
+; CHECK-NEXT:    lfd 2, 48(1) # Vec Defs: F2(VSR2)
 ; CHECK-NEXT:    bl fminl
-; CHECK-NEXT:    stfd 1, 16(1)
+; CHECK-NEXT:    stfd 1, 16(1) # Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    lwz 3, 20(1)
-; CHECK-NEXT:    stfd 2, 24(1)
+; CHECK-NEXT:    stfd 2, 24(1) # Vec Uses: F2(VSR2)
 ; CHECK-NEXT:    stw 3, 92(1)
 ; CHECK-NEXT:    lwz 3, 16(1)
 ; CHECK-NEXT:    stw 3, 88(1)
 ; CHECK-NEXT:    lwz 3, 28(1)
-; CHECK-NEXT:    lfd 1, 88(1)
+; CHECK-NEXT:    lfd 1, 88(1) # Vec Defs: F1(VSR1)
 ; CHECK-NEXT:    stw 3, 84(1)
 ; CHECK-NEXT:    lwz 3, 24(1)
 ; CHECK-NEXT:    stw 3, 80(1)
-; CHECK-NEXT:    lfd 2, 80(1)
+; CHECK-NEXT:    lfd 2, 80(1) # Vec Defs: F2(VSR2)
 ; CHECK-NEXT:    lwz 0, 100(1)
 ; CHECK-NEXT:    addi 1, 1, 96
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
   %2 = tail call fast ppc_fp128 @llvm.minnum.ppcf128(ppc_fp128 %0, ppc_fp128 0xM3FF00000000000000000000000000000)
   ret ppc_fp128 %2
 }
 

llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s \
 ; RUN:   -check-prefix=P8
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 \
 ; RUN:   | FileCheck %s -check-prefix=P9
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -mattr=-vsx | \
 ; RUN:   FileCheck %s -check-prefix=NOVSX
 
 define i32 @test_f32_oeq_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_oeq_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    iseleq r3, r3, r4
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_oeq_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    iseleq r3, r3, r4
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_oeq_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    iseleq r3, r3, r4
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"oeq",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ogt_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_ogt_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    iselgt r3, r3, r4
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_ogt_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    iselgt r3, r3, r4
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_ogt_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    iselgt r3, r3, r4
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"ogt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_oge_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_oge_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    crnor 4*cr5+lt, un, lt
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_oge_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    crnor 4*cr5+lt, un, lt
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_oge_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, lt
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"oge",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_olt_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_olt_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    isellt r3, r3, r4
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_olt_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    isellt r3, r3, r4
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_olt_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    isellt r3, r3, r4
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"olt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ole_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_ole_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    crnor 4*cr5+lt, un, gt
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_ole_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    crnor 4*cr5+lt, un, gt
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_ole_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, gt
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"ole",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_one_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_one_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    crnor 4*cr5+lt, un, eq
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_one_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    crnor 4*cr5+lt, un, eq
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_one_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, eq
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"one",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ord_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_ord_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    isel r3, r4, r3, un
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_ord_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    isel r3, r4, r3, un
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_ord_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    isel r3, r4, r3, un
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"ord",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ueq_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_ueq_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    cror 4*cr5+lt, eq, un
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_ueq_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    cror 4*cr5+lt, eq, un
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_ueq_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    cror 4*cr5+lt, eq, un
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"ueq",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ugt_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_ugt_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    cror 4*cr5+lt, gt, un
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_ugt_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    cror 4*cr5+lt, gt, un
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_ugt_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    cror 4*cr5+lt, gt, un
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"ugt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_uge_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_uge_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    isellt r3, r4, r3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_uge_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    isellt r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_uge_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    isellt r3, r4, r3
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"uge",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ult_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_ult_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    cror 4*cr5+lt, lt, un
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_ult_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    cror 4*cr5+lt, lt, un
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_ult_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    cror 4*cr5+lt, lt, un
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"ult",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ule_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_ule_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    iselgt r3, r4, r3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_ule_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    iselgt r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_ule_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    iselgt r3, r4, r3
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"ule",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_une_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_une_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    iseleq r3, r4, r3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_une_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    iseleq r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_une_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    iseleq r3, r4, r3
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"une",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_uno_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_uno_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    isel r3, r3, r4, un
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_uno_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    isel r3, r3, r4, un
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_uno_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    isel r3, r3, r4, un
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f32(
                                                float %f1, float %f2, metadata !"uno",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_oeq_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_oeq_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    iseleq r3, r3, r4
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_oeq_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    iseleq r3, r3, r4
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_oeq_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    iseleq r3, r3, r4
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"oeq",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ogt_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_ogt_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    iselgt r3, r3, r4
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_ogt_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    iselgt r3, r3, r4
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_ogt_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    iselgt r3, r3, r4
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"ogt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_oge_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_oge_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    crnor 4*cr5+lt, un, lt
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_oge_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    crnor 4*cr5+lt, un, lt
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_oge_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, lt
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"oge",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_olt_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_olt_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    isellt r3, r3, r4
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_olt_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    isellt r3, r3, r4
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_olt_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    isellt r3, r3, r4
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"olt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ole_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_ole_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    crnor 4*cr5+lt, un, gt
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_ole_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    crnor 4*cr5+lt, un, gt
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_ole_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, gt
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"ole",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_one_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_one_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    crnor 4*cr5+lt, un, eq
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_one_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    crnor 4*cr5+lt, un, eq
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_one_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, eq
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"one",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ord_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_ord_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    isel r3, r4, r3, un
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_ord_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    isel r3, r4, r3, un
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_ord_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    isel r3, r4, r3, un
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"ord",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ueq_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_ueq_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    cror 4*cr5+lt, eq, un
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_ueq_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    cror 4*cr5+lt, eq, un
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_ueq_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    cror 4*cr5+lt, eq, un
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"ueq",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ugt_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_ugt_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    cror 4*cr5+lt, gt, un
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_ugt_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    cror 4*cr5+lt, gt, un
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_ugt_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    cror 4*cr5+lt, gt, un
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"ugt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_uge_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_uge_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    isellt r3, r4, r3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_uge_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    isellt r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_uge_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    isellt r3, r4, r3
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"uge",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ult_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_ult_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    cror 4*cr5+lt, lt, un
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_ult_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    cror 4*cr5+lt, lt, un
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_ult_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    cror 4*cr5+lt, lt, un
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"ult",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ule_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_ule_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    iselgt r3, r4, r3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_ule_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    iselgt r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_ule_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    iselgt r3, r4, r3
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"ule",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_une_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_une_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    iseleq r3, r4, r3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_une_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    iseleq r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_une_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    iseleq r3, r4, r3
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"une",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_uno_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_uno_q:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f2
+; P8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    isel r3, r3, r4, un
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_uno_q:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f2
+; P9-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    isel r3, r3, r4, un
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_uno_q:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f2
+; NOVSX-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    isel r3, r3, r4, un
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
                                                double %f1, double %f2, metadata !"uno",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_oeq_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_oeq_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    iseleq r3, r3, r4
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_oeq_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    iseleq r3, r3, r4
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_oeq_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    iseleq r3, r3, r4
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"oeq",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ogt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_ogt_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    iselgt r3, r3, r4
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_ogt_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    iselgt r3, r3, r4
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_ogt_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    iselgt r3, r3, r4
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"ogt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_oge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_oge_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    crnor 4*cr5+lt, un, lt
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_oge_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    crnor 4*cr5+lt, un, lt
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_oge_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, lt
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"oge",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_olt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_olt_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    isellt r3, r3, r4
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_olt_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    isellt r3, r3, r4
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_olt_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    isellt r3, r3, r4
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"olt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ole_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_ole_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    crnor 4*cr5+lt, un, gt
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_ole_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    crnor 4*cr5+lt, un, gt
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_ole_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, gt
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"ole",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_one_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_one_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    crnor 4*cr5+lt, un, eq
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_one_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    crnor 4*cr5+lt, un, eq
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_one_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, eq
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"one",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ord_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_ord_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    isel r3, r4, r3, un
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_ord_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    isel r3, r4, r3, un
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_ord_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    isel r3, r4, r3, un
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"ord",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ueq_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_ueq_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    cror 4*cr5+lt, eq, un
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_ueq_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    cror 4*cr5+lt, eq, un
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_ueq_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    cror 4*cr5+lt, eq, un
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"ueq",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ugt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_ugt_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    cror 4*cr5+lt, gt, un
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_ugt_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    cror 4*cr5+lt, gt, un
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_ugt_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    cror 4*cr5+lt, gt, un
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"ugt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_uge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_uge_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    isellt r3, r4, r3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_uge_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    isellt r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_uge_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    isellt r3, r4, r3
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"uge",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ult_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_ult_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    cror 4*cr5+lt, lt, un
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_ult_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    cror 4*cr5+lt, lt, un
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_ult_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    cror 4*cr5+lt, lt, un
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"ult",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ule_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_ule_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    iselgt r3, r4, r3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_ule_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    iselgt r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_ule_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    iselgt r3, r4, r3
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"ule",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_une_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_une_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    iseleq r3, r4, r3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_une_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    iseleq r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_une_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    iseleq r3, r4, r3
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"une",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_uno_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; P8-LABEL: test_f32_uno_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    isel r3, r3, r4, un
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f32_uno_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    isel r3, r3, r4, un
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f32_uno_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    isel r3, r3, r4, un
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(
                                                float %f1, float %f2, metadata !"uno",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_oeq_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_oeq_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    iseleq r3, r3, r4
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_oeq_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    iseleq r3, r3, r4
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_oeq_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    iseleq r3, r3, r4
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"oeq",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ogt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_ogt_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    iselgt r3, r3, r4
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_ogt_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    iselgt r3, r3, r4
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_ogt_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    iselgt r3, r3, r4
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"ogt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_oge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_oge_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    crnor 4*cr5+lt, un, lt
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_oge_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    crnor 4*cr5+lt, un, lt
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_oge_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, lt
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"oge",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_olt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_olt_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    isellt r3, r3, r4
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_olt_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    isellt r3, r3, r4
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_olt_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    isellt r3, r3, r4
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"olt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ole_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_ole_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    crnor 4*cr5+lt, un, gt
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_ole_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    crnor 4*cr5+lt, un, gt
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_ole_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, gt
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"ole",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_one_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_one_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    crnor 4*cr5+lt, un, eq
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_one_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    crnor 4*cr5+lt, un, eq
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_one_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, eq
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"one",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ord_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_ord_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    isel r3, r4, r3, un
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_ord_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    isel r3, r4, r3, un
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_ord_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    isel r3, r4, r3, un
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"ord",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ueq_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_ueq_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    cror 4*cr5+lt, eq, un
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_ueq_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    cror 4*cr5+lt, eq, un
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_ueq_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    cror 4*cr5+lt, eq, un
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"ueq",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ugt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_ugt_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    cror 4*cr5+lt, gt, un
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_ugt_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    cror 4*cr5+lt, gt, un
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_ugt_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    cror 4*cr5+lt, gt, un
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"ugt",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_uge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_uge_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    isellt r3, r4, r3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_uge_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    isellt r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_uge_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    isellt r3, r4, r3
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"uge",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ult_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_ult_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    cror 4*cr5+lt, lt, un
 ; P8-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_ult_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    cror 4*cr5+lt, lt, un
 ; P9-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_ult_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    cror 4*cr5+lt, lt, un
 ; NOVSX-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"ult",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ule_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_ule_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    iselgt r3, r4, r3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_ule_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    iselgt r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_ule_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    iselgt r3, r4, r3
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"ule",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_une_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_une_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    iseleq r3, r4, r3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_une_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    iseleq r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_une_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    iseleq r3, r4, r3
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"une",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_uno_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; P8-LABEL: test_f64_uno_s:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f2
+; P8-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P8-NEXT:    isel r3, r3, r4, un
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: test_f64_uno_s:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f2
+; P9-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; P9-NEXT:    isel r3, r3, r4, un
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: test_f64_uno_s:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f2
+; NOVSX-NEXT:    fcmpo cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; NOVSX-NEXT:    isel r3, r3, r4, un
 ; NOVSX-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
                                                double %f1, double %f2, metadata !"uno",
                                                metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }

 ; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_olt_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpuqp cr0, v2, v3
+; P9-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 0
 ; P9-NEXT:    li r4, 1
 ; P9-NEXT:    isellt r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_olt_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0

 ; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_ole_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpuqp cr0, v2, v3
-; P9-NEXT:    xscmpuqp cr1, v2, v3
+; P9-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
+; P9-NEXT:    xscmpuqp cr1, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, un, 4*cr1+un
 ; P9-NEXT:    crnor 4*cr5+gt, gt, 4*cr1+gt
 ; P9-NEXT:    crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_ole_f128:

 ; P8-NEXT:    rldicl r3, r3, 1, 63
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_ogt_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpuqp cr0, v2, v3
+; P9-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 0
 ; P9-NEXT:    li r4, 1
 ; P9-NEXT:    iselgt r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_ogt_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0

 ; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_oge_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpuqp cr0, v2, v3
-; P9-NEXT:    xscmpuqp cr1, v2, v3
+; P9-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
+; P9-NEXT:    xscmpuqp cr1, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, un, 4*cr1+un
 ; P9-NEXT:    crnor 4*cr5+gt, lt, 4*cr1+lt
 ; P9-NEXT:    crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_oge_f128:

 ; P8-NEXT:    srwi r3, r3, 5
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_oeq_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpuqp cr0, v2, v3
+; P9-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 0
 ; P9-NEXT:    li r4, 1
 ; P9-NEXT:    iseleq r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_oeq_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0

 ; P8-LABEL: fcmp_one_f128:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -176(r1)
 ; P8-NEXT:    li r3, 128
 ; P8-NEXT:    std r30, 160(r1) # 8-byte Folded Spill
 ; P8-NEXT:    stxvd2x v30, r1, r3 # 16-byte Folded Spill
+; P8-NEXT:    # Vec Uses: V30(VSR62)
 ; P8-NEXT:    li r3, 144
-; P8-NEXT:    vmr v30, v2
+; P8-NEXT:    vmr v30, v2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; P8-NEXT:    stxvd2x v31, r1, r3 # 16-byte Folded Spill
-; P8-NEXT:    vmr v31, v3
+; P8-NEXT:    # Vec Uses: V31(VSR63)
+; P8-NEXT:    vmr v31, v3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
 ; P8-NEXT:    bl __unordkf2
 ; P8-NEXT:    nop
-; P8-NEXT:    vmr v2, v30
+; P8-NEXT:    vmr v2, v30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; P8-NEXT:    cntlzw r3, r3
-; P8-NEXT:    vmr v3, v31
+; P8-NEXT:    vmr v3, v31 # Vec Defs: V3(VSR35) Vec Uses: V31(VSR63)V31(VSR63)
 ; P8-NEXT:    srwi r30, r3, 5
 ; P8-NEXT:    bl __eqkf2
 ; P8-NEXT:    nop
 ; P8-NEXT:    cntlzw r3, r3
 ; P8-NEXT:    li r4, 144
 ; P8-NEXT:    srwi r3, r3, 5
 ; P8-NEXT:    lxvd2x v31, r1, r4 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V31(VSR63)
 ; P8-NEXT:    li r4, 128
 ; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    lxvd2x v30, r1, r4 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V30(VSR62)
 ; P8-NEXT:    and r3, r30, r3
 ; P8-NEXT:    ld r30, 160(r1) # 8-byte Folded Reload
 ; P8-NEXT:    addi r1, r1, 176
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_one_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpuqp cr0, v2, v3
-; P9-NEXT:    xscmpuqp cr1, v2, v3
+; P9-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
+; P9-NEXT:    xscmpuqp cr1, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, un, 4*cr1+un
 ; P9-NEXT:    crnor 4*cr5+gt, eq, 4*cr1+eq
 ; P9-NEXT:    crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_one_f128:

 ; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_ult_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpuqp cr0, v2, v3
+; P9-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, lt, un
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_ult_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0

 ; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_ule_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpuqp cr0, v2, v3
+; P9-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    iselgt r3, 0, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_ule_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)

 ; P8-NEXT:    rldicl r3, r3, 1, 63
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_ugt_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpuqp cr0, v2, v3
+; P9-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, gt, un
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_ugt_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0

 ; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_uge_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpuqp cr0, v2, v3
+; P9-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    isellt r3, 0, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_uge_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)

 ; P8-LABEL: fcmp_ueq_f128:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -176(r1)
 ; P8-NEXT:    li r3, 128
 ; P8-NEXT:    std r30, 160(r1) # 8-byte Folded Spill
 ; P8-NEXT:    stxvd2x v30, r1, r3 # 16-byte Folded Spill
+; P8-NEXT:    # Vec Uses: V30(VSR62)
 ; P8-NEXT:    li r3, 144
-; P8-NEXT:    vmr v30, v2
+; P8-NEXT:    vmr v30, v2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; P8-NEXT:    stxvd2x v31, r1, r3 # 16-byte Folded Spill
-; P8-NEXT:    vmr v31, v3
+; P8-NEXT:    # Vec Uses: V31(VSR63)
+; P8-NEXT:    vmr v31, v3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
 ; P8-NEXT:    bl __eqkf2
 ; P8-NEXT:    nop
-; P8-NEXT:    vmr v2, v30
+; P8-NEXT:    vmr v2, v30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; P8-NEXT:    cntlzw r3, r3
-; P8-NEXT:    vmr v3, v31
+; P8-NEXT:    vmr v3, v31 # Vec Defs: V3(VSR35) Vec Uses: V31(VSR63)V31(VSR63)
 ; P8-NEXT:    srwi r30, r3, 5
 ; P8-NEXT:    bl __unordkf2
 ; P8-NEXT:    nop
 ; P8-NEXT:    cntlzw r3, r3
 ; P8-NEXT:    li r4, 144
 ; P8-NEXT:    srwi r3, r3, 5
 ; P8-NEXT:    lxvd2x v31, r1, r4 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V31(VSR63)
 ; P8-NEXT:    li r4, 128
 ; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    lxvd2x v30, r1, r4 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V30(VSR62)
 ; P8-NEXT:    or r3, r3, r30
 ; P8-NEXT:    ld r30, 160(r1) # 8-byte Folded Reload
 ; P8-NEXT:    addi r1, r1, 176
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_ueq_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpuqp cr0, v2, v3
+; P9-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, eq, un
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_ueq_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0

 ; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_une_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpuqp cr0, v2, v3
+; P9-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    iseleq r3, 0, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_une_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)

 ; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_olt_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpoqp cr0, v2, v3
+; P9-NEXT:    xscmpoqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 0
 ; P9-NEXT:    li r4, 1
 ; P9-NEXT:    isellt r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_olt_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0

 ; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_ole_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpoqp cr0, v2, v3
-; P9-NEXT:    xscmpoqp cr1, v2, v3
+; P9-NEXT:    xscmpoqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
+; P9-NEXT:    xscmpoqp cr1, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, un, 4*cr1+un
 ; P9-NEXT:    crnor 4*cr5+gt, gt, 4*cr1+gt
 ; P9-NEXT:    crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_ole_f128:

 ; P8-NEXT:    rldicl r3, r3, 1, 63
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_ogt_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpoqp cr0, v2, v3
+; P9-NEXT:    xscmpoqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 0
 ; P9-NEXT:    li r4, 1
 ; P9-NEXT:    iselgt r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_ogt_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0

 ; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_oge_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpoqp cr0, v2, v3
-; P9-NEXT:    xscmpoqp cr1, v2, v3
+; P9-NEXT:    xscmpoqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
+; P9-NEXT:    xscmpoqp cr1, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, un, 4*cr1+un
 ; P9-NEXT:    crnor 4*cr5+gt, lt, 4*cr1+lt
 ; P9-NEXT:    crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_oge_f128:

 ; P8-NEXT:    srwi r3, r3, 5
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_oeq_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpoqp cr0, v2, v3
+; P9-NEXT:    xscmpoqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 0
 ; P9-NEXT:    li r4, 1
 ; P9-NEXT:    iseleq r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_oeq_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0

 ; P8-LABEL: fcmps_one_f128:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -176(r1)
 ; P8-NEXT:    li r3, 128
 ; P8-NEXT:    std r30, 160(r1) # 8-byte Folded Spill
 ; P8-NEXT:    stxvd2x v30, r1, r3 # 16-byte Folded Spill
+; P8-NEXT:    # Vec Uses: V30(VSR62)
 ; P8-NEXT:    li r3, 144
-; P8-NEXT:    vmr v30, v2
+; P8-NEXT:    vmr v30, v2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; P8-NEXT:    stxvd2x v31, r1, r3 # 16-byte Folded Spill
-; P8-NEXT:    vmr v31, v3
+; P8-NEXT:    # Vec Uses: V31(VSR63)
+; P8-NEXT:    vmr v31, v3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
 ; P8-NEXT:    bl __unordkf2
 ; P8-NEXT:    nop
-; P8-NEXT:    vmr v2, v30
+; P8-NEXT:    vmr v2, v30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; P8-NEXT:    cntlzw r3, r3
-; P8-NEXT:    vmr v3, v31
+; P8-NEXT:    vmr v3, v31 # Vec Defs: V3(VSR35) Vec Uses: V31(VSR63)V31(VSR63)
 ; P8-NEXT:    srwi r30, r3, 5
 ; P8-NEXT:    bl __eqkf2
 ; P8-NEXT:    nop
 ; P8-NEXT:    cntlzw r3, r3
 ; P8-NEXT:    li r4, 144
 ; P8-NEXT:    srwi r3, r3, 5
 ; P8-NEXT:    lxvd2x v31, r1, r4 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V31(VSR63)
 ; P8-NEXT:    li r4, 128
 ; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    lxvd2x v30, r1, r4 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V30(VSR62)
 ; P8-NEXT:    and r3, r30, r3
 ; P8-NEXT:    ld r30, 160(r1) # 8-byte Folded Reload
 ; P8-NEXT:    addi r1, r1, 176
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_one_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpoqp cr0, v2, v3
-; P9-NEXT:    xscmpoqp cr1, v2, v3
+; P9-NEXT:    xscmpoqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
+; P9-NEXT:    xscmpoqp cr1, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, un, 4*cr1+un
 ; P9-NEXT:    crnor 4*cr5+gt, eq, 4*cr1+eq
 ; P9-NEXT:    crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_one_f128:

 ; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_ult_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpoqp cr0, v2, v3
+; P9-NEXT:    xscmpoqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, lt, un
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_ult_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0

 ; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_ule_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpoqp cr0, v2, v3
+; P9-NEXT:    xscmpoqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    iselgt r3, 0, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_ule_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)

 ; P8-NEXT:    rldicl r3, r3, 1, 63
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_ugt_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpoqp cr0, v2, v3
+; P9-NEXT:    xscmpoqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, gt, un
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_ugt_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0

 ; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_uge_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpoqp cr0, v2, v3
+; P9-NEXT:    xscmpoqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    isellt r3, 0, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_uge_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)

 ; P8-LABEL: fcmps_ueq_f128:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -176(r1)
 ; P8-NEXT:    li r3, 128
 ; P8-NEXT:    std r30, 160(r1) # 8-byte Folded Spill
 ; P8-NEXT:    stxvd2x v30, r1, r3 # 16-byte Folded Spill
+; P8-NEXT:    # Vec Uses: V30(VSR62)
 ; P8-NEXT:    li r3, 144
-; P8-NEXT:    vmr v30, v2
+; P8-NEXT:    vmr v30, v2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; P8-NEXT:    stxvd2x v31, r1, r3 # 16-byte Folded Spill
-; P8-NEXT:    vmr v31, v3
+; P8-NEXT:    # Vec Uses: V31(VSR63)
+; P8-NEXT:    vmr v31, v3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
 ; P8-NEXT:    bl __eqkf2
 ; P8-NEXT:    nop
-; P8-NEXT:    vmr v2, v30
+; P8-NEXT:    vmr v2, v30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; P8-NEXT:    cntlzw r3, r3
-; P8-NEXT:    vmr v3, v31
+; P8-NEXT:    vmr v3, v31 # Vec Defs: V3(VSR35) Vec Uses: V31(VSR63)V31(VSR63)
 ; P8-NEXT:    srwi r30, r3, 5
 ; P8-NEXT:    bl __unordkf2
 ; P8-NEXT:    nop
 ; P8-NEXT:    cntlzw r3, r3
 ; P8-NEXT:    li r4, 144
 ; P8-NEXT:    srwi r3, r3, 5
 ; P8-NEXT:    lxvd2x v31, r1, r4 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V31(VSR63)
 ; P8-NEXT:    li r4, 128
 ; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    lxvd2x v30, r1, r4 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V30(VSR62)
 ; P8-NEXT:    or r3, r3, r30
 ; P8-NEXT:    ld r30, 160(r1) # 8-byte Folded Reload
 ; P8-NEXT:    addi r1, r1, 176
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_ueq_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpoqp cr0, v2, v3
+; P9-NEXT:    xscmpoqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, eq, un
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_ueq_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0

 ; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_une_f128:
 ; P9:       # %bb.0:
-; P9-NEXT:    xscmpoqp cr0, v2, v3
+; P9-NEXT:    xscmpoqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    iseleq r3, 0, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_une_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmp_olt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmp_olt_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f3
-; P8-NEXT:    fcmpu cr1, f2, f4
+; P8-NEXT:    fcmpu cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P8-NEXT:    fcmpu cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crand 4*cr5+lt, eq, 4*cr1+lt
 ; P8-NEXT:    crandc 4*cr5+gt, lt, eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_olt_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f3
-; P9-NEXT:    fcmpu cr1, f2, f4
+; P9-NEXT:    fcmpu cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P9-NEXT:    fcmpu cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr1+lt
 ; P9-NEXT:    crandc 4*cr5+gt, lt, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_olt_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f3
-; NOVSX-NEXT:    fcmpu cr1, f2, f4
+; NOVSX-NEXT:    fcmpu cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; NOVSX-NEXT:    fcmpu cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crand 4*cr5+lt, eq, 4*cr1+lt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, lt, eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"olt", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmp_ole_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmp_ole_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f2, f4
-; P8-NEXT:    fcmpu cr1, f1, f3
+; P8-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crnor 4*cr5+lt, un, gt
 ; P8-NEXT:    crnor 4*cr5+gt, 4*cr1+un, 4*cr1+gt
 ; P8-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; P8-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_ole_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f2, f4
+; P9-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, un, gt
-; P9-NEXT:    fcmpu cr0, f1, f3
+; P9-NEXT:    fcmpu cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P9-NEXT:    crnor 4*cr5+gt, un, gt
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr5+lt
 ; P9-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_ole_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f2, f4
-; NOVSX-NEXT:    fcmpu cr1, f1, f3
+; NOVSX-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, gt
 ; NOVSX-NEXT:    crnor 4*cr5+gt, 4*cr1+un, 4*cr1+gt
 ; NOVSX-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ole", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmp_ogt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmp_ogt_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f3
-; P8-NEXT:    fcmpu cr1, f2, f4
+; P8-NEXT:    fcmpu cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P8-NEXT:    fcmpu cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crand 4*cr5+lt, eq, 4*cr1+gt
 ; P8-NEXT:    crandc 4*cr5+gt, gt, eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_ogt_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f3
-; P9-NEXT:    fcmpu cr1, f2, f4
+; P9-NEXT:    fcmpu cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P9-NEXT:    fcmpu cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr1+gt
 ; P9-NEXT:    crandc 4*cr5+gt, gt, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_ogt_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f3
-; NOVSX-NEXT:    fcmpu cr1, f2, f4
+; NOVSX-NEXT:    fcmpu cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; NOVSX-NEXT:    fcmpu cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crand 4*cr5+lt, eq, 4*cr1+gt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, gt, eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ogt", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmp_oge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmp_oge_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f2, f4
-; P8-NEXT:    fcmpu cr1, f1, f3
+; P8-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crnor 4*cr5+lt, un, lt
 ; P8-NEXT:    crnor 4*cr5+gt, 4*cr1+un, 4*cr1+lt
 ; P8-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; P8-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_oge_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f2, f4
+; P9-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, un, lt
-; P9-NEXT:    fcmpu cr0, f1, f3
+; P9-NEXT:    fcmpu cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P9-NEXT:    crnor 4*cr5+gt, un, lt
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr5+lt
 ; P9-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_oge_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f2, f4
-; NOVSX-NEXT:    fcmpu cr1, f1, f3
+; NOVSX-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, lt
 ; NOVSX-NEXT:    crnor 4*cr5+gt, 4*cr1+un, 4*cr1+lt
 ; NOVSX-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"oge", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmp_oeq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmp_oeq_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f1, f3
-; P8-NEXT:    fcmpu cr1, f2, f4
+; P8-NEXT:    fcmpu cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P8-NEXT:    fcmpu cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crand 4*cr5+lt, eq, 4*cr1+eq
 ; P8-NEXT:    crandc 4*cr5+gt, eq, eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_oeq_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f3
-; P9-NEXT:    fcmpu cr1, f2, f4
+; P9-NEXT:    fcmpu cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P9-NEXT:    fcmpu cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr1+eq
 ; P9-NEXT:    crandc 4*cr5+gt, eq, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_oeq_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f1, f3
-; NOVSX-NEXT:    fcmpu cr1, f2, f4
+; NOVSX-NEXT:    fcmpu cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; NOVSX-NEXT:    fcmpu cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crand 4*cr5+lt, eq, 4*cr1+eq
 ; NOVSX-NEXT:    crandc 4*cr5+gt, eq, eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"oeq", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmp_one_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmp_one_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f2, f4
-; P8-NEXT:    fcmpu cr1, f1, f3
+; P8-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crnor 4*cr5+lt, un, eq
 ; P8-NEXT:    crnor 4*cr5+gt, 4*cr1+un, 4*cr1+eq
 ; P8-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; P8-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_one_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f2, f4
+; P9-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, un, eq
-; P9-NEXT:    fcmpu cr0, f1, f3
+; P9-NEXT:    fcmpu cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P9-NEXT:    crnor 4*cr5+gt, un, eq
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr5+lt
 ; P9-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_one_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f2, f4
-; NOVSX-NEXT:    fcmpu cr1, f1, f3
+; NOVSX-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, eq
 ; NOVSX-NEXT:    crnor 4*cr5+gt, 4*cr1+un, 4*cr1+eq
 ; NOVSX-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"one", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmp_ult_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmp_ult_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f2, f4
-; P8-NEXT:    fcmpu cr1, f1, f3
+; P8-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    cror 4*cr5+lt, lt, un
 ; P8-NEXT:    cror 4*cr5+gt, 4*cr1+lt, 4*cr1+un
 ; P8-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; P8-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_ult_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f3
-; P9-NEXT:    fcmpu cr1, f2, f4
+; P9-NEXT:    fcmpu cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P9-NEXT:    fcmpu cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    cror 4*cr5+lt, 4*cr1+lt, 4*cr1+un
 ; P9-NEXT:    cror 4*cr5+gt, lt, un
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr5+lt
 ; P9-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_ult_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f2, f4
-; NOVSX-NEXT:    fcmpu cr1, f1, f3
+; NOVSX-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    cror 4*cr5+lt, lt, un
 ; NOVSX-NEXT:    cror 4*cr5+gt, 4*cr1+lt, 4*cr1+un
 ; NOVSX-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ult", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmp_ule_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmp_ule_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f2, f4
-; P8-NEXT:    fcmpu cr1, f1, f3
+; P8-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, gt
 ; P8-NEXT:    crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_ule_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f2, f4
-; P9-NEXT:    fcmpu cr1, f1, f3
+; P9-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P9-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, gt
 ; P9-NEXT:    crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_ule_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f2, f4
-; NOVSX-NEXT:    fcmpu cr1, f1, f3
+; NOVSX-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, gt
 ; NOVSX-NEXT:    crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ule", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmp_ugt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmp_ugt_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f2, f4
-; P8-NEXT:    fcmpu cr1, f1, f3
+; P8-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    cror 4*cr5+lt, gt, un
 ; P8-NEXT:    cror 4*cr5+gt, 4*cr1+gt, 4*cr1+un
 ; P8-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; P8-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_ugt_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f3
-; P9-NEXT:    fcmpu cr1, f2, f4
+; P9-NEXT:    fcmpu cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P9-NEXT:    fcmpu cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    cror 4*cr5+lt, 4*cr1+gt, 4*cr1+un
 ; P9-NEXT:    cror 4*cr5+gt, gt, un
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr5+lt
 ; P9-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_ugt_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f2, f4
-; NOVSX-NEXT:    fcmpu cr1, f1, f3
+; NOVSX-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    cror 4*cr5+lt, gt, un
 ; NOVSX-NEXT:    cror 4*cr5+gt, 4*cr1+gt, 4*cr1+un
 ; NOVSX-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ugt", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmp_uge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmp_uge_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f2, f4
-; P8-NEXT:    fcmpu cr1, f1, f3
+; P8-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, lt
 ; P8-NEXT:    crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_uge_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f2, f4
-; P9-NEXT:    fcmpu cr1, f1, f3
+; P9-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P9-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, lt
 ; P9-NEXT:    crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_uge_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f2, f4
-; NOVSX-NEXT:    fcmpu cr1, f1, f3
+; NOVSX-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, lt
 ; NOVSX-NEXT:    crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"uge", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmp_ueq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmp_ueq_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f2, f4
-; P8-NEXT:    fcmpu cr1, f1, f3
+; P8-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    cror 4*cr5+lt, eq, un
 ; P8-NEXT:    cror 4*cr5+gt, 4*cr1+eq, 4*cr1+un
 ; P8-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; P8-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_ueq_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f1, f3
-; P9-NEXT:    fcmpu cr1, f2, f4
+; P9-NEXT:    fcmpu cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P9-NEXT:    fcmpu cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    cror 4*cr5+lt, 4*cr1+eq, 4*cr1+un
 ; P9-NEXT:    cror 4*cr5+gt, eq, un
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr5+lt
 ; P9-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_ueq_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f2, f4
-; NOVSX-NEXT:    fcmpu cr1, f1, f3
+; NOVSX-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    cror 4*cr5+lt, eq, un
 ; NOVSX-NEXT:    cror 4*cr5+gt, 4*cr1+eq, 4*cr1+un
 ; NOVSX-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ueq", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmp_une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmp_une_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpu cr0, f2, f4
-; P8-NEXT:    fcmpu cr1, f1, f3
+; P8-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, eq
 ; P8-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_une_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpu cr0, f2, f4
-; P9-NEXT:    fcmpu cr1, f1, f3
+; P9-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P9-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, eq
 ; P9-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_une_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpu cr0, f2, f4
-; NOVSX-NEXT:    fcmpu cr1, f1, f3
+; NOVSX-NEXT:    fcmpu cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpu cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, eq
 ; NOVSX-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmps_olt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmps_olt_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f3
-; P8-NEXT:    fcmpo cr1, f2, f4
+; P8-NEXT:    fcmpo cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P8-NEXT:    fcmpo cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crand 4*cr5+lt, eq, 4*cr1+lt
 ; P8-NEXT:    crandc 4*cr5+gt, lt, eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_olt_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f3
-; P9-NEXT:    fcmpo cr1, f2, f4
+; P9-NEXT:    fcmpo cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P9-NEXT:    fcmpo cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr1+lt
 ; P9-NEXT:    crandc 4*cr5+gt, lt, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_olt_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f3
-; NOVSX-NEXT:    fcmpo cr1, f2, f4
+; NOVSX-NEXT:    fcmpo cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; NOVSX-NEXT:    fcmpo cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crand 4*cr5+lt, eq, 4*cr1+lt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, lt, eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"olt", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmps_ole_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmps_ole_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f2, f4
-; P8-NEXT:    fcmpo cr1, f1, f3
+; P8-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crnor 4*cr5+lt, un, gt
 ; P8-NEXT:    crnor 4*cr5+gt, 4*cr1+un, 4*cr1+gt
 ; P8-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; P8-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_ole_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f2, f4
+; P9-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, un, gt
-; P9-NEXT:    fcmpo cr0, f1, f3
+; P9-NEXT:    fcmpo cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P9-NEXT:    crnor 4*cr5+gt, un, gt
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr5+lt
 ; P9-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_ole_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f2, f4
-; NOVSX-NEXT:    fcmpo cr1, f1, f3
+; NOVSX-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, gt
 ; NOVSX-NEXT:    crnor 4*cr5+gt, 4*cr1+un, 4*cr1+gt
 ; NOVSX-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ole", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmps_ogt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmps_ogt_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f3
-; P8-NEXT:    fcmpo cr1, f2, f4
+; P8-NEXT:    fcmpo cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P8-NEXT:    fcmpo cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crand 4*cr5+lt, eq, 4*cr1+gt
 ; P8-NEXT:    crandc 4*cr5+gt, gt, eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_ogt_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f3
-; P9-NEXT:    fcmpo cr1, f2, f4
+; P9-NEXT:    fcmpo cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P9-NEXT:    fcmpo cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr1+gt
 ; P9-NEXT:    crandc 4*cr5+gt, gt, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_ogt_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f3
-; NOVSX-NEXT:    fcmpo cr1, f2, f4
+; NOVSX-NEXT:    fcmpo cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; NOVSX-NEXT:    fcmpo cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crand 4*cr5+lt, eq, 4*cr1+gt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, gt, eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ogt", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmps_oge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmps_oge_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f2, f4
-; P8-NEXT:    fcmpo cr1, f1, f3
+; P8-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crnor 4*cr5+lt, un, lt
 ; P8-NEXT:    crnor 4*cr5+gt, 4*cr1+un, 4*cr1+lt
 ; P8-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; P8-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_oge_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f2, f4
+; P9-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, un, lt
-; P9-NEXT:    fcmpo cr0, f1, f3
+; P9-NEXT:    fcmpo cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P9-NEXT:    crnor 4*cr5+gt, un, lt
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr5+lt
 ; P9-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_oge_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f2, f4
-; NOVSX-NEXT:    fcmpo cr1, f1, f3
+; NOVSX-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, lt
 ; NOVSX-NEXT:    crnor 4*cr5+gt, 4*cr1+un, 4*cr1+lt
 ; NOVSX-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"oge", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmps_oeq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmps_oeq_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f1, f3
-; P8-NEXT:    fcmpo cr1, f2, f4
+; P8-NEXT:    fcmpo cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P8-NEXT:    fcmpo cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crand 4*cr5+lt, eq, 4*cr1+eq
 ; P8-NEXT:    crandc 4*cr5+gt, eq, eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_oeq_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f3
-; P9-NEXT:    fcmpo cr1, f2, f4
+; P9-NEXT:    fcmpo cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P9-NEXT:    fcmpo cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr1+eq
 ; P9-NEXT:    crandc 4*cr5+gt, eq, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_oeq_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f1, f3
-; NOVSX-NEXT:    fcmpo cr1, f2, f4
+; NOVSX-NEXT:    fcmpo cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; NOVSX-NEXT:    fcmpo cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crand 4*cr5+lt, eq, 4*cr1+eq
 ; NOVSX-NEXT:    crandc 4*cr5+gt, eq, eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"oeq", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmps_one_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmps_one_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f2, f4
-; P8-NEXT:    fcmpo cr1, f1, f3
+; P8-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crnor 4*cr5+lt, un, eq
 ; P8-NEXT:    crnor 4*cr5+gt, 4*cr1+un, 4*cr1+eq
 ; P8-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; P8-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_one_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f2, f4
+; P9-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, un, eq
-; P9-NEXT:    fcmpo cr0, f1, f3
+; P9-NEXT:    fcmpo cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P9-NEXT:    crnor 4*cr5+gt, un, eq
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr5+lt
 ; P9-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_one_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f2, f4
-; NOVSX-NEXT:    fcmpo cr1, f1, f3
+; NOVSX-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crnor 4*cr5+lt, un, eq
 ; NOVSX-NEXT:    crnor 4*cr5+gt, 4*cr1+un, 4*cr1+eq
 ; NOVSX-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"one", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmps_ult_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmps_ult_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f2, f4
-; P8-NEXT:    fcmpo cr1, f1, f3
+; P8-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    cror 4*cr5+lt, lt, un
 ; P8-NEXT:    cror 4*cr5+gt, 4*cr1+lt, 4*cr1+un
 ; P8-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; P8-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_ult_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f3
-; P9-NEXT:    fcmpo cr1, f2, f4
+; P9-NEXT:    fcmpo cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P9-NEXT:    fcmpo cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    cror 4*cr5+lt, 4*cr1+lt, 4*cr1+un
 ; P9-NEXT:    cror 4*cr5+gt, lt, un
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr5+lt
 ; P9-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_ult_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f2, f4
-; NOVSX-NEXT:    fcmpo cr1, f1, f3
+; NOVSX-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    cror 4*cr5+lt, lt, un
 ; NOVSX-NEXT:    cror 4*cr5+gt, 4*cr1+lt, 4*cr1+un
 ; NOVSX-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ult", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmps_ule_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmps_ule_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f2, f4
-; P8-NEXT:    fcmpo cr1, f1, f3
+; P8-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, gt
 ; P8-NEXT:    crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_ule_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f2, f4
-; P9-NEXT:    fcmpo cr1, f1, f3
+; P9-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P9-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, gt
 ; P9-NEXT:    crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_ule_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f2, f4
-; NOVSX-NEXT:    fcmpo cr1, f1, f3
+; NOVSX-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, gt
 ; NOVSX-NEXT:    crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ule", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmps_ugt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmps_ugt_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f2, f4
-; P8-NEXT:    fcmpo cr1, f1, f3
+; P8-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    cror 4*cr5+lt, gt, un
 ; P8-NEXT:    cror 4*cr5+gt, 4*cr1+gt, 4*cr1+un
 ; P8-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; P8-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_ugt_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f3
-; P9-NEXT:    fcmpo cr1, f2, f4
+; P9-NEXT:    fcmpo cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P9-NEXT:    fcmpo cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    cror 4*cr5+lt, 4*cr1+gt, 4*cr1+un
 ; P9-NEXT:    cror 4*cr5+gt, gt, un
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr5+lt
 ; P9-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_ugt_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f2, f4
-; NOVSX-NEXT:    fcmpo cr1, f1, f3
+; NOVSX-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    cror 4*cr5+lt, gt, un
 ; NOVSX-NEXT:    cror 4*cr5+gt, 4*cr1+gt, 4*cr1+un
 ; NOVSX-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ugt", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmps_uge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmps_uge_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f2, f4
-; P8-NEXT:    fcmpo cr1, f1, f3
+; P8-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, lt
 ; P8-NEXT:    crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_uge_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f2, f4
-; P9-NEXT:    fcmpo cr1, f1, f3
+; P9-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P9-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, lt
 ; P9-NEXT:    crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_uge_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f2, f4
-; NOVSX-NEXT:    fcmpo cr1, f1, f3
+; NOVSX-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, lt
 ; NOVSX-NEXT:    crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"uge", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmps_ueq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmps_ueq_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f2, f4
-; P8-NEXT:    fcmpo cr1, f1, f3
+; P8-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    cror 4*cr5+lt, eq, un
 ; P8-NEXT:    cror 4*cr5+gt, 4*cr1+eq, 4*cr1+un
 ; P8-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; P8-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; P8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_ueq_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f1, f3
-; P9-NEXT:    fcmpo cr1, f2, f4
+; P9-NEXT:    fcmpo cr0, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
+; P9-NEXT:    fcmpo cr1, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    cror 4*cr5+lt, 4*cr1+eq, 4*cr1+un
 ; P9-NEXT:    cror 4*cr5+gt, eq, un
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr5+lt
 ; P9-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, eq
 ; P9-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_ueq_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f2, f4
-; NOVSX-NEXT:    fcmpo cr1, f1, f3
+; NOVSX-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    cror 4*cr5+lt, eq, un
 ; NOVSX-NEXT:    cror 4*cr5+gt, 4*cr1+eq, 4*cr1+un
 ; NOVSX-NEXT:    crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
 ; NOVSX-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ueq", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @fcmps_une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; P8-LABEL: fcmps_une_ppcf128:
 ; P8:       # %bb.0:
-; P8-NEXT:    fcmpo cr0, f2, f4
-; P8-NEXT:    fcmpo cr1, f1, f3
+; P8-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P8-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P8-NEXT:    li r3, 1
 ; P8-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, eq
 ; P8-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; P8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_une_ppcf128:
 ; P9:       # %bb.0:
-; P9-NEXT:    fcmpo cr0, f2, f4
-; P9-NEXT:    fcmpo cr1, f1, f3
+; P9-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; P9-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, eq
 ; P9-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_une_ppcf128:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    fcmpo cr0, f2, f4
-; NOVSX-NEXT:    fcmpo cr1, f1, f3
+; NOVSX-NEXT:    fcmpo cr0, f2, f4 # Vec Uses: F2(VSR2)F4(VSR4)
+; NOVSX-NEXT:    fcmpo cr1, f1, f3 # Vec Uses: F1(VSR1)F3(VSR3)
 ; NOVSX-NEXT:    li r3, 1
 ; NOVSX-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, eq
 ; NOVSX-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv

llvm/test/CodeGen/PowerPC/fp-strict-round.ll

 declare float @llvm.experimental.constrained.trunc.f32(float, metadata)
 declare double @llvm.experimental.constrained.trunc.f64(double, metadata)
 declare <4 x float> @llvm.experimental.constrained.trunc.v4f32(<4 x float>, metadata)
 declare <2 x double> @llvm.experimental.constrained.trunc.v2f64(<2 x double>, metadata)
 
 define float @ceil_f32(float %f1) {
 ; P8-LABEL: ceil_f32:
 ; P8:       # %bb.0:
-; P8-NEXT:    xsrdpip f1, f1
+; P8-NEXT:    xsrdpip f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: ceil_f32:
 ; P9:       # %bb.0:
-; P9-NEXT:    xsrdpip f1, f1
+; P9-NEXT:    xsrdpip f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P9-NEXT:    blr
   %res = call float @llvm.experimental.constrained.ceil.f32(
                         float %f1,
                         metadata !"fpexcept.strict")
   ret float %res
 }
 
 define double @ceil_f64(double %f1) {
 ; P8-LABEL: ceil_f64:
 ; P8:       # %bb.0:
-; P8-NEXT:    xsrdpip f1, f1
+; P8-NEXT:    xsrdpip f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: ceil_f64:
 ; P9:       # %bb.0:
-; P9-NEXT:    xsrdpip f1, f1
+; P9-NEXT:    xsrdpip f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P9-NEXT:    blr
   %res = call double @llvm.experimental.constrained.ceil.f64(
                         double %f1,
                         metadata !"fpexcept.strict")
   ret double %res
 }
 
 define <4 x float> @ceil_v4f32(<4 x float> %vf1) {
 ; P8-LABEL: ceil_v4f32:
 ; P8:       # %bb.0:
-; P8-NEXT:    xvrspip v2, v2
+; P8-NEXT:    xvrspip v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: ceil_v4f32:
 ; P9:       # %bb.0:
-; P9-NEXT:    xvrspip v2, v2
+; P9-NEXT:    xvrspip v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; P9-NEXT:    blr
   %res = call <4 x float> @llvm.experimental.constrained.ceil.v4f32(
                         <4 x float> %vf1,
                         metadata !"fpexcept.strict")
   ret <4 x float> %res
 }
 
 define <2 x double> @ceil_v2f64(<2 x double> %vf1) {
 ; P8-LABEL: ceil_v2f64:
 ; P8:       # %bb.0:
-; P8-NEXT:    xvrdpip v2, v2
+; P8-NEXT:    xvrdpip v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: ceil_v2f64:
 ; P9:       # %bb.0:
-; P9-NEXT:    xvrdpip v2, v2
+; P9-NEXT:    xvrdpip v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; P9-NEXT:    blr
   %res = call <2 x double> @llvm.experimental.constrained.ceil.v2f64(
                         <2 x double> %vf1,
                         metadata !"fpexcept.strict")
   ret <2 x double> %res
 }
 
 define float @floor_f32(float %f1) {
 ; P8-LABEL: floor_f32:
 ; P8:       # %bb.0:
-; P8-NEXT:    xsrdpim f1, f1
+; P8-NEXT:    xsrdpim f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: floor_f32:
 ; P9:       # %bb.0:
-; P9-NEXT:    xsrdpim f1, f1
+; P9-NEXT:    xsrdpim f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P9-NEXT:    blr
   %res = call float @llvm.experimental.constrained.floor.f32(
                         float %f1,
                         metadata !"fpexcept.strict")
   ret float %res
 }
 
 define double @floor_f64(double %f1) {
 ; P8-LABEL: floor_f64:
 ; P8:       # %bb.0:
-; P8-NEXT:    xsrdpim f1, f1
+; P8-NEXT:    xsrdpim f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: floor_f64:
 ; P9:       # %bb.0:
-; P9-NEXT:    xsrdpim f1, f1
+; P9-NEXT:    xsrdpim f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P9-NEXT:    blr
   %res = call double @llvm.experimental.constrained.floor.f64(
                         double %f1,
                         metadata !"fpexcept.strict")
   ret double %res;
 }
 
 define <4 x float> @floor_v4f32(<4 x float> %vf1) {
 ; P8-LABEL: floor_v4f32:
 ; P8:       # %bb.0:
-; P8-NEXT:    xvrspim v2, v2
+; P8-NEXT:    xvrspim v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: floor_v4f32:
 ; P9:       # %bb.0:
-; P9-NEXT:    xvrspim v2, v2
+; P9-NEXT:    xvrspim v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; P9-NEXT:    blr
   %res = call <4 x float> @llvm.experimental.constrained.floor.v4f32(
                         <4 x float> %vf1,
                         metadata !"fpexcept.strict")
   ret <4 x float> %res;
 }
 
 define <2 x double> @floor_v2f64(<2 x double> %vf1) {
 ; P8-LABEL: floor_v2f64:
 ; P8:       # %bb.0:
-; P8-NEXT:    xvrdpim v2, v2
+; P8-NEXT:    xvrdpim v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: floor_v2f64:
 ; P9:       # %bb.0:
-; P9-NEXT:    xvrdpim v2, v2
+; P9-NEXT:    xvrdpim v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; P9-NEXT:    blr
   %res = call <2 x double> @llvm.experimental.constrained.floor.v2f64(
                         <2 x double> %vf1,
                         metadata !"fpexcept.strict")
   ret <2 x double> %res;
 }
 
 define double @nearbyint_f64(double %f1, double %f2) {

 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -176(r1)
 ; P8-NEXT:    .cfi_def_cfa_offset 176
 ; P8-NEXT:    .cfi_offset lr, 16
 ; P8-NEXT:    .cfi_offset v29, -48
 ; P8-NEXT:    .cfi_offset v30, -32
 ; P8-NEXT:    .cfi_offset v31, -16
-; P8-NEXT:    xxsldwi vs0, v2, v2, 3
+; P8-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; P8-NEXT:    li r3, 128
 ; P8-NEXT:    stxvd2x v29, r1, r3 # 16-byte Folded Spill
+; P8-NEXT:    # Vec Uses: V29(VSR61)
 ; P8-NEXT:    li r3, 144
 ; P8-NEXT:    stxvd2x v30, r1, r3 # 16-byte Folded Spill
+; P8-NEXT:    # Vec Uses: V30(VSR62)
 ; P8-NEXT:    li r3, 160
-; P8-NEXT:    xscvspdpn f1, vs0
+; P8-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; P8-NEXT:    stxvd2x v31, r1, r3 # 16-byte Folded Spill
-; P8-NEXT:    vmr v31, v2
+; P8-NEXT:    # Vec Uses: V31(VSR63)
+; P8-NEXT:    vmr v31, v2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; P8-NEXT:    bl nearbyintf
 ; P8-NEXT:    nop
-; P8-NEXT:    xxsldwi vs0, v31, v31, 1
-; P8-NEXT:    xxlor v30, f1, f1
-; P8-NEXT:    xscvspdpn f1, vs0
+; P8-NEXT:    xxsldwi vs0, v31, v31, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; P8-NEXT:    xxlor v30, f1, f1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; P8-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; P8-NEXT:    bl nearbyintf
 ; P8-NEXT:    nop
 ; P8-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; P8-NEXT:    xxmrghd vs0, vs1, v30
-; P8-NEXT:    xscvspdpn f1, v31
-; P8-NEXT:    xvcvdpsp v29, vs0
+; P8-NEXT:    xxmrghd vs0, vs1, v30 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)V30(VSR62)
+; P8-NEXT:    xscvspdpn f1, v31 # Vec Defs: F1(VSR1) Vec Uses: V31(VSR63)
+; P8-NEXT:    xvcvdpsp v29, vs0 # Vec Defs: V29(VSR61) Vec Uses: VSL0(VSR0)
 ; P8-NEXT:    bl nearbyintf
 ; P8-NEXT:    nop
-; P8-NEXT:    xxswapd vs0, v31
-; P8-NEXT:    xxlor v30, f1, f1
-; P8-NEXT:    xscvspdpn f1, vs0
+; P8-NEXT:    xxswapd vs0, v31 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; P8-NEXT:    xxlor v30, f1, f1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; P8-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; P8-NEXT:    bl nearbyintf
 ; P8-NEXT:    nop
 ; P8-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; P8-NEXT:    xxmrghd vs0, v30, vs1
+; P8-NEXT:    xxmrghd vs0, v30, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; P8-NEXT:    li r3, 160
 ; P8-NEXT:    lxvd2x v31, r1, r3 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V31(VSR63)
 ; P8-NEXT:    li r3, 144
 ; P8-NEXT:    lxvd2x v30, r1, r3 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V30(VSR62)
 ; P8-NEXT:    li r3, 128
-; P8-NEXT:    xvcvdpsp v2, vs0
-; P8-NEXT:    vmrgew v2, v2, v29
+; P8-NEXT:    xvcvdpsp v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
+; P8-NEXT:    vmrgew v2, v2, v29 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V29(VSR61)
 ; P8-NEXT:    lxvd2x v29, r1, r3 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V29(VSR61)
 ; P8-NEXT:    addi r1, r1, 176
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: nearbyint_v4f32:
 ; P9:       # %bb.0:
 ; P9-NEXT:    mflr r0
 ; P9-NEXT:    std r0, 16(r1)
 ; P9-NEXT:    stdu r1, -80(r1)
 ; P9-NEXT:    .cfi_def_cfa_offset 80
 ; P9-NEXT:    .cfi_offset lr, 16
 ; P9-NEXT:    .cfi_offset v29, -48
 ; P9-NEXT:    .cfi_offset v30, -32
 ; P9-NEXT:    .cfi_offset v31, -16
-; P9-NEXT:    xxsldwi vs0, v2, v2, 3
+; P9-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; P9-NEXT:    stxv v29, 32(r1) # 16-byte Folded Spill
-; P9-NEXT:    xscvspdpn f1, vs0
+; P9-NEXT:    # Vec Uses: V29(VSR61)
+; P9-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; P9-NEXT:    stxv v30, 48(r1) # 16-byte Folded Spill
+; P9-NEXT:    # Vec Uses: V30(VSR62)
 ; P9-NEXT:    stxv v31, 64(r1) # 16-byte Folded Spill
-; P9-NEXT:    vmr v31, v2
+; P9-NEXT:    # Vec Uses: V31(VSR63)
+; P9-NEXT:    vmr v31, v2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; P9-NEXT:    bl nearbyintf
 ; P9-NEXT:    nop
-; P9-NEXT:    xxsldwi vs0, v31, v31, 1
-; P9-NEXT:    xscpsgndp v30, f1, f1
-; P9-NEXT:    xscvspdpn f1, vs0
+; P9-NEXT:    xxsldwi vs0, v31, v31, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; P9-NEXT:    xscpsgndp v30, f1, f1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; P9-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; P9-NEXT:    bl nearbyintf
 ; P9-NEXT:    nop
 ; P9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; P9-NEXT:    xxmrghd vs0, vs1, v30
-; P9-NEXT:    xscvspdpn f1, v31
-; P9-NEXT:    xvcvdpsp v29, vs0
+; P9-NEXT:    xxmrghd vs0, vs1, v30 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)V30(VSR62)
+; P9-NEXT:    xscvspdpn f1, v31 # Vec Defs: F1(VSR1) Vec Uses: V31(VSR63)
+; P9-NEXT:    xvcvdpsp v29, vs0 # Vec Defs: V29(VSR61) Vec Uses: VSL0(VSR0)
 ; P9-NEXT:    bl nearbyintf
 ; P9-NEXT:    nop
-; P9-NEXT:    xxswapd vs0, v31
-; P9-NEXT:    xscpsgndp v30, f1, f1
-; P9-NEXT:    xscvspdpn f1, vs0
+; P9-NEXT:    xxswapd vs0, v31 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; P9-NEXT:    xscpsgndp v30, f1, f1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; P9-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; P9-NEXT:    bl nearbyintf
 ; P9-NEXT:    nop
 ; P9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; P9-NEXT:    xxmrghd vs0, v30, vs1
+; P9-NEXT:    xxmrghd vs0, v30, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; P9-NEXT:    lxv v31, 64(r1) # 16-byte Folded Reload
+; P9-NEXT:    # Vec Defs: V31(VSR63)
 ; P9-NEXT:    lxv v30, 48(r1) # 16-byte Folded Reload
-; P9-NEXT:    xvcvdpsp v2, vs0
-; P9-NEXT:    vmrgew v2, v2, v29
+; P9-NEXT:    # Vec Defs: V30(VSR62)
+; P9-NEXT:    xvcvdpsp v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
+; P9-NEXT:    vmrgew v2, v2, v29 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V29(VSR61)
 ; P9-NEXT:    lxv v29, 32(r1) # 16-byte Folded Reload
+; P9-NEXT:    # Vec Defs: V29(VSR61)
 ; P9-NEXT:    addi r1, r1, 80
 ; P9-NEXT:    ld r0, 16(r1)
 ; P9-NEXT:    mtlr r0
 ; P9-NEXT:    blr
   %res = call <4 x float> @llvm.experimental.constrained.nearbyint.v4f32(
                         <4 x float> %vf1,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict")
   ret <4 x float> %res
 }
 
 define <2 x double> @nearbyint_v2f64(<2 x double> %vf1, <2 x double> %vf2) {
 ; P8-LABEL: nearbyint_v2f64:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -160(r1)
 ; P8-NEXT:    .cfi_def_cfa_offset 160
 ; P8-NEXT:    .cfi_offset lr, 16
 ; P8-NEXT:    .cfi_offset v30, -32
 ; P8-NEXT:    .cfi_offset v31, -16
 ; P8-NEXT:    li r3, 128
 ; P8-NEXT:    stxvd2x v30, r1, r3 # 16-byte Folded Spill
+; P8-NEXT:    # Vec Uses: V30(VSR62)
 ; P8-NEXT:    li r3, 144
 ; P8-NEXT:    stxvd2x v31, r1, r3 # 16-byte Folded Spill
-; P8-NEXT:    vmr v31, v2
-; P8-NEXT:    xxlor f1, v31, v31
+; P8-NEXT:    # Vec Uses: V31(VSR63)
+; P8-NEXT:    vmr v31, v2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; P8-NEXT:    xxlor f1, v31, v31 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; P8-NEXT:    bl nearbyint
 ; P8-NEXT:    nop
-; P8-NEXT:    xxlor v30, f1, f1
-; P8-NEXT:    xxswapd vs1, v31
+; P8-NEXT:    xxlor v30, f1, f1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; P8-NEXT:    xxswapd vs1, v31 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; P8-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; P8-NEXT:    bl nearbyint
 ; P8-NEXT:    nop
 ; P8-NEXT:    li r3, 144
 ; P8-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; P8-NEXT:    xxmrghd v2, v30, vs1
+; P8-NEXT:    xxmrghd v2, v30, vs1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; P8-NEXT:    lxvd2x v31, r1, r3 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V31(VSR63)
 ; P8-NEXT:    li r3, 128
 ; P8-NEXT:    lxvd2x v30, r1, r3 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V30(VSR62)
 ; P8-NEXT:    addi r1, r1, 160
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: nearbyint_v2f64:
 ; P9:       # %bb.0:
 ; P9-NEXT:    mflr r0
 ; P9-NEXT:    std r0, 16(r1)
 ; P9-NEXT:    stdu r1, -64(r1)
 ; P9-NEXT:    .cfi_def_cfa_offset 64
 ; P9-NEXT:    .cfi_offset lr, 16
 ; P9-NEXT:    .cfi_offset v30, -32
 ; P9-NEXT:    .cfi_offset v31, -16
 ; P9-NEXT:    stxv v31, 48(r1) # 16-byte Folded Spill
-; P9-NEXT:    vmr v31, v2
-; P9-NEXT:    xscpsgndp f1, v31, v31
+; P9-NEXT:    # Vec Uses: V31(VSR63)
+; P9-NEXT:    vmr v31, v2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; P9-NEXT:    xscpsgndp f1, v31, v31 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; P9-NEXT:    stxv v30, 32(r1) # 16-byte Folded Spill
+; P9-NEXT:    # Vec Uses: V30(VSR62)
 ; P9-NEXT:    bl nearbyint
 ; P9-NEXT:    nop
-; P9-NEXT:    xscpsgndp v30, f1, f1
-; P9-NEXT:    xxswapd vs1, v31
+; P9-NEXT:    xscpsgndp v30, f1, f1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; P9-NEXT:    xxswapd vs1, v31 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; P9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; P9-NEXT:    bl nearbyint
 ; P9-NEXT:    nop
 ; P9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; P9-NEXT:    xxmrghd v2, v30, vs1
+; P9-NEXT:    xxmrghd v2, v30, vs1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; P9-NEXT:    lxv v31, 48(r1) # 16-byte Folded Reload
+; P9-NEXT:    # Vec Defs: V31(VSR63)
 ; P9-NEXT:    lxv v30, 32(r1) # 16-byte Folded Reload
+; P9-NEXT:    # Vec Defs: V30(VSR62)
 ; P9-NEXT:    addi r1, r1, 64
 ; P9-NEXT:    ld r0, 16(r1)
 ; P9-NEXT:    mtlr r0
 ; P9-NEXT:    blr
   %res = call <2 x double> @llvm.experimental.constrained.nearbyint.v2f64(
                         <2 x double> %vf1,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict")
   ret <2 x double> %res
 }
 
 define <4 x double> @fpext_v4f64_v4f32(<4 x float> %vf1) {
 ; P8-LABEL: fpext_v4f64_v4f32:
 ; P8:       # %bb.0:
-; P8-NEXT:    xxsldwi vs0, v2, v2, 1
-; P8-NEXT:    xxsldwi vs1, v2, v2, 3
-; P8-NEXT:    xxswapd vs3, v2
-; P8-NEXT:    xscvspdpn f2, v2
-; P8-NEXT:    xscvspdpn f0, vs0
-; P8-NEXT:    xscvspdpn f1, vs1
-; P8-NEXT:    xscvspdpn f3, vs3
-; P8-NEXT:    xxmrghd v2, vs2, vs0
-; P8-NEXT:    xxmrghd v3, vs3, vs1
+; P8-NEXT:    xxsldwi vs0, v2, v2, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; P8-NEXT:    xxsldwi vs1, v2, v2, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; P8-NEXT:    xxswapd vs3, v2 # Vec Defs: VSL3(VSR3) Vec Uses: V2(VSR34)V2(VSR34)
+; P8-NEXT:    xscvspdpn f2, v2 # Vec Defs: F2(VSR2) Vec Uses: V2(VSR34)
+; P8-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; P8-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; P8-NEXT:    xscvspdpn f3, vs3 # Vec Defs: F3(VSR3) Vec Uses: VSL3(VSR3)
+; P8-NEXT:    xxmrghd v2, vs2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL2(VSR2)VSL0(VSR0)
+; P8-NEXT:    xxmrghd v3, vs3, vs1 # Vec Defs: V3(VSR35) Vec Uses: VSL3(VSR3)VSL1(VSR1)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fpext_v4f64_v4f32:
 ; P9:       # %bb.0:
-; P9-NEXT:    xxsldwi vs0, v2, v2, 3
-; P9-NEXT:    xxswapd vs1, v2
-; P9-NEXT:    xscvspdpn f0, vs0
-; P9-NEXT:    xscvspdpn f1, vs1
-; P9-NEXT:    xxsldwi vs2, v2, v2, 1
-; P9-NEXT:    xscvspdpn f2, vs2
-; P9-NEXT:    xxmrghd vs0, vs1, vs0
-; P9-NEXT:    xscvspdpn f1, v2
-; P9-NEXT:    xxmrghd v3, vs1, vs2
-; P9-NEXT:    xxlor v2, vs0, vs0
+; P9-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; P9-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; P9-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; P9-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; P9-NEXT:    xxsldwi vs2, v2, v2, 1 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
+; P9-NEXT:    xscvspdpn f2, vs2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; P9-NEXT:    xxmrghd vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; P9-NEXT:    xscvspdpn f1, v2 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; P9-NEXT:    xxmrghd v3, vs1, vs2 # Vec Defs: V3(VSR35) Vec Uses: VSL1(VSR1)VSL2(VSR2)
+; P9-NEXT:    xxlor v2, vs0, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; P9-NEXT:    blr
   %res = call <4 x double> @llvm.experimental.constrained.fpext.v4f64.v4f32(
                         <4 x float> %vf1,
                         metadata !"fpexcept.strict")
   ret <4 x double> %res
 }
 
 define <2 x double> @fpext_v2f64_v2f32(<2 x float> %vf1) {
 ; P8-LABEL: fpext_v2f64_v2f32:
 ; P8:       # %bb.0:
-; P8-NEXT:    xxsldwi vs0, v2, v2, 1
-; P8-NEXT:    xscvspdpn f1, v2
-; P8-NEXT:    xscvspdpn f0, vs0
-; P8-NEXT:    xxmrghd v2, vs1, vs0
+; P8-NEXT:    xxsldwi vs0, v2, v2, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; P8-NEXT:    xscvspdpn f1, v2 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; P8-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; P8-NEXT:    xxmrghd v2, vs1, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL1(VSR1)VSL0(VSR0)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fpext_v2f64_v2f32:
 ; P9:       # %bb.0:
-; P9-NEXT:    xxsldwi vs0, v2, v2, 3
-; P9-NEXT:    xxswapd vs1, v2
-; P9-NEXT:    xscvspdpn f0, vs0
-; P9-NEXT:    xscvspdpn f1, vs1
-; P9-NEXT:    xxmrghd v2, vs1, vs0
+; P9-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; P9-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; P9-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; P9-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; P9-NEXT:    xxmrghd v2, vs1, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL1(VSR1)VSL0(VSR0)
 ; P9-NEXT:    blr
   %res = call <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f32(
                         <2 x float> %vf1,
                         metadata !"fpexcept.strict")
   ret <2 x double> %res
 }
 
 define float @fptrunc_f32_f64(double %f1) {
 ; P8-LABEL: fptrunc_f32_f64:
 ; P8:       # %bb.0:
-; P8-NEXT:    xsrsp f1, f1
+; P8-NEXT:    xsrsp f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fptrunc_f32_f64:
 ; P9:       # %bb.0:
-; P9-NEXT:    xsrsp f1, f1
+; P9-NEXT:    xsrsp f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P9-NEXT:    blr
   %res = call float @llvm.experimental.constrained.fptrunc.f32.f64(
                         double %f1,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict")
   ret float %res;
 }
 
 define <4 x float> @fptrunc_v4f32_v4f64(<4 x double> %vf1) {
 ; P8-LABEL: fptrunc_v4f32_v4f64:
 ; P8:       # %bb.0:
-; P8-NEXT:    xxmrgld vs0, v2, v3
-; P8-NEXT:    xxmrghd vs1, v2, v3
-; P8-NEXT:    xvcvdpsp v2, vs0
-; P8-NEXT:    xvcvdpsp v3, vs1
-; P8-NEXT:    vmrgew v2, v3, v2
+; P8-NEXT:    xxmrgld vs0, v2, v3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V3(VSR35)
+; P8-NEXT:    xxmrghd vs1, v2, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V3(VSR35)
+; P8-NEXT:    xvcvdpsp v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
+; P8-NEXT:    xvcvdpsp v3, vs1 # Vec Defs: V3(VSR35) Vec Uses: VSL1(VSR1)
+; P8-NEXT:    vmrgew v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fptrunc_v4f32_v4f64:
 ; P9:       # %bb.0:
-; P9-NEXT:    xxmrgld vs0, v3, v2
-; P9-NEXT:    xvcvdpsp v4, vs0
-; P9-NEXT:    xxmrghd vs0, v3, v2
-; P9-NEXT:    xvcvdpsp v2, vs0
-; P9-NEXT:    vmrgew v2, v2, v4
+; P9-NEXT:    xxmrgld vs0, v3, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V2(VSR34)
+; P9-NEXT:    xvcvdpsp v4, vs0 # Vec Defs: V4(VSR36) Vec Uses: VSL0(VSR0)
+; P9-NEXT:    xxmrghd vs0, v3, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V2(VSR34)
+; P9-NEXT:    xvcvdpsp v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
+; P9-NEXT:    vmrgew v2, v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
 ; P9-NEXT:    blr
   %res = call <4 x float> @llvm.experimental.constrained.fptrunc.v4f32.v4f64(
                         <4 x double> %vf1,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict")
   ret <4 x float> %res
 }
 
 define <2 x float> @fptrunc_v2f32_v2f64(<2 x double> %vf1) {
 ; P8-LABEL: fptrunc_v2f32_v2f64:
 ; P8:       # %bb.0:
-; P8-NEXT:    xxswapd vs0, v2
-; P8-NEXT:    xsrsp f1, v2
-; P8-NEXT:    xsrsp f0, f0
-; P8-NEXT:    xscvdpspn v2, f1
-; P8-NEXT:    xscvdpspn v3, f0
-; P8-NEXT:    vmrgow v2, v2, v3
+; P8-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; P8-NEXT:    xsrsp f1, v2 # Vec Defs: F1(VSR1) Vec Uses: VF2(VSR2)
+; P8-NEXT:    xsrsp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; P8-NEXT:    xscvdpspn v2, f1 # Vec Defs: V2(VSR34) Vec Uses: F1(VSR1)
+; P8-NEXT:    xscvdpspn v3, f0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; P8-NEXT:    vmrgow v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fptrunc_v2f32_v2f64:
 ; P9:       # %bb.0:
-; P9-NEXT:    xsrsp f0, v2
-; P9-NEXT:    xscvdpspn v3, f0
-; P9-NEXT:    xxswapd vs0, v2
-; P9-NEXT:    xsrsp f0, f0
-; P9-NEXT:    xscvdpspn v2, f0
-; P9-NEXT:    vmrghw v2, v3, v2
+; P9-NEXT:    xsrsp f0, v2 # Vec Defs: F0(VSR0) Vec Uses: VF2(VSR2)
+; P9-NEXT:    xscvdpspn v3, f0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; P9-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; P9-NEXT:    xsrsp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; P9-NEXT:    xscvdpspn v2, f0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; P9-NEXT:    vmrghw v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; P9-NEXT:    blr
   %res = call <2 x float> @llvm.experimental.constrained.fptrunc.v2f32.v2f64(
                         <2 x double> %vf1,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict")
   ret <2 x float> %res
 }
 
 define float @round_f32(float %f1) {
 ; P8-LABEL: round_f32:
 ; P8:       # %bb.0:
-; P8-NEXT:    xsrdpi f1, f1
+; P8-NEXT:    xsrdpi f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: round_f32:
 ; P9:       # %bb.0:
-; P9-NEXT:    xsrdpi f1, f1
+; P9-NEXT:    xsrdpi f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P9-NEXT:    blr
   %res = call float @llvm.experimental.constrained.round.f32(
                         float %f1,
                         metadata !"fpexcept.strict")
   ret float %res
 }
 
 define double @round_f64(double %f1) {
 ; P8-LABEL: round_f64:
 ; P8:       # %bb.0:
-; P8-NEXT:    xsrdpi f1, f1
+; P8-NEXT:    xsrdpi f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: round_f64:
 ; P9:       # %bb.0:
-; P9-NEXT:    xsrdpi f1, f1
+; P9-NEXT:    xsrdpi f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P9-NEXT:    blr
   %res = call double @llvm.experimental.constrained.round.f64(
                         double %f1,
                         metadata !"fpexcept.strict")
   ret double %res
 }
 
 define <4 x float> @round_v4f32(<4 x float> %vf1) {
 ; P8-LABEL: round_v4f32:
 ; P8:       # %bb.0:
-; P8-NEXT:    xvrspi v2, v2
+; P8-NEXT:    xvrspi v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: round_v4f32:
 ; P9:       # %bb.0:
-; P9-NEXT:    xvrspi v2, v2
+; P9-NEXT:    xvrspi v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; P9-NEXT:    blr
   %res = call <4 x float> @llvm.experimental.constrained.round.v4f32(
                         <4 x float> %vf1,
                         metadata !"fpexcept.strict")
   ret <4 x float> %res
 }
 
 define <2 x double> @round_v2f64(<2 x double> %vf1) {
 ; P8-LABEL: round_v2f64:
 ; P8:       # %bb.0:
-; P8-NEXT:    xvrdpi v2, v2
+; P8-NEXT:    xvrdpi v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: round_v2f64:
 ; P9:       # %bb.0:
-; P9-NEXT:    xvrdpi v2, v2
+; P9-NEXT:    xvrdpi v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; P9-NEXT:    blr
   %res = call <2 x double> @llvm.experimental.constrained.round.v2f64(
                         <2 x double> %vf1,
                         metadata !"fpexcept.strict")
   ret <2 x double> %res
 }
 
 define float @trunc_f32(float %f1) {
 ; P8-LABEL: trunc_f32:
 ; P8:       # %bb.0:
-; P8-NEXT:    xsrdpiz f1, f1
+; P8-NEXT:    xsrdpiz f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: trunc_f32:
 ; P9:       # %bb.0:
-; P9-NEXT:    xsrdpiz f1, f1
+; P9-NEXT:    xsrdpiz f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P9-NEXT:    blr
   %res = call float @llvm.experimental.constrained.trunc.f32(
                         float %f1,
                         metadata !"fpexcept.strict")
   ret float %res
 }
 
 define double @trunc_f64(double %f1) {
 ; P8-LABEL: trunc_f64:
 ; P8:       # %bb.0:
-; P8-NEXT:    xsrdpiz f1, f1
+; P8-NEXT:    xsrdpiz f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: trunc_f64:
 ; P9:       # %bb.0:
-; P9-NEXT:    xsrdpiz f1, f1
+; P9-NEXT:    xsrdpiz f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; P9-NEXT:    blr
   %res = call double @llvm.experimental.constrained.trunc.f64(
                         double %f1,
                         metadata !"fpexcept.strict")
   ret double %res
 }
 
 define <4 x float> @trunc_v4f32(<4 x float> %vf1) {
 ; P8-LABEL: trunc_v4f32:
 ; P8:       # %bb.0:
-; P8-NEXT:    xvrspiz v2, v2
+; P8-NEXT:    xvrspiz v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: trunc_v4f32:
 ; P9:       # %bb.0:
-; P9-NEXT:    xvrspiz v2, v2
+; P9-NEXT:    xvrspiz v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; P9-NEXT:    blr
   %res = call <4 x float> @llvm.experimental.constrained.trunc.v4f32(
                         <4 x float> %vf1,
                         metadata !"fpexcept.strict")
   ret <4 x float> %res
 }
 
 define <2 x double> @trunc_v2f64(<2 x double> %vf1) {
 ; P8-LABEL: trunc_v2f64:
 ; P8:       # %bb.0:
-; P8-NEXT:    xvrdpiz v2, v2
+; P8-NEXT:    xvrdpiz v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: trunc_v2f64:
 ; P9:       # %bb.0:
-; P9-NEXT:    xvrdpiz v2, v2
+; P9-NEXT:    xvrdpiz v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; P9-NEXT:    blr
   %res = call <2 x double> @llvm.experimental.constrained.trunc.v2f64(
                         <2 x double> %vf1,
                         metadata !"fpexcept.strict")
   ret <2 x double> %res
 }

llvm/test/CodeGen/PowerPC/frem.ll

 ; CHECK-NEXT:    std 0, 16(1)
 ; CHECK-NEXT:    stdu 1, -96(1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 96
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    .cfi_offset v28, -64
 ; CHECK-NEXT:    .cfi_offset v29, -48
 ; CHECK-NEXT:    .cfi_offset v30, -32
 ; CHECK-NEXT:    .cfi_offset v31, -16
-; CHECK-NEXT:    xxsldwi 0, 34, 34, 3
+; CHECK-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    stxv 60, 32(1) # 16-byte Folded Spill
-; CHECK-NEXT:    xscvspdpn 1, 0
-; CHECK-NEXT:    xxsldwi 0, 35, 35, 3
+; CHECK-NEXT:    # Vec Uses: V28(VSR60)
+; CHECK-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; CHECK-NEXT:    xxsldwi 0, 35, 35, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-NEXT:    stxv 61, 48(1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V29(VSR61)
 ; CHECK-NEXT:    stxv 62, 64(1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V30(VSR62)
 ; CHECK-NEXT:    stxv 63, 80(1) # 16-byte Folded Spill
-; CHECK-NEXT:    xscvspdpn 2, 0
-; CHECK-NEXT:    vmr 31, 3
-; CHECK-NEXT:    vmr 30, 2
+; CHECK-NEXT:    # Vec Uses: V31(VSR63)
+; CHECK-NEXT:    xscvspdpn 2, 0 # Vec Defs: F2(VSR2) Vec Uses: VSL0(VSR0)
+; CHECK-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    bl fmodf
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    xxsldwi 0, 62, 62, 1
-; CHECK-NEXT:    xscpsgndp 61, 1, 1
-; CHECK-NEXT:    xscvspdpn 1, 0
-; CHECK-NEXT:    xxsldwi 0, 63, 63, 1
-; CHECK-NEXT:    xscvspdpn 2, 0
+; CHECK-NEXT:    xxsldwi 0, 62, 62, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; CHECK-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; CHECK-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; CHECK-NEXT:    xxsldwi 0, 63, 63, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; CHECK-NEXT:    xscvspdpn 2, 0 # Vec Defs: F2(VSR2) Vec Uses: VSL0(VSR0)
 ; CHECK-NEXT:    bl fmodf
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; CHECK-NEXT:    xxmrghd 0, 1, 61
-; CHECK-NEXT:    xscvspdpn 1, 62
-; CHECK-NEXT:    xscvspdpn 2, 63
-; CHECK-NEXT:    xvcvdpsp 60, 0
+; CHECK-NEXT:    xxmrghd 0, 1, 61 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)V29(VSR61)
+; CHECK-NEXT:    xscvspdpn 1, 62 # Vec Defs: F1(VSR1) Vec Uses: V30(VSR62)
+; CHECK-NEXT:    xscvspdpn 2, 63 # Vec Defs: F2(VSR2) Vec Uses: V31(VSR63)
+; CHECK-NEXT:    xvcvdpsp 60, 0 # Vec Defs: V28(VSR60) Vec Uses: VSL0(VSR0)
 ; CHECK-NEXT:    bl fmodf
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    xxswapd 0, 62
-; CHECK-NEXT:    xscpsgndp 61, 1, 1
-; CHECK-NEXT:    xscvspdpn 1, 0
-; CHECK-NEXT:    xxswapd 0, 63
-; CHECK-NEXT:    xscvspdpn 2, 0
+; CHECK-NEXT:    xxswapd 0, 62 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; CHECK-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; CHECK-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; CHECK-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; CHECK-NEXT:    xscvspdpn 2, 0 # Vec Defs: F2(VSR2) Vec Uses: VSL0(VSR0)
 ; CHECK-NEXT:    bl fmodf
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; CHECK-NEXT:    xxmrghd 0, 61, 1
+; CHECK-NEXT:    xxmrghd 0, 61, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; CHECK-NEXT:    lxv 63, 80(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-NEXT:    lxv 62, 64(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V30(VSR62)
 ; CHECK-NEXT:    lxv 61, 48(1) # 16-byte Folded Reload
-; CHECK-NEXT:    xvcvdpsp 34, 0
-; CHECK-NEXT:    vmrgew 2, 2, 28
+; CHECK-NEXT:    # Vec Defs: V29(VSR61)
+; CHECK-NEXT:    xvcvdpsp 34, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
+; CHECK-NEXT:    vmrgew 2, 2, 28 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V28(VSR60)
 ; CHECK-NEXT:    lxv 60, 32(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V28(VSR60)
 ; CHECK-NEXT:    addi 1, 1, 96
 ; CHECK-NEXT:    ld 0, 16(1)
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 entry:
   %rem = frem fast <4 x float> %a, %b
   ret <4 x float> %rem
 }
 
 define <2 x double> @frem2x64(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: frem2x64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    std 0, 16(1)
 ; CHECK-NEXT:    stdu 1, -80(1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    .cfi_offset v29, -48
 ; CHECK-NEXT:    .cfi_offset v30, -32
 ; CHECK-NEXT:    .cfi_offset v31, -16
 ; CHECK-NEXT:    stxv 62, 48(1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V30(VSR62)
 ; CHECK-NEXT:    stxv 63, 64(1) # 16-byte Folded Spill
-; CHECK-NEXT:    vmr 31, 3
-; CHECK-NEXT:    xscpsgndp 2, 63, 63
-; CHECK-NEXT:    vmr 30, 2
-; CHECK-NEXT:    xscpsgndp 1, 62, 62
+; CHECK-NEXT:    # Vec Uses: V31(VSR63)
+; CHECK-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
+; CHECK-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    xscpsgndp 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; CHECK-NEXT:    stxv 61, 32(1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V29(VSR61)
 ; CHECK-NEXT:    bl fmod
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    xscpsgndp 61, 1, 1
-; CHECK-NEXT:    xxswapd 1, 62
-; CHECK-NEXT:    xxswapd 2, 63
+; CHECK-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; CHECK-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
+; CHECK-NEXT:    xxswapd 2, 63 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; CHECK-NEXT:    bl fmod
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; CHECK-NEXT:    xxmrghd 34, 61, 1
+; CHECK-NEXT:    xxmrghd 34, 61, 1 # Vec Defs: V2(VSR34) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; CHECK-NEXT:    lxv 63, 64(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-NEXT:    lxv 62, 48(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V30(VSR62)
 ; CHECK-NEXT:    lxv 61, 32(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V29(VSR61)
 ; CHECK-NEXT:    addi 1, 1, 80
 ; CHECK-NEXT:    ld 0, 16(1)
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 entry:
   %rem = frem fast <2 x double> %a, %b
   ret <2 x double> %rem
 }

llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll

 ; P8-NEXT:    addi r1, r1, 32
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: loadd:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r3, r3, 2
-; CHECK-NEXT:    lxsihzx f0, 0, r3
-; CHECK-NEXT:    xscvhpdp f1, f0
+; CHECK-NEXT:    lxsihzx f0, 0, r3 # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    xscvhpdp f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: loadd:
 ; SOFT:       # %bb.0: # %entry
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r0, 16(r1)
 ; SOFT-NEXT:    stdu r1, -32(r1)
 ; SOFT-NEXT:    lhz r3, 2(r3)

 ; P8-NEXT:    addi r1, r1, 32
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: loadf:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r3, r3, 2
-; CHECK-NEXT:    lxsihzx f0, 0, r3
-; CHECK-NEXT:    xscvhpdp f1, f0
+; CHECK-NEXT:    lxsihzx f0, 0, r3 # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    xscvhpdp f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: loadf:
 ; SOFT:       # %bb.0: # %entry
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r0, 16(r1)
 ; SOFT-NEXT:    stdu r1, -32(r1)
 ; SOFT-NEXT:    lhz r3, 2(r3)

 ; P8-NEXT:    addi r1, r1, 48
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: stored:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xscvdphp f0, f1
-; CHECK-NEXT:    stxsihx f0, 0, r3
+; CHECK-NEXT:    xscvdphp f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    stxsihx f0, 0, r3 # Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: stored:
 ; SOFT:       # %bb.0: # %entry
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; SOFT-NEXT:    std r0, 16(r1)
 ; SOFT-NEXT:    stdu r1, -48(r1)

 ; P8-NEXT:    addi r1, r1, 48
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: storef:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xscvdphp f0, f1
-; CHECK-NEXT:    stxsihx f0, 0, r3
+; CHECK-NEXT:    xscvdphp f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    stxsihx f0, 0, r3 # Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: storef:
 ; SOFT:       # %bb.0: # %entry
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; SOFT-NEXT:    std r0, 16(r1)
 ; SOFT-NEXT:    stdu r1, -48(r1)

 ; P8-NEXT:    nop
 ; P8-NEXT:    addi r1, r1, 32
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: test_extend32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lxsihzx f0, 0, r3
-; CHECK-NEXT:    xscvhpdp f1, f0
+; CHECK-NEXT:    lxsihzx f0, 0, r3 # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    xscvhpdp f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: test_extend32:
 ; SOFT:       # %bb.0:
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r0, 16(r1)
 ; SOFT-NEXT:    stdu r1, -32(r1)
 ; SOFT-NEXT:    lhz r3, 0(r3)

 ; P8-NEXT:    nop
 ; P8-NEXT:    addi r1, r1, 32
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: test_extend64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lxsihzx f0, 0, r3
-; CHECK-NEXT:    xscvhpdp f1, f0
+; CHECK-NEXT:    lxsihzx f0, 0, r3 # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    xscvhpdp f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: test_extend64:
 ; SOFT:       # %bb.0:
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r0, 16(r1)
 ; SOFT-NEXT:    stdu r1, -32(r1)
 ; SOFT-NEXT:    lhz r3, 0(r3)

 ; P8-NEXT:    addi r1, r1, 48
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: test_trunc32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xscvdphp f0, f1
-; CHECK-NEXT:    stxsihx f0, 0, r4
+; CHECK-NEXT:    xscvdphp f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    stxsihx f0, 0, r4 # Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: test_trunc32:
 ; SOFT:       # %bb.0:
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; SOFT-NEXT:    std r0, 16(r1)
 ; SOFT-NEXT:    stdu r1, -48(r1)

 ; P8-NEXT:    addi r1, r1, 48
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: test_trunc64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xscvdphp f0, f1
-; CHECK-NEXT:    stxsihx f0, 0, r4
+; CHECK-NEXT:    xscvdphp f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    stxsihx f0, 0, r4 # Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: test_trunc64:
 ; SOFT:       # %bb.0:
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; SOFT-NEXT:    std r0, 16(r1)
 ; SOFT-NEXT:    stdu r1, -48(r1)

 ; P8-LABEL: test_fptosi_i64:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -32(r1)
 ; P8-NEXT:    lhz r3, 0(r3)
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
-; P8-NEXT:    xscvdpsxds f0, f1
-; P8-NEXT:    mffprd r3, f0
+; P8-NEXT:    xscvdpsxds f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; P8-NEXT:    mffprd r3, f0 # Vec Uses: F0(VSR0)
 ; P8-NEXT:    addi r1, r1, 32
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: test_fptosi_i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    mtfprwz f0, r3
-; CHECK-NEXT:    xscvhpdp f0, f0
-; CHECK-NEXT:    xscvdpsxds f0, f0
-; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    mtfprwz f0, r3 # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    xscvhpdp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    xscvdpsxds f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    mffprd r3, f0 # Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: test_fptosi_i64:
 ; SOFT:       # %bb.0:
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r0, 16(r1)
 ; SOFT-NEXT:    stdu r1, -32(r1)
 ; SOFT-NEXT:    lhz r3, 0(r3)

 }
 define void @test_sitofp_i64(i64 %a, half* %p) #0 {
 ; P8-LABEL: test_sitofp_i64:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -48(r1)
-; P8-NEXT:    mtfprd f0, r3
+; P8-NEXT:    mtfprd f0, r3 # Vec Defs: F0(VSR0)
 ; P8-NEXT:    mr r30, r4
-; P8-NEXT:    xscvsxdsp f1, f0
+; P8-NEXT:    xscvsxdsp f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; P8-NEXT:    bl __gnu_f2h_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    sth r3, 0(r30)
 ; P8-NEXT:    addi r1, r1, 48
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: test_sitofp_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    mtfprd f0, r3
-; CHECK-NEXT:    xscvsxdsp f0, f0
-; CHECK-NEXT:    xscvdphp f0, f0
-; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    mtfprd f0, r3 # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    xscvsxdsp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    xscvdphp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    mffprwz r3, f0 # Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    sth r3, 0(r4)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: test_sitofp_i64:
 ; SOFT:       # %bb.0:
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; SOFT-NEXT:    std r0, 16(r1)

 ; P8-LABEL: test_fptoui_i64:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -32(r1)
 ; P8-NEXT:    lhz r3, 0(r3)
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
-; P8-NEXT:    xscvdpuxds f0, f1
-; P8-NEXT:    mffprd r3, f0
+; P8-NEXT:    xscvdpuxds f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; P8-NEXT:    mffprd r3, f0 # Vec Uses: F0(VSR0)
 ; P8-NEXT:    addi r1, r1, 32
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: test_fptoui_i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    mtfprwz f0, r3
-; CHECK-NEXT:    xscvhpdp f0, f0
-; CHECK-NEXT:    xscvdpuxds f0, f0
-; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    mtfprwz f0, r3 # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    xscvhpdp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    xscvdpuxds f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    mffprd r3, f0 # Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: test_fptoui_i64:
 ; SOFT:       # %bb.0:
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r0, 16(r1)
 ; SOFT-NEXT:    stdu r1, -32(r1)
 ; SOFT-NEXT:    lhz r3, 0(r3)

 }
 define void @test_uitofp_i64(i64 %a, half* %p) #0 {
 ; P8-LABEL: test_uitofp_i64:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -48(r1)
-; P8-NEXT:    mtfprd f0, r3
+; P8-NEXT:    mtfprd f0, r3 # Vec Defs: F0(VSR0)
 ; P8-NEXT:    mr r30, r4
-; P8-NEXT:    xscvuxdsp f1, f0
+; P8-NEXT:    xscvuxdsp f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; P8-NEXT:    bl __gnu_f2h_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    sth r3, 0(r30)
 ; P8-NEXT:    addi r1, r1, 48
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: test_uitofp_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    mtfprd f0, r3
-; CHECK-NEXT:    xscvuxdsp f0, f0
-; CHECK-NEXT:    xscvdphp f0, f0
-; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    mtfprd f0, r3 # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    xscvuxdsp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    xscvdphp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    mffprwz r3, f0 # Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    sth r3, 0(r4)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: test_uitofp_i64:
 ; SOFT:       # %bb.0:
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; SOFT-NEXT:    std r0, 16(r1)

 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    li r4, 48
 ; P8-NEXT:    std r30, 96(r1) # 8-byte Folded Spill
 ; P8-NEXT:    mr r30, r3
 ; P8-NEXT:    lhz r3, 6(r3)
 ; P8-NEXT:    stxvd2x vs61, r1, r4 # 16-byte Folded Spill
+; P8-NEXT:    # Vec Uses: V29(VSR61)
 ; P8-NEXT:    li r4, 64
 ; P8-NEXT:    stxvd2x vs62, r1, r4 # 16-byte Folded Spill
+; P8-NEXT:    # Vec Uses: V30(VSR62)
 ; P8-NEXT:    li r4, 80
 ; P8-NEXT:    stxvd2x vs63, r1, r4 # 16-byte Folded Spill
+; P8-NEXT:    # Vec Uses: V31(VSR63)
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    lhz r3, 2(r30)
-; P8-NEXT:    xxlor vs63, f1, f1
+; P8-NEXT:    xxlor vs63, f1, f1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    lhz r3, 4(r30)
-; P8-NEXT:    xxlor vs62, f1, f1
+; P8-NEXT:    xxlor vs62, f1, f1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    lhz r3, 0(r30)
-; P8-NEXT:    xxlor vs61, f1, f1
+; P8-NEXT:    xxlor vs61, f1, f1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; P8-NEXT:    xxmrghd vs0, vs63, vs62
+; P8-NEXT:    xxmrghd vs0, vs63, vs62 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V30(VSR62)
 ; P8-NEXT:    li r3, 80
 ; P8-NEXT:    ld r30, 96(r1) # 8-byte Folded Reload
-; P8-NEXT:    xxmrghd vs1, vs61, vs1
+; P8-NEXT:    xxmrghd vs1, vs61, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; P8-NEXT:    lxvd2x vs63, r1, r3 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V31(VSR63)
 ; P8-NEXT:    li r3, 64
 ; P8-NEXT:    lxvd2x vs62, r1, r3 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V30(VSR62)
 ; P8-NEXT:    li r3, 48
-; P8-NEXT:    xvcvdpsp vs34, vs0
+; P8-NEXT:    xvcvdpsp vs34, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
 ; P8-NEXT:    lxvd2x vs61, r1, r3 # 16-byte Folded Reload
-; P8-NEXT:    xvcvdpsp vs35, vs1
-; P8-NEXT:    vmrgew v2, v2, v3
+; P8-NEXT:    # Vec Defs: V29(VSR61)
+; P8-NEXT:    xvcvdpsp vs35, vs1 # Vec Defs: V3(VSR35) Vec Uses: VSL1(VSR1)
+; P8-NEXT:    vmrgew v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: test_extend32_vec4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lhz r4, 6(r3)
-; CHECK-NEXT:    mtfprwz f0, r4
-; CHECK-NEXT:    xscvhpdp f0, f0
+; CHECK-NEXT:    mtfprwz f0, r4 # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    xscvhpdp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    lhz r4, 2(r3)
-; CHECK-NEXT:    mtfprwz f1, r4
-; CHECK-NEXT:    xscvhpdp f1, f1
+; CHECK-NEXT:    mtfprwz f1, r4 # Vec Defs: F1(VSR1)
+; CHECK-NEXT:    xscvhpdp f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    lhz r4, 4(r3)
-; CHECK-NEXT:    mtfprwz f2, r4
-; CHECK-NEXT:    xscvhpdp f2, f2
+; CHECK-NEXT:    mtfprwz f2, r4 # Vec Defs: F2(VSR2)
+; CHECK-NEXT:    xscvhpdp f2, f2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    xxmrghd vs0, vs0, vs1
-; CHECK-NEXT:    mtfprwz f3, r3
-; CHECK-NEXT:    xvcvdpsp vs35, vs0
-; CHECK-NEXT:    xscvhpdp f3, f3
-; CHECK-NEXT:    xxmrghd vs2, vs2, vs3
-; CHECK-NEXT:    xvcvdpsp vs34, vs2
-; CHECK-NEXT:    vmrgew v2, v3, v2
+; CHECK-NEXT:    xxmrghd vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; CHECK-NEXT:    mtfprwz f3, r3 # Vec Defs: F3(VSR3)
+; CHECK-NEXT:    xvcvdpsp vs35, vs0 # Vec Defs: V3(VSR35) Vec Uses: VSL0(VSR0)
+; CHECK-NEXT:    xscvhpdp f3, f3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; CHECK-NEXT:    xxmrghd vs2, vs2, vs3 # Vec Defs: VSL2(VSR2) Vec Uses: VSL2(VSR2)VSL3(VSR3)
+; CHECK-NEXT:    xvcvdpsp vs34, vs2 # Vec Defs: V2(VSR34) Vec Uses: VSL2(VSR2)
+; CHECK-NEXT:    vmrgew v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: test_extend32_vec4:
 ; SOFT:       # %bb.0:
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r27, -40(r1) # 8-byte Folded Spill
 ; SOFT-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
 ; SOFT-NEXT:    std r29, -24(r1) # 8-byte Folded Spill

 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    li r4, 48
 ; P8-NEXT:    std r30, 96(r1) # 8-byte Folded Spill
 ; P8-NEXT:    mr r30, r3
 ; P8-NEXT:    lhz r3, 6(r3)
 ; P8-NEXT:    stxvd2x vs61, r1, r4 # 16-byte Folded Spill
+; P8-NEXT:    # Vec Uses: V29(VSR61)
 ; P8-NEXT:    li r4, 64
 ; P8-NEXT:    stxvd2x vs62, r1, r4 # 16-byte Folded Spill
+; P8-NEXT:    # Vec Uses: V30(VSR62)
 ; P8-NEXT:    li r4, 80
 ; P8-NEXT:    stxvd2x vs63, r1, r4 # 16-byte Folded Spill
+; P8-NEXT:    # Vec Uses: V31(VSR63)
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    lhz r3, 4(r30)
-; P8-NEXT:    xxlor vs63, f1, f1
+; P8-NEXT:    xxlor vs63, f1, f1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    lhz r3, 2(r30)
-; P8-NEXT:    xxlor vs62, f1, f1
+; P8-NEXT:    xxlor vs62, f1, f1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    lhz r3, 0(r30)
-; P8-NEXT:    xxlor vs61, f1, f1
+; P8-NEXT:    xxlor vs61, f1, f1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    li r3, 80
-; P8-NEXT:    xxmrghd vs35, vs63, vs62
+; P8-NEXT:    xxmrghd vs35, vs63, vs62 # Vec Defs: V3(VSR35) Vec Uses: V31(VSR63)V30(VSR62)
 ; P8-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; P8-NEXT:    xxmrghd vs34, vs61, vs1
+; P8-NEXT:    xxmrghd vs34, vs61, vs1 # Vec Defs: V2(VSR34) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; P8-NEXT:    ld r30, 96(r1) # 8-byte Folded Reload
 ; P8-NEXT:    lxvd2x vs63, r1, r3 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V31(VSR63)
 ; P8-NEXT:    li r3, 64
 ; P8-NEXT:    lxvd2x vs62, r1, r3 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V30(VSR62)
 ; P8-NEXT:    li r3, 48
 ; P8-NEXT:    lxvd2x vs61, r1, r3 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V29(VSR61)
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: test_extend64_vec4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lhz r4, 6(r3)
 ; CHECK-NEXT:    lhz r5, 4(r3)
 ; CHECK-NEXT:    lhz r6, 2(r3)
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    mtfprwz f0, r3
-; CHECK-NEXT:    mtfprwz f1, r6
-; CHECK-NEXT:    xscvhpdp f0, f0
-; CHECK-NEXT:    xscvhpdp f1, f1
-; CHECK-NEXT:    xxmrghd vs34, vs1, vs0
-; CHECK-NEXT:    mtfprwz f0, r5
-; CHECK-NEXT:    mtfprwz f1, r4
-; CHECK-NEXT:    xscvhpdp f0, f0
-; CHECK-NEXT:    xscvhpdp f1, f1
-; CHECK-NEXT:    xxmrghd vs35, vs1, vs0
+; CHECK-NEXT:    mtfprwz f0, r3 # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    mtfprwz f1, r6 # Vec Defs: F1(VSR1)
+; CHECK-NEXT:    xscvhpdp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    xscvhpdp f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    xxmrghd vs34, vs1, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; CHECK-NEXT:    mtfprwz f0, r5 # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    mtfprwz f1, r4 # Vec Defs: F1(VSR1)
+; CHECK-NEXT:    xscvhpdp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    xscvhpdp f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    xxmrghd vs35, vs1, vs0 # Vec Defs: V3(VSR35) Vec Uses: VSL1(VSR1)VSL0(VSR0)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: test_extend64_vec4:
 ; SOFT:       # %bb.0:
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r27, -40(r1) # 8-byte Folded Spill
 ; SOFT-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
 ; SOFT-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
; SOFT-NEXT:    blr
   ret <4 x double> %b
 }
 define void @test_trunc32_vec4(<4 x float> %a, <4 x half>* %p) #0 {
 ; P8-LABEL: test_trunc32_vec4:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -112(r1)
-; P8-NEXT:    xxsldwi vs0, vs34, vs34, 3
+; P8-NEXT:    xxsldwi vs0, vs34, vs34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; P8-NEXT:    li r3, 48
 ; P8-NEXT:    std r27, 72(r1) # 8-byte Folded Spill
 ; P8-NEXT:    std r28, 80(r1) # 8-byte Folded Spill
 ; P8-NEXT:    std r29, 88(r1) # 8-byte Folded Spill
 ; P8-NEXT:    std r30, 96(r1) # 8-byte Folded Spill
 ; P8-NEXT:    mr r30, r5
-; P8-NEXT:    xscvspdpn f1, vs0
+; P8-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; P8-NEXT:    stxvd2x vs63, r1, r3 # 16-byte Folded Spill
-; P8-NEXT:    vmr v31, v2
+; P8-NEXT:    # Vec Uses: V31(VSR63)
+; P8-NEXT:    vmr v31, v2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; P8-NEXT:    bl __gnu_f2h_ieee
 ; P8-NEXT:    nop
-; P8-NEXT:    xxswapd vs0, vs63
+; P8-NEXT:    xxswapd vs0, vs63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
 ; P8-NEXT:    mr r29, r3
-; P8-NEXT:    xscvspdpn f1, vs0
+; P8-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; P8-NEXT:    bl __gnu_f2h_ieee
 ; P8-NEXT:    nop
-; P8-NEXT:    xxsldwi vs0, vs63, vs63, 1
+; P8-NEXT:    xxsldwi vs0, vs63, vs63, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
 ; P8-NEXT:    mr r28, r3
-; P8-NEXT:    xscvspdpn f1, vs0
+; P8-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; P8-NEXT:    bl __gnu_f2h_ieee
 ; P8-NEXT:    nop
-; P8-NEXT:    xscvspdpn f1, vs63
+; P8-NEXT:    xscvspdpn f1, vs63 # Vec Defs: F1(VSR1) Vec Uses: V31(VSR63)
 ; P8-NEXT:    mr r27, r3
 ; P8-NEXT:    bl __gnu_f2h_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    sth r3, 6(r30)
 ; P8-NEXT:    li r3, 48
 ; P8-NEXT:    sth r27, 4(r30)
 ; P8-NEXT:    ld r27, 72(r1) # 8-byte Folded Reload
 ; P8-NEXT:    sth r28, 2(r30)
 ; P8-NEXT:    sth r29, 0(r30)
 ; P8-NEXT:    ld r30, 96(r1) # 8-byte Folded Reload
 ; P8-NEXT:    ld r29, 88(r1) # 8-byte Folded Reload
 ; P8-NEXT:    lxvd2x vs63, r1, r3 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V31(VSR63)
 ; P8-NEXT:    ld r28, 80(r1) # 8-byte Folded Reload
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: test_trunc32_vec4:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxsldwi vs0, vs34, vs34, 3
-; CHECK-NEXT:    xxsldwi vs1, vs34, vs34, 1
-; CHECK-NEXT:    xscvspdpn f0, vs0
-; CHECK-NEXT:    xscvspdpn f1, vs1
-; CHECK-NEXT:    xscvdphp f0, f0
-; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    xxswapd vs0, vs34
-; CHECK-NEXT:    xscvspdpn f0, vs0
-; CHECK-NEXT:    xscvdphp f0, f0
-; CHECK-NEXT:    xscvdphp f1, f1
-; CHECK-NEXT:    mffprwz r4, f1
-; CHECK-NEXT:    xscvspdpn f1, vs34
-; CHECK-NEXT:    xscvdphp f1, f1
+; CHECK-NEXT:    xxsldwi vs0, vs34, vs34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    xxsldwi vs1, vs34, vs34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; CHECK-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; CHECK-NEXT:    xscvdphp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    mffprwz r3, f0 # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    xxswapd vs0, vs34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; CHECK-NEXT:    xscvdphp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    xscvdphp f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    mffprwz r4, f1 # Vec Uses: F1(VSR1)
+; CHECK-NEXT:    xscvspdpn f1, vs34 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; CHECK-NEXT:    xscvdphp f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    sth r4, 4(r5)
-; CHECK-NEXT:    mffprwz r4, f0
+; CHECK-NEXT:    mffprwz r4, f0 # Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    sth r3, 0(r5)
 ; CHECK-NEXT:    sth r4, 2(r5)
-; CHECK-NEXT:    mffprwz r6, f1
+; CHECK-NEXT:    mffprwz r6, f1 # Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    sth r6, 6(r5)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: test_trunc32_vec4:
 ; SOFT:       # %bb.0:
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r26, -48(r1) # 8-byte Folded Spill
 ; SOFT-NEXT:    std r27, -40(r1) # 8-byte Folded Spill

 }
 define void @test_trunc64_vec4(<4 x double> %a, <4 x half>* %p) #0 {
 ; P8-LABEL: test_trunc64_vec4:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -128(r1)
 ; P8-NEXT:    li r3, 48
-; P8-NEXT:    xxswapd vs1, vs34
+; P8-NEXT:    xxswapd vs1, vs34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; P8-NEXT:    std r27, 88(r1) # 8-byte Folded Spill
 ; P8-NEXT:    std r28, 96(r1) # 8-byte Folded Spill
 ; P8-NEXT:    std r29, 104(r1) # 8-byte Folded Spill
 ; P8-NEXT:    std r30, 112(r1) # 8-byte Folded Spill
 ; P8-NEXT:    mr r30, r7
 ; P8-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; P8-NEXT:    stxvd2x vs62, r1, r3 # 16-byte Folded Spill
+; P8-NEXT:    # Vec Uses: V30(VSR62)
 ; P8-NEXT:    li r3, 64
-; P8-NEXT:    vmr v30, v2
+; P8-NEXT:    vmr v30, v2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; P8-NEXT:    stxvd2x vs63, r1, r3 # 16-byte Folded Spill
-; P8-NEXT:    vmr v31, v3
+; P8-NEXT:    # Vec Uses: V31(VSR63)
+; P8-NEXT:    vmr v31, v3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
 ; P8-NEXT:    bl __truncdfhf2
 ; P8-NEXT:    nop
-; P8-NEXT:    xxswapd vs1, vs63
+; P8-NEXT:    xxswapd vs1, vs63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; P8-NEXT:    mr r29, r3
 ; P8-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; P8-NEXT:    bl __truncdfhf2
 ; P8-NEXT:    nop
-; P8-NEXT:    xxlor f1, vs62, vs62
+; P8-NEXT:    xxlor f1, vs62, vs62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; P8-NEXT:    mr r28, r3
 ; P8-NEXT:    bl __truncdfhf2
 ; P8-NEXT:    nop
-; P8-NEXT:    xxlor f1, vs63, vs63
+; P8-NEXT:    xxlor f1, vs63, vs63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; P8-NEXT:    mr r27, r3
 ; P8-NEXT:    bl __truncdfhf2
 ; P8-NEXT:    nop
 ; P8-NEXT:    sth r3, 6(r30)
 ; P8-NEXT:    li r3, 64
 ; P8-NEXT:    sth r27, 2(r30)
 ; P8-NEXT:    ld r27, 88(r1) # 8-byte Folded Reload
 ; P8-NEXT:    sth r28, 4(r30)
 ; P8-NEXT:    sth r29, 0(r30)
 ; P8-NEXT:    ld r30, 112(r1) # 8-byte Folded Reload
 ; P8-NEXT:    ld r29, 104(r1) # 8-byte Folded Reload
 ; P8-NEXT:    lxvd2x vs63, r1, r3 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V31(VSR63)
 ; P8-NEXT:    li r3, 48
 ; P8-NEXT:    ld r28, 96(r1) # 8-byte Folded Reload
 ; P8-NEXT:    lxvd2x vs62, r1, r3 # 16-byte Folded Reload
+; P8-NEXT:    # Vec Defs: V30(VSR62)
 ; P8-NEXT:    addi r1, r1, 128
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: test_trunc64_vec4:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxswapd vs0, vs34
-; CHECK-NEXT:    xscvdphp f0, f0
-; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    xxswapd vs0, vs35
-; CHECK-NEXT:    xscvdphp f0, f0
-; CHECK-NEXT:    xscvdphp f1, vs34
-; CHECK-NEXT:    mffprwz r4, f1
-; CHECK-NEXT:    xscvdphp f1, vs35
+; CHECK-NEXT:    xxswapd vs0, vs34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    xscvdphp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    mffprwz r3, f0 # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    xxswapd vs0, vs35 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    xscvdphp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    xscvdphp f1, vs34 # Vec Defs: F1(VSR1) Vec Uses: VF2(VSR2)
+; CHECK-NEXT:    mffprwz r4, f1 # Vec Uses: F1(VSR1)
+; CHECK-NEXT:    xscvdphp f1, vs35 # Vec Defs: F1(VSR1) Vec Uses: VF3(VSR3)
 ; CHECK-NEXT:    sth r3, 0(r7)
 ; CHECK-NEXT:    sth r4, 2(r7)
-; CHECK-NEXT:    mffprwz r4, f0
+; CHECK-NEXT:    mffprwz r4, f0 # Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    sth r4, 4(r7)
-; CHECK-NEXT:    mffprwz r5, f1
+; CHECK-NEXT:    mffprwz r5, f1 # Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    sth r5, 6(r7)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: test_trunc64_vec4:
 ; SOFT:       # %bb.0:
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r26, -48(r1) # 8-byte Folded Spill
 ; SOFT-NEXT:    std r27, -40(r1) # 8-byte Folded Spill
; SOFT-NEXT:    blr
   ret void
 }
 define float @test_sitofp_fadd_i32(i32 %a, half* %b) #0 {
 ; P8-LABEL: test_sitofp_fadd_i32:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r30, -24(r1) # 8-byte Folded Spill
 ; P8-NEXT:    stfd f31, -8(r1) # 8-byte Folded Spill
+; P8-NEXT:    # Vec Uses: F31(VSR31)
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -64(r1)
 ; P8-NEXT:    mr r30, r3
 ; P8-NEXT:    lhz r3, 0(r4)
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
-; P8-NEXT:    mtfprwa f0, r30
-; P8-NEXT:    fmr f31, f1
-; P8-NEXT:    xscvsxdsp f1, f0
+; P8-NEXT:    mtfprwa f0, r30 # Vec Defs: F0(VSR0)
+; P8-NEXT:    fmr f31, f1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; P8-NEXT:    xscvsxdsp f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; P8-NEXT:    bl __gnu_f2h_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    clrldi r3, r3, 48
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
-; P8-NEXT:    xsaddsp f1, f31, f1
+; P8-NEXT:    xsaddsp f1, f31, f1 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)F1(VSR1)
 ; P8-NEXT:    addi r1, r1, 64
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    lfd f31, -8(r1) # 8-byte Folded Reload
+; P8-NEXT:    # Vec Defs: F31(VSR31)
 ; P8-NEXT:    ld r30, -24(r1) # 8-byte Folded Reload
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: test_sitofp_fadd_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    mtfprwa f1, r3
+; CHECK-NEXT:    mtfprwa f1, r3 # Vec Defs: F1(VSR1)
 ; CHECK-NEXT:    lhz r4, 0(r4)
-; CHECK-NEXT:    xscvsxdsp f1, f1
-; CHECK-NEXT:    mtfprwz f0, r4
-; CHECK-NEXT:    xscvhpdp f0, f0
-; CHECK-NEXT:    xscvdphp f1, f1
-; CHECK-NEXT:    mffprwz r3, f1
+; CHECK-NEXT:    xscvsxdsp f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    mtfprwz f0, r4 # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    xscvhpdp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    xscvdphp f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    mffprwz r3, f1 # Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    clrlwi r3, r3, 16
-; CHECK-NEXT:    mtfprwz f1, r3
-; CHECK-NEXT:    xscvhpdp f1, f1
-; CHECK-NEXT:    xsaddsp f1, f0, f1
+; CHECK-NEXT:    mtfprwz f1, r3 # Vec Defs: F1(VSR1)
+; CHECK-NEXT:    xscvhpdp f1, f1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: test_sitofp_fadd_i32:
 ; SOFT:       # %bb.0:
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; SOFT-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; SOFT-NEXT:    std r0, 16(r1)

 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -32(r1)
 ; P8-NEXT:    bl __gnu_f2h_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    clrldi r3, r3, 48
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
-; P8-NEXT:    xxlxor f0, f0, f0
-; P8-NEXT:    fcmpu cr0, f1, f0
+; P8-NEXT:    xxlxor f0, f0, f0 # Vec Defs: F0(VSR0)
+; P8-NEXT:    fcmpu cr0, f1, f0 # Vec Uses: F1(VSR1)F0(VSR0)
 ; P8-NEXT:    beq cr0, .LBB20_2
 ; P8-NEXT:  # %bb.1:
 ; P8-NEXT:    addis r3, r2, .LCPI20_0@toc@ha
-; P8-NEXT:    lfs f0, .LCPI20_0@toc@l(r3)
+; P8-NEXT:    lfs f0, .LCPI20_0@toc@l(r3) # Vec Defs: F0(VSR0)
 ; P8-NEXT:  .LBB20_2:
-; P8-NEXT:    fmr f1, f0
+; P8-NEXT:    fmr f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; P8-NEXT:    addi r1, r1, 32
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: PR40273:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xscvdphp f0, f1
-; CHECK-NEXT:    xxlxor f1, f1, f1
-; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    xscvdphp f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; CHECK-NEXT:    xxlxor f1, f1, f1 # Vec Defs: F1(VSR1)
+; CHECK-NEXT:    mffprwz r3, f0 # Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    clrlwi r3, r3, 16
-; CHECK-NEXT:    mtfprwz f0, r3
-; CHECK-NEXT:    xscvhpdp f0, f0
-; CHECK-NEXT:    fcmpu cr0, f0, f1
+; CHECK-NEXT:    mtfprwz f0, r3 # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    xscvhpdp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    fcmpu cr0, f0, f1 # Vec Uses: F0(VSR0)F1(VSR1)
 ; CHECK-NEXT:    beqlr cr0
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    addis r3, r2, .LCPI20_0@toc@ha
-; CHECK-NEXT:    lfs f1, .LCPI20_0@toc@l(r3)
+; CHECK-NEXT:    lfs f1, .LCPI20_0@toc@l(r3) # Vec Defs: F1(VSR1)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: PR40273:
 ; SOFT:       # %bb.0:
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r0, 16(r1)
 ; SOFT-NEXT:    stdu r1, -32(r1)
 ; SOFT-NEXT:    clrldi r3, r3, 48

llvm/test/CodeGen/PowerPC/inline-asm-vsx-clobbers.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -verify-machineinstrs -ppc-vsr-nums-as-vr \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s
 
 define dso_local void @clobberVR(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
 ; CHECK-LABEL: clobberVR:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    stxv v22, -160(r1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V22(VSR54)
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    lxv v22, -160(r1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V22(VSR54)
 ; CHECK-NEXT:    blr
 entry:
   tail call void asm sideeffect "nop", "~{vs54}"()
   ret void
 }
 
 define dso_local void @clobberFPR(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
 ; CHECK-LABEL: clobberFPR:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    stfd f14, -144(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F14(VSR14)
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    lfd f14, -144(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F14(VSR14)
 ; CHECK-NEXT:    blr
 entry:
   tail call void asm sideeffect "nop", "~{vs14}"()
   ret void
 }

llvm/test/CodeGen/PowerPC/larger-than-red-zone.ll

 ; CHECK-NEXT:    std r25, 120(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r26, 128(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r27, 136(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r28, 144(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r29, 152(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r30, 160(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r31, 168(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stfd f14, 176(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F14(VSR14)
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    add r3, r3, r4
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    bl callee
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    lfd f14, 176(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F14(VSR14)
 ; CHECK-NEXT:    ld r31, 168(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r30, 160(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r29, 152(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r28, 144(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r27, 136(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r26, 128(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r25, 120(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r24, 112(r1) # 8-byte Folded Reload

llvm/test/CodeGen/PowerPC/mma-acc-spill.ll

 ; CHECK-NEXT:    .cfi_offset r30, -16
 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -176(r1)
 ; CHECK-NEXT:    # kill: def $v5 killed $v5 killed $vsrp18 def $vsrp18
 ; CHECK-NEXT:    # kill: def $v4 killed $v4 killed $vsrp18 def $vsrp18
 ; CHECK-NEXT:    # kill: def $v3 killed $v3 killed $vsrp17 def $vsrp17
 ; CHECK-NEXT:    # kill: def $v2 killed $v2 killed $vsrp17 def $vsrp17
-; CHECK-NEXT:    xxlor vs0, v2, v2
-; CHECK-NEXT:    xxlor vs1, v3, v3
+; CHECK-NEXT:    xxlor vs0, v2, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    xxlor vs1, v3, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-NEXT:    stxvp vsp34, 128(r1) # 32-byte Folded Spill
-; CHECK-NEXT:    xxlor vs2, v4, v4
-; CHECK-NEXT:    xxlor vs3, v5, v5
+; CHECK-NEXT:    # Vec Uses: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    xxlor vs2, v4, v4 # Vec Defs: VSL2(VSR2) Vec Uses: V4(VSR36)V4(VSR36)
+; CHECK-NEXT:    xxlor vs3, v5, v5 # Vec Defs: VSL3(VSR3) Vec Uses: V5(VSR37)V5(VSR37)
 ; CHECK-NEXT:    ld r30, 272(r1)
 ; CHECK-NEXT:    stxvp vsp36, 96(r1) # 32-byte Folded Spill
-; CHECK-NEXT:    xxmtacc acc0
-; CHECK-NEXT:    xvf16ger2pp acc0, v2, v4
-; CHECK-NEXT:    xxmfacc acc0
-; CHECK-NEXT:    stxvp vsp0, 64(r1)
-; CHECK-NEXT:    stxvp vsp2, 32(r1)
+; CHECK-NEXT:    # Vec Uses: VSRp18(VSR36,VSR37)
+; CHECK-NEXT:    xxmtacc acc0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)
+; CHECK-NEXT:    xvf16ger2pp acc0, v2, v4 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)V2(VSR34)V4(VSR36)
+; CHECK-NEXT:    xxmfacc acc0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)
+; CHECK-NEXT:    stxvp vsp0, 64(r1) # Vec Uses: VSRp0(VSR0,VSR1)
+; CHECK-NEXT:    stxvp vsp2, 32(r1) # Vec Uses: VSRp1(VSR2,VSR3)
 ; CHECK-NEXT:    bl foo@notoc
-; CHECK-NEXT:    lxvp vsp0, 64(r1)
-; CHECK-NEXT:    lxvp vsp2, 32(r1)
-; CHECK-NEXT:    xxmtacc acc0
+; CHECK-NEXT:    lxvp vsp0, 64(r1) # Vec Defs: VSRp0(VSR0,VSR1)
+; CHECK-NEXT:    lxvp vsp2, 32(r1) # Vec Defs: VSRp1(VSR2,VSR3)
+; CHECK-NEXT:    xxmtacc acc0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)
 ; CHECK-NEXT:    lxvp vsp34, 128(r1) # 32-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    lxvp vsp36, 96(r1) # 32-byte Folded Reload
-; CHECK-NEXT:    xvf16ger2pp acc0, v2, v4
-; CHECK-NEXT:    xxmfacc acc0
-; CHECK-NEXT:    stxv vs0, 48(r30)
-; CHECK-NEXT:    stxv vs1, 32(r30)
-; CHECK-NEXT:    stxv vs2, 16(r30)
-; CHECK-NEXT:    stxv vs3, 0(r30)
+; CHECK-NEXT:    # Vec Defs: VSRp18(VSR36,VSR37)
+; CHECK-NEXT:    xvf16ger2pp acc0, v2, v4 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)V2(VSR34)V4(VSR36)
+; CHECK-NEXT:    xxmfacc acc0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)
+; CHECK-NEXT:    stxv vs0, 48(r30) # Vec Uses: VSL0(VSR0)
+; CHECK-NEXT:    stxv vs1, 32(r30) # Vec Uses: VSL1(VSR1)
+; CHECK-NEXT:    stxv vs2, 16(r30) # Vec Uses: VSL2(VSR2)
+; CHECK-NEXT:    stxv vs3, 0(r30) # Vec Uses: VSL3(VSR3)
 ; CHECK-NEXT:    addi r1, r1, 176
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: intrinsics1:
 ; CHECK-BE:       # %bb.0:
 ; CHECK-BE-NEXT:    mflr r0
 ; CHECK-BE-NEXT:    std r0, 16(r1)
 ; CHECK-BE-NEXT:    stdu r1, -256(r1)
 ; CHECK-BE-NEXT:    .cfi_def_cfa_offset 256
 ; CHECK-BE-NEXT:    .cfi_offset lr, 16
 ; CHECK-BE-NEXT:    .cfi_offset r30, -16
 ; CHECK-BE-NEXT:    std r30, 240(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    # kill: def $v5 killed $v5 killed $vsrp18 def $vsrp18
 ; CHECK-BE-NEXT:    # kill: def $v4 killed $v4 killed $vsrp18 def $vsrp18
 ; CHECK-BE-NEXT:    # kill: def $v3 killed $v3 killed $vsrp17 def $vsrp17
 ; CHECK-BE-NEXT:    # kill: def $v2 killed $v2 killed $vsrp17 def $vsrp17
-; CHECK-BE-NEXT:    xxlor vs0, v2, v2
-; CHECK-BE-NEXT:    xxlor vs1, v3, v3
+; CHECK-BE-NEXT:    xxlor vs0, v2, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-NEXT:    xxlor vs1, v3, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-NEXT:    stxvp vsp34, 208(r1) # 32-byte Folded Spill
-; CHECK-BE-NEXT:    xxlor vs2, v4, v4
-; CHECK-BE-NEXT:    xxlor vs3, v5, v5
+; CHECK-BE-NEXT:    # Vec Uses: VSRp17(VSR34,VSR35)
+; CHECK-BE-NEXT:    xxlor vs2, v4, v4 # Vec Defs: VSL2(VSR2) Vec Uses: V4(VSR36)V4(VSR36)
+; CHECK-BE-NEXT:    xxlor vs3, v5, v5 # Vec Defs: VSL3(VSR3) Vec Uses: V5(VSR37)V5(VSR37)
 ; CHECK-BE-NEXT:    stxvp vsp36, 176(r1) # 32-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: VSRp18(VSR36,VSR37)
 ; CHECK-BE-NEXT:    ld r30, 368(r1)
-; CHECK-BE-NEXT:    xxmtacc acc0
-; CHECK-BE-NEXT:    xvf16ger2pp acc0, v2, v4
-; CHECK-BE-NEXT:    xxmfacc acc0
-; CHECK-BE-NEXT:    stxvp vsp0, 112(r1)
-; CHECK-BE-NEXT:    stxvp vsp2, 144(r1)
+; CHECK-BE-NEXT:    xxmtacc acc0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)
+; CHECK-BE-NEXT:    xvf16ger2pp acc0, v2, v4 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)V2(VSR34)V4(VSR36)
+; CHECK-BE-NEXT:    xxmfacc acc0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)
+; CHECK-BE-NEXT:    stxvp vsp0, 112(r1) # Vec Uses: VSRp0(VSR0,VSR1)
+; CHECK-BE-NEXT:    stxvp vsp2, 144(r1) # Vec Uses: VSRp1(VSR2,VSR3)
 ; CHECK-BE-NEXT:    bl foo
 ; CHECK-BE-NEXT:    nop
-; CHECK-BE-NEXT:    lxvp vsp0, 112(r1)
-; CHECK-BE-NEXT:    lxvp vsp2, 144(r1)
-; CHECK-BE-NEXT:    xxmtacc acc0
+; CHECK-BE-NEXT:    lxvp vsp0, 112(r1) # Vec Defs: VSRp0(VSR0,VSR1)
+; CHECK-BE-NEXT:    lxvp vsp2, 144(r1) # Vec Defs: VSRp1(VSR2,VSR3)
+; CHECK-BE-NEXT:    xxmtacc acc0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)
 ; CHECK-BE-NEXT:    lxvp vsp34, 208(r1) # 32-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    lxvp vsp36, 176(r1) # 32-byte Folded Reload
-; CHECK-BE-NEXT:    xvf16ger2pp acc0, v2, v4
-; CHECK-BE-NEXT:    xxmfacc acc0
-; CHECK-BE-NEXT:    stxv vs1, 16(r30)
-; CHECK-BE-NEXT:    stxv vs0, 0(r30)
-; CHECK-BE-NEXT:    stxv vs3, 48(r30)
-; CHECK-BE-NEXT:    stxv vs2, 32(r30)
+; CHECK-BE-NEXT:    # Vec Defs: VSRp18(VSR36,VSR37)
+; CHECK-BE-NEXT:    xvf16ger2pp acc0, v2, v4 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)V2(VSR34)V4(VSR36)
+; CHECK-BE-NEXT:    xxmfacc acc0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)
+; CHECK-BE-NEXT:    stxv vs1, 16(r30) # Vec Uses: VSL1(VSR1)
+; CHECK-BE-NEXT:    stxv vs0, 0(r30) # Vec Uses: VSL0(VSR0)
+; CHECK-BE-NEXT:    stxv vs3, 48(r30) # Vec Uses: VSL3(VSR3)
+; CHECK-BE-NEXT:    stxv vs2, 32(r30) # Vec Uses: VSL2(VSR2)
 ; CHECK-BE-NEXT:    ld r30, 240(r1) # 8-byte Folded Reload
 ; CHECK-BE-NEXT:    addi r1, r1, 256
 ; CHECK-BE-NEXT:    ld r0, 16(r1)
 ; CHECK-BE-NEXT:    mtlr r0
 ; CHECK-BE-NEXT:    blr
   %1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4)
   %2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc3)
   tail call void @foo()
   %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
   %4 = bitcast i8* %ptr to <512 x i1>*
   store <512 x i1> %3, <512 x i1>* %4, align 64
   ret void
 }

llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll

 ; CHECK-NEXT:    std 25, 488(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 26, 496(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 27, 504(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 28, 512(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 29, 520(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 30, 528(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 31, 536(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stfd 26, 544(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F26(VSR26)
 ; CHECK-NEXT:    stfd 27, 552(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F27(VSR27)
 ; CHECK-NEXT:    stfd 28, 560(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F28(VSR28)
 ; CHECK-NEXT:    stfd 29, 568(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F29(VSR29)
 ; CHECK-NEXT:    stfd 30, 576(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F30(VSR30)
 ; CHECK-NEXT:    stfd 31, 584(1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F31(VSR31)
 ; CHECK-NEXT:    stxv 52, 208(1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V20(VSR52)
 ; CHECK-NEXT:    stxv 53, 224(1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V21(VSR53)
 ; CHECK-NEXT:    stxv 54, 240(1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V22(VSR54)
 ; CHECK-NEXT:    stxv 55, 256(1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V23(VSR55)
 ; CHECK-NEXT:    stxv 56, 272(1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V24(VSR56)
 ; CHECK-NEXT:    stxv 57, 288(1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V25(VSR57)
 ; CHECK-NEXT:    stxv 58, 304(1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V26(VSR58)
 ; CHECK-NEXT:    stxv 59, 320(1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V27(VSR59)
 ; CHECK-NEXT:    stxv 60, 336(1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V28(VSR60)
 ; CHECK-NEXT:    stxv 61, 352(1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V29(VSR61)
 ; CHECK-NEXT:    stxv 62, 368(1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V30(VSR62)
 ; CHECK-NEXT:    stxv 63, 384(1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V31(VSR63)
 ; CHECK-NEXT:    blt 0, .LBB0_7
 ; CHECK-NEXT:  # %bb.1: # %_loop_1_do_.lr.ph
 ; CHECK-NEXT:    lwz 3, 0(3)
 ; CHECK-NEXT:    cmpwi 3, 1
 ; CHECK-NEXT:    blt 0, .LBB0_7
 ; CHECK-NEXT:  # %bb.2: # %_loop_1_do_.preheader
 ; CHECK-NEXT:    mr 21, 5
 ; CHECK-NEXT:    ld 5, 848(1)
 ; CHECK-NEXT:    lwa 0, 0(7)
 ; CHECK-NEXT:    addi 3, 3, 1
 ; CHECK-NEXT:    mr 14, 7
 ; CHECK-NEXT:    mr 22, 6
 ; CHECK-NEXT:    mr 11, 10
 ; CHECK-NEXT:    ld 18, 736(1)
 ; CHECK-NEXT:    ld 17, 728(1)
 ; CHECK-NEXT:    std 8, 32(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 9, 40(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    cmpldi 3, 9
 ; CHECK-NEXT:    ld 19, 744(1)
 ; CHECK-NEXT:    ld 20, 752(1)
 ; CHECK-NEXT:    std 5, 200(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    ld 5, 840(1)
 ; CHECK-NEXT:    std 17, 80(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 18, 88(1) # 8-byte Folded Spill
-; CHECK-NEXT:    lxv 36, 0(18)
+; CHECK-NEXT:    lxv 36, 0(18) # Vec Defs: V4(VSR36)
 ; CHECK-NEXT:    std 19, 96(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 20, 104(1) # 8-byte Folded Spill
-; CHECK-NEXT:    lxv 13, 0(19)
-; CHECK-NEXT:    lxv 12, 0(20)
+; CHECK-NEXT:    lxv 13, 0(19) # Vec Defs: VSL13(VSR13)
+; CHECK-NEXT:    lxv 12, 0(20) # Vec Defs: VSL12(VSR12)
 ; CHECK-NEXT:    ld 30, 832(1)
 ; CHECK-NEXT:    ld 2, 824(1)
 ; CHECK-NEXT:    ld 12, 816(1)
 ; CHECK-NEXT:    ld 29, 808(1)
 ; CHECK-NEXT:    std 2, 176(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 30, 184(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 29, 160(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 12, 168(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 5, 192(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    li 5, 9
 ; CHECK-NEXT:    ld 28, 800(1)
 ; CHECK-NEXT:    ld 27, 792(1)
 ; CHECK-NEXT:    ld 26, 784(1)
 ; CHECK-NEXT:    ld 25, 776(1)
 ; CHECK-NEXT:    ld 24, 768(1)
 ; CHECK-NEXT:    ld 23, 760(1)
 ; CHECK-NEXT:    ld 16, 720(1)
 ; CHECK-NEXT:    ld 15, 712(1)
 ; CHECK-NEXT:    ld 6, 704(1)
 ; CHECK-NEXT:    ld 7, 696(1)
 ; CHECK-NEXT:    ld 10, 688(1)
-; CHECK-NEXT:    lxv 43, 0(8)
+; CHECK-NEXT:    lxv 43, 0(8) # Vec Defs: V11(VSR43)
 ; CHECK-NEXT:    std 11, 48(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 6, 56(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 27, 144(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 28, 152(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    mr 8, 7
 ; CHECK-NEXT:    std 25, 128(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 26, 136(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 15, 64(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 16, 72(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 23, 112(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 24, 120(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    iselgt 3, 3, 5
 ; CHECK-NEXT:    sldi 5, 0, 3
 ; CHECK-NEXT:    add 5, 5, 21
-; CHECK-NEXT:    lxv 42, 0(9)
-; CHECK-NEXT:    lxv 41, 0(11)
-; CHECK-NEXT:    lxv 40, 0(10)
-; CHECK-NEXT:    lxv 39, 0(7)
+; CHECK-NEXT:    lxv 42, 0(9) # Vec Defs: V10(VSR42)
+; CHECK-NEXT:    lxv 41, 0(11) # Vec Defs: V9(VSR41)
+; CHECK-NEXT:    lxv 40, 0(10) # Vec Defs: V8(VSR40)
+; CHECK-NEXT:    lxv 39, 0(7) # Vec Defs: V7(VSR39)
 ; CHECK-NEXT:    mulli 11, 0, 48
 ; CHECK-NEXT:    addi 14, 5, 32
 ; CHECK-NEXT:    sldi 5, 0, 4
 ; CHECK-NEXT:    addi 3, 3, -2
-; CHECK-NEXT:    lxv 38, 0(6)
-; CHECK-NEXT:    lxv 33, 0(15)
-; CHECK-NEXT:    lxv 32, 0(16)
-; CHECK-NEXT:    lxv 37, 0(17)
+; CHECK-NEXT:    lxv 38, 0(6) # Vec Defs: V6(VSR38)
+; CHECK-NEXT:    lxv 33, 0(15) # Vec Defs: V1(VSR33)
+; CHECK-NEXT:    lxv 32, 0(16) # Vec Defs: V0(VSR32)
+; CHECK-NEXT:    lxv 37, 0(17) # Vec Defs: V5(VSR37)
 ; CHECK-NEXT:    add 5, 5, 21
-; CHECK-NEXT:    lxv 11, 0(23)
-; CHECK-NEXT:    lxv 10, 0(24)
-; CHECK-NEXT:    lxv 8, 0(25)
-; CHECK-NEXT:    lxv 6, 0(26)
+; CHECK-NEXT:    lxv 11, 0(23) # Vec Defs: VSL11(VSR11)
+; CHECK-NEXT:    lxv 10, 0(24) # Vec Defs: VSL10(VSR10)
+; CHECK-NEXT:    lxv 8, 0(25) # Vec Defs: VSL8(VSR8)
+; CHECK-NEXT:    lxv 6, 0(26) # Vec Defs: VSL6(VSR6)
 ; CHECK-NEXT:    rldicl 3, 3, 61, 3
 ; CHECK-NEXT:    li 26, 0
 ; CHECK-NEXT:    mr 25, 21
 ; CHECK-NEXT:    addi 31, 5, 32
 ; CHECK-NEXT:    mulli 5, 0, 40
-; CHECK-NEXT:    lxv 5, 0(27)
-; CHECK-NEXT:    lxv 3, 0(28)
-; CHECK-NEXT:    lxv 1, 0(29)
-; CHECK-NEXT:    lxv 0, 0(12)
+; CHECK-NEXT:    lxv 5, 0(27) # Vec Defs: VSL5(VSR5)
+; CHECK-NEXT:    lxv 3, 0(28) # Vec Defs: VSL3(VSR3)
+; CHECK-NEXT:    lxv 1, 0(29) # Vec Defs: VSL1(VSR1)
+; CHECK-NEXT:    lxv 0, 0(12) # Vec Defs: VSL0(VSR0)
 ; CHECK-NEXT:    mulli 28, 0, 6
 ; CHECK-NEXT:    addi 3, 3, 1
 ; CHECK-NEXT:    li 27, 1
 ; CHECK-NEXT:    add 18, 21, 5
 ; CHECK-NEXT:    sldi 5, 0, 5
-; CHECK-NEXT:    lxv 2, 0(2)
-; CHECK-NEXT:    lxv 4, 0(30)
+; CHECK-NEXT:    lxv 2, 0(2) # Vec Defs: VSL2(VSR2)
+; CHECK-NEXT:    lxv 4, 0(30) # Vec Defs: VSL4(VSR4)
 ; CHECK-NEXT:    sldi 2, 0, 1
 ; CHECK-NEXT:    add 19, 21, 5
 ; CHECK-NEXT:    mulli 5, 0, 24
 ; CHECK-NEXT:    add 20, 21, 5
 ; CHECK-NEXT:    ld 5, 192(1) # 8-byte Folded Reload
-; CHECK-NEXT:    lxv 9, 0(5)
+; CHECK-NEXT:    lxv 9, 0(5) # Vec Defs: VSL9(VSR9)
 ; CHECK-NEXT:    ld 5, 200(1) # 8-byte Folded Reload
-; CHECK-NEXT:    lxv 7, 0(5)
+; CHECK-NEXT:    lxv 7, 0(5) # Vec Defs: VSL7(VSR7)
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_3: # %_loop_2_do_.lr.ph
 ; CHECK-NEXT:    # =>This Loop Header: Depth=1
 ; CHECK-NEXT:    # Child Loop BB0_4 Depth 2
 ; CHECK-NEXT:    maddld 5, 28, 26, 2
 ; CHECK-NEXT:    mr 6, 22
 ; CHECK-NEXT:    mr 29, 20
 ; CHECK-NEXT:    mr 30, 19
 ; CHECK-NEXT:    mr 12, 18
 ; CHECK-NEXT:    mtctr 3
 ; CHECK-NEXT:    sldi 5, 5, 3
 ; CHECK-NEXT:    add 24, 21, 5
 ; CHECK-NEXT:    maddld 5, 28, 26, 0
 ; CHECK-NEXT:    sldi 5, 5, 3
 ; CHECK-NEXT:    add 23, 21, 5
 ; CHECK-NEXT:    mr 5, 25
 ; CHECK-NEXT:    .p2align 5
 ; CHECK-NEXT:  .LBB0_4: # %_loop_2_do_
 ; CHECK-NEXT:    # Parent Loop BB0_3 Depth=1
 ; CHECK-NEXT:    # => This Inner Loop Header: Depth=2
-; CHECK-NEXT:    lxvp 34, 0(6)
-; CHECK-NEXT:    lxvp 44, 0(5)
-; CHECK-NEXT:    xvmaddadp 43, 45, 35
-; CHECK-NEXT:    lxvp 46, 0(23)
-; CHECK-NEXT:    xvmaddadp 42, 47, 35
-; CHECK-NEXT:    lxvp 48, 0(24)
-; CHECK-NEXT:    lxvp 50, 0(29)
-; CHECK-NEXT:    lxvp 62, 0(30)
-; CHECK-NEXT:    lxvp 60, 0(12)
-; CHECK-NEXT:    lxvp 58, 32(6)
-; CHECK-NEXT:    lxvp 56, 32(5)
-; CHECK-NEXT:    lxvp 54, 32(23)
-; CHECK-NEXT:    lxvp 52, 32(24)
-; CHECK-NEXT:    lxvp 30, 32(29)
-; CHECK-NEXT:    lxvp 28, 32(30)
-; CHECK-NEXT:    lxvp 26, 32(12)
-; CHECK-NEXT:    xvmaddadp 41, 49, 35
-; CHECK-NEXT:    xvmaddadp 40, 51, 35
-; CHECK-NEXT:    xvmaddadp 39, 63, 35
-; CHECK-NEXT:    xvmaddadp 38, 61, 35
-; CHECK-NEXT:    xvmaddadp 33, 44, 34
-; CHECK-NEXT:    xvmaddadp 32, 46, 34
-; CHECK-NEXT:    xvmaddadp 37, 48, 34
-; CHECK-NEXT:    xvmaddadp 36, 50, 34
-; CHECK-NEXT:    xvmaddadp 13, 62, 34
-; CHECK-NEXT:    xvmaddadp 12, 60, 34
-; CHECK-NEXT:    xvmaddadp 11, 57, 59
-; CHECK-NEXT:    xvmaddadp 10, 55, 59
-; CHECK-NEXT:    xvmaddadp 8, 53, 59
-; CHECK-NEXT:    xvmaddadp 6, 31, 59
-; CHECK-NEXT:    xvmaddadp 5, 29, 59
-; CHECK-NEXT:    xvmaddadp 3, 27, 59
-; CHECK-NEXT:    xvmaddadp 1, 56, 58
-; CHECK-NEXT:    xvmaddadp 0, 54, 58
-; CHECK-NEXT:    xvmaddadp 2, 52, 58
-; CHECK-NEXT:    xvmaddadp 4, 30, 58
-; CHECK-NEXT:    xvmaddadp 9, 28, 58
-; CHECK-NEXT:    xvmaddadp 7, 26, 58
+; CHECK-NEXT:    lxvp 34, 0(6) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    lxvp 44, 0(5) # Vec Defs: VSRp22(VSR44,VSR45)
+; CHECK-NEXT:    xvmaddadp 43, 45, 35 # Vec Defs: V11(VSR43) Vec Uses: V11(VSR43)V13(VSR45)V3(VSR35)
+; CHECK-NEXT:    lxvp 46, 0(23) # Vec Defs: VSRp23(VSR46,VSR47)
+; CHECK-NEXT:    xvmaddadp 42, 47, 35 # Vec Defs: V10(VSR42) Vec Uses: V10(VSR42)V15(VSR47)V3(VSR35)
+; CHECK-NEXT:    lxvp 48, 0(24) # Vec Defs: VSRp24(VSR48,VSR49)
+; CHECK-NEXT:    lxvp 50, 0(29) # Vec Defs: VSRp25(VSR50,VSR51)
+; CHECK-NEXT:    lxvp 62, 0(30) # Vec Defs: VSRp31(VSR62,VSR63)
+; CHECK-NEXT:    lxvp 60, 0(12) # Vec Defs: VSRp30(VSR60,VSR61)
+; CHECK-NEXT:    lxvp 58, 32(6) # Vec Defs: VSRp29(VSR58,VSR59)
+; CHECK-NEXT:    lxvp 56, 32(5) # Vec Defs: VSRp28(VSR56,VSR57)
+; CHECK-NEXT:    lxvp 54, 32(23) # Vec Defs: VSRp27(VSR54,VSR55)
+; CHECK-NEXT:    lxvp 52, 32(24) # Vec Defs: VSRp26(VSR52,VSR53)
+; CHECK-NEXT:    lxvp 30, 32(29) # Vec Defs: VSRp15(VSR30,VSR31)
+; CHECK-NEXT:    lxvp 28, 32(30) # Vec Defs: VSRp14(VSR28,VSR29)
+; CHECK-NEXT:    lxvp 26, 32(12) # Vec Defs: VSRp13(VSR26,VSR27)
+; CHECK-NEXT:    xvmaddadp 41, 49, 35 # Vec Defs: V9(VSR41) Vec Uses: V9(VSR41)V17(VSR49)V3(VSR35)
+; CHECK-NEXT:    xvmaddadp 40, 51, 35 # Vec Defs: V8(VSR40) Vec Uses: V8(VSR40)V19(VSR51)V3(VSR35)
+; CHECK-NEXT:    xvmaddadp 39, 63, 35 # Vec Defs: V7(VSR39) Vec Uses: V7(VSR39)V31(VSR63)V3(VSR35)
+; CHECK-NEXT:    xvmaddadp 38, 61, 35 # Vec Defs: V6(VSR38) Vec Uses: V6(VSR38)V29(VSR61)V3(VSR35)
+; CHECK-NEXT:    xvmaddadp 33, 44, 34 # Vec Defs: V1(VSR33) Vec Uses: V1(VSR33)V12(VSR44)V2(VSR34)
+; CHECK-NEXT:    xvmaddadp 32, 46, 34 # Vec Defs: V0(VSR32) Vec Uses: V0(VSR32)V14(VSR46)V2(VSR34)
+; CHECK-NEXT:    xvmaddadp 37, 48, 34 # Vec Defs: V5(VSR37) Vec Uses: V5(VSR37)V16(VSR48)V2(VSR34)
+; CHECK-NEXT:    xvmaddadp 36, 50, 34 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V18(VSR50)V2(VSR34)
+; CHECK-NEXT:    xvmaddadp 13, 62, 34 # Vec Defs: VSL13(VSR13) Vec Uses: VSL13(VSR13)V30(VSR62)V2(VSR34)
+; CHECK-NEXT:    xvmaddadp 12, 60, 34 # Vec Defs: VSL12(VSR12) Vec Uses: VSL12(VSR12)V28(VSR60)V2(VSR34)
+; CHECK-NEXT:    xvmaddadp 11, 57, 59 # Vec Defs: VSL11(VSR11) Vec Uses: VSL11(VSR11)V25(VSR57)V27(VSR59)
+; CHECK-NEXT:    xvmaddadp 10, 55, 59 # Vec Defs: VSL10(VSR10) Vec Uses: VSL10(VSR10)V23(VSR55)V27(VSR59)
+; CHECK-NEXT:    xvmaddadp 8, 53, 59 # Vec Defs: VSL8(VSR8) Vec Uses: VSL8(VSR8)V21(VSR53)V27(VSR59)
+; CHECK-NEXT:    xvmaddadp 6, 31, 59 # Vec Defs: VSL6(VSR6) Vec Uses: VSL6(VSR6)VSL31(VSR31)V27(VSR59)
+; CHECK-NEXT:    xvmaddadp 5, 29, 59 # Vec Defs: VSL5(VSR5) Vec Uses: VSL5(VSR5)VSL29(VSR29)V27(VSR59)
+; CHECK-NEXT:    xvmaddadp 3, 27, 59 # Vec Defs: VSL3(VSR3) Vec Uses: VSL3(VSR3)VSL27(VSR27)V27(VSR59)
+; CHECK-NEXT:    xvmaddadp 1, 56, 58 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)V24(VSR56)V26(VSR58)
+; CHECK-NEXT:    xvmaddadp 0, 54, 58 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)V22(VSR54)V26(VSR58)
+; CHECK-NEXT:    xvmaddadp 2, 52, 58 # Vec Defs: VSL2(VSR2) Vec Uses: VSL2(VSR2)V20(VSR52)V26(VSR58)
+; CHECK-NEXT:    xvmaddadp 4, 30, 58 # Vec Defs: VSL4(VSR4) Vec Uses: VSL4(VSR4)VSL30(VSR30)V26(VSR58)
+; CHECK-NEXT:    xvmaddadp 9, 28, 58 # Vec Defs: VSL9(VSR9) Vec Uses: VSL9(VSR9)VSL28(VSR28)V26(VSR58)
+; CHECK-NEXT:    xvmaddadp 7, 26, 58 # Vec Defs: VSL7(VSR7) Vec Uses: VSL7(VSR7)VSL26(VSR26)V26(VSR58)
 ; CHECK-NEXT:    addi 6, 6, 64
 ; CHECK-NEXT:    addi 5, 5, 64
 ; CHECK-NEXT:    addi 23, 23, 64
 ; CHECK-NEXT:    addi 24, 24, 64
 ; CHECK-NEXT:    addi 29, 29, 64
 ; CHECK-NEXT:    addi 30, 30, 64
 ; CHECK-NEXT:    addi 12, 12, 64
 ; CHECK-NEXT:    bdnz .LBB0_4
 ; CHECK-NEXT:  # %bb.5: # %_loop_2_endl_
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    addi 27, 27, 6
 ; CHECK-NEXT:    add 25, 25, 11
 ; CHECK-NEXT:    add 14, 14, 11
 ; CHECK-NEXT:    add 18, 18, 11
 ; CHECK-NEXT:    add 31, 31, 11
 ; CHECK-NEXT:    add 19, 19, 11
 ; CHECK-NEXT:    add 20, 20, 11
 ; CHECK-NEXT:    addi 26, 26, 1
 ; CHECK-NEXT:    cmpld 27, 4
 ; CHECK-NEXT:    ble 0, .LBB0_3
 ; CHECK-NEXT:  # %bb.6: # %_loop_1_loopHeader_._return_bb_crit_edge.loopexit
 ; CHECK-NEXT:    ld 3, 32(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 43, 0(3)
+; CHECK-NEXT:    stxv 43, 0(3) # Vec Uses: V11(VSR43)
 ; CHECK-NEXT:    ld 3, 40(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 42, 0(3)
+; CHECK-NEXT:    stxv 42, 0(3) # Vec Uses: V10(VSR42)
 ; CHECK-NEXT:    ld 3, 48(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 41, 0(3)
+; CHECK-NEXT:    stxv 41, 0(3) # Vec Uses: V9(VSR41)
 ; CHECK-NEXT:    ld 3, 56(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 40, 0(10)
-; CHECK-NEXT:    stxv 39, 0(8)
-; CHECK-NEXT:    stxv 38, 0(3)
+; CHECK-NEXT:    stxv 40, 0(10) # Vec Uses: V8(VSR40)
+; CHECK-NEXT:    stxv 39, 0(8) # Vec Uses: V7(VSR39)
+; CHECK-NEXT:    stxv 38, 0(3) # Vec Uses: V6(VSR38)
 ; CHECK-NEXT:    ld 3, 64(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 33, 0(3)
+; CHECK-NEXT:    stxv 33, 0(3) # Vec Uses: V1(VSR33)
 ; CHECK-NEXT:    ld 3, 72(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 32, 0(3)
+; CHECK-NEXT:    stxv 32, 0(3) # Vec Uses: V0(VSR32)
 ; CHECK-NEXT:    ld 3, 80(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 37, 0(3)
+; CHECK-NEXT:    stxv 37, 0(3) # Vec Uses: V5(VSR37)
 ; CHECK-NEXT:    ld 3, 88(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 36, 0(3)
+; CHECK-NEXT:    stxv 36, 0(3) # Vec Uses: V4(VSR36)
 ; CHECK-NEXT:    ld 3, 96(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 13, 0(3)
+; CHECK-NEXT:    stxv 13, 0(3) # Vec Uses: VSL13(VSR13)
 ; CHECK-NEXT:    ld 3, 104(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 12, 0(3)
+; CHECK-NEXT:    stxv 12, 0(3) # Vec Uses: VSL12(VSR12)
 ; CHECK-NEXT:    ld 3, 112(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 11, 0(3)
+; CHECK-NEXT:    stxv 11, 0(3) # Vec Uses: VSL11(VSR11)
 ; CHECK-NEXT:    ld 3, 120(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 10, 0(3)
+; CHECK-NEXT:    stxv 10, 0(3) # Vec Uses: VSL10(VSR10)
 ; CHECK-NEXT:    ld 3, 128(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 8, 0(3)
+; CHECK-NEXT:    stxv 8, 0(3) # Vec Uses: VSL8(VSR8)
 ; CHECK-NEXT:    ld 3, 136(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 6, 0(3)
+; CHECK-NEXT:    stxv 6, 0(3) # Vec Uses: VSL6(VSR6)
 ; CHECK-NEXT:    ld 3, 144(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 5, 0(3)
+; CHECK-NEXT:    stxv 5, 0(3) # Vec Uses: VSL5(VSR5)
 ; CHECK-NEXT:    ld 3, 152(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 3, 0(3)
+; CHECK-NEXT:    stxv 3, 0(3) # Vec Uses: VSL3(VSR3)
 ; CHECK-NEXT:    ld 3, 160(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 1, 0(3)
+; CHECK-NEXT:    stxv 1, 0(3) # Vec Uses: VSL1(VSR1)
 ; CHECK-NEXT:    ld 3, 168(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 0, 0(3)
+; CHECK-NEXT:    stxv 0, 0(3) # Vec Uses: VSL0(VSR0)
 ; CHECK-NEXT:    ld 3, 176(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 2, 0(3)
+; CHECK-NEXT:    stxv 2, 0(3) # Vec Uses: VSL2(VSR2)
 ; CHECK-NEXT:    ld 3, 184(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 4, 0(3)
+; CHECK-NEXT:    stxv 4, 0(3) # Vec Uses: VSL4(VSR4)
 ; CHECK-NEXT:    ld 3, 192(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 9, 0(3)
+; CHECK-NEXT:    stxv 9, 0(3) # Vec Uses: VSL9(VSR9)
 ; CHECK-NEXT:    ld 3, 200(1) # 8-byte Folded Reload
-; CHECK-NEXT:    stxv 7, 0(3)
+; CHECK-NEXT:    stxv 7, 0(3) # Vec Uses: VSL7(VSR7)
 ; CHECK-NEXT:  .LBB0_7: # %_return_bb
 ; CHECK-NEXT:    lxv 63, 384(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-NEXT:    lxv 62, 368(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V30(VSR62)
 ; CHECK-NEXT:    lxv 61, 352(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V29(VSR61)
 ; CHECK-NEXT:    lxv 60, 336(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V28(VSR60)
 ; CHECK-NEXT:    lxv 59, 320(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V27(VSR59)
 ; CHECK-NEXT:    lxv 58, 304(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V26(VSR58)
 ; CHECK-NEXT:    lxv 57, 288(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V25(VSR57)
 ; CHECK-NEXT:    lxv 56, 272(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V24(VSR56)
 ; CHECK-NEXT:    lxv 55, 256(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V23(VSR55)
 ; CHECK-NEXT:    lxv 54, 240(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V22(VSR54)
 ; CHECK-NEXT:    lxv 53, 224(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V21(VSR53)
 ; CHECK-NEXT:    lxv 52, 208(1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V20(VSR52)
 ; CHECK-NEXT:    lfd 31, 584(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F31(VSR31)
 ; CHECK-NEXT:    lfd 30, 576(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F30(VSR30)
 ; CHECK-NEXT:    lfd 29, 568(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F29(VSR29)
 ; CHECK-NEXT:    lfd 28, 560(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F28(VSR28)
 ; CHECK-NEXT:    lfd 27, 552(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F27(VSR27)
 ; CHECK-NEXT:    lfd 26, 544(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F26(VSR26)
 ; CHECK-NEXT:    ld 31, 536(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld 30, 528(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld 29, 520(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld 28, 512(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld 27, 504(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld 26, 496(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld 25, 488(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld 24, 480(1) # 8-byte Folded Reload

llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,CHECK-OPT %s
 ; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,CHECK-O0 %s
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-BE,CHECK-BE-OPT
 ; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-BE,CHECK-BE-O0
 
 ; The following testcases take one halfword element from the second vector and
 ; inserts it at various locations in the first vector
 define <8 x i16> @shuffle_vector_halfword_0_8(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: shuffle_vector_halfword_0_8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-NEXT:    vinserth 2, 3, 14
+; CHECK-NEXT:    vsldoi 3, 3, 3, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinserth 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_0_8:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-BE-NEXT:    vinserth 2, 3, 0
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinserth 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_1_15(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: shuffle_vector_halfword_1_15:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-NEXT:    vinserth 2, 3, 12
+; CHECK-NEXT:    vsldoi 3, 3, 3, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinserth 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_1_15:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-BE-NEXT:    vinserth 2, 3, 2
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinserth 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 15, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_2_9(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: shuffle_vector_halfword_2_9:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-NEXT:    vinserth 2, 3, 10
+; CHECK-NEXT:    vsldoi 3, 3, 3, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinserth 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_2_9:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-BE-NEXT:    vinserth 2, 3, 4
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinserth 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 9, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_3_13(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: shuffle_vector_halfword_3_13:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-NEXT:    vinserth 2, 3, 8
+; CHECK-NEXT:    vsldoi 3, 3, 3, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinserth 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_3_13:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-BE-NEXT:    vinserth 2, 3, 6
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinserth 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_4_10(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: shuffle_vector_halfword_4_10:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-NEXT:    vinserth 2, 3, 6
+; CHECK-NEXT:    vsldoi 3, 3, 3, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinserth 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_4_10:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-BE-NEXT:    vinserth 2, 3, 8
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinserth 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_5_14(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: shuffle_vector_halfword_5_14:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-NEXT:    vinserth 2, 3, 4
+; CHECK-NEXT:    vsldoi 3, 3, 3, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinserth 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_5_14:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-BE-NEXT:    vinserth 2, 3, 10
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinserth 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 14, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_6_11(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: shuffle_vector_halfword_6_11:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-NEXT:    vinserth 2, 3, 2
+; CHECK-NEXT:    vsldoi 3, 3, 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinserth 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_6_11:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinserth 2, 3, 12
+; CHECK-BE-NEXT:    vinserth 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 11, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_7_12(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: shuffle_vector_halfword_7_12:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinserth 2, 3, 0
+; CHECK-NEXT:    vinserth 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_7_12:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-BE-NEXT:    vinserth 2, 3, 14
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinserth 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 12>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_8_1(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_halfword_8_1:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 6
-; CHECK-OPT-NEXT:    vinserth 3, 2, 14
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinserth 3, 2, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_halfword_8_1:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-O0-NEXT:    vinserth 2, 3, 14
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinserth 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_8_1:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 12
-; CHECK-BE-OPT-NEXT:    vinserth 3, 2, 0
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinserth 3, 2, 0 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_halfword_8_1:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-BE-O0-NEXT:    vinserth 2, 3, 0
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinserth 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
 
 ; The following testcases take one halfword element from the first vector and
 ; inserts it at various locations in the second vector
 define <8 x i16> @shuffle_vector_halfword_9_7(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_halfword_9_7:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 10
-; CHECK-OPT-NEXT:    vinserth 3, 2, 12
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinserth 3, 2, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_halfword_9_7:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-O0-NEXT:    vinserth 2, 3, 12
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinserth 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_9_7:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 8
-; CHECK-BE-OPT-NEXT:    vinserth 3, 2, 2
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinserth 3, 2, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_halfword_9_7:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-BE-O0-NEXT:    vinserth 2, 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinserth 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_10_4(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_halfword_10_4:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vinserth 3, 2, 10
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vinserth 3, 2, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_halfword_10_4:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vinserth 2, 3, 10
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vinserth 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_10_4:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 2
-; CHECK-BE-OPT-NEXT:    vinserth 3, 2, 4
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinserth 3, 2, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_halfword_10_4:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-BE-O0-NEXT:    vinserth 2, 3, 4
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinserth 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 4, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_11_2(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_halfword_11_2:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 4
-; CHECK-OPT-NEXT:    vinserth 3, 2, 8
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinserth 3, 2, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_halfword_11_2:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-O0-NEXT:    vinserth 2, 3, 8
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinserth 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_11_2:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 14
-; CHECK-BE-OPT-NEXT:    vinserth 3, 2, 6
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinserth 3, 2, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_halfword_11_2:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-BE-O0-NEXT:    vinserth 2, 3, 6
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinserth 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 2, i32 12, i32 13, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_12_6(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_halfword_12_6:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 12
-; CHECK-OPT-NEXT:    vinserth 3, 2, 6
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinserth 3, 2, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_halfword_12_6:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-O0-NEXT:    vinserth 2, 3, 6
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinserth 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_12_6:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 6
-; CHECK-BE-OPT-NEXT:    vinserth 3, 2, 8
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinserth 3, 2, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_halfword_12_6:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-BE-O0-NEXT:    vinserth 2, 3, 8
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinserth 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 6, i32 13, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_13_3(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_halfword_13_3:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 2
-; CHECK-OPT-NEXT:    vinserth 3, 2, 4
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinserth 3, 2, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_halfword_13_3:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-O0-NEXT:    vinserth 2, 3, 4
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinserth 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_13_3:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vinserth 3, 2, 10
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vinserth 3, 2, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_halfword_13_3:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vinserth 2, 3, 10
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vinserth 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 3, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_14_5(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_halfword_14_5:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 14
-; CHECK-OPT-NEXT:    vinserth 3, 2, 2
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinserth 3, 2, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_halfword_14_5:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-O0-NEXT:    vinserth 2, 3, 2
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinserth 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_14_5:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 4
-; CHECK-BE-OPT-NEXT:    vinserth 3, 2, 12
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinserth 3, 2, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_halfword_14_5:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-BE-O0-NEXT:    vinserth 2, 3, 12
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinserth 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 5, i32 15>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_15_0(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_halfword_15_0:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 8
-; CHECK-OPT-NEXT:    vinserth 3, 2, 0
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinserth 3, 2, 0 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_halfword_15_0:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-O0-NEXT:    vinserth 2, 3, 0
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinserth 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_15_0:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 10
-; CHECK-BE-OPT-NEXT:    vinserth 3, 2, 14
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinserth 3, 2, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_halfword_15_0:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-BE-O0-NEXT:    vinserth 2, 3, 14
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinserth 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>
   ret <8 x i16> %vecins
 }
 
 ; The following testcases use the same vector in both arguments of the
 ; shufflevector.  If halfword element 3 in BE mode(or 4 in LE mode) is the one
 ; we're attempting to insert, then we can use the vector insert instruction
 define <8 x i16> @shuffle_vector_halfword_0_4(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_0_4:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinserth 2, 2, 14
+; CHECK-NEXT:    vinserth 2, 2, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_0_4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI16_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI16_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_1_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI17_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI17_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_1_3:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinserth 2, 2, 2
+; CHECK-BE-NEXT:    vinserth 2, 2, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_2_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI18_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI18_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_2_3:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinserth 2, 2, 4
+; CHECK-BE-NEXT:    vinserth 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_3_4:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinserth 2, 2, 8
+; CHECK-NEXT:    vinserth 2, 2, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_3_4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI19_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI19_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_4_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI20_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI20_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_4_3:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinserth 2, 2, 8
+; CHECK-BE-NEXT:    vinserth 2, 2, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_5_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI21_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_5_3:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinserth 2, 2, 10
+; CHECK-BE-NEXT:    vinserth 2, 2, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_6_4:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinserth 2, 2, 2
+; CHECK-NEXT:    vinserth 2, 2, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_6_4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI22_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI22_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_7_4:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinserth 2, 2, 0
+; CHECK-NEXT:    vinserth 2, 2, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_7_4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI23_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI23_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4>
   ret <8 x i16> %vecins
 }
 
 ; The following testcases take one byte element from the second vector and
 ; inserts it at various locations in the first vector
 define <16 x i8> @shuffle_vector_byte_0_16(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: shuffle_vector_byte_0_16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-NEXT:    vinsertb 2, 3, 15
+; CHECK-NEXT:    vsldoi 3, 3, 3, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinsertb 2, 3, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_0_16:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 9
-; CHECK-BE-NEXT:    vinsertb 2, 3, 0
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 9 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinsertb 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_1_25(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: shuffle_vector_byte_1_25:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 15
-; CHECK-NEXT:    vinsertb 2, 3, 14
+; CHECK-NEXT:    vsldoi 3, 3, 3, 15 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinsertb 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_1_25:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-BE-NEXT:    vinsertb 2, 3, 1
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinsertb 2, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 25, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_2_18(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: shuffle_vector_byte_2_18:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-NEXT:    vinsertb 2, 3, 13
+; CHECK-NEXT:    vsldoi 3, 3, 3, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinsertb 2, 3, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_2_18:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 11
-; CHECK-BE-NEXT:    vinsertb 2, 3, 2
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 11 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinsertb 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 18, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_3_27(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: shuffle_vector_byte_3_27:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 13
-; CHECK-NEXT:    vinsertb 2, 3, 12
+; CHECK-NEXT:    vsldoi 3, 3, 3, 13 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinsertb 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_3_27:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-BE-NEXT:    vinsertb 2, 3, 3
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinsertb 2, 3, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 27, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_4_20(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: shuffle_vector_byte_4_20:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-NEXT:    vinsertb 2, 3, 11
+; CHECK-NEXT:    vsldoi 3, 3, 3, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinsertb 2, 3, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_4_20:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 13
-; CHECK-BE-NEXT:    vinsertb 2, 3, 4
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 13 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinsertb 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_5_29(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: shuffle_vector_byte_5_29:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 11
-; CHECK-NEXT:    vinsertb 2, 3, 10
+; CHECK-NEXT:    vsldoi 3, 3, 3, 11 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinsertb 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_5_29:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-BE-NEXT:    vinsertb 2, 3, 5
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinsertb 2, 3, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 29, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_6_22(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: shuffle_vector_byte_6_22:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-NEXT:    vinsertb 2, 3, 9
+; CHECK-NEXT:    vsldoi 3, 3, 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinsertb 2, 3, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_6_22:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 15
-; CHECK-BE-NEXT:    vinsertb 2, 3, 6
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 15 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinsertb 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 22, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_7_31(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: shuffle_vector_byte_7_31:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 9
-; CHECK-NEXT:    vinsertb 2, 3, 8
+; CHECK-NEXT:    vsldoi 3, 3, 3, 9 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinsertb 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_7_31:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-BE-NEXT:    vinsertb 2, 3, 7
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinsertb 2, 3, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 31, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_8_24(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: shuffle_vector_byte_8_24:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 3, 7
+; CHECK-NEXT:    vinsertb 2, 3, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_8_24:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 1
-; CHECK-BE-NEXT:    vinsertb 2, 3, 8
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 1 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinsertb 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_9_17(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: shuffle_vector_byte_9_17:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 7
-; CHECK-NEXT:    vinsertb 2, 3, 6
+; CHECK-NEXT:    vsldoi 3, 3, 3, 7 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinsertb 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_9_17:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-BE-NEXT:    vinsertb 2, 3, 9
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinsertb 2, 3, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 17, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_10_26(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: shuffle_vector_byte_10_26:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-NEXT:    vinsertb 2, 3, 5
+; CHECK-NEXT:    vsldoi 3, 3, 3, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinsertb 2, 3, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_10_26:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 3
-; CHECK-BE-NEXT:    vinsertb 2, 3, 10
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 3 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinsertb 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 26, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_11_19(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: shuffle_vector_byte_11_19:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 5
-; CHECK-NEXT:    vinsertb 2, 3, 4
+; CHECK-NEXT:    vsldoi 3, 3, 3, 5 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinsertb 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_11_19:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-BE-NEXT:    vinsertb 2, 3, 11
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinsertb 2, 3, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 19, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_12_28(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: shuffle_vector_byte_12_28:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-NEXT:    vinsertb 2, 3, 3
+; CHECK-NEXT:    vsldoi 3, 3, 3, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinsertb 2, 3, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_12_28:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 5
-; CHECK-BE-NEXT:    vinsertb 2, 3, 12
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 5 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinsertb 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 28, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_13_21(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: shuffle_vector_byte_13_21:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 3
-; CHECK-NEXT:    vinsertb 2, 3, 2
+; CHECK-NEXT:    vsldoi 3, 3, 3, 3 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinsertb 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_13_21:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-BE-NEXT:    vinsertb 2, 3, 13
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinsertb 2, 3, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 21, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_14_30(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: shuffle_vector_byte_14_30:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-NEXT:    vinsertb 2, 3, 1
+; CHECK-NEXT:    vsldoi 3, 3, 3, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinsertb 2, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_14_30:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 7
-; CHECK-BE-NEXT:    vinsertb 2, 3, 14
+; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 7 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-NEXT:    vinsertb 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 30, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_15_23(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: shuffle_vector_byte_15_23:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 1
-; CHECK-NEXT:    vinsertb 2, 3, 0
+; CHECK-NEXT:    vsldoi 3, 3, 3, 1 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    vinsertb 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_15_23:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 3, 15
+; CHECK-BE-NEXT:    vinsertb 2, 3, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 23>
   ret <16 x i8> %vecins
 }
 
 ; The following testcases take one byte element from the first vector and
 ; inserts it at various locations in the second vector
 define <16 x i8> @shuffle_vector_byte_16_8(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_byte_16_8:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vinsertb 3, 2, 15
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vinsertb 3, 2, 15 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_byte_16_8:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vinsertb 2, 3, 15
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_16_8:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 1
-; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 0
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 0 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_16_8:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 1
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 0
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 1 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_17_1(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_byte_17_1:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 7
-; CHECK-OPT-NEXT:    vinsertb 3, 2, 14
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinsertb 3, 2, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_byte_17_1:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 7
-; CHECK-O0-NEXT:    vinsertb 2, 3, 14
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 7 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_17_1:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 10
-; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 1
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 1 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_17_1:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 1
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_18_10(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_byte_18_10:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 14
-; CHECK-OPT-NEXT:    vinsertb 3, 2, 13
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinsertb 3, 2, 13 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_byte_18_10:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-O0-NEXT:    vinsertb 2, 3, 13
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_18_10:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 3
-; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 2
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_18_10:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 3
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 3 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 10, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_19_3(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_byte_19_3:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 5
-; CHECK-OPT-NEXT:    vinsertb 3, 2, 12
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinsertb 3, 2, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_byte_19_3:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 5
-; CHECK-O0-NEXT:    vinsertb 2, 3, 12
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 5 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_19_3:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 12
-; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 3
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 3 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_19_3:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 3
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_20_12(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_byte_20_12:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 12
-; CHECK-OPT-NEXT:    vinsertb 3, 2, 11
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinsertb 3, 2, 11 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_byte_20_12:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-O0-NEXT:    vinsertb 2, 3, 11
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_20_12:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 4
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_20_12:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 5
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 4
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 5 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 12, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_21_5(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_byte_21_5:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 3
-; CHECK-OPT-NEXT:    vinsertb 3, 2, 10
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinsertb 3, 2, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_byte_21_5:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 3
-; CHECK-O0-NEXT:    vinsertb 2, 3, 10
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 3 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_21_5:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 14
-; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 5
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 5 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_21_5:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 5
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 5, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_22_14(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_byte_22_14:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 10
-; CHECK-OPT-NEXT:    vinsertb 3, 2, 9
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinsertb 3, 2, 9 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_byte_22_14:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-O0-NEXT:    vinsertb 2, 3, 9
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_22_14:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 7
-; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 6
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_22_14:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 7
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 6
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 7 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 14, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_23_7(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_byte_23_7:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 1
-; CHECK-OPT-NEXT:    vinsertb 3, 2, 8
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinsertb 3, 2, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_byte_23_7:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 1
-; CHECK-O0-NEXT:    vinsertb 2, 3, 8
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 1 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_23_7:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 7
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 7 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_23_7:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 7
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_24_0(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_byte_24_0:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 8
-; CHECK-OPT-NEXT:    vinsertb 3, 2, 7
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinsertb 3, 2, 7 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_byte_24_0:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-O0-NEXT:    vinsertb 2, 3, 7
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_24_0:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 9
-; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 8
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_24_0:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 9
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 8
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 9 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 0, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_25_9(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_byte_25_9:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 15
-; CHECK-OPT-NEXT:    vinsertb 3, 2, 6
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinsertb 3, 2, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_byte_25_9:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 15
-; CHECK-O0-NEXT:    vinsertb 2, 3, 6
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 15 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_25_9:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 2
-; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 9
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 9 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_25_9:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 9
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 9, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_26_2(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_byte_26_2:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 6
-; CHECK-OPT-NEXT:    vinsertb 3, 2, 5
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinsertb 3, 2, 5 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_byte_26_2:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-O0-NEXT:    vinsertb 2, 3, 5
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_26_2:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 11
-; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 10
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 10 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_26_2:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 11
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 10
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 11 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 2, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_27_11(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_byte_27_11:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 13
-; CHECK-OPT-NEXT:    vinsertb 3, 2, 4
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinsertb 3, 2, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_byte_27_11:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 13
-; CHECK-O0-NEXT:    vinsertb 2, 3, 4
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 13 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_27_11:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 4
-; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 11
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 11 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_27_11:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 11
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 11, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_28_4(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_byte_28_4:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 4
-; CHECK-OPT-NEXT:    vinsertb 3, 2, 3
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinsertb 3, 2, 3 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_byte_28_4:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-O0-NEXT:    vinsertb 2, 3, 3
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 4 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_28_4:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 13
-; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 12
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 12 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_28_4:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 13
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 12
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 13 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 4, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_29_13(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_byte_29_13:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 11
-; CHECK-OPT-NEXT:    vinsertb 3, 2, 2
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinsertb 3, 2, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_byte_29_13:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 11
-; CHECK-O0-NEXT:    vinsertb 2, 3, 2
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 11 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_29_13:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 6
-; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 13
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 13 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_29_13:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 13
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 6 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 13, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_30_6(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_byte_30_6:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 2
-; CHECK-OPT-NEXT:    vinsertb 3, 2, 1
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinsertb 3, 2, 1 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_byte_30_6:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-O0-NEXT:    vinsertb 2, 3, 1
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_30_6:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 15
-; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 14
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 14 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_30_6:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 15
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 14
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 15 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 6, i32 31>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_31_15(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-OPT-LABEL: shuffle_vector_byte_31_15:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 9
-; CHECK-OPT-NEXT:    vinsertb 3, 2, 0
-; CHECK-OPT-NEXT:    vmr 2, 3
+; CHECK-OPT-NEXT:    vsldoi 2, 2, 2, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-OPT-NEXT:    vinsertb 3, 2, 0 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: shuffle_vector_byte_31_15:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-O0-NEXT:    vmr 3, 2
+; CHECK-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 9
-; CHECK-O0-NEXT:    vinsertb 2, 3, 0
+; CHECK-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-O0-NEXT:    vsldoi 3, 3, 3, 9 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_31_15:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 8
-; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 15
-; CHECK-BE-OPT-NEXT:    vmr 2, 3
+; CHECK-BE-OPT-NEXT:    vsldoi 2, 2, 2, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vinsertb 3, 2, 15 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V2(VSR34)
+; CHECK-BE-OPT-NEXT:    vmr 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_31_15:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    stxv 35, -16(1) # 16-byte Folded Spill
-; CHECK-BE-O0-NEXT:    vmr 3, 2
+; CHECK-BE-O0-NEXT:    # Vec Uses: V3(VSR35)
+; CHECK-BE-O0-NEXT:    vmr 3, 2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-O0-NEXT:    lxv 34, -16(1) # 16-byte Folded Reload
-; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 15
+; CHECK-BE-O0-NEXT:    # Vec Defs: V2(VSR34)
+; CHECK-BE-O0-NEXT:    vsldoi 3, 3, 3, 8 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 15>
   ret <16 x i8> %vecins
 }
 
 ; The following testcases use the same vector in both arguments of the
 ; shufflevector.  If byte element 7 in BE mode(or 8 in LE mode) is the one
 ; we're attempting to insert, then we can use the vector insert instruction
 define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_0_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI56_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI56_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_0_7:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 0
+; CHECK-BE-NEXT:    vinsertb 2, 2, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_1_8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 14
+; CHECK-NEXT:    vinsertb 2, 2, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_1_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI57_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI57_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_2_8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 13
+; CHECK-NEXT:    vinsertb 2, 2, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_2_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI58_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI58_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_3_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI59_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI59_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_3_7:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 3
+; CHECK-BE-NEXT:    vinsertb 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_4_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI60_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI60_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_4_7:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 4
+; CHECK-BE-NEXT:    vinsertb 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_5_8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 10
+; CHECK-NEXT:    vinsertb 2, 2, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_5_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI61_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI61_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_6_8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 9
+; CHECK-NEXT:    vinsertb 2, 2, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_6_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI62_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI62_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_7_8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 8
+; CHECK-NEXT:    vinsertb 2, 2, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_7_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI63_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI63_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_8_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI64_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI64_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_8_7:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 8
+; CHECK-BE-NEXT:    vinsertb 2, 2, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_9_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI65_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI65_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_9_7:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 9
+; CHECK-BE-NEXT:    vinsertb 2, 2, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_10_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI66_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI66_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_10_7:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 10
+; CHECK-BE-NEXT:    vinsertb 2, 2, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_11_8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 4
+; CHECK-NEXT:    vinsertb 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_11_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI67_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI67_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_12_8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 3
+; CHECK-NEXT:    vinsertb 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_12_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI68_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI68_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_13_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI69_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI69_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_13_7:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 13
+; CHECK-BE-NEXT:    vinsertb 2, 2, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 7, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_14_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI70_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI70_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_14_7:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 14
+; CHECK-BE-NEXT:    vinsertb 2, 2, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_15_8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 0
+; CHECK-NEXT:    vinsertb 2, 2, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_15_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI71_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI71_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8>
   ret <16 x i8> %vecins
 }
 
 ; The following tests try to insert one halfword element into the vector.  We
 ; should always be using the 'vinserth' instruction.
 define <8 x i16> @insert_halfword_0(<8 x i16> %a, i16 %b) {
 ; CHECK-OPT-LABEL: insert_halfword_0:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinserth 2, 3, 14
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinserth 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_halfword_0:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinserth 2, 3, 14
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinserth 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_halfword_0:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinserth 2, 3, 0
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinserth 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_halfword_0:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinserth 2, 3, 0
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinserth 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <8 x i16> %a, i16 %b, i32 0
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @insert_halfword_1(<8 x i16> %a, i16 %b) {
 ; CHECK-OPT-LABEL: insert_halfword_1:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinserth 2, 3, 12
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinserth 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_halfword_1:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinserth 2, 3, 12
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinserth 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_halfword_1:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinserth 2, 3, 2
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinserth 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_halfword_1:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinserth 2, 3, 2
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinserth 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <8 x i16> %a, i16 %b, i32 1
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @insert_halfword_2(<8 x i16> %a, i16 %b) {
 ; CHECK-OPT-LABEL: insert_halfword_2:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinserth 2, 3, 10
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinserth 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_halfword_2:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinserth 2, 3, 10
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinserth 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_halfword_2:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinserth 2, 3, 4
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinserth 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_halfword_2:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinserth 2, 3, 4
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinserth 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <8 x i16> %a, i16 %b, i32 2
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @insert_halfword_3(<8 x i16> %a, i16 %b) {
 ; CHECK-OPT-LABEL: insert_halfword_3:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinserth 2, 3, 8
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinserth 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_halfword_3:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinserth 2, 3, 8
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinserth 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_halfword_3:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinserth 2, 3, 6
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinserth 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_halfword_3:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinserth 2, 3, 6
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinserth 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <8 x i16> %a, i16 %b, i32 3
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @insert_halfword_4(<8 x i16> %a, i16 %b) {
 ; CHECK-OPT-LABEL: insert_halfword_4:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinserth 2, 3, 6
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinserth 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_halfword_4:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinserth 2, 3, 6
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinserth 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_halfword_4:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinserth 2, 3, 8
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinserth 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_halfword_4:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinserth 2, 3, 8
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinserth 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <8 x i16> %a, i16 %b, i32 4
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @insert_halfword_5(<8 x i16> %a, i16 %b) {
 ; CHECK-OPT-LABEL: insert_halfword_5:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinserth 2, 3, 4
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinserth 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_halfword_5:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinserth 2, 3, 4
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinserth 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_halfword_5:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinserth 2, 3, 10
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinserth 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_halfword_5:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinserth 2, 3, 10
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinserth 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <8 x i16> %a, i16 %b, i32 5
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @insert_halfword_6(<8 x i16> %a, i16 %b) {
 ; CHECK-OPT-LABEL: insert_halfword_6:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinserth 2, 3, 2
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinserth 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_halfword_6:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinserth 2, 3, 2
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinserth 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_halfword_6:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinserth 2, 3, 12
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinserth 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_halfword_6:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinserth 2, 3, 12
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinserth 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <8 x i16> %a, i16 %b, i32 6
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @insert_halfword_7(<8 x i16> %a, i16 %b) {
 ; CHECK-OPT-LABEL: insert_halfword_7:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinserth 2, 3, 0
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinserth 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_halfword_7:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinserth 2, 3, 0
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinserth 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_halfword_7:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinserth 2, 3, 14
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinserth 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_halfword_7:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinserth 2, 3, 14
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinserth 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <8 x i16> %a, i16 %b, i32 7
   ret <8 x i16> %vecins
 }
 
 ; The following tests try to insert one byte element into the vector.  We
 ; should always be using the 'vinsertb' instruction.
 define <16 x i8> @insert_byte_0(<16 x i8> %a, i8 %b) {
 ; CHECK-OPT-LABEL: insert_byte_0:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinsertb 2, 3, 15
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinsertb 2, 3, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_byte_0:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinsertb 2, 3, 15
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_byte_0:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 0
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_byte_0:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 0
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 0
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_1(<16 x i8> %a, i8 %b) {
 ; CHECK-OPT-LABEL: insert_byte_1:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinsertb 2, 3, 14
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinsertb 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_byte_1:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinsertb 2, 3, 14
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_byte_1:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 1
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_byte_1:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 1
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 1
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_2(<16 x i8> %a, i8 %b) {
 ; CHECK-OPT-LABEL: insert_byte_2:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinsertb 2, 3, 13
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinsertb 2, 3, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_byte_2:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinsertb 2, 3, 13
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_byte_2:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 2
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_byte_2:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 2
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 2
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_3(<16 x i8> %a, i8 %b) {
 ; CHECK-OPT-LABEL: insert_byte_3:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinsertb 2, 3, 12
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinsertb 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_byte_3:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinsertb 2, 3, 12
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_byte_3:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 3
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_byte_3:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 3
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 3
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_4(<16 x i8> %a, i8 %b) {
 ; CHECK-OPT-LABEL: insert_byte_4:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinsertb 2, 3, 11
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinsertb 2, 3, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_byte_4:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinsertb 2, 3, 11
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_byte_4:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 4
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_byte_4:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 4
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 4
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_5(<16 x i8> %a, i8 %b) {
 ; CHECK-OPT-LABEL: insert_byte_5:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinsertb 2, 3, 10
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinsertb 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_byte_5:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinsertb 2, 3, 10
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_byte_5:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 5
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_byte_5:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 5
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 5
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_6(<16 x i8> %a, i8 %b) {
 ; CHECK-OPT-LABEL: insert_byte_6:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinsertb 2, 3, 9
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinsertb 2, 3, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_byte_6:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinsertb 2, 3, 9
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_byte_6:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 6
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_byte_6:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 6
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 6
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_7(<16 x i8> %a, i8 %b) {
 ; CHECK-OPT-LABEL: insert_byte_7:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinsertb 2, 3, 8
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinsertb 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_byte_7:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinsertb 2, 3, 8
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_byte_7:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 7
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_byte_7:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 7
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 7
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_8(<16 x i8> %a, i8 %b) {
 ; CHECK-OPT-LABEL: insert_byte_8:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinsertb 2, 3, 7
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinsertb 2, 3, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_byte_8:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinsertb 2, 3, 7
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 7 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_byte_8:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 8
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_byte_8:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 8
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 8 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 8
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_9(<16 x i8> %a, i8 %b) {
 ; CHECK-OPT-LABEL: insert_byte_9:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinsertb 2, 3, 6
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinsertb 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_byte_9:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinsertb 2, 3, 6
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 6 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_byte_9:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 9
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_byte_9:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 9
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 9 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 9
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_10(<16 x i8> %a, i8 %b) {
 ; CHECK-OPT-LABEL: insert_byte_10:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinsertb 2, 3, 5
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinsertb 2, 3, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_byte_10:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinsertb 2, 3, 5
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 5 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_byte_10:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 10
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_byte_10:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 10
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 10 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 10
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_11(<16 x i8> %a, i8 %b) {
 ; CHECK-OPT-LABEL: insert_byte_11:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinsertb 2, 3, 4
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinsertb 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_byte_11:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinsertb 2, 3, 4
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_byte_11:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 11
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_byte_11:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 11
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 11 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 11
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_12(<16 x i8> %a, i8 %b) {
 ; CHECK-OPT-LABEL: insert_byte_12:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinsertb 2, 3, 3
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinsertb 2, 3, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_byte_12:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinsertb 2, 3, 3
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_byte_12:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 12
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_byte_12:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 12
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 12 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 12
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_13(<16 x i8> %a, i8 %b) {
 ; CHECK-OPT-LABEL: insert_byte_13:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinsertb 2, 3, 2
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinsertb 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_byte_13:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinsertb 2, 3, 2
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_byte_13:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 13
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_byte_13:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 13
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 13 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 13
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_14(<16 x i8> %a, i8 %b) {
 ; CHECK-OPT-LABEL: insert_byte_14:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinsertb 2, 3, 1
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinsertb 2, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_byte_14:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinsertb 2, 3, 1
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_byte_14:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 14
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_byte_14:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 14
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 14 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 14
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @insert_byte_15(<16 x i8> %a, i8 %b) {
 ; CHECK-OPT-LABEL: insert_byte_15:
 ; CHECK-OPT:       # %bb.0: # %entry
-; CHECK-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-OPT-NEXT:    vinsertb 2, 3, 0
+; CHECK-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-OPT-NEXT:    vinsertb 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-OPT-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: insert_byte_15:
 ; CHECK-O0:       # %bb.0: # %entry
 ; CHECK-O0-NEXT:    mr 3, 5
-; CHECK-O0-NEXT:    mtfprwz 0, 3
-; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-O0-NEXT:    vinsertb 2, 3, 0
+; CHECK-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-O0-NEXT:    vinsertb 2, 3, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-O0-NEXT:    blr
 ;
 ; CHECK-BE-OPT-LABEL: insert_byte_15:
 ; CHECK-BE-OPT:       # %bb.0: # %entry
-; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5
-; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 15
+; CHECK-BE-OPT-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; CHECK-BE-OPT-NEXT:    vinsertb 2, 3, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-OPT-NEXT:    blr
 ;
 ; CHECK-BE-O0-LABEL: insert_byte_15:
 ; CHECK-BE-O0:       # %bb.0: # %entry
 ; CHECK-BE-O0-NEXT:    mr 3, 5
-; CHECK-BE-O0-NEXT:    mtfprwz 0, 3
-; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0
-; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 15
+; CHECK-BE-O0-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; CHECK-BE-O0-NEXT:    xscpsgndp 35, 0, 0 # Vec Defs: VF3(VSR3) Vec Uses: F0(VSR0)F0(VSR0)
+; CHECK-BE-O0-NEXT:    vinsertb 2, 3, 15 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-BE-O0-NEXT:    blr
 entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 15
   ret <16 x i8> %vecins
 }

llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll

 ; This test also checks that the paired vector intrinsics are available even
 ; when MMA is disabled.
 
 ; assemble_pair
 declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
 define void @ass_pair(<256 x i1>* %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: ass_pair:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmr v3, v2
-; CHECK-NEXT:    stxv v2, 16(r3)
-; CHECK-NEXT:    stxv v3, 0(r3)
+; CHECK-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    stxv v2, 16(r3) # Vec Uses: V2(VSR34)
+; CHECK-NEXT:    stxv v3, 0(r3) # Vec Uses: V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: ass_pair:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    vmr v3, v2
-; CHECK-NOMMA-NEXT:    stxv v2, 16(r3)
-; CHECK-NOMMA-NEXT:    stxv v3, 0(r3)
+; CHECK-NOMMA-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NOMMA-NEXT:    stxv v2, 16(r3) # Vec Uses: V2(VSR34)
+; CHECK-NOMMA-NEXT:    stxv v3, 0(r3) # Vec Uses: V3(VSR35)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: ass_pair:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vmr v3, v2
-; CHECK-BE-NEXT:    stxv v2, 16(r3)
-; CHECK-BE-NEXT:    stxv v2, 0(r3)
+; CHECK-BE-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-NEXT:    stxv v2, 16(r3) # Vec Uses: V2(VSR34)
+; CHECK-BE-NEXT:    stxv v2, 0(r3) # Vec Uses: V2(VSR34)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: ass_pair:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    vmr v3, v2
-; CHECK-BE-NOMMA-NEXT:    stxv v2, 16(r3)
-; CHECK-BE-NOMMA-NEXT:    stxv v2, 0(r3)
+; CHECK-BE-NOMMA-NEXT:    vmr v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-BE-NOMMA-NEXT:    stxv v2, 16(r3) # Vec Uses: V2(VSR34)
+; CHECK-BE-NOMMA-NEXT:    stxv v2, 0(r3) # Vec Uses: V2(VSR34)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc, <16 x i8> %vc)
   store <256 x i1> %0, <256 x i1>* %ptr, align 32
   ret void
 }
 
 ; disassemble_pair
 declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)
 define void @disass_pair(<256 x i1>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3) {
 ; CHECK-LABEL: disass_pair:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv v3, 0(r3)
-; CHECK-NEXT:    lxv v2, 16(r3)
-; CHECK-NEXT:    stxv v3, 0(r4)
-; CHECK-NEXT:    stxv v2, 0(r5)
+; CHECK-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    lxv v2, 16(r3) # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    stxv v3, 0(r4) # Vec Uses: V3(VSR35)
+; CHECK-NEXT:    stxv v2, 0(r5) # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: disass_pair:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    lxv v3, 0(r3)
-; CHECK-NOMMA-NEXT:    lxv v2, 16(r3)
-; CHECK-NOMMA-NEXT:    stxv v3, 0(r4)
-; CHECK-NOMMA-NEXT:    stxv v2, 0(r5)
+; CHECK-NOMMA-NEXT:    lxv v3, 0(r3) # Vec Defs: V3(VSR35)
+; CHECK-NOMMA-NEXT:    lxv v2, 16(r3) # Vec Defs: V2(VSR34)
+; CHECK-NOMMA-NEXT:    stxv v3, 0(r4) # Vec Uses: V3(VSR35)
+; CHECK-NOMMA-NEXT:    stxv v2, 0(r5) # Vec Uses: V2(VSR34)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: disass_pair:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv v3, 16(r3)
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    stxv v2, 0(r4)
-; CHECK-BE-NEXT:    stxv v3, 0(r5)
+; CHECK-BE-NEXT:    lxv v3, 16(r3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
+; CHECK-BE-NEXT:    stxv v2, 0(r4) # Vec Uses: V2(VSR34)
+; CHECK-BE-NEXT:    stxv v3, 0(r5) # Vec Uses: V3(VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: disass_pair:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    lxv v3, 16(r3)
-; CHECK-BE-NOMMA-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NOMMA-NEXT:    stxv v2, 0(r4)
-; CHECK-BE-NOMMA-NEXT:    stxv v3, 0(r5)
+; CHECK-BE-NOMMA-NEXT:    lxv v3, 16(r3) # Vec Defs: V3(VSR35)
+; CHECK-BE-NOMMA-NEXT:    lxv v2, 0(r3) # Vec Defs: V2(VSR34)
+; CHECK-BE-NOMMA-NEXT:    stxv v2, 0(r4) # Vec Uses: V2(VSR34)
+; CHECK-BE-NOMMA-NEXT:    stxv v3, 0(r5) # Vec Uses: V3(VSR35)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = load <256 x i1>, <256 x i1>* %ptr1, align 32
   %1 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> %0)
   %2 = extractvalue { <16 x i8>, <16 x i8> } %1, 0
   %3 = extractvalue { <16 x i8>, <16 x i8> } %1, 1
   store <16 x i8> %2, <16 x i8>* %ptr2, align 16
   store <16 x i8> %3, <16 x i8>* %ptr3, align 16
   ret void
 }
 
 define void @test_ldst_1(<256 x i1>* %vpp, <256 x i1>* %vp2) {
 ; CHECK-LABEL: test_ldst_1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxvp vsp34, 0(r3)
-; CHECK-NEXT:    stxvp vsp34, 0(r4)
+; CHECK-NEXT:    lxvp vsp34, 0(r3) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    stxvp vsp34, 0(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_1:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    lxvp vsp34, 0(r3)
-; CHECK-NOMMA-NEXT:    stxvp vsp34, 0(r4)
+; CHECK-NOMMA-NEXT:    lxvp vsp34, 0(r3) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NOMMA-NEXT:    stxvp vsp34, 0(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_1:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxvp vsp34, 0(r3)
-; CHECK-BE-NEXT:    stxvp vsp34, 0(r4)
+; CHECK-BE-NEXT:    lxvp vsp34, 0(r3) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NEXT:    stxvp vsp34, 0(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_1:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    lxvp vsp34, 0(r3)
-; CHECK-BE-NOMMA-NEXT:    stxvp vsp34, 0(r4)
+; CHECK-BE-NOMMA-NEXT:    lxvp vsp34, 0(r3) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NOMMA-NEXT:    stxvp vsp34, 0(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %0)
   %2 = bitcast <256 x i1>* %vp2 to i8*
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, i8* %2)
   ret void
 }
 
 declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*)
 declare void @llvm.ppc.vsx.stxvp(<256 x i1>, i8*)
 
 define void @test_ldst_2(<256 x i1>* %vpp, i64 %offset, <256 x i1>* %vp2)  {
 ; CHECK-LABEL: test_ldst_2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxvpx vsp34, r3, r4
-; CHECK-NEXT:    stxvpx vsp34, r5, r4
+; CHECK-NEXT:    lxvpx vsp34, r3, r4 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    stxvpx vsp34, r5, r4 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_2:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    lxvpx vsp34, r3, r4
-; CHECK-NOMMA-NEXT:    stxvpx vsp34, r5, r4
+; CHECK-NOMMA-NEXT:    lxvpx vsp34, r3, r4 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NOMMA-NEXT:    stxvpx vsp34, r5, r4 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_2:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxvpx vsp34, r3, r4
-; CHECK-BE-NEXT:    stxvpx vsp34, r5, r4
+; CHECK-BE-NEXT:    lxvpx vsp34, r3, r4 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NEXT:    stxvpx vsp34, r5, r4 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_2:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    lxvpx vsp34, r3, r4
-; CHECK-BE-NOMMA-NEXT:    stxvpx vsp34, r5, r4
+; CHECK-BE-NOMMA-NEXT:    lxvpx vsp34, r3, r4 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NOMMA-NEXT:    stxvpx vsp34, r5, r4 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = getelementptr i8, i8* %0, i64 %offset
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = bitcast <256 x i1>* %vp2 to i8*
   %4 = getelementptr i8, i8* %3, i64 %offset
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }
 
 define void @test_ldst_3(<256 x i1>* %vpp, <256 x i1>* %vp2)  {
 ; CHECK-LABEL: test_ldst_3:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxvp vsp34, 18(r3), 0
-; CHECK-NEXT:    pstxvp vsp34, 18(r4), 0
+; CHECK-NEXT:    plxvp vsp34, 18(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    pstxvp vsp34, 18(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_3:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    plxvp vsp34, 18(r3), 0
-; CHECK-NOMMA-NEXT:    pstxvp vsp34, 18(r4), 0
+; CHECK-NOMMA-NEXT:    plxvp vsp34, 18(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NOMMA-NEXT:    pstxvp vsp34, 18(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_3:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    plxvp vsp34, 18(r3), 0
-; CHECK-BE-NEXT:    pstxvp vsp34, 18(r4), 0
+; CHECK-BE-NEXT:    plxvp vsp34, 18(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NEXT:    pstxvp vsp34, 18(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_3:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 18(r3), 0
-; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 18(r4), 0
+; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 18(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 18(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = getelementptr i8, i8* %0, i64 18
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = bitcast <256 x i1>* %vp2 to i8*
   %4 = getelementptr i8, i8* %3, i64 18
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }
 
 define void @test_ldst_4(<256 x i1>* %vpp, <256 x i1>* %vp2)  {
 ; CHECK-LABEL: test_ldst_4:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxvp vsp34, 1(r3), 0
-; CHECK-NEXT:    pstxvp vsp34, 1(r4), 0
+; CHECK-NEXT:    plxvp vsp34, 1(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    pstxvp vsp34, 1(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_4:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    plxvp vsp34, 1(r3), 0
-; CHECK-NOMMA-NEXT:    pstxvp vsp34, 1(r4), 0
+; CHECK-NOMMA-NEXT:    plxvp vsp34, 1(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NOMMA-NEXT:    pstxvp vsp34, 1(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_4:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    plxvp vsp34, 1(r3), 0
-; CHECK-BE-NEXT:    pstxvp vsp34, 1(r4), 0
+; CHECK-BE-NEXT:    plxvp vsp34, 1(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NEXT:    pstxvp vsp34, 1(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_4:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 1(r3), 0
-; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 1(r4), 0
+; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 1(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 1(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = getelementptr i8, i8* %0, i64 1
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = bitcast <256 x i1>* %vp2 to i8*
   %4 = getelementptr i8, i8* %3, i64 1
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }
 
 define void @test_ldst_5(<256 x i1>* %vpp, <256 x i1>* %vp2)  {
 ; CHECK-LABEL: test_ldst_5:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxvp vsp34, 42(r3), 0
-; CHECK-NEXT:    pstxvp vsp34, 42(r4), 0
+; CHECK-NEXT:    plxvp vsp34, 42(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    pstxvp vsp34, 42(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_5:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    plxvp vsp34, 42(r3), 0
-; CHECK-NOMMA-NEXT:    pstxvp vsp34, 42(r4), 0
+; CHECK-NOMMA-NEXT:    plxvp vsp34, 42(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NOMMA-NEXT:    pstxvp vsp34, 42(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_5:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    plxvp vsp34, 42(r3), 0
-; CHECK-BE-NEXT:    pstxvp vsp34, 42(r4), 0
+; CHECK-BE-NEXT:    plxvp vsp34, 42(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NEXT:    pstxvp vsp34, 42(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_5:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 42(r3), 0
-; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 42(r4), 0
+; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 42(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 42(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = getelementptr i8, i8* %0, i64 42
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = bitcast <256 x i1>* %vp2 to i8*
   %4 = getelementptr i8, i8* %3, i64 42
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }
 
 define void @test_ldst_6(<256 x i1>* %vpp, <256 x i1>* %vp2)  {
 ; CHECK-LABEL: test_ldst_6:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxvp vsp34, 4096(r3)
-; CHECK-NEXT:    stxvp vsp34, 4096(r4)
+; CHECK-NEXT:    lxvp vsp34, 4096(r3) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    stxvp vsp34, 4096(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_6:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    lxvp vsp34, 4096(r3)
-; CHECK-NOMMA-NEXT:    stxvp vsp34, 4096(r4)
+; CHECK-NOMMA-NEXT:    lxvp vsp34, 4096(r3) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NOMMA-NEXT:    stxvp vsp34, 4096(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_6:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxvp vsp34, 4096(r3)
-; CHECK-BE-NEXT:    stxvp vsp34, 4096(r4)
+; CHECK-BE-NEXT:    lxvp vsp34, 4096(r3) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NEXT:    stxvp vsp34, 4096(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_6:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    lxvp vsp34, 4096(r3)
-; CHECK-BE-NOMMA-NEXT:    stxvp vsp34, 4096(r4)
+; CHECK-BE-NOMMA-NEXT:    lxvp vsp34, 4096(r3) # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NOMMA-NEXT:    stxvp vsp34, 4096(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = getelementptr <256 x i1>, <256 x i1>* %vpp, i64 128
   %1 = bitcast <256 x i1>* %0 to i8*
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = getelementptr <256 x i1>, <256 x i1>* %vp2, i64 128
   %4 = bitcast <256 x i1>* %3 to i8*
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }
 
 define void @test_ldst_7(<256 x i1>* %vpp, <256 x i1>* %vp2)  {
 ; FIXME: A prefixed load (plxvp) is expected here as the offset in this
 ; test case is a constant that fits within 34-bits.
 ; CHECK-LABEL: test_ldst_7:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    plxvp vsp34, 32799(r3), 0
-; CHECK-NEXT:    pstxvp vsp34, 32799(r4), 0
+; CHECK-NEXT:    plxvp vsp34, 32799(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    pstxvp vsp34, 32799(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_7:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    plxvp vsp34, 32799(r3), 0
-; CHECK-NOMMA-NEXT:    pstxvp vsp34, 32799(r4), 0
+; CHECK-NOMMA-NEXT:    plxvp vsp34, 32799(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NOMMA-NEXT:    pstxvp vsp34, 32799(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_7:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    plxvp vsp34, 32799(r3), 0
-; CHECK-BE-NEXT:    pstxvp vsp34, 32799(r4), 0
+; CHECK-BE-NEXT:    plxvp vsp34, 32799(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NEXT:    pstxvp vsp34, 32799(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_7:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 32799(r3), 0
-; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 32799(r4), 0
+; CHECK-BE-NOMMA-NEXT:    plxvp vsp34, 32799(r3), 0 # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NOMMA-NEXT:    pstxvp vsp34, 32799(r4), 0 # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = getelementptr i8, i8* %0, i64 32799
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = bitcast <256 x i1>* %vp2 to i8*
   %4 = getelementptr i8, i8* %3, i64 32799
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }

llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll

 }
 
 ; Test with float/double/float128 for input parameter
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
 define i64 @setbf1(float %a, float %b) {
 ; CHECK-LABEL: setbf1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-NEXT:    setb r3, cr0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-PWR8-LABEL: setbf1:
 ; CHECK-PWR8:       # %bb.0:
-; CHECK-PWR8-NEXT:    fcmpu cr0, f2, f1
-; CHECK-PWR8-NEXT:    fcmpu cr1, f1, f2
+; CHECK-PWR8-NEXT:    fcmpu cr0, f2, f1 # Vec Uses: F2(VSR2)F1(VSR1)
+; CHECK-PWR8-NEXT:    fcmpu cr1, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-PWR8-NEXT:    li r3, 0
 ; CHECK-PWR8-NEXT:    li r4, 1
 ; CHECK-PWR8-NEXT:    isellt r3, r4, r3
 ; CHECK-PWR8-NEXT:    li r4, -1
 ; CHECK-PWR8-NEXT:    isel r3, r4, r3, 4*cr1+lt
 ; CHECK-PWR8-NEXT:    blr
   %t1 = fcmp nnan olt float %a, %b
   %t2 = fcmp nnan olt float %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt
 define i64 @setbf2(float %a, float %b) {
 ; CHECK-LABEL: setbf2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-NEXT:    setb r3, cr0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-PWR8-LABEL: setbf2:
 ; CHECK-PWR8:       # %bb.0:
-; CHECK-PWR8-NEXT:    fcmpu cr0, f2, f1
+; CHECK-PWR8-NEXT:    fcmpu cr0, f2, f1 # Vec Uses: F2(VSR2)F1(VSR1)
 ; CHECK-PWR8-NEXT:    li r3, 0
 ; CHECK-PWR8-NEXT:    li r4, 1
 ; CHECK-PWR8-NEXT:    isellt r3, r4, r3
 ; CHECK-PWR8-NEXT:    li r4, -1
 ; CHECK-PWR8-NEXT:    iselgt r3, r4, r3
 ; CHECK-PWR8-NEXT:    blr
   %t1 = fcmp nnan ogt float %b, %a
   %t2 = fcmp nnan olt float %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
 }
 
 ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setgt), seteq
 define i64 @setbdf1(double %a, double %b) {
 ; CHECK-LABEL: setbdf1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xscmpudp cr0, f1, f2
+; CHECK-NEXT:    xscmpudp cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-NEXT:    setb r3, cr0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-PWR8-LABEL: setbdf1:
 ; CHECK-PWR8:       # %bb.0:
-; CHECK-PWR8-NEXT:    xscmpudp cr0, f2, f1
+; CHECK-PWR8-NEXT:    xscmpudp cr0, f2, f1 # Vec Uses: F2(VSR2)F1(VSR1)
 ; CHECK-PWR8-NEXT:    li r3, 1
 ; CHECK-PWR8-NEXT:    li r4, -1
 ; CHECK-PWR8-NEXT:    iselgt r3, r4, r3
 ; CHECK-PWR8-NEXT:    iseleq r3, 0, r3
 ; CHECK-PWR8-NEXT:    blr
   %t1 = fcmp nnan oeq double %b, %a
   %t2 = fcmp nnan ogt double %b, %a
   %t3 = select i1 %t2, i64 -1, i64 1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setlt
 define i64 @setbdf2(double %a, double %b) {
 ; CHECK-LABEL: setbdf2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xscmpudp cr0, f1, f2
+; CHECK-NEXT:    xscmpudp cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-NEXT:    setb r3, cr0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-PWR8-LABEL: setbdf2:
 ; CHECK-PWR8:       # %bb.0:
-; CHECK-PWR8-NEXT:    fcmpu cr0, f2, f1
-; CHECK-PWR8-NEXT:    xscmpudp cr1, f2, f1
+; CHECK-PWR8-NEXT:    fcmpu cr0, f2, f1 # Vec Uses: F2(VSR2)F1(VSR1)
+; CHECK-PWR8-NEXT:    xscmpudp cr1, f2, f1 # Vec Uses: F2(VSR2)F1(VSR1)
 ; CHECK-PWR8-NEXT:    li r3, 0
 ; CHECK-PWR8-NEXT:    li r4, -1
 ; CHECK-PWR8-NEXT:    iselgt r3, r4, r3
 ; CHECK-PWR8-NEXT:    li r4, 1
 ; CHECK-PWR8-NEXT:    isel r3, r4, r3, 4*cr1+lt
 ; CHECK-PWR8-NEXT:    blr
   %t1 = fcmp nnan olt double %b, %a
   %t2 = fcmp nnan ogt double %b, %a
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
 }
 
 define i64 @setbf128(fp128 %a, fp128 %b) {
 ; CHECK-LABEL: setbf128:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3 # Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    setb r3, cr0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-PWR8-LABEL: setbf128:
 ; CHECK-PWR8:       # %bb.0:
 ; CHECK-PWR8-NEXT:    mflr r0
 ; CHECK-PWR8-NEXT:    std r0, 16(r1)
 ; CHECK-PWR8-NEXT:    stdu r1, -96(r1)
 ; CHECK-PWR8-NEXT:    .cfi_def_cfa_offset 96
 ; CHECK-PWR8-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR8-NEXT:    .cfi_offset r30, -16
 ; CHECK-PWR8-NEXT:    .cfi_offset v30, -48
 ; CHECK-PWR8-NEXT:    .cfi_offset v31, -32
 ; CHECK-PWR8-NEXT:    li r3, 48
 ; CHECK-PWR8-NEXT:    std r30, 80(r1) # 8-byte Folded Spill
 ; CHECK-PWR8-NEXT:    stvx v30, r1, r3 # 16-byte Folded Spill
+; CHECK-PWR8-NEXT:    # Vec Uses: V30(VSR62)
 ; CHECK-PWR8-NEXT:    li r3, 64
-; CHECK-PWR8-NEXT:    vmr v30, v2
+; CHECK-PWR8-NEXT:    vmr v30, v2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-PWR8-NEXT:    stvx v31, r1, r3 # 16-byte Folded Spill
-; CHECK-PWR8-NEXT:    vmr v31, v3
+; CHECK-PWR8-NEXT:    # Vec Uses: V31(VSR63)
+; CHECK-PWR8-NEXT:    vmr v31, v3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
 ; CHECK-PWR8-NEXT:    bl __ltkf2
 ; CHECK-PWR8-NEXT:    nop
-; CHECK-PWR8-NEXT:    vmr v2, v30
+; CHECK-PWR8-NEXT:    vmr v2, v30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; CHECK-PWR8-NEXT:    srawi r30, r3, 31
-; CHECK-PWR8-NEXT:    vmr v3, v31
+; CHECK-PWR8-NEXT:    vmr v3, v31 # Vec Defs: V3(VSR35) Vec Uses: V31(VSR63)V31(VSR63)
 ; CHECK-PWR8-NEXT:    bl __gtkf2
 ; CHECK-PWR8-NEXT:    nop
 ; CHECK-PWR8-NEXT:    li r4, 1
 ; CHECK-PWR8-NEXT:    cmpwi r3, 0
 ; CHECK-PWR8-NEXT:    iselgt r3, r4, r30
 ; CHECK-PWR8-NEXT:    li r4, 64
 ; CHECK-PWR8-NEXT:    ld r30, 80(r1) # 8-byte Folded Reload
 ; CHECK-PWR8-NEXT:    lvx v31, r1, r4 # 16-byte Folded Reload
+; CHECK-PWR8-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-PWR8-NEXT:    li r4, 48
 ; CHECK-PWR8-NEXT:    lvx v30, r1, r4 # 16-byte Folded Reload
+; CHECK-PWR8-NEXT:    # Vec Defs: V30(VSR62)
 ; CHECK-PWR8-NEXT:    addi r1, r1, 96
 ; CHECK-PWR8-NEXT:    ld r0, 16(r1)
 ; CHECK-PWR8-NEXT:    mtlr r0
 ; CHECK-PWR8-NEXT:    blr
   %t1 = fcmp nnan ogt fp128 %a, %b
   %t2 = fcmp nnan olt fp128 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
; CHECK-PWR8-NEXT:    blr
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
 }
 
 define i64 @setbn2(double %a, double %b) {
 ; CHECK-LABEL: setbn2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-NEXT:    li r3, 1
 ; CHECK-NEXT:    li r4, -1
 ; CHECK-NEXT:    cror 4*cr5+lt, un, eq
-; CHECK-NEXT:    xscmpudp cr0, f1, f2
+; CHECK-NEXT:    xscmpudp cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; CHECK-NEXT:    isellt r3, r4, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-PWR8-LABEL: setbn2:
 ; CHECK-PWR8:       # %bb.0:
-; CHECK-PWR8-NEXT:    fcmpu cr0, f1, f2
-; CHECK-PWR8-NEXT:    xscmpudp cr1, f1, f2
+; CHECK-PWR8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
+; CHECK-PWR8-NEXT:    xscmpudp cr1, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-PWR8-NEXT:    li r3, 1
 ; CHECK-PWR8-NEXT:    li r4, -1
 ; CHECK-PWR8-NEXT:    cror 4*cr5+lt, un, eq
 ; CHECK-PWR8-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; CHECK-PWR8-NEXT:    isel r3, r4, r3, 4*cr1+lt
 ; CHECK-PWR8-NEXT:    blr
   %t1 = fcmp olt double %a, %b
   %t2 = fcmp one double %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
 }
 
 define i64 @setbn3(float %a, float %b) {
 ; CHECK-LABEL: setbn3:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-NEXT:    li r3, 1
 ; CHECK-NEXT:    li r4, -1
 ; CHECK-NEXT:    iseleq r3, 0, r3
 ; CHECK-NEXT:    cror 4*cr5+lt, lt, un
 ; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-PWR8-LABEL: setbn3:
 ; CHECK-PWR8:       # %bb.0:
-; CHECK-PWR8-NEXT:    fcmpu cr0, f1, f2
+; CHECK-PWR8-NEXT:    fcmpu cr0, f1, f2 # Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-PWR8-NEXT:    li r3, 1
 ; CHECK-PWR8-NEXT:    li r4, -1
 ; CHECK-PWR8-NEXT:    cror 4*cr5+lt, lt, un
 ; CHECK-PWR8-NEXT:    iseleq r3, 0, r3
 ; CHECK-PWR8-NEXT:    isel r3, r4, r3, 4*cr5+lt
 ; CHECK-PWR8-NEXT:    blr
   %t1 = fcmp ult float %a, %b
   %t2 = fcmp une float %a, %b

llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
 ; RUN:    | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:     -ppc-track-subreg-liveness < %s | FileCheck %s --check-prefix=TRACKLIVE
 
 %0 = type <{ double }>
 %1 = type <{ double }>
 
 define void @acc_regalloc(i32* %arg, [0 x %0]* %arg1, [0 x %1]* %arg2) local_unnamed_addr {
 ; CHECK-LABEL: acc_regalloc:
 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    lxv v4, 0(0)
-; CHECK-NEXT:    xxlxor v0, v0, v0
-; CHECK-NEXT:    xxlxor v1, v1, v1
-; CHECK-NEXT:    xxlxor v2, v2, v2
+; CHECK-NEXT:    lxv v4, 0(0) # Vec Defs: V4(VSR36)
+; CHECK-NEXT:    xxlxor v0, v0, v0 # Vec Defs: V0(VSR32)
+; CHECK-NEXT:    xxlxor v1, v1, v1 # Vec Defs: V1(VSR33)
+; CHECK-NEXT:    xxlxor v2, v2, v2 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    li r6, 1
 ; CHECK-NEXT:    li r4, 16
 ; CHECK-NEXT:    stfd f14, -144(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F14(VSR14)
 ; CHECK-NEXT:    stfd f15, -136(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F15(VSR15)
 ; CHECK-NEXT:    extswsli r3, r3, 3
-; CHECK-NEXT:    xvmaddadp v1, v4, v1
-; CHECK-NEXT:    lxvdsx v5, 0, r3
-; CHECK-NEXT:    xvmaddadp v0, v5, v0
+; CHECK-NEXT:    xvmaddadp v1, v4, v1 # Vec Defs: V1(VSR33) Vec Uses: V1(VSR33)V4(VSR36)V1(VSR33)
+; CHECK-NEXT:    lxvdsx v5, 0, r3 # Vec Defs: V5(VSR37)
+; CHECK-NEXT:    xvmaddadp v0, v5, v0 # Vec Defs: V0(VSR32) Vec Uses: V0(VSR32)V5(VSR37)V0(VSR32)
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_1: # %bb9
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    addi r6, r6, 2
-; CHECK-NEXT:    lxv vs0, 16(0)
-; CHECK-NEXT:    lxv vs1, -64(r5)
-; CHECK-NEXT:    xxlxor v7, v7, v7
-; CHECK-NEXT:    vmr v9, v0
-; CHECK-NEXT:    xxlxor v10, v10, v10
+; CHECK-NEXT:    lxv vs0, 16(0) # Vec Defs: VSL0(VSR0)
+; CHECK-NEXT:    lxv vs1, -64(r5) # Vec Defs: VSL1(VSR1)
+; CHECK-NEXT:    xxlxor v7, v7, v7 # Vec Defs: V7(VSR39)
+; CHECK-NEXT:    vmr v9, v0 # Vec Defs: V9(VSR41) Vec Uses: V0(VSR32)V0(VSR32)
+; CHECK-NEXT:    xxlxor v10, v10, v10 # Vec Defs: V10(VSR42)
 ; CHECK-NEXT:    mulld r6, r6, r3
-; CHECK-NEXT:    xvmaddadp v7, vs0, v5
-; CHECK-NEXT:    xvmuldp v6, vs0, v2
-; CHECK-NEXT:    lxv vs0, -16(r5)
-; CHECK-NEXT:    xvmaddadp v9, vs1, v2
-; CHECK-NEXT:    xxlxor v8, v8, v8
-; CHECK-NEXT:    xvmaddadp v7, v2, v2
-; CHECK-NEXT:    xvmaddadp v6, v2, v2
-; CHECK-NEXT:    lxvdsx v14, r6, r4
+; CHECK-NEXT:    xvmaddadp v7, vs0, v5 # Vec Defs: V7(VSR39) Vec Uses: V7(VSR39)VSL0(VSR0)V5(VSR37)
+; CHECK-NEXT:    xvmuldp v6, vs0, v2 # Vec Defs: V6(VSR38) Vec Uses: VSL0(VSR0)V2(VSR34)
+; CHECK-NEXT:    lxv vs0, -16(r5) # Vec Defs: VSL0(VSR0)
+; CHECK-NEXT:    xvmaddadp v9, vs1, v2 # Vec Defs: V9(VSR41) Vec Uses: V9(VSR41)VSL1(VSR1)V2(VSR34)
+; CHECK-NEXT:    xxlxor v8, v8, v8 # Vec Defs: V8(VSR40)
+; CHECK-NEXT:    xvmaddadp v7, v2, v2 # Vec Defs: V7(VSR39) Vec Uses: V7(VSR39)V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    xvmaddadp v6, v2, v2 # Vec Defs: V6(VSR38) Vec Uses: V6(VSR38)V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    lxvdsx v14, r6, r4 # Vec Defs: V14(VSR46)
 ; CHECK-NEXT:    li r6, 0
-; CHECK-NEXT:    xvmaddadp v8, vs1, v8
-; CHECK-NEXT:    xvmaddadp v10, vs0, v10
-; CHECK-NEXT:    xvmuldp v3, vs1, v14
-; CHECK-NEXT:    xvmuldp v11, vs0, v14
-; CHECK-NEXT:    xvmuldp vs5, v14, v2
-; CHECK-NEXT:    xvmuldp v13, v4, v14
-; CHECK-NEXT:    xxlor vs0, v2, v2
-; CHECK-NEXT:    vmr v12, v2
-; CHECK-NEXT:    xxlor vs14, v10, v10
-; CHECK-NEXT:    xxlor vs4, v2, v2
+; CHECK-NEXT:    xvmaddadp v8, vs1, v8 # Vec Defs: V8(VSR40) Vec Uses: V8(VSR40)VSL1(VSR1)V8(VSR40)
+; CHECK-NEXT:    xvmaddadp v10, vs0, v10 # Vec Defs: V10(VSR42) Vec Uses: V10(VSR42)VSL0(VSR0)V10(VSR42)
+; CHECK-NEXT:    xvmuldp v3, vs1, v14 # Vec Defs: V3(VSR35) Vec Uses: VSL1(VSR1)V14(VSR46)
+; CHECK-NEXT:    xvmuldp v11, vs0, v14 # Vec Defs: V11(VSR43) Vec Uses: VSL0(VSR0)V14(VSR46)
+; CHECK-NEXT:    xvmuldp vs5, v14, v2 # Vec Defs: VSL5(VSR5) Vec Uses: V14(VSR46)V2(VSR34)
+; CHECK-NEXT:    xvmuldp v13, v4, v14 # Vec Defs: V13(VSR45) Vec Uses: V4(VSR36)V14(VSR46)
+; CHECK-NEXT:    xxlor vs0, v2, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    vmr v12, v2 # Vec Defs: V12(VSR44) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    xxlor vs14, v10, v10 # Vec Defs: VSL14(VSR14) Vec Uses: V10(VSR42)V10(VSR42)
+; CHECK-NEXT:    xxlor vs4, v2, v2 # Vec Defs: VSL4(VSR4) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    # kill: def $vsrp2 killed $vsrp2 def $uacc1
-; CHECK-NEXT:    xxlor vs6, v6, v6
-; CHECK-NEXT:    xxlor vs7, v7, v7
-; CHECK-NEXT:    xxlor vs8, v12, v12
-; CHECK-NEXT:    xxlor vs9, v13, v13
-; CHECK-NEXT:    vmr v12, v1
-; CHECK-NEXT:    xxlor vs1, v3, v3
-; CHECK-NEXT:    xxlor vs2, v8, v8
-; CHECK-NEXT:    xxlor vs3, v9, v9
-; CHECK-NEXT:    xxlor vs15, v11, v11
-; CHECK-NEXT:    vmr v10, v2
-; CHECK-NEXT:    xxlor vs10, v12, v12
-; CHECK-NEXT:    xxlor vs11, v13, v13
-; CHECK-NEXT:    xxmtacc acc1
-; CHECK-NEXT:    xxlor vs12, v10, v10
-; CHECK-NEXT:    xxlor vs13, v11, v11
-; CHECK-NEXT:    xxmtacc acc0
-; CHECK-NEXT:    xxmtacc acc2
-; CHECK-NEXT:    xxmtacc acc3
-; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; CHECK-NEXT:    xxmfacc acc0
-; CHECK-NEXT:    xxmfacc acc1
-; CHECK-NEXT:    xxmfacc acc2
-; CHECK-NEXT:    xxmfacc acc3
-; CHECK-NEXT:    stxv vs1, 0(r3)
-; CHECK-NEXT:    stxv vs9, 32(r3)
-; CHECK-NEXT:    stxv vs4, 16(0)
-; CHECK-NEXT:    stxv vs12, 48(0)
+; CHECK-NEXT:    xxlor vs6, v6, v6 # Vec Defs: VSL6(VSR6) Vec Uses: V6(VSR38)V6(VSR38)
+; CHECK-NEXT:    xxlor vs7, v7, v7 # Vec Defs: VSL7(VSR7) Vec Uses: V7(VSR39)V7(VSR39)
+; CHECK-NEXT:    xxlor vs8, v12, v12 # Vec Defs: VSL8(VSR8) Vec Uses: V12(VSR44)V12(VSR44)
+; CHECK-NEXT:    xxlor vs9, v13, v13 # Vec Defs: VSL9(VSR9) Vec Uses: V13(VSR45)V13(VSR45)
+; CHECK-NEXT:    vmr v12, v1 # Vec Defs: V12(VSR44) Vec Uses: V1(VSR33)V1(VSR33)
+; CHECK-NEXT:    xxlor vs1, v3, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-NEXT:    xxlor vs2, v8, v8 # Vec Defs: VSL2(VSR2) Vec Uses: V8(VSR40)V8(VSR40)
+; CHECK-NEXT:    xxlor vs3, v9, v9 # Vec Defs: VSL3(VSR3) Vec Uses: V9(VSR41)V9(VSR41)
+; CHECK-NEXT:    xxlor vs15, v11, v11 # Vec Defs: VSL15(VSR15) Vec Uses: V11(VSR43)V11(VSR43)
+; CHECK-NEXT:    vmr v10, v2 # Vec Defs: V10(VSR42) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    xxlor vs10, v12, v12 # Vec Defs: VSL10(VSR10) Vec Uses: V12(VSR44)V12(VSR44)
+; CHECK-NEXT:    xxlor vs11, v13, v13 # Vec Defs: VSL11(VSR11) Vec Uses: V13(VSR45)V13(VSR45)
+; CHECK-NEXT:    xxmtacc acc1 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)
+; CHECK-NEXT:    xxlor vs12, v10, v10 # Vec Defs: VSL12(VSR12) Vec Uses: V10(VSR42)V10(VSR42)
+; CHECK-NEXT:    xxlor vs13, v11, v11 # Vec Defs: VSL13(VSR13) Vec Uses: V11(VSR43)V11(VSR43)
+; CHECK-NEXT:    xxmtacc acc0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)
+; CHECK-NEXT:    xxmtacc acc2 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)
+; CHECK-NEXT:    xxmtacc acc3 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; CHECK-NEXT:    xxmfacc acc0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)
+; CHECK-NEXT:    xxmfacc acc1 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)
+; CHECK-NEXT:    xxmfacc acc2 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)
+; CHECK-NEXT:    xxmfacc acc3 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)
+; CHECK-NEXT:    stxv vs1, 0(r3) # Vec Uses: VSL1(VSR1)
+; CHECK-NEXT:    stxv vs9, 32(r3) # Vec Uses: VSL9(VSR9)
+; CHECK-NEXT:    stxv vs4, 16(0) # Vec Uses: VSL4(VSR4)
+; CHECK-NEXT:    stxv vs12, 48(0) # Vec Uses: VSL12(VSR12)
 ; CHECK-NEXT:    b .LBB0_1
 ;
 ; TRACKLIVE-LABEL: acc_regalloc:
 ; TRACKLIVE:       # %bb.0: # %bb
 ; TRACKLIVE-NEXT:    lwz r3, 0(r3)
-; TRACKLIVE-NEXT:    lxv v4, 0(0)
-; TRACKLIVE-NEXT:    xxlxor v0, v0, v0
-; TRACKLIVE-NEXT:    xxlxor v1, v1, v1
-; TRACKLIVE-NEXT:    xxlxor v2, v2, v2
+; TRACKLIVE-NEXT:    lxv v4, 0(0) # Vec Defs: V4(VSR36)
+; TRACKLIVE-NEXT:    xxlxor v0, v0, v0 # Vec Defs: V0(VSR32)
+; TRACKLIVE-NEXT:    xxlxor v1, v1, v1 # Vec Defs: V1(VSR33)
+; TRACKLIVE-NEXT:    xxlxor v2, v2, v2 # Vec Defs: V2(VSR34)
 ; TRACKLIVE-NEXT:    li r6, 1
 ; TRACKLIVE-NEXT:    li r4, 16
 ; TRACKLIVE-NEXT:    stfd f14, -144(r1) # 8-byte Folded Spill
+; TRACKLIVE-NEXT:    # Vec Uses: F14(VSR14)
 ; TRACKLIVE-NEXT:    stfd f15, -136(r1) # 8-byte Folded Spill
+; TRACKLIVE-NEXT:    # Vec Uses: F15(VSR15)
 ; TRACKLIVE-NEXT:    extswsli r3, r3, 3
-; TRACKLIVE-NEXT:    xvmaddadp v1, v4, v1
-; TRACKLIVE-NEXT:    lxvdsx v5, 0, r3
-; TRACKLIVE-NEXT:    xvmaddadp v0, v5, v0
+; TRACKLIVE-NEXT:    xvmaddadp v1, v4, v1 # Vec Defs: V1(VSR33) Vec Uses: V1(VSR33)V4(VSR36)V1(VSR33)
+; TRACKLIVE-NEXT:    lxvdsx v5, 0, r3 # Vec Defs: V5(VSR37)
+; TRACKLIVE-NEXT:    xvmaddadp v0, v5, v0 # Vec Defs: V0(VSR32) Vec Uses: V0(VSR32)V5(VSR37)V0(VSR32)
 ; TRACKLIVE-NEXT:    .p2align 4
 ; TRACKLIVE-NEXT:  .LBB0_1: # %bb9
 ; TRACKLIVE-NEXT:    #
 ; TRACKLIVE-NEXT:    addi r6, r6, 2
-; TRACKLIVE-NEXT:    lxv vs0, 16(0)
-; TRACKLIVE-NEXT:    lxv vs1, -64(r5)
-; TRACKLIVE-NEXT:    xxlxor vs7, vs7, vs7
-; TRACKLIVE-NEXT:    xxlor vs3, v0, v0
-; TRACKLIVE-NEXT:    xxlxor vs2, vs2, vs2
-; TRACKLIVE-NEXT:    xxlxor vs12, vs12, vs12
+; TRACKLIVE-NEXT:    lxv vs0, 16(0) # Vec Defs: VSL0(VSR0)
+; TRACKLIVE-NEXT:    lxv vs1, -64(r5) # Vec Defs: VSL1(VSR1)
+; TRACKLIVE-NEXT:    xxlxor vs7, vs7, vs7 # Vec Defs: VSL7(VSR7)
+; TRACKLIVE-NEXT:    xxlor vs3, v0, v0 # Vec Defs: VSL3(VSR3) Vec Uses: V0(VSR32)V0(VSR32)
+; TRACKLIVE-NEXT:    xxlxor vs2, vs2, vs2 # Vec Defs: VSL2(VSR2)
+; TRACKLIVE-NEXT:    xxlxor vs12, vs12, vs12 # Vec Defs: VSL12(VSR12)
 ; TRACKLIVE-NEXT:    mulld r6, r6, r3
-; TRACKLIVE-NEXT:    xxlor vs10, v2, v2
-; TRACKLIVE-NEXT:    xxlor vs4, v2, v2
-; TRACKLIVE-NEXT:    xxlor vs8, vs10, vs10
-; TRACKLIVE-NEXT:    xxlor vs10, v1, v1
-; TRACKLIVE-NEXT:    xvmaddadp vs7, vs0, v5
-; TRACKLIVE-NEXT:    xvmuldp vs6, vs0, v2
-; TRACKLIVE-NEXT:    lxv vs0, -16(r5)
-; TRACKLIVE-NEXT:    xvmaddadp vs3, vs1, v2
-; TRACKLIVE-NEXT:    xvmaddadp vs2, vs1, vs2
-; TRACKLIVE-NEXT:    lxvdsx v6, r6, r4
+; TRACKLIVE-NEXT:    xxlor vs10, v2, v2 # Vec Defs: VSL10(VSR10) Vec Uses: V2(VSR34)V2(VSR34)
+; TRACKLIVE-NEXT:    xxlor vs4, v2, v2 # Vec Defs: VSL4(VSR4) Vec Uses: V2(VSR34)V2(VSR34)
+; TRACKLIVE-NEXT:    xxlor vs8, vs10, vs10 # Vec Defs: VSL8(VSR8) Vec Uses: VSL10(VSR10)VSL10(VSR10)
+; TRACKLIVE-NEXT:    xxlor vs10, v1, v1 # Vec Defs: VSL10(VSR10) Vec Uses: V1(VSR33)V1(VSR33)
+; TRACKLIVE-NEXT:    xvmaddadp vs7, vs0, v5 # Vec Defs: VSL7(VSR7) Vec Uses: VSL7(VSR7)VSL0(VSR0)V5(VSR37)
+; TRACKLIVE-NEXT:    xvmuldp vs6, vs0, v2 # Vec Defs: VSL6(VSR6) Vec Uses: VSL0(VSR0)V2(VSR34)
+; TRACKLIVE-NEXT:    lxv vs0, -16(r5) # Vec Defs: VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvmaddadp vs3, vs1, v2 # Vec Defs: VSL3(VSR3) Vec Uses: VSL3(VSR3)VSL1(VSR1)V2(VSR34)
+; TRACKLIVE-NEXT:    xvmaddadp vs2, vs1, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL2(VSR2)VSL1(VSR1)VSL2(VSR2)
+; TRACKLIVE-NEXT:    lxvdsx v6, r6, r4 # Vec Defs: V6(VSR38)
 ; TRACKLIVE-NEXT:    li r6, 0
-; TRACKLIVE-NEXT:    xvmaddadp vs7, v2, v2
-; TRACKLIVE-NEXT:    xvmaddadp vs6, v2, v2
-; TRACKLIVE-NEXT:    xvmaddadp vs12, vs0, vs12
-; TRACKLIVE-NEXT:    xvmuldp v3, vs1, v6
-; TRACKLIVE-NEXT:    xvmuldp vs11, v4, v6
-; TRACKLIVE-NEXT:    xvmuldp vs13, vs0, v6
-; TRACKLIVE-NEXT:    xvmuldp vs5, v6, v2
-; TRACKLIVE-NEXT:    xxlor vs0, v2, v2
-; TRACKLIVE-NEXT:    xxlor vs14, vs12, vs12
-; TRACKLIVE-NEXT:    xxlor vs12, v2, v2
-; TRACKLIVE-NEXT:    xxlor vs1, v3, v3
-; TRACKLIVE-NEXT:    xxlor vs9, vs11, vs11
-; TRACKLIVE-NEXT:    xxlor vs15, vs13, vs13
-; TRACKLIVE-NEXT:    xxmtacc acc1
-; TRACKLIVE-NEXT:    xxmtacc acc0
-; TRACKLIVE-NEXT:    xxmtacc acc2
-; TRACKLIVE-NEXT:    xxmtacc acc3
-; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0
-; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0
-; TRACKLIVE-NEXT:    xxmfacc acc0
-; TRACKLIVE-NEXT:    xxmfacc acc1
-; TRACKLIVE-NEXT:    xxmfacc acc2
-; TRACKLIVE-NEXT:    xxmfacc acc3
-; TRACKLIVE-NEXT:    stxv vs1, 0(r3)
-; TRACKLIVE-NEXT:    stxv vs9, 32(r3)
-; TRACKLIVE-NEXT:    stxv vs4, 16(0)
-; TRACKLIVE-NEXT:    stxv vs12, 48(0)
+; TRACKLIVE-NEXT:    xvmaddadp vs7, v2, v2 # Vec Defs: VSL7(VSR7) Vec Uses: VSL7(VSR7)V2(VSR34)V2(VSR34)
+; TRACKLIVE-NEXT:    xvmaddadp vs6, v2, v2 # Vec Defs: VSL6(VSR6) Vec Uses: VSL6(VSR6)V2(VSR34)V2(VSR34)
+; TRACKLIVE-NEXT:    xvmaddadp vs12, vs0, vs12 # Vec Defs: VSL12(VSR12) Vec Uses: VSL12(VSR12)VSL0(VSR0)VSL12(VSR12)
+; TRACKLIVE-NEXT:    xvmuldp v3, vs1, v6 # Vec Defs: V3(VSR35) Vec Uses: VSL1(VSR1)V6(VSR38)
+; TRACKLIVE-NEXT:    xvmuldp vs11, v4, v6 # Vec Defs: VSL11(VSR11) Vec Uses: V4(VSR36)V6(VSR38)
+; TRACKLIVE-NEXT:    xvmuldp vs13, vs0, v6 # Vec Defs: VSL13(VSR13) Vec Uses: VSL0(VSR0)V6(VSR38)
+; TRACKLIVE-NEXT:    xvmuldp vs5, v6, v2 # Vec Defs: VSL5(VSR5) Vec Uses: V6(VSR38)V2(VSR34)
+; TRACKLIVE-NEXT:    xxlor vs0, v2, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; TRACKLIVE-NEXT:    xxlor vs14, vs12, vs12 # Vec Defs: VSL14(VSR14) Vec Uses: VSL12(VSR12)VSL12(VSR12)
+; TRACKLIVE-NEXT:    xxlor vs12, v2, v2 # Vec Defs: VSL12(VSR12) Vec Uses: V2(VSR34)V2(VSR34)
+; TRACKLIVE-NEXT:    xxlor vs1, v3, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; TRACKLIVE-NEXT:    xxlor vs9, vs11, vs11 # Vec Defs: VSL9(VSR9) Vec Uses: VSL11(VSR11)VSL11(VSR11)
+; TRACKLIVE-NEXT:    xxlor vs15, vs13, vs13 # Vec Defs: VSL15(VSR15) Vec Uses: VSL13(VSR13)VSL13(VSR13)
+; TRACKLIVE-NEXT:    xxmtacc acc1 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)
+; TRACKLIVE-NEXT:    xxmtacc acc0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)
+; TRACKLIVE-NEXT:    xxmtacc acc2 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)
+; TRACKLIVE-NEXT:    xxmtacc acc3 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)
+; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc0, vsp34, vs0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc1, vsp34, vs0 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc2, vsp34, vs0 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xvf64gerpp acc3, vsp34, vs0 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)VSRp17(VSR34,VSR35)VSL0(VSR0)
+; TRACKLIVE-NEXT:    xxmfacc acc0 # Vec Defs: ACC0(VSR0,VSR1,VSR2,VSR3) Vec Uses: ACC0(VSR0,VSR1,VSR2,VSR3)
+; TRACKLIVE-NEXT:    xxmfacc acc1 # Vec Defs: ACC1(VSR4,VSR5,VSR6,VSR7) Vec Uses: ACC1(VSR4,VSR5,VSR6,VSR7)
+; TRACKLIVE-NEXT:    xxmfacc acc2 # Vec Defs: ACC2(VSR8,VSR9,VSR10,VSR11) Vec Uses: ACC2(VSR8,VSR9,VSR10,VSR11)
+; TRACKLIVE-NEXT:    xxmfacc acc3 # Vec Defs: ACC3(VSR12,VSR13,VSR14,VSR15) Vec Uses: ACC3(VSR12,VSR13,VSR14,VSR15)
+; TRACKLIVE-NEXT:    stxv vs1, 0(r3) # Vec Uses: VSL1(VSR1)
+; TRACKLIVE-NEXT:    stxv vs9, 32(r3) # Vec Uses: VSL9(VSR9)
+; TRACKLIVE-NEXT:    stxv vs4, 16(0) # Vec Uses: VSL4(VSR4)
+; TRACKLIVE-NEXT:    stxv vs12, 48(0) # Vec Uses: VSL12(VSR12)
 ; TRACKLIVE-NEXT:    b .LBB0_1
 bb:
   %i = load i32, i32* %arg, align 4
   %i3 = sext i32 %i to i64
   %i4 = shl nsw i64 %i3, 3
   %i5 = bitcast [0 x %0]* %arg1 to i8*
   %i6 = getelementptr i8, i8* %i5, i64 undef
   %i7 = getelementptr [0 x %1], [0 x %1]* %arg2, i64 0, i64 -8

llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll

 ; BE-P10-NEXT:    std r25, 424(r1) # 8-byte Folded Spill
 ; BE-P10-NEXT:    std r26, 432(r1) # 8-byte Folded Spill
 ; BE-P10-NEXT:    std r27, 440(r1) # 8-byte Folded Spill
 ; BE-P10-NEXT:    std r28, 448(r1) # 8-byte Folded Spill
 ; BE-P10-NEXT:    std r29, 456(r1) # 8-byte Folded Spill
 ; BE-P10-NEXT:    std r30, 464(r1) # 8-byte Folded Spill
 ; BE-P10-NEXT:    std r31, 472(r1) # 8-byte Folded Spill
 ; BE-P10-NEXT:    stfd f14, 480(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-P10-NEXT:    stfd f15, 488(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-P10-NEXT:    stfd f16, 496(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-P10-NEXT:    stfd f17, 504(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-P10-NEXT:    stfd f18, 512(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-P10-NEXT:    stfd f19, 520(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-P10-NEXT:    stfd f20, 528(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-P10-NEXT:    stfd f21, 536(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-P10-NEXT:    stfd f22, 544(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-P10-NEXT:    stfd f23, 552(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-P10-NEXT:    stfd f24, 560(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-P10-NEXT:    stfd f25, 568(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-P10-NEXT:    stfd f26, 576(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-P10-NEXT:    stfd f27, 584(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-P10-NEXT:    stfd f28, 592(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-P10-NEXT:    stfd f29, 600(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-P10-NEXT:    stfd f30, 608(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-P10-NEXT:    stfd f31, 616(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-P10-NEXT:    stxv v20, 144(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-P10-NEXT:    stxv v21, 160(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-P10-NEXT:    stxv v22, 176(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-P10-NEXT:    stxv v23, 192(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-P10-NEXT:    stxv v24, 208(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-P10-NEXT:    stxv v25, 224(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-P10-NEXT:    stxv v26, 240(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-P10-NEXT:    stxv v27, 256(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-P10-NEXT:    stxv v28, 272(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-P10-NEXT:    stxv v29, 288(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-P10-NEXT:    stxv v30, 304(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-P10-NEXT:    stxv v31, 320(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-P10-NEXT:    std r3, 120(r1) # 8-byte Folded Spill
 ; BE-P10-NEXT:    stw r4, 132(r1)
 ; BE-P10-NEXT:    #APP
 ; BE-P10-NEXT:    nop
 ; BE-P10-NEXT:    #NO_APP
 ; BE-P10-NEXT:    addi r3, r1, 132
 ; BE-P10-NEXT:    bl .callee2[PR]
 ; BE-P10-NEXT:    nop
 ; BE-P10-NEXT:    ld r4, 120(r1) # 8-byte Folded Reload
 ; BE-P10-NEXT:    lxv v31, 320(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-P10-NEXT:    lxv v30, 304(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-P10-NEXT:    lxv v29, 288(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-P10-NEXT:    lxv v28, 272(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-P10-NEXT:    lxv v27, 256(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-P10-NEXT:    lxv v26, 240(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-P10-NEXT:    lxv v25, 224(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-P10-NEXT:    lxv v24, 208(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-P10-NEXT:    lxv v23, 192(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-P10-NEXT:    lxv v22, 176(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-P10-NEXT:    lxv v21, 160(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-P10-NEXT:    lxv v20, 144(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-P10-NEXT:    lfd f31, 616(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-P10-NEXT:    lfd f30, 608(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-P10-NEXT:    lfd f29, 600(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-P10-NEXT:    lfd f28, 592(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-P10-NEXT:    lfd f27, 584(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-P10-NEXT:    lfd f26, 576(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-P10-NEXT:    lfd f25, 568(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-P10-NEXT:    lfd f24, 560(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-P10-NEXT:    lfd f23, 552(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-P10-NEXT:    lfd f22, 544(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-P10-NEXT:    lfd f21, 536(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-P10-NEXT:    lfd f20, 528(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-P10-NEXT:    lfd f19, 520(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-P10-NEXT:    lfd f18, 512(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-P10-NEXT:    lfd f17, 504(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-P10-NEXT:    lfd f16, 496(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-P10-NEXT:    lfd f15, 488(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-P10-NEXT:    lfd f14, 480(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-P10-NEXT:    ld r31, 472(r1) # 8-byte Folded Reload
 ; BE-P10-NEXT:    ld r30, 464(r1) # 8-byte Folded Reload
 ; BE-P10-NEXT:    ld r29, 456(r1) # 8-byte Folded Reload
 ; BE-P10-NEXT:    ld r28, 448(r1) # 8-byte Folded Reload
 ; BE-P10-NEXT:    ld r27, 440(r1) # 8-byte Folded Reload
 ; BE-P10-NEXT:    ld r26, 432(r1) # 8-byte Folded Reload
 ; BE-P10-NEXT:    ld r25, 424(r1) # 8-byte Folded Reload
 ; BE-P10-NEXT:    ld r24, 416(r1) # 8-byte Folded Reload

 ; BE-P9-NEXT:    std r0, 16(r1)
 ; BE-P9-NEXT:    hashst r0, -488(r1)
 ; BE-P9-NEXT:    stw r12, 8(r1)
 ; BE-P9-NEXT:    stdu r1, -624(r1)
 ; BE-P9-NEXT:    lwz r4, 12(r3)
 ; BE-P9-NEXT:    std r14, 336(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    std r15, 344(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v20, 144(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-P9-NEXT:    stxv v21, 160(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-P9-NEXT:    stxv v22, 176(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-P9-NEXT:    std r16, 352(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    std r17, 360(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v23, 192(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-P9-NEXT:    std r18, 368(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v24, 208(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-P9-NEXT:    std r19, 376(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v25, 224(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-P9-NEXT:    std r20, 384(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    std r21, 392(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v26, 240(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-P9-NEXT:    std r22, 400(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v27, 256(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-P9-NEXT:    std r23, 408(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v28, 272(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-P9-NEXT:    std r24, 416(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    std r25, 424(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v29, 288(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-P9-NEXT:    std r26, 432(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v30, 304(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-P9-NEXT:    std r27, 440(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v31, 320(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-P9-NEXT:    std r28, 448(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    std r29, 456(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    std r30, 464(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    std r31, 472(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stfd f14, 480(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-P9-NEXT:    stfd f15, 488(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-P9-NEXT:    stfd f16, 496(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-P9-NEXT:    stfd f17, 504(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-P9-NEXT:    stfd f18, 512(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-P9-NEXT:    stfd f19, 520(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-P9-NEXT:    stfd f20, 528(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-P9-NEXT:    stfd f21, 536(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-P9-NEXT:    stfd f22, 544(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-P9-NEXT:    stfd f23, 552(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-P9-NEXT:    stfd f24, 560(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-P9-NEXT:    stfd f25, 568(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-P9-NEXT:    stfd f26, 576(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-P9-NEXT:    stfd f27, 584(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-P9-NEXT:    stfd f28, 592(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-P9-NEXT:    stfd f29, 600(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-P9-NEXT:    stfd f30, 608(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-P9-NEXT:    stfd f31, 616(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-P9-NEXT:    std r3, 120(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stw r4, 132(r1)
 ; BE-P9-NEXT:    #APP
 ; BE-P9-NEXT:    nop
 ; BE-P9-NEXT:    #NO_APP
 ; BE-P9-NEXT:    addi r3, r1, 132
 ; BE-P9-NEXT:    bl .callee2[PR]
 ; BE-P9-NEXT:    nop
 ; BE-P9-NEXT:    ld r4, 120(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    lxv v31, 320(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-P9-NEXT:    lxv v30, 304(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-P9-NEXT:    lxv v29, 288(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-P9-NEXT:    lxv v28, 272(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-P9-NEXT:    lxv v27, 256(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-P9-NEXT:    lxv v26, 240(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-P9-NEXT:    lxv v25, 224(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-P9-NEXT:    lxv v24, 208(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-P9-NEXT:    lxv v23, 192(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-P9-NEXT:    lxv v22, 176(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-P9-NEXT:    lxv v21, 160(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-P9-NEXT:    lxv v20, 144(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-P9-NEXT:    lfd f31, 616(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-P9-NEXT:    lfd f30, 608(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-P9-NEXT:    lfd f29, 600(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-P9-NEXT:    lfd f28, 592(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-P9-NEXT:    lfd f27, 584(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-P9-NEXT:    ld r31, 472(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r30, 464(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r29, 456(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    lfd f26, 576(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-P9-NEXT:    ld r28, 448(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r27, 440(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r26, 432(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    lfd f25, 568(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-P9-NEXT:    ld r25, 424(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r24, 416(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r23, 408(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    lfd f24, 560(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-P9-NEXT:    ld r22, 400(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r21, 392(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    lwz r4, 16(r4)
 ; BE-P9-NEXT:    add r3, r4, r3
 ; BE-P9-NEXT:    lfd f23, 552(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-P9-NEXT:    lfd f22, 544(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-P9-NEXT:    ld r20, 384(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r19, 376(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r18, 368(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r17, 360(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r16, 352(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r15, 344(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r14, 336(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    lfd f21, 536(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-P9-NEXT:    lfd f20, 528(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-P9-NEXT:    lfd f19, 520(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-P9-NEXT:    lfd f18, 512(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-P9-NEXT:    lfd f17, 504(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-P9-NEXT:    lfd f16, 496(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-P9-NEXT:    lfd f15, 488(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-P9-NEXT:    lfd f14, 480(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-P9-NEXT:    clrldi r3, r3, 32
 ; BE-P9-NEXT:    addi r1, r1, 624
 ; BE-P9-NEXT:    ld r0, 16(r1)
 ; BE-P9-NEXT:    lwz r12, 8(r1)
 ; BE-P9-NEXT:    mtlr r0
 ; BE-P9-NEXT:    hashchk r0, -488(r1)
 ; BE-P9-NEXT:    mtocrf 32, r12
 ; BE-P9-NEXT:    mtocrf 16, r12

 ; BE-P8-NEXT:    stw r12, 8(r1)
 ; BE-P8-NEXT:    stdu r1, -624(r1)
 ; BE-P8-NEXT:    li r4, 144
 ; BE-P8-NEXT:    std r14, 336(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r15, 344(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r16, 352(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r17, 360(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    stxvd2x v20, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-P8-NEXT:    li r4, 160
 ; BE-P8-NEXT:    std r18, 368(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r19, 376(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r20, 384(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r21, 392(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    stxvd2x v21, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-P8-NEXT:    li r4, 176
 ; BE-P8-NEXT:    std r22, 400(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r23, 408(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r24, 416(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r25, 424(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r26, 432(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r27, 440(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r28, 448(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r29, 456(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r30, 464(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r31, 472(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r3, 120(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    stxvd2x v22, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-P8-NEXT:    li r4, 192
 ; BE-P8-NEXT:    stxvd2x v23, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-P8-NEXT:    li r4, 208
 ; BE-P8-NEXT:    stfd f14, 480(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-P8-NEXT:    stxvd2x v24, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-P8-NEXT:    li r4, 224
 ; BE-P8-NEXT:    stfd f15, 488(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-P8-NEXT:    stxvd2x v25, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-P8-NEXT:    li r4, 240
 ; BE-P8-NEXT:    stfd f16, 496(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-P8-NEXT:    stxvd2x v26, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-P8-NEXT:    li r4, 256
 ; BE-P8-NEXT:    stfd f17, 504(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-P8-NEXT:    stxvd2x v27, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-P8-NEXT:    li r4, 272
 ; BE-P8-NEXT:    stfd f18, 512(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-P8-NEXT:    stxvd2x v28, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-P8-NEXT:    li r4, 288
 ; BE-P8-NEXT:    stfd f19, 520(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-P8-NEXT:    stxvd2x v29, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-P8-NEXT:    li r4, 304
 ; BE-P8-NEXT:    stfd f20, 528(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-P8-NEXT:    stxvd2x v30, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-P8-NEXT:    li r4, 320
 ; BE-P8-NEXT:    stfd f21, 536(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-P8-NEXT:    stxvd2x v31, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-P8-NEXT:    lwz r4, 12(r3)
 ; BE-P8-NEXT:    stfd f22, 544(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-P8-NEXT:    stfd f23, 552(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-P8-NEXT:    stfd f24, 560(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-P8-NEXT:    stfd f25, 568(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-P8-NEXT:    stfd f26, 576(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-P8-NEXT:    stfd f27, 584(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-P8-NEXT:    stfd f28, 592(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-P8-NEXT:    stfd f29, 600(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-P8-NEXT:    stfd f30, 608(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-P8-NEXT:    stfd f31, 616(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-P8-NEXT:    stw r4, 132(r1)
 ; BE-P8-NEXT:    #APP
 ; BE-P8-NEXT:    nop
 ; BE-P8-NEXT:    #NO_APP
 ; BE-P8-NEXT:    addi r3, r1, 132
 ; BE-P8-NEXT:    bl .callee2[PR]
 ; BE-P8-NEXT:    nop
 ; BE-P8-NEXT:    ld r4, 120(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lfd f31, 616(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-P8-NEXT:    lfd f30, 608(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-P8-NEXT:    ld r31, 472(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lfd f29, 600(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-P8-NEXT:    lfd f28, 592(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-P8-NEXT:    ld r30, 464(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    ld r29, 456(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lwz r4, 16(r4)
 ; BE-P8-NEXT:    lfd f27, 584(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-P8-NEXT:    lfd f26, 576(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-P8-NEXT:    ld r28, 448(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lfd f25, 568(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-P8-NEXT:    lfd f24, 560(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-P8-NEXT:    ld r27, 440(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    ld r26, 432(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    add r3, r4, r3
 ; BE-P8-NEXT:    li r4, 320
 ; BE-P8-NEXT:    lfd f23, 552(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-P8-NEXT:    lfd f22, 544(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-P8-NEXT:    ld r25, 424(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    ld r24, 416(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lxvd2x v31, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-P8-NEXT:    li r4, 304
 ; BE-P8-NEXT:    lfd f21, 536(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-P8-NEXT:    ld r23, 408(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    ld r22, 400(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    clrldi r3, r3, 32
 ; BE-P8-NEXT:    lxvd2x v30, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-P8-NEXT:    li r4, 288
 ; BE-P8-NEXT:    lfd f20, 528(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-P8-NEXT:    ld r21, 392(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    ld r20, 384(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lxvd2x v29, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-P8-NEXT:    li r4, 272
 ; BE-P8-NEXT:    lfd f19, 520(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-P8-NEXT:    ld r19, 376(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    ld r18, 368(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lxvd2x v28, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-P8-NEXT:    li r4, 256
 ; BE-P8-NEXT:    lfd f18, 512(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-P8-NEXT:    ld r17, 360(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    ld r16, 352(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lxvd2x v27, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-P8-NEXT:    li r4, 240
 ; BE-P8-NEXT:    lfd f17, 504(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-P8-NEXT:    ld r15, 344(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    ld r14, 336(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lxvd2x v26, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-P8-NEXT:    li r4, 224
 ; BE-P8-NEXT:    lfd f16, 496(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-P8-NEXT:    lxvd2x v25, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-P8-NEXT:    li r4, 208
 ; BE-P8-NEXT:    lfd f15, 488(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-P8-NEXT:    lxvd2x v24, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-P8-NEXT:    li r4, 192
 ; BE-P8-NEXT:    lfd f14, 480(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-P8-NEXT:    lxvd2x v23, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-P8-NEXT:    li r4, 176
 ; BE-P8-NEXT:    lxvd2x v22, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-P8-NEXT:    li r4, 160
 ; BE-P8-NEXT:    lxvd2x v21, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-P8-NEXT:    li r4, 144
 ; BE-P8-NEXT:    lxvd2x v20, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-P8-NEXT:    addi r1, r1, 624
 ; BE-P8-NEXT:    ld r0, 16(r1)
 ; BE-P8-NEXT:    lwz r12, 8(r1)
 ; BE-P8-NEXT:    mtocrf 32, r12
 ; BE-P8-NEXT:    hashchk r0, -488(r1)
 ; BE-P8-NEXT:    mtlr r0
 ; BE-P8-NEXT:    mtocrf 16, r12
 ; BE-P8-NEXT:    mtocrf 8, r12

 ; BE-32BIT-P10-NEXT:    stw r25, 324(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-NEXT:    stw r26, 328(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-NEXT:    stw r27, 332(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-NEXT:    stw r28, 336(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-NEXT:    stw r29, 340(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-NEXT:    stw r30, 344(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-NEXT:    stw r31, 348(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-NEXT:    stfd f14, 352(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-32BIT-P10-NEXT:    stfd f15, 360(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-32BIT-P10-NEXT:    stfd f16, 368(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-32BIT-P10-NEXT:    stfd f17, 376(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-32BIT-P10-NEXT:    stfd f18, 384(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-32BIT-P10-NEXT:    stfd f19, 392(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-32BIT-P10-NEXT:    stfd f20, 400(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-32BIT-P10-NEXT:    stfd f21, 408(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-32BIT-P10-NEXT:    stfd f22, 416(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-32BIT-P10-NEXT:    stfd f23, 424(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-32BIT-P10-NEXT:    stfd f24, 432(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-32BIT-P10-NEXT:    stfd f25, 440(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-32BIT-P10-NEXT:    stfd f26, 448(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-32BIT-P10-NEXT:    stfd f27, 456(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-32BIT-P10-NEXT:    stfd f28, 464(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-32BIT-P10-NEXT:    stfd f29, 472(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-32BIT-P10-NEXT:    stfd f30, 480(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-32BIT-P10-NEXT:    stfd f31, 488(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-32BIT-P10-NEXT:    stxv v20, 80(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-32BIT-P10-NEXT:    stxv v21, 96(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-32BIT-P10-NEXT:    stxv v22, 112(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-32BIT-P10-NEXT:    stxv v23, 128(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-32BIT-P10-NEXT:    stxv v24, 144(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-32BIT-P10-NEXT:    stxv v25, 160(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-32BIT-P10-NEXT:    stxv v26, 176(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-32BIT-P10-NEXT:    stxv v27, 192(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-32BIT-P10-NEXT:    stxv v28, 208(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-32BIT-P10-NEXT:    stxv v29, 224(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-32BIT-P10-NEXT:    stxv v30, 240(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-32BIT-P10-NEXT:    stxv v31, 256(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-32BIT-P10-NEXT:    stw r3, 64(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-NEXT:    stw r4, 68(r1)
 ; BE-32BIT-P10-NEXT:    #APP
 ; BE-32BIT-P10-NEXT:    nop
 ; BE-32BIT-P10-NEXT:    #NO_APP
 ; BE-32BIT-P10-NEXT:    addi r3, r1, 68
 ; BE-32BIT-P10-NEXT:    bl .callee2[PR]
 ; BE-32BIT-P10-NEXT:    nop
 ; BE-32BIT-P10-NEXT:    lwz r4, 64(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-NEXT:    lxv v31, 256(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-32BIT-P10-NEXT:    lxv v30, 240(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-32BIT-P10-NEXT:    lxv v29, 224(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-32BIT-P10-NEXT:    lxv v28, 208(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-32BIT-P10-NEXT:    lxv v27, 192(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-32BIT-P10-NEXT:    lxv v26, 176(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-32BIT-P10-NEXT:    lxv v25, 160(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-32BIT-P10-NEXT:    lxv v24, 144(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-32BIT-P10-NEXT:    lxv v23, 128(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-32BIT-P10-NEXT:    lxv v22, 112(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-32BIT-P10-NEXT:    lxv v21, 96(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-32BIT-P10-NEXT:    lxv v20, 80(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-32BIT-P10-NEXT:    lfd f31, 488(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-32BIT-P10-NEXT:    lfd f30, 480(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-32BIT-P10-NEXT:    lfd f29, 472(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-32BIT-P10-NEXT:    lfd f28, 464(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-32BIT-P10-NEXT:    lfd f27, 456(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-32BIT-P10-NEXT:    lfd f26, 448(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-32BIT-P10-NEXT:    lfd f25, 440(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-32BIT-P10-NEXT:    lfd f24, 432(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-32BIT-P10-NEXT:    lfd f23, 424(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-32BIT-P10-NEXT:    lfd f22, 416(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-32BIT-P10-NEXT:    lfd f21, 408(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-32BIT-P10-NEXT:    lfd f20, 400(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-32BIT-P10-NEXT:    lfd f19, 392(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-32BIT-P10-NEXT:    lfd f18, 384(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-32BIT-P10-NEXT:    lfd f17, 376(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-32BIT-P10-NEXT:    lfd f16, 368(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-32BIT-P10-NEXT:    lfd f15, 360(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-32BIT-P10-NEXT:    lfd f14, 352(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-32BIT-P10-NEXT:    lwz r31, 348(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-NEXT:    lwz r30, 344(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-NEXT:    lwz r29, 340(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-NEXT:    lwz r28, 336(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-NEXT:    lwz r27, 332(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-NEXT:    lwz r26, 328(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-NEXT:    lwz r25, 324(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-NEXT:    lwz r24, 320(r1) # 4-byte Folded Reload

 ; BE-32BIT-P9-NEXT:    stw r0, 8(r1)
 ; BE-32BIT-P9-NEXT:    hashst r0, -424(r1)
 ; BE-32BIT-P9-NEXT:    stw r12, 4(r1)
 ; BE-32BIT-P9-NEXT:    stwu r1, -496(r1)
 ; BE-32BIT-P9-NEXT:    lwz r4, 12(r3)
 ; BE-32BIT-P9-NEXT:    stw r13, 276(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stw r14, 280(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stxv v20, 80(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-32BIT-P9-NEXT:    stxv v21, 96(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-32BIT-P9-NEXT:    stxv v22, 112(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-32BIT-P9-NEXT:    stw r15, 284(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stw r16, 288(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stxv v23, 128(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-32BIT-P9-NEXT:    stw r17, 292(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stxv v24, 144(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-32BIT-P9-NEXT:    stw r18, 296(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stxv v25, 160(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-32BIT-P9-NEXT:    stw r19, 300(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stw r20, 304(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stxv v26, 176(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-32BIT-P9-NEXT:    stw r21, 308(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stxv v27, 192(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-32BIT-P9-NEXT:    stw r22, 312(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stxv v28, 208(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-32BIT-P9-NEXT:    stw r23, 316(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stw r24, 320(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stxv v29, 224(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-32BIT-P9-NEXT:    stw r25, 324(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stxv v30, 240(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-32BIT-P9-NEXT:    stw r26, 328(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stxv v31, 256(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-32BIT-P9-NEXT:    stw r27, 332(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stw r28, 336(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stw r29, 340(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stw r30, 344(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stw r31, 348(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stfd f14, 352(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-32BIT-P9-NEXT:    stfd f15, 360(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-32BIT-P9-NEXT:    stfd f16, 368(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-32BIT-P9-NEXT:    stfd f17, 376(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-32BIT-P9-NEXT:    stfd f18, 384(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-32BIT-P9-NEXT:    stfd f19, 392(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-32BIT-P9-NEXT:    stfd f20, 400(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-32BIT-P9-NEXT:    stfd f21, 408(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-32BIT-P9-NEXT:    stfd f22, 416(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-32BIT-P9-NEXT:    stfd f23, 424(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-32BIT-P9-NEXT:    stfd f24, 432(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-32BIT-P9-NEXT:    stfd f25, 440(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-32BIT-P9-NEXT:    stfd f26, 448(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-32BIT-P9-NEXT:    stfd f27, 456(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-32BIT-P9-NEXT:    stfd f28, 464(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-32BIT-P9-NEXT:    stfd f29, 472(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-32BIT-P9-NEXT:    stfd f30, 480(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-32BIT-P9-NEXT:    stfd f31, 488(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-32BIT-P9-NEXT:    stw r3, 64(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stw r4, 68(r1)
 ; BE-32BIT-P9-NEXT:    #APP
 ; BE-32BIT-P9-NEXT:    nop
 ; BE-32BIT-P9-NEXT:    #NO_APP
 ; BE-32BIT-P9-NEXT:    addi r3, r1, 68
 ; BE-32BIT-P9-NEXT:    bl .callee2[PR]
 ; BE-32BIT-P9-NEXT:    nop
 ; BE-32BIT-P9-NEXT:    lwz r4, 64(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lxv v31, 256(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-32BIT-P9-NEXT:    lxv v30, 240(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-32BIT-P9-NEXT:    lxv v29, 224(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-32BIT-P9-NEXT:    lxv v28, 208(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-32BIT-P9-NEXT:    lxv v27, 192(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-32BIT-P9-NEXT:    lxv v26, 176(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-32BIT-P9-NEXT:    lxv v25, 160(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-32BIT-P9-NEXT:    lxv v24, 144(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-32BIT-P9-NEXT:    lxv v23, 128(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-32BIT-P9-NEXT:    lxv v22, 112(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-32BIT-P9-NEXT:    lxv v21, 96(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-32BIT-P9-NEXT:    lxv v20, 80(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-32BIT-P9-NEXT:    lfd f31, 488(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-32BIT-P9-NEXT:    lfd f30, 480(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-32BIT-P9-NEXT:    lfd f29, 472(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-32BIT-P9-NEXT:    lfd f28, 464(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-32BIT-P9-NEXT:    lfd f27, 456(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-32BIT-P9-NEXT:    lwz r31, 348(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r30, 344(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r29, 340(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lfd f26, 448(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-32BIT-P9-NEXT:    lwz r28, 336(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r27, 332(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r26, 328(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lfd f25, 440(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-32BIT-P9-NEXT:    lwz r25, 324(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r24, 320(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r23, 316(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lfd f24, 432(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-32BIT-P9-NEXT:    lwz r22, 312(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r21, 308(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r4, 16(r4)
 ; BE-32BIT-P9-NEXT:    add r3, r4, r3
 ; BE-32BIT-P9-NEXT:    lfd f23, 424(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-32BIT-P9-NEXT:    lfd f22, 416(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-32BIT-P9-NEXT:    lwz r20, 304(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r19, 300(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r18, 296(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r17, 292(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r16, 288(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r15, 284(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r14, 280(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r13, 276(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lfd f21, 408(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-32BIT-P9-NEXT:    lfd f20, 400(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-32BIT-P9-NEXT:    lfd f19, 392(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-32BIT-P9-NEXT:    lfd f18, 384(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-32BIT-P9-NEXT:    lfd f17, 376(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-32BIT-P9-NEXT:    lfd f16, 368(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-32BIT-P9-NEXT:    lfd f15, 360(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-32BIT-P9-NEXT:    lfd f14, 352(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-32BIT-P9-NEXT:    addi r1, r1, 496
 ; BE-32BIT-P9-NEXT:    lwz r0, 8(r1)
 ; BE-32BIT-P9-NEXT:    lwz r12, 4(r1)
 ; BE-32BIT-P9-NEXT:    mtlr r0
 ; BE-32BIT-P9-NEXT:    hashchk r0, -424(r1)
 ; BE-32BIT-P9-NEXT:    mtocrf 32, r12
 ; BE-32BIT-P9-NEXT:    mtocrf 16, r12
 ; BE-32BIT-P9-NEXT:    mtocrf 8, r12
 ; BE-32BIT-P9-NEXT:    blr
 ;
 ; BE-32BIT-P8-LABEL: spill:
 ; BE-32BIT-P8:       # %bb.0: # %entry
 ; BE-32BIT-P8-NEXT:    mfcr r12
 ; BE-32BIT-P8-NEXT:    mflr r0
 ; BE-32BIT-P8-NEXT:    stw r0, 8(r1)
 ; BE-32BIT-P8-NEXT:    hashst r0, -424(r1)
 ; BE-32BIT-P8-NEXT:    stw r12, 4(r1)
 ; BE-32BIT-P8-NEXT:    stwu r1, -496(r1)
 ; BE-32BIT-P8-NEXT:    li r4, 80
 ; BE-32BIT-P8-NEXT:    stw r13, 276(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stw r14, 280(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stxvd2x v20, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-32BIT-P8-NEXT:    li r4, 96
 ; BE-32BIT-P8-NEXT:    stw r15, 284(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stxvd2x v21, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-32BIT-P8-NEXT:    li r4, 112
 ; BE-32BIT-P8-NEXT:    stw r16, 288(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stxvd2x v22, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-32BIT-P8-NEXT:    li r4, 128
 ; BE-32BIT-P8-NEXT:    stw r17, 292(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stxvd2x v23, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-32BIT-P8-NEXT:    li r4, 144
 ; BE-32BIT-P8-NEXT:    stw r18, 296(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stxvd2x v24, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-32BIT-P8-NEXT:    li r4, 160
 ; BE-32BIT-P8-NEXT:    stw r19, 300(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stxvd2x v25, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-32BIT-P8-NEXT:    li r4, 176
 ; BE-32BIT-P8-NEXT:    stw r20, 304(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stxvd2x v26, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-32BIT-P8-NEXT:    li r4, 192
 ; BE-32BIT-P8-NEXT:    stw r21, 308(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stxvd2x v27, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-32BIT-P8-NEXT:    li r4, 208
 ; BE-32BIT-P8-NEXT:    stw r22, 312(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stxvd2x v28, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-32BIT-P8-NEXT:    li r4, 224
 ; BE-32BIT-P8-NEXT:    stw r23, 316(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stxvd2x v29, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-32BIT-P8-NEXT:    li r4, 240
 ; BE-32BIT-P8-NEXT:    stw r24, 320(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stxvd2x v30, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-32BIT-P8-NEXT:    li r4, 256
 ; BE-32BIT-P8-NEXT:    stw r25, 324(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stxvd2x v31, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-32BIT-P8-NEXT:    lwz r4, 12(r3)
 ; BE-32BIT-P8-NEXT:    stw r26, 328(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stw r27, 332(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stw r28, 336(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stw r29, 340(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stw r30, 344(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stw r31, 348(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stfd f14, 352(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-32BIT-P8-NEXT:    stfd f15, 360(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-32BIT-P8-NEXT:    stfd f16, 368(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-32BIT-P8-NEXT:    stfd f17, 376(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-32BIT-P8-NEXT:    stfd f18, 384(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-32BIT-P8-NEXT:    stfd f19, 392(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-32BIT-P8-NEXT:    stfd f20, 400(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-32BIT-P8-NEXT:    stfd f21, 408(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-32BIT-P8-NEXT:    stfd f22, 416(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-32BIT-P8-NEXT:    stfd f23, 424(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-32BIT-P8-NEXT:    stfd f24, 432(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-32BIT-P8-NEXT:    stfd f25, 440(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-32BIT-P8-NEXT:    stfd f26, 448(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-32BIT-P8-NEXT:    stfd f27, 456(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-32BIT-P8-NEXT:    stfd f28, 464(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-32BIT-P8-NEXT:    stfd f29, 472(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-32BIT-P8-NEXT:    stfd f30, 480(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-32BIT-P8-NEXT:    stfd f31, 488(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-32BIT-P8-NEXT:    stw r3, 64(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stw r4, 68(r1)
 ; BE-32BIT-P8-NEXT:    #APP
 ; BE-32BIT-P8-NEXT:    nop
 ; BE-32BIT-P8-NEXT:    #NO_APP
 ; BE-32BIT-P8-NEXT:    addi r3, r1, 68
 ; BE-32BIT-P8-NEXT:    bl .callee2[PR]
 ; BE-32BIT-P8-NEXT:    nop
 ; BE-32BIT-P8-NEXT:    lwz r4, 64(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lfd f31, 488(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-32BIT-P8-NEXT:    lfd f30, 480(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-32BIT-P8-NEXT:    lwz r31, 348(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lfd f29, 472(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-32BIT-P8-NEXT:    lfd f28, 464(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-32BIT-P8-NEXT:    lwz r30, 344(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lwz r29, 340(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lwz r4, 16(r4)
 ; BE-32BIT-P8-NEXT:    lfd f27, 456(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-32BIT-P8-NEXT:    lfd f26, 448(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-32BIT-P8-NEXT:    lwz r28, 336(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lfd f25, 440(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-32BIT-P8-NEXT:    lfd f24, 432(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-32BIT-P8-NEXT:    lwz r27, 332(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lwz r26, 328(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    add r3, r4, r3
 ; BE-32BIT-P8-NEXT:    li r4, 256
 ; BE-32BIT-P8-NEXT:    lfd f23, 424(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-32BIT-P8-NEXT:    lfd f22, 416(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-32BIT-P8-NEXT:    lwz r25, 324(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lwz r24, 320(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lxvd2x v31, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-32BIT-P8-NEXT:    li r4, 240
 ; BE-32BIT-P8-NEXT:    lfd f21, 408(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-32BIT-P8-NEXT:    lwz r23, 316(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lwz r22, 312(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lxvd2x v30, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-32BIT-P8-NEXT:    li r4, 224
 ; BE-32BIT-P8-NEXT:    lfd f20, 400(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-32BIT-P8-NEXT:    lwz r21, 308(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lwz r20, 304(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lxvd2x v29, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-32BIT-P8-NEXT:    li r4, 208
 ; BE-32BIT-P8-NEXT:    lfd f19, 392(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-32BIT-P8-NEXT:    lwz r19, 300(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lwz r18, 296(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lxvd2x v28, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-32BIT-P8-NEXT:    li r4, 192
 ; BE-32BIT-P8-NEXT:    lfd f18, 384(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-32BIT-P8-NEXT:    lwz r17, 292(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lwz r16, 288(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lxvd2x v27, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-32BIT-P8-NEXT:    li r4, 176
 ; BE-32BIT-P8-NEXT:    lfd f17, 376(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-32BIT-P8-NEXT:    lwz r15, 284(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lwz r14, 280(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lxvd2x v26, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-32BIT-P8-NEXT:    li r4, 160
 ; BE-32BIT-P8-NEXT:    lfd f16, 368(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-32BIT-P8-NEXT:    lwz r13, 276(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lxvd2x v25, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-32BIT-P8-NEXT:    li r4, 144
 ; BE-32BIT-P8-NEXT:    lfd f15, 360(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-32BIT-P8-NEXT:    lxvd2x v24, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-32BIT-P8-NEXT:    li r4, 128
 ; BE-32BIT-P8-NEXT:    lfd f14, 352(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-32BIT-P8-NEXT:    lxvd2x v23, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-32BIT-P8-NEXT:    li r4, 112
 ; BE-32BIT-P8-NEXT:    lxvd2x v22, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-32BIT-P8-NEXT:    li r4, 96
 ; BE-32BIT-P8-NEXT:    lxvd2x v21, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-32BIT-P8-NEXT:    li r4, 80
 ; BE-32BIT-P8-NEXT:    lxvd2x v20, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-32BIT-P8-NEXT:    addi r1, r1, 496
 ; BE-32BIT-P8-NEXT:    lwz r0, 8(r1)
 ; BE-32BIT-P8-NEXT:    lwz r12, 4(r1)
 ; BE-32BIT-P8-NEXT:    mtocrf 32, r12
 ; BE-32BIT-P8-NEXT:    hashchk r0, -424(r1)
 ; BE-32BIT-P8-NEXT:    mtlr r0
 ; BE-32BIT-P8-NEXT:    mtocrf 16, r12
 ; BE-32BIT-P8-NEXT:    mtocrf 8, r12

 ; BE-P10-PRIV-NEXT:    std r25, 424(r1) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    std r26, 432(r1) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    std r27, 440(r1) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    std r28, 448(r1) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    std r29, 456(r1) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    std r30, 464(r1) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    std r31, 472(r1) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    stfd f14, 480(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-P10-PRIV-NEXT:    stfd f15, 488(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-P10-PRIV-NEXT:    stfd f16, 496(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-P10-PRIV-NEXT:    stfd f17, 504(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-P10-PRIV-NEXT:    stfd f18, 512(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-P10-PRIV-NEXT:    stfd f19, 520(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-P10-PRIV-NEXT:    stfd f20, 528(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-P10-PRIV-NEXT:    stfd f21, 536(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-P10-PRIV-NEXT:    stfd f22, 544(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-P10-PRIV-NEXT:    stfd f23, 552(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-P10-PRIV-NEXT:    stfd f24, 560(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-P10-PRIV-NEXT:    stfd f25, 568(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-P10-PRIV-NEXT:    stfd f26, 576(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-P10-PRIV-NEXT:    stfd f27, 584(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-P10-PRIV-NEXT:    stfd f28, 592(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-P10-PRIV-NEXT:    stfd f29, 600(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-P10-PRIV-NEXT:    stfd f30, 608(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-P10-PRIV-NEXT:    stfd f31, 616(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-P10-PRIV-NEXT:    stxv v20, 144(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-P10-PRIV-NEXT:    stxv v21, 160(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-P10-PRIV-NEXT:    stxv v22, 176(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-P10-PRIV-NEXT:    stxv v23, 192(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-P10-PRIV-NEXT:    stxv v24, 208(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-P10-PRIV-NEXT:    stxv v25, 224(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-P10-PRIV-NEXT:    stxv v26, 240(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-P10-PRIV-NEXT:    stxv v27, 256(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-P10-PRIV-NEXT:    stxv v28, 272(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-P10-PRIV-NEXT:    stxv v29, 288(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-P10-PRIV-NEXT:    stxv v30, 304(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-P10-PRIV-NEXT:    stxv v31, 320(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-P10-PRIV-NEXT:    std r3, 120(r1) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    stw r4, 132(r1)
 ; BE-P10-PRIV-NEXT:    #APP
 ; BE-P10-PRIV-NEXT:    nop
 ; BE-P10-PRIV-NEXT:    #NO_APP
 ; BE-P10-PRIV-NEXT:    addi r3, r1, 132
 ; BE-P10-PRIV-NEXT:    bl .callee2[PR]
 ; BE-P10-PRIV-NEXT:    nop
 ; BE-P10-PRIV-NEXT:    ld r4, 120(r1) # 8-byte Folded Reload
 ; BE-P10-PRIV-NEXT:    lxv v31, 320(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-P10-PRIV-NEXT:    lxv v30, 304(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-P10-PRIV-NEXT:    lxv v29, 288(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-P10-PRIV-NEXT:    lxv v28, 272(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-P10-PRIV-NEXT:    lxv v27, 256(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-P10-PRIV-NEXT:    lxv v26, 240(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-P10-PRIV-NEXT:    lxv v25, 224(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-P10-PRIV-NEXT:    lxv v24, 208(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-P10-PRIV-NEXT:    lxv v23, 192(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-P10-PRIV-NEXT:    lxv v22, 176(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-P10-PRIV-NEXT:    lxv v21, 160(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-P10-PRIV-NEXT:    lxv v20, 144(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-P10-PRIV-NEXT:    lfd f31, 616(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-P10-PRIV-NEXT:    lfd f30, 608(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-P10-PRIV-NEXT:    lfd f29, 600(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-P10-PRIV-NEXT:    lfd f28, 592(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-P10-PRIV-NEXT:    lfd f27, 584(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-P10-PRIV-NEXT:    lfd f26, 576(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-P10-PRIV-NEXT:    lfd f25, 568(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-P10-PRIV-NEXT:    lfd f24, 560(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-P10-PRIV-NEXT:    lfd f23, 552(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-P10-PRIV-NEXT:    lfd f22, 544(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-P10-PRIV-NEXT:    lfd f21, 536(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-P10-PRIV-NEXT:    lfd f20, 528(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-P10-PRIV-NEXT:    lfd f19, 520(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-P10-PRIV-NEXT:    lfd f18, 512(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-P10-PRIV-NEXT:    lfd f17, 504(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-P10-PRIV-NEXT:    lfd f16, 496(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-P10-PRIV-NEXT:    lfd f15, 488(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-P10-PRIV-NEXT:    lfd f14, 480(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-P10-PRIV-NEXT:    ld r31, 472(r1) # 8-byte Folded Reload
 ; BE-P10-PRIV-NEXT:    ld r30, 464(r1) # 8-byte Folded Reload
 ; BE-P10-PRIV-NEXT:    ld r29, 456(r1) # 8-byte Folded Reload
 ; BE-P10-PRIV-NEXT:    ld r28, 448(r1) # 8-byte Folded Reload
 ; BE-P10-PRIV-NEXT:    ld r27, 440(r1) # 8-byte Folded Reload
 ; BE-P10-PRIV-NEXT:    ld r26, 432(r1) # 8-byte Folded Reload
 ; BE-P10-PRIV-NEXT:    ld r25, 424(r1) # 8-byte Folded Reload
 ; BE-P10-PRIV-NEXT:    ld r24, 416(r1) # 8-byte Folded Reload

 ; BE-P9-PRIV-NEXT:    std r0, 16(r1)
 ; BE-P9-PRIV-NEXT:    hashstp r0, -488(r1)
 ; BE-P9-PRIV-NEXT:    stw r12, 8(r1)
 ; BE-P9-PRIV-NEXT:    stdu r1, -624(r1)
 ; BE-P9-PRIV-NEXT:    lwz r4, 12(r3)
 ; BE-P9-PRIV-NEXT:    std r14, 336(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    std r15, 344(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v20, 144(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-P9-PRIV-NEXT:    stxv v21, 160(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-P9-PRIV-NEXT:    stxv v22, 176(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-P9-PRIV-NEXT:    std r16, 352(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    std r17, 360(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v23, 192(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-P9-PRIV-NEXT:    std r18, 368(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v24, 208(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-P9-PRIV-NEXT:    std r19, 376(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v25, 224(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-P9-PRIV-NEXT:    std r20, 384(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    std r21, 392(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v26, 240(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-P9-PRIV-NEXT:    std r22, 400(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v27, 256(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-P9-PRIV-NEXT:    std r23, 408(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v28, 272(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-P9-PRIV-NEXT:    std r24, 416(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    std r25, 424(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v29, 288(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-P9-PRIV-NEXT:    std r26, 432(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v30, 304(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-P9-PRIV-NEXT:    std r27, 440(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v31, 320(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-P9-PRIV-NEXT:    std r28, 448(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    std r29, 456(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    std r30, 464(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    std r31, 472(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stfd f14, 480(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-P9-PRIV-NEXT:    stfd f15, 488(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-P9-PRIV-NEXT:    stfd f16, 496(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-P9-PRIV-NEXT:    stfd f17, 504(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-P9-PRIV-NEXT:    stfd f18, 512(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-P9-PRIV-NEXT:    stfd f19, 520(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-P9-PRIV-NEXT:    stfd f20, 528(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-P9-PRIV-NEXT:    stfd f21, 536(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-P9-PRIV-NEXT:    stfd f22, 544(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-P9-PRIV-NEXT:    stfd f23, 552(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-P9-PRIV-NEXT:    stfd f24, 560(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-P9-PRIV-NEXT:    stfd f25, 568(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-P9-PRIV-NEXT:    stfd f26, 576(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-P9-PRIV-NEXT:    stfd f27, 584(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-P9-PRIV-NEXT:    stfd f28, 592(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-P9-PRIV-NEXT:    stfd f29, 600(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-P9-PRIV-NEXT:    stfd f30, 608(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-P9-PRIV-NEXT:    stfd f31, 616(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-P9-PRIV-NEXT:    std r3, 120(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stw r4, 132(r1)
 ; BE-P9-PRIV-NEXT:    #APP
 ; BE-P9-PRIV-NEXT:    nop
 ; BE-P9-PRIV-NEXT:    #NO_APP
 ; BE-P9-PRIV-NEXT:    addi r3, r1, 132
 ; BE-P9-PRIV-NEXT:    bl .callee2[PR]
 ; BE-P9-PRIV-NEXT:    nop
 ; BE-P9-PRIV-NEXT:    ld r4, 120(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    lxv v31, 320(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-P9-PRIV-NEXT:    lxv v30, 304(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-P9-PRIV-NEXT:    lxv v29, 288(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-P9-PRIV-NEXT:    lxv v28, 272(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-P9-PRIV-NEXT:    lxv v27, 256(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-P9-PRIV-NEXT:    lxv v26, 240(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-P9-PRIV-NEXT:    lxv v25, 224(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-P9-PRIV-NEXT:    lxv v24, 208(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-P9-PRIV-NEXT:    lxv v23, 192(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-P9-PRIV-NEXT:    lxv v22, 176(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-P9-PRIV-NEXT:    lxv v21, 160(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-P9-PRIV-NEXT:    lxv v20, 144(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-P9-PRIV-NEXT:    lfd f31, 616(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-P9-PRIV-NEXT:    lfd f30, 608(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-P9-PRIV-NEXT:    lfd f29, 600(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-P9-PRIV-NEXT:    lfd f28, 592(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-P9-PRIV-NEXT:    lfd f27, 584(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-P9-PRIV-NEXT:    ld r31, 472(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r30, 464(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r29, 456(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    lfd f26, 576(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-P9-PRIV-NEXT:    ld r28, 448(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r27, 440(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r26, 432(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    lfd f25, 568(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-P9-PRIV-NEXT:    ld r25, 424(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r24, 416(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r23, 408(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    lfd f24, 560(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-P9-PRIV-NEXT:    ld r22, 400(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r21, 392(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    lwz r4, 16(r4)
 ; BE-P9-PRIV-NEXT:    add r3, r4, r3
 ; BE-P9-PRIV-NEXT:    lfd f23, 552(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-P9-PRIV-NEXT:    lfd f22, 544(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-P9-PRIV-NEXT:    ld r20, 384(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r19, 376(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r18, 368(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r17, 360(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r16, 352(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r15, 344(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r14, 336(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    lfd f21, 536(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-P9-PRIV-NEXT:    lfd f20, 528(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-P9-PRIV-NEXT:    lfd f19, 520(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-P9-PRIV-NEXT:    lfd f18, 512(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-P9-PRIV-NEXT:    lfd f17, 504(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-P9-PRIV-NEXT:    lfd f16, 496(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-P9-PRIV-NEXT:    lfd f15, 488(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-P9-PRIV-NEXT:    lfd f14, 480(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-P9-PRIV-NEXT:    clrldi r3, r3, 32
 ; BE-P9-PRIV-NEXT:    addi r1, r1, 624
 ; BE-P9-PRIV-NEXT:    ld r0, 16(r1)
 ; BE-P9-PRIV-NEXT:    lwz r12, 8(r1)
 ; BE-P9-PRIV-NEXT:    mtlr r0
 ; BE-P9-PRIV-NEXT:    hashchkp r0, -488(r1)
 ; BE-P9-PRIV-NEXT:    mtocrf 32, r12
 ; BE-P9-PRIV-NEXT:    mtocrf 16, r12

 ; BE-P8-PRIV-NEXT:    stw r12, 8(r1)
 ; BE-P8-PRIV-NEXT:    stdu r1, -624(r1)
 ; BE-P8-PRIV-NEXT:    li r4, 144
 ; BE-P8-PRIV-NEXT:    std r14, 336(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r15, 344(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r16, 352(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r17, 360(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    stxvd2x v20, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-P8-PRIV-NEXT:    li r4, 160
 ; BE-P8-PRIV-NEXT:    std r18, 368(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r19, 376(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r20, 384(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r21, 392(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    stxvd2x v21, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-P8-PRIV-NEXT:    li r4, 176
 ; BE-P8-PRIV-NEXT:    std r22, 400(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r23, 408(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r24, 416(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r25, 424(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r26, 432(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r27, 440(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r28, 448(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r29, 456(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r30, 464(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r31, 472(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r3, 120(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    stxvd2x v22, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-P8-PRIV-NEXT:    li r4, 192
 ; BE-P8-PRIV-NEXT:    stxvd2x v23, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-P8-PRIV-NEXT:    li r4, 208
 ; BE-P8-PRIV-NEXT:    stfd f14, 480(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-P8-PRIV-NEXT:    stxvd2x v24, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-P8-PRIV-NEXT:    li r4, 224
 ; BE-P8-PRIV-NEXT:    stfd f15, 488(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-P8-PRIV-NEXT:    stxvd2x v25, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-P8-PRIV-NEXT:    li r4, 240
 ; BE-P8-PRIV-NEXT:    stfd f16, 496(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-P8-PRIV-NEXT:    stxvd2x v26, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-P8-PRIV-NEXT:    li r4, 256
 ; BE-P8-PRIV-NEXT:    stfd f17, 504(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-P8-PRIV-NEXT:    stxvd2x v27, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-P8-PRIV-NEXT:    li r4, 272
 ; BE-P8-PRIV-NEXT:    stfd f18, 512(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-P8-PRIV-NEXT:    stxvd2x v28, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-P8-PRIV-NEXT:    li r4, 288
 ; BE-P8-PRIV-NEXT:    stfd f19, 520(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-P8-PRIV-NEXT:    stxvd2x v29, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-P8-PRIV-NEXT:    li r4, 304
 ; BE-P8-PRIV-NEXT:    stfd f20, 528(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-P8-PRIV-NEXT:    stxvd2x v30, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-P8-PRIV-NEXT:    li r4, 320
 ; BE-P8-PRIV-NEXT:    stfd f21, 536(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-P8-PRIV-NEXT:    stxvd2x v31, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-P8-PRIV-NEXT:    lwz r4, 12(r3)
 ; BE-P8-PRIV-NEXT:    stfd f22, 544(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-P8-PRIV-NEXT:    stfd f23, 552(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-P8-PRIV-NEXT:    stfd f24, 560(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-P8-PRIV-NEXT:    stfd f25, 568(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-P8-PRIV-NEXT:    stfd f26, 576(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-P8-PRIV-NEXT:    stfd f27, 584(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-P8-PRIV-NEXT:    stfd f28, 592(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-P8-PRIV-NEXT:    stfd f29, 600(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-P8-PRIV-NEXT:    stfd f30, 608(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-P8-PRIV-NEXT:    stfd f31, 616(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-P8-PRIV-NEXT:    stw r4, 132(r1)
 ; BE-P8-PRIV-NEXT:    #APP
 ; BE-P8-PRIV-NEXT:    nop
 ; BE-P8-PRIV-NEXT:    #NO_APP
 ; BE-P8-PRIV-NEXT:    addi r3, r1, 132
 ; BE-P8-PRIV-NEXT:    bl .callee2[PR]
 ; BE-P8-PRIV-NEXT:    nop
 ; BE-P8-PRIV-NEXT:    ld r4, 120(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lfd f31, 616(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-P8-PRIV-NEXT:    lfd f30, 608(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-P8-PRIV-NEXT:    ld r31, 472(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lfd f29, 600(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-P8-PRIV-NEXT:    lfd f28, 592(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-P8-PRIV-NEXT:    ld r30, 464(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    ld r29, 456(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lwz r4, 16(r4)
 ; BE-P8-PRIV-NEXT:    lfd f27, 584(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-P8-PRIV-NEXT:    lfd f26, 576(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-P8-PRIV-NEXT:    ld r28, 448(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lfd f25, 568(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-P8-PRIV-NEXT:    lfd f24, 560(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-P8-PRIV-NEXT:    ld r27, 440(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    ld r26, 432(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    add r3, r4, r3
 ; BE-P8-PRIV-NEXT:    li r4, 320
 ; BE-P8-PRIV-NEXT:    lfd f23, 552(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-P8-PRIV-NEXT:    lfd f22, 544(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-P8-PRIV-NEXT:    ld r25, 424(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    ld r24, 416(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lxvd2x v31, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-P8-PRIV-NEXT:    li r4, 304
 ; BE-P8-PRIV-NEXT:    lfd f21, 536(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-P8-PRIV-NEXT:    ld r23, 408(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    ld r22, 400(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    clrldi r3, r3, 32
 ; BE-P8-PRIV-NEXT:    lxvd2x v30, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-P8-PRIV-NEXT:    li r4, 288
 ; BE-P8-PRIV-NEXT:    lfd f20, 528(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-P8-PRIV-NEXT:    ld r21, 392(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    ld r20, 384(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lxvd2x v29, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-P8-PRIV-NEXT:    li r4, 272
 ; BE-P8-PRIV-NEXT:    lfd f19, 520(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-P8-PRIV-NEXT:    ld r19, 376(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    ld r18, 368(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lxvd2x v28, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-P8-PRIV-NEXT:    li r4, 256
 ; BE-P8-PRIV-NEXT:    lfd f18, 512(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-P8-PRIV-NEXT:    ld r17, 360(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    ld r16, 352(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lxvd2x v27, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-P8-PRIV-NEXT:    li r4, 240
 ; BE-P8-PRIV-NEXT:    lfd f17, 504(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-P8-PRIV-NEXT:    ld r15, 344(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    ld r14, 336(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lxvd2x v26, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-P8-PRIV-NEXT:    li r4, 224
 ; BE-P8-PRIV-NEXT:    lfd f16, 496(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-P8-PRIV-NEXT:    lxvd2x v25, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-P8-PRIV-NEXT:    li r4, 208
 ; BE-P8-PRIV-NEXT:    lfd f15, 488(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-P8-PRIV-NEXT:    lxvd2x v24, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-P8-PRIV-NEXT:    li r4, 192
 ; BE-P8-PRIV-NEXT:    lfd f14, 480(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-P8-PRIV-NEXT:    lxvd2x v23, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-P8-PRIV-NEXT:    li r4, 176
 ; BE-P8-PRIV-NEXT:    lxvd2x v22, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-P8-PRIV-NEXT:    li r4, 160
 ; BE-P8-PRIV-NEXT:    lxvd2x v21, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-P8-PRIV-NEXT:    li r4, 144
 ; BE-P8-PRIV-NEXT:    lxvd2x v20, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-P8-PRIV-NEXT:    addi r1, r1, 624
 ; BE-P8-PRIV-NEXT:    ld r0, 16(r1)
 ; BE-P8-PRIV-NEXT:    lwz r12, 8(r1)
 ; BE-P8-PRIV-NEXT:    mtocrf 32, r12
 ; BE-P8-PRIV-NEXT:    hashchkp r0, -488(r1)
 ; BE-P8-PRIV-NEXT:    mtlr r0
 ; BE-P8-PRIV-NEXT:    mtocrf 16, r12
 ; BE-P8-PRIV-NEXT:    mtocrf 8, r12

 ; BE-32BIT-P10-PRIV-NEXT:    stw r25, 324(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-PRIV-NEXT:    stw r26, 328(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-PRIV-NEXT:    stw r27, 332(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-PRIV-NEXT:    stw r28, 336(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-PRIV-NEXT:    stw r29, 340(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-PRIV-NEXT:    stw r30, 344(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-PRIV-NEXT:    stw r31, 348(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f14, 352(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f15, 360(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f16, 368(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f17, 376(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f18, 384(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f19, 392(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f20, 400(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f21, 408(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f22, 416(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f23, 424(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f24, 432(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f25, 440(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f26, 448(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f27, 456(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f28, 464(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f29, 472(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f30, 480(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-32BIT-P10-PRIV-NEXT:    stfd f31, 488(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-32BIT-P10-PRIV-NEXT:    stxv v20, 80(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-32BIT-P10-PRIV-NEXT:    stxv v21, 96(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-32BIT-P10-PRIV-NEXT:    stxv v22, 112(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-32BIT-P10-PRIV-NEXT:    stxv v23, 128(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-32BIT-P10-PRIV-NEXT:    stxv v24, 144(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-32BIT-P10-PRIV-NEXT:    stxv v25, 160(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-32BIT-P10-PRIV-NEXT:    stxv v26, 176(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-32BIT-P10-PRIV-NEXT:    stxv v27, 192(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-32BIT-P10-PRIV-NEXT:    stxv v28, 208(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-32BIT-P10-PRIV-NEXT:    stxv v29, 224(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-32BIT-P10-PRIV-NEXT:    stxv v30, 240(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-32BIT-P10-PRIV-NEXT:    stxv v31, 256(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-32BIT-P10-PRIV-NEXT:    stw r3, 64(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-PRIV-NEXT:    stw r4, 68(r1)
 ; BE-32BIT-P10-PRIV-NEXT:    #APP
 ; BE-32BIT-P10-PRIV-NEXT:    nop
 ; BE-32BIT-P10-PRIV-NEXT:    #NO_APP
 ; BE-32BIT-P10-PRIV-NEXT:    addi r3, r1, 68
 ; BE-32BIT-P10-PRIV-NEXT:    bl .callee2[PR]
 ; BE-32BIT-P10-PRIV-NEXT:    nop
 ; BE-32BIT-P10-PRIV-NEXT:    lwz r4, 64(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-PRIV-NEXT:    lxv v31, 256(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-32BIT-P10-PRIV-NEXT:    lxv v30, 240(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-32BIT-P10-PRIV-NEXT:    lxv v29, 224(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-32BIT-P10-PRIV-NEXT:    lxv v28, 208(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-32BIT-P10-PRIV-NEXT:    lxv v27, 192(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-32BIT-P10-PRIV-NEXT:    lxv v26, 176(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-32BIT-P10-PRIV-NEXT:    lxv v25, 160(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-32BIT-P10-PRIV-NEXT:    lxv v24, 144(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-32BIT-P10-PRIV-NEXT:    lxv v23, 128(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-32BIT-P10-PRIV-NEXT:    lxv v22, 112(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-32BIT-P10-PRIV-NEXT:    lxv v21, 96(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-32BIT-P10-PRIV-NEXT:    lxv v20, 80(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f31, 488(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f30, 480(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f29, 472(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f28, 464(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f27, 456(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f26, 448(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f25, 440(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f24, 432(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f23, 424(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f22, 416(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f21, 408(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f20, 400(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f19, 392(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f18, 384(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f17, 376(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f16, 368(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f15, 360(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-32BIT-P10-PRIV-NEXT:    lfd f14, 352(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-PRIV-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-32BIT-P10-PRIV-NEXT:    lwz r31, 348(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-PRIV-NEXT:    lwz r30, 344(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-PRIV-NEXT:    lwz r29, 340(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-PRIV-NEXT:    lwz r28, 336(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-PRIV-NEXT:    lwz r27, 332(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-PRIV-NEXT:    lwz r26, 328(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-PRIV-NEXT:    lwz r25, 324(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-PRIV-NEXT:    lwz r24, 320(r1) # 4-byte Folded Reload

 ; BE-32BIT-P9-PRIV-NEXT:    stw r0, 8(r1)
 ; BE-32BIT-P9-PRIV-NEXT:    hashstp r0, -424(r1)
 ; BE-32BIT-P9-PRIV-NEXT:    stw r12, 4(r1)
 ; BE-32BIT-P9-PRIV-NEXT:    stwu r1, -496(r1)
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r4, 12(r3)
 ; BE-32BIT-P9-PRIV-NEXT:    stw r13, 276(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stw r14, 280(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stxv v20, 80(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-32BIT-P9-PRIV-NEXT:    stxv v21, 96(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-32BIT-P9-PRIV-NEXT:    stxv v22, 112(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-32BIT-P9-PRIV-NEXT:    stw r15, 284(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stw r16, 288(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stxv v23, 128(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-32BIT-P9-PRIV-NEXT:    stw r17, 292(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stxv v24, 144(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-32BIT-P9-PRIV-NEXT:    stw r18, 296(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stxv v25, 160(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-32BIT-P9-PRIV-NEXT:    stw r19, 300(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stw r20, 304(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stxv v26, 176(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-32BIT-P9-PRIV-NEXT:    stw r21, 308(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stxv v27, 192(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-32BIT-P9-PRIV-NEXT:    stw r22, 312(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stxv v28, 208(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-32BIT-P9-PRIV-NEXT:    stw r23, 316(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stw r24, 320(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stxv v29, 224(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-32BIT-P9-PRIV-NEXT:    stw r25, 324(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stxv v30, 240(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-32BIT-P9-PRIV-NEXT:    stw r26, 328(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stxv v31, 256(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-32BIT-P9-PRIV-NEXT:    stw r27, 332(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stw r28, 336(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stw r29, 340(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stw r30, 344(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stw r31, 348(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f14, 352(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f15, 360(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f16, 368(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f17, 376(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f18, 384(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f19, 392(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f20, 400(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f21, 408(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f22, 416(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f23, 424(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f24, 432(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f25, 440(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f26, 448(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f27, 456(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f28, 464(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f29, 472(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f30, 480(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-32BIT-P9-PRIV-NEXT:    stfd f31, 488(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-32BIT-P9-PRIV-NEXT:    stw r3, 64(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    stw r4, 68(r1)
 ; BE-32BIT-P9-PRIV-NEXT:    #APP
 ; BE-32BIT-P9-PRIV-NEXT:    nop
 ; BE-32BIT-P9-PRIV-NEXT:    #NO_APP
 ; BE-32BIT-P9-PRIV-NEXT:    addi r3, r1, 68
 ; BE-32BIT-P9-PRIV-NEXT:    bl .callee2[PR]
 ; BE-32BIT-P9-PRIV-NEXT:    nop
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r4, 64(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lxv v31, 256(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-32BIT-P9-PRIV-NEXT:    lxv v30, 240(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-32BIT-P9-PRIV-NEXT:    lxv v29, 224(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-32BIT-P9-PRIV-NEXT:    lxv v28, 208(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-32BIT-P9-PRIV-NEXT:    lxv v27, 192(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-32BIT-P9-PRIV-NEXT:    lxv v26, 176(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-32BIT-P9-PRIV-NEXT:    lxv v25, 160(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-32BIT-P9-PRIV-NEXT:    lxv v24, 144(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-32BIT-P9-PRIV-NEXT:    lxv v23, 128(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-32BIT-P9-PRIV-NEXT:    lxv v22, 112(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-32BIT-P9-PRIV-NEXT:    lxv v21, 96(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-32BIT-P9-PRIV-NEXT:    lxv v20, 80(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f31, 488(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f30, 480(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f29, 472(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f28, 464(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f27, 456(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r31, 348(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r30, 344(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r29, 340(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f26, 448(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r28, 336(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r27, 332(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r26, 328(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f25, 440(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r25, 324(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r24, 320(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r23, 316(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f24, 432(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r22, 312(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r21, 308(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r4, 16(r4)
 ; BE-32BIT-P9-PRIV-NEXT:    add r3, r4, r3
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f23, 424(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f22, 416(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r20, 304(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r19, 300(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r18, 296(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r17, 292(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r16, 288(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r15, 284(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r14, 280(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r13, 276(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f21, 408(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f20, 400(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f19, 392(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f18, 384(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f17, 376(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f16, 368(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f15, 360(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-32BIT-P9-PRIV-NEXT:    lfd f14, 352(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-PRIV-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-32BIT-P9-PRIV-NEXT:    addi r1, r1, 496
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r0, 8(r1)
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r12, 4(r1)
 ; BE-32BIT-P9-PRIV-NEXT:    mtlr r0
 ; BE-32BIT-P9-PRIV-NEXT:    hashchkp r0, -424(r1)
 ; BE-32BIT-P9-PRIV-NEXT:    mtocrf 32, r12
 ; BE-32BIT-P9-PRIV-NEXT:    mtocrf 16, r12
 ; BE-32BIT-P9-PRIV-NEXT:    mtocrf 8, r12
 ; BE-32BIT-P9-PRIV-NEXT:    blr
 ;
 ; BE-32BIT-P8-PRIV-LABEL: spill:
 ; BE-32BIT-P8-PRIV:       # %bb.0: # %entry
 ; BE-32BIT-P8-PRIV-NEXT:    mfcr r12
 ; BE-32BIT-P8-PRIV-NEXT:    mflr r0
 ; BE-32BIT-P8-PRIV-NEXT:    stw r0, 8(r1)
 ; BE-32BIT-P8-PRIV-NEXT:    hashstp r0, -424(r1)
 ; BE-32BIT-P8-PRIV-NEXT:    stw r12, 4(r1)
 ; BE-32BIT-P8-PRIV-NEXT:    stwu r1, -496(r1)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 80
 ; BE-32BIT-P8-PRIV-NEXT:    stw r13, 276(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stw r14, 280(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stxvd2x v20, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 96
 ; BE-32BIT-P8-PRIV-NEXT:    stw r15, 284(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stxvd2x v21, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 112
 ; BE-32BIT-P8-PRIV-NEXT:    stw r16, 288(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stxvd2x v22, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 128
 ; BE-32BIT-P8-PRIV-NEXT:    stw r17, 292(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stxvd2x v23, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 144
 ; BE-32BIT-P8-PRIV-NEXT:    stw r18, 296(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stxvd2x v24, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 160
 ; BE-32BIT-P8-PRIV-NEXT:    stw r19, 300(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stxvd2x v25, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 176
 ; BE-32BIT-P8-PRIV-NEXT:    stw r20, 304(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stxvd2x v26, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 192
 ; BE-32BIT-P8-PRIV-NEXT:    stw r21, 308(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stxvd2x v27, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 208
 ; BE-32BIT-P8-PRIV-NEXT:    stw r22, 312(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stxvd2x v28, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 224
 ; BE-32BIT-P8-PRIV-NEXT:    stw r23, 316(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stxvd2x v29, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 240
 ; BE-32BIT-P8-PRIV-NEXT:    stw r24, 320(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stxvd2x v30, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 256
 ; BE-32BIT-P8-PRIV-NEXT:    stw r25, 324(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stxvd2x v31, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r4, 12(r3)
 ; BE-32BIT-P8-PRIV-NEXT:    stw r26, 328(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stw r27, 332(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stw r28, 336(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stw r29, 340(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stw r30, 344(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stw r31, 348(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f14, 352(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f15, 360(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f16, 368(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f17, 376(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f18, 384(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f19, 392(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f20, 400(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f21, 408(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f22, 416(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f23, 424(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f24, 432(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f25, 440(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f26, 448(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f27, 456(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f28, 464(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f29, 472(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f30, 480(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-32BIT-P8-PRIV-NEXT:    stfd f31, 488(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-32BIT-P8-PRIV-NEXT:    stw r3, 64(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    stw r4, 68(r1)
 ; BE-32BIT-P8-PRIV-NEXT:    #APP
 ; BE-32BIT-P8-PRIV-NEXT:    nop
 ; BE-32BIT-P8-PRIV-NEXT:    #NO_APP
 ; BE-32BIT-P8-PRIV-NEXT:    addi r3, r1, 68
 ; BE-32BIT-P8-PRIV-NEXT:    bl .callee2[PR]
 ; BE-32BIT-P8-PRIV-NEXT:    nop
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r4, 64(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f31, 488(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f30, 480(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r31, 348(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f29, 472(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f28, 464(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r30, 344(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r29, 340(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r4, 16(r4)
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f27, 456(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f26, 448(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r28, 336(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f25, 440(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f24, 432(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r27, 332(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r26, 328(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    add r3, r4, r3
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 256
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f23, 424(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f22, 416(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r25, 324(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r24, 320(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lxvd2x v31, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 240
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f21, 408(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r23, 316(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r22, 312(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lxvd2x v30, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 224
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f20, 400(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r21, 308(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r20, 304(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lxvd2x v29, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 208
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f19, 392(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r19, 300(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r18, 296(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lxvd2x v28, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 192
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f18, 384(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r17, 292(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r16, 288(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lxvd2x v27, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 176
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f17, 376(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r15, 284(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r14, 280(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lxvd2x v26, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 160
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f16, 368(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r13, 276(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-PRIV-NEXT:    lxvd2x v25, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 144
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f15, 360(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-32BIT-P8-PRIV-NEXT:    lxvd2x v24, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 128
 ; BE-32BIT-P8-PRIV-NEXT:    lfd f14, 352(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-32BIT-P8-PRIV-NEXT:    lxvd2x v23, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 112
 ; BE-32BIT-P8-PRIV-NEXT:    lxvd2x v22, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 96
 ; BE-32BIT-P8-PRIV-NEXT:    lxvd2x v21, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-32BIT-P8-PRIV-NEXT:    li r4, 80
 ; BE-32BIT-P8-PRIV-NEXT:    lxvd2x v20, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-PRIV-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-32BIT-P8-PRIV-NEXT:    addi r1, r1, 496
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r0, 8(r1)
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r12, 4(r1)
 ; BE-32BIT-P8-PRIV-NEXT:    mtocrf 32, r12
 ; BE-32BIT-P8-PRIV-NEXT:    hashchkp r0, -424(r1)
 ; BE-32BIT-P8-PRIV-NEXT:    mtlr r0
 ; BE-32BIT-P8-PRIV-NEXT:    mtocrf 16, r12
 ; BE-32BIT-P8-PRIV-NEXT:    mtocrf 8, r12

llvm/test/CodeGen/PowerPC/ppc64-rop-protection.ll

 ; LE-P10-NEXT:    std r25, 344(r1) # 8-byte Folded Spill
 ; LE-P10-NEXT:    std r26, 352(r1) # 8-byte Folded Spill
 ; LE-P10-NEXT:    std r27, 360(r1) # 8-byte Folded Spill
 ; LE-P10-NEXT:    std r28, 368(r1) # 8-byte Folded Spill
 ; LE-P10-NEXT:    std r29, 376(r1) # 8-byte Folded Spill
 ; LE-P10-NEXT:    std r30, 384(r1) # 8-byte Folded Spill
 ; LE-P10-NEXT:    std r31, 392(r1) # 8-byte Folded Spill
 ; LE-P10-NEXT:    stfd f14, 400(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F14(VSR14)
 ; LE-P10-NEXT:    stfd f15, 408(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F15(VSR15)
 ; LE-P10-NEXT:    stfd f16, 416(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F16(VSR16)
 ; LE-P10-NEXT:    stfd f17, 424(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F17(VSR17)
 ; LE-P10-NEXT:    stfd f18, 432(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F18(VSR18)
 ; LE-P10-NEXT:    stfd f19, 440(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F19(VSR19)
 ; LE-P10-NEXT:    stfd f20, 448(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F20(VSR20)
 ; LE-P10-NEXT:    stfd f21, 456(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F21(VSR21)
 ; LE-P10-NEXT:    stfd f22, 464(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F22(VSR22)
 ; LE-P10-NEXT:    stfd f23, 472(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F23(VSR23)
 ; LE-P10-NEXT:    stfd f24, 480(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F24(VSR24)
 ; LE-P10-NEXT:    stfd f25, 488(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F25(VSR25)
 ; LE-P10-NEXT:    stfd f26, 496(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F26(VSR26)
 ; LE-P10-NEXT:    stfd f27, 504(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F27(VSR27)
 ; LE-P10-NEXT:    stfd f28, 512(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F28(VSR28)
 ; LE-P10-NEXT:    stfd f29, 520(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F29(VSR29)
 ; LE-P10-NEXT:    stfd f30, 528(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F30(VSR30)
 ; LE-P10-NEXT:    stfd f31, 536(r1) # 8-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: F31(VSR31)
 ; LE-P10-NEXT:    stxv v20, 64(r1) # 16-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: V20(VSR52)
 ; LE-P10-NEXT:    stxv v21, 80(r1) # 16-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: V21(VSR53)
 ; LE-P10-NEXT:    stxv v22, 96(r1) # 16-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: V22(VSR54)
 ; LE-P10-NEXT:    stxv v23, 112(r1) # 16-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: V23(VSR55)
 ; LE-P10-NEXT:    stxv v24, 128(r1) # 16-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: V24(VSR56)
 ; LE-P10-NEXT:    stxv v25, 144(r1) # 16-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: V25(VSR57)
 ; LE-P10-NEXT:    stxv v26, 160(r1) # 16-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: V26(VSR58)
 ; LE-P10-NEXT:    stxv v27, 176(r1) # 16-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: V27(VSR59)
 ; LE-P10-NEXT:    stxv v28, 192(r1) # 16-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: V28(VSR60)
 ; LE-P10-NEXT:    stxv v29, 208(r1) # 16-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: V29(VSR61)
 ; LE-P10-NEXT:    stxv v30, 224(r1) # 16-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: V30(VSR62)
 ; LE-P10-NEXT:    stxv v31, 240(r1) # 16-byte Folded Spill
+; LE-P10-NEXT:    # Vec Uses: V31(VSR63)
 ; LE-P10-NEXT:    std r3, 40(r1) # 8-byte Folded Spill
 ; LE-P10-NEXT:    stw r4, 52(r1)
 ; LE-P10-NEXT:    #APP
 ; LE-P10-NEXT:    nop
 ; LE-P10-NEXT:    #NO_APP
 ; LE-P10-NEXT:    addi r3, r1, 52
 ; LE-P10-NEXT:    bl callee2@notoc
 ; LE-P10-NEXT:    ld r4, 40(r1) # 8-byte Folded Reload
 ; LE-P10-NEXT:    lxv v31, 240(r1) # 16-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: V31(VSR63)
 ; LE-P10-NEXT:    lxv v30, 224(r1) # 16-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: V30(VSR62)
 ; LE-P10-NEXT:    lxv v29, 208(r1) # 16-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: V29(VSR61)
 ; LE-P10-NEXT:    lxv v28, 192(r1) # 16-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: V28(VSR60)
 ; LE-P10-NEXT:    lxv v27, 176(r1) # 16-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: V27(VSR59)
 ; LE-P10-NEXT:    lxv v26, 160(r1) # 16-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: V26(VSR58)
 ; LE-P10-NEXT:    lxv v25, 144(r1) # 16-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: V25(VSR57)
 ; LE-P10-NEXT:    lxv v24, 128(r1) # 16-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: V24(VSR56)
 ; LE-P10-NEXT:    lxv v23, 112(r1) # 16-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: V23(VSR55)
 ; LE-P10-NEXT:    lxv v22, 96(r1) # 16-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: V22(VSR54)
 ; LE-P10-NEXT:    lxv v21, 80(r1) # 16-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: V21(VSR53)
 ; LE-P10-NEXT:    lxv v20, 64(r1) # 16-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: V20(VSR52)
 ; LE-P10-NEXT:    lfd f31, 536(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F31(VSR31)
 ; LE-P10-NEXT:    lfd f30, 528(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F30(VSR30)
 ; LE-P10-NEXT:    lfd f29, 520(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F29(VSR29)
 ; LE-P10-NEXT:    lfd f28, 512(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F28(VSR28)
 ; LE-P10-NEXT:    lfd f27, 504(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F27(VSR27)
 ; LE-P10-NEXT:    lfd f26, 496(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F26(VSR26)
 ; LE-P10-NEXT:    lfd f25, 488(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F25(VSR25)
 ; LE-P10-NEXT:    lfd f24, 480(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F24(VSR24)
 ; LE-P10-NEXT:    lfd f23, 472(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F23(VSR23)
 ; LE-P10-NEXT:    lfd f22, 464(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F22(VSR22)
 ; LE-P10-NEXT:    lfd f21, 456(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F21(VSR21)
 ; LE-P10-NEXT:    lfd f20, 448(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F20(VSR20)
 ; LE-P10-NEXT:    lfd f19, 440(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F19(VSR19)
 ; LE-P10-NEXT:    lfd f18, 432(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F18(VSR18)
 ; LE-P10-NEXT:    lfd f17, 424(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F17(VSR17)
 ; LE-P10-NEXT:    lfd f16, 416(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F16(VSR16)
 ; LE-P10-NEXT:    lfd f15, 408(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F15(VSR15)
 ; LE-P10-NEXT:    lfd f14, 400(r1) # 8-byte Folded Reload
+; LE-P10-NEXT:    # Vec Defs: F14(VSR14)
 ; LE-P10-NEXT:    ld r31, 392(r1) # 8-byte Folded Reload
 ; LE-P10-NEXT:    ld r30, 384(r1) # 8-byte Folded Reload
 ; LE-P10-NEXT:    ld r29, 376(r1) # 8-byte Folded Reload
 ; LE-P10-NEXT:    ld r28, 368(r1) # 8-byte Folded Reload
 ; LE-P10-NEXT:    ld r27, 360(r1) # 8-byte Folded Reload
 ; LE-P10-NEXT:    ld r26, 352(r1) # 8-byte Folded Reload
 ; LE-P10-NEXT:    ld r25, 344(r1) # 8-byte Folded Reload
 ; LE-P10-NEXT:    ld r24, 336(r1) # 8-byte Folded Reload

 ; LE-P9-NEXT:    std r0, 16(r1)
 ; LE-P9-NEXT:    hashst r0, -488(r1)
 ; LE-P9-NEXT:    stw r12, 8(r1)
 ; LE-P9-NEXT:    stdu r1, -544(r1)
 ; LE-P9-NEXT:    lwz r4, 12(r3)
 ; LE-P9-NEXT:    std r14, 256(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    std r15, 264(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    stxv v20, 64(r1) # 16-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: V20(VSR52)
 ; LE-P9-NEXT:    stxv v21, 80(r1) # 16-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: V21(VSR53)
 ; LE-P9-NEXT:    stxv v22, 96(r1) # 16-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: V22(VSR54)
 ; LE-P9-NEXT:    std r16, 272(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    std r17, 280(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    stxv v23, 112(r1) # 16-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: V23(VSR55)
 ; LE-P9-NEXT:    std r18, 288(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    stxv v24, 128(r1) # 16-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: V24(VSR56)
 ; LE-P9-NEXT:    std r19, 296(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    stxv v25, 144(r1) # 16-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: V25(VSR57)
 ; LE-P9-NEXT:    std r20, 304(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    std r21, 312(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    stxv v26, 160(r1) # 16-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: V26(VSR58)
 ; LE-P9-NEXT:    std r22, 320(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    stxv v27, 176(r1) # 16-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: V27(VSR59)
 ; LE-P9-NEXT:    std r23, 328(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    stxv v28, 192(r1) # 16-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: V28(VSR60)
 ; LE-P9-NEXT:    std r24, 336(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    std r25, 344(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    stxv v29, 208(r1) # 16-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: V29(VSR61)
 ; LE-P9-NEXT:    std r26, 352(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    stxv v30, 224(r1) # 16-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: V30(VSR62)
 ; LE-P9-NEXT:    std r27, 360(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    stxv v31, 240(r1) # 16-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: V31(VSR63)
 ; LE-P9-NEXT:    std r28, 368(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    std r29, 376(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    std r30, 384(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    std r31, 392(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    stfd f14, 400(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F14(VSR14)
 ; LE-P9-NEXT:    stfd f15, 408(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F15(VSR15)
 ; LE-P9-NEXT:    stfd f16, 416(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F16(VSR16)
 ; LE-P9-NEXT:    stfd f17, 424(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F17(VSR17)
 ; LE-P9-NEXT:    stfd f18, 432(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F18(VSR18)
 ; LE-P9-NEXT:    stfd f19, 440(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F19(VSR19)
 ; LE-P9-NEXT:    stfd f20, 448(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F20(VSR20)
 ; LE-P9-NEXT:    stfd f21, 456(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F21(VSR21)
 ; LE-P9-NEXT:    stfd f22, 464(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F22(VSR22)
 ; LE-P9-NEXT:    stfd f23, 472(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F23(VSR23)
 ; LE-P9-NEXT:    stfd f24, 480(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F24(VSR24)
 ; LE-P9-NEXT:    stfd f25, 488(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F25(VSR25)
 ; LE-P9-NEXT:    stfd f26, 496(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F26(VSR26)
 ; LE-P9-NEXT:    stfd f27, 504(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F27(VSR27)
 ; LE-P9-NEXT:    stfd f28, 512(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F28(VSR28)
 ; LE-P9-NEXT:    stfd f29, 520(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F29(VSR29)
 ; LE-P9-NEXT:    stfd f30, 528(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F30(VSR30)
 ; LE-P9-NEXT:    stfd f31, 536(r1) # 8-byte Folded Spill
+; LE-P9-NEXT:    # Vec Uses: F31(VSR31)
 ; LE-P9-NEXT:    std r3, 40(r1) # 8-byte Folded Spill
 ; LE-P9-NEXT:    stw r4, 52(r1)
 ; LE-P9-NEXT:    #APP
 ; LE-P9-NEXT:    nop
 ; LE-P9-NEXT:    #NO_APP
 ; LE-P9-NEXT:    addi r3, r1, 52
 ; LE-P9-NEXT:    bl callee2
 ; LE-P9-NEXT:    nop
 ; LE-P9-NEXT:    ld r4, 40(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    lxv v31, 240(r1) # 16-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: V31(VSR63)
 ; LE-P9-NEXT:    lxv v30, 224(r1) # 16-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: V30(VSR62)
 ; LE-P9-NEXT:    lxv v29, 208(r1) # 16-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: V29(VSR61)
 ; LE-P9-NEXT:    lxv v28, 192(r1) # 16-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: V28(VSR60)
 ; LE-P9-NEXT:    lxv v27, 176(r1) # 16-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: V27(VSR59)
 ; LE-P9-NEXT:    lxv v26, 160(r1) # 16-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: V26(VSR58)
 ; LE-P9-NEXT:    lxv v25, 144(r1) # 16-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: V25(VSR57)
 ; LE-P9-NEXT:    lxv v24, 128(r1) # 16-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: V24(VSR56)
 ; LE-P9-NEXT:    lxv v23, 112(r1) # 16-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: V23(VSR55)
 ; LE-P9-NEXT:    lxv v22, 96(r1) # 16-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: V22(VSR54)
 ; LE-P9-NEXT:    lxv v21, 80(r1) # 16-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: V21(VSR53)
 ; LE-P9-NEXT:    lxv v20, 64(r1) # 16-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: V20(VSR52)
 ; LE-P9-NEXT:    lfd f31, 536(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F31(VSR31)
 ; LE-P9-NEXT:    lfd f30, 528(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F30(VSR30)
 ; LE-P9-NEXT:    lfd f29, 520(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F29(VSR29)
 ; LE-P9-NEXT:    lfd f28, 512(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F28(VSR28)
 ; LE-P9-NEXT:    lfd f27, 504(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F27(VSR27)
 ; LE-P9-NEXT:    ld r31, 392(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    ld r30, 384(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    ld r29, 376(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    lfd f26, 496(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F26(VSR26)
 ; LE-P9-NEXT:    ld r28, 368(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    ld r27, 360(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    ld r26, 352(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    lfd f25, 488(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F25(VSR25)
 ; LE-P9-NEXT:    ld r25, 344(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    ld r24, 336(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    ld r23, 328(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    lfd f24, 480(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F24(VSR24)
 ; LE-P9-NEXT:    ld r22, 320(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    ld r21, 312(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    lwz r4, 16(r4)
 ; LE-P9-NEXT:    add r3, r4, r3
 ; LE-P9-NEXT:    lfd f23, 472(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F23(VSR23)
 ; LE-P9-NEXT:    lfd f22, 464(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F22(VSR22)
 ; LE-P9-NEXT:    ld r20, 304(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    ld r19, 296(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    ld r18, 288(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    ld r17, 280(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    ld r16, 272(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    ld r15, 264(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    ld r14, 256(r1) # 8-byte Folded Reload
 ; LE-P9-NEXT:    lfd f21, 456(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F21(VSR21)
 ; LE-P9-NEXT:    lfd f20, 448(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F20(VSR20)
 ; LE-P9-NEXT:    lfd f19, 440(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F19(VSR19)
 ; LE-P9-NEXT:    lfd f18, 432(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F18(VSR18)
 ; LE-P9-NEXT:    lfd f17, 424(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F17(VSR17)
 ; LE-P9-NEXT:    lfd f16, 416(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F16(VSR16)
 ; LE-P9-NEXT:    lfd f15, 408(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F15(VSR15)
 ; LE-P9-NEXT:    lfd f14, 400(r1) # 8-byte Folded Reload
+; LE-P9-NEXT:    # Vec Defs: F14(VSR14)
 ; LE-P9-NEXT:    clrldi r3, r3, 32
 ; LE-P9-NEXT:    addi r1, r1, 544
 ; LE-P9-NEXT:    ld r0, 16(r1)
 ; LE-P9-NEXT:    lwz r12, 8(r1)
 ; LE-P9-NEXT:    mtlr r0
 ; LE-P9-NEXT:    hashchk r0, -488(r1)
 ; LE-P9-NEXT:    mtocrf 32, r12
 ; LE-P9-NEXT:    mtocrf 16, r12

 ; LE-P8-NEXT:    stw r12, 8(r1)
 ; LE-P8-NEXT:    stdu r1, -544(r1)
 ; LE-P8-NEXT:    li r4, 64
 ; LE-P8-NEXT:    std r14, 256(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    std r15, 264(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    std r16, 272(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    std r17, 280(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    stxvd2x v20, r1, r4 # 16-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: V20(VSR52)
 ; LE-P8-NEXT:    li r4, 80
 ; LE-P8-NEXT:    std r18, 288(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    std r19, 296(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    std r20, 304(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    std r21, 312(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    stxvd2x v21, r1, r4 # 16-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: V21(VSR53)
 ; LE-P8-NEXT:    li r4, 96
 ; LE-P8-NEXT:    std r22, 320(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    std r23, 328(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    std r24, 336(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    std r25, 344(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    std r26, 352(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    std r27, 360(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    std r28, 368(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    std r29, 376(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    std r30, 384(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    std r31, 392(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    std r3, 40(r1) # 8-byte Folded Spill
 ; LE-P8-NEXT:    stxvd2x v22, r1, r4 # 16-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: V22(VSR54)
 ; LE-P8-NEXT:    li r4, 112
 ; LE-P8-NEXT:    stxvd2x v23, r1, r4 # 16-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: V23(VSR55)
 ; LE-P8-NEXT:    li r4, 128
 ; LE-P8-NEXT:    stfd f14, 400(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F14(VSR14)
 ; LE-P8-NEXT:    stxvd2x v24, r1, r4 # 16-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: V24(VSR56)
 ; LE-P8-NEXT:    li r4, 144
 ; LE-P8-NEXT:    stfd f15, 408(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F15(VSR15)
 ; LE-P8-NEXT:    stxvd2x v25, r1, r4 # 16-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: V25(VSR57)
 ; LE-P8-NEXT:    li r4, 160
 ; LE-P8-NEXT:    stfd f16, 416(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F16(VSR16)
 ; LE-P8-NEXT:    stxvd2x v26, r1, r4 # 16-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: V26(VSR58)
 ; LE-P8-NEXT:    li r4, 176
 ; LE-P8-NEXT:    stfd f17, 424(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F17(VSR17)
 ; LE-P8-NEXT:    stxvd2x v27, r1, r4 # 16-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: V27(VSR59)
 ; LE-P8-NEXT:    li r4, 192
 ; LE-P8-NEXT:    stfd f18, 432(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F18(VSR18)
 ; LE-P8-NEXT:    stxvd2x v28, r1, r4 # 16-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: V28(VSR60)
 ; LE-P8-NEXT:    li r4, 208
 ; LE-P8-NEXT:    stfd f19, 440(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F19(VSR19)
 ; LE-P8-NEXT:    stxvd2x v29, r1, r4 # 16-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: V29(VSR61)
 ; LE-P8-NEXT:    li r4, 224
 ; LE-P8-NEXT:    stfd f20, 448(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F20(VSR20)
 ; LE-P8-NEXT:    stxvd2x v30, r1, r4 # 16-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: V30(VSR62)
 ; LE-P8-NEXT:    li r4, 240
 ; LE-P8-NEXT:    stfd f21, 456(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F21(VSR21)
 ; LE-P8-NEXT:    stxvd2x v31, r1, r4 # 16-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: V31(VSR63)
 ; LE-P8-NEXT:    lwz r4, 12(r3)
 ; LE-P8-NEXT:    stfd f22, 464(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F22(VSR22)
 ; LE-P8-NEXT:    stfd f23, 472(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F23(VSR23)
 ; LE-P8-NEXT:    stfd f24, 480(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F24(VSR24)
 ; LE-P8-NEXT:    stfd f25, 488(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F25(VSR25)
 ; LE-P8-NEXT:    stfd f26, 496(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F26(VSR26)
 ; LE-P8-NEXT:    stfd f27, 504(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F27(VSR27)
 ; LE-P8-NEXT:    stfd f28, 512(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F28(VSR28)
 ; LE-P8-NEXT:    stfd f29, 520(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F29(VSR29)
 ; LE-P8-NEXT:    stfd f30, 528(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F30(VSR30)
 ; LE-P8-NEXT:    stfd f31, 536(r1) # 8-byte Folded Spill
+; LE-P8-NEXT:    # Vec Uses: F31(VSR31)
 ; LE-P8-NEXT:    stw r4, 52(r1)
 ; LE-P8-NEXT:    #APP
 ; LE-P8-NEXT:    nop
 ; LE-P8-NEXT:    #NO_APP
 ; LE-P8-NEXT:    addi r3, r1, 52
 ; LE-P8-NEXT:    bl callee2
 ; LE-P8-NEXT:    nop
 ; LE-P8-NEXT:    ld r4, 40(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    lfd f31, 536(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F31(VSR31)
 ; LE-P8-NEXT:    lfd f30, 528(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F30(VSR30)
 ; LE-P8-NEXT:    ld r31, 392(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    lfd f29, 520(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F29(VSR29)
 ; LE-P8-NEXT:    lfd f28, 512(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F28(VSR28)
 ; LE-P8-NEXT:    ld r30, 384(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    ld r29, 376(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    lwz r4, 16(r4)
 ; LE-P8-NEXT:    lfd f27, 504(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F27(VSR27)
 ; LE-P8-NEXT:    lfd f26, 496(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F26(VSR26)
 ; LE-P8-NEXT:    ld r28, 368(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    lfd f25, 488(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F25(VSR25)
 ; LE-P8-NEXT:    lfd f24, 480(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F24(VSR24)
 ; LE-P8-NEXT:    ld r27, 360(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    ld r26, 352(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    add r3, r4, r3
 ; LE-P8-NEXT:    li r4, 240
 ; LE-P8-NEXT:    lfd f23, 472(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F23(VSR23)
 ; LE-P8-NEXT:    lfd f22, 464(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F22(VSR22)
 ; LE-P8-NEXT:    ld r25, 344(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    ld r24, 336(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    lxvd2x v31, r1, r4 # 16-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; LE-P8-NEXT:    li r4, 224
 ; LE-P8-NEXT:    lfd f21, 456(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F21(VSR21)
 ; LE-P8-NEXT:    ld r23, 328(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    ld r22, 320(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    clrldi r3, r3, 32
 ; LE-P8-NEXT:    lxvd2x v30, r1, r4 # 16-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: V30(VSR62)
 ; LE-P8-NEXT:    li r4, 208
 ; LE-P8-NEXT:    lfd f20, 448(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F20(VSR20)
 ; LE-P8-NEXT:    ld r21, 312(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    ld r20, 304(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    lxvd2x v29, r1, r4 # 16-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: V29(VSR61)
 ; LE-P8-NEXT:    li r4, 192
 ; LE-P8-NEXT:    lfd f19, 440(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F19(VSR19)
 ; LE-P8-NEXT:    ld r19, 296(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    ld r18, 288(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    lxvd2x v28, r1, r4 # 16-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: V28(VSR60)
 ; LE-P8-NEXT:    li r4, 176
 ; LE-P8-NEXT:    lfd f18, 432(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F18(VSR18)
 ; LE-P8-NEXT:    ld r17, 280(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    ld r16, 272(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    lxvd2x v27, r1, r4 # 16-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: V27(VSR59)
 ; LE-P8-NEXT:    li r4, 160
 ; LE-P8-NEXT:    lfd f17, 424(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F17(VSR17)
 ; LE-P8-NEXT:    ld r15, 264(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    ld r14, 256(r1) # 8-byte Folded Reload
 ; LE-P8-NEXT:    lxvd2x v26, r1, r4 # 16-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: V26(VSR58)
 ; LE-P8-NEXT:    li r4, 144
 ; LE-P8-NEXT:    lfd f16, 416(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F16(VSR16)
 ; LE-P8-NEXT:    lxvd2x v25, r1, r4 # 16-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: V25(VSR57)
 ; LE-P8-NEXT:    li r4, 128
 ; LE-P8-NEXT:    lfd f15, 408(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F15(VSR15)
 ; LE-P8-NEXT:    lxvd2x v24, r1, r4 # 16-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: V24(VSR56)
 ; LE-P8-NEXT:    li r4, 112
 ; LE-P8-NEXT:    lfd f14, 400(r1) # 8-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: F14(VSR14)
 ; LE-P8-NEXT:    lxvd2x v23, r1, r4 # 16-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: V23(VSR55)
 ; LE-P8-NEXT:    li r4, 96
 ; LE-P8-NEXT:    lxvd2x v22, r1, r4 # 16-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: V22(VSR54)
 ; LE-P8-NEXT:    li r4, 80
 ; LE-P8-NEXT:    lxvd2x v21, r1, r4 # 16-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: V21(VSR53)
 ; LE-P8-NEXT:    li r4, 64
 ; LE-P8-NEXT:    lxvd2x v20, r1, r4 # 16-byte Folded Reload
+; LE-P8-NEXT:    # Vec Defs: V20(VSR52)
 ; LE-P8-NEXT:    addi r1, r1, 544
 ; LE-P8-NEXT:    ld r0, 16(r1)
 ; LE-P8-NEXT:    lwz r12, 8(r1)
 ; LE-P8-NEXT:    mtocrf 32, r12
 ; LE-P8-NEXT:    hashchk r0, -488(r1)
 ; LE-P8-NEXT:    mtlr r0
 ; LE-P8-NEXT:    mtocrf 16, r12
 ; LE-P8-NEXT:    mtocrf 8, r12

 ; LE-P10-O0-NEXT:    std r25, 344(r1) # 8-byte Folded Spill
 ; LE-P10-O0-NEXT:    std r26, 352(r1) # 8-byte Folded Spill
 ; LE-P10-O0-NEXT:    std r27, 360(r1) # 8-byte Folded Spill
 ; LE-P10-O0-NEXT:    std r28, 368(r1) # 8-byte Folded Spill
 ; LE-P10-O0-NEXT:    std r29, 376(r1) # 8-byte Folded Spill
 ; LE-P10-O0-NEXT:    std r30, 384(r1) # 8-byte Folded Spill
 ; LE-P10-O0-NEXT:    std r31, 392(r1) # 8-byte Folded Spill
 ; LE-P10-O0-NEXT:    stfd f14, 400(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F14(VSR14)
 ; LE-P10-O0-NEXT:    stfd f15, 408(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F15(VSR15)
 ; LE-P10-O0-NEXT:    stfd f16, 416(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F16(VSR16)
 ; LE-P10-O0-NEXT:    stfd f17, 424(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F17(VSR17)
 ; LE-P10-O0-NEXT:    stfd f18, 432(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F18(VSR18)
 ; LE-P10-O0-NEXT:    stfd f19, 440(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F19(VSR19)
 ; LE-P10-O0-NEXT:    stfd f20, 448(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F20(VSR20)
 ; LE-P10-O0-NEXT:    stfd f21, 456(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F21(VSR21)
 ; LE-P10-O0-NEXT:    stfd f22, 464(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F22(VSR22)
 ; LE-P10-O0-NEXT:    stfd f23, 472(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F23(VSR23)
 ; LE-P10-O0-NEXT:    stfd f24, 480(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F24(VSR24)
 ; LE-P10-O0-NEXT:    stfd f25, 488(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F25(VSR25)
 ; LE-P10-O0-NEXT:    stfd f26, 496(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F26(VSR26)
 ; LE-P10-O0-NEXT:    stfd f27, 504(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F27(VSR27)
 ; LE-P10-O0-NEXT:    stfd f28, 512(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F28(VSR28)
 ; LE-P10-O0-NEXT:    stfd f29, 520(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F29(VSR29)
 ; LE-P10-O0-NEXT:    stfd f30, 528(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F30(VSR30)
 ; LE-P10-O0-NEXT:    stfd f31, 536(r1) # 8-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: F31(VSR31)
 ; LE-P10-O0-NEXT:    stxv v20, 64(r1) # 16-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: V20(VSR52)
 ; LE-P10-O0-NEXT:    stxv v21, 80(r1) # 16-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: V21(VSR53)
 ; LE-P10-O0-NEXT:    stxv v22, 96(r1) # 16-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: V22(VSR54)
 ; LE-P10-O0-NEXT:    stxv v23, 112(r1) # 16-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: V23(VSR55)
 ; LE-P10-O0-NEXT:    stxv v24, 128(r1) # 16-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: V24(VSR56)
 ; LE-P10-O0-NEXT:    stxv v25, 144(r1) # 16-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: V25(VSR57)
 ; LE-P10-O0-NEXT:    stxv v26, 160(r1) # 16-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: V26(VSR58)
 ; LE-P10-O0-NEXT:    stxv v27, 176(r1) # 16-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: V27(VSR59)
 ; LE-P10-O0-NEXT:    stxv v28, 192(r1) # 16-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: V28(VSR60)
 ; LE-P10-O0-NEXT:    stxv v29, 208(r1) # 16-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: V29(VSR61)
 ; LE-P10-O0-NEXT:    stxv v30, 224(r1) # 16-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: V30(VSR62)
 ; LE-P10-O0-NEXT:    stxv v31, 240(r1) # 16-byte Folded Spill
+; LE-P10-O0-NEXT:    # Vec Uses: V31(VSR63)
 ; LE-P10-O0-NEXT:    std r3, 40(r1) # 8-byte Folded Spill
 ; LE-P10-O0-NEXT:    lwz r3, 12(r3)
 ; LE-P10-O0-NEXT:    stw r3, 52(r1)
 ; LE-P10-O0-NEXT:    #APP
 ; LE-P10-O0-NEXT:    nop
 ; LE-P10-O0-NEXT:    #NO_APP
 ; LE-P10-O0-NEXT:    addi r3, r1, 52
 ; LE-P10-O0-NEXT:    bl callee2@notoc
 ; LE-P10-O0-NEXT:    mr r4, r3
 ; LE-P10-O0-NEXT:    ld r3, 40(r1) # 8-byte Folded Reload
 ; LE-P10-O0-NEXT:    # kill: def $r4 killed $r4 killed $x4
 ; LE-P10-O0-NEXT:    lwz r3, 16(r3)
 ; LE-P10-O0-NEXT:    add r3, r3, r4
 ; LE-P10-O0-NEXT:    clrldi r3, r3, 32
 ; LE-P10-O0-NEXT:    lxv v31, 240(r1) # 16-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: V31(VSR63)
 ; LE-P10-O0-NEXT:    lxv v30, 224(r1) # 16-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: V30(VSR62)
 ; LE-P10-O0-NEXT:    lxv v29, 208(r1) # 16-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: V29(VSR61)
 ; LE-P10-O0-NEXT:    lxv v28, 192(r1) # 16-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: V28(VSR60)
 ; LE-P10-O0-NEXT:    lxv v27, 176(r1) # 16-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: V27(VSR59)
 ; LE-P10-O0-NEXT:    lxv v26, 160(r1) # 16-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: V26(VSR58)
 ; LE-P10-O0-NEXT:    lxv v25, 144(r1) # 16-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: V25(VSR57)
 ; LE-P10-O0-NEXT:    lxv v24, 128(r1) # 16-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: V24(VSR56)
 ; LE-P10-O0-NEXT:    lxv v23, 112(r1) # 16-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: V23(VSR55)
 ; LE-P10-O0-NEXT:    lxv v22, 96(r1) # 16-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: V22(VSR54)
 ; LE-P10-O0-NEXT:    lxv v21, 80(r1) # 16-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: V21(VSR53)
 ; LE-P10-O0-NEXT:    lxv v20, 64(r1) # 16-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: V20(VSR52)
 ; LE-P10-O0-NEXT:    lfd f31, 536(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F31(VSR31)
 ; LE-P10-O0-NEXT:    lfd f30, 528(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F30(VSR30)
 ; LE-P10-O0-NEXT:    lfd f29, 520(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F29(VSR29)
 ; LE-P10-O0-NEXT:    lfd f28, 512(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F28(VSR28)
 ; LE-P10-O0-NEXT:    lfd f27, 504(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F27(VSR27)
 ; LE-P10-O0-NEXT:    lfd f26, 496(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F26(VSR26)
 ; LE-P10-O0-NEXT:    lfd f25, 488(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F25(VSR25)
 ; LE-P10-O0-NEXT:    lfd f24, 480(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F24(VSR24)
 ; LE-P10-O0-NEXT:    lfd f23, 472(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F23(VSR23)
 ; LE-P10-O0-NEXT:    lfd f22, 464(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F22(VSR22)
 ; LE-P10-O0-NEXT:    lfd f21, 456(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F21(VSR21)
 ; LE-P10-O0-NEXT:    lfd f20, 448(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F20(VSR20)
 ; LE-P10-O0-NEXT:    lfd f19, 440(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F19(VSR19)
 ; LE-P10-O0-NEXT:    lfd f18, 432(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F18(VSR18)
 ; LE-P10-O0-NEXT:    lfd f17, 424(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F17(VSR17)
 ; LE-P10-O0-NEXT:    lfd f16, 416(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F16(VSR16)
 ; LE-P10-O0-NEXT:    lfd f15, 408(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F15(VSR15)
 ; LE-P10-O0-NEXT:    lfd f14, 400(r1) # 8-byte Folded Reload
+; LE-P10-O0-NEXT:    # Vec Defs: F14(VSR14)
 ; LE-P10-O0-NEXT:    ld r31, 392(r1) # 8-byte Folded Reload
 ; LE-P10-O0-NEXT:    ld r30, 384(r1) # 8-byte Folded Reload
 ; LE-P10-O0-NEXT:    ld r29, 376(r1) # 8-byte Folded Reload
 ; LE-P10-O0-NEXT:    ld r28, 368(r1) # 8-byte Folded Reload
 ; LE-P10-O0-NEXT:    ld r27, 360(r1) # 8-byte Folded Reload
 ; LE-P10-O0-NEXT:    ld r26, 352(r1) # 8-byte Folded Reload
 ; LE-P10-O0-NEXT:    ld r25, 344(r1) # 8-byte Folded Reload
 ; LE-P10-O0-NEXT:    ld r24, 336(r1) # 8-byte Folded Reload

 ; LE-P9-O0-NEXT:    std r25, 408(r1) # 8-byte Folded Spill
 ; LE-P9-O0-NEXT:    std r26, 416(r1) # 8-byte Folded Spill
 ; LE-P9-O0-NEXT:    std r27, 424(r1) # 8-byte Folded Spill
 ; LE-P9-O0-NEXT:    std r28, 432(r1) # 8-byte Folded Spill
 ; LE-P9-O0-NEXT:    std r29, 440(r1) # 8-byte Folded Spill
 ; LE-P9-O0-NEXT:    std r30, 448(r1) # 8-byte Folded Spill
 ; LE-P9-O0-NEXT:    std r31, 456(r1) # 8-byte Folded Spill
 ; LE-P9-O0-NEXT:    stfd f14, 464(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F14(VSR14)
 ; LE-P9-O0-NEXT:    stfd f15, 472(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F15(VSR15)
 ; LE-P9-O0-NEXT:    stfd f16, 480(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F16(VSR16)
 ; LE-P9-O0-NEXT:    stfd f17, 488(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F17(VSR17)
 ; LE-P9-O0-NEXT:    stfd f18, 496(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F18(VSR18)
 ; LE-P9-O0-NEXT:    stfd f19, 504(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F19(VSR19)
 ; LE-P9-O0-NEXT:    stfd f20, 512(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F20(VSR20)
 ; LE-P9-O0-NEXT:    stfd f21, 520(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F21(VSR21)
 ; LE-P9-O0-NEXT:    stfd f22, 528(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F22(VSR22)
 ; LE-P9-O0-NEXT:    stfd f23, 536(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F23(VSR23)
 ; LE-P9-O0-NEXT:    stfd f24, 544(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F24(VSR24)
 ; LE-P9-O0-NEXT:    stfd f25, 552(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F25(VSR25)
 ; LE-P9-O0-NEXT:    stfd f26, 560(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F26(VSR26)
 ; LE-P9-O0-NEXT:    stfd f27, 568(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F27(VSR27)
 ; LE-P9-O0-NEXT:    stfd f28, 576(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F28(VSR28)
 ; LE-P9-O0-NEXT:    stfd f29, 584(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F29(VSR29)
 ; LE-P9-O0-NEXT:    stfd f30, 592(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F30(VSR30)
 ; LE-P9-O0-NEXT:    stfd f31, 600(r1) # 8-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: F31(VSR31)
 ; LE-P9-O0-NEXT:    stxv v20, 128(r1) # 16-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: V20(VSR52)
 ; LE-P9-O0-NEXT:    stxv v21, 144(r1) # 16-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: V21(VSR53)
 ; LE-P9-O0-NEXT:    stxv v22, 160(r1) # 16-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: V22(VSR54)
 ; LE-P9-O0-NEXT:    stxv v23, 176(r1) # 16-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: V23(VSR55)
 ; LE-P9-O0-NEXT:    stxv v24, 192(r1) # 16-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: V24(VSR56)
 ; LE-P9-O0-NEXT:    stxv v25, 208(r1) # 16-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: V25(VSR57)
 ; LE-P9-O0-NEXT:    stxv v26, 224(r1) # 16-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: V26(VSR58)
 ; LE-P9-O0-NEXT:    stxv v27, 240(r1) # 16-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: V27(VSR59)
 ; LE-P9-O0-NEXT:    stxv v28, 256(r1) # 16-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: V28(VSR60)
 ; LE-P9-O0-NEXT:    stxv v29, 272(r1) # 16-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: V29(VSR61)
 ; LE-P9-O0-NEXT:    stxv v30, 288(r1) # 16-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: V30(VSR62)
 ; LE-P9-O0-NEXT:    stxv v31, 304(r1) # 16-byte Folded Spill
+; LE-P9-O0-NEXT:    # Vec Uses: V31(VSR63)
 ; LE-P9-O0-NEXT:    std r3, 104(r1) # 8-byte Folded Spill
 ; LE-P9-O0-NEXT:    lwz r3, 12(r3)
 ; LE-P9-O0-NEXT:    stw r3, 116(r1)
 ; LE-P9-O0-NEXT:    #APP
 ; LE-P9-O0-NEXT:    nop
 ; LE-P9-O0-NEXT:    #NO_APP
 ; LE-P9-O0-NEXT:    addi r3, r1, 116
 ; LE-P9-O0-NEXT:    bl callee2
 ; LE-P9-O0-NEXT:    nop
 ; LE-P9-O0-NEXT:    mr r4, r3
 ; LE-P9-O0-NEXT:    ld r3, 104(r1) # 8-byte Folded Reload
 ; LE-P9-O0-NEXT:    lwz r3, 16(r3)
 ; LE-P9-O0-NEXT:    add r3, r3, r4
 ; LE-P9-O0-NEXT:    clrldi r3, r3, 32
 ; LE-P9-O0-NEXT:    lxv v31, 304(r1) # 16-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: V31(VSR63)
 ; LE-P9-O0-NEXT:    lxv v30, 288(r1) # 16-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: V30(VSR62)
 ; LE-P9-O0-NEXT:    lxv v29, 272(r1) # 16-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: V29(VSR61)
 ; LE-P9-O0-NEXT:    lxv v28, 256(r1) # 16-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: V28(VSR60)
 ; LE-P9-O0-NEXT:    lxv v27, 240(r1) # 16-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: V27(VSR59)
 ; LE-P9-O0-NEXT:    lxv v26, 224(r1) # 16-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: V26(VSR58)
 ; LE-P9-O0-NEXT:    lxv v25, 208(r1) # 16-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: V25(VSR57)
 ; LE-P9-O0-NEXT:    lxv v24, 192(r1) # 16-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: V24(VSR56)
 ; LE-P9-O0-NEXT:    lxv v23, 176(r1) # 16-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: V23(VSR55)
 ; LE-P9-O0-NEXT:    lxv v22, 160(r1) # 16-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: V22(VSR54)
 ; LE-P9-O0-NEXT:    lxv v21, 144(r1) # 16-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: V21(VSR53)
 ; LE-P9-O0-NEXT:    lxv v20, 128(r1) # 16-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: V20(VSR52)
 ; LE-P9-O0-NEXT:    lfd f31, 600(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F31(VSR31)
 ; LE-P9-O0-NEXT:    lfd f30, 592(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F30(VSR30)
 ; LE-P9-O0-NEXT:    lfd f29, 584(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F29(VSR29)
 ; LE-P9-O0-NEXT:    lfd f28, 576(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F28(VSR28)
 ; LE-P9-O0-NEXT:    lfd f27, 568(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F27(VSR27)
 ; LE-P9-O0-NEXT:    lfd f26, 560(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F26(VSR26)
 ; LE-P9-O0-NEXT:    lfd f25, 552(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F25(VSR25)
 ; LE-P9-O0-NEXT:    lfd f24, 544(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F24(VSR24)
 ; LE-P9-O0-NEXT:    lfd f23, 536(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F23(VSR23)
 ; LE-P9-O0-NEXT:    lfd f22, 528(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F22(VSR22)
 ; LE-P9-O0-NEXT:    lfd f21, 520(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F21(VSR21)
 ; LE-P9-O0-NEXT:    lfd f20, 512(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F20(VSR20)
 ; LE-P9-O0-NEXT:    lfd f19, 504(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F19(VSR19)
 ; LE-P9-O0-NEXT:    lfd f18, 496(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F18(VSR18)
 ; LE-P9-O0-NEXT:    lfd f17, 488(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F17(VSR17)
 ; LE-P9-O0-NEXT:    lfd f16, 480(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F16(VSR16)
 ; LE-P9-O0-NEXT:    lfd f15, 472(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F15(VSR15)
 ; LE-P9-O0-NEXT:    lfd f14, 464(r1) # 8-byte Folded Reload
+; LE-P9-O0-NEXT:    # Vec Defs: F14(VSR14)
 ; LE-P9-O0-NEXT:    ld r31, 456(r1) # 8-byte Folded Reload
 ; LE-P9-O0-NEXT:    ld r30, 448(r1) # 8-byte Folded Reload
 ; LE-P9-O0-NEXT:    ld r29, 440(r1) # 8-byte Folded Reload
 ; LE-P9-O0-NEXT:    ld r28, 432(r1) # 8-byte Folded Reload
 ; LE-P9-O0-NEXT:    ld r27, 424(r1) # 8-byte Folded Reload
 ; LE-P9-O0-NEXT:    ld r26, 416(r1) # 8-byte Folded Reload
 ; LE-P9-O0-NEXT:    ld r25, 408(r1) # 8-byte Folded Reload
 ; LE-P9-O0-NEXT:    ld r24, 400(r1) # 8-byte Folded Reload

 ; LE-P8-O0-NEXT:    std r25, 408(r1) # 8-byte Folded Spill
 ; LE-P8-O0-NEXT:    std r26, 416(r1) # 8-byte Folded Spill
 ; LE-P8-O0-NEXT:    std r27, 424(r1) # 8-byte Folded Spill
 ; LE-P8-O0-NEXT:    std r28, 432(r1) # 8-byte Folded Spill
 ; LE-P8-O0-NEXT:    std r29, 440(r1) # 8-byte Folded Spill
 ; LE-P8-O0-NEXT:    std r30, 448(r1) # 8-byte Folded Spill
 ; LE-P8-O0-NEXT:    std r31, 456(r1) # 8-byte Folded Spill
 ; LE-P8-O0-NEXT:    stfd f14, 464(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F14(VSR14)
 ; LE-P8-O0-NEXT:    stfd f15, 472(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F15(VSR15)
 ; LE-P8-O0-NEXT:    stfd f16, 480(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F16(VSR16)
 ; LE-P8-O0-NEXT:    stfd f17, 488(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F17(VSR17)
 ; LE-P8-O0-NEXT:    stfd f18, 496(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F18(VSR18)
 ; LE-P8-O0-NEXT:    stfd f19, 504(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F19(VSR19)
 ; LE-P8-O0-NEXT:    stfd f20, 512(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F20(VSR20)
 ; LE-P8-O0-NEXT:    stfd f21, 520(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F21(VSR21)
 ; LE-P8-O0-NEXT:    stfd f22, 528(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F22(VSR22)
 ; LE-P8-O0-NEXT:    stfd f23, 536(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F23(VSR23)
 ; LE-P8-O0-NEXT:    stfd f24, 544(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F24(VSR24)
 ; LE-P8-O0-NEXT:    stfd f25, 552(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F25(VSR25)
 ; LE-P8-O0-NEXT:    stfd f26, 560(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F26(VSR26)
 ; LE-P8-O0-NEXT:    stfd f27, 568(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F27(VSR27)
 ; LE-P8-O0-NEXT:    stfd f28, 576(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F28(VSR28)
 ; LE-P8-O0-NEXT:    stfd f29, 584(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F29(VSR29)
 ; LE-P8-O0-NEXT:    stfd f30, 592(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F30(VSR30)
 ; LE-P8-O0-NEXT:    stfd f31, 600(r1) # 8-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: F31(VSR31)
 ; LE-P8-O0-NEXT:    li r4, 128
 ; LE-P8-O0-NEXT:    stxvd2x v20, r1, r4 # 16-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: V20(VSR52)
 ; LE-P8-O0-NEXT:    li r4, 144
 ; LE-P8-O0-NEXT:    stxvd2x v21, r1, r4 # 16-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: V21(VSR53)
 ; LE-P8-O0-NEXT:    li r4, 160
 ; LE-P8-O0-NEXT:    stxvd2x v22, r1, r4 # 16-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: V22(VSR54)
 ; LE-P8-O0-NEXT:    li r4, 176
 ; LE-P8-O0-NEXT:    stxvd2x v23, r1, r4 # 16-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: V23(VSR55)
 ; LE-P8-O0-NEXT:    li r4, 192
 ; LE-P8-O0-NEXT:    stxvd2x v24, r1, r4 # 16-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: V24(VSR56)
 ; LE-P8-O0-NEXT:    li r4, 208
 ; LE-P8-O0-NEXT:    stxvd2x v25, r1, r4 # 16-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: V25(VSR57)
 ; LE-P8-O0-NEXT:    li r4, 224
 ; LE-P8-O0-NEXT:    stxvd2x v26, r1, r4 # 16-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: V26(VSR58)
 ; LE-P8-O0-NEXT:    li r4, 240
 ; LE-P8-O0-NEXT:    stxvd2x v27, r1, r4 # 16-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: V27(VSR59)
 ; LE-P8-O0-NEXT:    li r4, 256
 ; LE-P8-O0-NEXT:    stxvd2x v28, r1, r4 # 16-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: V28(VSR60)
 ; LE-P8-O0-NEXT:    li r4, 272
 ; LE-P8-O0-NEXT:    stxvd2x v29, r1, r4 # 16-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: V29(VSR61)
 ; LE-P8-O0-NEXT:    li r4, 288
 ; LE-P8-O0-NEXT:    stxvd2x v30, r1, r4 # 16-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: V30(VSR62)
 ; LE-P8-O0-NEXT:    li r4, 304
 ; LE-P8-O0-NEXT:    stxvd2x v31, r1, r4 # 16-byte Folded Spill
+; LE-P8-O0-NEXT:    # Vec Uses: V31(VSR63)
 ; LE-P8-O0-NEXT:    std r3, 104(r1) # 8-byte Folded Spill
 ; LE-P8-O0-NEXT:    lwz r3, 12(r3)
 ; LE-P8-O0-NEXT:    stw r3, 116(r1)
 ; LE-P8-O0-NEXT:    #APP
 ; LE-P8-O0-NEXT:    nop
 ; LE-P8-O0-NEXT:    #NO_APP
 ; LE-P8-O0-NEXT:    addi r3, r1, 116
 ; LE-P8-O0-NEXT:    bl callee2
 ; LE-P8-O0-NEXT:    nop
 ; LE-P8-O0-NEXT:    mr r4, r3
 ; LE-P8-O0-NEXT:    ld r3, 104(r1) # 8-byte Folded Reload
 ; LE-P8-O0-NEXT:    lwz r3, 16(r3)
 ; LE-P8-O0-NEXT:    add r3, r3, r4
 ; LE-P8-O0-NEXT:    clrldi r3, r3, 32
 ; LE-P8-O0-NEXT:    li r4, 304
 ; LE-P8-O0-NEXT:    lxvd2x v31, r1, r4 # 16-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: V31(VSR63)
 ; LE-P8-O0-NEXT:    li r4, 288
 ; LE-P8-O0-NEXT:    lxvd2x v30, r1, r4 # 16-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: V30(VSR62)
 ; LE-P8-O0-NEXT:    li r4, 272
 ; LE-P8-O0-NEXT:    lxvd2x v29, r1, r4 # 16-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: V29(VSR61)
 ; LE-P8-O0-NEXT:    li r4, 256
 ; LE-P8-O0-NEXT:    lxvd2x v28, r1, r4 # 16-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: V28(VSR60)
 ; LE-P8-O0-NEXT:    li r4, 240
 ; LE-P8-O0-NEXT:    lxvd2x v27, r1, r4 # 16-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: V27(VSR59)
 ; LE-P8-O0-NEXT:    li r4, 224
 ; LE-P8-O0-NEXT:    lxvd2x v26, r1, r4 # 16-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: V26(VSR58)
 ; LE-P8-O0-NEXT:    li r4, 208
 ; LE-P8-O0-NEXT:    lxvd2x v25, r1, r4 # 16-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: V25(VSR57)
 ; LE-P8-O0-NEXT:    li r4, 192
 ; LE-P8-O0-NEXT:    lxvd2x v24, r1, r4 # 16-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: V24(VSR56)
 ; LE-P8-O0-NEXT:    li r4, 176
 ; LE-P8-O0-NEXT:    lxvd2x v23, r1, r4 # 16-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: V23(VSR55)
 ; LE-P8-O0-NEXT:    li r4, 160
 ; LE-P8-O0-NEXT:    lxvd2x v22, r1, r4 # 16-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: V22(VSR54)
 ; LE-P8-O0-NEXT:    li r4, 144
 ; LE-P8-O0-NEXT:    lxvd2x v21, r1, r4 # 16-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: V21(VSR53)
 ; LE-P8-O0-NEXT:    li r4, 128
 ; LE-P8-O0-NEXT:    lxvd2x v20, r1, r4 # 16-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: V20(VSR52)
 ; LE-P8-O0-NEXT:    lfd f31, 600(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F31(VSR31)
 ; LE-P8-O0-NEXT:    lfd f30, 592(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F30(VSR30)
 ; LE-P8-O0-NEXT:    lfd f29, 584(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F29(VSR29)
 ; LE-P8-O0-NEXT:    lfd f28, 576(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F28(VSR28)
 ; LE-P8-O0-NEXT:    lfd f27, 568(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F27(VSR27)
 ; LE-P8-O0-NEXT:    lfd f26, 560(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F26(VSR26)
 ; LE-P8-O0-NEXT:    lfd f25, 552(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F25(VSR25)
 ; LE-P8-O0-NEXT:    lfd f24, 544(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F24(VSR24)
 ; LE-P8-O0-NEXT:    lfd f23, 536(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F23(VSR23)
 ; LE-P8-O0-NEXT:    lfd f22, 528(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F22(VSR22)
 ; LE-P8-O0-NEXT:    lfd f21, 520(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F21(VSR21)
 ; LE-P8-O0-NEXT:    lfd f20, 512(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F20(VSR20)
 ; LE-P8-O0-NEXT:    lfd f19, 504(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F19(VSR19)
 ; LE-P8-O0-NEXT:    lfd f18, 496(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F18(VSR18)
 ; LE-P8-O0-NEXT:    lfd f17, 488(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F17(VSR17)
 ; LE-P8-O0-NEXT:    lfd f16, 480(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F16(VSR16)
 ; LE-P8-O0-NEXT:    lfd f15, 472(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F15(VSR15)
 ; LE-P8-O0-NEXT:    lfd f14, 464(r1) # 8-byte Folded Reload
+; LE-P8-O0-NEXT:    # Vec Defs: F14(VSR14)
 ; LE-P8-O0-NEXT:    ld r31, 456(r1) # 8-byte Folded Reload
 ; LE-P8-O0-NEXT:    ld r30, 448(r1) # 8-byte Folded Reload
 ; LE-P8-O0-NEXT:    ld r29, 440(r1) # 8-byte Folded Reload
 ; LE-P8-O0-NEXT:    ld r28, 432(r1) # 8-byte Folded Reload
 ; LE-P8-O0-NEXT:    ld r27, 424(r1) # 8-byte Folded Reload
 ; LE-P8-O0-NEXT:    ld r26, 416(r1) # 8-byte Folded Reload
 ; LE-P8-O0-NEXT:    ld r25, 408(r1) # 8-byte Folded Reload
 ; LE-P8-O0-NEXT:    ld r24, 400(r1) # 8-byte Folded Reload

 ; BE-P10-NEXT:    std r25, 424(r1) # 8-byte Folded Spill
 ; BE-P10-NEXT:    std r26, 432(r1) # 8-byte Folded Spill
 ; BE-P10-NEXT:    std r27, 440(r1) # 8-byte Folded Spill
 ; BE-P10-NEXT:    std r28, 448(r1) # 8-byte Folded Spill
 ; BE-P10-NEXT:    std r29, 456(r1) # 8-byte Folded Spill
 ; BE-P10-NEXT:    std r30, 464(r1) # 8-byte Folded Spill
 ; BE-P10-NEXT:    std r31, 472(r1) # 8-byte Folded Spill
 ; BE-P10-NEXT:    stfd f14, 480(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-P10-NEXT:    stfd f15, 488(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-P10-NEXT:    stfd f16, 496(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-P10-NEXT:    stfd f17, 504(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-P10-NEXT:    stfd f18, 512(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-P10-NEXT:    stfd f19, 520(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-P10-NEXT:    stfd f20, 528(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-P10-NEXT:    stfd f21, 536(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-P10-NEXT:    stfd f22, 544(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-P10-NEXT:    stfd f23, 552(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-P10-NEXT:    stfd f24, 560(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-P10-NEXT:    stfd f25, 568(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-P10-NEXT:    stfd f26, 576(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-P10-NEXT:    stfd f27, 584(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-P10-NEXT:    stfd f28, 592(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-P10-NEXT:    stfd f29, 600(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-P10-NEXT:    stfd f30, 608(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-P10-NEXT:    stfd f31, 616(r1) # 8-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-P10-NEXT:    stxv v20, 144(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-P10-NEXT:    stxv v21, 160(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-P10-NEXT:    stxv v22, 176(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-P10-NEXT:    stxv v23, 192(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-P10-NEXT:    stxv v24, 208(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-P10-NEXT:    stxv v25, 224(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-P10-NEXT:    stxv v26, 240(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-P10-NEXT:    stxv v27, 256(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-P10-NEXT:    stxv v28, 272(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-P10-NEXT:    stxv v29, 288(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-P10-NEXT:    stxv v30, 304(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-P10-NEXT:    stxv v31, 320(r1) # 16-byte Folded Spill
+; BE-P10-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-P10-NEXT:    std r3, 120(r1) # 8-byte Folded Spill
 ; BE-P10-NEXT:    stw r4, 132(r1)
 ; BE-P10-NEXT:    #APP
 ; BE-P10-NEXT:    nop
 ; BE-P10-NEXT:    #NO_APP
 ; BE-P10-NEXT:    addi r3, r1, 132
 ; BE-P10-NEXT:    bl callee2
 ; BE-P10-NEXT:    nop
 ; BE-P10-NEXT:    ld r4, 120(r1) # 8-byte Folded Reload
 ; BE-P10-NEXT:    lxv v31, 320(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-P10-NEXT:    lxv v30, 304(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-P10-NEXT:    lxv v29, 288(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-P10-NEXT:    lxv v28, 272(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-P10-NEXT:    lxv v27, 256(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-P10-NEXT:    lxv v26, 240(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-P10-NEXT:    lxv v25, 224(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-P10-NEXT:    lxv v24, 208(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-P10-NEXT:    lxv v23, 192(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-P10-NEXT:    lxv v22, 176(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-P10-NEXT:    lxv v21, 160(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-P10-NEXT:    lxv v20, 144(r1) # 16-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-P10-NEXT:    lfd f31, 616(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-P10-NEXT:    lfd f30, 608(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-P10-NEXT:    lfd f29, 600(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-P10-NEXT:    lfd f28, 592(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-P10-NEXT:    lfd f27, 584(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-P10-NEXT:    lfd f26, 576(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-P10-NEXT:    lfd f25, 568(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-P10-NEXT:    lfd f24, 560(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-P10-NEXT:    lfd f23, 552(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-P10-NEXT:    lfd f22, 544(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-P10-NEXT:    lfd f21, 536(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-P10-NEXT:    lfd f20, 528(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-P10-NEXT:    lfd f19, 520(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-P10-NEXT:    lfd f18, 512(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-P10-NEXT:    lfd f17, 504(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-P10-NEXT:    lfd f16, 496(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-P10-NEXT:    lfd f15, 488(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-P10-NEXT:    lfd f14, 480(r1) # 8-byte Folded Reload
+; BE-P10-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-P10-NEXT:    ld r31, 472(r1) # 8-byte Folded Reload
 ; BE-P10-NEXT:    ld r30, 464(r1) # 8-byte Folded Reload
 ; BE-P10-NEXT:    ld r29, 456(r1) # 8-byte Folded Reload
 ; BE-P10-NEXT:    ld r28, 448(r1) # 8-byte Folded Reload
 ; BE-P10-NEXT:    ld r27, 440(r1) # 8-byte Folded Reload
 ; BE-P10-NEXT:    ld r26, 432(r1) # 8-byte Folded Reload
 ; BE-P10-NEXT:    ld r25, 424(r1) # 8-byte Folded Reload
 ; BE-P10-NEXT:    ld r24, 416(r1) # 8-byte Folded Reload

 ; BE-P9-NEXT:    std r0, 16(r1)
 ; BE-P9-NEXT:    hashst r0, -488(r1)
 ; BE-P9-NEXT:    stw r12, 8(r1)
 ; BE-P9-NEXT:    stdu r1, -624(r1)
 ; BE-P9-NEXT:    lwz r4, 12(r3)
 ; BE-P9-NEXT:    std r14, 336(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    std r15, 344(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v20, 144(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-P9-NEXT:    stxv v21, 160(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-P9-NEXT:    stxv v22, 176(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-P9-NEXT:    std r16, 352(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    std r17, 360(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v23, 192(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-P9-NEXT:    std r18, 368(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v24, 208(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-P9-NEXT:    std r19, 376(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v25, 224(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-P9-NEXT:    std r20, 384(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    std r21, 392(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v26, 240(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-P9-NEXT:    std r22, 400(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v27, 256(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-P9-NEXT:    std r23, 408(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v28, 272(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-P9-NEXT:    std r24, 416(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    std r25, 424(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v29, 288(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-P9-NEXT:    std r26, 432(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v30, 304(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-P9-NEXT:    std r27, 440(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stxv v31, 320(r1) # 16-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-P9-NEXT:    std r28, 448(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    std r29, 456(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    std r30, 464(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    std r31, 472(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stfd f14, 480(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-P9-NEXT:    stfd f15, 488(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-P9-NEXT:    stfd f16, 496(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-P9-NEXT:    stfd f17, 504(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-P9-NEXT:    stfd f18, 512(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-P9-NEXT:    stfd f19, 520(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-P9-NEXT:    stfd f20, 528(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-P9-NEXT:    stfd f21, 536(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-P9-NEXT:    stfd f22, 544(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-P9-NEXT:    stfd f23, 552(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-P9-NEXT:    stfd f24, 560(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-P9-NEXT:    stfd f25, 568(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-P9-NEXT:    stfd f26, 576(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-P9-NEXT:    stfd f27, 584(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-P9-NEXT:    stfd f28, 592(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-P9-NEXT:    stfd f29, 600(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-P9-NEXT:    stfd f30, 608(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-P9-NEXT:    stfd f31, 616(r1) # 8-byte Folded Spill
+; BE-P9-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-P9-NEXT:    std r3, 120(r1) # 8-byte Folded Spill
 ; BE-P9-NEXT:    stw r4, 132(r1)
 ; BE-P9-NEXT:    #APP
 ; BE-P9-NEXT:    nop
 ; BE-P9-NEXT:    #NO_APP
 ; BE-P9-NEXT:    addi r3, r1, 132
 ; BE-P9-NEXT:    bl callee2
 ; BE-P9-NEXT:    nop
 ; BE-P9-NEXT:    ld r4, 120(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    lxv v31, 320(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-P9-NEXT:    lxv v30, 304(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-P9-NEXT:    lxv v29, 288(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-P9-NEXT:    lxv v28, 272(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-P9-NEXT:    lxv v27, 256(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-P9-NEXT:    lxv v26, 240(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-P9-NEXT:    lxv v25, 224(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-P9-NEXT:    lxv v24, 208(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-P9-NEXT:    lxv v23, 192(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-P9-NEXT:    lxv v22, 176(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-P9-NEXT:    lxv v21, 160(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-P9-NEXT:    lxv v20, 144(r1) # 16-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-P9-NEXT:    lfd f31, 616(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-P9-NEXT:    lfd f30, 608(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-P9-NEXT:    lfd f29, 600(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-P9-NEXT:    lfd f28, 592(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-P9-NEXT:    lfd f27, 584(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-P9-NEXT:    ld r31, 472(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r30, 464(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r29, 456(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    lfd f26, 576(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-P9-NEXT:    ld r28, 448(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r27, 440(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r26, 432(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    lfd f25, 568(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-P9-NEXT:    ld r25, 424(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r24, 416(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r23, 408(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    lfd f24, 560(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-P9-NEXT:    ld r22, 400(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r21, 392(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    lwz r4, 16(r4)
 ; BE-P9-NEXT:    add r3, r4, r3
 ; BE-P9-NEXT:    lfd f23, 552(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-P9-NEXT:    lfd f22, 544(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-P9-NEXT:    ld r20, 384(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r19, 376(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r18, 368(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r17, 360(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r16, 352(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r15, 344(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    ld r14, 336(r1) # 8-byte Folded Reload
 ; BE-P9-NEXT:    lfd f21, 536(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-P9-NEXT:    lfd f20, 528(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-P9-NEXT:    lfd f19, 520(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-P9-NEXT:    lfd f18, 512(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-P9-NEXT:    lfd f17, 504(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-P9-NEXT:    lfd f16, 496(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-P9-NEXT:    lfd f15, 488(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-P9-NEXT:    lfd f14, 480(r1) # 8-byte Folded Reload
+; BE-P9-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-P9-NEXT:    clrldi r3, r3, 32
 ; BE-P9-NEXT:    addi r1, r1, 624
 ; BE-P9-NEXT:    ld r0, 16(r1)
 ; BE-P9-NEXT:    lwz r12, 8(r1)
 ; BE-P9-NEXT:    mtlr r0
 ; BE-P9-NEXT:    hashchk r0, -488(r1)
 ; BE-P9-NEXT:    mtocrf 32, r12
 ; BE-P9-NEXT:    mtocrf 16, r12

 ; BE-P8-NEXT:    stw r12, 8(r1)
 ; BE-P8-NEXT:    stdu r1, -624(r1)
 ; BE-P8-NEXT:    li r4, 144
 ; BE-P8-NEXT:    std r14, 336(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r15, 344(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r16, 352(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r17, 360(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    stxvd2x v20, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-P8-NEXT:    li r4, 160
 ; BE-P8-NEXT:    std r18, 368(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r19, 376(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r20, 384(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r21, 392(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    stxvd2x v21, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-P8-NEXT:    li r4, 176
 ; BE-P8-NEXT:    std r22, 400(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r23, 408(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r24, 416(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r25, 424(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r26, 432(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r27, 440(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r28, 448(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r29, 456(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r30, 464(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r31, 472(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    std r3, 120(r1) # 8-byte Folded Spill
 ; BE-P8-NEXT:    stxvd2x v22, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-P8-NEXT:    li r4, 192
 ; BE-P8-NEXT:    stxvd2x v23, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-P8-NEXT:    li r4, 208
 ; BE-P8-NEXT:    stfd f14, 480(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-P8-NEXT:    stxvd2x v24, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-P8-NEXT:    li r4, 224
 ; BE-P8-NEXT:    stfd f15, 488(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-P8-NEXT:    stxvd2x v25, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-P8-NEXT:    li r4, 240
 ; BE-P8-NEXT:    stfd f16, 496(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-P8-NEXT:    stxvd2x v26, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-P8-NEXT:    li r4, 256
 ; BE-P8-NEXT:    stfd f17, 504(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-P8-NEXT:    stxvd2x v27, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-P8-NEXT:    li r4, 272
 ; BE-P8-NEXT:    stfd f18, 512(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-P8-NEXT:    stxvd2x v28, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-P8-NEXT:    li r4, 288
 ; BE-P8-NEXT:    stfd f19, 520(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-P8-NEXT:    stxvd2x v29, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-P8-NEXT:    li r4, 304
 ; BE-P8-NEXT:    stfd f20, 528(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-P8-NEXT:    stxvd2x v30, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-P8-NEXT:    li r4, 320
 ; BE-P8-NEXT:    stfd f21, 536(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-P8-NEXT:    stxvd2x v31, r1, r4 # 16-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-P8-NEXT:    lwz r4, 12(r3)
 ; BE-P8-NEXT:    stfd f22, 544(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-P8-NEXT:    stfd f23, 552(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-P8-NEXT:    stfd f24, 560(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-P8-NEXT:    stfd f25, 568(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-P8-NEXT:    stfd f26, 576(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-P8-NEXT:    stfd f27, 584(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-P8-NEXT:    stfd f28, 592(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-P8-NEXT:    stfd f29, 600(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-P8-NEXT:    stfd f30, 608(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-P8-NEXT:    stfd f31, 616(r1) # 8-byte Folded Spill
+; BE-P8-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-P8-NEXT:    stw r4, 132(r1)
 ; BE-P8-NEXT:    #APP
 ; BE-P8-NEXT:    nop
 ; BE-P8-NEXT:    #NO_APP
 ; BE-P8-NEXT:    addi r3, r1, 132
 ; BE-P8-NEXT:    bl callee2
 ; BE-P8-NEXT:    nop
 ; BE-P8-NEXT:    ld r4, 120(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lfd f31, 616(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-P8-NEXT:    lfd f30, 608(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-P8-NEXT:    ld r31, 472(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lfd f29, 600(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-P8-NEXT:    lfd f28, 592(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-P8-NEXT:    ld r30, 464(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    ld r29, 456(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lwz r4, 16(r4)
 ; BE-P8-NEXT:    lfd f27, 584(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-P8-NEXT:    lfd f26, 576(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-P8-NEXT:    ld r28, 448(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lfd f25, 568(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-P8-NEXT:    lfd f24, 560(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-P8-NEXT:    ld r27, 440(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    ld r26, 432(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    add r3, r4, r3
 ; BE-P8-NEXT:    li r4, 320
 ; BE-P8-NEXT:    lfd f23, 552(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-P8-NEXT:    lfd f22, 544(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-P8-NEXT:    ld r25, 424(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    ld r24, 416(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lxvd2x v31, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-P8-NEXT:    li r4, 304
 ; BE-P8-NEXT:    lfd f21, 536(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-P8-NEXT:    ld r23, 408(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    ld r22, 400(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    clrldi r3, r3, 32
 ; BE-P8-NEXT:    lxvd2x v30, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-P8-NEXT:    li r4, 288
 ; BE-P8-NEXT:    lfd f20, 528(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-P8-NEXT:    ld r21, 392(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    ld r20, 384(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lxvd2x v29, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-P8-NEXT:    li r4, 272
 ; BE-P8-NEXT:    lfd f19, 520(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-P8-NEXT:    ld r19, 376(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    ld r18, 368(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lxvd2x v28, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-P8-NEXT:    li r4, 256
 ; BE-P8-NEXT:    lfd f18, 512(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-P8-NEXT:    ld r17, 360(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    ld r16, 352(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lxvd2x v27, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-P8-NEXT:    li r4, 240
 ; BE-P8-NEXT:    lfd f17, 504(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-P8-NEXT:    ld r15, 344(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    ld r14, 336(r1) # 8-byte Folded Reload
 ; BE-P8-NEXT:    lxvd2x v26, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-P8-NEXT:    li r4, 224
 ; BE-P8-NEXT:    lfd f16, 496(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-P8-NEXT:    lxvd2x v25, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-P8-NEXT:    li r4, 208
 ; BE-P8-NEXT:    lfd f15, 488(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-P8-NEXT:    lxvd2x v24, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-P8-NEXT:    li r4, 192
 ; BE-P8-NEXT:    lfd f14, 480(r1) # 8-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-P8-NEXT:    lxvd2x v23, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-P8-NEXT:    li r4, 176
 ; BE-P8-NEXT:    lxvd2x v22, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-P8-NEXT:    li r4, 160
 ; BE-P8-NEXT:    lxvd2x v21, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-P8-NEXT:    li r4, 144
 ; BE-P8-NEXT:    lxvd2x v20, r1, r4 # 16-byte Folded Reload
+; BE-P8-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-P8-NEXT:    addi r1, r1, 624
 ; BE-P8-NEXT:    ld r0, 16(r1)
 ; BE-P8-NEXT:    lwz r12, 8(r1)
 ; BE-P8-NEXT:    mtocrf 32, r12
 ; BE-P8-NEXT:    hashchk r0, -488(r1)
 ; BE-P8-NEXT:    mtlr r0
 ; BE-P8-NEXT:    mtocrf 16, r12
 ; BE-P8-NEXT:    mtocrf 8, r12

 ; BE-32BIT-P10-NEXT:    stw r27, 284(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-NEXT:    stw r28, 288(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-NEXT:    stw r29, 292(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-NEXT:    stw r30, 296(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-NEXT:    stw r31, 300(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-NEXT:    stw r12, 228(r1)
 ; BE-32BIT-P10-NEXT:    lwz r4, 12(r3)
 ; BE-32BIT-P10-NEXT:    stfd f14, 304(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-32BIT-P10-NEXT:    stfd f15, 312(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-32BIT-P10-NEXT:    stfd f16, 320(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-32BIT-P10-NEXT:    stfd f17, 328(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-32BIT-P10-NEXT:    stfd f18, 336(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-32BIT-P10-NEXT:    stfd f19, 344(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-32BIT-P10-NEXT:    stfd f20, 352(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-32BIT-P10-NEXT:    stfd f21, 360(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-32BIT-P10-NEXT:    stfd f22, 368(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-32BIT-P10-NEXT:    stfd f23, 376(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-32BIT-P10-NEXT:    stfd f24, 384(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-32BIT-P10-NEXT:    stfd f25, 392(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-32BIT-P10-NEXT:    stfd f26, 400(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-32BIT-P10-NEXT:    stfd f27, 408(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-32BIT-P10-NEXT:    stfd f28, 416(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-32BIT-P10-NEXT:    stfd f29, 424(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-32BIT-P10-NEXT:    stfd f30, 432(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-32BIT-P10-NEXT:    stfd f31, 440(r1) # 8-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-32BIT-P10-NEXT:    stxv v20, 32(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-32BIT-P10-NEXT:    stxv v21, 48(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-32BIT-P10-NEXT:    stxv v22, 64(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-32BIT-P10-NEXT:    stxv v23, 80(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-32BIT-P10-NEXT:    stxv v24, 96(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-32BIT-P10-NEXT:    stxv v25, 112(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-32BIT-P10-NEXT:    stxv v26, 128(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-32BIT-P10-NEXT:    stxv v27, 144(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-32BIT-P10-NEXT:    stxv v28, 160(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-32BIT-P10-NEXT:    stxv v29, 176(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-32BIT-P10-NEXT:    stxv v30, 192(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-32BIT-P10-NEXT:    stxv v31, 208(r1) # 16-byte Folded Spill
+; BE-32BIT-P10-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-32BIT-P10-NEXT:    stw r3, 16(r1) # 4-byte Folded Spill
 ; BE-32BIT-P10-NEXT:    stw r4, 20(r1)
 ; BE-32BIT-P10-NEXT:    #APP
 ; BE-32BIT-P10-NEXT:    nop
 ; BE-32BIT-P10-NEXT:    #NO_APP
 ; BE-32BIT-P10-NEXT:    addi r3, r1, 20
 ; BE-32BIT-P10-NEXT:    bl callee2
 ; BE-32BIT-P10-NEXT:    lwz r4, 16(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-NEXT:    lxv v31, 208(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-32BIT-P10-NEXT:    lxv v30, 192(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-32BIT-P10-NEXT:    lxv v29, 176(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-32BIT-P10-NEXT:    lxv v28, 160(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-32BIT-P10-NEXT:    lxv v27, 144(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-32BIT-P10-NEXT:    lxv v26, 128(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-32BIT-P10-NEXT:    lxv v25, 112(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-32BIT-P10-NEXT:    lxv v24, 96(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-32BIT-P10-NEXT:    lxv v23, 80(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-32BIT-P10-NEXT:    lxv v22, 64(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-32BIT-P10-NEXT:    lxv v21, 48(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-32BIT-P10-NEXT:    lxv v20, 32(r1) # 16-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-32BIT-P10-NEXT:    lfd f31, 440(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-32BIT-P10-NEXT:    lfd f30, 432(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-32BIT-P10-NEXT:    lfd f29, 424(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-32BIT-P10-NEXT:    lfd f28, 416(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-32BIT-P10-NEXT:    lfd f27, 408(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-32BIT-P10-NEXT:    lfd f26, 400(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-32BIT-P10-NEXT:    lfd f25, 392(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-32BIT-P10-NEXT:    lfd f24, 384(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-32BIT-P10-NEXT:    lfd f23, 376(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-32BIT-P10-NEXT:    lfd f22, 368(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-32BIT-P10-NEXT:    lfd f21, 360(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-32BIT-P10-NEXT:    lfd f20, 352(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-32BIT-P10-NEXT:    lfd f19, 344(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-32BIT-P10-NEXT:    lfd f18, 336(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-32BIT-P10-NEXT:    lfd f17, 328(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-32BIT-P10-NEXT:    lfd f16, 320(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-32BIT-P10-NEXT:    lfd f15, 312(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-32BIT-P10-NEXT:    lwz r4, 16(r4)
 ; BE-32BIT-P10-NEXT:    add r3, r4, r3
 ; BE-32BIT-P10-NEXT:    lwz r12, 228(r1)
 ; BE-32BIT-P10-NEXT:    mtocrf 32, r12
 ; BE-32BIT-P10-NEXT:    mtocrf 16, r12
 ; BE-32BIT-P10-NEXT:    mtocrf 8, r12
 ; BE-32BIT-P10-NEXT:    lfd f14, 304(r1) # 8-byte Folded Reload
+; BE-32BIT-P10-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-32BIT-P10-NEXT:    lwz r31, 300(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-NEXT:    lwz r30, 296(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-NEXT:    lwz r29, 292(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-NEXT:    lwz r28, 288(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-NEXT:    lwz r27, 284(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-NEXT:    lwz r26, 280(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-NEXT:    lwz r25, 276(r1) # 4-byte Folded Reload
 ; BE-32BIT-P10-NEXT:    lwz r24, 272(r1) # 4-byte Folded Reload

 ; BE-32BIT-P9-NEXT:    stw r26, 280(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stw r27, 284(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stw r28, 288(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stw r29, 292(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stw r30, 296(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stw r31, 300(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stw r12, 228(r1)
 ; BE-32BIT-P9-NEXT:    stxv v20, 32(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-32BIT-P9-NEXT:    stxv v21, 48(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-32BIT-P9-NEXT:    stxv v22, 64(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-32BIT-P9-NEXT:    stxv v23, 80(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-32BIT-P9-NEXT:    stxv v24, 96(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-32BIT-P9-NEXT:    stxv v25, 112(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-32BIT-P9-NEXT:    stxv v26, 128(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-32BIT-P9-NEXT:    stxv v27, 144(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-32BIT-P9-NEXT:    stxv v28, 160(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-32BIT-P9-NEXT:    stxv v29, 176(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-32BIT-P9-NEXT:    stxv v30, 192(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-32BIT-P9-NEXT:    stxv v31, 208(r1) # 16-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-32BIT-P9-NEXT:    lwz r4, 12(r3)
 ; BE-32BIT-P9-NEXT:    stfd f14, 304(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-32BIT-P9-NEXT:    stfd f15, 312(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-32BIT-P9-NEXT:    stfd f16, 320(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-32BIT-P9-NEXT:    stfd f17, 328(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-32BIT-P9-NEXT:    stfd f18, 336(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-32BIT-P9-NEXT:    stfd f19, 344(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-32BIT-P9-NEXT:    stfd f20, 352(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-32BIT-P9-NEXT:    stfd f21, 360(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-32BIT-P9-NEXT:    stfd f22, 368(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-32BIT-P9-NEXT:    stfd f23, 376(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-32BIT-P9-NEXT:    stfd f24, 384(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-32BIT-P9-NEXT:    stfd f25, 392(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-32BIT-P9-NEXT:    stfd f26, 400(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-32BIT-P9-NEXT:    stfd f27, 408(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-32BIT-P9-NEXT:    stfd f28, 416(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-32BIT-P9-NEXT:    stfd f29, 424(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-32BIT-P9-NEXT:    stfd f30, 432(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-32BIT-P9-NEXT:    stfd f31, 440(r1) # 8-byte Folded Spill
+; BE-32BIT-P9-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-32BIT-P9-NEXT:    stw r3, 16(r1) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    stw r4, 20(r1)
 ; BE-32BIT-P9-NEXT:    #APP
 ; BE-32BIT-P9-NEXT:    nop
 ; BE-32BIT-P9-NEXT:    #NO_APP
 ; BE-32BIT-P9-NEXT:    addi r3, r1, 20
 ; BE-32BIT-P9-NEXT:    bl callee2
 ; BE-32BIT-P9-NEXT:    lwz r4, 16(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lxv v31, 208(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-32BIT-P9-NEXT:    lxv v30, 192(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-32BIT-P9-NEXT:    lxv v29, 176(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-32BIT-P9-NEXT:    lxv v28, 160(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-32BIT-P9-NEXT:    lxv v27, 144(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-32BIT-P9-NEXT:    lxv v26, 128(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-32BIT-P9-NEXT:    lxv v25, 112(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-32BIT-P9-NEXT:    lxv v24, 96(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-32BIT-P9-NEXT:    lxv v23, 80(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-32BIT-P9-NEXT:    lxv v22, 64(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-32BIT-P9-NEXT:    lxv v21, 48(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-32BIT-P9-NEXT:    lxv v20, 32(r1) # 16-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-32BIT-P9-NEXT:    lfd f31, 440(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-32BIT-P9-NEXT:    lfd f30, 432(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-32BIT-P9-NEXT:    lfd f29, 424(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-32BIT-P9-NEXT:    lfd f28, 416(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-32BIT-P9-NEXT:    lfd f27, 408(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-32BIT-P9-NEXT:    lwz r4, 16(r4)
 ; BE-32BIT-P9-NEXT:    lfd f26, 400(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-32BIT-P9-NEXT:    add r3, r4, r3
 ; BE-32BIT-P9-NEXT:    lfd f25, 392(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-32BIT-P9-NEXT:    lfd f24, 384(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-32BIT-P9-NEXT:    lfd f23, 376(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-32BIT-P9-NEXT:    lfd f22, 368(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-32BIT-P9-NEXT:    lfd f21, 360(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-32BIT-P9-NEXT:    lfd f20, 352(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-32BIT-P9-NEXT:    lfd f19, 344(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-32BIT-P9-NEXT:    lfd f18, 336(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-32BIT-P9-NEXT:    lfd f17, 328(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-32BIT-P9-NEXT:    lfd f16, 320(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-32BIT-P9-NEXT:    lfd f15, 312(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-32BIT-P9-NEXT:    lwz r12, 228(r1)
 ; BE-32BIT-P9-NEXT:    lwz r31, 300(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r30, 296(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r29, 292(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r28, 288(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r27, 284(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r26, 280(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r25, 276(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r24, 272(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r23, 268(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r22, 264(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r21, 260(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r20, 256(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r19, 252(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r18, 248(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r17, 244(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r16, 240(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r15, 236(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lwz r14, 232(r1) # 4-byte Folded Reload
 ; BE-32BIT-P9-NEXT:    lfd f14, 304(r1) # 8-byte Folded Reload
+; BE-32BIT-P9-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-32BIT-P9-NEXT:    lwz r0, 452(r1)
 ; BE-32BIT-P9-NEXT:    mtocrf 32, r12
 ; BE-32BIT-P9-NEXT:    mtocrf 16, r12
 ; BE-32BIT-P9-NEXT:    mtocrf 8, r12
 ; BE-32BIT-P9-NEXT:    addi r1, r1, 448
 ; BE-32BIT-P9-NEXT:    mtlr r0
 ; BE-32BIT-P9-NEXT:    hashchk r0, -424(r1)
 ; BE-32BIT-P9-NEXT:    blr

 ; BE-32BIT-P8-NEXT:    stw r26, 280(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stw r27, 284(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stw r28, 288(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stw r29, 292(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stw r30, 296(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stw r31, 300(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stw r12, 228(r1)
 ; BE-32BIT-P8-NEXT:    stxvd2x v20, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-32BIT-P8-NEXT:    li r4, 48
 ; BE-32BIT-P8-NEXT:    stxvd2x v21, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-32BIT-P8-NEXT:    li r4, 64
 ; BE-32BIT-P8-NEXT:    stfd f14, 304(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-32BIT-P8-NEXT:    stxvd2x v22, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-32BIT-P8-NEXT:    li r4, 80
 ; BE-32BIT-P8-NEXT:    stfd f15, 312(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-32BIT-P8-NEXT:    stxvd2x v23, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-32BIT-P8-NEXT:    li r4, 96
 ; BE-32BIT-P8-NEXT:    stfd f16, 320(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-32BIT-P8-NEXT:    stxvd2x v24, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-32BIT-P8-NEXT:    li r4, 112
 ; BE-32BIT-P8-NEXT:    stfd f17, 328(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-32BIT-P8-NEXT:    stxvd2x v25, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-32BIT-P8-NEXT:    li r4, 128
 ; BE-32BIT-P8-NEXT:    stfd f18, 336(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-32BIT-P8-NEXT:    stxvd2x v26, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-32BIT-P8-NEXT:    li r4, 144
 ; BE-32BIT-P8-NEXT:    stfd f19, 344(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-32BIT-P8-NEXT:    stxvd2x v27, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-32BIT-P8-NEXT:    li r4, 160
 ; BE-32BIT-P8-NEXT:    stfd f20, 352(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-32BIT-P8-NEXT:    stxvd2x v28, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-32BIT-P8-NEXT:    li r4, 176
 ; BE-32BIT-P8-NEXT:    stfd f21, 360(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-32BIT-P8-NEXT:    stxvd2x v29, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-32BIT-P8-NEXT:    li r4, 192
 ; BE-32BIT-P8-NEXT:    stfd f22, 368(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-32BIT-P8-NEXT:    stxvd2x v30, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-32BIT-P8-NEXT:    li r4, 208
 ; BE-32BIT-P8-NEXT:    stfd f23, 376(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-32BIT-P8-NEXT:    stxvd2x v31, r1, r4 # 16-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-32BIT-P8-NEXT:    lwz r4, 12(r3)
 ; BE-32BIT-P8-NEXT:    stfd f24, 384(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-32BIT-P8-NEXT:    stfd f25, 392(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-32BIT-P8-NEXT:    stfd f26, 400(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-32BIT-P8-NEXT:    stfd f27, 408(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-32BIT-P8-NEXT:    stfd f28, 416(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-32BIT-P8-NEXT:    stfd f29, 424(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-32BIT-P8-NEXT:    stfd f30, 432(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-32BIT-P8-NEXT:    stfd f31, 440(r1) # 8-byte Folded Spill
+; BE-32BIT-P8-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-32BIT-P8-NEXT:    stw r3, 16(r1) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    stw r4, 20(r1)
 ; BE-32BIT-P8-NEXT:    #APP
 ; BE-32BIT-P8-NEXT:    nop
 ; BE-32BIT-P8-NEXT:    #NO_APP
 ; BE-32BIT-P8-NEXT:    addi r3, r1, 20
 ; BE-32BIT-P8-NEXT:    bl callee2
 ; BE-32BIT-P8-NEXT:    lwz r4, 16(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lfd f31, 440(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-32BIT-P8-NEXT:    lfd f30, 432(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-32BIT-P8-NEXT:    lfd f29, 424(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-32BIT-P8-NEXT:    lfd f28, 416(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-32BIT-P8-NEXT:    lwz r4, 16(r4)
 ; BE-32BIT-P8-NEXT:    lfd f27, 408(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-32BIT-P8-NEXT:    lfd f26, 400(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-32BIT-P8-NEXT:    lfd f25, 392(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-32BIT-P8-NEXT:    lfd f24, 384(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-32BIT-P8-NEXT:    add r3, r4, r3
 ; BE-32BIT-P8-NEXT:    li r4, 208
 ; BE-32BIT-P8-NEXT:    lfd f23, 376(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-32BIT-P8-NEXT:    lfd f22, 368(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-32BIT-P8-NEXT:    lxvd2x v31, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-32BIT-P8-NEXT:    li r4, 192
 ; BE-32BIT-P8-NEXT:    lfd f21, 360(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-32BIT-P8-NEXT:    lxvd2x v30, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-32BIT-P8-NEXT:    li r4, 176
 ; BE-32BIT-P8-NEXT:    lfd f20, 352(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-32BIT-P8-NEXT:    lxvd2x v29, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-32BIT-P8-NEXT:    li r4, 160
 ; BE-32BIT-P8-NEXT:    lfd f19, 344(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-32BIT-P8-NEXT:    lxvd2x v28, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-32BIT-P8-NEXT:    li r4, 144
 ; BE-32BIT-P8-NEXT:    lfd f18, 336(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-32BIT-P8-NEXT:    lxvd2x v27, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-32BIT-P8-NEXT:    li r4, 128
 ; BE-32BIT-P8-NEXT:    lfd f17, 328(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-32BIT-P8-NEXT:    lxvd2x v26, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-32BIT-P8-NEXT:    li r4, 112
 ; BE-32BIT-P8-NEXT:    lfd f16, 320(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-32BIT-P8-NEXT:    lxvd2x v25, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-32BIT-P8-NEXT:    li r4, 96
 ; BE-32BIT-P8-NEXT:    lfd f15, 312(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-32BIT-P8-NEXT:    lxvd2x v24, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-32BIT-P8-NEXT:    li r4, 80
 ; BE-32BIT-P8-NEXT:    lxvd2x v23, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-32BIT-P8-NEXT:    li r4, 64
 ; BE-32BIT-P8-NEXT:    lxvd2x v22, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-32BIT-P8-NEXT:    li r4, 48
 ; BE-32BIT-P8-NEXT:    lxvd2x v21, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-32BIT-P8-NEXT:    li r4, 32
 ; BE-32BIT-P8-NEXT:    lxvd2x v20, r1, r4 # 16-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-32BIT-P8-NEXT:    lwz r12, 228(r1)
 ; BE-32BIT-P8-NEXT:    lfd f14, 304(r1) # 8-byte Folded Reload
+; BE-32BIT-P8-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-32BIT-P8-NEXT:    lwz r31, 300(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lwz r30, 296(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lwz r29, 292(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lwz r28, 288(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lwz r27, 284(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lwz r26, 280(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lwz r25, 276(r1) # 4-byte Folded Reload
 ; BE-32BIT-P8-NEXT:    lwz r24, 272(r1) # 4-byte Folded Reload

 ; LE-P10-PRIV-NEXT:    std r25, 344(r1) # 8-byte Folded Spill
 ; LE-P10-PRIV-NEXT:    std r26, 352(r1) # 8-byte Folded Spill
 ; LE-P10-PRIV-NEXT:    std r27, 360(r1) # 8-byte Folded Spill
 ; LE-P10-PRIV-NEXT:    std r28, 368(r1) # 8-byte Folded Spill
 ; LE-P10-PRIV-NEXT:    std r29, 376(r1) # 8-byte Folded Spill
 ; LE-P10-PRIV-NEXT:    std r30, 384(r1) # 8-byte Folded Spill
 ; LE-P10-PRIV-NEXT:    std r31, 392(r1) # 8-byte Folded Spill
 ; LE-P10-PRIV-NEXT:    stfd f14, 400(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F14(VSR14)
 ; LE-P10-PRIV-NEXT:    stfd f15, 408(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F15(VSR15)
 ; LE-P10-PRIV-NEXT:    stfd f16, 416(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F16(VSR16)
 ; LE-P10-PRIV-NEXT:    stfd f17, 424(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F17(VSR17)
 ; LE-P10-PRIV-NEXT:    stfd f18, 432(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F18(VSR18)
 ; LE-P10-PRIV-NEXT:    stfd f19, 440(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F19(VSR19)
 ; LE-P10-PRIV-NEXT:    stfd f20, 448(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F20(VSR20)
 ; LE-P10-PRIV-NEXT:    stfd f21, 456(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F21(VSR21)
 ; LE-P10-PRIV-NEXT:    stfd f22, 464(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F22(VSR22)
 ; LE-P10-PRIV-NEXT:    stfd f23, 472(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F23(VSR23)
 ; LE-P10-PRIV-NEXT:    stfd f24, 480(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F24(VSR24)
 ; LE-P10-PRIV-NEXT:    stfd f25, 488(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F25(VSR25)
 ; LE-P10-PRIV-NEXT:    stfd f26, 496(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F26(VSR26)
 ; LE-P10-PRIV-NEXT:    stfd f27, 504(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F27(VSR27)
 ; LE-P10-PRIV-NEXT:    stfd f28, 512(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F28(VSR28)
 ; LE-P10-PRIV-NEXT:    stfd f29, 520(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F29(VSR29)
 ; LE-P10-PRIV-NEXT:    stfd f30, 528(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F30(VSR30)
 ; LE-P10-PRIV-NEXT:    stfd f31, 536(r1) # 8-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: F31(VSR31)
 ; LE-P10-PRIV-NEXT:    stxv v20, 64(r1) # 16-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: V20(VSR52)
 ; LE-P10-PRIV-NEXT:    stxv v21, 80(r1) # 16-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: V21(VSR53)
 ; LE-P10-PRIV-NEXT:    stxv v22, 96(r1) # 16-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: V22(VSR54)
 ; LE-P10-PRIV-NEXT:    stxv v23, 112(r1) # 16-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: V23(VSR55)
 ; LE-P10-PRIV-NEXT:    stxv v24, 128(r1) # 16-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: V24(VSR56)
 ; LE-P10-PRIV-NEXT:    stxv v25, 144(r1) # 16-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: V25(VSR57)
 ; LE-P10-PRIV-NEXT:    stxv v26, 160(r1) # 16-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: V26(VSR58)
 ; LE-P10-PRIV-NEXT:    stxv v27, 176(r1) # 16-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: V27(VSR59)
 ; LE-P10-PRIV-NEXT:    stxv v28, 192(r1) # 16-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: V28(VSR60)
 ; LE-P10-PRIV-NEXT:    stxv v29, 208(r1) # 16-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: V29(VSR61)
 ; LE-P10-PRIV-NEXT:    stxv v30, 224(r1) # 16-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: V30(VSR62)
 ; LE-P10-PRIV-NEXT:    stxv v31, 240(r1) # 16-byte Folded Spill
+; LE-P10-PRIV-NEXT:    # Vec Uses: V31(VSR63)
 ; LE-P10-PRIV-NEXT:    std r3, 40(r1) # 8-byte Folded Spill
 ; LE-P10-PRIV-NEXT:    stw r4, 52(r1)
 ; LE-P10-PRIV-NEXT:    #APP
 ; LE-P10-PRIV-NEXT:    nop
 ; LE-P10-PRIV-NEXT:    #NO_APP
 ; LE-P10-PRIV-NEXT:    addi r3, r1, 52
 ; LE-P10-PRIV-NEXT:    bl callee2@notoc
 ; LE-P10-PRIV-NEXT:    ld r4, 40(r1) # 8-byte Folded Reload
 ; LE-P10-PRIV-NEXT:    lxv v31, 240(r1) # 16-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: V31(VSR63)
 ; LE-P10-PRIV-NEXT:    lxv v30, 224(r1) # 16-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: V30(VSR62)
 ; LE-P10-PRIV-NEXT:    lxv v29, 208(r1) # 16-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: V29(VSR61)
 ; LE-P10-PRIV-NEXT:    lxv v28, 192(r1) # 16-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: V28(VSR60)
 ; LE-P10-PRIV-NEXT:    lxv v27, 176(r1) # 16-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: V27(VSR59)
 ; LE-P10-PRIV-NEXT:    lxv v26, 160(r1) # 16-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: V26(VSR58)
 ; LE-P10-PRIV-NEXT:    lxv v25, 144(r1) # 16-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: V25(VSR57)
 ; LE-P10-PRIV-NEXT:    lxv v24, 128(r1) # 16-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: V24(VSR56)
 ; LE-P10-PRIV-NEXT:    lxv v23, 112(r1) # 16-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: V23(VSR55)
 ; LE-P10-PRIV-NEXT:    lxv v22, 96(r1) # 16-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: V22(VSR54)
 ; LE-P10-PRIV-NEXT:    lxv v21, 80(r1) # 16-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: V21(VSR53)
 ; LE-P10-PRIV-NEXT:    lxv v20, 64(r1) # 16-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: V20(VSR52)
 ; LE-P10-PRIV-NEXT:    lfd f31, 536(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F31(VSR31)
 ; LE-P10-PRIV-NEXT:    lfd f30, 528(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F30(VSR30)
 ; LE-P10-PRIV-NEXT:    lfd f29, 520(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F29(VSR29)
 ; LE-P10-PRIV-NEXT:    lfd f28, 512(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F28(VSR28)
 ; LE-P10-PRIV-NEXT:    lfd f27, 504(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F27(VSR27)
 ; LE-P10-PRIV-NEXT:    lfd f26, 496(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F26(VSR26)
 ; LE-P10-PRIV-NEXT:    lfd f25, 488(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F25(VSR25)
 ; LE-P10-PRIV-NEXT:    lfd f24, 480(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F24(VSR24)
 ; LE-P10-PRIV-NEXT:    lfd f23, 472(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F23(VSR23)
 ; LE-P10-PRIV-NEXT:    lfd f22, 464(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F22(VSR22)
 ; LE-P10-PRIV-NEXT:    lfd f21, 456(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F21(VSR21)
 ; LE-P10-PRIV-NEXT:    lfd f20, 448(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F20(VSR20)
 ; LE-P10-PRIV-NEXT:    lfd f19, 440(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F19(VSR19)
 ; LE-P10-PRIV-NEXT:    lfd f18, 432(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F18(VSR18)
 ; LE-P10-PRIV-NEXT:    lfd f17, 424(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F17(VSR17)
 ; LE-P10-PRIV-NEXT:    lfd f16, 416(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F16(VSR16)
 ; LE-P10-PRIV-NEXT:    lfd f15, 408(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F15(VSR15)
 ; LE-P10-PRIV-NEXT:    lfd f14, 400(r1) # 8-byte Folded Reload
+; LE-P10-PRIV-NEXT:    # Vec Defs: F14(VSR14)
 ; LE-P10-PRIV-NEXT:    ld r31, 392(r1) # 8-byte Folded Reload
 ; LE-P10-PRIV-NEXT:    ld r30, 384(r1) # 8-byte Folded Reload
 ; LE-P10-PRIV-NEXT:    ld r29, 376(r1) # 8-byte Folded Reload
 ; LE-P10-PRIV-NEXT:    ld r28, 368(r1) # 8-byte Folded Reload
 ; LE-P10-PRIV-NEXT:    ld r27, 360(r1) # 8-byte Folded Reload
 ; LE-P10-PRIV-NEXT:    ld r26, 352(r1) # 8-byte Folded Reload
 ; LE-P10-PRIV-NEXT:    ld r25, 344(r1) # 8-byte Folded Reload
 ; LE-P10-PRIV-NEXT:    ld r24, 336(r1) # 8-byte Folded Reload

 ; LE-P9-PRIV-NEXT:    std r0, 16(r1)
 ; LE-P9-PRIV-NEXT:    hashstp r0, -488(r1)
 ; LE-P9-PRIV-NEXT:    stw r12, 8(r1)
 ; LE-P9-PRIV-NEXT:    stdu r1, -544(r1)
 ; LE-P9-PRIV-NEXT:    lwz r4, 12(r3)
 ; LE-P9-PRIV-NEXT:    std r14, 256(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    std r15, 264(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    stxv v20, 64(r1) # 16-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: V20(VSR52)
 ; LE-P9-PRIV-NEXT:    stxv v21, 80(r1) # 16-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: V21(VSR53)
 ; LE-P9-PRIV-NEXT:    stxv v22, 96(r1) # 16-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: V22(VSR54)
 ; LE-P9-PRIV-NEXT:    std r16, 272(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    std r17, 280(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    stxv v23, 112(r1) # 16-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: V23(VSR55)
 ; LE-P9-PRIV-NEXT:    std r18, 288(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    stxv v24, 128(r1) # 16-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: V24(VSR56)
 ; LE-P9-PRIV-NEXT:    std r19, 296(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    stxv v25, 144(r1) # 16-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: V25(VSR57)
 ; LE-P9-PRIV-NEXT:    std r20, 304(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    std r21, 312(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    stxv v26, 160(r1) # 16-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: V26(VSR58)
 ; LE-P9-PRIV-NEXT:    std r22, 320(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    stxv v27, 176(r1) # 16-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: V27(VSR59)
 ; LE-P9-PRIV-NEXT:    std r23, 328(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    stxv v28, 192(r1) # 16-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: V28(VSR60)
 ; LE-P9-PRIV-NEXT:    std r24, 336(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    std r25, 344(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    stxv v29, 208(r1) # 16-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: V29(VSR61)
 ; LE-P9-PRIV-NEXT:    std r26, 352(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    stxv v30, 224(r1) # 16-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: V30(VSR62)
 ; LE-P9-PRIV-NEXT:    std r27, 360(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    stxv v31, 240(r1) # 16-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: V31(VSR63)
 ; LE-P9-PRIV-NEXT:    std r28, 368(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    std r29, 376(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    std r30, 384(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    std r31, 392(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    stfd f14, 400(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F14(VSR14)
 ; LE-P9-PRIV-NEXT:    stfd f15, 408(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F15(VSR15)
 ; LE-P9-PRIV-NEXT:    stfd f16, 416(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F16(VSR16)
 ; LE-P9-PRIV-NEXT:    stfd f17, 424(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F17(VSR17)
 ; LE-P9-PRIV-NEXT:    stfd f18, 432(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F18(VSR18)
 ; LE-P9-PRIV-NEXT:    stfd f19, 440(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F19(VSR19)
 ; LE-P9-PRIV-NEXT:    stfd f20, 448(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F20(VSR20)
 ; LE-P9-PRIV-NEXT:    stfd f21, 456(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F21(VSR21)
 ; LE-P9-PRIV-NEXT:    stfd f22, 464(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F22(VSR22)
 ; LE-P9-PRIV-NEXT:    stfd f23, 472(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F23(VSR23)
 ; LE-P9-PRIV-NEXT:    stfd f24, 480(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F24(VSR24)
 ; LE-P9-PRIV-NEXT:    stfd f25, 488(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F25(VSR25)
 ; LE-P9-PRIV-NEXT:    stfd f26, 496(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F26(VSR26)
 ; LE-P9-PRIV-NEXT:    stfd f27, 504(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F27(VSR27)
 ; LE-P9-PRIV-NEXT:    stfd f28, 512(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F28(VSR28)
 ; LE-P9-PRIV-NEXT:    stfd f29, 520(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F29(VSR29)
 ; LE-P9-PRIV-NEXT:    stfd f30, 528(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F30(VSR30)
 ; LE-P9-PRIV-NEXT:    stfd f31, 536(r1) # 8-byte Folded Spill
+; LE-P9-PRIV-NEXT:    # Vec Uses: F31(VSR31)
 ; LE-P9-PRIV-NEXT:    std r3, 40(r1) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    stw r4, 52(r1)
 ; LE-P9-PRIV-NEXT:    #APP
 ; LE-P9-PRIV-NEXT:    nop
 ; LE-P9-PRIV-NEXT:    #NO_APP
 ; LE-P9-PRIV-NEXT:    addi r3, r1, 52
 ; LE-P9-PRIV-NEXT:    bl callee2
 ; LE-P9-PRIV-NEXT:    nop
 ; LE-P9-PRIV-NEXT:    ld r4, 40(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    lxv v31, 240(r1) # 16-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: V31(VSR63)
 ; LE-P9-PRIV-NEXT:    lxv v30, 224(r1) # 16-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: V30(VSR62)
 ; LE-P9-PRIV-NEXT:    lxv v29, 208(r1) # 16-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: V29(VSR61)
 ; LE-P9-PRIV-NEXT:    lxv v28, 192(r1) # 16-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: V28(VSR60)
 ; LE-P9-PRIV-NEXT:    lxv v27, 176(r1) # 16-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: V27(VSR59)
 ; LE-P9-PRIV-NEXT:    lxv v26, 160(r1) # 16-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: V26(VSR58)
 ; LE-P9-PRIV-NEXT:    lxv v25, 144(r1) # 16-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: V25(VSR57)
 ; LE-P9-PRIV-NEXT:    lxv v24, 128(r1) # 16-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: V24(VSR56)
 ; LE-P9-PRIV-NEXT:    lxv v23, 112(r1) # 16-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: V23(VSR55)
 ; LE-P9-PRIV-NEXT:    lxv v22, 96(r1) # 16-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: V22(VSR54)
 ; LE-P9-PRIV-NEXT:    lxv v21, 80(r1) # 16-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: V21(VSR53)
 ; LE-P9-PRIV-NEXT:    lxv v20, 64(r1) # 16-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: V20(VSR52)
 ; LE-P9-PRIV-NEXT:    lfd f31, 536(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F31(VSR31)
 ; LE-P9-PRIV-NEXT:    lfd f30, 528(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F30(VSR30)
 ; LE-P9-PRIV-NEXT:    lfd f29, 520(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F29(VSR29)
 ; LE-P9-PRIV-NEXT:    lfd f28, 512(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F28(VSR28)
 ; LE-P9-PRIV-NEXT:    lfd f27, 504(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F27(VSR27)
 ; LE-P9-PRIV-NEXT:    ld r31, 392(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    ld r30, 384(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    ld r29, 376(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    lfd f26, 496(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F26(VSR26)
 ; LE-P9-PRIV-NEXT:    ld r28, 368(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    ld r27, 360(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    ld r26, 352(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    lfd f25, 488(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F25(VSR25)
 ; LE-P9-PRIV-NEXT:    ld r25, 344(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    ld r24, 336(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    ld r23, 328(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    lfd f24, 480(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F24(VSR24)
 ; LE-P9-PRIV-NEXT:    ld r22, 320(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    ld r21, 312(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    lwz r4, 16(r4)
 ; LE-P9-PRIV-NEXT:    add r3, r4, r3
 ; LE-P9-PRIV-NEXT:    lfd f23, 472(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F23(VSR23)
 ; LE-P9-PRIV-NEXT:    lfd f22, 464(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F22(VSR22)
 ; LE-P9-PRIV-NEXT:    ld r20, 304(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    ld r19, 296(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    ld r18, 288(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    ld r17, 280(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    ld r16, 272(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    ld r15, 264(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    ld r14, 256(r1) # 8-byte Folded Reload
 ; LE-P9-PRIV-NEXT:    lfd f21, 456(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F21(VSR21)
 ; LE-P9-PRIV-NEXT:    lfd f20, 448(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F20(VSR20)
 ; LE-P9-PRIV-NEXT:    lfd f19, 440(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F19(VSR19)
 ; LE-P9-PRIV-NEXT:    lfd f18, 432(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F18(VSR18)
 ; LE-P9-PRIV-NEXT:    lfd f17, 424(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F17(VSR17)
 ; LE-P9-PRIV-NEXT:    lfd f16, 416(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F16(VSR16)
 ; LE-P9-PRIV-NEXT:    lfd f15, 408(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F15(VSR15)
 ; LE-P9-PRIV-NEXT:    lfd f14, 400(r1) # 8-byte Folded Reload
+; LE-P9-PRIV-NEXT:    # Vec Defs: F14(VSR14)
 ; LE-P9-PRIV-NEXT:    clrldi r3, r3, 32
 ; LE-P9-PRIV-NEXT:    addi r1, r1, 544
 ; LE-P9-PRIV-NEXT:    ld r0, 16(r1)
 ; LE-P9-PRIV-NEXT:    lwz r12, 8(r1)
 ; LE-P9-PRIV-NEXT:    mtlr r0
 ; LE-P9-PRIV-NEXT:    hashchkp r0, -488(r1)
 ; LE-P9-PRIV-NEXT:    mtocrf 32, r12
 ; LE-P9-PRIV-NEXT:    mtocrf 16, r12

 ; LE-P8-PRIV-NEXT:    stw r12, 8(r1)
 ; LE-P8-PRIV-NEXT:    stdu r1, -544(r1)
 ; LE-P8-PRIV-NEXT:    li r4, 64
 ; LE-P8-PRIV-NEXT:    std r14, 256(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    std r15, 264(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    std r16, 272(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    std r17, 280(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    stxvd2x v20, r1, r4 # 16-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: V20(VSR52)
 ; LE-P8-PRIV-NEXT:    li r4, 80
 ; LE-P8-PRIV-NEXT:    std r18, 288(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    std r19, 296(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    std r20, 304(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    std r21, 312(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    stxvd2x v21, r1, r4 # 16-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: V21(VSR53)
 ; LE-P8-PRIV-NEXT:    li r4, 96
 ; LE-P8-PRIV-NEXT:    std r22, 320(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    std r23, 328(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    std r24, 336(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    std r25, 344(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    std r26, 352(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    std r27, 360(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    std r28, 368(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    std r29, 376(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    std r30, 384(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    std r31, 392(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    std r3, 40(r1) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    stxvd2x v22, r1, r4 # 16-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: V22(VSR54)
 ; LE-P8-PRIV-NEXT:    li r4, 112
 ; LE-P8-PRIV-NEXT:    stxvd2x v23, r1, r4 # 16-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: V23(VSR55)
 ; LE-P8-PRIV-NEXT:    li r4, 128
 ; LE-P8-PRIV-NEXT:    stfd f14, 400(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F14(VSR14)
 ; LE-P8-PRIV-NEXT:    stxvd2x v24, r1, r4 # 16-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: V24(VSR56)
 ; LE-P8-PRIV-NEXT:    li r4, 144
 ; LE-P8-PRIV-NEXT:    stfd f15, 408(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F15(VSR15)
 ; LE-P8-PRIV-NEXT:    stxvd2x v25, r1, r4 # 16-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: V25(VSR57)
 ; LE-P8-PRIV-NEXT:    li r4, 160
 ; LE-P8-PRIV-NEXT:    stfd f16, 416(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F16(VSR16)
 ; LE-P8-PRIV-NEXT:    stxvd2x v26, r1, r4 # 16-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: V26(VSR58)
 ; LE-P8-PRIV-NEXT:    li r4, 176
 ; LE-P8-PRIV-NEXT:    stfd f17, 424(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F17(VSR17)
 ; LE-P8-PRIV-NEXT:    stxvd2x v27, r1, r4 # 16-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: V27(VSR59)
 ; LE-P8-PRIV-NEXT:    li r4, 192
 ; LE-P8-PRIV-NEXT:    stfd f18, 432(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F18(VSR18)
 ; LE-P8-PRIV-NEXT:    stxvd2x v28, r1, r4 # 16-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: V28(VSR60)
 ; LE-P8-PRIV-NEXT:    li r4, 208
 ; LE-P8-PRIV-NEXT:    stfd f19, 440(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F19(VSR19)
 ; LE-P8-PRIV-NEXT:    stxvd2x v29, r1, r4 # 16-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: V29(VSR61)
 ; LE-P8-PRIV-NEXT:    li r4, 224
 ; LE-P8-PRIV-NEXT:    stfd f20, 448(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F20(VSR20)
 ; LE-P8-PRIV-NEXT:    stxvd2x v30, r1, r4 # 16-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: V30(VSR62)
 ; LE-P8-PRIV-NEXT:    li r4, 240
 ; LE-P8-PRIV-NEXT:    stfd f21, 456(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F21(VSR21)
 ; LE-P8-PRIV-NEXT:    stxvd2x v31, r1, r4 # 16-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: V31(VSR63)
 ; LE-P8-PRIV-NEXT:    lwz r4, 12(r3)
 ; LE-P8-PRIV-NEXT:    stfd f22, 464(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F22(VSR22)
 ; LE-P8-PRIV-NEXT:    stfd f23, 472(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F23(VSR23)
 ; LE-P8-PRIV-NEXT:    stfd f24, 480(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F24(VSR24)
 ; LE-P8-PRIV-NEXT:    stfd f25, 488(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F25(VSR25)
 ; LE-P8-PRIV-NEXT:    stfd f26, 496(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F26(VSR26)
 ; LE-P8-PRIV-NEXT:    stfd f27, 504(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F27(VSR27)
 ; LE-P8-PRIV-NEXT:    stfd f28, 512(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F28(VSR28)
 ; LE-P8-PRIV-NEXT:    stfd f29, 520(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F29(VSR29)
 ; LE-P8-PRIV-NEXT:    stfd f30, 528(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F30(VSR30)
 ; LE-P8-PRIV-NEXT:    stfd f31, 536(r1) # 8-byte Folded Spill
+; LE-P8-PRIV-NEXT:    # Vec Uses: F31(VSR31)
 ; LE-P8-PRIV-NEXT:    stw r4, 52(r1)
 ; LE-P8-PRIV-NEXT:    #APP
 ; LE-P8-PRIV-NEXT:    nop
 ; LE-P8-PRIV-NEXT:    #NO_APP
 ; LE-P8-PRIV-NEXT:    addi r3, r1, 52
 ; LE-P8-PRIV-NEXT:    bl callee2
 ; LE-P8-PRIV-NEXT:    nop
 ; LE-P8-PRIV-NEXT:    ld r4, 40(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    lfd f31, 536(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F31(VSR31)
 ; LE-P8-PRIV-NEXT:    lfd f30, 528(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F30(VSR30)
 ; LE-P8-PRIV-NEXT:    ld r31, 392(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    lfd f29, 520(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F29(VSR29)
 ; LE-P8-PRIV-NEXT:    lfd f28, 512(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F28(VSR28)
 ; LE-P8-PRIV-NEXT:    ld r30, 384(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    ld r29, 376(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    lwz r4, 16(r4)
 ; LE-P8-PRIV-NEXT:    lfd f27, 504(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F27(VSR27)
 ; LE-P8-PRIV-NEXT:    lfd f26, 496(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F26(VSR26)
 ; LE-P8-PRIV-NEXT:    ld r28, 368(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    lfd f25, 488(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F25(VSR25)
 ; LE-P8-PRIV-NEXT:    lfd f24, 480(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F24(VSR24)
 ; LE-P8-PRIV-NEXT:    ld r27, 360(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    ld r26, 352(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    add r3, r4, r3
 ; LE-P8-PRIV-NEXT:    li r4, 240
 ; LE-P8-PRIV-NEXT:    lfd f23, 472(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F23(VSR23)
 ; LE-P8-PRIV-NEXT:    lfd f22, 464(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F22(VSR22)
 ; LE-P8-PRIV-NEXT:    ld r25, 344(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    ld r24, 336(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    lxvd2x v31, r1, r4 # 16-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: V31(VSR63)
 ; LE-P8-PRIV-NEXT:    li r4, 224
 ; LE-P8-PRIV-NEXT:    lfd f21, 456(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F21(VSR21)
 ; LE-P8-PRIV-NEXT:    ld r23, 328(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    ld r22, 320(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    clrldi r3, r3, 32
 ; LE-P8-PRIV-NEXT:    lxvd2x v30, r1, r4 # 16-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: V30(VSR62)
 ; LE-P8-PRIV-NEXT:    li r4, 208
 ; LE-P8-PRIV-NEXT:    lfd f20, 448(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F20(VSR20)
 ; LE-P8-PRIV-NEXT:    ld r21, 312(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    ld r20, 304(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    lxvd2x v29, r1, r4 # 16-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: V29(VSR61)
 ; LE-P8-PRIV-NEXT:    li r4, 192
 ; LE-P8-PRIV-NEXT:    lfd f19, 440(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F19(VSR19)
 ; LE-P8-PRIV-NEXT:    ld r19, 296(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    ld r18, 288(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    lxvd2x v28, r1, r4 # 16-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: V28(VSR60)
 ; LE-P8-PRIV-NEXT:    li r4, 176
 ; LE-P8-PRIV-NEXT:    lfd f18, 432(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F18(VSR18)
 ; LE-P8-PRIV-NEXT:    ld r17, 280(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    ld r16, 272(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    lxvd2x v27, r1, r4 # 16-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: V27(VSR59)
 ; LE-P8-PRIV-NEXT:    li r4, 160
 ; LE-P8-PRIV-NEXT:    lfd f17, 424(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F17(VSR17)
 ; LE-P8-PRIV-NEXT:    ld r15, 264(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    ld r14, 256(r1) # 8-byte Folded Reload
 ; LE-P8-PRIV-NEXT:    lxvd2x v26, r1, r4 # 16-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: V26(VSR58)
 ; LE-P8-PRIV-NEXT:    li r4, 144
 ; LE-P8-PRIV-NEXT:    lfd f16, 416(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F16(VSR16)
 ; LE-P8-PRIV-NEXT:    lxvd2x v25, r1, r4 # 16-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: V25(VSR57)
 ; LE-P8-PRIV-NEXT:    li r4, 128
 ; LE-P8-PRIV-NEXT:    lfd f15, 408(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F15(VSR15)
 ; LE-P8-PRIV-NEXT:    lxvd2x v24, r1, r4 # 16-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: V24(VSR56)
 ; LE-P8-PRIV-NEXT:    li r4, 112
 ; LE-P8-PRIV-NEXT:    lfd f14, 400(r1) # 8-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: F14(VSR14)
 ; LE-P8-PRIV-NEXT:    lxvd2x v23, r1, r4 # 16-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: V23(VSR55)
 ; LE-P8-PRIV-NEXT:    li r4, 96
 ; LE-P8-PRIV-NEXT:    lxvd2x v22, r1, r4 # 16-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: V22(VSR54)
 ; LE-P8-PRIV-NEXT:    li r4, 80
 ; LE-P8-PRIV-NEXT:    lxvd2x v21, r1, r4 # 16-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: V21(VSR53)
 ; LE-P8-PRIV-NEXT:    li r4, 64
 ; LE-P8-PRIV-NEXT:    lxvd2x v20, r1, r4 # 16-byte Folded Reload
+; LE-P8-PRIV-NEXT:    # Vec Defs: V20(VSR52)
 ; LE-P8-PRIV-NEXT:    addi r1, r1, 544
 ; LE-P8-PRIV-NEXT:    ld r0, 16(r1)
 ; LE-P8-PRIV-NEXT:    lwz r12, 8(r1)
 ; LE-P8-PRIV-NEXT:    mtocrf 32, r12
 ; LE-P8-PRIV-NEXT:    hashchkp r0, -488(r1)
 ; LE-P8-PRIV-NEXT:    mtlr r0
 ; LE-P8-PRIV-NEXT:    mtocrf 16, r12
 ; LE-P8-PRIV-NEXT:    mtocrf 8, r12

 ; BE-P10-PRIV-NEXT:    std r25, 424(r1) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    std r26, 432(r1) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    std r27, 440(r1) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    std r28, 448(r1) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    std r29, 456(r1) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    std r30, 464(r1) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    std r31, 472(r1) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    stfd f14, 480(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-P10-PRIV-NEXT:    stfd f15, 488(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-P10-PRIV-NEXT:    stfd f16, 496(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-P10-PRIV-NEXT:    stfd f17, 504(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-P10-PRIV-NEXT:    stfd f18, 512(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-P10-PRIV-NEXT:    stfd f19, 520(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-P10-PRIV-NEXT:    stfd f20, 528(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-P10-PRIV-NEXT:    stfd f21, 536(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-P10-PRIV-NEXT:    stfd f22, 544(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-P10-PRIV-NEXT:    stfd f23, 552(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-P10-PRIV-NEXT:    stfd f24, 560(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-P10-PRIV-NEXT:    stfd f25, 568(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-P10-PRIV-NEXT:    stfd f26, 576(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-P10-PRIV-NEXT:    stfd f27, 584(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-P10-PRIV-NEXT:    stfd f28, 592(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-P10-PRIV-NEXT:    stfd f29, 600(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-P10-PRIV-NEXT:    stfd f30, 608(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-P10-PRIV-NEXT:    stfd f31, 616(r1) # 8-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-P10-PRIV-NEXT:    stxv v20, 144(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-P10-PRIV-NEXT:    stxv v21, 160(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-P10-PRIV-NEXT:    stxv v22, 176(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-P10-PRIV-NEXT:    stxv v23, 192(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-P10-PRIV-NEXT:    stxv v24, 208(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-P10-PRIV-NEXT:    stxv v25, 224(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-P10-PRIV-NEXT:    stxv v26, 240(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-P10-PRIV-NEXT:    stxv v27, 256(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-P10-PRIV-NEXT:    stxv v28, 272(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-P10-PRIV-NEXT:    stxv v29, 288(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-P10-PRIV-NEXT:    stxv v30, 304(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-P10-PRIV-NEXT:    stxv v31, 320(r1) # 16-byte Folded Spill
+; BE-P10-PRIV-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-P10-PRIV-NEXT:    std r3, 120(r1) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    stw r4, 132(r1)
 ; BE-P10-PRIV-NEXT:    #APP
 ; BE-P10-PRIV-NEXT:    nop
 ; BE-P10-PRIV-NEXT:    #NO_APP
 ; BE-P10-PRIV-NEXT:    addi r3, r1, 132
 ; BE-P10-PRIV-NEXT:    bl callee2
 ; BE-P10-PRIV-NEXT:    nop
 ; BE-P10-PRIV-NEXT:    ld r4, 120(r1) # 8-byte Folded Reload
 ; BE-P10-PRIV-NEXT:    lxv v31, 320(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-P10-PRIV-NEXT:    lxv v30, 304(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-P10-PRIV-NEXT:    lxv v29, 288(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-P10-PRIV-NEXT:    lxv v28, 272(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-P10-PRIV-NEXT:    lxv v27, 256(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-P10-PRIV-NEXT:    lxv v26, 240(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-P10-PRIV-NEXT:    lxv v25, 224(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-P10-PRIV-NEXT:    lxv v24, 208(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-P10-PRIV-NEXT:    lxv v23, 192(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-P10-PRIV-NEXT:    lxv v22, 176(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-P10-PRIV-NEXT:    lxv v21, 160(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-P10-PRIV-NEXT:    lxv v20, 144(r1) # 16-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-P10-PRIV-NEXT:    lfd f31, 616(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-P10-PRIV-NEXT:    lfd f30, 608(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-P10-PRIV-NEXT:    lfd f29, 600(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-P10-PRIV-NEXT:    lfd f28, 592(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-P10-PRIV-NEXT:    lfd f27, 584(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-P10-PRIV-NEXT:    lfd f26, 576(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-P10-PRIV-NEXT:    lfd f25, 568(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-P10-PRIV-NEXT:    lfd f24, 560(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-P10-PRIV-NEXT:    lfd f23, 552(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-P10-PRIV-NEXT:    lfd f22, 544(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-P10-PRIV-NEXT:    lfd f21, 536(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-P10-PRIV-NEXT:    lfd f20, 528(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-P10-PRIV-NEXT:    lfd f19, 520(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-P10-PRIV-NEXT:    lfd f18, 512(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-P10-PRIV-NEXT:    lfd f17, 504(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-P10-PRIV-NEXT:    lfd f16, 496(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-P10-PRIV-NEXT:    lfd f15, 488(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-P10-PRIV-NEXT:    lfd f14, 480(r1) # 8-byte Folded Reload
+; BE-P10-PRIV-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-P10-PRIV-NEXT:    ld r31, 472(r1) # 8-byte Folded Reload
 ; BE-P10-PRIV-NEXT:    ld r30, 464(r1) # 8-byte Folded Reload
 ; BE-P10-PRIV-NEXT:    ld r29, 456(r1) # 8-byte Folded Reload
 ; BE-P10-PRIV-NEXT:    ld r28, 448(r1) # 8-byte Folded Reload
 ; BE-P10-PRIV-NEXT:    ld r27, 440(r1) # 8-byte Folded Reload
 ; BE-P10-PRIV-NEXT:    ld r26, 432(r1) # 8-byte Folded Reload
 ; BE-P10-PRIV-NEXT:    ld r25, 424(r1) # 8-byte Folded Reload
 ; BE-P10-PRIV-NEXT:    ld r24, 416(r1) # 8-byte Folded Reload

 ; BE-P9-PRIV-NEXT:    std r0, 16(r1)
 ; BE-P9-PRIV-NEXT:    hashstp r0, -488(r1)
 ; BE-P9-PRIV-NEXT:    stw r12, 8(r1)
 ; BE-P9-PRIV-NEXT:    stdu r1, -624(r1)
 ; BE-P9-PRIV-NEXT:    lwz r4, 12(r3)
 ; BE-P9-PRIV-NEXT:    std r14, 336(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    std r15, 344(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v20, 144(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-P9-PRIV-NEXT:    stxv v21, 160(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-P9-PRIV-NEXT:    stxv v22, 176(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-P9-PRIV-NEXT:    std r16, 352(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    std r17, 360(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v23, 192(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-P9-PRIV-NEXT:    std r18, 368(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v24, 208(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-P9-PRIV-NEXT:    std r19, 376(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v25, 224(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-P9-PRIV-NEXT:    std r20, 384(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    std r21, 392(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v26, 240(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-P9-PRIV-NEXT:    std r22, 400(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v27, 256(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-P9-PRIV-NEXT:    std r23, 408(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v28, 272(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-P9-PRIV-NEXT:    std r24, 416(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    std r25, 424(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v29, 288(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-P9-PRIV-NEXT:    std r26, 432(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v30, 304(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-P9-PRIV-NEXT:    std r27, 440(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stxv v31, 320(r1) # 16-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-P9-PRIV-NEXT:    std r28, 448(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    std r29, 456(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    std r30, 464(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    std r31, 472(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stfd f14, 480(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-P9-PRIV-NEXT:    stfd f15, 488(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-P9-PRIV-NEXT:    stfd f16, 496(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-P9-PRIV-NEXT:    stfd f17, 504(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-P9-PRIV-NEXT:    stfd f18, 512(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-P9-PRIV-NEXT:    stfd f19, 520(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-P9-PRIV-NEXT:    stfd f20, 528(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-P9-PRIV-NEXT:    stfd f21, 536(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-P9-PRIV-NEXT:    stfd f22, 544(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-P9-PRIV-NEXT:    stfd f23, 552(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-P9-PRIV-NEXT:    stfd f24, 560(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-P9-PRIV-NEXT:    stfd f25, 568(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-P9-PRIV-NEXT:    stfd f26, 576(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-P9-PRIV-NEXT:    stfd f27, 584(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-P9-PRIV-NEXT:    stfd f28, 592(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-P9-PRIV-NEXT:    stfd f29, 600(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-P9-PRIV-NEXT:    stfd f30, 608(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-P9-PRIV-NEXT:    stfd f31, 616(r1) # 8-byte Folded Spill
+; BE-P9-PRIV-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-P9-PRIV-NEXT:    std r3, 120(r1) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    stw r4, 132(r1)
 ; BE-P9-PRIV-NEXT:    #APP
 ; BE-P9-PRIV-NEXT:    nop
 ; BE-P9-PRIV-NEXT:    #NO_APP
 ; BE-P9-PRIV-NEXT:    addi r3, r1, 132
 ; BE-P9-PRIV-NEXT:    bl callee2
 ; BE-P9-PRIV-NEXT:    nop
 ; BE-P9-PRIV-NEXT:    ld r4, 120(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    lxv v31, 320(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-P9-PRIV-NEXT:    lxv v30, 304(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-P9-PRIV-NEXT:    lxv v29, 288(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-P9-PRIV-NEXT:    lxv v28, 272(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-P9-PRIV-NEXT:    lxv v27, 256(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-P9-PRIV-NEXT:    lxv v26, 240(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-P9-PRIV-NEXT:    lxv v25, 224(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-P9-PRIV-NEXT:    lxv v24, 208(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-P9-PRIV-NEXT:    lxv v23, 192(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-P9-PRIV-NEXT:    lxv v22, 176(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-P9-PRIV-NEXT:    lxv v21, 160(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-P9-PRIV-NEXT:    lxv v20, 144(r1) # 16-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-P9-PRIV-NEXT:    lfd f31, 616(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-P9-PRIV-NEXT:    lfd f30, 608(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-P9-PRIV-NEXT:    lfd f29, 600(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-P9-PRIV-NEXT:    lfd f28, 592(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-P9-PRIV-NEXT:    lfd f27, 584(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-P9-PRIV-NEXT:    ld r31, 472(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r30, 464(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r29, 456(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    lfd f26, 576(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-P9-PRIV-NEXT:    ld r28, 448(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r27, 440(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r26, 432(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    lfd f25, 568(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-P9-PRIV-NEXT:    ld r25, 424(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r24, 416(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r23, 408(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    lfd f24, 560(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-P9-PRIV-NEXT:    ld r22, 400(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r21, 392(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    lwz r4, 16(r4)
 ; BE-P9-PRIV-NEXT:    add r3, r4, r3
 ; BE-P9-PRIV-NEXT:    lfd f23, 552(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-P9-PRIV-NEXT:    lfd f22, 544(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-P9-PRIV-NEXT:    ld r20, 384(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r19, 376(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r18, 368(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r17, 360(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r16, 352(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r15, 344(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    ld r14, 336(r1) # 8-byte Folded Reload
 ; BE-P9-PRIV-NEXT:    lfd f21, 536(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-P9-PRIV-NEXT:    lfd f20, 528(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-P9-PRIV-NEXT:    lfd f19, 520(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-P9-PRIV-NEXT:    lfd f18, 512(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-P9-PRIV-NEXT:    lfd f17, 504(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-P9-PRIV-NEXT:    lfd f16, 496(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-P9-PRIV-NEXT:    lfd f15, 488(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-P9-PRIV-NEXT:    lfd f14, 480(r1) # 8-byte Folded Reload
+; BE-P9-PRIV-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-P9-PRIV-NEXT:    clrldi r3, r3, 32
 ; BE-P9-PRIV-NEXT:    addi r1, r1, 624
 ; BE-P9-PRIV-NEXT:    ld r0, 16(r1)
 ; BE-P9-PRIV-NEXT:    lwz r12, 8(r1)
 ; BE-P9-PRIV-NEXT:    mtlr r0
 ; BE-P9-PRIV-NEXT:    hashchkp r0, -488(r1)
 ; BE-P9-PRIV-NEXT:    mtocrf 32, r12
 ; BE-P9-PRIV-NEXT:    mtocrf 16, r12

 ; BE-P8-PRIV-NEXT:    stw r12, 8(r1)
 ; BE-P8-PRIV-NEXT:    stdu r1, -624(r1)
 ; BE-P8-PRIV-NEXT:    li r4, 144
 ; BE-P8-PRIV-NEXT:    std r14, 336(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r15, 344(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r16, 352(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r17, 360(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    stxvd2x v20, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V20(VSR52)
 ; BE-P8-PRIV-NEXT:    li r4, 160
 ; BE-P8-PRIV-NEXT:    std r18, 368(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r19, 376(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r20, 384(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r21, 392(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    stxvd2x v21, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V21(VSR53)
 ; BE-P8-PRIV-NEXT:    li r4, 176
 ; BE-P8-PRIV-NEXT:    std r22, 400(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r23, 408(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r24, 416(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r25, 424(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r26, 432(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r27, 440(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r28, 448(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r29, 456(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r30, 464(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r31, 472(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    std r3, 120(r1) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    stxvd2x v22, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V22(VSR54)
 ; BE-P8-PRIV-NEXT:    li r4, 192
 ; BE-P8-PRIV-NEXT:    stxvd2x v23, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V23(VSR55)
 ; BE-P8-PRIV-NEXT:    li r4, 208
 ; BE-P8-PRIV-NEXT:    stfd f14, 480(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F14(VSR14)
 ; BE-P8-PRIV-NEXT:    stxvd2x v24, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V24(VSR56)
 ; BE-P8-PRIV-NEXT:    li r4, 224
 ; BE-P8-PRIV-NEXT:    stfd f15, 488(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F15(VSR15)
 ; BE-P8-PRIV-NEXT:    stxvd2x v25, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V25(VSR57)
 ; BE-P8-PRIV-NEXT:    li r4, 240
 ; BE-P8-PRIV-NEXT:    stfd f16, 496(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F16(VSR16)
 ; BE-P8-PRIV-NEXT:    stxvd2x v26, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V26(VSR58)
 ; BE-P8-PRIV-NEXT:    li r4, 256
 ; BE-P8-PRIV-NEXT:    stfd f17, 504(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F17(VSR17)
 ; BE-P8-PRIV-NEXT:    stxvd2x v27, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V27(VSR59)
 ; BE-P8-PRIV-NEXT:    li r4, 272
 ; BE-P8-PRIV-NEXT:    stfd f18, 512(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F18(VSR18)
 ; BE-P8-PRIV-NEXT:    stxvd2x v28, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V28(VSR60)
 ; BE-P8-PRIV-NEXT:    li r4, 288
 ; BE-P8-PRIV-NEXT:    stfd f19, 520(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F19(VSR19)
 ; BE-P8-PRIV-NEXT:    stxvd2x v29, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V29(VSR61)
 ; BE-P8-PRIV-NEXT:    li r4, 304
 ; BE-P8-PRIV-NEXT:    stfd f20, 528(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F20(VSR20)
 ; BE-P8-PRIV-NEXT:    stxvd2x v30, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V30(VSR62)
 ; BE-P8-PRIV-NEXT:    li r4, 320
 ; BE-P8-PRIV-NEXT:    stfd f21, 536(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F21(VSR21)
 ; BE-P8-PRIV-NEXT:    stxvd2x v31, r1, r4 # 16-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: V31(VSR63)
 ; BE-P8-PRIV-NEXT:    lwz r4, 12(r3)
 ; BE-P8-PRIV-NEXT:    stfd f22, 544(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F22(VSR22)
 ; BE-P8-PRIV-NEXT:    stfd f23, 552(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F23(VSR23)
 ; BE-P8-PRIV-NEXT:    stfd f24, 560(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F24(VSR24)
 ; BE-P8-PRIV-NEXT:    stfd f25, 568(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F25(VSR25)
 ; BE-P8-PRIV-NEXT:    stfd f26, 576(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F26(VSR26)
 ; BE-P8-PRIV-NEXT:    stfd f27, 584(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F27(VSR27)
 ; BE-P8-PRIV-NEXT:    stfd f28, 592(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F28(VSR28)
 ; BE-P8-PRIV-NEXT:    stfd f29, 600(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F29(VSR29)
 ; BE-P8-PRIV-NEXT:    stfd f30, 608(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F30(VSR30)
 ; BE-P8-PRIV-NEXT:    stfd f31, 616(r1) # 8-byte Folded Spill
+; BE-P8-PRIV-NEXT:    # Vec Uses: F31(VSR31)
 ; BE-P8-PRIV-NEXT:    stw r4, 132(r1)
 ; BE-P8-PRIV-NEXT:    #APP
 ; BE-P8-PRIV-NEXT:    nop
 ; BE-P8-PRIV-NEXT:    #NO_APP
 ; BE-P8-PRIV-NEXT:    addi r3, r1, 132
 ; BE-P8-PRIV-NEXT:    bl callee2
 ; BE-P8-PRIV-NEXT:    nop
 ; BE-P8-PRIV-NEXT:    ld r4, 120(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lfd f31, 616(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F31(VSR31)
 ; BE-P8-PRIV-NEXT:    lfd f30, 608(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F30(VSR30)
 ; BE-P8-PRIV-NEXT:    ld r31, 472(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lfd f29, 600(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F29(VSR29)
 ; BE-P8-PRIV-NEXT:    lfd f28, 592(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F28(VSR28)
 ; BE-P8-PRIV-NEXT:    ld r30, 464(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    ld r29, 456(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lwz r4, 16(r4)
 ; BE-P8-PRIV-NEXT:    lfd f27, 584(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F27(VSR27)
 ; BE-P8-PRIV-NEXT:    lfd f26, 576(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F26(VSR26)
 ; BE-P8-PRIV-NEXT:    ld r28, 448(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lfd f25, 568(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F25(VSR25)
 ; BE-P8-PRIV-NEXT:    lfd f24, 560(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F24(VSR24)
 ; BE-P8-PRIV-NEXT:    ld r27, 440(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    ld r26, 432(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    add r3, r4, r3
 ; BE-P8-PRIV-NEXT:    li r4, 320
 ; BE-P8-PRIV-NEXT:    lfd f23, 552(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F23(VSR23)
 ; BE-P8-PRIV-NEXT:    lfd f22, 544(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F22(VSR22)
 ; BE-P8-PRIV-NEXT:    ld r25, 424(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    ld r24, 416(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lxvd2x v31, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V31(VSR63)
 ; BE-P8-PRIV-NEXT:    li r4, 304
 ; BE-P8-PRIV-NEXT:    lfd f21, 536(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F21(VSR21)
 ; BE-P8-PRIV-NEXT:    ld r23, 408(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    ld r22, 400(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    clrldi r3, r3, 32
 ; BE-P8-PRIV-NEXT:    lxvd2x v30, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V30(VSR62)
 ; BE-P8-PRIV-NEXT:    li r4, 288
 ; BE-P8-PRIV-NEXT:    lfd f20, 528(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F20(VSR20)
 ; BE-P8-PRIV-NEXT:    ld r21, 392(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    ld r20, 384(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lxvd2x v29, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V29(VSR61)
 ; BE-P8-PRIV-NEXT:    li r4, 272
 ; BE-P8-PRIV-NEXT:    lfd f19, 520(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F19(VSR19)
 ; BE-P8-PRIV-NEXT:    ld r19, 376(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    ld r18, 368(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lxvd2x v28, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V28(VSR60)
 ; BE-P8-PRIV-NEXT:    li r4, 256
 ; BE-P8-PRIV-NEXT:    lfd f18, 512(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F18(VSR18)
 ; BE-P8-PRIV-NEXT:    ld r17, 360(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    ld r16, 352(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lxvd2x v27, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V27(VSR59)
 ; BE-P8-PRIV-NEXT:    li r4, 240
 ; BE-P8-PRIV-NEXT:    lfd f17, 504(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F17(VSR17)
 ; BE-P8-PRIV-NEXT:    ld r15, 344(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    ld r14, 336(r1) # 8-byte Folded Reload
 ; BE-P8-PRIV-NEXT:    lxvd2x v26, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V26(VSR58)
 ; BE-P8-PRIV-NEXT:    li r4, 224
 ; BE-P8-PRIV-NEXT:    lfd f16, 496(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F16(VSR16)
 ; BE-P8-PRIV-NEXT:    lxvd2x v25, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V25(VSR57)
 ; BE-P8-PRIV-NEXT:    li r4, 208
 ; BE-P8-PRIV-NEXT:    lfd f15, 488(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F15(VSR15)
 ; BE-P8-PRIV-NEXT:    lxvd2x v24, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V24(VSR56)
 ; BE-P8-PRIV-NEXT:    li r4, 192
 ; BE-P8-PRIV-NEXT:    lfd f14, 480(r1) # 8-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: F14(VSR14)
 ; BE-P8-PRIV-NEXT:    lxvd2x v23, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V23(VSR55)
 ; BE-P8-PRIV-NEXT:    li r4, 176
 ; BE-P8-PRIV-NEXT:    lxvd2x v22, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V22(VSR54)
 ; BE-P8-PRIV-NEXT:    li r4, 160
 ; BE-P8-PRIV-NEXT:    lxvd2x v21, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V21(VSR53)
 ; BE-P8-PRIV-NEXT:    li r4, 144
 ; BE-P8-PRIV-NEXT:    lxvd2x v20, r1, r4 # 16-byte Folded Reload
+; BE-P8-PRIV-NEXT:    # Vec Defs: V20(VSR52)
 ; BE-P8-PRIV-NEXT:    addi r1, r1, 624
 ; BE-P8-PRIV-NEXT:    ld r0, 16(r1)
 ; BE-P8-PRIV-NEXT:    lwz r12, 8(r1)
 ; BE-P8-PRIV-NEXT:    mtocrf 32, r12
 ; BE-P8-PRIV-NEXT:    hashchkp r0, -488(r1)
 ; BE-P8-PRIV-NEXT:    mtlr r0
 ; BE-P8-PRIV-NEXT:    mtocrf 16, r12
 ; BE-P8-PRIV-NEXT:    mtocrf 8, r12

llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll

%trunc = call ppc_fp128 @llvm.experimental.constrained.trunc.ppcf128(
                     ppc_fp128 %first,
                     metadata !"fpexcept.strict") #1
   ret ppc_fp128 %trunc
 }
 
 define float @test_fptrunc_ppc_fp128_f32(ppc_fp128 %first) #0 {
 ; PC64LE-LABEL: test_fptrunc_ppc_fp128_f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xsrsp 1, 1
+; PC64LE-NEXT:    xsrsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: test_fptrunc_ppc_fp128_f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xsrsp 1, 1
+; PC64LE9-NEXT:    xsrsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64LE9-NEXT:    blr
 ;
 ; PC64-LABEL: test_fptrunc_ppc_fp128_f32:
 ; PC64:       # %bb.0: # %entry
-; PC64-NEXT:    frsp 1, 1
+; PC64-NEXT:    frsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64-NEXT:    blr
 entry:
   %fptrunc = call float @llvm.experimental.constrained.fptrunc.ppcf128.f32(
                     ppc_fp128 %first,
                     metadata !"round.dynamic",
                     metadata !"fpexcept.strict") #1
   ret float %fptrunc
 }
%fptrunc = call double @llvm.experimental.constrained.fptrunc.ppcf128.f64(
                     metadata !"round.dynamic",
                     metadata !"fpexcept.strict") #1
   ret double %fptrunc
 }
 
 define ppc_fp128 @test_fpext_ppc_fp128_f32(float %first) #0 {
 ; PC64LE-LABEL: test_fpext_ppc_fp128_f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxlxor 2, 2, 2
+; PC64LE-NEXT:    xxlxor 2, 2, 2 # Vec Defs: F2(VSR2)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: test_fpext_ppc_fp128_f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxlxor 2, 2, 2
+; PC64LE9-NEXT:    xxlxor 2, 2, 2 # Vec Defs: F2(VSR2)
 ; PC64LE9-NEXT:    blr
 ;
 ; PC64-LABEL: test_fpext_ppc_fp128_f32:
 ; PC64:       # %bb.0: # %entry
 ; PC64-NEXT:    addis 3, 2, .LCPI26_0@toc@ha
-; PC64-NEXT:    lfs 2, .LCPI26_0@toc@l(3)
+; PC64-NEXT:    lfs 2, .LCPI26_0@toc@l(3) # Vec Defs: F2(VSR2)
 ; PC64-NEXT:    blr
 entry:
   %fpext = call ppc_fp128 @llvm.experimental.constrained.fpext.f32.ppcf128(
                     float %first,
                     metadata !"fpexcept.strict") #1
   ret ppc_fp128 %fpext
 }
 
 define ppc_fp128 @test_fpext_ppc_fp128_f64(double %first) #0 {
 ; PC64LE-LABEL: test_fpext_ppc_fp128_f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxlxor 2, 2, 2
+; PC64LE-NEXT:    xxlxor 2, 2, 2 # Vec Defs: F2(VSR2)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: test_fpext_ppc_fp128_f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxlxor 2, 2, 2
+; PC64LE9-NEXT:    xxlxor 2, 2, 2 # Vec Defs: F2(VSR2)
 ; PC64LE9-NEXT:    blr
 ;
 ; PC64-LABEL: test_fpext_ppc_fp128_f64:
 ; PC64:       # %bb.0: # %entry
 ; PC64-NEXT:    addis 3, 2, .LCPI27_0@toc@ha
-; PC64-NEXT:    lfs 2, .LCPI27_0@toc@l(3)
+; PC64-NEXT:    lfs 2, .LCPI27_0@toc@l(3) # Vec Defs: F2(VSR2)
 ; PC64-NEXT:    blr
 entry:
   %fpext = call ppc_fp128 @llvm.experimental.constrained.fpext.f64.ppcf128(
                     double %first,
                     metadata !"fpexcept.strict") #1
   ret ppc_fp128 %fpext
 }
 
%fpext = call i64 @llvm.experimental.constrained.fptosi.i64.ppcf128(
                     ppc_fp128 %first,
                     metadata !"fpexcept.strict") #1
   ret i64 %fpext
 }
 
 define i32 @test_fptosi_ppc_i32_ppc_fp128(ppc_fp128 %first) #0 {
 ; PC64LE-LABEL: test_fptosi_ppc_i32_ppc_fp128:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mffs 0
+; PC64LE-NEXT:    mffs 0 # Vec Defs: F0(VSR0)
 ; PC64LE-NEXT:    mtfsb1 31
 ; PC64LE-NEXT:    mtfsb0 30
-; PC64LE-NEXT:    fadd 1, 2, 1
-; PC64LE-NEXT:    mtfsf 1, 0
-; PC64LE-NEXT:    xscvdpsxws 0, 1
-; PC64LE-NEXT:    mffprwz 3, 0
+; PC64LE-NEXT:    fadd 1, 2, 1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PC64LE-NEXT:    mtfsf 1, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpsxws 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: test_fptosi_ppc_i32_ppc_fp128:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mffs 0
+; PC64LE9-NEXT:    mffs 0 # Vec Defs: F0(VSR0)
 ; PC64LE9-NEXT:    mtfsb1 31
 ; PC64LE9-NEXT:    mtfsb0 30
-; PC64LE9-NEXT:    fadd 1, 2, 1
-; PC64LE9-NEXT:    mtfsf 1, 0
-; PC64LE9-NEXT:    xscvdpsxws 0, 1
-; PC64LE9-NEXT:    mffprwz 3, 0
+; PC64LE9-NEXT:    fadd 1, 2, 1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PC64LE9-NEXT:    mtfsf 1, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxws 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 ;
 ; PC64-LABEL: test_fptosi_ppc_i32_ppc_fp128:
 ; PC64:       # %bb.0: # %entry
-; PC64-NEXT:    mffs 0
+; PC64-NEXT:    mffs 0 # Vec Defs: F0(VSR0)
 ; PC64-NEXT:    mtfsb1 31
 ; PC64-NEXT:    mtfsb0 30
-; PC64-NEXT:    fadd 1, 2, 1
-; PC64-NEXT:    mtfsf 1, 0
-; PC64-NEXT:    fctiwz 0, 1
-; PC64-NEXT:    stfd 0, -8(1)
+; PC64-NEXT:    fadd 1, 2, 1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PC64-NEXT:    mtfsf 1, 0 # Vec Uses: F0(VSR0)
+; PC64-NEXT:    fctiwz 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64-NEXT:    stfd 0, -8(1) # Vec Uses: F0(VSR0)
 ; PC64-NEXT:    lwz 3, -4(1)
 ; PC64-NEXT:    blr
 entry:
   %fpext = call i32 @llvm.experimental.constrained.fptosi.i32.ppcf128(
                     ppc_fp128  %first,
                     metadata !"fpexcept.strict") #1
   ret i32 %fpext
 }

 define i32 @test_fptoui_ppc_i32_ppc_fp128(ppc_fp128 %first) #0 {
 ; PC64LE-LABEL: test_fptoui_ppc_i32_ppc_fp128:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 30, -16(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -48(1)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI31_0@toc@ha
-; PC64LE-NEXT:    xxlxor 3, 3, 3
-; PC64LE-NEXT:    lfs 0, .LCPI31_0@toc@l(3)
+; PC64LE-NEXT:    xxlxor 3, 3, 3 # Vec Defs: F3(VSR3)
+; PC64LE-NEXT:    lfs 0, .LCPI31_0@toc@l(3) # Vec Defs: F0(VSR0)
 ; PC64LE-NEXT:    lis 3, -32768
-; PC64LE-NEXT:    fcmpo 0, 2, 3
-; PC64LE-NEXT:    xxlxor 3, 3, 3
-; PC64LE-NEXT:    fcmpo 1, 1, 0
+; PC64LE-NEXT:    fcmpo 0, 2, 3 # Vec Uses: F2(VSR2)F3(VSR3)
+; PC64LE-NEXT:    xxlxor 3, 3, 3 # Vec Defs: F3(VSR3)
+; PC64LE-NEXT:    fcmpo 1, 1, 0 # Vec Uses: F1(VSR1)F0(VSR0)
 ; PC64LE-NEXT:    crand 20, 6, 0
 ; PC64LE-NEXT:    crandc 21, 4, 6
 ; PC64LE-NEXT:    cror 20, 21, 20
 ; PC64LE-NEXT:    isel 30, 0, 3, 20
 ; PC64LE-NEXT:    bc 12, 20, .LBB31_2
 ; PC64LE-NEXT:  # %bb.1: # %entry
-; PC64LE-NEXT:    fmr 3, 0
+; PC64LE-NEXT:    fmr 3, 0 # Vec Defs: F3(VSR3) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:  .LBB31_2: # %entry
-; PC64LE-NEXT:    xxlxor 4, 4, 4
+; PC64LE-NEXT:    xxlxor 4, 4, 4 # Vec Defs: F4(VSR4)
 ; PC64LE-NEXT:    bl __gcc_qsub
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    mffs 0
+; PC64LE-NEXT:    mffs 0 # Vec Defs: F0(VSR0)
 ; PC64LE-NEXT:    mtfsb1 31
 ; PC64LE-NEXT:    mtfsb0 30
-; PC64LE-NEXT:    fadd 1, 2, 1
-; PC64LE-NEXT:    mtfsf 1, 0
-; PC64LE-NEXT:    xscvdpsxws 0, 1
-; PC64LE-NEXT:    mffprwz 3, 0
+; PC64LE-NEXT:    fadd 1, 2, 1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PC64LE-NEXT:    mtfsf 1, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpsxws 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    xor 3, 3, 30
 ; PC64LE-NEXT:    addi 1, 1, 48
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: test_fptoui_ppc_i32_ppc_fp128:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 30, -16(1) # 8-byte Folded Spill
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -48(1)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI31_0@toc@ha
-; PC64LE9-NEXT:    xxlxor 3, 3, 3
-; PC64LE9-NEXT:    lfs 0, .LCPI31_0@toc@l(3)
-; PC64LE9-NEXT:    fcmpo 1, 2, 3
+; PC64LE9-NEXT:    xxlxor 3, 3, 3 # Vec Defs: F3(VSR3)
+; PC64LE9-NEXT:    lfs 0, .LCPI31_0@toc@l(3) # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    fcmpo 1, 2, 3 # Vec Uses: F2(VSR2)F3(VSR3)
 ; PC64LE9-NEXT:    lis 3, -32768
-; PC64LE9-NEXT:    fcmpo 0, 1, 0
-; PC64LE9-NEXT:    xxlxor 3, 3, 3
+; PC64LE9-NEXT:    fcmpo 0, 1, 0 # Vec Uses: F1(VSR1)F0(VSR0)
+; PC64LE9-NEXT:    xxlxor 3, 3, 3 # Vec Defs: F3(VSR3)
 ; PC64LE9-NEXT:    crand 20, 2, 4
 ; PC64LE9-NEXT:    crandc 21, 0, 2
 ; PC64LE9-NEXT:    cror 20, 21, 20
 ; PC64LE9-NEXT:    isel 30, 0, 3, 20
 ; PC64LE9-NEXT:    bc 12, 20, .LBB31_2
 ; PC64LE9-NEXT:  # %bb.1: # %entry
-; PC64LE9-NEXT:    fmr 3, 0
+; PC64LE9-NEXT:    fmr 3, 0 # Vec Defs: F3(VSR3) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:  .LBB31_2: # %entry
-; PC64LE9-NEXT:    xxlxor 4, 4, 4
+; PC64LE9-NEXT:    xxlxor 4, 4, 4 # Vec Defs: F4(VSR4)
 ; PC64LE9-NEXT:    bl __gcc_qsub
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    mffs 0
+; PC64LE9-NEXT:    mffs 0 # Vec Defs: F0(VSR0)
 ; PC64LE9-NEXT:    mtfsb1 31
 ; PC64LE9-NEXT:    mtfsb0 30
-; PC64LE9-NEXT:    fadd 1, 2, 1
-; PC64LE9-NEXT:    mtfsf 1, 0
-; PC64LE9-NEXT:    xscvdpsxws 0, 1
-; PC64LE9-NEXT:    mffprwz 3, 0
+; PC64LE9-NEXT:    fadd 1, 2, 1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PC64LE9-NEXT:    mtfsf 1, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxws 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    xor 3, 3, 30
 ; PC64LE9-NEXT:    addi 1, 1, 48
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 ;
 ; PC64-LABEL: test_fptoui_ppc_i32_ppc_fp128:
 ; PC64:       # %bb.0: # %entry
 ; PC64-NEXT:    mflr 0
 ; PC64-NEXT:    std 0, 16(1)
 ; PC64-NEXT:    mfcr 12
 ; PC64-NEXT:    stw 12, 8(1)
 ; PC64-NEXT:    stdu 1, -128(1)
 ; PC64-NEXT:    addis 3, 2, .LCPI31_0@toc@ha
-; PC64-NEXT:    lfs 0, .LCPI31_0@toc@l(3)
+; PC64-NEXT:    lfs 0, .LCPI31_0@toc@l(3) # Vec Defs: F0(VSR0)
 ; PC64-NEXT:    addis 3, 2, .LCPI31_1@toc@ha
-; PC64-NEXT:    lfs 4, .LCPI31_1@toc@l(3)
-; PC64-NEXT:    fcmpo 0, 1, 0
+; PC64-NEXT:    lfs 4, .LCPI31_1@toc@l(3) # Vec Defs: F4(VSR4)
+; PC64-NEXT:    fcmpo 0, 1, 0 # Vec Uses: F1(VSR1)F0(VSR0)
 ; PC64-NEXT:    crandc 21, 0, 2
-; PC64-NEXT:    fcmpo 1, 2, 4
+; PC64-NEXT:    fcmpo 1, 2, 4 # Vec Uses: F2(VSR2)F4(VSR4)
 ; PC64-NEXT:    crand 20, 2, 4
 ; PC64-NEXT:    cror 8, 21, 20
-; PC64-NEXT:    fmr 3, 4
+; PC64-NEXT:    fmr 3, 4 # Vec Defs: F3(VSR3) Vec Uses: F4(VSR4)
 ; PC64-NEXT:    bc 12, 8, .LBB31_2
 ; PC64-NEXT:  # %bb.1: # %entry
-; PC64-NEXT:    fmr 3, 0
+; PC64-NEXT:    fmr 3, 0 # Vec Defs: F3(VSR3) Vec Uses: F0(VSR0)
 ; PC64-NEXT:  .LBB31_2: # %entry
 ; PC64-NEXT:    bl __gcc_qsub
 ; PC64-NEXT:    nop
-; PC64-NEXT:    mffs 0
+; PC64-NEXT:    mffs 0 # Vec Defs: F0(VSR0)
 ; PC64-NEXT:    mtfsb1 31
 ; PC64-NEXT:    lis 4, -32768
 ; PC64-NEXT:    bc 12, 8, .LBB31_3
 ; PC64-NEXT:    b .LBB31_4
 ; PC64-NEXT:  .LBB31_3: # %entry
 ; PC64-NEXT:    li 4, 0
 ; PC64-NEXT:  .LBB31_4: # %entry
 ; PC64-NEXT:    mtfsb0 30
-; PC64-NEXT:    fadd 1, 2, 1
-; PC64-NEXT:    mtfsf 1, 0
-; PC64-NEXT:    fctiwz 0, 1
-; PC64-NEXT:    stfd 0, 120(1)
+; PC64-NEXT:    fadd 1, 2, 1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PC64-NEXT:    mtfsf 1, 0 # Vec Uses: F0(VSR0)
+; PC64-NEXT:    fctiwz 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64-NEXT:    stfd 0, 120(1) # Vec Uses: F0(VSR0)
 ; PC64-NEXT:    lwz 3, 124(1)
 ; PC64-NEXT:    xor 3, 3, 4
 ; PC64-NEXT:    addi 1, 1, 128
 ; PC64-NEXT:    ld 0, 16(1)
 ; PC64-NEXT:    lwz 12, 8(1)
 ; PC64-NEXT:    mtlr 0
 ; PC64-NEXT:    mtcrf 32, 12 # cr2
 ; PC64-NEXT:    blr
 entry:
   %fpext = call i32 @llvm.experimental.constrained.fptoui.i32.ppcf128(
                     ppc_fp128   %first,
                     metadata !"fpexcept.strict") #1
   ret i32 %fpext
 }
 
 ; Test that resultant libcalls retain order even when their non-strict FLOP form could be
 ; trivially optimized into differing sequences.
 define void @test_constrained_libcall_multichain(float* %firstptr, ppc_fp128* %result) #0 {
 ; PC64LE-LABEL: test_constrained_libcall_multichain:
 ; PC64LE:       # %bb.0:
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 29, -48(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    std 30, -40(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    stfd 29, -24(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F29(VSR29)
 ; PC64LE-NEXT:    stfd 30, -16(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, -8(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    mr 29, 3
-; PC64LE-NEXT:    xxlxor 2, 2, 2
+; PC64LE-NEXT:    xxlxor 2, 2, 2 # Vec Defs: F2(VSR2)
 ; PC64LE-NEXT:    li 3, 0
 ; PC64LE-NEXT:    mr 30, 4
-; PC64LE-NEXT:    lfs 31, 0(29)
-; PC64LE-NEXT:    xxlxor 4, 4, 4
+; PC64LE-NEXT:    lfs 31, 0(29) # Vec Defs: F31(VSR31)
+; PC64LE-NEXT:    xxlxor 4, 4, 4 # Vec Defs: F4(VSR4)
 ; PC64LE-NEXT:    std 3, 8(4)
-; PC64LE-NEXT:    fmr 1, 31
-; PC64LE-NEXT:    fmr 3, 31
-; PC64LE-NEXT:    stfd 31, 0(4)
+; PC64LE-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
+; PC64LE-NEXT:    fmr 3, 31 # Vec Defs: F3(VSR3) Vec Uses: F31(VSR31)
+; PC64LE-NEXT:    stfd 31, 0(4) # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    bl __gcc_qadd
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    fmr 3, 1
-; PC64LE-NEXT:    fmr 4, 2
-; PC64LE-NEXT:    fmr 30, 1
-; PC64LE-NEXT:    fmr 29, 2
-; PC64LE-NEXT:    stfd 2, 24(30)
-; PC64LE-NEXT:    stfd 1, 16(30)
+; PC64LE-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    fmr 4, 2 # Vec Defs: F4(VSR4) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    fmr 29, 2 # Vec Defs: F29(VSR29) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    stfd 2, 24(30) # Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    stfd 1, 16(30) # Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    bl __gcc_qmul
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    fmr 1, 31
-; PC64LE-NEXT:    xxlxor 2, 2, 2
+; PC64LE-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
+; PC64LE-NEXT:    xxlxor 2, 2, 2 # Vec Defs: F2(VSR2)
 ; PC64LE-NEXT:    li 5, 2
-; PC64LE-NEXT:    stfd 29, 40(30)
-; PC64LE-NEXT:    stfd 30, 32(30)
+; PC64LE-NEXT:    stfd 29, 40(30) # Vec Uses: F29(VSR29)
+; PC64LE-NEXT:    stfd 30, 32(30) # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    bl __powitf2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xsrsp 0, 1
-; PC64LE-NEXT:    stfs 0, 0(29)
-; PC64LE-NEXT:    stfd 1, -16(30)
-; PC64LE-NEXT:    stfd 2, -8(30)
+; PC64LE-NEXT:    xsrsp 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    stfs 0, 0(29) # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    stfd 1, -16(30) # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    stfd 2, -8(30) # Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    lfd 31, -8(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE-NEXT:    lfd 30, -16(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE-NEXT:    ld 30, -40(1) # 8-byte Folded Reload
 ; PC64LE-NEXT:    lfd 29, -24(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F29(VSR29)
 ; PC64LE-NEXT:    ld 29, -48(1) # 8-byte Folded Reload
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: test_constrained_libcall_multichain:
 ; PC64LE9:       # %bb.0:
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 29, -48(1) # 8-byte Folded Spill
 ; PC64LE9-NEXT:    std 30, -40(1) # 8-byte Folded Spill
 ; PC64LE9-NEXT:    stfd 29, -24(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F29(VSR29)
 ; PC64LE9-NEXT:    stfd 30, -16(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, -8(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
-; PC64LE9-NEXT:    lfs 31, 0(3)
+; PC64LE9-NEXT:    lfs 31, 0(3) # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    mr 29, 3
 ; PC64LE9-NEXT:    li 3, 0
-; PC64LE9-NEXT:    xxlxor 2, 2, 2
-; PC64LE9-NEXT:    xxlxor 4, 4, 4
+; PC64LE9-NEXT:    xxlxor 2, 2, 2 # Vec Defs: F2(VSR2)
+; PC64LE9-NEXT:    xxlxor 4, 4, 4 # Vec Defs: F4(VSR4)
 ; PC64LE9-NEXT:    mr 30, 4
 ; PC64LE9-NEXT:    std 3, 8(4)
-; PC64LE9-NEXT:    fmr 1, 31
-; PC64LE9-NEXT:    fmr 3, 31
-; PC64LE9-NEXT:    stfd 31, 0(4)
+; PC64LE9-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
+; PC64LE9-NEXT:    fmr 3, 31 # Vec Defs: F3(VSR3) Vec Uses: F31(VSR31)
+; PC64LE9-NEXT:    stfd 31, 0(4) # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    bl __gcc_qadd
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    fmr 4, 2
-; PC64LE9-NEXT:    fmr 30, 1
-; PC64LE9-NEXT:    fmr 29, 2
-; PC64LE9-NEXT:    stfd 2, 24(30)
-; PC64LE9-NEXT:    stfd 1, 16(30)
+; PC64LE9-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    fmr 4, 2 # Vec Defs: F4(VSR4) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    fmr 29, 2 # Vec Defs: F29(VSR29) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    stfd 2, 24(30) # Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    stfd 1, 16(30) # Vec Uses: F1(VSR1)
 ; PC64LE9-NEXT:    bl __gcc_qmul
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    fmr 1, 31
-; PC64LE9-NEXT:    xxlxor 2, 2, 2
+; PC64LE9-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
+; PC64LE9-NEXT:    xxlxor 2, 2, 2 # Vec Defs: F2(VSR2)
 ; PC64LE9-NEXT:    li 5, 2
-; PC64LE9-NEXT:    stfd 29, 40(30)
-; PC64LE9-NEXT:    stfd 30, 32(30)
+; PC64LE9-NEXT:    stfd 29, 40(30) # Vec Uses: F29(VSR29)
+; PC64LE9-NEXT:    stfd 30, 32(30) # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    bl __powitf2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xsrsp 0, 1
-; PC64LE9-NEXT:    stfs 0, 0(29)
-; PC64LE9-NEXT:    stfd 1, -16(30)
-; PC64LE9-NEXT:    stfd 2, -8(30)
+; PC64LE9-NEXT:    xsrsp 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    stfs 0, 0(29) # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    stfd 1, -16(30) # Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    stfd 2, -8(30) # Vec Uses: F2(VSR2)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    lfd 31, -8(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    lfd 30, -16(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    ld 30, -40(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    ld 29, -48(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    lfd 29, -24(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F29(VSR29)
 ; PC64LE9-NEXT:    blr
 ;
 ; PC64-LABEL: test_constrained_libcall_multichain:
 ; PC64:       # %bb.0:
 ; PC64-NEXT:    mflr 0
 ; PC64-NEXT:    std 0, 16(1)
 ; PC64-NEXT:    stdu 1, -176(1)
 ; PC64-NEXT:    std 29, 120(1) # 8-byte Folded Spill
 ; PC64-NEXT:    mr 29, 3
 ; PC64-NEXT:    li 3, 0
 ; PC64-NEXT:    stfd 31, 168(1) # 8-byte Folded Spill
+; PC64-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64-NEXT:    std 30, 128(1) # 8-byte Folded Spill
 ; PC64-NEXT:    mr 30, 4
-; PC64-NEXT:    lfs 31, 0(29)
+; PC64-NEXT:    lfs 31, 0(29) # Vec Defs: F31(VSR31)
 ; PC64-NEXT:    std 3, 8(4)
 ; PC64-NEXT:    addis 3, 2, .LCPI32_0@toc@ha
 ; PC64-NEXT:    stfd 30, 160(1) # 8-byte Folded Spill
-; PC64-NEXT:    lfs 30, .LCPI32_0@toc@l(3)
-; PC64-NEXT:    fmr 1, 31
-; PC64-NEXT:    fmr 3, 31
+; PC64-NEXT:    # Vec Uses: F30(VSR30)
+; PC64-NEXT:    lfs 30, .LCPI32_0@toc@l(3) # Vec Defs: F30(VSR30)
+; PC64-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
+; PC64-NEXT:    fmr 3, 31 # Vec Defs: F3(VSR3) Vec Uses: F31(VSR31)
 ; PC64-NEXT:    stfd 28, 144(1) # 8-byte Folded Spill
-; PC64-NEXT:    fmr 2, 30
-; PC64-NEXT:    fmr 4, 30
+; PC64-NEXT:    # Vec Uses: F28(VSR28)
+; PC64-NEXT:    fmr 2, 30 # Vec Defs: F2(VSR2) Vec Uses: F30(VSR30)
+; PC64-NEXT:    fmr 4, 30 # Vec Defs: F4(VSR4) Vec Uses: F30(VSR30)
 ; PC64-NEXT:    stfd 29, 152(1) # 8-byte Folded Spill
-; PC64-NEXT:    stfd 31, 0(4)
+; PC64-NEXT:    # Vec Uses: F29(VSR29)
+; PC64-NEXT:    stfd 31, 0(4) # Vec Uses: F31(VSR31)
 ; PC64-NEXT:    bl __gcc_qadd
 ; PC64-NEXT:    nop
-; PC64-NEXT:    fmr 3, 1
-; PC64-NEXT:    fmr 4, 2
-; PC64-NEXT:    fmr 29, 1
-; PC64-NEXT:    fmr 28, 2
-; PC64-NEXT:    stfd 2, 24(30)
-; PC64-NEXT:    stfd 1, 16(30)
+; PC64-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64-NEXT:    fmr 4, 2 # Vec Defs: F4(VSR4) Vec Uses: F2(VSR2)
+; PC64-NEXT:    fmr 29, 1 # Vec Defs: F29(VSR29) Vec Uses: F1(VSR1)
+; PC64-NEXT:    fmr 28, 2 # Vec Defs: F28(VSR28) Vec Uses: F2(VSR2)
+; PC64-NEXT:    stfd 2, 24(30) # Vec Uses: F2(VSR2)
+; PC64-NEXT:    stfd 1, 16(30) # Vec Uses: F1(VSR1)
 ; PC64-NEXT:    bl __gcc_qmul
 ; PC64-NEXT:    nop
-; PC64-NEXT:    fmr 1, 31
-; PC64-NEXT:    fmr 2, 30
+; PC64-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
+; PC64-NEXT:    fmr 2, 30 # Vec Defs: F2(VSR2) Vec Uses: F30(VSR30)
 ; PC64-NEXT:    li 5, 2
-; PC64-NEXT:    stfd 28, 40(30)
-; PC64-NEXT:    stfd 29, 32(30)
+; PC64-NEXT:    stfd 28, 40(30) # Vec Uses: F28(VSR28)
+; PC64-NEXT:    stfd 29, 32(30) # Vec Uses: F29(VSR29)
 ; PC64-NEXT:    bl __powitf2
 ; PC64-NEXT:    nop
-; PC64-NEXT:    frsp 0, 1
-; PC64-NEXT:    stfs 0, 0(29)
+; PC64-NEXT:    frsp 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64-NEXT:    stfs 0, 0(29) # Vec Uses: F0(VSR0)
 ; PC64-NEXT:    ld 29, 120(1) # 8-byte Folded Reload
-; PC64-NEXT:    stfd 1, -16(30)
-; PC64-NEXT:    stfd 2, -8(30)
+; PC64-NEXT:    stfd 1, -16(30) # Vec Uses: F1(VSR1)
+; PC64-NEXT:    stfd 2, -8(30) # Vec Uses: F2(VSR2)
 ; PC64-NEXT:    ld 30, 128(1) # 8-byte Folded Reload
 ; PC64-NEXT:    lfd 31, 168(1) # 8-byte Folded Reload
+; PC64-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64-NEXT:    lfd 30, 160(1) # 8-byte Folded Reload
+; PC64-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64-NEXT:    lfd 29, 152(1) # 8-byte Folded Reload
+; PC64-NEXT:    # Vec Defs: F29(VSR29)
 ; PC64-NEXT:    lfd 28, 144(1) # 8-byte Folded Reload
+; PC64-NEXT:    # Vec Defs: F28(VSR28)
 ; PC64-NEXT:    addi 1, 1, 176
 ; PC64-NEXT:    ld 0, 16(1)
 ; PC64-NEXT:    mtlr 0
 ; PC64-NEXT:    blr
   %load = load float, float* %firstptr
   %first = call ppc_fp128 @llvm.experimental.constrained.fpext.f32.ppcf128(
                     float %load,
                     metadata !"fpexcept.strict") #1
; PC64-NEXT:    blr
   %stridxn1 = getelementptr ppc_fp128, ppc_fp128* %result, i32 -1
   store ppc_fp128 %powi, ppc_fp128* %stridxn1
   ret void
 }
 
 define ppc_fp128 @i32_to_ppcq(i32 signext %m) #0 {
 ; PC64LE-LABEL: i32_to_ppcq:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mtfprwa 0, 3
-; PC64LE-NEXT:    xxlxor 2, 2, 2
-; PC64LE-NEXT:    xscvsxddp 1, 0
+; PC64LE-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    xxlxor 2, 2, 2 # Vec Defs: F2(VSR2)
+; PC64LE-NEXT:    xscvsxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: i32_to_ppcq:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mtfprwa 0, 3
-; PC64LE9-NEXT:    xxlxor 2, 2, 2
-; PC64LE9-NEXT:    xscvsxddp 1, 0
+; PC64LE9-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xxlxor 2, 2, 2 # Vec Defs: F2(VSR2)
+; PC64LE9-NEXT:    xscvsxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 ;
 ; PC64-LABEL: i32_to_ppcq:
 ; PC64:       # %bb.0: # %entry
 ; PC64-NEXT:    std 3, -8(1)
 ; PC64-NEXT:    addis 3, 2, .LCPI33_0@toc@ha
-; PC64-NEXT:    lfd 0, -8(1)
-; PC64-NEXT:    lfs 2, .LCPI33_0@toc@l(3)
-; PC64-NEXT:    fcfid 1, 0
+; PC64-NEXT:    lfd 0, -8(1) # Vec Defs: F0(VSR0)
+; PC64-NEXT:    lfs 2, .LCPI33_0@toc@l(3) # Vec Defs: F2(VSR2)
+; PC64-NEXT:    fcfid 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64-NEXT:    blr
 entry:
   %conv = tail call ppc_fp128 @llvm.experimental.constrained.sitofp.ppcf128.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1
   ret ppc_fp128 %conv
 }
 
 define ppc_fp128 @i64_to_ppcq(i64 %m) #0 {
 ; PC64LE-LABEL: i64_to_ppcq:

 entry:
   %conv = tail call ppc_fp128 @llvm.experimental.constrained.sitofp.ppcf128.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1
   ret ppc_fp128 %conv
 }
 
 define ppc_fp128 @u32_to_ppcq(i32 zeroext %m) #0 {
 ; PC64LE-LABEL: u32_to_ppcq:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mtfprwz 0, 3
-; PC64LE-NEXT:    xxlxor 2, 2, 2
-; PC64LE-NEXT:    xscvuxddp 1, 0
+; PC64LE-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    xxlxor 2, 2, 2 # Vec Defs: F2(VSR2)
+; PC64LE-NEXT:    xscvuxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: u32_to_ppcq:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mtfprwz 0, 3
-; PC64LE9-NEXT:    xxlxor 2, 2, 2
-; PC64LE9-NEXT:    xscvuxddp 1, 0
+; PC64LE9-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xxlxor 2, 2, 2 # Vec Defs: F2(VSR2)
+; PC64LE9-NEXT:    xscvuxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 ;
 ; PC64-LABEL: u32_to_ppcq:
 ; PC64:       # %bb.0: # %entry
 ; PC64-NEXT:    lis 4, 17200
 ; PC64-NEXT:    stw 3, -4(1)
 ; PC64-NEXT:    addis 3, 2, .LCPI35_0@toc@ha
 ; PC64-NEXT:    stw 4, -8(1)
-; PC64-NEXT:    lfs 0, .LCPI35_0@toc@l(3)
+; PC64-NEXT:    lfs 0, .LCPI35_0@toc@l(3) # Vec Defs: F0(VSR0)
 ; PC64-NEXT:    addis 3, 2, .LCPI35_1@toc@ha
-; PC64-NEXT:    lfd 1, -8(1)
-; PC64-NEXT:    lfs 2, .LCPI35_1@toc@l(3)
-; PC64-NEXT:    fsub 1, 1, 0
+; PC64-NEXT:    lfd 1, -8(1) # Vec Defs: F1(VSR1)
+; PC64-NEXT:    lfs 2, .LCPI35_1@toc@l(3) # Vec Defs: F2(VSR2)
+; PC64-NEXT:    fsub 1, 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PC64-NEXT:    blr
 entry:
   %conv = tail call ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1
   ret ppc_fp128 %conv
 }
 
 define ppc_fp128 @u64_to_ppcq(i64 %m) #0 {
 ; PC64LE-LABEL: u64_to_ppcq:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 30, -32(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    stfd 30, -16(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, -8(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -64(1)
 ; PC64LE-NEXT:    mr 30, 3
 ; PC64LE-NEXT:    bl __floatditf
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    addis 3, 2, .LCPI36_0@toc@ha
-; PC64LE-NEXT:    xxlxor 4, 4, 4
-; PC64LE-NEXT:    fmr 30, 1
-; PC64LE-NEXT:    lfs 3, .LCPI36_0@toc@l(3)
-; PC64LE-NEXT:    fmr 31, 2
+; PC64LE-NEXT:    xxlxor 4, 4, 4 # Vec Defs: F4(VSR4)
+; PC64LE-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    lfs 3, .LCPI36_0@toc@l(3) # Vec Defs: F3(VSR3)
+; PC64LE-NEXT:    fmr 31, 2 # Vec Defs: F31(VSR31) Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    bl __gcc_qadd
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    cmpdi 30, 0
 ; PC64LE-NEXT:    blt 0, .LBB36_2
 ; PC64LE-NEXT:  # %bb.1: # %entry
-; PC64LE-NEXT:    fmr 1, 30
+; PC64LE-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:  .LBB36_2: # %entry
 ; PC64LE-NEXT:    blt 0, .LBB36_4
 ; PC64LE-NEXT:  # %bb.3: # %entry
-; PC64LE-NEXT:    fmr 2, 31
+; PC64LE-NEXT:    fmr 2, 31 # Vec Defs: F2(VSR2) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:  .LBB36_4: # %entry
 ; PC64LE-NEXT:    addi 1, 1, 64
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    lfd 31, -8(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE-NEXT:    lfd 30, -16(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE-NEXT:    ld 30, -32(1) # 8-byte Folded Reload
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: u64_to_ppcq:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 30, -32(1) # 8-byte Folded Spill
 ; PC64LE9-NEXT:    stfd 30, -16(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, -8(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    mr 30, 3
 ; PC64LE9-NEXT:    bl __floatditf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI36_0@toc@ha
-; PC64LE9-NEXT:    xxlxor 4, 4, 4
-; PC64LE9-NEXT:    fmr 30, 1
-; PC64LE9-NEXT:    fmr 31, 2
-; PC64LE9-NEXT:    lfs 3, .LCPI36_0@toc@l(3)
+; PC64LE9-NEXT:    xxlxor 4, 4, 4 # Vec Defs: F4(VSR4)
+; PC64LE9-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    fmr 31, 2 # Vec Defs: F31(VSR31) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    lfs 3, .LCPI36_0@toc@l(3) # Vec Defs: F3(VSR3)
 ; PC64LE9-NEXT:    bl __gcc_qadd
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    cmpdi 30, 0
 ; PC64LE9-NEXT:    blt 0, .LBB36_2
 ; PC64LE9-NEXT:  # %bb.1: # %entry
-; PC64LE9-NEXT:    fmr 1, 30
+; PC64LE9-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:  .LBB36_2: # %entry
 ; PC64LE9-NEXT:    blt 0, .LBB36_4
 ; PC64LE9-NEXT:  # %bb.3: # %entry
-; PC64LE9-NEXT:    fmr 2, 31
+; PC64LE9-NEXT:    fmr 2, 31 # Vec Defs: F2(VSR2) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:  .LBB36_4: # %entry
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    lfd 31, -8(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    lfd 30, -16(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    ld 30, -32(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 ;
 ; PC64-LABEL: u64_to_ppcq:
 ; PC64:       # %bb.0: # %entry
 ; PC64-NEXT:    mflr 0
 ; PC64-NEXT:    std 0, 16(1)
 ; PC64-NEXT:    stdu 1, -144(1)
 ; PC64-NEXT:    std 30, 112(1) # 8-byte Folded Spill
 ; PC64-NEXT:    stfd 30, 128(1) # 8-byte Folded Spill
+; PC64-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64-NEXT:    mr 30, 3
 ; PC64-NEXT:    stfd 31, 136(1) # 8-byte Folded Spill
+; PC64-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64-NEXT:    bl __floatditf
 ; PC64-NEXT:    nop
 ; PC64-NEXT:    addis 3, 2, .LCPI36_0@toc@ha
-; PC64-NEXT:    fmr 31, 2
-; PC64-NEXT:    lfs 3, .LCPI36_0@toc@l(3)
+; PC64-NEXT:    fmr 31, 2 # Vec Defs: F31(VSR31) Vec Uses: F2(VSR2)
+; PC64-NEXT:    lfs 3, .LCPI36_0@toc@l(3) # Vec Defs: F3(VSR3)
 ; PC64-NEXT:    addis 3, 2, .LCPI36_1@toc@ha
-; PC64-NEXT:    fmr 30, 1
-; PC64-NEXT:    lfs 4, .LCPI36_1@toc@l(3)
+; PC64-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64-NEXT:    lfs 4, .LCPI36_1@toc@l(3) # Vec Defs: F4(VSR4)
 ; PC64-NEXT:    bl __gcc_qadd
 ; PC64-NEXT:    nop
 ; PC64-NEXT:    cmpdi 30, 0
 ; PC64-NEXT:    blt 0, .LBB36_2
 ; PC64-NEXT:  # %bb.1: # %entry
-; PC64-NEXT:    fmr 1, 30
+; PC64-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64-NEXT:  .LBB36_2: # %entry
 ; PC64-NEXT:    blt 0, .LBB36_4
 ; PC64-NEXT:  # %bb.3: # %entry
-; PC64-NEXT:    fmr 2, 31
+; PC64-NEXT:    fmr 2, 31 # Vec Defs: F2(VSR2) Vec Uses: F31(VSR31)
 ; PC64-NEXT:  .LBB36_4: # %entry
 ; PC64-NEXT:    lfd 31, 136(1) # 8-byte Folded Reload
+; PC64-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64-NEXT:    ld 30, 112(1) # 8-byte Folded Reload
 ; PC64-NEXT:    lfd 30, 128(1) # 8-byte Folded Reload
+; PC64-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64-NEXT:    addi 1, 1, 144
 ; PC64-NEXT:    ld 0, 16(1)
 ; PC64-NEXT:    mtlr 0
 ; PC64-NEXT:    blr
 entry:
   %conv = tail call ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1
   ret ppc_fp128 %conv
 }

 }
 
 define ppc_fp128 @u128_to_ppcq(i128 %m) #0 {
 ; PC64LE-LABEL: u128_to_ppcq:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 30, -32(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    stfd 30, -16(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, -8(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -64(1)
 ; PC64LE-NEXT:    mr 30, 4
 ; PC64LE-NEXT:    bl __floattitf
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    addis 3, 2, .LCPI38_0@toc@ha
-; PC64LE-NEXT:    xxlxor 4, 4, 4
-; PC64LE-NEXT:    fmr 30, 1
-; PC64LE-NEXT:    lfd 3, .LCPI38_0@toc@l(3)
-; PC64LE-NEXT:    fmr 31, 2
+; PC64LE-NEXT:    xxlxor 4, 4, 4 # Vec Defs: F4(VSR4)
+; PC64LE-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    lfd 3, .LCPI38_0@toc@l(3) # Vec Defs: F3(VSR3)
+; PC64LE-NEXT:    fmr 31, 2 # Vec Defs: F31(VSR31) Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    bl __gcc_qadd
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    cmpdi 30, 0
 ; PC64LE-NEXT:    blt 0, .LBB38_2
 ; PC64LE-NEXT:  # %bb.1: # %entry
-; PC64LE-NEXT:    fmr 1, 30
+; PC64LE-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:  .LBB38_2: # %entry
 ; PC64LE-NEXT:    blt 0, .LBB38_4
 ; PC64LE-NEXT:  # %bb.3: # %entry
-; PC64LE-NEXT:    fmr 2, 31
+; PC64LE-NEXT:    fmr 2, 31 # Vec Defs: F2(VSR2) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:  .LBB38_4: # %entry
 ; PC64LE-NEXT:    addi 1, 1, 64
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    lfd 31, -8(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE-NEXT:    lfd 30, -16(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE-NEXT:    ld 30, -32(1) # 8-byte Folded Reload
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: u128_to_ppcq:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 30, -32(1) # 8-byte Folded Spill
 ; PC64LE9-NEXT:    stfd 30, -16(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, -8(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    mr 30, 4
 ; PC64LE9-NEXT:    bl __floattitf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI38_0@toc@ha
-; PC64LE9-NEXT:    xxlxor 4, 4, 4
-; PC64LE9-NEXT:    fmr 30, 1
-; PC64LE9-NEXT:    lfd 3, .LCPI38_0@toc@l(3)
-; PC64LE9-NEXT:    fmr 31, 2
+; PC64LE9-NEXT:    xxlxor 4, 4, 4 # Vec Defs: F4(VSR4)
+; PC64LE9-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    lfd 3, .LCPI38_0@toc@l(3) # Vec Defs: F3(VSR3)
+; PC64LE9-NEXT:    fmr 31, 2 # Vec Defs: F31(VSR31) Vec Uses: F2(VSR2)
 ; PC64LE9-NEXT:    bl __gcc_qadd
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    cmpdi 30, 0
 ; PC64LE9-NEXT:    blt 0, .LBB38_2
 ; PC64LE9-NEXT:  # %bb.1: # %entry
-; PC64LE9-NEXT:    fmr 1, 30
+; PC64LE9-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:  .LBB38_2: # %entry
 ; PC64LE9-NEXT:    blt 0, .LBB38_4
 ; PC64LE9-NEXT:  # %bb.3: # %entry
-; PC64LE9-NEXT:    fmr 2, 31
+; PC64LE9-NEXT:    fmr 2, 31 # Vec Defs: F2(VSR2) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:  .LBB38_4: # %entry
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    lfd 31, -8(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    lfd 30, -16(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    ld 30, -32(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 ;
 ; PC64-LABEL: u128_to_ppcq:
 ; PC64:       # %bb.0: # %entry
 ; PC64-NEXT:    mflr 0
 ; PC64-NEXT:    std 0, 16(1)
 ; PC64-NEXT:    stdu 1, -144(1)
 ; PC64-NEXT:    std 30, 112(1) # 8-byte Folded Spill
 ; PC64-NEXT:    stfd 30, 128(1) # 8-byte Folded Spill
+; PC64-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64-NEXT:    mr 30, 3
 ; PC64-NEXT:    stfd 31, 136(1) # 8-byte Folded Spill
+; PC64-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64-NEXT:    bl __floattitf
 ; PC64-NEXT:    nop
 ; PC64-NEXT:    addis 3, 2, .LCPI38_0@toc@ha
-; PC64-NEXT:    fmr 31, 2
-; PC64-NEXT:    lfd 3, .LCPI38_0@toc@l(3)
+; PC64-NEXT:    fmr 31, 2 # Vec Defs: F31(VSR31) Vec Uses: F2(VSR2)
+; PC64-NEXT:    lfd 3, .LCPI38_0@toc@l(3) # Vec Defs: F3(VSR3)
 ; PC64-NEXT:    addis 3, 2, .LCPI38_1@toc@ha
-; PC64-NEXT:    fmr 30, 1
-; PC64-NEXT:    lfs 4, .LCPI38_1@toc@l(3)
+; PC64-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64-NEXT:    lfs 4, .LCPI38_1@toc@l(3) # Vec Defs: F4(VSR4)
 ; PC64-NEXT:    bl __gcc_qadd
 ; PC64-NEXT:    nop
 ; PC64-NEXT:    cmpdi 30, 0
 ; PC64-NEXT:    blt 0, .LBB38_2
 ; PC64-NEXT:  # %bb.1: # %entry
-; PC64-NEXT:    fmr 1, 30
+; PC64-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64-NEXT:  .LBB38_2: # %entry
 ; PC64-NEXT:    blt 0, .LBB38_4
 ; PC64-NEXT:  # %bb.3: # %entry
-; PC64-NEXT:    fmr 2, 31
+; PC64-NEXT:    fmr 2, 31 # Vec Defs: F2(VSR2) Vec Uses: F31(VSR31)
 ; PC64-NEXT:  .LBB38_4: # %entry
 ; PC64-NEXT:    lfd 31, 136(1) # 8-byte Folded Reload
+; PC64-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64-NEXT:    ld 30, 112(1) # 8-byte Folded Reload
 ; PC64-NEXT:    lfd 30, 128(1) # 8-byte Folded Reload
+; PC64-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64-NEXT:    addi 1, 1, 144
 ; PC64-NEXT:    ld 0, 16(1)
 ; PC64-NEXT:    mtlr 0
 ; PC64-NEXT:    blr
 entry:
   %conv = tail call ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i128(i128 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1
   ret ppc_fp128 %conv
 }

llvm/test/CodeGen/PowerPC/pr48519.ll

 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -48(r1)
 ; CHECK-NEXT:    li r3, 1
 ; CHECK-NEXT:    li r30, 0
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_1: # %bb3
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    addi r3, r3, -1
-; CHECK-NEXT:    mtfprd f0, r3
-; CHECK-NEXT:    xscvsxdsp f1, f0
+; CHECK-NEXT:    mtfprd f0, r3 # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    xscvsxdsp f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    bl __gnu_f2h_ieee
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    bl __gnu_h2f_ieee
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi r30, r30, -1
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    cmpldi r30, 0
 ; CHECK-NEXT:    bne+ cr0, .LBB0_1
 ; CHECK-NEXT:  # %bb.2: # %bb11
 ; CHECK-NEXT:    bl __gnu_f2h_ieee
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    sth r3, 0(r3)
 ;
 ; CHECK-P9-LABEL: julia__typed_vcat_20:
 ; CHECK-P9:       # %bb.0: # %bb
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    mtctr r3
 ; CHECK-P9-NEXT:    li r3, 1
 ; CHECK-P9-NEXT:    .p2align 4
 ; CHECK-P9-NEXT:  .LBB0_1: # %bb3
 ; CHECK-P9-NEXT:    #
 ; CHECK-P9-NEXT:    addi r3, r3, -1
-; CHECK-P9-NEXT:    mtfprd f0, r3
-; CHECK-P9-NEXT:    xscvsxdsp f0, f0
-; CHECK-P9-NEXT:    xscvdphp f0, f0
-; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3 # Vec Defs: F0(VSR0)
+; CHECK-P9-NEXT:    xscvsxdsp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-P9-NEXT:    xscvdphp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-P9-NEXT:    mffprwz r3, f0 # Vec Uses: F0(VSR0)
 ; CHECK-P9-NEXT:    clrlwi r3, r3, 16
-; CHECK-P9-NEXT:    mtfprwz f0, r3
+; CHECK-P9-NEXT:    mtfprwz f0, r3 # Vec Defs: F0(VSR0)
 ; CHECK-P9-NEXT:    li r3, 0
-; CHECK-P9-NEXT:    xscvhpdp f0, f0
+; CHECK-P9-NEXT:    xscvhpdp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
 ; CHECK-P9-NEXT:    bdnz .LBB0_1
 ; CHECK-P9-NEXT:  # %bb.2: # %bb11
-; CHECK-P9-NEXT:    xscvdphp f0, f0
-; CHECK-P9-NEXT:    stxsihx f0, 0, r3
+; CHECK-P9-NEXT:    xscvdphp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-P9-NEXT:    stxsihx f0, 0, r3 # Vec Uses: F0(VSR0)
 bb:
   %i = load i64, i64 addrspace(11)* null, align 8
   %i1 = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %i, i64 0)
   %i2 = extractvalue { i64, i1 } %i1, 0
   br label %bb3
 
 bb3:                                              ; preds = %bb3, %bb
   %i4 = phi i64 [ %i10, %bb3 ], [ 1, %bb ]

 ; CHECK-NEXT:    addi r30, r30, -1
 ; CHECK-NEXT:    cmpldi r30, 0
 ; CHECK-NEXT:    beq cr0, .LBB1_3
 ; CHECK-NEXT:  # %bb.2: # %bb3
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lhz r3, 0(0)
 ; CHECK-NEXT:    bl __gnu_h2f_ieee
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    fcmpu cr0, f1, f1
+; CHECK-NEXT:    fcmpu cr0, f1, f1 # Vec Uses: F1(VSR1)F1(VSR1)
 ; CHECK-NEXT:    bun cr0, .LBB1_1
 ; CHECK-NEXT:  .LBB1_3: # %bb9
 ; CHECK-NEXT:    addi r1, r1, 48
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: julia__hypot_17:
 ; CHECK-P9:       # %bb.0: # %bb
 ; CHECK-P9-NEXT:    li r3, 3
 ; CHECK-P9-NEXT:    mtctr r3
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    .p2align 5
 ; CHECK-P9-NEXT:  .LBB1_1: # %bb1
 ; CHECK-P9-NEXT:    #
 ; CHECK-P9-NEXT:    bdzlr
 ; CHECK-P9-NEXT:  # %bb.2: # %bb3
 ; CHECK-P9-NEXT:    #
-; CHECK-P9-NEXT:    lxsihzx f0, 0, r3
-; CHECK-P9-NEXT:    xscvhpdp f0, f0
-; CHECK-P9-NEXT:    fcmpu cr0, f0, f0
+; CHECK-P9-NEXT:    lxsihzx f0, 0, r3 # Vec Defs: F0(VSR0)
+; CHECK-P9-NEXT:    xscvhpdp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-P9-NEXT:    fcmpu cr0, f0, f0 # Vec Uses: F0(VSR0)F0(VSR0)
 ; CHECK-P9-NEXT:    bun cr0, .LBB1_1
 ; CHECK-P9-NEXT:  # %bb.3: # %bb9
 ; CHECK-P9-NEXT:    blr
 bb:
   br label %bb1
 
 bb1:                                              ; preds = %bb3, %bb
   %i = phi i64 [ %i4, %bb3 ], [ 2, %bb ]

 ; CHECK-P9-NEXT:  .LBB2_1: # %bb10
 ; CHECK-P9-NEXT:    #
 ; CHECK-P9-NEXT:    bdzlr
 ; CHECK-P9-NEXT:  .LBB2_2: # %bb2
 ; CHECK-P9-NEXT:    #
 ; CHECK-P9-NEXT:    bc 12, 4*cr5+lt, .LBB2_1
 ; CHECK-P9-NEXT:  # %bb.3: # %bb4
 ; CHECK-P9-NEXT:    #
-; CHECK-P9-NEXT:    lxsihzx f0, 0, r3
-; CHECK-P9-NEXT:    xscvhpdp f0, f0
+; CHECK-P9-NEXT:    lxsihzx f0, 0, r3 # Vec Defs: F0(VSR0)
+; CHECK-P9-NEXT:    xscvhpdp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
 ; CHECK-P9-NEXT:    bc 4, 4*cr5+lt, .LBB2_5
 ; CHECK-P9-NEXT:  # %bb.4: # %bb8
 ; CHECK-P9-NEXT:    #
-; CHECK-P9-NEXT:    xscvdphp f0, f0
-; CHECK-P9-NEXT:    stxsihx f0, 0, r3
+; CHECK-P9-NEXT:    xscvdphp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-P9-NEXT:    stxsihx f0, 0, r3 # Vec Uses: F0(VSR0)
 ; CHECK-P9-NEXT:    b .LBB2_1
 ; CHECK-P9-NEXT:  .LBB2_5: # %bb15
 bb:
   %i = load i64, i64 addrspace(11)* undef, align 8
   %i1 = load i64, i64 addrspace(11)* undef, align 8
   br label %bb2
 
 bb2:                                              ; preds = %bb12, %bb

 
 define void @func_48785(half %arg) #0 {
 ; CHECK-LABEL: func_48785:
 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    std r29, -32(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r30, -24(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stfd f31, -8(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F31(VSR31)
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -64(r1)
-; CHECK-NEXT:    fmr f31, f1
+; CHECK-NEXT:    fmr f31, f1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
 ; CHECK-NEXT:    li r30, 0
 ; CHECK-NEXT:    li r29, 0
 ; CHECK-NEXT:    .p2align 5
 ; CHECK-NEXT:  .LBB3_1: # %bb1
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    fmr f1, f31
+; CHECK-NEXT:    fmr f1, f31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; CHECK-NEXT:    bl __gnu_f2h_ieee
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi r29, r29, -12
 ; CHECK-NEXT:    sth r3, 0(r30)
 ; CHECK-NEXT:    addi r30, r30, 24
 ; CHECK-NEXT:    cmpldi r29, 0
 ; CHECK-NEXT:    bne+ cr0, .LBB3_1
 ; CHECK-NEXT:  # %bb.2: # %bb5
 ;
 ; CHECK-P9-LABEL: func_48785:
 ; CHECK-P9:       # %bb.0: # %bb
 ; CHECK-P9-NEXT:    li r3, 1
 ; CHECK-P9-NEXT:    rldic r3, r3, 62, 1
 ; CHECK-P9-NEXT:    mtctr r3
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    .p2align 4
 ; CHECK-P9-NEXT:  .LBB3_1: # %bb1
 ; CHECK-P9-NEXT:    #
-; CHECK-P9-NEXT:    xscvdphp f0, f1
-; CHECK-P9-NEXT:    stxsihx f0, 0, r3
+; CHECK-P9-NEXT:    xscvdphp f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; CHECK-P9-NEXT:    stxsihx f0, 0, r3 # Vec Uses: F0(VSR0)
 ; CHECK-P9-NEXT:    addi r3, r3, 24
 ; CHECK-P9-NEXT:    bdnz .LBB3_1
 ; CHECK-P9-NEXT:  # %bb.2: # %bb5
 bb:
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb
   %i = phi i64 [ 0, %bb ], [ %i3, %bb1 ]

llvm/test/CodeGen/PowerPC/reg-scavenging.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
 
 define dso_local signext i32 @caller(i32 signext %a, i32 signext %b) local_unnamed_addr {
 ; CHECK-LABEL: caller:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -240(r1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 240
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    .cfi_offset v20, -192
 ; CHECK-NEXT:    li r5, 48
 ; CHECK-NEXT:    stvx v20, r1, r5 # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V20(VSR52)
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    add r3, r3, r4
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    bl callee
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    li r4, 48
 ; CHECK-NEXT:    lvx v20, r1, r4 # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V20(VSR52)
 ; CHECK-NEXT:    addi r1, r1, 240
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    blr
 entry:
   %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{v20}"(i32 %a, i32 %b)
   %call = tail call signext i32 @callee(i32 signext %0)
   ret i32 %call
 }
 
 declare signext i32 @callee(i32 signext) local_unnamed_addr
 

llvm/test/CodeGen/PowerPC/spill-vec-pair.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O3 \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O3 \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   < %s | FileCheck %s --check-prefix=CHECK-BE
 define dso_local void @test(<256 x i1>* %vpp, <256 x i1>* %vp2) local_unnamed_addr #0 {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    stdu r1, -400(r1)
 ; CHECK-NEXT:    stfd f14, 256(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F14(VSR14)
 ; CHECK-NEXT:    stfd f15, 264(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F15(VSR15)
 ; CHECK-NEXT:    stfd f16, 272(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F16(VSR16)
 ; CHECK-NEXT:    stfd f17, 280(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F17(VSR17)
 ; CHECK-NEXT:    stfd f18, 288(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F18(VSR18)
 ; CHECK-NEXT:    stfd f19, 296(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F19(VSR19)
 ; CHECK-NEXT:    stfd f20, 304(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F20(VSR20)
 ; CHECK-NEXT:    stfd f21, 312(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F21(VSR21)
 ; CHECK-NEXT:    stfd f22, 320(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F22(VSR22)
 ; CHECK-NEXT:    stfd f23, 328(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F23(VSR23)
 ; CHECK-NEXT:    stfd f24, 336(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F24(VSR24)
 ; CHECK-NEXT:    stfd f25, 344(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F25(VSR25)
 ; CHECK-NEXT:    stfd f26, 352(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F26(VSR26)
 ; CHECK-NEXT:    stfd f27, 360(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F27(VSR27)
 ; CHECK-NEXT:    stfd f28, 368(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F28(VSR28)
 ; CHECK-NEXT:    stfd f29, 376(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F29(VSR29)
 ; CHECK-NEXT:    stfd f30, 384(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F30(VSR30)
 ; CHECK-NEXT:    stfd f31, 392(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: F31(VSR31)
 ; CHECK-NEXT:    stxv v20, 64(r1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V20(VSR52)
 ; CHECK-NEXT:    stxv v21, 80(r1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V21(VSR53)
 ; CHECK-NEXT:    stxv v22, 96(r1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V22(VSR54)
 ; CHECK-NEXT:    stxv v23, 112(r1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V23(VSR55)
 ; CHECK-NEXT:    stxv v24, 128(r1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V24(VSR56)
 ; CHECK-NEXT:    stxv v25, 144(r1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V25(VSR57)
 ; CHECK-NEXT:    stxv v26, 160(r1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V26(VSR58)
 ; CHECK-NEXT:    stxv v27, 176(r1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V27(VSR59)
 ; CHECK-NEXT:    stxv v28, 192(r1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V28(VSR60)
 ; CHECK-NEXT:    stxv v29, 208(r1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V29(VSR61)
 ; CHECK-NEXT:    stxv v30, 224(r1) # 16-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: V30(VSR62)
 ; CHECK-NEXT:    stxv v31, 240(r1) # 16-byte Folded Spill
-; CHECK-NEXT:    lxvp vsp34, 0(r3)
+; CHECK-NEXT:    # Vec Uses: V31(VSR63)
+; CHECK-NEXT:    lxvp vsp34, 0(r3) # Vec Defs: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    stxvp vsp34, 32(r1) # 32-byte Folded Spill
+; CHECK-NEXT:    # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    lxvp vsp34, 32(r1) # 32-byte Folded Reload
-; CHECK-NEXT:    stxvp vsp34, 0(r4)
+; CHECK-NEXT:    # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-NEXT:    stxvp vsp34, 0(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-NEXT:    lxv v31, 240(r1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-NEXT:    lxv v30, 224(r1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V30(VSR62)
 ; CHECK-NEXT:    lxv v29, 208(r1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V29(VSR61)
 ; CHECK-NEXT:    lxv v28, 192(r1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V28(VSR60)
 ; CHECK-NEXT:    lxv v27, 176(r1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V27(VSR59)
 ; CHECK-NEXT:    lxv v26, 160(r1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V26(VSR58)
 ; CHECK-NEXT:    lxv v25, 144(r1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V25(VSR57)
 ; CHECK-NEXT:    lxv v24, 128(r1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V24(VSR56)
 ; CHECK-NEXT:    lxv v23, 112(r1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V23(VSR55)
 ; CHECK-NEXT:    lxv v22, 96(r1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V22(VSR54)
 ; CHECK-NEXT:    lxv v21, 80(r1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V21(VSR53)
 ; CHECK-NEXT:    lxv v20, 64(r1) # 16-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: V20(VSR52)
 ; CHECK-NEXT:    lfd f31, 392(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F31(VSR31)
 ; CHECK-NEXT:    lfd f30, 384(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F30(VSR30)
 ; CHECK-NEXT:    lfd f29, 376(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F29(VSR29)
 ; CHECK-NEXT:    lfd f28, 368(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F28(VSR28)
 ; CHECK-NEXT:    lfd f27, 360(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F27(VSR27)
 ; CHECK-NEXT:    lfd f26, 352(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F26(VSR26)
 ; CHECK-NEXT:    lfd f25, 344(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F25(VSR25)
 ; CHECK-NEXT:    lfd f24, 336(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F24(VSR24)
 ; CHECK-NEXT:    lfd f23, 328(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F23(VSR23)
 ; CHECK-NEXT:    lfd f22, 320(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F22(VSR22)
 ; CHECK-NEXT:    lfd f21, 312(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F21(VSR21)
 ; CHECK-NEXT:    lfd f20, 304(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F20(VSR20)
 ; CHECK-NEXT:    lfd f19, 296(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F19(VSR19)
 ; CHECK-NEXT:    lfd f18, 288(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F18(VSR18)
 ; CHECK-NEXT:    lfd f17, 280(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F17(VSR17)
 ; CHECK-NEXT:    lfd f16, 272(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F16(VSR16)
 ; CHECK-NEXT:    lfd f15, 264(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F15(VSR15)
 ; CHECK-NEXT:    lfd f14, 256(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    # Vec Defs: F14(VSR14)
 ; CHECK-NEXT:    addi r1, r1, 400
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    stdu r1, -416(r1)
 ; CHECK-BE-NEXT:    stfd f14, 272(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F14(VSR14)
 ; CHECK-BE-NEXT:    stfd f15, 280(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F15(VSR15)
 ; CHECK-BE-NEXT:    stfd f16, 288(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F16(VSR16)
 ; CHECK-BE-NEXT:    stfd f17, 296(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F17(VSR17)
 ; CHECK-BE-NEXT:    stfd f18, 304(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F18(VSR18)
 ; CHECK-BE-NEXT:    stfd f19, 312(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F19(VSR19)
 ; CHECK-BE-NEXT:    stfd f20, 320(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F20(VSR20)
 ; CHECK-BE-NEXT:    stfd f21, 328(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F21(VSR21)
 ; CHECK-BE-NEXT:    stfd f22, 336(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F22(VSR22)
 ; CHECK-BE-NEXT:    stfd f23, 344(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F23(VSR23)
 ; CHECK-BE-NEXT:    stfd f24, 352(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F24(VSR24)
 ; CHECK-BE-NEXT:    stfd f25, 360(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F25(VSR25)
 ; CHECK-BE-NEXT:    stfd f26, 368(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F26(VSR26)
 ; CHECK-BE-NEXT:    stfd f27, 376(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F27(VSR27)
 ; CHECK-BE-NEXT:    stfd f28, 384(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F28(VSR28)
 ; CHECK-BE-NEXT:    stfd f29, 392(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F29(VSR29)
 ; CHECK-BE-NEXT:    stfd f30, 400(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F30(VSR30)
 ; CHECK-BE-NEXT:    stfd f31, 408(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: F31(VSR31)
 ; CHECK-BE-NEXT:    stxv v20, 80(r1) # 16-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: V20(VSR52)
 ; CHECK-BE-NEXT:    stxv v21, 96(r1) # 16-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: V21(VSR53)
 ; CHECK-BE-NEXT:    stxv v22, 112(r1) # 16-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: V22(VSR54)
 ; CHECK-BE-NEXT:    stxv v23, 128(r1) # 16-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: V23(VSR55)
 ; CHECK-BE-NEXT:    stxv v24, 144(r1) # 16-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: V24(VSR56)
 ; CHECK-BE-NEXT:    stxv v25, 160(r1) # 16-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: V25(VSR57)
 ; CHECK-BE-NEXT:    stxv v26, 176(r1) # 16-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: V26(VSR58)
 ; CHECK-BE-NEXT:    stxv v27, 192(r1) # 16-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: V27(VSR59)
 ; CHECK-BE-NEXT:    stxv v28, 208(r1) # 16-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: V28(VSR60)
 ; CHECK-BE-NEXT:    stxv v29, 224(r1) # 16-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: V29(VSR61)
 ; CHECK-BE-NEXT:    stxv v30, 240(r1) # 16-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: V30(VSR62)
 ; CHECK-BE-NEXT:    stxv v31, 256(r1) # 16-byte Folded Spill
-; CHECK-BE-NEXT:    lxvp vsp34, 0(r3)
+; CHECK-BE-NEXT:    # Vec Uses: V31(VSR63)
+; CHECK-BE-NEXT:    lxvp vsp34, 0(r3) # Vec Defs: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    stxvp vsp34, 48(r1) # 32-byte Folded Spill
+; CHECK-BE-NEXT:    # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    #APP
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:    #NO_APP
 ; CHECK-BE-NEXT:    lxvp vsp34, 48(r1) # 32-byte Folded Reload
-; CHECK-BE-NEXT:    stxvp vsp34, 0(r4)
+; CHECK-BE-NEXT:    # Vec Defs: VSRp17(VSR34,VSR35)
+; CHECK-BE-NEXT:    stxvp vsp34, 0(r4) # Vec Uses: VSRp17(VSR34,VSR35)
 ; CHECK-BE-NEXT:    lxv v31, 256(r1) # 16-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: V31(VSR63)
 ; CHECK-BE-NEXT:    lxv v30, 240(r1) # 16-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: V30(VSR62)
 ; CHECK-BE-NEXT:    lxv v29, 224(r1) # 16-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: V29(VSR61)
 ; CHECK-BE-NEXT:    lxv v28, 208(r1) # 16-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: V28(VSR60)
 ; CHECK-BE-NEXT:    lxv v27, 192(r1) # 16-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: V27(VSR59)
 ; CHECK-BE-NEXT:    lxv v26, 176(r1) # 16-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: V26(VSR58)
 ; CHECK-BE-NEXT:    lxv v25, 160(r1) # 16-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: V25(VSR57)
 ; CHECK-BE-NEXT:    lxv v24, 144(r1) # 16-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: V24(VSR56)
 ; CHECK-BE-NEXT:    lxv v23, 128(r1) # 16-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: V23(VSR55)
 ; CHECK-BE-NEXT:    lxv v22, 112(r1) # 16-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: V22(VSR54)
 ; CHECK-BE-NEXT:    lxv v21, 96(r1) # 16-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: V21(VSR53)
 ; CHECK-BE-NEXT:    lxv v20, 80(r1) # 16-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: V20(VSR52)
 ; CHECK-BE-NEXT:    lfd f31, 408(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F31(VSR31)
 ; CHECK-BE-NEXT:    lfd f30, 400(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F30(VSR30)
 ; CHECK-BE-NEXT:    lfd f29, 392(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F29(VSR29)
 ; CHECK-BE-NEXT:    lfd f28, 384(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F28(VSR28)
 ; CHECK-BE-NEXT:    lfd f27, 376(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F27(VSR27)
 ; CHECK-BE-NEXT:    lfd f26, 368(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F26(VSR26)
 ; CHECK-BE-NEXT:    lfd f25, 360(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F25(VSR25)
 ; CHECK-BE-NEXT:    lfd f24, 352(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F24(VSR24)
 ; CHECK-BE-NEXT:    lfd f23, 344(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F23(VSR23)
 ; CHECK-BE-NEXT:    lfd f22, 336(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F22(VSR22)
 ; CHECK-BE-NEXT:    lfd f21, 328(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F21(VSR21)
 ; CHECK-BE-NEXT:    lfd f20, 320(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F20(VSR20)
 ; CHECK-BE-NEXT:    lfd f19, 312(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F19(VSR19)
 ; CHECK-BE-NEXT:    lfd f18, 304(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F18(VSR18)
 ; CHECK-BE-NEXT:    lfd f17, 296(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F17(VSR17)
 ; CHECK-BE-NEXT:    lfd f16, 288(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F16(VSR16)
 ; CHECK-BE-NEXT:    lfd f15, 280(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F15(VSR15)
 ; CHECK-BE-NEXT:    lfd f14, 272(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    # Vec Defs: F14(VSR14)
 ; CHECK-BE-NEXT:    addi r1, r1, 416
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %0)
   tail call void asm sideeffect "nop", "~{memory},~{vs0},~{vs1},~{vs2},~{vs3},~{vs4},~{vs5},~{vs6},~{vs7},~{vs8},~{vs9},~{vs10},~{vs11},~{vs12},~{vs13},~{vs14},~{vs15},~{vs16},~{vs17},~{vs18},~{vs19},~{vs20},~{vs21},~{vs22},~{vs23},~{vs24},~{vs25},~{vs26},~{vs27},~{vs28},~{vs29},~{vs30},~{vs31},~{vs32},~{vs33},~{vs34},~{vs35},~{vs36},~{vs37},~{vs38},~{vs39},~{vs40},~{vs41},~{vs42},~{vs43},~{vs44},~{vs45},~{vs46},~{vs47},~{vs48},~{vs49},~{vs50},~{vs51},~{vs52},~{vs53},~{vs54},~{vs55},~{vs56},~{vs57},~{vs58},~{vs59},~{vs60},~{vs61},~{vs62},~{vs63}"()
   %2 = bitcast <256 x i1>* %vp2 to i8*
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, i8* %2)
   ret void
 }
 
 declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*) #1
 
 declare void @llvm.ppc.vsx.stxvp(<256 x i1>, i8*) #2
 
 attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/vec-bswap.ll

 
 define dso_local void @test(i32* %Arr, i32 signext %Len) {
 ; CHECK-LABEL: test:
 ; CHECK:         lxv [[REG:vs[0-9]+]], 0(r{{[0-9]+}})
 ; CHECK-NOT:     [[REG]]
 ; CHECK:         xxbrw vs{{[0-9]+}}, [[REG]]
 
 ; AIX-LABEL:     test:
-; AIX64:         lxv [[REG64:[0-9]+]], {{[0-9]+}}({{[0-9]+}})
+; AIX64:         lxv [[REG64:[0-9]+]], {{[0-9]+}}({{[0-9]+}}) # Vec Defs: VSL[[REG64]](VSR[[REG64]])
 ; AIX32:         lxv [[REG32:[0-9]+]], {{[0-9]+}}({{[0-9]+}})
 ; AIX64-NOT:     [[REG64]]
 ; AIX64:         xxbrw {{[0-9]+}}, [[REG64]]
 ; AIX32:         xxbrw {{[0-9]+}}, [[REG32]]
 entry:
   %cmp1 = icmp slt i32 0, %Len
   br i1 %cmp1, label %for.body.lr.ph, label %for.cond.cleanup
 

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -O3 -mtriple=powerpc64le-linux-gnu < %s | FileCheck --check-prefix=PC64LE %s
 ; RUN: llc -O3 -mtriple=powerpc64le-linux-gnu -mcpu=pwr9 < %s | FileCheck --check-prefix=PC64LE9 %s
 
 define <1 x float> @constrained_vector_fdiv_v1f32(<1 x float> %x, <1 x float> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fdiv_v1f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xsdivsp 1, 1, 2
+; PC64LE-NEXT:    xsdivsp 1, 1, 2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fdiv_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xsdivsp 1, 1, 2
+; PC64LE9-NEXT:    xsdivsp 1, 1, 2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; PC64LE9-NEXT:    blr
 entry:
   %div = call <1 x float> @llvm.experimental.constrained.fdiv.v1f32(
            <1 x float> %x,
            <1 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <1 x float> %div
 }
 
 define <2 x double> @constrained_vector_fdiv_v2f64(<2 x double> %x, <2 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fdiv_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvdivdp 34, 34, 35
+; PC64LE-NEXT:    xvdivdp 34, 34, 35 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fdiv_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvdivdp 34, 34, 35
+; PC64LE9-NEXT:    xvdivdp 34, 34, 35 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %div = call <2 x double> @llvm.experimental.constrained.fdiv.v2f64(
            <2 x double> %x,
            <2 x double> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <2 x double> %div
 }
 
 define <3 x float> @constrained_vector_fdiv_v3f32(<3 x float> %x, <3 x float> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fdiv_v3f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 35
-; PC64LE-NEXT:    xxsldwi 1, 35, 35, 3
+; PC64LE-NEXT:    xxswapd 0, 35 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxsldwi 1, 35, 35, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
-; PC64LE-NEXT:    xxsldwi 2, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 3, 34
+; PC64LE-NEXT:    xxsldwi 2, 34, 34, 3 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 3, 34 # Vec Defs: VSL3(VSR3) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI2_0@toc@l
-; PC64LE-NEXT:    xxsldwi 4, 35, 35, 1
-; PC64LE-NEXT:    xxsldwi 5, 34, 34, 1
-; PC64LE-NEXT:    lvx 4, 0, 3
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    xscvspdpn 3, 3
-; PC64LE-NEXT:    xsdivsp 1, 2, 1
-; PC64LE-NEXT:    xscvspdpn 2, 4
-; PC64LE-NEXT:    xsdivsp 0, 3, 0
-; PC64LE-NEXT:    xscvspdpn 3, 5
-; PC64LE-NEXT:    xsdivsp 2, 3, 2
-; PC64LE-NEXT:    xscvdpspn 34, 1
-; PC64LE-NEXT:    xscvdpspn 35, 0
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    xscvdpspn 35, 2
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    xxsldwi 4, 35, 35, 1 # Vec Defs: VSL4(VSR4) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxsldwi 5, 34, 34, 1 # Vec Defs: VSL5(VSR5) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    xscvspdpn 3, 3 # Vec Defs: F3(VSR3) Vec Uses: VSL3(VSR3)
+; PC64LE-NEXT:    xsdivsp 1, 2, 1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 2, 4 # Vec Defs: F2(VSR2) Vec Uses: VSL4(VSR4)
+; PC64LE-NEXT:    xsdivsp 0, 3, 0 # Vec Defs: F0(VSR0) Vec Uses: F3(VSR3)F0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 3, 5 # Vec Defs: F3(VSR3) Vec Uses: VSL5(VSR5)
+; PC64LE-NEXT:    xsdivsp 2, 3, 2 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)F2(VSR2)
+; PC64LE-NEXT:    xscvdpspn 34, 1 # Vec Defs: V2(VSR34) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xscvdpspn 35, 2 # Vec Defs: V3(VSR35) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fdiv_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 35, 35, 1
-; PC64LE9-NEXT:    xxsldwi 1, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 35, 35, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI2_0@toc@l
-; PC64LE9-NEXT:    xxswapd 2, 34
-; PC64LE9-NEXT:    xxsldwi 3, 34, 34, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvspdpn 1, 1
-; PC64LE9-NEXT:    xscvspdpn 2, 2
-; PC64LE9-NEXT:    xscvspdpn 3, 3
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    xsdivsp 0, 1, 0
-; PC64LE9-NEXT:    xxswapd 1, 35
-; PC64LE9-NEXT:    xscvspdpn 1, 1
-; PC64LE9-NEXT:    xsdivsp 1, 2, 1
-; PC64LE9-NEXT:    xxsldwi 2, 35, 35, 3
-; PC64LE9-NEXT:    xscvspdpn 2, 2
-; PC64LE9-NEXT:    xsdivsp 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 1
-; PC64LE9-NEXT:    xscvdpspn 34, 2
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    xxswapd 2, 34 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xxsldwi 3, 34, 34, 3 # Vec Defs: VSL3(VSR3) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE9-NEXT:    xscvspdpn 3, 3 # Vec Defs: F3(VSR3) Vec Uses: VSL3(VSR3)
+; PC64LE9-NEXT:    lxv 36, 0(3) # Vec Defs: V4(VSR36)
+; PC64LE9-NEXT:    xsdivsp 0, 1, 0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 1, 35 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE9-NEXT:    xsdivsp 1, 2, 1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PC64LE9-NEXT:    xxsldwi 2, 35, 35, 3 # Vec Defs: VSL2(VSR2) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE9-NEXT:    xsdivsp 2, 3, 2 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)F2(VSR2)
+; PC64LE9-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 34, 2 # Vec Defs: V2(VSR34) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE9-NEXT:    blr
 entry:
   %div = call <3 x float> @llvm.experimental.constrained.fdiv.v3f32(
            <3 x float> %x,
            <3 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x float> %div
 }
 
 define <3 x double> @constrained_vector_fdiv_v3f64(<3 x double> %x, <3 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fdiv_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
 ; PC64LE-NEXT:    # kill: def $f5 killed $f5 def $vsl5
 ; PC64LE-NEXT:    # kill: def $f4 killed $f4 def $vsl4
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 def $vsl2
-; PC64LE-NEXT:    xxmrghd 0, 5, 4
-; PC64LE-NEXT:    xsdivdp 3, 3, 6
-; PC64LE-NEXT:    xxmrghd 1, 2, 1
-; PC64LE-NEXT:    xvdivdp 2, 1, 0
-; PC64LE-NEXT:    xxswapd 1, 2
+; PC64LE-NEXT:    xxmrghd 0, 5, 4 # Vec Defs: VSL0(VSR0) Vec Uses: VSL5(VSR5)VSL4(VSR4)
+; PC64LE-NEXT:    xsdivdp 3, 3, 6 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)F6(VSR6)
+; PC64LE-NEXT:    xxmrghd 1, 2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE-NEXT:    xvdivdp 2, 1, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fdiv_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    # kill: def $f5 killed $f5 def $vsl5
 ; PC64LE9-NEXT:    # kill: def $f4 killed $f4 def $vsl4
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 0, 5, 4
-; PC64LE9-NEXT:    xxmrghd 1, 2, 1
-; PC64LE9-NEXT:    xsdivdp 3, 3, 6
-; PC64LE9-NEXT:    xvdivdp 2, 1, 0
-; PC64LE9-NEXT:    xxswapd 1, 2
+; PC64LE9-NEXT:    xxmrghd 0, 5, 4 # Vec Defs: VSL0(VSR0) Vec Uses: VSL5(VSR5)VSL4(VSR4)
+; PC64LE9-NEXT:    xxmrghd 1, 2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE9-NEXT:    xsdivdp 3, 3, 6 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)F6(VSR6)
+; PC64LE9-NEXT:    xvdivdp 2, 1, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE9-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    blr
 entry:
   %div = call <3 x double> @llvm.experimental.constrained.fdiv.v3f64(
            <3 x double> %x,
            <3 x double> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x double> %div
 }
 
 define <4 x double> @constrained_vector_fdiv_v4f64(<4 x double> %x, <4 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fdiv_v4f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvdivdp 35, 35, 37
-; PC64LE-NEXT:    xvdivdp 34, 34, 36
+; PC64LE-NEXT:    xvdivdp 35, 35, 37 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V5(VSR37)
+; PC64LE-NEXT:    xvdivdp 34, 34, 36 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fdiv_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvdivdp 35, 35, 37
-; PC64LE9-NEXT:    xvdivdp 34, 34, 36
+; PC64LE9-NEXT:    xvdivdp 35, 35, 37 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V5(VSR37)
+; PC64LE9-NEXT:    xvdivdp 34, 34, 36 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
 ; PC64LE9-NEXT:    blr
 entry:
   %div = call <4 x double> @llvm.experimental.constrained.fdiv.v4f64(
            <4 x double> %x,
            <4 x double> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <4 x double> %div

 define <2 x double> @constrained_vector_frem_v2f64(<2 x double> %x, <2 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_frem_v2f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 61, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 80
-; PC64LE-NEXT:    vmr 30, 2
+; PC64LE-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 3
-; PC64LE-NEXT:    xxlor 1, 62, 62
-; PC64LE-NEXT:    xxlor 2, 63, 63
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxlor 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl fmod
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 62
-; PC64LE-NEXT:    xxswapd 2, 63
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE-NEXT:    xxswapd 2, 63 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    bl fmod
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 80
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 34, 61, 1
+; PC64LE-NEXT:    xxmrghd 34, 61, 1 # Vec Defs: V2(VSR34) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 61, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_frem_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
 ; PC64LE9-NEXT:    stxv 62, 48(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE9-NEXT:    stxv 63, 64(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 3
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
-; PC64LE9-NEXT:    vmr 30, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 62, 62
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
+; PC64LE9-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE9-NEXT:    stxv 61, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE9-NEXT:    bl fmod
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 62
-; PC64LE9-NEXT:    xxswapd 2, 63
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE9-NEXT:    xxswapd 2, 63 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    bl fmod
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 34, 61, 1
+; PC64LE9-NEXT:    xxmrghd 34, 61, 1 # Vec Defs: V2(VSR34) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; PC64LE9-NEXT:    lxv 63, 64(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lxv 61, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %rem = call <2 x double> @llvm.experimental.constrained.frem.v2f64(
            <2 x double> %x,
            <2 x double> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <2 x double> %rem
 }
 
 define <3 x float> @constrained_vector_frem_v3f32(<3 x float> %x, <3 x float> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_frem_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE-NEXT:    xxsldwi 2, 35, 35, 1
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 2, 35, 35, 1 # Vec Defs: VSL2(VSR2) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stfd 30, 80(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 88(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    xscvspdpn 1, 0
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    vmr 31, 3
-; PC64LE-NEXT:    vmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    bl fmodf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 62
-; PC64LE-NEXT:    xxswapd 2, 63
-; PC64LE-NEXT:    fmr 31, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
-; PC64LE-NEXT:    xscvspdpn 2, 2
+; PC64LE-NEXT:    xxswapd 0, 62 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE-NEXT:    xxswapd 2, 63 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
 ; PC64LE-NEXT:    bl fmodf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxsldwi 0, 62, 62, 3
-; PC64LE-NEXT:    xxsldwi 2, 63, 63, 3
-; PC64LE-NEXT:    fmr 30, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
-; PC64LE-NEXT:    xscvspdpn 2, 2
+; PC64LE-NEXT:    xxsldwi 0, 62, 62, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE-NEXT:    xxsldwi 2, 63, 63, 3 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
 ; PC64LE-NEXT:    bl fmodf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xscvdpspn 34, 30
+; PC64LE-NEXT:    xscvdpspn 34, 30 # Vec Defs: V2(VSR34) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
 ; PC64LE-NEXT:    lfd 30, 80(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    xscvdpspn 35, 1
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI7_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    vmrghw 2, 2, 3
-; PC64LE-NEXT:    xscvdpspn 35, 31
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 88(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_frem_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 62, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    xxsldwi 0, 35, 35, 1
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxsldwi 0, 35, 35, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xscvspdpn 2, 0
-; PC64LE9-NEXT:    vmr 31, 3
-; PC64LE9-NEXT:    vmr 30, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 2, 0 # Vec Defs: F2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    bl fmodf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxswapd 0, 62
-; PC64LE9-NEXT:    fmr 31, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    xxswapd 0, 63
-; PC64LE9-NEXT:    xscvspdpn 2, 0
+; PC64LE9-NEXT:    xxswapd 0, 62 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE9-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 2, 0 # Vec Defs: F2(VSR2) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl fmodf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxsldwi 0, 62, 62, 3
-; PC64LE9-NEXT:    fmr 30, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE9-NEXT:    xscvspdpn 2, 0
+; PC64LE9-NEXT:    xxsldwi 0, 62, 62, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE9-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 2, 0 # Vec Defs: F2(VSR2) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl fmodf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscvdpspn 34, 1
-; PC64LE9-NEXT:    xscvdpspn 35, 30
+; PC64LE9-NEXT:    xscvdpspn 34, 1 # Vec Defs: V2(VSR34) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 35, 30 # Vec Defs: V3(VSR35) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI7_0@toc@l
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 31
+; PC64LE9-NEXT:    lxv 36, 0(3) # Vec Defs: V4(VSR36)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE9-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %rem = call <3 x float> @llvm.experimental.constrained.frem.v3f32(
            <3 x float> %x,
            <3 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x float> %rem
 }
 
 define <3 x double> @constrained_vector_frem_v3f64(<3 x double> %x, <3 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_frem_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
 ; PC64LE-NEXT:    stfd 28, 64(1) # 8-byte Folded Spill
-; PC64LE-NEXT:    fmr 28, 2
+; PC64LE-NEXT:    # Vec Uses: F28(VSR28)
+; PC64LE-NEXT:    fmr 28, 2 # Vec Defs: F28(VSR28) Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    fmr 2, 4
+; PC64LE-NEXT:    fmr 2, 4 # Vec Defs: F2(VSR2) Vec Uses: F4(VSR4)
 ; PC64LE-NEXT:    stfd 29, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F29(VSR29)
 ; PC64LE-NEXT:    stfd 30, 80(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 88(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    fmr 31, 6
-; PC64LE-NEXT:    fmr 30, 5
-; PC64LE-NEXT:    fmr 29, 3
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 6 # Vec Defs: F31(VSR31) Vec Uses: F6(VSR6)
+; PC64LE-NEXT:    fmr 30, 5 # Vec Defs: F30(VSR30) Vec Uses: F5(VSR5)
+; PC64LE-NEXT:    fmr 29, 3 # Vec Defs: F29(VSR29) Vec Uses: F3(VSR3)
 ; PC64LE-NEXT:    bl fmod
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 63, 1, 1
-; PC64LE-NEXT:    fmr 1, 28
-; PC64LE-NEXT:    fmr 2, 30
+; PC64LE-NEXT:    xxlor 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 28 # Vec Defs: F1(VSR1) Vec Uses: F28(VSR28)
+; PC64LE-NEXT:    fmr 2, 30 # Vec Defs: F2(VSR2) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    bl fmod
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 63, 1, 63
-; PC64LE-NEXT:    fmr 2, 31
-; PC64LE-NEXT:    fmr 1, 29
+; PC64LE-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE-NEXT:    fmr 2, 31 # Vec Defs: F2(VSR2) Vec Uses: F31(VSR31)
+; PC64LE-NEXT:    fmr 1, 29 # Vec Defs: F1(VSR1) Vec Uses: F29(VSR29)
 ; PC64LE-NEXT:    bl fmod
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    xxlor 2, 63, 63
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 88(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE-NEXT:    lfd 30, 80(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    lfd 29, 72(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    fmr 3, 1
+; PC64LE-NEXT:    # Vec Defs: F29(VSR29)
+; PC64LE-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    lfd 28, 64(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    fmr 1, 0
+; PC64LE-NEXT:    # Vec Defs: F28(VSR28)
+; PC64LE-NEXT:    fmr 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_frem_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
 ; PC64LE9-NEXT:    stfd 28, 48(1) # 8-byte Folded Spill
-; PC64LE9-NEXT:    fmr 28, 2
+; PC64LE9-NEXT:    # Vec Uses: F28(VSR28)
+; PC64LE9-NEXT:    fmr 28, 2 # Vec Defs: F28(VSR28) Vec Uses: F2(VSR2)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    fmr 2, 4
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    fmr 2, 4 # Vec Defs: F2(VSR2) Vec Uses: F4(VSR4)
 ; PC64LE9-NEXT:    stfd 29, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F29(VSR29)
 ; PC64LE9-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
-; PC64LE9-NEXT:    fmr 31, 6
-; PC64LE9-NEXT:    fmr 30, 5
-; PC64LE9-NEXT:    fmr 29, 3
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
+; PC64LE9-NEXT:    fmr 31, 6 # Vec Defs: F31(VSR31) Vec Uses: F6(VSR6)
+; PC64LE9-NEXT:    fmr 30, 5 # Vec Defs: F30(VSR30) Vec Uses: F5(VSR5)
+; PC64LE9-NEXT:    fmr 29, 3 # Vec Defs: F29(VSR29) Vec Uses: F3(VSR3)
 ; PC64LE9-NEXT:    bl fmod
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 63, 1, 1
-; PC64LE9-NEXT:    fmr 1, 28
-; PC64LE9-NEXT:    fmr 2, 30
+; PC64LE9-NEXT:    xscpsgndp 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    fmr 1, 28 # Vec Defs: F1(VSR1) Vec Uses: F28(VSR28)
+; PC64LE9-NEXT:    fmr 2, 30 # Vec Defs: F2(VSR2) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    bl fmod
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 1, 63
-; PC64LE9-NEXT:    fmr 1, 29
-; PC64LE9-NEXT:    fmr 2, 31
+; PC64LE9-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE9-NEXT:    fmr 1, 29 # Vec Defs: F1(VSR1) Vec Uses: F29(VSR29)
+; PC64LE9-NEXT:    fmr 2, 31 # Vec Defs: F2(VSR2) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    bl fmod
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
+; PC64LE9-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    lfd 29, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F29(VSR29)
 ; PC64LE9-NEXT:    lfd 28, 48(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F28(VSR28)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %rem = call <3 x double> @llvm.experimental.constrained.frem.v3f64(
            <3 x double> %x,
            <3 x double> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x double> %rem
 }
 
 define <4 x double> @constrained_vector_frem_v4f64(<4 x double> %x, <4 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_frem_v4f64:
 ; PC64LE:       # %bb.0:
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -128(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 59, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V27(VSR59)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 60, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V28(VSR60)
 ; PC64LE-NEXT:    li 3, 80
-; PC64LE-NEXT:    vmr 28, 2
+; PC64LE-NEXT:    vmr 28, 2 # Vec Defs: V28(VSR60) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    stxvd2x 61, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE-NEXT:    li 3, 96
-; PC64LE-NEXT:    vmr 29, 3
+; PC64LE-NEXT:    vmr 29, 3 # Vec Defs: V29(VSR61) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 30, 4
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE-NEXT:    vmr 30, 4 # Vec Defs: V30(VSR62) Vec Uses: V4(VSR36)V4(VSR36)
 ; PC64LE-NEXT:    li 3, 112
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 5
-; PC64LE-NEXT:    xxlor 1, 60, 60
-; PC64LE-NEXT:    xxlor 2, 62, 62
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 5 # Vec Defs: V31(VSR63) Vec Uses: V5(VSR37)V5(VSR37)
+; PC64LE-NEXT:    xxlor 1, 60, 60 # Vec Defs: F1(VSR1) Vec Uses: VF28(VSR28)VF28(VSR28)
+; PC64LE-NEXT:    xxlor 2, 62, 62 # Vec Defs: F2(VSR2) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE-NEXT:    bl fmod
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 59, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 60
-; PC64LE-NEXT:    xxswapd 2, 62
+; PC64LE-NEXT:    xxlor 59, 1, 1 # Vec Defs: VF27(VSR27) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 60 # Vec Defs: VSL1(VSR1) Vec Uses: V28(VSR60)V28(VSR60)
+; PC64LE-NEXT:    xxswapd 2, 62 # Vec Defs: VSL2(VSR2) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    bl fmod
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 62, 59, 1
-; PC64LE-NEXT:    xxlor 2, 63, 63
-; PC64LE-NEXT:    xxlor 1, 61, 61
+; PC64LE-NEXT:    xxmrghd 62, 59, 1 # Vec Defs: V30(VSR62) Vec Uses: V27(VSR59)VSL1(VSR1)
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
+; PC64LE-NEXT:    xxlor 1, 61, 61 # Vec Defs: F1(VSR1) Vec Uses: VF29(VSR29)VF29(VSR29)
 ; PC64LE-NEXT:    bl fmod
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 60, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 61
-; PC64LE-NEXT:    xxswapd 2, 63
+; PC64LE-NEXT:    xxlor 60, 1, 1 # Vec Defs: VF28(VSR28) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 61 # Vec Defs: VSL1(VSR1) Vec Uses: V29(VSR61)V29(VSR61)
+; PC64LE-NEXT:    xxswapd 2, 63 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    bl fmod
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 112
-; PC64LE-NEXT:    vmr 2, 30
+; PC64LE-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 35, 60, 1
+; PC64LE-NEXT:    xxmrghd 35, 60, 1 # Vec Defs: V3(VSR35) Vec Uses: V28(VSR60)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 96
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 80
 ; PC64LE-NEXT:    lxvd2x 61, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 60, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V28(VSR60)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 59, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V27(VSR59)
 ; PC64LE-NEXT:    addi 1, 1, 128
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_frem_v4f64:
 ; PC64LE9:       # %bb.0:
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -112(1)
 ; PC64LE9-NEXT:    stxv 60, 48(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V28(VSR60)
 ; PC64LE9-NEXT:    stxv 62, 80(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 30, 4
-; PC64LE9-NEXT:    xscpsgndp 2, 62, 62
-; PC64LE9-NEXT:    vmr 28, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 60, 60
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE9-NEXT:    vmr 30, 4 # Vec Defs: V30(VSR62) Vec Uses: V4(VSR36)V4(VSR36)
+; PC64LE9-NEXT:    xscpsgndp 2, 62, 62 # Vec Defs: F2(VSR2) Vec Uses: VF30(VSR30)VF30(VSR30)
+; PC64LE9-NEXT:    vmr 28, 2 # Vec Defs: V28(VSR60) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 60, 60 # Vec Defs: F1(VSR1) Vec Uses: VF28(VSR28)VF28(VSR28)
 ; PC64LE9-NEXT:    stxv 59, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V27(VSR59)
 ; PC64LE9-NEXT:    stxv 61, 64(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE9-NEXT:    stxv 63, 96(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 5
-; PC64LE9-NEXT:    vmr 29, 3
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 5 # Vec Defs: V31(VSR63) Vec Uses: V5(VSR37)V5(VSR37)
+; PC64LE9-NEXT:    vmr 29, 3 # Vec Defs: V29(VSR61) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE9-NEXT:    bl fmod
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 59, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 60
-; PC64LE9-NEXT:    xxswapd 2, 62
+; PC64LE9-NEXT:    xscpsgndp 59, 1, 1 # Vec Defs: VF27(VSR27) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 60 # Vec Defs: VSL1(VSR1) Vec Uses: V28(VSR60)V28(VSR60)
+; PC64LE9-NEXT:    xxswapd 2, 62 # Vec Defs: VSL2(VSR2) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    bl fmod
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 62, 59, 1
-; PC64LE9-NEXT:    xscpsgndp 1, 61, 61
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
+; PC64LE9-NEXT:    xxmrghd 62, 59, 1 # Vec Defs: V30(VSR62) Vec Uses: V27(VSR59)VSL1(VSR1)
+; PC64LE9-NEXT:    xscpsgndp 1, 61, 61 # Vec Defs: F1(VSR1) Vec Uses: VF29(VSR29)VF29(VSR29)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    bl fmod
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 60, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 61
-; PC64LE9-NEXT:    xxswapd 2, 63
+; PC64LE9-NEXT:    xscpsgndp 60, 1, 1 # Vec Defs: VF28(VSR28) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 61 # Vec Defs: VSL1(VSR1) Vec Uses: V29(VSR61)V29(VSR61)
+; PC64LE9-NEXT:    xxswapd 2, 63 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    bl fmod
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 35, 60, 1
-; PC64LE9-NEXT:    vmr 2, 30
+; PC64LE9-NEXT:    xxmrghd 35, 60, 1 # Vec Defs: V3(VSR35) Vec Uses: V28(VSR60)VSL1(VSR1)
+; PC64LE9-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    lxv 63, 96(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 80(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lxv 61, 64(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE9-NEXT:    lxv 60, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V28(VSR60)
 ; PC64LE9-NEXT:    lxv 59, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V27(VSR59)
 ; PC64LE9-NEXT:    addi 1, 1, 112
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
   %rem = call <4 x double> @llvm.experimental.constrained.frem.v4f64(
            <4 x double> %x,
            <4 x double> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <4 x double> %rem
 }
 
 define <1 x float> @constrained_vector_fmul_v1f32(<1 x float> %x, <1 x float> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fmul_v1f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xsmulsp 1, 1, 2
+; PC64LE-NEXT:    xsmulsp 1, 1, 2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fmul_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xsmulsp 1, 1, 2
+; PC64LE9-NEXT:    xsmulsp 1, 1, 2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; PC64LE9-NEXT:    blr
 entry:
   %mul = call <1 x float> @llvm.experimental.constrained.fmul.v1f32(
            <1 x float> %x,
            <1 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <1 x float> %mul
 }
 
 define <2 x double> @constrained_vector_fmul_v2f64(<2 x double> %x, <2 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fmul_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvmuldp 34, 34, 35
+; PC64LE-NEXT:    xvmuldp 34, 34, 35 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fmul_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvmuldp 34, 34, 35
+; PC64LE9-NEXT:    xvmuldp 34, 34, 35 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %mul = call <2 x double> @llvm.experimental.constrained.fmul.v2f64(
            <2 x double> %x,
            <2 x double> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <2 x double> %mul
 }
 
 define <3 x float> @constrained_vector_fmul_v3f32(<3 x float> %x, <3 x float> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fmul_v3f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 35, 35, 3
-; PC64LE-NEXT:    xxsldwi 1, 34, 34, 3
+; PC64LE-NEXT:    xxsldwi 0, 35, 35, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxsldwi 1, 34, 34, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
-; PC64LE-NEXT:    xxswapd 2, 35
-; PC64LE-NEXT:    xxswapd 3, 34
+; PC64LE-NEXT:    xxswapd 2, 35 # Vec Defs: VSL2(VSR2) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxswapd 3, 34 # Vec Defs: VSL3(VSR3) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI12_0@toc@l
-; PC64LE-NEXT:    xxsldwi 4, 35, 35, 1
-; PC64LE-NEXT:    lvx 4, 0, 3
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    xscvspdpn 3, 3
-; PC64LE-NEXT:    xscvspdpn 4, 4
-; PC64LE-NEXT:    xsmulsp 0, 1, 0
-; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1
-; PC64LE-NEXT:    xsmulsp 2, 3, 2
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    xscvdpspn 35, 2
-; PC64LE-NEXT:    xsmulsp 0, 1, 4
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    xscvdpspn 35, 0
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    xxsldwi 4, 35, 35, 1 # Vec Defs: VSL4(VSR4) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    xscvspdpn 3, 3 # Vec Defs: F3(VSR3) Vec Uses: VSL3(VSR3)
+; PC64LE-NEXT:    xscvspdpn 4, 4 # Vec Defs: F4(VSR4) Vec Uses: VSL4(VSR4)
+; PC64LE-NEXT:    xsmulsp 0, 1, 0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xsmulsp 2, 3, 2 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)F2(VSR2)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 35, 2 # Vec Defs: V3(VSR35) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xsmulsp 0, 1, 4 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F4(VSR4)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fmul_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 35, 35, 1
-; PC64LE9-NEXT:    xxsldwi 1, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 35, 35, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI12_0@toc@l
-; PC64LE9-NEXT:    xxswapd 2, 34
-; PC64LE9-NEXT:    xxsldwi 3, 34, 34, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvspdpn 1, 1
-; PC64LE9-NEXT:    xscvspdpn 2, 2
-; PC64LE9-NEXT:    xscvspdpn 3, 3
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    xsmulsp 0, 1, 0
-; PC64LE9-NEXT:    xxswapd 1, 35
-; PC64LE9-NEXT:    xscvspdpn 1, 1
-; PC64LE9-NEXT:    xsmulsp 1, 2, 1
-; PC64LE9-NEXT:    xxsldwi 2, 35, 35, 3
-; PC64LE9-NEXT:    xscvspdpn 2, 2
-; PC64LE9-NEXT:    xsmulsp 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 1
-; PC64LE9-NEXT:    xscvdpspn 34, 2
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    xxswapd 2, 34 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xxsldwi 3, 34, 34, 3 # Vec Defs: VSL3(VSR3) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE9-NEXT:    xscvspdpn 3, 3 # Vec Defs: F3(VSR3) Vec Uses: VSL3(VSR3)
+; PC64LE9-NEXT:    lxv 36, 0(3) # Vec Defs: V4(VSR36)
+; PC64LE9-NEXT:    xsmulsp 0, 1, 0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 1, 35 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE9-NEXT:    xsmulsp 1, 2, 1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PC64LE9-NEXT:    xxsldwi 2, 35, 35, 3 # Vec Defs: VSL2(VSR2) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE9-NEXT:    xsmulsp 2, 3, 2 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)F2(VSR2)
+; PC64LE9-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 34, 2 # Vec Defs: V2(VSR34) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE9-NEXT:    blr
 entry:
   %mul = call <3 x float> @llvm.experimental.constrained.fmul.v3f32(
            <3 x float> %x,
            <3 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x float> %mul
 }
 
 define <3 x double> @constrained_vector_fmul_v3f64(<3 x double> %x, <3 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fmul_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
 ; PC64LE-NEXT:    # kill: def $f5 killed $f5 def $vsl5
 ; PC64LE-NEXT:    # kill: def $f4 killed $f4 def $vsl4
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 def $vsl2
-; PC64LE-NEXT:    xxmrghd 0, 5, 4
-; PC64LE-NEXT:    xsmuldp 3, 3, 6
-; PC64LE-NEXT:    xxmrghd 1, 2, 1
-; PC64LE-NEXT:    xvmuldp 2, 1, 0
-; PC64LE-NEXT:    xxswapd 1, 2
+; PC64LE-NEXT:    xxmrghd 0, 5, 4 # Vec Defs: VSL0(VSR0) Vec Uses: VSL5(VSR5)VSL4(VSR4)
+; PC64LE-NEXT:    xsmuldp 3, 3, 6 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)F6(VSR6)
+; PC64LE-NEXT:    xxmrghd 1, 2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE-NEXT:    xvmuldp 2, 1, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fmul_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    # kill: def $f5 killed $f5 def $vsl5
 ; PC64LE9-NEXT:    # kill: def $f4 killed $f4 def $vsl4
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 0, 5, 4
-; PC64LE9-NEXT:    xxmrghd 1, 2, 1
-; PC64LE9-NEXT:    xsmuldp 3, 3, 6
-; PC64LE9-NEXT:    xvmuldp 2, 1, 0
-; PC64LE9-NEXT:    xxswapd 1, 2
+; PC64LE9-NEXT:    xxmrghd 0, 5, 4 # Vec Defs: VSL0(VSR0) Vec Uses: VSL5(VSR5)VSL4(VSR4)
+; PC64LE9-NEXT:    xxmrghd 1, 2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE9-NEXT:    xsmuldp 3, 3, 6 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)F6(VSR6)
+; PC64LE9-NEXT:    xvmuldp 2, 1, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE9-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    blr
 entry:
   %mul = call <3 x double> @llvm.experimental.constrained.fmul.v3f64(
            <3 x double> %x,
            <3 x double> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x double> %mul
 }
 
 define <4 x double> @constrained_vector_fmul_v4f64(<4 x double> %x, <4 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fmul_v4f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvmuldp 35, 35, 37
-; PC64LE-NEXT:    xvmuldp 34, 34, 36
+; PC64LE-NEXT:    xvmuldp 35, 35, 37 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V5(VSR37)
+; PC64LE-NEXT:    xvmuldp 34, 34, 36 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fmul_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvmuldp 35, 35, 37
-; PC64LE9-NEXT:    xvmuldp 34, 34, 36
+; PC64LE9-NEXT:    xvmuldp 35, 35, 37 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V5(VSR37)
+; PC64LE9-NEXT:    xvmuldp 34, 34, 36 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
 ; PC64LE9-NEXT:    blr
 entry:
   %mul = call <4 x double> @llvm.experimental.constrained.fmul.v4f64(
            <4 x double> %x,
            <4 x double> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <4 x double> %mul
 }
 
 define <1 x float> @constrained_vector_fadd_v1f32(<1 x float> %x, <1 x float> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fadd_v1f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xsaddsp 1, 1, 2
+; PC64LE-NEXT:    xsaddsp 1, 1, 2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fadd_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xsaddsp 1, 1, 2
+; PC64LE9-NEXT:    xsaddsp 1, 1, 2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; PC64LE9-NEXT:    blr
 entry:
   %add = call <1 x float> @llvm.experimental.constrained.fadd.v1f32(
            <1 x float> %x,
            <1 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <1 x float> %add
 }
 
 define <2 x double> @constrained_vector_fadd_v2f64(<2 x double> %x, <2 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fadd_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvadddp 34, 34, 35
+; PC64LE-NEXT:    xvadddp 34, 34, 35 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fadd_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvadddp 34, 34, 35
+; PC64LE9-NEXT:    xvadddp 34, 34, 35 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %add = call <2 x double> @llvm.experimental.constrained.fadd.v2f64(
            <2 x double> %x,
            <2 x double> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <2 x double> %add
 }
 
 define <3 x float> @constrained_vector_fadd_v3f32(<3 x float> %x, <3 x float> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fadd_v3f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 35, 35, 3
-; PC64LE-NEXT:    xxsldwi 1, 34, 34, 3
+; PC64LE-NEXT:    xxsldwi 0, 35, 35, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxsldwi 1, 34, 34, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI17_0@toc@ha
-; PC64LE-NEXT:    xxswapd 2, 35
-; PC64LE-NEXT:    xxswapd 3, 34
+; PC64LE-NEXT:    xxswapd 2, 35 # Vec Defs: VSL2(VSR2) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxswapd 3, 34 # Vec Defs: VSL3(VSR3) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI17_0@toc@l
-; PC64LE-NEXT:    xxsldwi 4, 35, 35, 1
-; PC64LE-NEXT:    lvx 4, 0, 3
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    xscvspdpn 3, 3
-; PC64LE-NEXT:    xscvspdpn 4, 4
-; PC64LE-NEXT:    xsaddsp 0, 1, 0
-; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1
-; PC64LE-NEXT:    xsaddsp 2, 3, 2
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    xscvdpspn 35, 2
-; PC64LE-NEXT:    xsaddsp 0, 1, 4
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    xscvdpspn 35, 0
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    xxsldwi 4, 35, 35, 1 # Vec Defs: VSL4(VSR4) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    xscvspdpn 3, 3 # Vec Defs: F3(VSR3) Vec Uses: VSL3(VSR3)
+; PC64LE-NEXT:    xscvspdpn 4, 4 # Vec Defs: F4(VSR4) Vec Uses: VSL4(VSR4)
+; PC64LE-NEXT:    xsaddsp 0, 1, 0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xsaddsp 2, 3, 2 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)F2(VSR2)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 35, 2 # Vec Defs: V3(VSR35) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xsaddsp 0, 1, 4 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F4(VSR4)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fadd_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 35, 35, 1
-; PC64LE9-NEXT:    xxsldwi 1, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 35, 35, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI17_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI17_0@toc@l
-; PC64LE9-NEXT:    xxswapd 2, 34
-; PC64LE9-NEXT:    xxsldwi 3, 34, 34, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvspdpn 1, 1
-; PC64LE9-NEXT:    xscvspdpn 2, 2
-; PC64LE9-NEXT:    xscvspdpn 3, 3
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    xsaddsp 0, 1, 0
-; PC64LE9-NEXT:    xxswapd 1, 35
-; PC64LE9-NEXT:    xscvspdpn 1, 1
-; PC64LE9-NEXT:    xsaddsp 1, 2, 1
-; PC64LE9-NEXT:    xxsldwi 2, 35, 35, 3
-; PC64LE9-NEXT:    xscvspdpn 2, 2
-; PC64LE9-NEXT:    xsaddsp 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 1
-; PC64LE9-NEXT:    xscvdpspn 34, 2
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    xxswapd 2, 34 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xxsldwi 3, 34, 34, 3 # Vec Defs: VSL3(VSR3) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE9-NEXT:    xscvspdpn 3, 3 # Vec Defs: F3(VSR3) Vec Uses: VSL3(VSR3)
+; PC64LE9-NEXT:    lxv 36, 0(3) # Vec Defs: V4(VSR36)
+; PC64LE9-NEXT:    xsaddsp 0, 1, 0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 1, 35 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE9-NEXT:    xsaddsp 1, 2, 1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PC64LE9-NEXT:    xxsldwi 2, 35, 35, 3 # Vec Defs: VSL2(VSR2) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE9-NEXT:    xsaddsp 2, 3, 2 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)F2(VSR2)
+; PC64LE9-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 34, 2 # Vec Defs: V2(VSR34) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE9-NEXT:    blr
 entry:
   %add = call <3 x float> @llvm.experimental.constrained.fadd.v3f32(
            <3 x float> %x,
            <3 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x float> %add
 }
 
 define <3 x double> @constrained_vector_fadd_v3f64(<3 x double> %x, <3 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fadd_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
 ; PC64LE-NEXT:    # kill: def $f5 killed $f5 def $vsl5
 ; PC64LE-NEXT:    # kill: def $f4 killed $f4 def $vsl4
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 def $vsl2
-; PC64LE-NEXT:    xxmrghd 0, 5, 4
-; PC64LE-NEXT:    xsadddp 3, 3, 6
-; PC64LE-NEXT:    xxmrghd 1, 2, 1
-; PC64LE-NEXT:    xvadddp 2, 1, 0
-; PC64LE-NEXT:    xxswapd 1, 2
+; PC64LE-NEXT:    xxmrghd 0, 5, 4 # Vec Defs: VSL0(VSR0) Vec Uses: VSL5(VSR5)VSL4(VSR4)
+; PC64LE-NEXT:    xsadddp 3, 3, 6 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)F6(VSR6)
+; PC64LE-NEXT:    xxmrghd 1, 2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE-NEXT:    xvadddp 2, 1, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fadd_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    # kill: def $f5 killed $f5 def $vsl5
 ; PC64LE9-NEXT:    # kill: def $f4 killed $f4 def $vsl4
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 0, 5, 4
-; PC64LE9-NEXT:    xxmrghd 1, 2, 1
-; PC64LE9-NEXT:    xsadddp 3, 3, 6
-; PC64LE9-NEXT:    xvadddp 2, 1, 0
-; PC64LE9-NEXT:    xxswapd 1, 2
+; PC64LE9-NEXT:    xxmrghd 0, 5, 4 # Vec Defs: VSL0(VSR0) Vec Uses: VSL5(VSR5)VSL4(VSR4)
+; PC64LE9-NEXT:    xxmrghd 1, 2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE9-NEXT:    xsadddp 3, 3, 6 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)F6(VSR6)
+; PC64LE9-NEXT:    xvadddp 2, 1, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE9-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    blr
 entry:
   %add = call <3 x double> @llvm.experimental.constrained.fadd.v3f64(
            <3 x double> %x,
            <3 x double> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x double> %add
 }
 
 define <4 x double> @constrained_vector_fadd_v4f64(<4 x double> %x, <4 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fadd_v4f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvadddp 35, 35, 37
-; PC64LE-NEXT:    xvadddp 34, 34, 36
+; PC64LE-NEXT:    xvadddp 35, 35, 37 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V5(VSR37)
+; PC64LE-NEXT:    xvadddp 34, 34, 36 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fadd_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvadddp 35, 35, 37
-; PC64LE9-NEXT:    xvadddp 34, 34, 36
+; PC64LE9-NEXT:    xvadddp 35, 35, 37 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V5(VSR37)
+; PC64LE9-NEXT:    xvadddp 34, 34, 36 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
 ; PC64LE9-NEXT:    blr
 entry:
   %add = call <4 x double> @llvm.experimental.constrained.fadd.v4f64(
            <4 x double> %x,
            <4 x double> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <4 x double> %add
 }
 
 define <1 x float> @constrained_vector_fsub_v1f32(<1 x float> %x, <1 x float> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fsub_v1f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xssubsp 1, 1, 2
+; PC64LE-NEXT:    xssubsp 1, 1, 2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fsub_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xssubsp 1, 1, 2
+; PC64LE9-NEXT:    xssubsp 1, 1, 2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; PC64LE9-NEXT:    blr
 entry:
   %sub = call <1 x float> @llvm.experimental.constrained.fsub.v1f32(
            <1 x float> %x,
            <1 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <1 x float> %sub
 }
 
 define <2 x double> @constrained_vector_fsub_v2f64(<2 x double> %x, <2 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fsub_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvsubdp 34, 34, 35
+; PC64LE-NEXT:    xvsubdp 34, 34, 35 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fsub_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvsubdp 34, 34, 35
+; PC64LE9-NEXT:    xvsubdp 34, 34, 35 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %sub = call <2 x double> @llvm.experimental.constrained.fsub.v2f64(
            <2 x double> %x,
            <2 x double> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <2 x double> %sub
 }
 
 define <3 x float> @constrained_vector_fsub_v3f32(<3 x float> %x, <3 x float> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fsub_v3f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 35, 35, 3
-; PC64LE-NEXT:    xxsldwi 1, 34, 34, 3
+; PC64LE-NEXT:    xxsldwi 0, 35, 35, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxsldwi 1, 34, 34, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI22_0@toc@ha
-; PC64LE-NEXT:    xxswapd 2, 35
-; PC64LE-NEXT:    xxswapd 3, 34
+; PC64LE-NEXT:    xxswapd 2, 35 # Vec Defs: VSL2(VSR2) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxswapd 3, 34 # Vec Defs: VSL3(VSR3) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI22_0@toc@l
-; PC64LE-NEXT:    xxsldwi 4, 35, 35, 1
-; PC64LE-NEXT:    lvx 4, 0, 3
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    xscvspdpn 3, 3
-; PC64LE-NEXT:    xscvspdpn 4, 4
-; PC64LE-NEXT:    xssubsp 0, 1, 0
-; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1
-; PC64LE-NEXT:    xssubsp 2, 3, 2
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    xscvdpspn 35, 2
-; PC64LE-NEXT:    xssubsp 0, 1, 4
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    xscvdpspn 35, 0
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    xxsldwi 4, 35, 35, 1 # Vec Defs: VSL4(VSR4) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    xscvspdpn 3, 3 # Vec Defs: F3(VSR3) Vec Uses: VSL3(VSR3)
+; PC64LE-NEXT:    xscvspdpn 4, 4 # Vec Defs: F4(VSR4) Vec Uses: VSL4(VSR4)
+; PC64LE-NEXT:    xssubsp 0, 1, 0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xssubsp 2, 3, 2 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)F2(VSR2)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 35, 2 # Vec Defs: V3(VSR35) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xssubsp 0, 1, 4 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F4(VSR4)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fsub_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 35, 35, 1
-; PC64LE9-NEXT:    xxsldwi 1, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 35, 35, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI22_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI22_0@toc@l
-; PC64LE9-NEXT:    xxswapd 2, 34
-; PC64LE9-NEXT:    xxsldwi 3, 34, 34, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvspdpn 1, 1
-; PC64LE9-NEXT:    xscvspdpn 2, 2
-; PC64LE9-NEXT:    xscvspdpn 3, 3
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    xssubsp 0, 1, 0
-; PC64LE9-NEXT:    xxswapd 1, 35
-; PC64LE9-NEXT:    xscvspdpn 1, 1
-; PC64LE9-NEXT:    xssubsp 1, 2, 1
-; PC64LE9-NEXT:    xxsldwi 2, 35, 35, 3
-; PC64LE9-NEXT:    xscvspdpn 2, 2
-; PC64LE9-NEXT:    xssubsp 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 1
-; PC64LE9-NEXT:    xscvdpspn 34, 2
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    xxswapd 2, 34 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xxsldwi 3, 34, 34, 3 # Vec Defs: VSL3(VSR3) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE9-NEXT:    xscvspdpn 3, 3 # Vec Defs: F3(VSR3) Vec Uses: VSL3(VSR3)
+; PC64LE9-NEXT:    lxv 36, 0(3) # Vec Defs: V4(VSR36)
+; PC64LE9-NEXT:    xssubsp 0, 1, 0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 1, 35 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE9-NEXT:    xssubsp 1, 2, 1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PC64LE9-NEXT:    xxsldwi 2, 35, 35, 3 # Vec Defs: VSL2(VSR2) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE9-NEXT:    xssubsp 2, 3, 2 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)F2(VSR2)
+; PC64LE9-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 34, 2 # Vec Defs: V2(VSR34) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE9-NEXT:    blr
 entry:
   %sub = call <3 x float> @llvm.experimental.constrained.fsub.v3f32(
            <3 x float> %x,
            <3 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x float> %sub
 }
 
 define <3 x double> @constrained_vector_fsub_v3f64(<3 x double> %x, <3 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fsub_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
 ; PC64LE-NEXT:    # kill: def $f5 killed $f5 def $vsl5
 ; PC64LE-NEXT:    # kill: def $f4 killed $f4 def $vsl4
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 def $vsl2
-; PC64LE-NEXT:    xxmrghd 0, 5, 4
-; PC64LE-NEXT:    xssubdp 3, 3, 6
-; PC64LE-NEXT:    xxmrghd 1, 2, 1
-; PC64LE-NEXT:    xvsubdp 2, 1, 0
-; PC64LE-NEXT:    xxswapd 1, 2
+; PC64LE-NEXT:    xxmrghd 0, 5, 4 # Vec Defs: VSL0(VSR0) Vec Uses: VSL5(VSR5)VSL4(VSR4)
+; PC64LE-NEXT:    xssubdp 3, 3, 6 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)F6(VSR6)
+; PC64LE-NEXT:    xxmrghd 1, 2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE-NEXT:    xvsubdp 2, 1, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fsub_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    # kill: def $f5 killed $f5 def $vsl5
 ; PC64LE9-NEXT:    # kill: def $f4 killed $f4 def $vsl4
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 0, 5, 4
-; PC64LE9-NEXT:    xxmrghd 1, 2, 1
-; PC64LE9-NEXT:    xssubdp 3, 3, 6
-; PC64LE9-NEXT:    xvsubdp 2, 1, 0
-; PC64LE9-NEXT:    xxswapd 1, 2
+; PC64LE9-NEXT:    xxmrghd 0, 5, 4 # Vec Defs: VSL0(VSR0) Vec Uses: VSL5(VSR5)VSL4(VSR4)
+; PC64LE9-NEXT:    xxmrghd 1, 2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE9-NEXT:    xssubdp 3, 3, 6 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)F6(VSR6)
+; PC64LE9-NEXT:    xvsubdp 2, 1, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE9-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    blr
 entry:
   %sub = call <3 x double> @llvm.experimental.constrained.fsub.v3f64(
            <3 x double> %x,
            <3 x double> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x double> %sub
 }
 
 define <4 x double> @constrained_vector_fsub_v4f64(<4 x double> %x, <4 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_fsub_v4f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvsubdp 35, 35, 37
-; PC64LE-NEXT:    xvsubdp 34, 34, 36
+; PC64LE-NEXT:    xvsubdp 35, 35, 37 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V5(VSR37)
+; PC64LE-NEXT:    xvsubdp 34, 34, 36 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fsub_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvsubdp 35, 35, 37
-; PC64LE9-NEXT:    xvsubdp 34, 34, 36
+; PC64LE9-NEXT:    xvsubdp 35, 35, 37 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V5(VSR37)
+; PC64LE9-NEXT:    xvsubdp 34, 34, 36 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
 ; PC64LE9-NEXT:    blr
 entry:
   %sub = call <4 x double> @llvm.experimental.constrained.fsub.v4f64(
            <4 x double> %x,
            <4 x double> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <4 x double> %sub
 }
 
 define <1 x float> @constrained_vector_sqrt_v1f32(<1 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sqrt_v1f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xssqrtsp 1, 1
+; PC64LE-NEXT:    xssqrtsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sqrt_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xssqrtsp 1, 1
+; PC64LE9-NEXT:    xssqrtsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64LE9-NEXT:    blr
 entry:
   %sqrt = call <1 x float> @llvm.experimental.constrained.sqrt.v1f32(
                               <1 x float> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <1 x float> %sqrt
 }
 
 define <2 x double> @constrained_vector_sqrt_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sqrt_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvsqrtdp 34, 34
+; PC64LE-NEXT:    xvsqrtdp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sqrt_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvsqrtdp 34, 34
+; PC64LE9-NEXT:    xvsqrtdp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %sqrt = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64(
                               <2 x double> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <2 x double> %sqrt
 }
 
 define <3 x float> @constrained_vector_sqrt_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sqrt_v3f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 1, 34
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI27_0@toc@ha
-; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI27_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    xssqrtsp 0, 0
-; PC64LE-NEXT:    xssqrtsp 1, 1
-; PC64LE-NEXT:    xssqrtsp 2, 2
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    xscvdpspn 35, 1
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    xscvdpspn 35, 2
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    xssqrtsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xssqrtsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xssqrtsp 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xscvdpspn 35, 2 # Vec Defs: V3(VSR35) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sqrt_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxswapd 1, 34
-; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3
+; PC64LE9-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI27_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI27_0@toc@l
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 1
-; PC64LE9-NEXT:    xscvspdpn 2, 2
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xssqrtsp 1, 1
-; PC64LE9-NEXT:    xssqrtsp 2, 2
-; PC64LE9-NEXT:    xssqrtsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xssqrtsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xssqrtsp 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    xssqrtsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 34, 2 # Vec Defs: V2(VSR34) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 36, 0 # Vec Defs: V4(VSR36) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %sqrt = call <3 x float> @llvm.experimental.constrained.sqrt.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %sqrt
 }
 
 define <3 x double> @constrained_vector_sqrt_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sqrt_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 0, 2, 1
-; PC64LE-NEXT:    xssqrtdp 3, 3
-; PC64LE-NEXT:    xvsqrtdp 2, 0
-; PC64LE-NEXT:    xxswapd 1, 2
+; PC64LE-NEXT:    xxmrghd 0, 2, 1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE-NEXT:    xssqrtdp 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    xvsqrtdp 2, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sqrt_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 0, 2, 1
-; PC64LE9-NEXT:    xssqrtdp 3, 3
-; PC64LE9-NEXT:    xvsqrtdp 2, 0
-; PC64LE9-NEXT:    xxswapd 1, 2
+; PC64LE9-NEXT:    xxmrghd 0, 2, 1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE9-NEXT:    xssqrtdp 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    xvsqrtdp 2, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    blr
 entry:
   %sqrt = call <3 x double> @llvm.experimental.constrained.sqrt.v3f64(
                           <3 x double> %x,
                           metadata !"round.dynamic",
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %sqrt
 }
 
 define <4 x double> @constrained_vector_sqrt_v4f64(<4 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sqrt_v4f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvsqrtdp 35, 35
-; PC64LE-NEXT:    xvsqrtdp 34, 34
+; PC64LE-NEXT:    xvsqrtdp 35, 35 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)
+; PC64LE-NEXT:    xvsqrtdp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sqrt_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvsqrtdp 35, 35
-; PC64LE9-NEXT:    xvsqrtdp 34, 34
+; PC64LE9-NEXT:    xvsqrtdp 35, 35 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)
+; PC64LE9-NEXT:    xvsqrtdp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
  entry:
   %sqrt = call <4 x double> @llvm.experimental.constrained.sqrt.v4f64(
                               <4 x double> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <4 x double> %sqrt
 }

 define <2 x double> @constrained_vector_pow_v2f64(<2 x double> %x, <2 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_pow_v2f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 61, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 80
-; PC64LE-NEXT:    vmr 30, 2
+; PC64LE-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 3
-; PC64LE-NEXT:    xxlor 1, 62, 62
-; PC64LE-NEXT:    xxlor 2, 63, 63
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxlor 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl pow
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 62
-; PC64LE-NEXT:    xxswapd 2, 63
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE-NEXT:    xxswapd 2, 63 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    bl pow
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 80
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 34, 61, 1
+; PC64LE-NEXT:    xxmrghd 34, 61, 1 # Vec Defs: V2(VSR34) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 61, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_pow_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
 ; PC64LE9-NEXT:    stxv 62, 48(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE9-NEXT:    stxv 63, 64(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 3
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
-; PC64LE9-NEXT:    vmr 30, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 62, 62
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
+; PC64LE9-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE9-NEXT:    stxv 61, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE9-NEXT:    bl pow
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 62
-; PC64LE9-NEXT:    xxswapd 2, 63
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE9-NEXT:    xxswapd 2, 63 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    bl pow
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 34, 61, 1
+; PC64LE9-NEXT:    xxmrghd 34, 61, 1 # Vec Defs: V2(VSR34) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; PC64LE9-NEXT:    lxv 63, 64(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lxv 61, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %pow = call <2 x double> @llvm.experimental.constrained.pow.v2f64(
                              <2 x double> %x,
                              <2 x double> %y,
                              metadata !"round.dynamic",
                              metadata !"fpexcept.strict") #1
   ret <2 x double> %pow
 }
 
 define <3 x float> @constrained_vector_pow_v3f32(<3 x float> %x, <3 x float> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_pow_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE-NEXT:    xxsldwi 2, 35, 35, 1
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 2, 35, 35, 1 # Vec Defs: VSL2(VSR2) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stfd 30, 80(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 88(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    xscvspdpn 1, 0
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    vmr 31, 3
-; PC64LE-NEXT:    vmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    bl powf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 62
-; PC64LE-NEXT:    xxswapd 2, 63
-; PC64LE-NEXT:    fmr 31, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
-; PC64LE-NEXT:    xscvspdpn 2, 2
+; PC64LE-NEXT:    xxswapd 0, 62 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE-NEXT:    xxswapd 2, 63 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
 ; PC64LE-NEXT:    bl powf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxsldwi 0, 62, 62, 3
-; PC64LE-NEXT:    xxsldwi 2, 63, 63, 3
-; PC64LE-NEXT:    fmr 30, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
-; PC64LE-NEXT:    xscvspdpn 2, 2
+; PC64LE-NEXT:    xxsldwi 0, 62, 62, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE-NEXT:    xxsldwi 2, 63, 63, 3 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
 ; PC64LE-NEXT:    bl powf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xscvdpspn 34, 30
+; PC64LE-NEXT:    xscvdpspn 34, 30 # Vec Defs: V2(VSR34) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI32_0@toc@ha
 ; PC64LE-NEXT:    lfd 30, 80(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    xscvdpspn 35, 1
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI32_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    vmrghw 2, 2, 3
-; PC64LE-NEXT:    xscvdpspn 35, 31
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 88(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_pow_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 62, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    xxsldwi 0, 35, 35, 1
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxsldwi 0, 35, 35, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xscvspdpn 2, 0
-; PC64LE9-NEXT:    vmr 31, 3
-; PC64LE9-NEXT:    vmr 30, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 2, 0 # Vec Defs: F2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    bl powf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxswapd 0, 62
-; PC64LE9-NEXT:    fmr 31, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    xxswapd 0, 63
-; PC64LE9-NEXT:    xscvspdpn 2, 0
+; PC64LE9-NEXT:    xxswapd 0, 62 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE9-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 2, 0 # Vec Defs: F2(VSR2) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl powf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxsldwi 0, 62, 62, 3
-; PC64LE9-NEXT:    fmr 30, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE9-NEXT:    xscvspdpn 2, 0
+; PC64LE9-NEXT:    xxsldwi 0, 62, 62, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE9-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 2, 0 # Vec Defs: F2(VSR2) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl powf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscvdpspn 34, 1
-; PC64LE9-NEXT:    xscvdpspn 35, 30
+; PC64LE9-NEXT:    xscvdpspn 34, 1 # Vec Defs: V2(VSR34) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 35, 30 # Vec Defs: V3(VSR35) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI32_0@toc@ha
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI32_0@toc@l
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 31
+; PC64LE9-NEXT:    lxv 36, 0(3) # Vec Defs: V4(VSR36)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE9-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %pow = call <3 x float> @llvm.experimental.constrained.pow.v3f32(
                              <3 x float> %x,
                              <3 x float> %y,
                              metadata !"round.dynamic",
                              metadata !"fpexcept.strict") #1
   ret <3 x float> %pow
 }
 
 define <3 x double> @constrained_vector_pow_v3f64(<3 x double> %x, <3 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_pow_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
 ; PC64LE-NEXT:    stfd 28, 64(1) # 8-byte Folded Spill
-; PC64LE-NEXT:    fmr 28, 2
+; PC64LE-NEXT:    # Vec Uses: F28(VSR28)
+; PC64LE-NEXT:    fmr 28, 2 # Vec Defs: F28(VSR28) Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    fmr 2, 4
+; PC64LE-NEXT:    fmr 2, 4 # Vec Defs: F2(VSR2) Vec Uses: F4(VSR4)
 ; PC64LE-NEXT:    stfd 29, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F29(VSR29)
 ; PC64LE-NEXT:    stfd 30, 80(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 88(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    fmr 31, 6
-; PC64LE-NEXT:    fmr 30, 5
-; PC64LE-NEXT:    fmr 29, 3
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 6 # Vec Defs: F31(VSR31) Vec Uses: F6(VSR6)
+; PC64LE-NEXT:    fmr 30, 5 # Vec Defs: F30(VSR30) Vec Uses: F5(VSR5)
+; PC64LE-NEXT:    fmr 29, 3 # Vec Defs: F29(VSR29) Vec Uses: F3(VSR3)
 ; PC64LE-NEXT:    bl pow
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 63, 1, 1
-; PC64LE-NEXT:    fmr 1, 28
-; PC64LE-NEXT:    fmr 2, 30
+; PC64LE-NEXT:    xxlor 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 28 # Vec Defs: F1(VSR1) Vec Uses: F28(VSR28)
+; PC64LE-NEXT:    fmr 2, 30 # Vec Defs: F2(VSR2) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    bl pow
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 63, 1, 63
-; PC64LE-NEXT:    fmr 2, 31
-; PC64LE-NEXT:    fmr 1, 29
+; PC64LE-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE-NEXT:    fmr 2, 31 # Vec Defs: F2(VSR2) Vec Uses: F31(VSR31)
+; PC64LE-NEXT:    fmr 1, 29 # Vec Defs: F1(VSR1) Vec Uses: F29(VSR29)
 ; PC64LE-NEXT:    bl pow
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    xxlor 2, 63, 63
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 88(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE-NEXT:    lfd 30, 80(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    lfd 29, 72(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    fmr 3, 1
+; PC64LE-NEXT:    # Vec Defs: F29(VSR29)
+; PC64LE-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    lfd 28, 64(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    fmr 1, 0
+; PC64LE-NEXT:    # Vec Defs: F28(VSR28)
+; PC64LE-NEXT:    fmr 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_pow_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
 ; PC64LE9-NEXT:    stfd 28, 48(1) # 8-byte Folded Spill
-; PC64LE9-NEXT:    fmr 28, 2
+; PC64LE9-NEXT:    # Vec Uses: F28(VSR28)
+; PC64LE9-NEXT:    fmr 28, 2 # Vec Defs: F28(VSR28) Vec Uses: F2(VSR2)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    fmr 2, 4
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    fmr 2, 4 # Vec Defs: F2(VSR2) Vec Uses: F4(VSR4)
 ; PC64LE9-NEXT:    stfd 29, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F29(VSR29)
 ; PC64LE9-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
-; PC64LE9-NEXT:    fmr 31, 6
-; PC64LE9-NEXT:    fmr 30, 5
-; PC64LE9-NEXT:    fmr 29, 3
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
+; PC64LE9-NEXT:    fmr 31, 6 # Vec Defs: F31(VSR31) Vec Uses: F6(VSR6)
+; PC64LE9-NEXT:    fmr 30, 5 # Vec Defs: F30(VSR30) Vec Uses: F5(VSR5)
+; PC64LE9-NEXT:    fmr 29, 3 # Vec Defs: F29(VSR29) Vec Uses: F3(VSR3)
 ; PC64LE9-NEXT:    bl pow
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 63, 1, 1
-; PC64LE9-NEXT:    fmr 1, 28
-; PC64LE9-NEXT:    fmr 2, 30
+; PC64LE9-NEXT:    xscpsgndp 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    fmr 1, 28 # Vec Defs: F1(VSR1) Vec Uses: F28(VSR28)
+; PC64LE9-NEXT:    fmr 2, 30 # Vec Defs: F2(VSR2) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    bl pow
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 1, 63
-; PC64LE9-NEXT:    fmr 1, 29
-; PC64LE9-NEXT:    fmr 2, 31
+; PC64LE9-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE9-NEXT:    fmr 1, 29 # Vec Defs: F1(VSR1) Vec Uses: F29(VSR29)
+; PC64LE9-NEXT:    fmr 2, 31 # Vec Defs: F2(VSR2) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    bl pow
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
+; PC64LE9-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    lfd 29, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F29(VSR29)
 ; PC64LE9-NEXT:    lfd 28, 48(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F28(VSR28)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %pow = call <3 x double> @llvm.experimental.constrained.pow.v3f64(
                           <3 x double> %x,
                           <3 x double> %y,
                           metadata !"round.dynamic",
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %pow
 }
 
 define <4 x double> @constrained_vector_pow_v4f64(<4 x double> %x, <4 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_pow_v4f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -128(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 59, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V27(VSR59)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 60, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V28(VSR60)
 ; PC64LE-NEXT:    li 3, 80
-; PC64LE-NEXT:    vmr 28, 2
+; PC64LE-NEXT:    vmr 28, 2 # Vec Defs: V28(VSR60) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    stxvd2x 61, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE-NEXT:    li 3, 96
-; PC64LE-NEXT:    vmr 29, 3
+; PC64LE-NEXT:    vmr 29, 3 # Vec Defs: V29(VSR61) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 30, 4
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE-NEXT:    vmr 30, 4 # Vec Defs: V30(VSR62) Vec Uses: V4(VSR36)V4(VSR36)
 ; PC64LE-NEXT:    li 3, 112
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 5
-; PC64LE-NEXT:    xxlor 1, 60, 60
-; PC64LE-NEXT:    xxlor 2, 62, 62
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 5 # Vec Defs: V31(VSR63) Vec Uses: V5(VSR37)V5(VSR37)
+; PC64LE-NEXT:    xxlor 1, 60, 60 # Vec Defs: F1(VSR1) Vec Uses: VF28(VSR28)VF28(VSR28)
+; PC64LE-NEXT:    xxlor 2, 62, 62 # Vec Defs: F2(VSR2) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE-NEXT:    bl pow
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 59, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 60
-; PC64LE-NEXT:    xxswapd 2, 62
+; PC64LE-NEXT:    xxlor 59, 1, 1 # Vec Defs: VF27(VSR27) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 60 # Vec Defs: VSL1(VSR1) Vec Uses: V28(VSR60)V28(VSR60)
+; PC64LE-NEXT:    xxswapd 2, 62 # Vec Defs: VSL2(VSR2) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    bl pow
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 62, 59, 1
-; PC64LE-NEXT:    xxlor 2, 63, 63
-; PC64LE-NEXT:    xxlor 1, 61, 61
+; PC64LE-NEXT:    xxmrghd 62, 59, 1 # Vec Defs: V30(VSR62) Vec Uses: V27(VSR59)VSL1(VSR1)
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
+; PC64LE-NEXT:    xxlor 1, 61, 61 # Vec Defs: F1(VSR1) Vec Uses: VF29(VSR29)VF29(VSR29)
 ; PC64LE-NEXT:    bl pow
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 60, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 61
-; PC64LE-NEXT:    xxswapd 2, 63
+; PC64LE-NEXT:    xxlor 60, 1, 1 # Vec Defs: VF28(VSR28) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 61 # Vec Defs: VSL1(VSR1) Vec Uses: V29(VSR61)V29(VSR61)
+; PC64LE-NEXT:    xxswapd 2, 63 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    bl pow
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 112
-; PC64LE-NEXT:    vmr 2, 30
+; PC64LE-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 35, 60, 1
+; PC64LE-NEXT:    xxmrghd 35, 60, 1 # Vec Defs: V3(VSR35) Vec Uses: V28(VSR60)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 96
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 80
 ; PC64LE-NEXT:    lxvd2x 61, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 60, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V28(VSR60)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 59, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V27(VSR59)
 ; PC64LE-NEXT:    addi 1, 1, 128
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_pow_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -112(1)
 ; PC64LE9-NEXT:    stxv 60, 48(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V28(VSR60)
 ; PC64LE9-NEXT:    stxv 62, 80(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 30, 4
-; PC64LE9-NEXT:    xscpsgndp 2, 62, 62
-; PC64LE9-NEXT:    vmr 28, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 60, 60
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE9-NEXT:    vmr 30, 4 # Vec Defs: V30(VSR62) Vec Uses: V4(VSR36)V4(VSR36)
+; PC64LE9-NEXT:    xscpsgndp 2, 62, 62 # Vec Defs: F2(VSR2) Vec Uses: VF30(VSR30)VF30(VSR30)
+; PC64LE9-NEXT:    vmr 28, 2 # Vec Defs: V28(VSR60) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 60, 60 # Vec Defs: F1(VSR1) Vec Uses: VF28(VSR28)VF28(VSR28)
 ; PC64LE9-NEXT:    stxv 59, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V27(VSR59)
 ; PC64LE9-NEXT:    stxv 61, 64(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE9-NEXT:    stxv 63, 96(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 5
-; PC64LE9-NEXT:    vmr 29, 3
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 5 # Vec Defs: V31(VSR63) Vec Uses: V5(VSR37)V5(VSR37)
+; PC64LE9-NEXT:    vmr 29, 3 # Vec Defs: V29(VSR61) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE9-NEXT:    bl pow
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 59, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 60
-; PC64LE9-NEXT:    xxswapd 2, 62
+; PC64LE9-NEXT:    xscpsgndp 59, 1, 1 # Vec Defs: VF27(VSR27) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 60 # Vec Defs: VSL1(VSR1) Vec Uses: V28(VSR60)V28(VSR60)
+; PC64LE9-NEXT:    xxswapd 2, 62 # Vec Defs: VSL2(VSR2) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    bl pow
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 62, 59, 1
-; PC64LE9-NEXT:    xscpsgndp 1, 61, 61
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
+; PC64LE9-NEXT:    xxmrghd 62, 59, 1 # Vec Defs: V30(VSR62) Vec Uses: V27(VSR59)VSL1(VSR1)
+; PC64LE9-NEXT:    xscpsgndp 1, 61, 61 # Vec Defs: F1(VSR1) Vec Uses: VF29(VSR29)VF29(VSR29)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    bl pow
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 60, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 61
-; PC64LE9-NEXT:    xxswapd 2, 63
+; PC64LE9-NEXT:    xscpsgndp 60, 1, 1 # Vec Defs: VF28(VSR28) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 61 # Vec Defs: VSL1(VSR1) Vec Uses: V29(VSR61)V29(VSR61)
+; PC64LE9-NEXT:    xxswapd 2, 63 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    bl pow
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 35, 60, 1
-; PC64LE9-NEXT:    vmr 2, 30
+; PC64LE9-NEXT:    xxmrghd 35, 60, 1 # Vec Defs: V3(VSR35) Vec Uses: V28(VSR60)VSL1(VSR1)
+; PC64LE9-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    lxv 63, 96(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 80(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lxv 61, 64(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE9-NEXT:    lxv 60, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V28(VSR60)
 ; PC64LE9-NEXT:    lxv 59, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V27(VSR59)
 ; PC64LE9-NEXT:    addi 1, 1, 112
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %pow = call <4 x double> @llvm.experimental.constrained.pow.v4f64(
                              <4 x double> %x,
                              <4 x double> %y,

 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    std 30, 80(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    clrldi 30, 5, 32
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    mr 4, 30
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl __powidf2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 62, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    mr 4, 30
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl __powidf2
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 34, 62, 1
+; PC64LE-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE-NEXT:    ld 30, 80(1) # 8-byte Folded Reload
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_powi_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
 ; PC64LE9-NEXT:    std 30, 64(1) # 8-byte Folded Spill
 ; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    clrldi 30, 5, 32
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    mr 4, 30
 ; PC64LE9-NEXT:    stxv 62, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE9-NEXT:    bl __powidf2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    mr 4, 30
-; PC64LE9-NEXT:    xscpsgndp 62, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl __powidf2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 34, 62, 1
+; PC64LE9-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    ld 30, 64(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %powi = call <2 x double> @llvm.experimental.constrained.powi.v2f64(
                               <2 x double> %x,
                               i32 %y,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <2 x double> %powi
 }
 
 define <3 x float> @constrained_vector_powi_v3f32(<3 x float> %x, i32 %y) #0 {
 ;
 ;
 ; PC64LE-LABEL: constrained_vector_powi_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    std 30, 64(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    clrldi 30, 5, 32
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 80(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    mr 4, 30
 ; PC64LE-NEXT:    stfd 31, 88(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl __powisf2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
-; PC64LE-NEXT:    fmr 31, 1
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    mr 4, 30
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl __powisf2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE-NEXT:    fmr 30, 1
+; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    mr 4, 30
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl __powisf2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xscvdpspn 34, 30
+; PC64LE-NEXT:    xscvdpspn 34, 30 # Vec Defs: V2(VSR34) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI37_0@toc@ha
 ; PC64LE-NEXT:    lfd 30, 80(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE-NEXT:    ld 30, 64(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    xscvdpspn 35, 1
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI37_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    vmrghw 2, 2, 3
-; PC64LE-NEXT:    xscvdpspn 35, 31
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 88(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_powi_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    std 30, 48(1) # 8-byte Folded Spill
 ; PC64LE9-NEXT:    clrldi 30, 5, 32
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
 ; PC64LE9-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 2
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    mr 4, 30
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl __powisf2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxswapd 0, 63
-; PC64LE9-NEXT:    fmr 31, 1
+; PC64LE9-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
 ; PC64LE9-NEXT:    mr 4, 30
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl __powisf2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE9-NEXT:    fmr 30, 1
+; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
 ; PC64LE9-NEXT:    mr 4, 30
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl __powisf2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscvdpspn 34, 1
-; PC64LE9-NEXT:    xscvdpspn 35, 30
+; PC64LE9-NEXT:    xscvdpspn 34, 1 # Vec Defs: V2(VSR34) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 35, 30 # Vec Defs: V3(VSR35) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI37_0@toc@ha
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    ld 30, 48(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI37_0@toc@l
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 31
+; PC64LE9-NEXT:    lxv 36, 0(3) # Vec Defs: V4(VSR36)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE9-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %powi = call <3 x float> @llvm.experimental.constrained.powi.v3f32(
                               <3 x float> %x,
                               i32 %y,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %powi
 }
 
 define <3 x double> @constrained_vector_powi_v3f64(<3 x double> %x, i32 %y) #0 {
 ; PC64LE-LABEL: constrained_vector_powi_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
 ; PC64LE-NEXT:    std 30, 64(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    clrldi 30, 6, 32
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 80(1) # 8-byte Folded Spill
-; PC64LE-NEXT:    fmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
+; PC64LE-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    mr 4, 30
 ; PC64LE-NEXT:    stfd 31, 88(1) # 8-byte Folded Spill
-; PC64LE-NEXT:    fmr 31, 3
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
+; PC64LE-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
 ; PC64LE-NEXT:    bl __powidf2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 63, 1, 1
-; PC64LE-NEXT:    fmr 1, 30
+; PC64LE-NEXT:    xxlor 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    mr 4, 30
 ; PC64LE-NEXT:    bl __powidf2
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 63, 1, 63
+; PC64LE-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
 ; PC64LE-NEXT:    mr 4, 30
-; PC64LE-NEXT:    fmr 1, 31
+; PC64LE-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    bl __powidf2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    xxlor 2, 63, 63
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 88(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE-NEXT:    lfd 30, 80(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE-NEXT:    ld 30, 64(1) # 8-byte Folded Reload
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    fmr 3, 1
-; PC64LE-NEXT:    fmr 1, 0
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_powi_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
 ; PC64LE9-NEXT:    std 30, 48(1) # 8-byte Folded Spill
 ; PC64LE9-NEXT:    clrldi 30, 6, 32
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
 ; PC64LE9-NEXT:    mr 4, 30
 ; PC64LE9-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
-; PC64LE9-NEXT:    fmr 31, 3
-; PC64LE9-NEXT:    fmr 30, 2
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
+; PC64LE9-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE9-NEXT:    bl __powidf2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 63, 1, 1
-; PC64LE9-NEXT:    fmr 1, 30
+; PC64LE9-NEXT:    xscpsgndp 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    mr 4, 30
 ; PC64LE9-NEXT:    bl __powidf2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 1, 63
-; PC64LE9-NEXT:    fmr 1, 31
+; PC64LE9-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE9-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    mr 4, 30
 ; PC64LE9-NEXT:    bl __powidf2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
+; PC64LE9-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    ld 30, 48(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %powi = call <3 x double> @llvm.experimental.constrained.powi.v3f64(
                           <3 x double> %x,
                           i32 %y,
                           metadata !"round.dynamic",
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %powi
 }
 
 define <4 x double> @constrained_vector_powi_v4f64(<4 x double> %x, i32 %y) #0 {
 ; PC64LE-LABEL: constrained_vector_powi_v4f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -112(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    std 30, 96(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    clrldi 30, 7, 32
 ; PC64LE-NEXT:    stxvd2x 61, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    mr 4, 30
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 80
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 3
-; PC64LE-NEXT:    xxlor 1, 62, 62
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxlor 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE-NEXT:    bl __powidf2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 62
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    mr 4, 30
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl __powidf2
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 62, 61, 1
+; PC64LE-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; PC64LE-NEXT:    mr 4, 30
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl __powidf2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    mr 4, 30
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl __powidf2
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 80
-; PC64LE-NEXT:    vmr 2, 30
+; PC64LE-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 35, 61, 1
+; PC64LE-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; PC64LE-NEXT:    ld 30, 96(1) # 8-byte Folded Reload
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 61, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE-NEXT:    addi 1, 1, 112
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_powi_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -96(1)
 ; PC64LE9-NEXT:    std 30, 80(1) # 8-byte Folded Spill
 ; PC64LE9-NEXT:    stxv 62, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 30, 2
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE9-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    clrldi 30, 7, 32
-; PC64LE9-NEXT:    xscpsgndp 1, 62, 62
+; PC64LE9-NEXT:    xscpsgndp 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE9-NEXT:    mr 4, 30
 ; PC64LE9-NEXT:    stxv 61, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE9-NEXT:    stxv 63, 64(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 3
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE9-NEXT:    bl __powidf2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    mr 4, 30
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 62
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl __powidf2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 62, 61, 1
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    mr 4, 30
 ; PC64LE9-NEXT:    bl __powidf2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    mr 4, 30
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl __powidf2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 35, 61, 1
-; PC64LE9-NEXT:    vmr 2, 30
+; PC64LE9-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    lxv 63, 64(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lxv 61, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE9-NEXT:    ld 30, 80(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    addi 1, 1, 96
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %powi = call <4 x double> @llvm.experimental.constrained.powi.v4f64(
                               <4 x double> %x,

 define <2 x double> @constrained_vector_sin_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sin_v2f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl sin
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 62, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl sin
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 34, 62, 1
+; PC64LE-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sin_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    stxv 62, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE9-NEXT:    bl sin
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 62, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl sin
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 34, 62, 1
+; PC64LE9-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %sin = call <2 x double> @llvm.experimental.constrained.sin.v2f64(
                              <2 x double> %x,
                              metadata !"round.dynamic",
                              metadata !"fpexcept.strict") #1
   ret <2 x double> %sin
 }
 
 define <3 x float> @constrained_vector_sin_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sin_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl sinf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
-; PC64LE-NEXT:    fmr 31, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl sinf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE-NEXT:    fmr 30, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl sinf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xscvdpspn 34, 30
+; PC64LE-NEXT:    xscvdpspn 34, 30 # Vec Defs: V2(VSR34) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI42_0@toc@ha
 ; PC64LE-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    xscvdpspn 35, 1
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI42_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    vmrghw 2, 2, 3
-; PC64LE-NEXT:    xscvdpspn 35, 31
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sin_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    vmr 31, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    bl sinf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxswapd 0, 63
-; PC64LE9-NEXT:    fmr 31, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl sinf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE9-NEXT:    fmr 30, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl sinf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscvdpspn 34, 1
-; PC64LE9-NEXT:    xscvdpspn 35, 30
+; PC64LE9-NEXT:    xscvdpspn 34, 1 # Vec Defs: V2(VSR34) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 35, 30 # Vec Defs: V3(VSR35) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI42_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    xscvdpspn 36, 31 # Vec Defs: V4(VSR36) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI42_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %sin = call <3 x float> @llvm.experimental.constrained.sin.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %sin
 }
 
 define <3 x double> @constrained_vector_sin_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sin_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    fmr 31, 3
-; PC64LE-NEXT:    fmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    bl sin
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 63, 1, 1
-; PC64LE-NEXT:    fmr 1, 30
+; PC64LE-NEXT:    xxlor 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    bl sin
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 63, 1, 63
-; PC64LE-NEXT:    fmr 1, 31
+; PC64LE-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    bl sin
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    xxlor 2, 63, 63
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    fmr 3, 1
-; PC64LE-NEXT:    fmr 1, 0
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sin_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    fmr 31, 3
-; PC64LE9-NEXT:    fmr 30, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE9-NEXT:    bl sin
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 63, 1, 1
-; PC64LE9-NEXT:    fmr 1, 30
+; PC64LE9-NEXT:    xscpsgndp 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    bl sin
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 1, 63
-; PC64LE9-NEXT:    fmr 1, 31
+; PC64LE9-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE9-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    bl sin
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
+; PC64LE9-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %sin = call <3 x double> @llvm.experimental.constrained.sin.v3f64(
                           <3 x double> %x,
                           metadata !"round.dynamic",
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %sin
 }
 
 define <4 x double> @constrained_vector_sin_v4f64(<4 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sin_v4f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 61, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 80
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 3
-; PC64LE-NEXT:    xxlor 1, 62, 62
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxlor 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE-NEXT:    bl sin
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 62
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl sin
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 62, 61, 1
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl sin
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl sin
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 80
-; PC64LE-NEXT:    vmr 2, 30
+; PC64LE-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 35, 61, 1
+; PC64LE-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 61, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sin_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
 ; PC64LE9-NEXT:    stxv 62, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 30, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 62, 62
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE9-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE9-NEXT:    stxv 61, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE9-NEXT:    stxv 63, 64(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 3
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE9-NEXT:    bl sin
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 62
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl sin
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 62, 61, 1
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    bl sin
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl sin
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 35, 61, 1
-; PC64LE9-NEXT:    vmr 2, 30
+; PC64LE9-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    lxv 63, 64(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lxv 61, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %sin = call <4 x double> @llvm.experimental.constrained.sin.v4f64(
                              <4 x double> %x,
                              metadata !"round.dynamic",

 define <2 x double> @constrained_vector_cos_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_cos_v2f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl cos
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 62, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl cos
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 34, 62, 1
+; PC64LE-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_cos_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    stxv 62, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE9-NEXT:    bl cos
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 62, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl cos
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 34, 62, 1
+; PC64LE9-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %cos = call <2 x double> @llvm.experimental.constrained.cos.v2f64(
                              <2 x double> %x,
                              metadata !"round.dynamic",
                              metadata !"fpexcept.strict") #1
   ret <2 x double> %cos
 }
 
 define <3 x float> @constrained_vector_cos_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_cos_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl cosf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
-; PC64LE-NEXT:    fmr 31, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl cosf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE-NEXT:    fmr 30, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl cosf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xscvdpspn 34, 30
+; PC64LE-NEXT:    xscvdpspn 34, 30 # Vec Defs: V2(VSR34) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI47_0@toc@ha
 ; PC64LE-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    xscvdpspn 35, 1
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI47_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    vmrghw 2, 2, 3
-; PC64LE-NEXT:    xscvdpspn 35, 31
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_cos_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    vmr 31, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    bl cosf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxswapd 0, 63
-; PC64LE9-NEXT:    fmr 31, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl cosf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE9-NEXT:    fmr 30, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl cosf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscvdpspn 34, 1
-; PC64LE9-NEXT:    xscvdpspn 35, 30
+; PC64LE9-NEXT:    xscvdpspn 34, 1 # Vec Defs: V2(VSR34) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 35, 30 # Vec Defs: V3(VSR35) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI47_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    xscvdpspn 36, 31 # Vec Defs: V4(VSR36) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI47_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %cos = call <3 x float> @llvm.experimental.constrained.cos.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %cos
 }
 
 define <3 x double> @constrained_vector_cos_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_cos_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    fmr 31, 3
-; PC64LE-NEXT:    fmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    bl cos
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 63, 1, 1
-; PC64LE-NEXT:    fmr 1, 30
+; PC64LE-NEXT:    xxlor 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    bl cos
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 63, 1, 63
-; PC64LE-NEXT:    fmr 1, 31
+; PC64LE-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    bl cos
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    xxlor 2, 63, 63
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    fmr 3, 1
-; PC64LE-NEXT:    fmr 1, 0
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_cos_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    fmr 31, 3
-; PC64LE9-NEXT:    fmr 30, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE9-NEXT:    bl cos
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 63, 1, 1
-; PC64LE9-NEXT:    fmr 1, 30
+; PC64LE9-NEXT:    xscpsgndp 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    bl cos
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 1, 63
-; PC64LE9-NEXT:    fmr 1, 31
+; PC64LE9-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE9-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    bl cos
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
+; PC64LE9-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %cos = call <3 x double> @llvm.experimental.constrained.cos.v3f64(
                           <3 x double> %x,
                           metadata !"round.dynamic",
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %cos
 }
 
 define <4 x double> @constrained_vector_cos_v4f64(<4 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_cos_v4f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 61, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 80
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 3
-; PC64LE-NEXT:    xxlor 1, 62, 62
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxlor 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE-NEXT:    bl cos
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 62
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl cos
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 62, 61, 1
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl cos
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl cos
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 80
-; PC64LE-NEXT:    vmr 2, 30
+; PC64LE-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 35, 61, 1
+; PC64LE-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 61, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_cos_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
 ; PC64LE9-NEXT:    stxv 62, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 30, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 62, 62
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE9-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE9-NEXT:    stxv 61, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE9-NEXT:    stxv 63, 64(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 3
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE9-NEXT:    bl cos
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 62
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl cos
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 62, 61, 1
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    bl cos
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl cos
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 35, 61, 1
-; PC64LE9-NEXT:    vmr 2, 30
+; PC64LE9-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    lxv 63, 64(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lxv 61, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %cos = call <4 x double> @llvm.experimental.constrained.cos.v4f64(
                              <4 x double> %x,
                              metadata !"round.dynamic",

 define <2 x double> @constrained_vector_exp_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_exp_v2f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl exp
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 62, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl exp
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 34, 62, 1
+; PC64LE-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_exp_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    stxv 62, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE9-NEXT:    bl exp
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 62, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl exp
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 34, 62, 1
+; PC64LE9-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %exp = call <2 x double> @llvm.experimental.constrained.exp.v2f64(
                              <2 x double> %x,
                              metadata !"round.dynamic",
                              metadata !"fpexcept.strict") #1
   ret <2 x double> %exp
 }
 
 define <3 x float> @constrained_vector_exp_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_exp_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl expf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
-; PC64LE-NEXT:    fmr 31, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl expf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE-NEXT:    fmr 30, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl expf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xscvdpspn 34, 30
+; PC64LE-NEXT:    xscvdpspn 34, 30 # Vec Defs: V2(VSR34) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI52_0@toc@ha
 ; PC64LE-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    xscvdpspn 35, 1
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI52_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    vmrghw 2, 2, 3
-; PC64LE-NEXT:    xscvdpspn 35, 31
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_exp_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    vmr 31, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    bl expf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxswapd 0, 63
-; PC64LE9-NEXT:    fmr 31, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl expf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE9-NEXT:    fmr 30, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl expf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscvdpspn 34, 1
-; PC64LE9-NEXT:    xscvdpspn 35, 30
+; PC64LE9-NEXT:    xscvdpspn 34, 1 # Vec Defs: V2(VSR34) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 35, 30 # Vec Defs: V3(VSR35) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI52_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    xscvdpspn 36, 31 # Vec Defs: V4(VSR36) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI52_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %exp = call <3 x float> @llvm.experimental.constrained.exp.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %exp
 }
 
 define <3 x double> @constrained_vector_exp_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_exp_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    fmr 31, 3
-; PC64LE-NEXT:    fmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    bl exp
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 63, 1, 1
-; PC64LE-NEXT:    fmr 1, 30
+; PC64LE-NEXT:    xxlor 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    bl exp
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 63, 1, 63
-; PC64LE-NEXT:    fmr 1, 31
+; PC64LE-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    bl exp
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    xxlor 2, 63, 63
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    fmr 3, 1
-; PC64LE-NEXT:    fmr 1, 0
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_exp_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    fmr 31, 3
-; PC64LE9-NEXT:    fmr 30, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE9-NEXT:    bl exp
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 63, 1, 1
-; PC64LE9-NEXT:    fmr 1, 30
+; PC64LE9-NEXT:    xscpsgndp 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    bl exp
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 1, 63
-; PC64LE9-NEXT:    fmr 1, 31
+; PC64LE9-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE9-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    bl exp
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
+; PC64LE9-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %exp = call <3 x double> @llvm.experimental.constrained.exp.v3f64(
                           <3 x double> %x,
                           metadata !"round.dynamic",
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %exp
 }
 
 define <4 x double> @constrained_vector_exp_v4f64(<4 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_exp_v4f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 61, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 80
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 3
-; PC64LE-NEXT:    xxlor 1, 62, 62
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxlor 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE-NEXT:    bl exp
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 62
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl exp
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 62, 61, 1
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl exp
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl exp
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 80
-; PC64LE-NEXT:    vmr 2, 30
+; PC64LE-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 35, 61, 1
+; PC64LE-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 61, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_exp_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
 ; PC64LE9-NEXT:    stxv 62, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 30, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 62, 62
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE9-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE9-NEXT:    stxv 61, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE9-NEXT:    stxv 63, 64(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 3
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE9-NEXT:    bl exp
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 62
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl exp
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 62, 61, 1
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    bl exp
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl exp
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 35, 61, 1
-; PC64LE9-NEXT:    vmr 2, 30
+; PC64LE9-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    lxv 63, 64(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lxv 61, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %exp = call <4 x double> @llvm.experimental.constrained.exp.v4f64(
                              <4 x double> %x,
                              metadata !"round.dynamic",

 define <2 x double> @constrained_vector_exp2_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_exp2_v2f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl exp2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 62, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl exp2
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 34, 62, 1
+; PC64LE-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_exp2_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    stxv 62, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE9-NEXT:    bl exp2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 62, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl exp2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 34, 62, 1
+; PC64LE9-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %exp2 = call <2 x double> @llvm.experimental.constrained.exp2.v2f64(
                               <2 x double> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <2 x double> %exp2
 }
 
 define <3 x float> @constrained_vector_exp2_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_exp2_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl exp2f
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
-; PC64LE-NEXT:    fmr 31, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl exp2f
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE-NEXT:    fmr 30, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl exp2f
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xscvdpspn 34, 30
+; PC64LE-NEXT:    xscvdpspn 34, 30 # Vec Defs: V2(VSR34) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI57_0@toc@ha
 ; PC64LE-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    xscvdpspn 35, 1
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI57_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    vmrghw 2, 2, 3
-; PC64LE-NEXT:    xscvdpspn 35, 31
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_exp2_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    vmr 31, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    bl exp2f
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxswapd 0, 63
-; PC64LE9-NEXT:    fmr 31, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl exp2f
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE9-NEXT:    fmr 30, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl exp2f
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscvdpspn 34, 1
-; PC64LE9-NEXT:    xscvdpspn 35, 30
+; PC64LE9-NEXT:    xscvdpspn 34, 1 # Vec Defs: V2(VSR34) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 35, 30 # Vec Defs: V3(VSR35) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI57_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    xscvdpspn 36, 31 # Vec Defs: V4(VSR36) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI57_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %exp2 = call <3 x float> @llvm.experimental.constrained.exp2.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %exp2
 }
 
 define <3 x double> @constrained_vector_exp2_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_exp2_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    fmr 31, 3
-; PC64LE-NEXT:    fmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    bl exp2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 63, 1, 1
-; PC64LE-NEXT:    fmr 1, 30
+; PC64LE-NEXT:    xxlor 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    bl exp2
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 63, 1, 63
-; PC64LE-NEXT:    fmr 1, 31
+; PC64LE-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    bl exp2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    xxlor 2, 63, 63
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    fmr 3, 1
-; PC64LE-NEXT:    fmr 1, 0
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_exp2_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    fmr 31, 3
-; PC64LE9-NEXT:    fmr 30, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE9-NEXT:    bl exp2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 63, 1, 1
-; PC64LE9-NEXT:    fmr 1, 30
+; PC64LE9-NEXT:    xscpsgndp 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    bl exp2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 1, 63
-; PC64LE9-NEXT:    fmr 1, 31
+; PC64LE9-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE9-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    bl exp2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
+; PC64LE9-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %exp2 = call <3 x double> @llvm.experimental.constrained.exp2.v3f64(
                           <3 x double> %x,
                           metadata !"round.dynamic",
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %exp2
 }
 
 define <4 x double> @constrained_vector_exp2_v4f64(<4 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_exp2_v4f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 61, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 80
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 3
-; PC64LE-NEXT:    xxlor 1, 62, 62
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxlor 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE-NEXT:    bl exp2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 62
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl exp2
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 62, 61, 1
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl exp2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl exp2
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 80
-; PC64LE-NEXT:    vmr 2, 30
+; PC64LE-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 35, 61, 1
+; PC64LE-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 61, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_exp2_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
 ; PC64LE9-NEXT:    stxv 62, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 30, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 62, 62
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE9-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE9-NEXT:    stxv 61, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE9-NEXT:    stxv 63, 64(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 3
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE9-NEXT:    bl exp2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 62
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl exp2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 62, 61, 1
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    bl exp2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl exp2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 35, 61, 1
-; PC64LE9-NEXT:    vmr 2, 30
+; PC64LE9-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    lxv 63, 64(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lxv 61, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %exp2 = call <4 x double> @llvm.experimental.constrained.exp2.v4f64(
                               <4 x double> %x,
                               metadata !"round.dynamic",

 define <2 x double> @constrained_vector_log_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_log_v2f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl log
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 62, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl log
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 34, 62, 1
+; PC64LE-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_log_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    stxv 62, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE9-NEXT:    bl log
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 62, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl log
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 34, 62, 1
+; PC64LE9-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log = call <2 x double> @llvm.experimental.constrained.log.v2f64(
                              <2 x double> %x,
                              metadata !"round.dynamic",
                              metadata !"fpexcept.strict") #1
   ret <2 x double> %log
 }
 
 define <3 x float> @constrained_vector_log_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_log_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl logf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
-; PC64LE-NEXT:    fmr 31, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl logf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE-NEXT:    fmr 30, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl logf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xscvdpspn 34, 30
+; PC64LE-NEXT:    xscvdpspn 34, 30 # Vec Defs: V2(VSR34) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI62_0@toc@ha
 ; PC64LE-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    xscvdpspn 35, 1
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI62_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    vmrghw 2, 2, 3
-; PC64LE-NEXT:    xscvdpspn 35, 31
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_log_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    vmr 31, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    bl logf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxswapd 0, 63
-; PC64LE9-NEXT:    fmr 31, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl logf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE9-NEXT:    fmr 30, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl logf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscvdpspn 34, 1
-; PC64LE9-NEXT:    xscvdpspn 35, 30
+; PC64LE9-NEXT:    xscvdpspn 34, 1 # Vec Defs: V2(VSR34) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 35, 30 # Vec Defs: V3(VSR35) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI62_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    xscvdpspn 36, 31 # Vec Defs: V4(VSR36) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI62_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log = call <3 x float> @llvm.experimental.constrained.log.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %log
 }
 
 define <3 x double> @constrained_vector_log_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_log_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    fmr 31, 3
-; PC64LE-NEXT:    fmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    bl log
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 63, 1, 1
-; PC64LE-NEXT:    fmr 1, 30
+; PC64LE-NEXT:    xxlor 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    bl log
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 63, 1, 63
-; PC64LE-NEXT:    fmr 1, 31
+; PC64LE-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    bl log
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    xxlor 2, 63, 63
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    fmr 3, 1
-; PC64LE-NEXT:    fmr 1, 0
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_log_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    fmr 31, 3
-; PC64LE9-NEXT:    fmr 30, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE9-NEXT:    bl log
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 63, 1, 1
-; PC64LE9-NEXT:    fmr 1, 30
+; PC64LE9-NEXT:    xscpsgndp 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    bl log
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 1, 63
-; PC64LE9-NEXT:    fmr 1, 31
+; PC64LE9-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE9-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    bl log
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
+; PC64LE9-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log = call <3 x double> @llvm.experimental.constrained.log.v3f64(
                           <3 x double> %x,
                           metadata !"round.dynamic",
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %log
 }
 
 define <4 x double> @constrained_vector_log_v4f64(<4 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_log_v4f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 61, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 80
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 3
-; PC64LE-NEXT:    xxlor 1, 62, 62
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxlor 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE-NEXT:    bl log
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 62
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl log
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 62, 61, 1
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl log
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl log
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 80
-; PC64LE-NEXT:    vmr 2, 30
+; PC64LE-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 35, 61, 1
+; PC64LE-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 61, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_log_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
 ; PC64LE9-NEXT:    stxv 62, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 30, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 62, 62
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE9-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE9-NEXT:    stxv 61, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE9-NEXT:    stxv 63, 64(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 3
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE9-NEXT:    bl log
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 62
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl log
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 62, 61, 1
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    bl log
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl log
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 35, 61, 1
-; PC64LE9-NEXT:    vmr 2, 30
+; PC64LE9-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    lxv 63, 64(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lxv 61, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log = call <4 x double> @llvm.experimental.constrained.log.v4f64(
                              <4 x double> %x,
                              metadata !"round.dynamic",

 define <2 x double> @constrained_vector_log10_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_log10_v2f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl log10
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 62, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl log10
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 34, 62, 1
+; PC64LE-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_log10_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    stxv 62, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE9-NEXT:    bl log10
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 62, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl log10
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 34, 62, 1
+; PC64LE9-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log10 = call <2 x double> @llvm.experimental.constrained.log10.v2f64(
                                <2 x double> %x,
                                metadata !"round.dynamic",
                                metadata !"fpexcept.strict") #1
   ret <2 x double> %log10
 }
 
 define <3 x float> @constrained_vector_log10_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_log10_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl log10f
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
-; PC64LE-NEXT:    fmr 31, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl log10f
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE-NEXT:    fmr 30, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl log10f
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xscvdpspn 34, 30
+; PC64LE-NEXT:    xscvdpspn 34, 30 # Vec Defs: V2(VSR34) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI67_0@toc@ha
 ; PC64LE-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    xscvdpspn 35, 1
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI67_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    vmrghw 2, 2, 3
-; PC64LE-NEXT:    xscvdpspn 35, 31
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_log10_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    vmr 31, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    bl log10f
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxswapd 0, 63
-; PC64LE9-NEXT:    fmr 31, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl log10f
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE9-NEXT:    fmr 30, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl log10f
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscvdpspn 34, 1
-; PC64LE9-NEXT:    xscvdpspn 35, 30
+; PC64LE9-NEXT:    xscvdpspn 34, 1 # Vec Defs: V2(VSR34) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 35, 30 # Vec Defs: V3(VSR35) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI67_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    xscvdpspn 36, 31 # Vec Defs: V4(VSR36) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI67_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log10 = call <3 x float> @llvm.experimental.constrained.log10.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %log10
 }
 
 define <3 x double> @constrained_vector_log10_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_log10_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    fmr 31, 3
-; PC64LE-NEXT:    fmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    bl log10
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 63, 1, 1
-; PC64LE-NEXT:    fmr 1, 30
+; PC64LE-NEXT:    xxlor 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    bl log10
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 63, 1, 63
-; PC64LE-NEXT:    fmr 1, 31
+; PC64LE-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    bl log10
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    xxlor 2, 63, 63
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    fmr 3, 1
-; PC64LE-NEXT:    fmr 1, 0
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_log10_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    fmr 31, 3
-; PC64LE9-NEXT:    fmr 30, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE9-NEXT:    bl log10
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 63, 1, 1
-; PC64LE9-NEXT:    fmr 1, 30
+; PC64LE9-NEXT:    xscpsgndp 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    bl log10
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 1, 63
-; PC64LE9-NEXT:    fmr 1, 31
+; PC64LE9-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE9-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    bl log10
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
+; PC64LE9-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log10 = call <3 x double> @llvm.experimental.constrained.log10.v3f64(
                           <3 x double> %x,
                           metadata !"round.dynamic",
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %log10
 }
 
 define <4 x double> @constrained_vector_log10_v4f64(<4 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_log10_v4f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 61, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 80
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 3
-; PC64LE-NEXT:    xxlor 1, 62, 62
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxlor 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE-NEXT:    bl log10
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 62
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl log10
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 62, 61, 1
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl log10
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl log10
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 80
-; PC64LE-NEXT:    vmr 2, 30
+; PC64LE-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 35, 61, 1
+; PC64LE-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 61, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_log10_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
 ; PC64LE9-NEXT:    stxv 62, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 30, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 62, 62
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE9-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE9-NEXT:    stxv 61, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE9-NEXT:    stxv 63, 64(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 3
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE9-NEXT:    bl log10
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 62
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl log10
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 62, 61, 1
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    bl log10
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl log10
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 35, 61, 1
-; PC64LE9-NEXT:    vmr 2, 30
+; PC64LE9-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    lxv 63, 64(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lxv 61, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log10 = call <4 x double> @llvm.experimental.constrained.log10.v4f64(
                                <4 x double> %x,
                                metadata !"round.dynamic",

 define <2 x double> @constrained_vector_log2_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_log2_v2f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl log2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 62, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl log2
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 34, 62, 1
+; PC64LE-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_log2_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    stxv 62, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE9-NEXT:    bl log2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 62, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl log2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 34, 62, 1
+; PC64LE9-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log2 = call <2 x double> @llvm.experimental.constrained.log2.v2f64(
                               <2 x double> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <2 x double> %log2
 }
 
 define <3 x float> @constrained_vector_log2_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_log2_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl log2f
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
-; PC64LE-NEXT:    fmr 31, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl log2f
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE-NEXT:    fmr 30, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl log2f
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xscvdpspn 34, 30
+; PC64LE-NEXT:    xscvdpspn 34, 30 # Vec Defs: V2(VSR34) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI72_0@toc@ha
 ; PC64LE-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    xscvdpspn 35, 1
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI72_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    vmrghw 2, 2, 3
-; PC64LE-NEXT:    xscvdpspn 35, 31
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_log2_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    vmr 31, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    bl log2f
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxswapd 0, 63
-; PC64LE9-NEXT:    fmr 31, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl log2f
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE9-NEXT:    fmr 30, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl log2f
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscvdpspn 34, 1
-; PC64LE9-NEXT:    xscvdpspn 35, 30
+; PC64LE9-NEXT:    xscvdpspn 34, 1 # Vec Defs: V2(VSR34) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 35, 30 # Vec Defs: V3(VSR35) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI72_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    xscvdpspn 36, 31 # Vec Defs: V4(VSR36) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI72_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log2 = call <3 x float> @llvm.experimental.constrained.log2.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %log2
 }
 
 define <3 x double> @constrained_vector_log2_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_log2_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    fmr 31, 3
-; PC64LE-NEXT:    fmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    bl log2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 63, 1, 1
-; PC64LE-NEXT:    fmr 1, 30
+; PC64LE-NEXT:    xxlor 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    bl log2
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 63, 1, 63
-; PC64LE-NEXT:    fmr 1, 31
+; PC64LE-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    bl log2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    xxlor 2, 63, 63
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    fmr 3, 1
-; PC64LE-NEXT:    fmr 1, 0
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_log2_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    fmr 31, 3
-; PC64LE9-NEXT:    fmr 30, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE9-NEXT:    bl log2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 63, 1, 1
-; PC64LE9-NEXT:    fmr 1, 30
+; PC64LE9-NEXT:    xscpsgndp 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    bl log2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 1, 63
-; PC64LE9-NEXT:    fmr 1, 31
+; PC64LE9-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE9-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    bl log2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
+; PC64LE9-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log2 = call <3 x double> @llvm.experimental.constrained.log2.v3f64(
                           <3 x double> %x,
                           metadata !"round.dynamic",
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %log2
 }
 
 define <4 x double> @constrained_vector_log2_v4f64(<4 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_log2_v4f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 61, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 80
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 3
-; PC64LE-NEXT:    xxlor 1, 62, 62
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxlor 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE-NEXT:    bl log2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 62
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl log2
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 62, 61, 1
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl log2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl log2
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 80
-; PC64LE-NEXT:    vmr 2, 30
+; PC64LE-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 35, 61, 1
+; PC64LE-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 61, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_log2_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
 ; PC64LE9-NEXT:    stxv 62, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 30, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 62, 62
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE9-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE9-NEXT:    stxv 61, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE9-NEXT:    stxv 63, 64(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 3
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE9-NEXT:    bl log2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 62
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl log2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 62, 61, 1
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    bl log2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl log2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 35, 61, 1
-; PC64LE9-NEXT:    vmr 2, 30
+; PC64LE9-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    lxv 63, 64(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lxv 61, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log2 = call <4 x double> @llvm.experimental.constrained.log2.v4f64(
                               <4 x double> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <4 x double> %log2
 }
 
 define <1 x float> @constrained_vector_rint_v1f32(<1 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_rint_v1f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xsrdpic 1, 1
+; PC64LE-NEXT:    xsrdpic 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_rint_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xsrdpic 1, 1
+; PC64LE9-NEXT:    xsrdpic 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64LE9-NEXT:    blr
 entry:
   %rint = call <1 x float> @llvm.experimental.constrained.rint.v1f32(
                              <1 x float> %x,
                              metadata !"round.dynamic",
                              metadata !"fpexcept.strict") #1
   ret <1 x float> %rint
 }
 
 define <2 x double> @constrained_vector_rint_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_rint_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvrdpic 34, 34
+; PC64LE-NEXT:    xvrdpic 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_rint_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvrdpic 34, 34
+; PC64LE9-NEXT:    xvrdpic 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %rint = call <2 x double> @llvm.experimental.constrained.rint.v2f64(
                         <2 x double> %x,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #1
   ret <2 x double> %rint
 }
 
 define <3 x float> @constrained_vector_rint_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_rint_v3f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 1, 34
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI77_0@toc@ha
-; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI77_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    xsrdpic 0, 0
-; PC64LE-NEXT:    xsrdpic 1, 1
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    xscvdpspn 35, 1
-; PC64LE-NEXT:    xsrdpic 0, 2
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    xscvdpspn 35, 0
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    xsrdpic 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xsrdpic 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xsrdpic 0, 2 # Vec Defs: F0(VSR0) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_rint_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxswapd 1, 34
-; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3
+; PC64LE9-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI77_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI77_0@toc@l
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 1
-; PC64LE9-NEXT:    xscvspdpn 2, 2
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xsrdpic 1, 1
-; PC64LE9-NEXT:    xsrdpic 2, 2
-; PC64LE9-NEXT:    xsrdpic 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xsrdpic 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xsrdpic 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    xsrdpic 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 34, 2 # Vec Defs: V2(VSR34) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 36, 0 # Vec Defs: V4(VSR36) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
  entry:
   %rint = call <3 x float> @llvm.experimental.constrained.rint.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %rint
 }
 
 define <3 x double> @constrained_vector_rint_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_rint_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 0, 2, 1
-; PC64LE-NEXT:    xsrdpic 3, 3
-; PC64LE-NEXT:    xvrdpic 2, 0
-; PC64LE-NEXT:    xxswapd 1, 2
+; PC64LE-NEXT:    xxmrghd 0, 2, 1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE-NEXT:    xsrdpic 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    xvrdpic 2, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_rint_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 0, 2, 1
-; PC64LE9-NEXT:    xsrdpic 3, 3
-; PC64LE9-NEXT:    xvrdpic 2, 0
-; PC64LE9-NEXT:    xxswapd 1, 2
+; PC64LE9-NEXT:    xxmrghd 0, 2, 1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE9-NEXT:    xsrdpic 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    xvrdpic 2, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    blr
 entry:
   %rint = call <3 x double> @llvm.experimental.constrained.rint.v3f64(
                           <3 x double> %x,
                           metadata !"round.dynamic",
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %rint
 }
 
 define <4 x double> @constrained_vector_rint_v4f64(<4 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_rint_v4f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvrdpic 35, 35
-; PC64LE-NEXT:    xvrdpic 34, 34
+; PC64LE-NEXT:    xvrdpic 35, 35 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)
+; PC64LE-NEXT:    xvrdpic 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_rint_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvrdpic 35, 35
-; PC64LE9-NEXT:    xvrdpic 34, 34
+; PC64LE9-NEXT:    xvrdpic 35, 35 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)
+; PC64LE9-NEXT:    xvrdpic 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %rint = call <4 x double> @llvm.experimental.constrained.rint.v4f64(
                         <4 x double> %x,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #1
   ret <4 x double> %rint
 }

 define <2 x double> @constrained_vector_nearbyint_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_nearbyint_v2f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl nearbyint
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 62, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl nearbyint
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 34, 62, 1
+; PC64LE-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_nearbyint_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    stxv 62, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE9-NEXT:    bl nearbyint
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 62, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 62, 1, 1 # Vec Defs: VF30(VSR30) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl nearbyint
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 34, 62, 1
+; PC64LE9-NEXT:    xxmrghd 34, 62, 1 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)VSL1(VSR1)
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %nearby = call <2 x double> @llvm.experimental.constrained.nearbyint.v2f64(
                                 <2 x double> %x,
                                 metadata !"round.dynamic",
                                 metadata !"fpexcept.strict") #1
   ret <2 x double> %nearby
 }
 
 define <3 x float> @constrained_vector_nearbyint_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_nearbyint_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 2
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl nearbyintf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
-; PC64LE-NEXT:    fmr 31, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl nearbyintf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE-NEXT:    fmr 30, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
+; PC64LE-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE-NEXT:    bl nearbyintf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xscvdpspn 34, 30
+; PC64LE-NEXT:    xscvdpspn 34, 30 # Vec Defs: V2(VSR34) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI82_0@toc@ha
 ; PC64LE-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    xscvdpspn 35, 1
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI82_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    vmrghw 2, 2, 3
-; PC64LE-NEXT:    xscvdpspn 35, 31
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_nearbyint_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    vmr 31, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    vmr 31, 2 # Vec Defs: V31(VSR63) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    bl nearbyintf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxswapd 0, 63
-; PC64LE9-NEXT:    fmr 31, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl nearbyintf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE9-NEXT:    fmr 30, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl nearbyintf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscvdpspn 34, 1
-; PC64LE9-NEXT:    xscvdpspn 35, 30
+; PC64LE9-NEXT:    xscvdpspn 34, 1 # Vec Defs: V2(VSR34) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 35, 30 # Vec Defs: V3(VSR35) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI82_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    xscvdpspn 36, 31 # Vec Defs: V4(VSR36) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI82_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %nearby = call <3 x float> @llvm.experimental.constrained.nearbyint.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %nearby
 }
 
 define <3 x double> @constrained_vector_nearby_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_nearby_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -80(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    fmr 31, 3
-; PC64LE-NEXT:    fmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    bl nearbyint
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 63, 1, 1
-; PC64LE-NEXT:    fmr 1, 30
+; PC64LE-NEXT:    xxlor 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    bl nearbyint
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 63, 1, 63
-; PC64LE-NEXT:    fmr 1, 31
+; PC64LE-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    bl nearbyint
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    xxlor 2, 63, 63
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    fmr 3, 1
-; PC64LE-NEXT:    fmr 1, 0
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_nearby_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    stfd 30, 48(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 56(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    fmr 31, 3
-; PC64LE9-NEXT:    fmr 30, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    fmr 31, 3 # Vec Defs: F31(VSR31) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    fmr 30, 2 # Vec Defs: F30(VSR30) Vec Uses: F2(VSR2)
 ; PC64LE9-NEXT:    bl nearbyint
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 63, 1, 1
-; PC64LE9-NEXT:    fmr 1, 30
+; PC64LE9-NEXT:    xscpsgndp 63, 1, 1 # Vec Defs: VF31(VSR31) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    fmr 1, 30 # Vec Defs: F1(VSR1) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    bl nearbyint
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 1, 63
-; PC64LE9-NEXT:    fmr 1, 31
+; PC64LE9-NEXT:    xxmrghd 63, 1, 63 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)V31(VSR63)
+; PC64LE9-NEXT:    fmr 1, 31 # Vec Defs: F1(VSR1) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    bl nearbyint
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
+; PC64LE9-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %nearby = call <3 x double> @llvm.experimental.constrained.nearbyint.v3f64(
                           <3 x double> %x,
                           metadata !"round.dynamic",
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %nearby
 }
 
 define <4 x double> @constrained_vector_nearbyint_v4f64(<4 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_nearbyint_v4f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 61, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    li 3, 80
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    vmr 31, 3
-; PC64LE-NEXT:    xxlor 1, 62, 62
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xxlor 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE-NEXT:    bl nearbyint
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 62
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl nearbyint
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 62, 61, 1
-; PC64LE-NEXT:    xxlor 1, 63, 63
+; PC64LE-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE-NEXT:    xxlor 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    bl nearbyint
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxlor 61, 1, 1
-; PC64LE-NEXT:    xxswapd 1, 63
+; PC64LE-NEXT:    xxlor 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    bl nearbyint
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    li 3, 80
-; PC64LE-NEXT:    vmr 2, 30
+; PC64LE-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 35, 61, 1
+; PC64LE-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 61, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_nearbyint_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
 ; PC64LE9-NEXT:    stxv 62, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 30, 2
-; PC64LE9-NEXT:    xscpsgndp 1, 62, 62
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE9-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscpsgndp 1, 62, 62 # Vec Defs: F1(VSR1) Vec Uses: VF30(VSR30)VF30(VSR30)
 ; PC64LE9-NEXT:    stxv 61, 32(1) # 16-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: V29(VSR61)
 ; PC64LE9-NEXT:    stxv 63, 64(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    vmr 31, 3
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE9-NEXT:    bl nearbyint
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 62
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 62 # Vec Defs: VSL1(VSR1) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl nearbyint
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 62, 61, 1
-; PC64LE9-NEXT:    xscpsgndp 1, 63, 63
+; PC64LE9-NEXT:    xxmrghd 62, 61, 1 # Vec Defs: V30(VSR62) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    xscpsgndp 1, 63, 63 # Vec Defs: F1(VSR1) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    bl nearbyint
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscpsgndp 61, 1, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
+; PC64LE9-NEXT:    xscpsgndp 61, 1, 1 # Vec Defs: VF29(VSR29) Vec Uses: F1(VSR1)F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    bl nearbyint
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 35, 61, 1
-; PC64LE9-NEXT:    vmr 2, 30
+; PC64LE9-NEXT:    xxmrghd 35, 61, 1 # Vec Defs: V3(VSR35) Vec Uses: V29(VSR61)VSL1(VSR1)
+; PC64LE9-NEXT:    vmr 2, 30 # Vec Defs: V2(VSR34) Vec Uses: V30(VSR62)V30(VSR62)
 ; PC64LE9-NEXT:    lxv 63, 64(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lxv 61, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V29(VSR61)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %nearby = call <4 x double> @llvm.experimental.constrained.nearbyint.v4f64(
                                 <4 x double> %x,
                                 metadata !"round.dynamic",
%max = call <1 x float> @llvm.experimental.constrained.maxnum.v1f32(
                                <1 x float> %x, <1 x float> %y,
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %max
 }
 
 define <2 x double> @constrained_vector_maxnum_v2f64(<2 x double> %x, <2 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_maxnum_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvmaxdp 34, 34, 35
+; PC64LE-NEXT:    xvmaxdp 34, 34, 35 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_maxnum_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvmaxdp 34, 34, 35
+; PC64LE9-NEXT:    xvmaxdp 34, 34, 35 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %max = call <2 x double> @llvm.experimental.constrained.maxnum.v2f64(
                                 <2 x double> %x,
                                 <2 x double> %y,
                                 metadata !"fpexcept.strict") #1
   ret <2 x double> %max
 }
 
 define <3 x float> @constrained_vector_maxnum_v3f32(<3 x float> %x, <3 x float> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_maxnum_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE-NEXT:    xxsldwi 2, 35, 35, 1
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 2, 35, 35, 1 # Vec Defs: VSL2(VSR2) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stfd 30, 80(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 88(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    xscvspdpn 1, 0
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    vmr 31, 3
-; PC64LE-NEXT:    vmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    bl fmaxf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 62
-; PC64LE-NEXT:    xxswapd 2, 63
-; PC64LE-NEXT:    fmr 31, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
-; PC64LE-NEXT:    xscvspdpn 2, 2
+; PC64LE-NEXT:    xxswapd 0, 62 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE-NEXT:    xxswapd 2, 63 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
 ; PC64LE-NEXT:    bl fmaxf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxsldwi 0, 62, 62, 3
-; PC64LE-NEXT:    xxsldwi 2, 63, 63, 3
-; PC64LE-NEXT:    fmr 30, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
-; PC64LE-NEXT:    xscvspdpn 2, 2
+; PC64LE-NEXT:    xxsldwi 0, 62, 62, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE-NEXT:    xxsldwi 2, 63, 63, 3 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
 ; PC64LE-NEXT:    bl fmaxf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xscvdpspn 34, 30
+; PC64LE-NEXT:    xscvdpspn 34, 30 # Vec Defs: V2(VSR34) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI87_0@toc@ha
 ; PC64LE-NEXT:    lfd 30, 80(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    xscvdpspn 35, 1
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI87_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    vmrghw 2, 2, 3
-; PC64LE-NEXT:    xscvdpspn 35, 31
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 88(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_maxnum_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 62, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    xxsldwi 0, 35, 35, 1
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxsldwi 0, 35, 35, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xscvspdpn 2, 0
-; PC64LE9-NEXT:    vmr 31, 3
-; PC64LE9-NEXT:    vmr 30, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 2, 0 # Vec Defs: F2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    bl fmaxf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxswapd 0, 62
-; PC64LE9-NEXT:    fmr 31, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    xxswapd 0, 63
-; PC64LE9-NEXT:    xscvspdpn 2, 0
+; PC64LE9-NEXT:    xxswapd 0, 62 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE9-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 2, 0 # Vec Defs: F2(VSR2) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl fmaxf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxsldwi 0, 62, 62, 3
-; PC64LE9-NEXT:    fmr 30, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE9-NEXT:    xscvspdpn 2, 0
+; PC64LE9-NEXT:    xxsldwi 0, 62, 62, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE9-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 2, 0 # Vec Defs: F2(VSR2) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl fmaxf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscvdpspn 34, 1
-; PC64LE9-NEXT:    xscvdpspn 35, 30
+; PC64LE9-NEXT:    xscvdpspn 34, 1 # Vec Defs: V2(VSR34) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 35, 30 # Vec Defs: V3(VSR35) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI87_0@toc@ha
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI87_0@toc@l
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 31
+; PC64LE9-NEXT:    lxv 36, 0(3) # Vec Defs: V4(VSR36)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE9-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %max = call <3 x float> @llvm.experimental.constrained.maxnum.v3f32(
                               <3 x float> %x,
                               <3 x float> %y,
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %max
 }
 
 define <3 x double> @constrained_vector_max_v3f64(<3 x double> %x, <3 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_max_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -64(1)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
 ; PC64LE-NEXT:    # kill: def $f5 killed $f5 def $vsl5
 ; PC64LE-NEXT:    # kill: def $f4 killed $f4 def $vsl4
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 def $vsl2
-; PC64LE-NEXT:    xxmrghd 0, 5, 4
+; PC64LE-NEXT:    xxmrghd 0, 5, 4 # Vec Defs: VSL0(VSR0) Vec Uses: VSL5(VSR5)VSL4(VSR4)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    xxmrghd 1, 2, 1
+; PC64LE-NEXT:    xxmrghd 1, 2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL1(VSR1)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    fmr 2, 6
-; PC64LE-NEXT:    xvmaxdp 63, 1, 0
-; PC64LE-NEXT:    fmr 1, 3
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    fmr 2, 6 # Vec Defs: F2(VSR2) Vec Uses: F6(VSR6)
+; PC64LE-NEXT:    xvmaxdp 63, 1, 0 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE-NEXT:    fmr 1, 3 # Vec Defs: F1(VSR1) Vec Uses: F3(VSR3)
 ; PC64LE-NEXT:    bl fmax
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    xxlor 2, 63, 63
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    fmr 3, 1
-; PC64LE-NEXT:    fmr 1, 0
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    addi 1, 1, 64
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_max_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -48(1)
 ; PC64LE9-NEXT:    # kill: def $f5 killed $f5 def $vsl5
 ; PC64LE9-NEXT:    # kill: def $f4 killed $f4 def $vsl4
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 0, 5, 4
-; PC64LE9-NEXT:    xxmrghd 1, 2, 1
-; PC64LE9-NEXT:    fmr 2, 6
+; PC64LE9-NEXT:    xxmrghd 0, 5, 4 # Vec Defs: VSL0(VSR0) Vec Uses: VSL5(VSR5)VSL4(VSR4)
+; PC64LE9-NEXT:    xxmrghd 1, 2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE9-NEXT:    fmr 2, 6 # Vec Defs: F2(VSR2) Vec Uses: F6(VSR6)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xvmaxdp 63, 1, 0
-; PC64LE9-NEXT:    fmr 1, 3
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    xvmaxdp 63, 1, 0 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE9-NEXT:    fmr 1, 3 # Vec Defs: F1(VSR1) Vec Uses: F3(VSR3)
 ; PC64LE9-NEXT:    bl fmax
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
+; PC64LE9-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    addi 1, 1, 48
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %max = call <3 x double> @llvm.experimental.constrained.maxnum.v3f64(
                           <3 x double> %x,
                           <3 x double> %y,
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %max
 }
 
 define <4 x double> @constrained_vector_maxnum_v4f64(<4 x double> %x, <4 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_maxnum_v4f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvmaxdp 34, 34, 36
-; PC64LE-NEXT:    xvmaxdp 35, 35, 37
+; PC64LE-NEXT:    xvmaxdp 34, 34, 36 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
+; PC64LE-NEXT:    xvmaxdp 35, 35, 37 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V5(VSR37)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_maxnum_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvmaxdp 34, 34, 36
-; PC64LE9-NEXT:    xvmaxdp 35, 35, 37
+; PC64LE9-NEXT:    xvmaxdp 34, 34, 36 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
+; PC64LE9-NEXT:    xvmaxdp 35, 35, 37 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V5(VSR37)
 ; PC64LE9-NEXT:    blr
 entry:
   %max = call <4 x double> @llvm.experimental.constrained.maxnum.v4f64(
                                 <4 x double> %x,
                                 <4 x double> %y,
                                 metadata !"fpexcept.strict") #1
   ret <4 x double> %max
 }
%min = call <1 x float> @llvm.experimental.constrained.minnum.v1f32(
                                <1 x float> %x, <1 x float> %y,
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %min
 }
 
 define <2 x double> @constrained_vector_minnum_v2f64(<2 x double> %x, <2 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_minnum_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvmindp 34, 34, 35
+; PC64LE-NEXT:    xvmindp 34, 34, 35 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_minnum_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvmindp 34, 34, 35
+; PC64LE9-NEXT:    xvmindp 34, 34, 35 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %min = call <2 x double> @llvm.experimental.constrained.minnum.v2f64(
                                 <2 x double> %x,
                                 <2 x double> %y,
                                 metadata !"fpexcept.strict") #1
   ret <2 x double> %min
 }
 
 define <3 x float> @constrained_vector_minnum_v3f32(<3 x float> %x, <3 x float> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_minnum_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE-NEXT:    xxsldwi 2, 35, 35, 1
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 2, 35, 35, 1 # Vec Defs: VSL2(VSR2) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    stxvd2x 62, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: V30(VSR62)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    stfd 30, 80(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    stfd 31, 88(1) # 8-byte Folded Spill
+; PC64LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    xscvspdpn 1, 0
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    vmr 31, 3
-; PC64LE-NEXT:    vmr 30, 2
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    bl fminf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 62
-; PC64LE-NEXT:    xxswapd 2, 63
-; PC64LE-NEXT:    fmr 31, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
-; PC64LE-NEXT:    xscvspdpn 2, 2
+; PC64LE-NEXT:    xxswapd 0, 62 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE-NEXT:    xxswapd 2, 63 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
 ; PC64LE-NEXT:    bl fminf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxsldwi 0, 62, 62, 3
-; PC64LE-NEXT:    xxsldwi 2, 63, 63, 3
-; PC64LE-NEXT:    fmr 30, 1
-; PC64LE-NEXT:    xscvspdpn 1, 0
-; PC64LE-NEXT:    xscvspdpn 2, 2
+; PC64LE-NEXT:    xxsldwi 0, 62, 62, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE-NEXT:    xxsldwi 2, 63, 63, 3 # Vec Defs: VSL2(VSR2) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
 ; PC64LE-NEXT:    bl fminf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xscvdpspn 34, 30
+; PC64LE-NEXT:    xscvdpspn 34, 30 # Vec Defs: V2(VSR34) Vec Uses: F30(VSR30)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI92_0@toc@ha
 ; PC64LE-NEXT:    lfd 30, 80(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    xscvdpspn 35, 1
+; PC64LE-NEXT:    # Vec Defs: F30(VSR30)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI92_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
 ; PC64LE-NEXT:    li 3, 64
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
 ; PC64LE-NEXT:    lxvd2x 62, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    vmrghw 2, 2, 3
-; PC64LE-NEXT:    xscvdpspn 35, 31
+; PC64LE-NEXT:    # Vec Defs: V30(VSR62)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE-NEXT:    lfd 31, 88(1) # 8-byte Folded Reload
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    addi 1, 1, 96
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_minnum_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -80(1)
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    stfd 30, 64(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    stfd 31, 72(1) # 8-byte Folded Spill
+; PC64LE9-NEXT:    # Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    stxv 62, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    xxsldwi 0, 35, 35, 1
+; PC64LE9-NEXT:    # Vec Uses: V30(VSR62)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxsldwi 0, 35, 35, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
 ; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xscvspdpn 2, 0
-; PC64LE9-NEXT:    vmr 31, 3
-; PC64LE9-NEXT:    vmr 30, 2
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 2, 0 # Vec Defs: F2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    vmr 31, 3 # Vec Defs: V31(VSR63) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    vmr 30, 2 # Vec Defs: V30(VSR62) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    bl fminf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxswapd 0, 62
-; PC64LE9-NEXT:    fmr 31, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    xxswapd 0, 63
-; PC64LE9-NEXT:    xscvspdpn 2, 0
+; PC64LE9-NEXT:    xxswapd 0, 62 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE9-NEXT:    fmr 31, 1 # Vec Defs: F31(VSR31) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 2, 0 # Vec Defs: F2(VSR2) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl fminf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xxsldwi 0, 62, 62, 3
-; PC64LE9-NEXT:    fmr 30, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 0
-; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
-; PC64LE9-NEXT:    xscvspdpn 2, 0
+; PC64LE9-NEXT:    xxsldwi 0, 62, 62, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V30(VSR62)V30(VSR62)
+; PC64LE9-NEXT:    fmr 30, 1 # Vec Defs: F30(VSR30) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscvspdpn 2, 0 # Vec Defs: F2(VSR2) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    bl fminf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    xscvdpspn 34, 1
-; PC64LE9-NEXT:    xscvdpspn 35, 30
+; PC64LE9-NEXT:    xscvdpspn 34, 1 # Vec Defs: V2(VSR34) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 35, 30 # Vec Defs: V3(VSR35) Vec Uses: F30(VSR30)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI92_0@toc@ha
 ; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V30(VSR62)
 ; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: F30(VSR30)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI92_0@toc@l
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 31
+; PC64LE9-NEXT:    lxv 36, 0(3) # Vec Defs: V4(VSR36)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    xscvdpspn 35, 31 # Vec Defs: V3(VSR35) Vec Uses: F31(VSR31)
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    # Vec Defs: F31(VSR31)
+; PC64LE9-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %min = call <3 x float> @llvm.experimental.constrained.minnum.v3f32(
                               <3 x float> %x,
                               <3 x float> %y,
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %min
 }
 
 define <3 x double> @constrained_vector_min_v3f64(<3 x double> %x, <3 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_min_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -64(1)
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
 ; PC64LE-NEXT:    # kill: def $f5 killed $f5 def $vsl5
 ; PC64LE-NEXT:    # kill: def $f4 killed $f4 def $vsl4
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 def $vsl2
-; PC64LE-NEXT:    xxmrghd 0, 5, 4
+; PC64LE-NEXT:    xxmrghd 0, 5, 4 # Vec Defs: VSL0(VSR0) Vec Uses: VSL5(VSR5)VSL4(VSR4)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    xxmrghd 1, 2, 1
+; PC64LE-NEXT:    xxmrghd 1, 2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL1(VSR1)
 ; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    fmr 2, 6
-; PC64LE-NEXT:    xvmindp 63, 1, 0
-; PC64LE-NEXT:    fmr 1, 3
+; PC64LE-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE-NEXT:    fmr 2, 6 # Vec Defs: F2(VSR2) Vec Uses: F6(VSR6)
+; PC64LE-NEXT:    xvmindp 63, 1, 0 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE-NEXT:    fmr 1, 3 # Vec Defs: F1(VSR1) Vec Uses: F3(VSR3)
 ; PC64LE-NEXT:    bl fmin
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
+; PC64LE-NEXT:    xxswapd 0, 63 # Vec Defs: VSL0(VSR0) Vec Uses: V31(VSR63)V31(VSR63)
 ; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    xxlor 2, 63, 63
+; PC64LE-NEXT:    xxlor 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    fmr 3, 1
-; PC64LE-NEXT:    fmr 1, 0
+; PC64LE-NEXT:    # Vec Defs: V31(VSR63)
+; PC64LE-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    fmr 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    addi 1, 1, 64
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_min_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -48(1)
 ; PC64LE9-NEXT:    # kill: def $f5 killed $f5 def $vsl5
 ; PC64LE9-NEXT:    # kill: def $f4 killed $f4 def $vsl4
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 0, 5, 4
-; PC64LE9-NEXT:    xxmrghd 1, 2, 1
-; PC64LE9-NEXT:    fmr 2, 6
+; PC64LE9-NEXT:    xxmrghd 0, 5, 4 # Vec Defs: VSL0(VSR0) Vec Uses: VSL5(VSR5)VSL4(VSR4)
+; PC64LE9-NEXT:    xxmrghd 1, 2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE9-NEXT:    fmr 2, 6 # Vec Defs: F2(VSR2) Vec Uses: F6(VSR6)
 ; PC64LE9-NEXT:    stxv 63, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    xvmindp 63, 1, 0
-; PC64LE9-NEXT:    fmr 1, 3
+; PC64LE9-NEXT:    # Vec Uses: V31(VSR63)
+; PC64LE9-NEXT:    xvmindp 63, 1, 0 # Vec Defs: V31(VSR63) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE9-NEXT:    fmr 1, 3 # Vec Defs: F1(VSR1) Vec Uses: F3(VSR3)
 ; PC64LE9-NEXT:    bl fmin
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
+; PC64LE9-NEXT:    fmr 3, 1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxswapd 1, 63 # Vec Defs: VSL1(VSR1) Vec Uses: V31(VSR63)V31(VSR63)
+; PC64LE9-NEXT:    xscpsgndp 2, 63, 63 # Vec Defs: F2(VSR2) Vec Uses: VF31(VSR31)VF31(VSR31)
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    # Vec Defs: V31(VSR63)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    addi 1, 1, 48
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
  %min = call <3 x double> @llvm.experimental.constrained.minnum.v3f64(
                           <3 x double> %x,
                           <3 x double> %y,
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %min
 }
 
 define <4 x double> @constrained_vector_minnum_v4f64(<4 x double> %x, <4 x double> %y) #0 {
 ; PC64LE-LABEL: constrained_vector_minnum_v4f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvmindp 34, 34, 36
-; PC64LE-NEXT:    xvmindp 35, 35, 37
+; PC64LE-NEXT:    xvmindp 34, 34, 36 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
+; PC64LE-NEXT:    xvmindp 35, 35, 37 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V5(VSR37)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_minnum_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvmindp 34, 34, 36
-; PC64LE9-NEXT:    xvmindp 35, 35, 37
+; PC64LE9-NEXT:    xvmindp 34, 34, 36 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
+; PC64LE9-NEXT:    xvmindp 35, 35, 37 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V5(VSR37)
 ; PC64LE9-NEXT:    blr
 entry:
   %min = call <4 x double> @llvm.experimental.constrained.minnum.v4f64(
                                 <4 x double> %x,
                                 <4 x double> %y,
                                 metadata !"fpexcept.strict") #1
   ret <4 x double> %min
 }
 
 define <1 x i32> @constrained_vector_fptosi_v1i32_v1f32(<1 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptosi_v1i32_v1f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xscvdpsxws 0, 1
-; PC64LE-NEXT:    mffprwz 3, 0
+; PC64LE-NEXT:    xscvdpsxws 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v1i32_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xscvdpsxws 0, 1
-; PC64LE9-NEXT:    mffprwz 3, 0
+; PC64LE9-NEXT:    xscvdpsxws 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x i32> @llvm.experimental.constrained.fptosi.v1i32.v1f32(
                                <1 x float> %x,
                                metadata !"fpexcept.strict") #0
   ret <1 x i32> %result
 }
 
 define <2 x i32> @constrained_vector_fptosi_v2i32_v2f32(<2 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptosi_v2i32_v2f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 1, 34
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvdpsxws 0, 0
-; PC64LE-NEXT:    xscvdpsxws 1, 1
-; PC64LE-NEXT:    mffprwz 3, 0
-; PC64LE-NEXT:    mffprwz 4, 1
-; PC64LE-NEXT:    mtvsrwz 34, 3
-; PC64LE-NEXT:    mtvsrwz 35, 4
-; PC64LE-NEXT:    vmrghw 2, 3, 2
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvdpsxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpsxws 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtvsrwz 34, 3 # Vec Defs: VF2(VSR2)
+; PC64LE-NEXT:    mtvsrwz 35, 4 # Vec Defs: VF3(VSR3)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v2i32_v2f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpsxws 0, 0
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 34
-; PC64LE9-NEXT:    mtvsrwz 35, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpsxws 0, 0
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    mtvsrwz 34, 3
-; PC64LE9-NEXT:    vmrghw 2, 2, 3
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtvsrwz 34, 3 # Vec Defs: VF2(VSR2)
+; PC64LE9-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x i32> @llvm.experimental.constrained.fptosi.v2i32.v2f32(
                                 <2 x float> %x,
                                 metadata !"fpexcept.strict") #0
   ret <2 x i32> %result
 }
 
 define <3 x i32> @constrained_vector_fptosi_v3i32_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptosi_v3i32_v3f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 1, 34
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI97_0@toc@ha
-; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI97_0@toc@l
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    xscvdpsxws 0, 0
-; PC64LE-NEXT:    xscvdpsxws 1, 1
-; PC64LE-NEXT:    xscvdpsxws 2, 2
-; PC64LE-NEXT:    mffprwz 4, 0
-; PC64LE-NEXT:    mffprwz 5, 1
-; PC64LE-NEXT:    mtvsrwz 34, 4
-; PC64LE-NEXT:    mtvsrwz 35, 5
-; PC64LE-NEXT:    mffprwz 4, 2
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    lvx 3, 0, 3
-; PC64LE-NEXT:    mtvsrwz 36, 4
-; PC64LE-NEXT:    vperm 2, 4, 2, 3
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    xscvdpsxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpsxws 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpsxws 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    mffprwz 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 5, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtvsrwz 34, 4 # Vec Defs: VF2(VSR2)
+; PC64LE-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; PC64LE-NEXT:    mffprwz 4, 2 # Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    lvx 3, 0, 3 # Vec Defs: V3(VSR35)
+; PC64LE-NEXT:    mtvsrwz 36, 4 # Vec Defs: VF4(VSR4)
+; PC64LE-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v3i32_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpsxws 0, 0
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 34
-; PC64LE9-NEXT:    mtvsrwz 35, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpsxws 0, 0
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE9-NEXT:    mtvsrwz 36, 3
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    mtvsrwz 36, 3 # Vec Defs: VF4(VSR4)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI97_0@toc@ha
-; PC64LE9-NEXT:    xscvspdpn 0, 0
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI97_0@toc@l
-; PC64LE9-NEXT:    vmrghw 3, 4, 3
-; PC64LE9-NEXT:    xscvdpsxws 0, 0
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    mtvsrwz 34, 3
-; PC64LE9-NEXT:    vperm 2, 2, 3, 4
+; PC64LE9-NEXT:    vmrghw 3, 4, 3 # Vec Defs: V3(VSR35) Vec Uses: V4(VSR36)V3(VSR35)
+; PC64LE9-NEXT:    xscvdpsxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    lxv 36, 0(3) # Vec Defs: V4(VSR36)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtvsrwz 34, 3 # Vec Defs: VF2(VSR2)
+; PC64LE9-NEXT:    vperm 2, 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)V4(VSR36)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x i32> @llvm.experimental.constrained.fptosi.v3i32.v3f32(
                                 <3 x float> %x,
                                 metadata !"fpexcept.strict") #0
   ret <3 x i32> %result
 }
 
 define <4 x i32> @constrained_vector_fptosi_v4i32_v4f32(<4 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptosi_v4i32_v4f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvcvspsxws 34, 34
+; PC64LE-NEXT:    xvcvspsxws 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v4i32_v4f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvcvspsxws 34, 34
+; PC64LE9-NEXT:    xvcvspsxws 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x i32> @llvm.experimental.constrained.fptosi.v4i32.v4f32(
                                 <4 x float> %x,
                                 metadata !"fpexcept.strict") #0
   ret <4 x i32> %result
 }
 
 define <1 x i64> @constrained_vector_fptosi_v1i64_v1f32(<1 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptosi_v1i64_v1f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xscvdpsxds 0, 1
-; PC64LE-NEXT:    mffprd 3, 0
+; PC64LE-NEXT:    xscvdpsxds 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v1i64_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xscvdpsxds 0, 1
-; PC64LE9-NEXT:    mffprd 3, 0
+; PC64LE9-NEXT:    xscvdpsxds 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x i64> @llvm.experimental.constrained.fptosi.v1i64.v1f32(
                                <1 x float> %x,
                                metadata !"fpexcept.strict") #0
   ret <1 x i64> %result
 }
 
 define <2 x i64> @constrained_vector_fptosi_v2i64_v2f32(<2 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptosi_v2i64_v2f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 1, 34
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvdpsxds 0, 0
-; PC64LE-NEXT:    xscvdpsxds 1, 1
-; PC64LE-NEXT:    mffprd 3, 0
-; PC64LE-NEXT:    mffprd 4, 1
-; PC64LE-NEXT:    mtfprd 0, 3
-; PC64LE-NEXT:    mtfprd 1, 4
-; PC64LE-NEXT:    xxmrghd 34, 1, 0
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvdpsxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpsxds 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprd 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprd 1, 4 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    xxmrghd 34, 1, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL1(VSR1)VSL0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v2i64_v2f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpsxds 0, 0
-; PC64LE9-NEXT:    mffprd 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 34
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpsxds 0, 0
-; PC64LE9-NEXT:    mffprd 4, 0
-; PC64LE9-NEXT:    mtvsrdd 34, 4, 3
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtvsrdd 34, 4, 3 # Vec Defs: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f32(
                                 <2 x float> %x,
                                 metadata !"fpexcept.strict") #0
   ret <2 x i64> %result
 }
 
 define <3 x i64> @constrained_vector_fptosi_v3i64_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptosi_v3i64_v3f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 1, 34
-; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    xscvdpsxds 0, 0
-; PC64LE-NEXT:    xscvdpsxds 1, 1
-; PC64LE-NEXT:    xscvdpsxds 2, 2
-; PC64LE-NEXT:    mffprd 3, 0
-; PC64LE-NEXT:    mffprd 4, 1
-; PC64LE-NEXT:    mffprd 5, 2
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    xscvdpsxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpsxds 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpsxds 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprd 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprd 5, 2 # Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v3i64_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpsxds 0, 0
-; PC64LE9-NEXT:    mffprd 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 34
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpsxds 0, 0
-; PC64LE9-NEXT:    mffprd 4, 0
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpsxds 0, 0
-; PC64LE9-NEXT:    mffprd 5, 0
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 5, 0 # Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x i64> @llvm.experimental.constrained.fptosi.v3i64.v3f32(
                                 <3 x float> %x,
                                 metadata !"fpexcept.strict") #0
   ret <3 x i64> %result
 }
 
 define <4 x i64> @constrained_vector_fptosi_v4i64_v4f32(<4 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptosi_v4i64_v4f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xscvspdpn 1, 34
-; PC64LE-NEXT:    xxswapd 2, 34
-; PC64LE-NEXT:    xxsldwi 3, 34, 34, 1
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    xscvspdpn 3, 3
-; PC64LE-NEXT:    xscvdpsxds 1, 1
-; PC64LE-NEXT:    xscvdpsxds 0, 0
-; PC64LE-NEXT:    xscvdpsxds 2, 2
-; PC64LE-NEXT:    xscvdpsxds 3, 3
-; PC64LE-NEXT:    mffprd 3, 1
-; PC64LE-NEXT:    mtfprd 1, 3
-; PC64LE-NEXT:    mffprd 3, 0
-; PC64LE-NEXT:    mffprd 4, 2
-; PC64LE-NEXT:    mtfprd 0, 3
-; PC64LE-NEXT:    mffprd 3, 3
-; PC64LE-NEXT:    mtfprd 2, 4
-; PC64LE-NEXT:    mtfprd 3, 3
-; PC64LE-NEXT:    xxmrghd 34, 2, 0
-; PC64LE-NEXT:    xxmrghd 35, 1, 3
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 1, 34 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; PC64LE-NEXT:    xxswapd 2, 34 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 3, 34, 34, 1 # Vec Defs: VSL3(VSR3) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    xscvspdpn 3, 3 # Vec Defs: F3(VSR3) Vec Uses: VSL3(VSR3)
+; PC64LE-NEXT:    xscvdpsxds 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpsxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpsxds 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xscvdpsxds 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    mffprd 3, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprd 1, 3 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprd 4, 2 # Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mffprd 3, 3 # Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    mtfprd 2, 4 # Vec Defs: F2(VSR2)
+; PC64LE-NEXT:    mtfprd 3, 3 # Vec Defs: F3(VSR3)
+; PC64LE-NEXT:    xxmrghd 34, 2, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL2(VSR2)VSL0(VSR0)
+; PC64LE-NEXT:    xxmrghd 35, 1, 3 # Vec Defs: V3(VSR35) Vec Uses: VSL1(VSR1)VSL3(VSR3)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v4i64_v4f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpsxds 0, 0
-; PC64LE9-NEXT:    mffprd 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 34
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpsxds 0, 0
-; PC64LE9-NEXT:    mffprd 4, 0
-; PC64LE9-NEXT:    xscvspdpn 0, 34
-; PC64LE9-NEXT:    mtvsrdd 36, 4, 3
-; PC64LE9-NEXT:    xscvdpsxds 0, 0
-; PC64LE9-NEXT:    mffprd 3, 0
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE9-NEXT:    vmr 2, 4
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpsxds 0, 0
-; PC64LE9-NEXT:    mffprd 4, 0
-; PC64LE9-NEXT:    mtvsrdd 35, 3, 4
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvspdpn 0, 34 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    mtvsrdd 36, 4, 3 # Vec Defs: V4(VSR36)
+; PC64LE9-NEXT:    xscvdpsxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    vmr 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V4(VSR36)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtvsrdd 35, 3, 4 # Vec Defs: V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x i64> @llvm.experimental.constrained.fptosi.v4i64.v4f32(
                                 <4 x float> %x,
                                 metadata !"fpexcept.strict") #0
   ret <4 x i64> %result
 }
 
 define <1 x i32> @constrained_vector_fptosi_v1i32_v1f64(<1 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptosi_v1i32_v1f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xscvdpsxws 0, 1
-; PC64LE-NEXT:    mffprwz 3, 0
+; PC64LE-NEXT:    xscvdpsxws 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v1i32_v1f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xscvdpsxws 0, 1
-; PC64LE9-NEXT:    mffprwz 3, 0
+; PC64LE9-NEXT:    xscvdpsxws 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x i32> @llvm.experimental.constrained.fptosi.v1i32.v1f64(
                                <1 x double> %x,
                                metadata !"fpexcept.strict") #0
   ret <1 x i32> %result
 }
 
 
 define <2 x i32> @constrained_vector_fptosi_v2i32_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptosi_v2i32_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    xscvdpsxws 1, 34
-; PC64LE-NEXT:    xscvdpsxws 0, 0
-; PC64LE-NEXT:    mffprwz 3, 1
-; PC64LE-NEXT:    mtvsrwz 34, 3
-; PC64LE-NEXT:    mffprwz 4, 0
-; PC64LE-NEXT:    mtvsrwz 35, 4
-; PC64LE-NEXT:    vmrghw 2, 2, 3
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvdpsxws 1, 34 # Vec Defs: F1(VSR1) Vec Uses: VF2(VSR2)
+; PC64LE-NEXT:    xscvdpsxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 3, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtvsrwz 34, 3 # Vec Defs: VF2(VSR2)
+; PC64LE-NEXT:    mffprwz 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mtvsrwz 35, 4 # Vec Defs: VF3(VSR3)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v2i32_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xscvdpsxws 0, 34
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 34
-; PC64LE9-NEXT:    mtvsrwz 35, 3
-; PC64LE9-NEXT:    xscvdpsxws 0, 0
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    mtvsrwz 34, 3
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
+; PC64LE9-NEXT:    xscvdpsxws 0, 34 # Vec Defs: F0(VSR0) Vec Uses: VF2(VSR2)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; PC64LE9-NEXT:    xscvdpsxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtvsrwz 34, 3 # Vec Defs: VF2(VSR2)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x i32> @llvm.experimental.constrained.fptosi.v2i32.v2f64(
                                 <2 x double> %x,
                                 metadata !"fpexcept.strict") #0
   ret <2 x i32> %result
 }
 
 define <3 x i32> @constrained_vector_fptosi_v3i32_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptosi_v3i32_v3f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xscvdpsxws 0, 1
+; PC64LE-NEXT:    xscvdpsxws 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI105_0@toc@ha
-; PC64LE-NEXT:    xscvdpsxws 1, 2
+; PC64LE-NEXT:    xscvdpsxws 1, 2 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI105_0@toc@l
-; PC64LE-NEXT:    xscvdpsxws 2, 3
-; PC64LE-NEXT:    mffprwz 4, 0
-; PC64LE-NEXT:    mffprwz 5, 1
-; PC64LE-NEXT:    mtvsrwz 34, 4
-; PC64LE-NEXT:    mtvsrwz 35, 5
-; PC64LE-NEXT:    mffprwz 4, 2
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    lvx 3, 0, 3
-; PC64LE-NEXT:    mtvsrwz 36, 4
-; PC64LE-NEXT:    vperm 2, 4, 2, 3
+; PC64LE-NEXT:    xscvdpsxws 2, 3 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    mffprwz 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 5, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtvsrwz 34, 4 # Vec Defs: VF2(VSR2)
+; PC64LE-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; PC64LE-NEXT:    mffprwz 4, 2 # Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    lvx 3, 0, 3 # Vec Defs: V3(VSR35)
+; PC64LE-NEXT:    mtvsrwz 36, 4 # Vec Defs: VF4(VSR4)
+; PC64LE-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v3i32_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xscvdpsxws 0, 1
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xscvdpsxws 0, 2
-; PC64LE9-NEXT:    mtvsrwz 34, 3
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xscvdpsxws 0, 3
-; PC64LE9-NEXT:    mtvsrwz 35, 3
+; PC64LE9-NEXT:    xscvdpsxws 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxws 0, 2 # Vec Defs: F0(VSR0) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    mtvsrwz 34, 3 # Vec Defs: VF2(VSR2)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxws 0, 3 # Vec Defs: F0(VSR0) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI105_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI105_0@toc@l
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    mtvsrwz 36, 3
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtvsrwz 36, 3 # Vec Defs: VF4(VSR4)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x i32> @llvm.experimental.constrained.fptosi.v3i32.v3f64(
                                 <3 x double> %x,
                                 metadata !"fpexcept.strict") #0
   ret <3 x i32> %result
 }
 
 define <4 x i32> @constrained_vector_fptosi_v4i32_v4f64(<4 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptosi_v4i32_v4f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    xxswapd 2, 35
-; PC64LE-NEXT:    xscvdpsxws 1, 34
-; PC64LE-NEXT:    xscvdpsxws 3, 35
-; PC64LE-NEXT:    xscvdpsxws 0, 0
-; PC64LE-NEXT:    xscvdpsxws 2, 2
-; PC64LE-NEXT:    mffprwz 3, 1
-; PC64LE-NEXT:    mffprwz 4, 3
-; PC64LE-NEXT:    mffprwz 5, 0
-; PC64LE-NEXT:    mffprwz 6, 2
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 2, 35 # Vec Defs: VSL2(VSR2) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xscvdpsxws 1, 34 # Vec Defs: F1(VSR1) Vec Uses: VF2(VSR2)
+; PC64LE-NEXT:    xscvdpsxws 3, 35 # Vec Defs: F3(VSR3) Vec Uses: VF3(VSR3)
+; PC64LE-NEXT:    xscvdpsxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpsxws 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    mffprwz 3, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprwz 4, 3 # Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    mffprwz 5, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 6, 2 # Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    rldimi 5, 3, 32, 0
 ; PC64LE-NEXT:    rldimi 6, 4, 32, 0
-; PC64LE-NEXT:    mtfprd 0, 5
-; PC64LE-NEXT:    mtfprd 1, 6
-; PC64LE-NEXT:    xxmrghd 34, 1, 0
+; PC64LE-NEXT:    mtfprd 0, 5 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprd 1, 6 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    xxmrghd 34, 1, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL1(VSR1)VSL0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v4i32_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xscvdpsxws 0, 34
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 34
-; PC64LE9-NEXT:    xscvdpsxws 0, 0
-; PC64LE9-NEXT:    mffprwz 4, 0
-; PC64LE9-NEXT:    xscvdpsxws 0, 35
+; PC64LE9-NEXT:    xscvdpsxws 0, 34 # Vec Defs: F0(VSR0) Vec Uses: VF2(VSR2)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvdpsxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprwz 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxws 0, 35 # Vec Defs: F0(VSR0) Vec Uses: VF3(VSR3)
 ; PC64LE9-NEXT:    rldimi 4, 3, 32, 0
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 35
-; PC64LE9-NEXT:    xscvdpsxws 0, 0
-; PC64LE9-NEXT:    mffprwz 5, 0
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 35 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    xscvdpsxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprwz 5, 0 # Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    rldimi 5, 3, 32, 0
-; PC64LE9-NEXT:    mtvsrdd 34, 5, 4
+; PC64LE9-NEXT:    mtvsrdd 34, 5, 4 # Vec Defs: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x i32> @llvm.experimental.constrained.fptosi.v4i32.v4f64(
                                 <4 x double> %x,
                                 metadata !"fpexcept.strict") #0
   ret <4 x i32> %result
 }
 
 define <1 x i64> @constrained_vector_fptosi_v1i64_v1f64(<1 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptosi_v1i64_v1f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xscvdpsxds 0, 1
-; PC64LE-NEXT:    mffprd 3, 0
+; PC64LE-NEXT:    xscvdpsxds 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v1i64_v1f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xscvdpsxds 0, 1
-; PC64LE9-NEXT:    mffprd 3, 0
+; PC64LE9-NEXT:    xscvdpsxds 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x i64> @llvm.experimental.constrained.fptosi.v1i64.v1f64(
                                <1 x double> %x,
                                metadata !"fpexcept.strict") #0
   ret <1 x i64> %result
 }
 
 define <2 x i64> @constrained_vector_fptosi_v2i64_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptosi_v2i64_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvcvdpsxds 34, 34
+; PC64LE-NEXT:    xvcvdpsxds 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v2i64_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvcvdpsxds 34, 34
+; PC64LE9-NEXT:    xvcvdpsxds 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f64(
                                 <2 x double> %x,
                                 metadata !"fpexcept.strict") #0
   ret <2 x i64> %result
 }
 
 define <3 x i64> @constrained_vector_fptosi_v3i64_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptosi_v3i64_v3f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xscvdpsxds 0, 1
-; PC64LE-NEXT:    xscvdpsxds 1, 2
-; PC64LE-NEXT:    xscvdpsxds 2, 3
-; PC64LE-NEXT:    mffprd 3, 0
-; PC64LE-NEXT:    mffprd 4, 1
-; PC64LE-NEXT:    mffprd 5, 2
+; PC64LE-NEXT:    xscvdpsxds 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpsxds 1, 2 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xscvdpsxds 2, 3 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprd 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprd 5, 2 # Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v3i64_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xscvdpsxds 0, 1
-; PC64LE9-NEXT:    mffprd 3, 0
-; PC64LE9-NEXT:    xscvdpsxds 0, 2
-; PC64LE9-NEXT:    mffprd 4, 0
-; PC64LE9-NEXT:    xscvdpsxds 0, 3
-; PC64LE9-NEXT:    mffprd 5, 0
+; PC64LE9-NEXT:    xscvdpsxds 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxds 0, 2 # Vec Defs: F0(VSR0) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    mffprd 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpsxds 0, 3 # Vec Defs: F0(VSR0) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    mffprd 5, 0 # Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x i64> @llvm.experimental.constrained.fptosi.v3i64.v3f64(
                                 <3 x double> %x,
                                 metadata !"fpexcept.strict") #0
   ret <3 x i64> %result
 }
 
 define <4 x i64> @constrained_vector_fptosi_v4i64_v4f64(<4 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptosi_v4i64_v4f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvcvdpsxds 35, 35
-; PC64LE-NEXT:    xvcvdpsxds 34, 34
+; PC64LE-NEXT:    xvcvdpsxds 35, 35 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)
+; PC64LE-NEXT:    xvcvdpsxds 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v4i64_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvcvdpsxds 35, 35
-; PC64LE9-NEXT:    xvcvdpsxds 34, 34
+; PC64LE9-NEXT:    xvcvdpsxds 35, 35 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)
+; PC64LE9-NEXT:    xvcvdpsxds 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x i64> @llvm.experimental.constrained.fptosi.v4i64.v4f64(
                                 <4 x double> %x,
                                 metadata !"fpexcept.strict") #0
   ret <4 x i64> %result
 }
 
 define <1 x i32> @constrained_vector_fptoui_v1i32_v1f32(<1 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptoui_v1i32_v1f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xscvdpuxws 0, 1
-; PC64LE-NEXT:    mffprwz 3, 0
+; PC64LE-NEXT:    xscvdpuxws 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v1i32_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xscvdpuxws 0, 1
-; PC64LE9-NEXT:    mffprwz 3, 0
+; PC64LE9-NEXT:    xscvdpuxws 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x i32> @llvm.experimental.constrained.fptoui.v1i32.v1f32(
                                <1 x float> %x,
                                metadata !"fpexcept.strict") #0
   ret <1 x i32> %result
 }
 
 define <2 x i32> @constrained_vector_fptoui_v2i32_v2f32(<2 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptoui_v2i32_v2f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 1, 34
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvdpuxws 0, 0
-; PC64LE-NEXT:    xscvdpuxws 1, 1
-; PC64LE-NEXT:    mffprwz 3, 0
-; PC64LE-NEXT:    mffprwz 4, 1
-; PC64LE-NEXT:    mtvsrwz 34, 3
-; PC64LE-NEXT:    mtvsrwz 35, 4
-; PC64LE-NEXT:    vmrghw 2, 3, 2
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvdpuxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpuxws 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtvsrwz 34, 3 # Vec Defs: VF2(VSR2)
+; PC64LE-NEXT:    mtvsrwz 35, 4 # Vec Defs: VF3(VSR3)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v2i32_v2f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpuxws 0, 0
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 34
-; PC64LE9-NEXT:    mtvsrwz 35, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpuxws 0, 0
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    mtvsrwz 34, 3
-; PC64LE9-NEXT:    vmrghw 2, 2, 3
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtvsrwz 34, 3 # Vec Defs: VF2(VSR2)
+; PC64LE9-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x i32> @llvm.experimental.constrained.fptoui.v2i32.v2f32(
                                 <2 x float> %x,
                                 metadata !"fpexcept.strict") #0
   ret <2 x i32> %result
 }
 
 define <3 x i32> @constrained_vector_fptoui_v3i32_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptoui_v3i32_v3f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 1, 34
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI113_0@toc@ha
-; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI113_0@toc@l
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    xscvdpuxws 0, 0
-; PC64LE-NEXT:    xscvdpuxws 1, 1
-; PC64LE-NEXT:    xscvdpuxws 2, 2
-; PC64LE-NEXT:    mffprwz 4, 0
-; PC64LE-NEXT:    mffprwz 5, 1
-; PC64LE-NEXT:    mtvsrwz 34, 4
-; PC64LE-NEXT:    mtvsrwz 35, 5
-; PC64LE-NEXT:    mffprwz 4, 2
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    lvx 3, 0, 3
-; PC64LE-NEXT:    mtvsrwz 36, 4
-; PC64LE-NEXT:    vperm 2, 4, 2, 3
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    xscvdpuxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpuxws 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpuxws 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    mffprwz 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 5, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtvsrwz 34, 4 # Vec Defs: VF2(VSR2)
+; PC64LE-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; PC64LE-NEXT:    mffprwz 4, 2 # Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    lvx 3, 0, 3 # Vec Defs: V3(VSR35)
+; PC64LE-NEXT:    mtvsrwz 36, 4 # Vec Defs: VF4(VSR4)
+; PC64LE-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v3i32_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpuxws 0, 0
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 34
-; PC64LE9-NEXT:    mtvsrwz 35, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpuxws 0, 0
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE9-NEXT:    mtvsrwz 36, 3
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    mtvsrwz 36, 3 # Vec Defs: VF4(VSR4)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI113_0@toc@ha
-; PC64LE9-NEXT:    xscvspdpn 0, 0
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI113_0@toc@l
-; PC64LE9-NEXT:    vmrghw 3, 4, 3
-; PC64LE9-NEXT:    xscvdpuxws 0, 0
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    mtvsrwz 34, 3
-; PC64LE9-NEXT:    vperm 2, 2, 3, 4
+; PC64LE9-NEXT:    vmrghw 3, 4, 3 # Vec Defs: V3(VSR35) Vec Uses: V4(VSR36)V3(VSR35)
+; PC64LE9-NEXT:    xscvdpuxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    lxv 36, 0(3) # Vec Defs: V4(VSR36)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtvsrwz 34, 3 # Vec Defs: VF2(VSR2)
+; PC64LE9-NEXT:    vperm 2, 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)V4(VSR36)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x i32> @llvm.experimental.constrained.fptoui.v3i32.v3f32(
                                 <3 x float> %x,
                                 metadata !"fpexcept.strict") #0
   ret <3 x i32> %result
 }
 
 define <4 x i32> @constrained_vector_fptoui_v4i32_v4f32(<4 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptoui_v4i32_v4f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvcvspuxws 34, 34
+; PC64LE-NEXT:    xvcvspuxws 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v4i32_v4f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvcvspuxws 34, 34
+; PC64LE9-NEXT:    xvcvspuxws 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x i32> @llvm.experimental.constrained.fptoui.v4i32.v4f32(
                                 <4 x float> %x,
                                 metadata !"fpexcept.strict") #0
   ret <4 x i32> %result
 }
 
 define <1 x i64> @constrained_vector_fptoui_v1i64_v1f32(<1 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptoui_v1i64_v1f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xscvdpuxds 0, 1
-; PC64LE-NEXT:    mffprd 3, 0
+; PC64LE-NEXT:    xscvdpuxds 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v1i64_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xscvdpuxds 0, 1
-; PC64LE9-NEXT:    mffprd 3, 0
+; PC64LE9-NEXT:    xscvdpuxds 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x i64> @llvm.experimental.constrained.fptoui.v1i64.v1f32(
                                <1 x float> %x,
                                metadata !"fpexcept.strict") #0
   ret <1 x i64> %result
 }
 
 define <2 x i64> @constrained_vector_fptoui_v2i64_v2f32(<2 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptoui_v2i64_v2f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 1, 34
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvdpuxds 0, 0
-; PC64LE-NEXT:    xscvdpuxds 1, 1
-; PC64LE-NEXT:    mffprd 3, 0
-; PC64LE-NEXT:    mffprd 4, 1
-; PC64LE-NEXT:    mtfprd 0, 3
-; PC64LE-NEXT:    mtfprd 1, 4
-; PC64LE-NEXT:    xxmrghd 34, 1, 0
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvdpuxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpuxds 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprd 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprd 1, 4 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    xxmrghd 34, 1, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL1(VSR1)VSL0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v2i64_v2f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpuxds 0, 0
-; PC64LE9-NEXT:    mffprd 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 34
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpuxds 0, 0
-; PC64LE9-NEXT:    mffprd 4, 0
-; PC64LE9-NEXT:    mtvsrdd 34, 4, 3
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtvsrdd 34, 4, 3 # Vec Defs: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f32(
                                 <2 x float> %x,
                                 metadata !"fpexcept.strict") #0
   ret <2 x i64> %result
 }
 
 define <3 x i64> @constrained_vector_fptoui_v3i64_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptoui_v3i64_v3f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 1, 34
-; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    xscvdpuxds 0, 0
-; PC64LE-NEXT:    xscvdpuxds 1, 1
-; PC64LE-NEXT:    xscvdpuxds 2, 2
-; PC64LE-NEXT:    mffprd 3, 0
-; PC64LE-NEXT:    mffprd 4, 1
-; PC64LE-NEXT:    mffprd 5, 2
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    xscvdpuxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpuxds 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpuxds 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprd 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprd 5, 2 # Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v3i64_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpuxds 0, 0
-; PC64LE9-NEXT:    mffprd 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 34
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpuxds 0, 0
-; PC64LE9-NEXT:    mffprd 4, 0
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpuxds 0, 0
-; PC64LE9-NEXT:    mffprd 5, 0
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 5, 0 # Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x i64> @llvm.experimental.constrained.fptoui.v3i64.v3f32(
                                 <3 x float> %x,
                                 metadata !"fpexcept.strict") #0
   ret <3 x i64> %result
 }
 
 define <4 x i64> @constrained_vector_fptoui_v4i64_v4f32(<4 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptoui_v4i64_v4f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xscvspdpn 1, 34
-; PC64LE-NEXT:    xxswapd 2, 34
-; PC64LE-NEXT:    xxsldwi 3, 34, 34, 1
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    xscvspdpn 3, 3
-; PC64LE-NEXT:    xscvdpuxds 1, 1
-; PC64LE-NEXT:    xscvdpuxds 0, 0
-; PC64LE-NEXT:    xscvdpuxds 2, 2
-; PC64LE-NEXT:    xscvdpuxds 3, 3
-; PC64LE-NEXT:    mffprd 3, 1
-; PC64LE-NEXT:    mtfprd 1, 3
-; PC64LE-NEXT:    mffprd 3, 0
-; PC64LE-NEXT:    mffprd 4, 2
-; PC64LE-NEXT:    mtfprd 0, 3
-; PC64LE-NEXT:    mffprd 3, 3
-; PC64LE-NEXT:    mtfprd 2, 4
-; PC64LE-NEXT:    mtfprd 3, 3
-; PC64LE-NEXT:    xxmrghd 34, 2, 0
-; PC64LE-NEXT:    xxmrghd 35, 1, 3
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 1, 34 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; PC64LE-NEXT:    xxswapd 2, 34 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 3, 34, 34, 1 # Vec Defs: VSL3(VSR3) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    xscvspdpn 3, 3 # Vec Defs: F3(VSR3) Vec Uses: VSL3(VSR3)
+; PC64LE-NEXT:    xscvdpuxds 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpuxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpuxds 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xscvdpuxds 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    mffprd 3, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprd 1, 3 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprd 4, 2 # Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mffprd 3, 3 # Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    mtfprd 2, 4 # Vec Defs: F2(VSR2)
+; PC64LE-NEXT:    mtfprd 3, 3 # Vec Defs: F3(VSR3)
+; PC64LE-NEXT:    xxmrghd 34, 2, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL2(VSR2)VSL0(VSR0)
+; PC64LE-NEXT:    xxmrghd 35, 1, 3 # Vec Defs: V3(VSR35) Vec Uses: VSL1(VSR1)VSL3(VSR3)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v4i64_v4f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpuxds 0, 0
-; PC64LE9-NEXT:    mffprd 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 34
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpuxds 0, 0
-; PC64LE9-NEXT:    mffprd 4, 0
-; PC64LE9-NEXT:    xscvspdpn 0, 34
-; PC64LE9-NEXT:    mtvsrdd 36, 4, 3
-; PC64LE9-NEXT:    xscvdpuxds 0, 0
-; PC64LE9-NEXT:    mffprd 3, 0
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE9-NEXT:    vmr 2, 4
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvdpuxds 0, 0
-; PC64LE9-NEXT:    mffprd 4, 0
-; PC64LE9-NEXT:    mtvsrdd 35, 3, 4
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvspdpn 0, 34 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    mtvsrdd 36, 4, 3 # Vec Defs: V4(VSR36)
+; PC64LE9-NEXT:    xscvdpuxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    vmr 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V4(VSR36)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxds 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprd 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtvsrdd 35, 3, 4 # Vec Defs: V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x i64> @llvm.experimental.constrained.fptoui.v4i64.v4f32(
                                 <4 x float> %x,
                                 metadata !"fpexcept.strict") #0
   ret <4 x i64> %result
 }
 
 define <1 x i32> @constrained_vector_fptoui_v1i32_v1f64(<1 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptoui_v1i32_v1f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xscvdpuxws 0, 1
-; PC64LE-NEXT:    mffprwz 3, 0
+; PC64LE-NEXT:    xscvdpuxws 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v1i32_v1f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xscvdpuxws 0, 1
-; PC64LE9-NEXT:    mffprwz 3, 0
+; PC64LE9-NEXT:    xscvdpuxws 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x i32> @llvm.experimental.constrained.fptoui.v1i32.v1f64(
                                <1 x double> %x,
                                metadata !"fpexcept.strict") #0
   ret <1 x i32> %result
 }
 
 define <2 x i32> @constrained_vector_fptoui_v2i32_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptoui_v2i32_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    xscvdpuxws 1, 34
-; PC64LE-NEXT:    xscvdpuxws 0, 0
-; PC64LE-NEXT:    mffprwz 3, 1
-; PC64LE-NEXT:    mtvsrwz 34, 3
-; PC64LE-NEXT:    mffprwz 4, 0
-; PC64LE-NEXT:    mtvsrwz 35, 4
-; PC64LE-NEXT:    vmrghw 2, 2, 3
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvdpuxws 1, 34 # Vec Defs: F1(VSR1) Vec Uses: VF2(VSR2)
+; PC64LE-NEXT:    xscvdpuxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 3, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtvsrwz 34, 3 # Vec Defs: VF2(VSR2)
+; PC64LE-NEXT:    mffprwz 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mtvsrwz 35, 4 # Vec Defs: VF3(VSR3)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v2i32_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xscvdpuxws 0, 34
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 34
-; PC64LE9-NEXT:    mtvsrwz 35, 3
-; PC64LE9-NEXT:    xscvdpuxws 0, 0
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    mtvsrwz 34, 3
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
+; PC64LE9-NEXT:    xscvdpuxws 0, 34 # Vec Defs: F0(VSR0) Vec Uses: VF2(VSR2)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
+; PC64LE9-NEXT:    xscvdpuxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtvsrwz 34, 3 # Vec Defs: VF2(VSR2)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x i32> @llvm.experimental.constrained.fptoui.v2i32.v2f64(
                                 <2 x double> %x,
                                 metadata !"fpexcept.strict") #0
   ret <2 x i32> %result
 }
 
 define <3 x i32> @constrained_vector_fptoui_v3i32_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptoui_v3i32_v3f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xscvdpuxws 0, 1
+; PC64LE-NEXT:    xscvdpuxws 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI121_0@toc@ha
-; PC64LE-NEXT:    xscvdpuxws 1, 2
+; PC64LE-NEXT:    xscvdpuxws 1, 2 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI121_0@toc@l
-; PC64LE-NEXT:    xscvdpuxws 2, 3
-; PC64LE-NEXT:    mffprwz 4, 0
-; PC64LE-NEXT:    mffprwz 5, 1
-; PC64LE-NEXT:    mtvsrwz 34, 4
-; PC64LE-NEXT:    mtvsrwz 35, 5
-; PC64LE-NEXT:    mffprwz 4, 2
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    lvx 3, 0, 3
-; PC64LE-NEXT:    mtvsrwz 36, 4
-; PC64LE-NEXT:    vperm 2, 4, 2, 3
+; PC64LE-NEXT:    xscvdpuxws 2, 3 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    mffprwz 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 5, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtvsrwz 34, 4 # Vec Defs: VF2(VSR2)
+; PC64LE-NEXT:    mtvsrwz 35, 5 # Vec Defs: VF3(VSR3)
+; PC64LE-NEXT:    mffprwz 4, 2 # Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    lvx 3, 0, 3 # Vec Defs: V3(VSR35)
+; PC64LE-NEXT:    mtvsrwz 36, 4 # Vec Defs: VF4(VSR4)
+; PC64LE-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v3i32_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xscvdpuxws 0, 1
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xscvdpuxws 0, 2
-; PC64LE9-NEXT:    mtvsrwz 34, 3
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xscvdpuxws 0, 3
-; PC64LE9-NEXT:    mtvsrwz 35, 3
+; PC64LE9-NEXT:    xscvdpuxws 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxws 0, 2 # Vec Defs: F0(VSR0) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    mtvsrwz 34, 3 # Vec Defs: VF2(VSR2)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxws 0, 3 # Vec Defs: F0(VSR0) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    mtvsrwz 35, 3 # Vec Defs: VF3(VSR3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI121_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI121_0@toc@l
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    mtvsrwz 36, 3
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtvsrwz 36, 3 # Vec Defs: VF4(VSR4)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x i32> @llvm.experimental.constrained.fptoui.v3i32.v3f64(
                                 <3 x double> %x,
                                 metadata !"fpexcept.strict") #0
   ret <3 x i32> %result
 }
 
 define <4 x i32> @constrained_vector_fptoui_v4i32_v4f64(<4 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptoui_v4i32_v4f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    xxswapd 2, 35
-; PC64LE-NEXT:    xscvdpuxws 1, 34
-; PC64LE-NEXT:    xscvdpuxws 3, 35
-; PC64LE-NEXT:    xscvdpuxws 0, 0
-; PC64LE-NEXT:    xscvdpuxws 2, 2
-; PC64LE-NEXT:    mffprwz 3, 1
-; PC64LE-NEXT:    mffprwz 4, 3
-; PC64LE-NEXT:    mffprwz 5, 0
-; PC64LE-NEXT:    mffprwz 6, 2
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 2, 35 # Vec Defs: VSL2(VSR2) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    xscvdpuxws 1, 34 # Vec Defs: F1(VSR1) Vec Uses: VF2(VSR2)
+; PC64LE-NEXT:    xscvdpuxws 3, 35 # Vec Defs: F3(VSR3) Vec Uses: VF3(VSR3)
+; PC64LE-NEXT:    xscvdpuxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpuxws 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    mffprwz 3, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprwz 4, 3 # Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    mffprwz 5, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 6, 2 # Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    rldimi 5, 3, 32, 0
 ; PC64LE-NEXT:    rldimi 6, 4, 32, 0
-; PC64LE-NEXT:    mtfprd 0, 5
-; PC64LE-NEXT:    mtfprd 1, 6
-; PC64LE-NEXT:    xxmrghd 34, 1, 0
+; PC64LE-NEXT:    mtfprd 0, 5 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprd 1, 6 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    xxmrghd 34, 1, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL1(VSR1)VSL0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v4i32_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xscvdpuxws 0, 34
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 34
-; PC64LE9-NEXT:    xscvdpuxws 0, 0
-; PC64LE9-NEXT:    mffprwz 4, 0
-; PC64LE9-NEXT:    xscvdpuxws 0, 35
+; PC64LE9-NEXT:    xscvdpuxws 0, 34 # Vec Defs: F0(VSR0) Vec Uses: VF2(VSR2)
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvdpuxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprwz 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxws 0, 35 # Vec Defs: F0(VSR0) Vec Uses: VF3(VSR3)
 ; PC64LE9-NEXT:    rldimi 4, 3, 32, 0
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 35
-; PC64LE9-NEXT:    xscvdpuxws 0, 0
-; PC64LE9-NEXT:    mffprwz 5, 0
+; PC64LE9-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 35 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE9-NEXT:    xscvdpuxws 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mffprwz 5, 0 # Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    rldimi 5, 3, 32, 0
-; PC64LE9-NEXT:    mtvsrdd 34, 5, 4
+; PC64LE9-NEXT:    mtvsrdd 34, 5, 4 # Vec Defs: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x i32> @llvm.experimental.constrained.fptoui.v4i32.v4f64(
                                 <4 x double> %x,
                                 metadata !"fpexcept.strict") #0
   ret <4 x i32> %result
 }
 
 define <1 x i64> @constrained_vector_fptoui_v1i64_v1f64(<1 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptoui_v1i64_v1f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xscvdpuxds 0, 1
-; PC64LE-NEXT:    mffprd 3, 0
+; PC64LE-NEXT:    xscvdpuxds 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v1i64_v1f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xscvdpuxds 0, 1
-; PC64LE9-NEXT:    mffprd 3, 0
+; PC64LE9-NEXT:    xscvdpuxds 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x i64> @llvm.experimental.constrained.fptoui.v1i64.v1f64(
                                <1 x double> %x,
                                metadata !"fpexcept.strict") #0
   ret <1 x i64> %result
 }
 
 define <2 x i64> @constrained_vector_fptoui_v2i64_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptoui_v2i64_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvcvdpuxds 34, 34
+; PC64LE-NEXT:    xvcvdpuxds 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v2i64_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvcvdpuxds 34, 34
+; PC64LE9-NEXT:    xvcvdpuxds 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f64(
                                 <2 x double> %x,
                                 metadata !"fpexcept.strict") #0
   ret <2 x i64> %result
 }
 
 define <3 x i64> @constrained_vector_fptoui_v3i64_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptoui_v3i64_v3f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xscvdpuxds 0, 1
-; PC64LE-NEXT:    xscvdpuxds 1, 2
-; PC64LE-NEXT:    xscvdpuxds 2, 3
-; PC64LE-NEXT:    mffprd 3, 0
-; PC64LE-NEXT:    mffprd 4, 1
-; PC64LE-NEXT:    mffprd 5, 2
+; PC64LE-NEXT:    xscvdpuxds 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpuxds 1, 2 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xscvdpuxds 2, 3 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprd 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mffprd 5, 2 # Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v3i64_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xscvdpuxds 0, 1
-; PC64LE9-NEXT:    mffprd 3, 0
-; PC64LE9-NEXT:    xscvdpuxds 0, 2
-; PC64LE9-NEXT:    mffprd 4, 0
-; PC64LE9-NEXT:    xscvdpuxds 0, 3
-; PC64LE9-NEXT:    mffprd 5, 0
+; PC64LE9-NEXT:    xscvdpuxds 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxds 0, 2 # Vec Defs: F0(VSR0) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    mffprd 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpuxds 0, 3 # Vec Defs: F0(VSR0) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    mffprd 5, 0 # Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x i64> @llvm.experimental.constrained.fptoui.v3i64.v3f64(
                                 <3 x double> %x,
                                 metadata !"fpexcept.strict") #0
   ret <3 x i64> %result
 }
 
 define <4 x i64> @constrained_vector_fptoui_v4i64_v4f64(<4 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptoui_v4i64_v4f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvcvdpuxds 35, 35
-; PC64LE-NEXT:    xvcvdpuxds 34, 34
+; PC64LE-NEXT:    xvcvdpuxds 35, 35 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)
+; PC64LE-NEXT:    xvcvdpuxds 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v4i64_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvcvdpuxds 35, 35
-; PC64LE9-NEXT:    xvcvdpuxds 34, 34
+; PC64LE9-NEXT:    xvcvdpuxds 35, 35 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)
+; PC64LE9-NEXT:    xvcvdpuxds 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x i64> @llvm.experimental.constrained.fptoui.v4i64.v4f64(
                                 <4 x double> %x,
                                 metadata !"fpexcept.strict") #0
   ret <4 x i64> %result
 }
 
 define <1 x float> @constrained_vector_fptrunc_v1f64(<1 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptrunc_v1f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xsrsp 1, 1
+; PC64LE-NEXT:    xsrsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptrunc_v1f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xsrsp 1, 1
+; PC64LE9-NEXT:    xsrsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x float> @llvm.experimental.constrained.fptrunc.v1f32.v1f64(
                                 <1 x double> %x,
                                 metadata !"round.dynamic",
                                 metadata !"fpexcept.strict") #1
   ret <1 x float> %result
 }
 
 define <2 x float> @constrained_vector_fptrunc_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptrunc_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    xsrsp 1, 34
-; PC64LE-NEXT:    xsrsp 0, 0
-; PC64LE-NEXT:    xscvdpspn 34, 1
-; PC64LE-NEXT:    xscvdpspn 35, 0
-; PC64LE-NEXT:    vmrghw 2, 2, 3
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xsrsp 1, 34 # Vec Defs: F1(VSR1) Vec Uses: VF2(VSR2)
+; PC64LE-NEXT:    xsrsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 34, 1 # Vec Defs: V2(VSR34) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptrunc_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xsrsp 0, 34
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    xxswapd 0, 34
-; PC64LE9-NEXT:    xsrsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 0
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
+; PC64LE9-NEXT:    xsrsp 0, 34 # Vec Defs: F0(VSR0) Vec Uses: VF2(VSR2)
+; PC64LE9-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xsrsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x float> @llvm.experimental.constrained.fptrunc.v2f32.v2f64(
                                 <2 x double> %x,
                                 metadata !"round.dynamic",
                                 metadata !"fpexcept.strict") #1
   ret <2 x float> %result
 }
 
 define <3 x float> @constrained_vector_fptrunc_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptrunc_v3f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xsrsp 0, 1
+; PC64LE-NEXT:    xsrsp 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI129_0@toc@ha
-; PC64LE-NEXT:    xsrsp 1, 2
+; PC64LE-NEXT:    xsrsp 1, 2 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI129_0@toc@l
-; PC64LE-NEXT:    xsrsp 2, 3
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    xscvdpspn 35, 1
-; PC64LE-NEXT:    xscvdpspn 36, 2
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    lvx 3, 0, 3
-; PC64LE-NEXT:    vperm 2, 4, 2, 3
+; PC64LE-NEXT:    xsrsp 2, 3 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpspn 36, 2 # Vec Defs: V4(VSR36) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    lvx 3, 0, 3 # Vec Defs: V3(VSR35)
+; PC64LE-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptrunc_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xsrsp 0, 1
+; PC64LE9-NEXT:    xsrsp 0, 1 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI129_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI129_0@toc@l
-; PC64LE9-NEXT:    xscvdpspn 34, 0
-; PC64LE9-NEXT:    xsrsp 0, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    xsrsp 0, 3
-; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xsrsp 0, 2 # Vec Defs: F0(VSR0) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xsrsp 0, 3 # Vec Defs: F0(VSR0) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    xscvdpspn 36, 0 # Vec Defs: V4(VSR36) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x float> @llvm.experimental.constrained.fptrunc.v3f32.v3f64(
                                 <3 x double> %x,
                                 metadata !"round.dynamic",
                                 metadata !"fpexcept.strict") #1
   ret <3 x float> %result
 }
 
 define <4 x float> @constrained_vector_fptrunc_v4f64(<4 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fptrunc_v4f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxmrgld 0, 35, 34
-; PC64LE-NEXT:    xxmrghd 1, 35, 34
-; PC64LE-NEXT:    xvcvdpsp 34, 0
-; PC64LE-NEXT:    xvcvdpsp 35, 1
-; PC64LE-NEXT:    vmrgew 2, 3, 2
+; PC64LE-NEXT:    xxmrgld 0, 35, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xxmrghd 1, 35, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xvcvdpsp 34, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xvcvdpsp 35, 1 # Vec Defs: V3(VSR35) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    vmrgew 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptrunc_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxmrgld 0, 35, 34
-; PC64LE9-NEXT:    xvcvdpsp 36, 0
-; PC64LE9-NEXT:    xxmrghd 0, 35, 34
-; PC64LE9-NEXT:    xvcvdpsp 34, 0
-; PC64LE9-NEXT:    vmrgew 2, 2, 4
+; PC64LE9-NEXT:    xxmrgld 0, 35, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    xvcvdpsp 36, 0 # Vec Defs: V4(VSR36) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxmrghd 0, 35, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    xvcvdpsp 34, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    vmrgew 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x float> @llvm.experimental.constrained.fptrunc.v4f32.v4f64(
                                 <4 x double> %x,
                                 metadata !"round.dynamic",
                                 metadata !"fpexcept.strict") #1
   ret <4 x float> %result
 }
%result = call <1 x double> @llvm.experimental.constrained.fpext.v1f64.v1f32(
                                 <1 x float> %x,
                                 metadata !"fpexcept.strict") #1
   ret <1 x double> %result
 }
 
 define <2 x double> @constrained_vector_fpext_v2f32(<2 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fpext_v2f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 1, 34
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xxmrghd 34, 1, 0
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xxmrghd 34, 1, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL1(VSR1)VSL0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fpext_v2f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE9-NEXT:    xxswapd 1, 34
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvspdpn 1, 1
-; PC64LE9-NEXT:    xxmrghd 34, 1, 0
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE9-NEXT:    xxmrghd 34, 1, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL1(VSR1)VSL0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f32(
                                 <2 x float> %x,
                                 metadata !"fpexcept.strict") #1
   ret <2 x double> %result
 }
 
 define <3 x double> @constrained_vector_fpext_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fpext_v3f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE-NEXT:    xxswapd 1, 34
-; PC64LE-NEXT:    xxsldwi 4, 34, 34, 3
-; PC64LE-NEXT:    xscvspdpn 3, 0
-; PC64LE-NEXT:    xscvspdpn 2, 1
-; PC64LE-NEXT:    xscvspdpn 1, 4
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 4, 34, 34, 3 # Vec Defs: VSL4(VSR4) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 3, 0 # Vec Defs: F3(VSR3) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 2, 1 # Vec Defs: F2(VSR2) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 1, 4 # Vec Defs: F1(VSR1) Vec Uses: VSL4(VSR4)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fpext_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE9-NEXT:    xscvspdpn 3, 0
-; PC64LE9-NEXT:    xxswapd 0, 34
-; PC64LE9-NEXT:    xscvspdpn 2, 0
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE9-NEXT:    xscvspdpn 1, 0
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 3, 0 # Vec Defs: F3(VSR3) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 2, 0 # Vec Defs: F2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 1, 0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x double> @llvm.experimental.constrained.fpext.v3f64.v3f32(
                                 <3 x float> %x,
                                 metadata !"fpexcept.strict") #1
   ret <3 x double> %result
 }
 
 define <4 x double> @constrained_vector_fpext_v4f32(<4 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_fpext_v4f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 1, 34
-; PC64LE-NEXT:    xxsldwi 3, 34, 34, 1
-; PC64LE-NEXT:    xscvspdpn 2, 34
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvspdpn 3, 3
-; PC64LE-NEXT:    xxmrghd 34, 1, 0
-; PC64LE-NEXT:    xxmrghd 35, 2, 3
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 3, 34, 34, 1 # Vec Defs: VSL3(VSR3) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 2, 34 # Vec Defs: F2(VSR2) Vec Uses: V2(VSR34)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 3, 3 # Vec Defs: F3(VSR3) Vec Uses: VSL3(VSR3)
+; PC64LE-NEXT:    xxmrghd 34, 1, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE-NEXT:    xxmrghd 35, 2, 3 # Vec Defs: V3(VSR35) Vec Uses: VSL2(VSR2)VSL3(VSR3)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fpext_v4f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE9-NEXT:    xxswapd 1, 34
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xscvspdpn 1, 1
-; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 1
-; PC64LE9-NEXT:    xscvspdpn 2, 2
-; PC64LE9-NEXT:    xxmrghd 0, 1, 0
-; PC64LE9-NEXT:    xscvspdpn 1, 34
-; PC64LE9-NEXT:    xxmrghd 35, 1, 2
-; PC64LE9-NEXT:    xxlor 34, 0, 0
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 1 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE9-NEXT:    xxmrghd 0, 1, 0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE9-NEXT:    xscvspdpn 1, 34 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    xxmrghd 35, 1, 2 # Vec Defs: V3(VSR35) Vec Uses: VSL1(VSR1)VSL2(VSR2)
+; PC64LE9-NEXT:    xxlor 34, 0, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x double> @llvm.experimental.constrained.fpext.v4f64.v4f32(
                                 <4 x float> %x,
                                 metadata !"fpexcept.strict") #1
   ret <4 x double> %result
 }
 
 define <1 x float> @constrained_vector_ceil_v1f32(<1 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_ceil_v1f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xsrdpip 1, 1
+; PC64LE-NEXT:    xsrdpip 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_ceil_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xsrdpip 1, 1
+; PC64LE9-NEXT:    xsrdpip 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64LE9-NEXT:    blr
 entry:
   %ceil = call <1 x float> @llvm.experimental.constrained.ceil.v1f32(
                                <1 x float> %x,
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %ceil
 }
 
 define <2 x double> @constrained_vector_ceil_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_ceil_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvrdpip 34, 34
+; PC64LE-NEXT:    xvrdpip 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_ceil_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvrdpip 34, 34
+; PC64LE9-NEXT:    xvrdpip 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %ceil = call <2 x double> @llvm.experimental.constrained.ceil.v2f64(
                                 <2 x double> %x,
                                 metadata !"fpexcept.strict") #1
   ret <2 x double> %ceil
 }
 
 define <3 x float> @constrained_vector_ceil_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_ceil_v3f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 1, 34
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI137_0@toc@ha
-; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI137_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    xsrdpip 0, 0
-; PC64LE-NEXT:    xsrdpip 1, 1
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    xscvdpspn 35, 1
-; PC64LE-NEXT:    xsrdpip 0, 2
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    xscvdpspn 35, 0
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    xsrdpip 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xsrdpip 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xsrdpip 0, 2 # Vec Defs: F0(VSR0) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_ceil_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxswapd 1, 34
-; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3
+; PC64LE9-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI137_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI137_0@toc@l
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 1
-; PC64LE9-NEXT:    xscvspdpn 2, 2
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xsrdpip 1, 1
-; PC64LE9-NEXT:    xsrdpip 2, 2
-; PC64LE9-NEXT:    xsrdpip 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xsrdpip 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xsrdpip 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    xsrdpip 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 34, 2 # Vec Defs: V2(VSR34) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 36, 0 # Vec Defs: V4(VSR36) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %ceil = call <3 x float> @llvm.experimental.constrained.ceil.v3f32(
                               <3 x float> %x,
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %ceil
 }
 
 define <3 x double> @constrained_vector_ceil_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_ceil_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 0, 2, 1
-; PC64LE-NEXT:    xsrdpip 3, 3
-; PC64LE-NEXT:    xvrdpip 2, 0
-; PC64LE-NEXT:    xxswapd 1, 2
+; PC64LE-NEXT:    xxmrghd 0, 2, 1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE-NEXT:    xsrdpip 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    xvrdpip 2, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_ceil_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 0, 2, 1
-; PC64LE9-NEXT:    xsrdpip 3, 3
-; PC64LE9-NEXT:    xvrdpip 2, 0
-; PC64LE9-NEXT:    xxswapd 1, 2
+; PC64LE9-NEXT:    xxmrghd 0, 2, 1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE9-NEXT:    xsrdpip 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    xvrdpip 2, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    blr
 entry:
   %ceil = call <3 x double> @llvm.experimental.constrained.ceil.v3f64(
                           <3 x double> %x,
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %ceil
 }
 
 define <1 x float> @constrained_vector_floor_v1f32(<1 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_floor_v1f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xsrdpim 1, 1
+; PC64LE-NEXT:    xsrdpim 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_floor_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xsrdpim 1, 1
+; PC64LE9-NEXT:    xsrdpim 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64LE9-NEXT:    blr
 entry:
   %floor = call <1 x float> @llvm.experimental.constrained.floor.v1f32(
                                <1 x float> %x,
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %floor
 }
 
 
 define <2 x double> @constrained_vector_floor_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_floor_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvrdpim 34, 34
+; PC64LE-NEXT:    xvrdpim 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_floor_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvrdpim 34, 34
+; PC64LE9-NEXT:    xvrdpim 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %floor = call <2 x double> @llvm.experimental.constrained.floor.v2f64(
                                 <2 x double> %x,
                                 metadata !"fpexcept.strict") #1
   ret <2 x double> %floor
 }
 
 define <3 x float> @constrained_vector_floor_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_floor_v3f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 1, 34
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI141_0@toc@ha
-; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI141_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    xsrdpim 0, 0
-; PC64LE-NEXT:    xsrdpim 1, 1
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    xscvdpspn 35, 1
-; PC64LE-NEXT:    xsrdpim 0, 2
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    xscvdpspn 35, 0
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    xsrdpim 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xsrdpim 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xsrdpim 0, 2 # Vec Defs: F0(VSR0) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_floor_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxswapd 1, 34
-; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3
+; PC64LE9-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI141_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI141_0@toc@l
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 1
-; PC64LE9-NEXT:    xscvspdpn 2, 2
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xsrdpim 1, 1
-; PC64LE9-NEXT:    xsrdpim 2, 2
-; PC64LE9-NEXT:    xsrdpim 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xsrdpim 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xsrdpim 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    xsrdpim 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 34, 2 # Vec Defs: V2(VSR34) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 36, 0 # Vec Defs: V4(VSR36) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %floor = call <3 x float> @llvm.experimental.constrained.floor.v3f32(
                               <3 x float> %x,
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %floor
 }
 
 define <3 x double> @constrained_vector_floor_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_floor_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 0, 2, 1
-; PC64LE-NEXT:    xsrdpim 3, 3
-; PC64LE-NEXT:    xvrdpim 2, 0
-; PC64LE-NEXT:    xxswapd 1, 2
+; PC64LE-NEXT:    xxmrghd 0, 2, 1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE-NEXT:    xsrdpim 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    xvrdpim 2, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_floor_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 0, 2, 1
-; PC64LE9-NEXT:    xsrdpim 3, 3
-; PC64LE9-NEXT:    xvrdpim 2, 0
-; PC64LE9-NEXT:    xxswapd 1, 2
+; PC64LE9-NEXT:    xxmrghd 0, 2, 1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE9-NEXT:    xsrdpim 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    xvrdpim 2, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    blr
 entry:
   %floor = call <3 x double> @llvm.experimental.constrained.floor.v3f64(
                           <3 x double> %x,
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %floor
 }
 
 define <1 x float> @constrained_vector_round_v1f32(<1 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_round_v1f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xsrdpi 1, 1
+; PC64LE-NEXT:    xsrdpi 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_round_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xsrdpi 1, 1
+; PC64LE9-NEXT:    xsrdpi 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64LE9-NEXT:    blr
 entry:
   %round = call <1 x float> @llvm.experimental.constrained.round.v1f32(
                                <1 x float> %x,
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %round
 }
 
 define <2 x double> @constrained_vector_round_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_round_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvrdpi 34, 34
+; PC64LE-NEXT:    xvrdpi 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_round_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvrdpi 34, 34
+; PC64LE9-NEXT:    xvrdpi 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %round = call <2 x double> @llvm.experimental.constrained.round.v2f64(
                                 <2 x double> %x,
                                 metadata !"fpexcept.strict") #1
   ret <2 x double> %round
 }
 
 define <3 x float> @constrained_vector_round_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_round_v3f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 1, 34
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI145_0@toc@ha
-; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI145_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    xsrdpi 0, 0
-; PC64LE-NEXT:    xsrdpi 1, 1
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    xscvdpspn 35, 1
-; PC64LE-NEXT:    xsrdpi 0, 2
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    xscvdpspn 35, 0
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    xsrdpi 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xsrdpi 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xsrdpi 0, 2 # Vec Defs: F0(VSR0) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_round_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxswapd 1, 34
-; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3
+; PC64LE9-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI145_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI145_0@toc@l
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 1
-; PC64LE9-NEXT:    xscvspdpn 2, 2
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xsrdpi 1, 1
-; PC64LE9-NEXT:    xsrdpi 2, 2
-; PC64LE9-NEXT:    xsrdpi 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xsrdpi 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xsrdpi 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    xsrdpi 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 34, 2 # Vec Defs: V2(VSR34) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 36, 0 # Vec Defs: V4(VSR36) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %round = call <3 x float> @llvm.experimental.constrained.round.v3f32(
                               <3 x float> %x,
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %round
 }
 
 
 define <3 x double> @constrained_vector_round_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_round_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 0, 2, 1
-; PC64LE-NEXT:    xsrdpi 3, 3
-; PC64LE-NEXT:    xvrdpi 2, 0
-; PC64LE-NEXT:    xxswapd 1, 2
+; PC64LE-NEXT:    xxmrghd 0, 2, 1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE-NEXT:    xsrdpi 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    xvrdpi 2, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_round_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 0, 2, 1
-; PC64LE9-NEXT:    xsrdpi 3, 3
-; PC64LE9-NEXT:    xvrdpi 2, 0
-; PC64LE9-NEXT:    xxswapd 1, 2
+; PC64LE9-NEXT:    xxmrghd 0, 2, 1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE9-NEXT:    xsrdpi 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    xvrdpi 2, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    blr
 entry:
   %round = call <3 x double> @llvm.experimental.constrained.round.v3f64(
                           <3 x double> %x,
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %round
 }
 
 define <1 x float> @constrained_vector_trunc_v1f32(<1 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_trunc_v1f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xsrdpiz 1, 1
+; PC64LE-NEXT:    xsrdpiz 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_trunc_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xsrdpiz 1, 1
+; PC64LE9-NEXT:    xsrdpiz 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
 ; PC64LE9-NEXT:    blr
 entry:
   %trunc = call <1 x float> @llvm.experimental.constrained.trunc.v1f32(
                                <1 x float> %x,
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %trunc
 }
 
 define <2 x double> @constrained_vector_trunc_v2f64(<2 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_trunc_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvrdpiz 34, 34
+; PC64LE-NEXT:    xvrdpiz 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_trunc_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvrdpiz 34, 34
+; PC64LE9-NEXT:    xvrdpiz 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %trunc = call <2 x double> @llvm.experimental.constrained.trunc.v2f64(
                                 <2 x double> %x,
                                 metadata !"fpexcept.strict") #1
   ret <2 x double> %trunc
 }
 
 define <3 x float> @constrained_vector_trunc_v3f32(<3 x float> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_trunc_v3f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    xxswapd 1, 34
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI149_0@toc@ha
-; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1
+; PC64LE-NEXT:    xxsldwi 2, 34, 34, 1 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI149_0@toc@l
-; PC64LE-NEXT:    lvx 4, 0, 3
-; PC64LE-NEXT:    xscvspdpn 0, 0
-; PC64LE-NEXT:    xscvspdpn 1, 1
-; PC64LE-NEXT:    xscvspdpn 2, 2
-; PC64LE-NEXT:    xsrdpiz 0, 0
-; PC64LE-NEXT:    xsrdpiz 1, 1
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    xscvdpspn 35, 1
-; PC64LE-NEXT:    xsrdpiz 0, 2
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    xscvdpspn 35, 0
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
+; PC64LE-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE-NEXT:    xsrdpiz 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xsrdpiz 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xsrdpiz 0, 2 # Vec Defs: F0(VSR0) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_trunc_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxswapd 1, 34
-; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3
+; PC64LE9-NEXT:    xxswapd 1, 34 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xxsldwi 2, 34, 34, 3 # Vec Defs: VSL2(VSR2) Vec Uses: V2(VSR34)V2(VSR34)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI149_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI149_0@toc@l
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
-; PC64LE9-NEXT:    xscvspdpn 1, 1
-; PC64LE9-NEXT:    xscvspdpn 2, 2
-; PC64LE9-NEXT:    xscvspdpn 0, 0
-; PC64LE9-NEXT:    xsrdpiz 1, 1
-; PC64LE9-NEXT:    xsrdpiz 2, 2
-; PC64LE9-NEXT:    xsrdpiz 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    xscvspdpn 1, 1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PC64LE9-NEXT:    xscvspdpn 2, 2 # Vec Defs: F2(VSR2) Vec Uses: VSL2(VSR2)
+; PC64LE9-NEXT:    xscvspdpn 0, 0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xsrdpiz 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xsrdpiz 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    xsrdpiz 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 34, 2 # Vec Defs: V2(VSR34) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvdpspn 36, 0 # Vec Defs: V4(VSR36) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %trunc = call <3 x float> @llvm.experimental.constrained.trunc.v3f32(
                               <3 x float> %x,
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %trunc
 }
 
 define <3 x double> @constrained_vector_trunc_v3f64(<3 x double> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_trunc_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    xxmrghd 0, 2, 1
-; PC64LE-NEXT:    xsrdpiz 3, 3
-; PC64LE-NEXT:    xvrdpiz 2, 0
-; PC64LE-NEXT:    xxswapd 1, 2
+; PC64LE-NEXT:    xxmrghd 0, 2, 1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE-NEXT:    xsrdpiz 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    xvrdpiz 2, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_trunc_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 def $vsl2
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 0, 2, 1
-; PC64LE9-NEXT:    xsrdpiz 3, 3
-; PC64LE9-NEXT:    xvrdpiz 2, 0
-; PC64LE9-NEXT:    xxswapd 1, 2
+; PC64LE9-NEXT:    xxmrghd 0, 2, 1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PC64LE9-NEXT:    xsrdpiz 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE9-NEXT:    xvrdpiz 2, 0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    xxswapd 1, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL2(VSR2)
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    blr
 entry:
   %trunc = call <3 x double> @llvm.experimental.constrained.trunc.v3f64(
                           <3 x double> %x,
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %trunc
 }
 
 define <1 x double> @constrained_vector_sitofp_v1f64_v1i32(<1 x i32> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v1f64_v1i32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mtfprwa 0, 3
-; PC64LE-NEXT:    xscvsxddp 1, 0
+; PC64LE-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    xscvsxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v1f64_v1i32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mtfprwa 0, 3
-; PC64LE9-NEXT:    xscvsxddp 1, 0
+; PC64LE9-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvsxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x double>
            @llvm.experimental.constrained.sitofp.v1f64.v1i32(<1 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <1 x double> %result
 }
 
 define <1 x float> @constrained_vector_sitofp_v1f32_v1i32(<1 x i32> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v1f32_v1i32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mtfprwa 0, 3
-; PC64LE-NEXT:    xscvsxdsp 1, 0
+; PC64LE-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    xscvsxdsp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v1f32_v1i32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mtfprwa 0, 3
-; PC64LE9-NEXT:    xscvsxdsp 1, 0
+; PC64LE9-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvsxdsp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x float>
            @llvm.experimental.constrained.sitofp.v1f32.v1i32(<1 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <1 x float> %result
 }
 
 define <1 x double> @constrained_vector_sitofp_v1f64_v1i64(<1 x i64> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v1f64_v1i64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mtfprd 0, 3
-; PC64LE-NEXT:    xscvsxddp 1, 0
+; PC64LE-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    xscvsxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v1f64_v1i64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mtfprd 0, 3
-; PC64LE9-NEXT:    xscvsxddp 1, 0
+; PC64LE9-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvsxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x double>
            @llvm.experimental.constrained.sitofp.v1f64.v1i64(<1 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <1 x double> %result
 }
 
 define <1 x float> @constrained_vector_sitofp_v1f32_v1i64(<1 x i64> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v1f32_v1i64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mtfprd 0, 3
-; PC64LE-NEXT:    xscvsxdsp 1, 0
+; PC64LE-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    xscvsxdsp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v1f32_v1i64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mtfprd 0, 3
-; PC64LE9-NEXT:    xscvsxdsp 1, 0
+; PC64LE9-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvsxdsp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x float>
            @llvm.experimental.constrained.sitofp.v1f32.v1i64(<1 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <1 x float> %result
 }
 
 define <2 x double> @constrained_vector_sitofp_v2f64_v2i16(<2 x i16> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v2f64_v2i16:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI155_0@toc@ha
 ; PC64LE-NEXT:    addi 3, 3, .LCPI155_0@toc@l
-; PC64LE-NEXT:    lvx 3, 0, 3
+; PC64LE-NEXT:    lvx 3, 0, 3 # Vec Defs: V3(VSR35)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI155_1@toc@ha
 ; PC64LE-NEXT:    addi 3, 3, .LCPI155_1@toc@l
-; PC64LE-NEXT:    lxvd2x 0, 0, 3
-; PC64LE-NEXT:    vperm 2, 2, 2, 3
-; PC64LE-NEXT:    xxswapd 35, 0
-; PC64LE-NEXT:    vsld 2, 2, 3
-; PC64LE-NEXT:    vsrad 2, 2, 3
-; PC64LE-NEXT:    xvcvsxddp 34, 34
+; PC64LE-NEXT:    lxvd2x 0, 0, 3 # Vec Defs: VSL0(VSR0)
+; PC64LE-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xxswapd 35, 0 # Vec Defs: V3(VSR35) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PC64LE-NEXT:    vsld 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    vsrad 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xvcvsxddp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v2f64_v2i16:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI155_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI155_0@toc@l
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 2, 2, 3
-; PC64LE9-NEXT:    vextsh2d 2, 2
-; PC64LE9-NEXT:    xvcvsxddp 34, 34
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
+; PC64LE9-NEXT:    vextsh2d 2, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    xvcvsxddp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x double>
            @llvm.experimental.constrained.sitofp.v2f64.v2i16(<2 x i16> %x,
                                                 metadata !"round.dynamic",
                                                 metadata !"fpexcept.strict") #0
   ret <2 x double> %result
 }
 
 define <2 x double> @constrained_vector_sitofp_v2f64_v2i32(<2 x i32> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v2f64_v2i32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1
-; PC64LE-NEXT:    mffprwz 3, 0
-; PC64LE-NEXT:    mffprwz 4, 1
-; PC64LE-NEXT:    mtfprwa 0, 3
-; PC64LE-NEXT:    mtfprwa 1, 4
-; PC64LE-NEXT:    xscvsxddp 0, 0
-; PC64LE-NEXT:    xscvsxddp 1, 1
-; PC64LE-NEXT:    xxmrghd 34, 1, 0
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprwa 1, 4 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    xscvsxddp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvsxddp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xxmrghd 34, 1, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL1(VSR1)VSL0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v2f64_v2i32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    li 3, 0
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    mtfprwa 0, 3
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
 ; PC64LE9-NEXT:    li 3, 4
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    xscvsxddp 0, 0
-; PC64LE9-NEXT:    mtfprwa 1, 3
-; PC64LE9-NEXT:    xscvsxddp 1, 1
-; PC64LE9-NEXT:    xxmrghd 34, 1, 0
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    xscvsxddp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprwa 1, 3 # Vec Defs: F1(VSR1)
+; PC64LE9-NEXT:    xscvsxddp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxmrghd 34, 1, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL1(VSR1)VSL0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x double>
            @llvm.experimental.constrained.sitofp.v2f64.v2i32(<2 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <2 x double> %result
 }
 
 define <2 x float> @constrained_vector_sitofp_v2f32_v2i32(<2 x i32> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v2f32_v2i32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1
-; PC64LE-NEXT:    mffprwz 3, 0
-; PC64LE-NEXT:    mffprwz 4, 1
-; PC64LE-NEXT:    mtfprwa 0, 3
-; PC64LE-NEXT:    mtfprwa 1, 4
-; PC64LE-NEXT:    xscvsxdsp 0, 0
-; PC64LE-NEXT:    xscvsxdsp 1, 1
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    xscvdpspn 35, 1
-; PC64LE-NEXT:    vmrghw 2, 3, 2
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprwa 1, 4 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvsxdsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v2f32_v2i32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    li 3, 0
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    mtfprwa 0, 3
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
 ; PC64LE9-NEXT:    li 3, 4
-; PC64LE9-NEXT:    xscvsxdsp 0, 0
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    mtfprwa 0, 3
-; PC64LE9-NEXT:    xscvsxdsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 0
-; PC64LE9-NEXT:    vmrghw 2, 2, 3
+; PC64LE9-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x float>
            @llvm.experimental.constrained.sitofp.v2f32.v2i32(<2 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <2 x float> %result
 }
 
 define <2 x double> @constrained_vector_sitofp_v2f64_v2i64(<2 x i64> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v2f64_v2i64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvcvsxddp 34, 34
+; PC64LE-NEXT:    xvcvsxddp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v2f64_v2i64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvcvsxddp 34, 34
+; PC64LE9-NEXT:    xvcvsxddp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x double>
            @llvm.experimental.constrained.sitofp.v2f64.v2i64(<2 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <2 x double> %result
 }
 
 define <2 x float> @constrained_vector_sitofp_v2f32_v2i64(<2 x i64> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v2f32_v2i64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    mfvsrd 3, 34
-; PC64LE-NEXT:    mffprd 4, 0
-; PC64LE-NEXT:    mtfprd 0, 3
-; PC64LE-NEXT:    mtfprd 1, 4
-; PC64LE-NEXT:    xscvsxdsp 0, 0
-; PC64LE-NEXT:    xscvsxdsp 1, 1
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    xscvdpspn 35, 1
-; PC64LE-NEXT:    vmrghw 2, 2, 3
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mfvsrd 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE-NEXT:    mffprd 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprd 1, 4 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvsxdsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v2f32_v2i64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mfvsrld 3, 34
-; PC64LE9-NEXT:    mtfprd 0, 3
-; PC64LE9-NEXT:    mfvsrd 3, 34
-; PC64LE9-NEXT:    xscvsxdsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    mtfprd 0, 3
-; PC64LE9-NEXT:    xscvsxdsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 0
-; PC64LE9-NEXT:    vmrghw 2, 2, 3
+; PC64LE9-NEXT:    mfvsrld 3, 34 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    mfvsrd 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE9-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x float>
            @llvm.experimental.constrained.sitofp.v2f32.v2i64(<2 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <2 x float> %result
 }
 
 define <3 x double> @constrained_vector_sitofp_v3f64_v3i32(<3 x i32> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v3f64_v3i32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1
-; PC64LE-NEXT:    mfvsrwz 3, 34
-; PC64LE-NEXT:    mtfprwa 3, 3
-; PC64LE-NEXT:    mffprwz 3, 0
-; PC64LE-NEXT:    mffprwz 4, 1
-; PC64LE-NEXT:    mtfprwa 0, 3
-; PC64LE-NEXT:    mtfprwa 2, 4
-; PC64LE-NEXT:    xscvsxddp 1, 0
-; PC64LE-NEXT:    xscvsxddp 2, 2
-; PC64LE-NEXT:    xscvsxddp 3, 3
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mfvsrwz 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE-NEXT:    mtfprwa 3, 3 # Vec Defs: F3(VSR3)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprwa 2, 4 # Vec Defs: F2(VSR2)
+; PC64LE-NEXT:    xscvsxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvsxddp 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xscvsxddp 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v3f64_v3i32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    li 3, 0
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    mtfprwa 0, 3
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
 ; PC64LE9-NEXT:    li 3, 4
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    xscvsxddp 1, 0
-; PC64LE9-NEXT:    mtfprwa 0, 3
-; PC64LE9-NEXT:    mfvsrwz 3, 34
-; PC64LE9-NEXT:    xscvsxddp 2, 0
-; PC64LE9-NEXT:    mtfprwa 0, 3
-; PC64LE9-NEXT:    xscvsxddp 3, 0
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    xscvsxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    mfvsrwz 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE9-NEXT:    xscvsxddp 2, 0 # Vec Defs: F2(VSR2) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvsxddp 3, 0 # Vec Defs: F3(VSR3) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x double>
            @llvm.experimental.constrained.sitofp.v3f64.v3i32(<3 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <3 x double> %result
 }
 
 define <3 x float> @constrained_vector_sitofp_v3f32_v3i32(<3 x i32> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v3f32_v3i32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1
-; PC64LE-NEXT:    mffprwz 3, 0
-; PC64LE-NEXT:    mffprwz 4, 1
-; PC64LE-NEXT:    mtfprwa 0, 3
-; PC64LE-NEXT:    mtfprwa 1, 4
-; PC64LE-NEXT:    xscvsxdsp 0, 0
-; PC64LE-NEXT:    xscvsxdsp 1, 1
-; PC64LE-NEXT:    mfvsrwz 3, 34
-; PC64LE-NEXT:    mtfprwa 2, 3
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprwa 1, 4 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvsxdsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mfvsrwz 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE-NEXT:    mtfprwa 2, 3 # Vec Defs: F2(VSR2)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI161_0@toc@ha
 ; PC64LE-NEXT:    addi 3, 3, .LCPI161_0@toc@l
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    lvx 4, 0, 3
-; PC64LE-NEXT:    xscvdpspn 35, 1
-; PC64LE-NEXT:    xscvsxdsp 0, 2
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    xscvdpspn 35, 0
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvsxdsp 0, 2 # Vec Defs: F0(VSR0) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v3f32_v3i32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    li 3, 0
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    mtfprwa 0, 3
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
 ; PC64LE9-NEXT:    li 3, 4
-; PC64LE9-NEXT:    xscvsxdsp 0, 0
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    mtfprwa 0, 3
+; PC64LE9-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI161_0@toc@ha
-; PC64LE9-NEXT:    xscvsxdsp 0, 0
+; PC64LE9-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI161_0@toc@l
-; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vmrghw 3, 4, 3
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    mfvsrwz 3, 34
-; PC64LE9-NEXT:    mtfprwa 0, 3
-; PC64LE9-NEXT:    xscvsxdsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 0
-; PC64LE9-NEXT:    vperm 2, 2, 3, 4
+; PC64LE9-NEXT:    xscvdpspn 36, 0 # Vec Defs: V4(VSR36) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vmrghw 3, 4, 3 # Vec Defs: V3(VSR35) Vec Uses: V4(VSR36)V3(VSR35)
+; PC64LE9-NEXT:    lxv 36, 0(3) # Vec Defs: V4(VSR36)
+; PC64LE9-NEXT:    mfvsrwz 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE9-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vperm 2, 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)V4(VSR36)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x float>
            @llvm.experimental.constrained.sitofp.v3f32.v3i32(<3 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <3 x float> %result
 }
 
 define <3 x double> @constrained_vector_sitofp_v3f64_v3i64(<3 x i64> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v3f64_v3i64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mtfprd 0, 3
-; PC64LE-NEXT:    mtfprd 2, 4
-; PC64LE-NEXT:    mtfprd 3, 5
-; PC64LE-NEXT:    xscvsxddp 1, 0
-; PC64LE-NEXT:    xscvsxddp 2, 2
-; PC64LE-NEXT:    xscvsxddp 3, 3
+; PC64LE-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprd 2, 4 # Vec Defs: F2(VSR2)
+; PC64LE-NEXT:    mtfprd 3, 5 # Vec Defs: F3(VSR3)
+; PC64LE-NEXT:    xscvsxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvsxddp 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xscvsxddp 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v3f64_v3i64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mtfprd 0, 3
-; PC64LE9-NEXT:    xscvsxddp 1, 0
-; PC64LE9-NEXT:    mtfprd 0, 4
-; PC64LE9-NEXT:    xscvsxddp 2, 0
-; PC64LE9-NEXT:    mtfprd 0, 5
-; PC64LE9-NEXT:    xscvsxddp 3, 0
+; PC64LE9-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvsxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprd 0, 4 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvsxddp 2, 0 # Vec Defs: F2(VSR2) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprd 0, 5 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvsxddp 3, 0 # Vec Defs: F3(VSR3) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x double>
            @llvm.experimental.constrained.sitofp.v3f64.v3i64(<3 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <3 x double> %result
 }
 
 define <3 x float> @constrained_vector_sitofp_v3f32_v3i64(<3 x i64> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v3f32_v3i64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mtfprd 0, 3
+; PC64LE-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI163_0@toc@ha
-; PC64LE-NEXT:    mtfprd 1, 4
+; PC64LE-NEXT:    mtfprd 1, 4 # Vec Defs: F1(VSR1)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI163_0@toc@l
-; PC64LE-NEXT:    xscvsxdsp 0, 0
-; PC64LE-NEXT:    lvx 4, 0, 3
-; PC64LE-NEXT:    xscvsxdsp 1, 1
-; PC64LE-NEXT:    mtfprd 2, 5
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    xscvdpspn 35, 1
-; PC64LE-NEXT:    xscvsxdsp 0, 2
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    xscvdpspn 35, 0
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
+; PC64LE-NEXT:    xscvsxdsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprd 2, 5 # Vec Defs: F2(VSR2)
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvsxdsp 0, 2 # Vec Defs: F0(VSR0) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v3f32_v3i64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mtfprd 0, 3
+; PC64LE9-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI163_0@toc@ha
-; PC64LE9-NEXT:    xscvsxdsp 0, 0
+; PC64LE9-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI163_0@toc@l
-; PC64LE9-NEXT:    xscvdpspn 34, 0
-; PC64LE9-NEXT:    mtfprd 0, 4
-; PC64LE9-NEXT:    xscvsxdsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    mtfprd 0, 5
-; PC64LE9-NEXT:    xscvsxdsp 0, 0
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprd 0, 4 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprd 0, 5 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    xscvdpspn 36, 0 # Vec Defs: V4(VSR36) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x float>
            @llvm.experimental.constrained.sitofp.v3f32.v3i64(<3 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <3 x float> %result
 }
 
 define <4 x double> @constrained_vector_sitofp_v4f64_v4i32(<4 x i32> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v4f64_v4i32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    mfvsrwz 3, 34
-; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1
-; PC64LE-NEXT:    mtfprwa 2, 3
-; PC64LE-NEXT:    mffprwz 3, 0
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    mffprwz 4, 1
-; PC64LE-NEXT:    mtfprwa 1, 3
-; PC64LE-NEXT:    mffprwz 3, 0
-; PC64LE-NEXT:    mtfprwa 3, 4
-; PC64LE-NEXT:    xscvsxddp 0, 2
-; PC64LE-NEXT:    mtfprwa 2, 3
-; PC64LE-NEXT:    xscvsxddp 1, 1
-; PC64LE-NEXT:    xscvsxddp 3, 3
-; PC64LE-NEXT:    xscvsxddp 2, 2
-; PC64LE-NEXT:    xxmrghd 34, 3, 1
-; PC64LE-NEXT:    xxmrghd 35, 2, 0
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mfvsrwz 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mtfprwa 2, 3 # Vec Defs: F2(VSR2)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mffprwz 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprwa 1, 3 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mtfprwa 3, 4 # Vec Defs: F3(VSR3)
+; PC64LE-NEXT:    xscvsxddp 0, 2 # Vec Defs: F0(VSR0) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    mtfprwa 2, 3 # Vec Defs: F2(VSR2)
+; PC64LE-NEXT:    xscvsxddp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvsxddp 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    xscvsxddp 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xxmrghd 34, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: VSL3(VSR3)VSL1(VSR1)
+; PC64LE-NEXT:    xxmrghd 35, 2, 0 # Vec Defs: V3(VSR35) Vec Uses: VSL2(VSR2)VSL0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v4f64_v4i32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    li 3, 0
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    mtfprwa 0, 3
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    mtfprwa 0, 3 # Vec Defs: F0(VSR0)
 ; PC64LE9-NEXT:    li 3, 4
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    xscvsxddp 0, 0
-; PC64LE9-NEXT:    mtfprwa 1, 3
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    xscvsxddp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprwa 1, 3 # Vec Defs: F1(VSR1)
 ; PC64LE9-NEXT:    li 3, 12
-; PC64LE9-NEXT:    xscvsxddp 1, 1
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    xxmrghd 0, 1, 0
-; PC64LE9-NEXT:    mtfprwa 1, 3
-; PC64LE9-NEXT:    mfvsrwz 3, 34
-; PC64LE9-NEXT:    mtfprwa 2, 3
-; PC64LE9-NEXT:    xscvsxddp 1, 1
-; PC64LE9-NEXT:    xscvsxddp 2, 2
-; PC64LE9-NEXT:    xxlor 34, 0, 0
-; PC64LE9-NEXT:    xxmrghd 35, 1, 2
+; PC64LE9-NEXT:    xscvsxddp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    xxmrghd 0, 1, 0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE9-NEXT:    mtfprwa 1, 3 # Vec Defs: F1(VSR1)
+; PC64LE9-NEXT:    mfvsrwz 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE9-NEXT:    mtfprwa 2, 3 # Vec Defs: F2(VSR2)
+; PC64LE9-NEXT:    xscvsxddp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvsxddp 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    xxlor 34, 0, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PC64LE9-NEXT:    xxmrghd 35, 1, 2 # Vec Defs: V3(VSR35) Vec Uses: VSL1(VSR1)VSL2(VSR2)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x double>
            @llvm.experimental.constrained.sitofp.v4f64.v4i32(<4 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <4 x double> %result
 }
 
 define <4 x float> @constrained_vector_sitofp_v4f32_v4i16(<4 x i16> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v4f32_v4i16:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    vmrglh 2, 2, 2
-; PC64LE-NEXT:    vspltisw 3, 8
-; PC64LE-NEXT:    vadduwm 3, 3, 3
-; PC64LE-NEXT:    vslw 2, 2, 3
-; PC64LE-NEXT:    vsraw 2, 2, 3
-; PC64LE-NEXT:    xvcvsxwsp 34, 34
+; PC64LE-NEXT:    vmrglh 2, 2, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    vspltisw 3, 8 # Vec Defs: V3(VSR35)
+; PC64LE-NEXT:    vadduwm 3, 3, 3 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    vslw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    vsraw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xvcvsxwsp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v4f32_v4i16:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    vmrglh 2, 2, 2
-; PC64LE9-NEXT:    vextsh2w 2, 2
-; PC64LE9-NEXT:    xvcvsxwsp 34, 34
+; PC64LE9-NEXT:    vmrglh 2, 2, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE9-NEXT:    vextsh2w 2, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    xvcvsxwsp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x float>
          @llvm.experimental.constrained.sitofp.v4f32.v4i16(<4 x i16> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <4 x float> %result
 }
 
 define <4 x float> @constrained_vector_sitofp_v4f32_v4i32(<4 x i32> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v4f32_v4i32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvcvsxwsp 34, 34
+; PC64LE-NEXT:    xvcvsxwsp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v4f32_v4i32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvcvsxwsp 34, 34
+; PC64LE9-NEXT:    xvcvsxwsp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x float>
            @llvm.experimental.constrained.sitofp.v4f32.v4i32(<4 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <4 x float> %result
 }
 
 define <4 x double> @constrained_vector_sitofp_v4f64_v4i64(<4 x i64> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v4f64_v4i64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvcvsxddp 35, 35
-; PC64LE-NEXT:    xvcvsxddp 34, 34
+; PC64LE-NEXT:    xvcvsxddp 35, 35 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)
+; PC64LE-NEXT:    xvcvsxddp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v4f64_v4i64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvcvsxddp 35, 35
-; PC64LE9-NEXT:    xvcvsxddp 34, 34
+; PC64LE9-NEXT:    xvcvsxddp 35, 35 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)
+; PC64LE9-NEXT:    xvcvsxddp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x double>
            @llvm.experimental.constrained.sitofp.v4f64.v4i64(<4 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <4 x double> %result
 }
 
 define <4 x float> @constrained_vector_sitofp_v4f32_v4i64(<4 x i64> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_sitofp_v4f32_v4i64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    mfvsrd 3, 34
-; PC64LE-NEXT:    xxswapd 2, 35
-; PC64LE-NEXT:    mfvsrd 4, 35
-; PC64LE-NEXT:    mtfprd 1, 3
-; PC64LE-NEXT:    mffprd 3, 0
-; PC64LE-NEXT:    mtfprd 0, 4
-; PC64LE-NEXT:    mtfprd 3, 3
-; PC64LE-NEXT:    mffprd 3, 2
-; PC64LE-NEXT:    xscvsxdsp 1, 1
-; PC64LE-NEXT:    mtfprd 2, 3
-; PC64LE-NEXT:    xscvsxdsp 0, 0
-; PC64LE-NEXT:    xscvsxdsp 3, 3
-; PC64LE-NEXT:    xscvsxdsp 2, 2
-; PC64LE-NEXT:    xxmrghd 0, 0, 1
-; PC64LE-NEXT:    xxmrghd 1, 2, 3
-; PC64LE-NEXT:    xvcvdpsp 34, 0
-; PC64LE-NEXT:    xvcvdpsp 35, 1
-; PC64LE-NEXT:    vmrgew 2, 2, 3
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mfvsrd 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE-NEXT:    xxswapd 2, 35 # Vec Defs: VSL2(VSR2) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    mfvsrd 4, 35 # Vec Uses: VF3(VSR3)
+; PC64LE-NEXT:    mtfprd 1, 3 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mtfprd 0, 4 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprd 3, 3 # Vec Defs: F3(VSR3)
+; PC64LE-NEXT:    mffprd 3, 2 # Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xscvsxdsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprd 2, 3 # Vec Defs: F2(VSR2)
+; PC64LE-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvsxdsp 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    xscvsxdsp 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xxmrghd 0, 0, 1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PC64LE-NEXT:    xxmrghd 1, 2, 3 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL3(VSR3)
+; PC64LE-NEXT:    xvcvdpsp 34, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xvcvdpsp 35, 1 # Vec Defs: V3(VSR35) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    vmrgew 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v4f32_v4i64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mfvsrld 3, 34
-; PC64LE9-NEXT:    mtfprd 0, 3
-; PC64LE9-NEXT:    mfvsrld 3, 35
-; PC64LE9-NEXT:    xscvsxdsp 0, 0
-; PC64LE9-NEXT:    mtfprd 1, 3
-; PC64LE9-NEXT:    mfvsrd 3, 34
-; PC64LE9-NEXT:    xscvsxdsp 1, 1
-; PC64LE9-NEXT:    xxmrghd 0, 1, 0
-; PC64LE9-NEXT:    xvcvdpsp 36, 0
-; PC64LE9-NEXT:    mtfprd 0, 3
-; PC64LE9-NEXT:    mfvsrd 3, 35
-; PC64LE9-NEXT:    mtfprd 1, 3
-; PC64LE9-NEXT:    xscvsxdsp 0, 0
-; PC64LE9-NEXT:    xscvsxdsp 1, 1
-; PC64LE9-NEXT:    xxmrghd 0, 1, 0
-; PC64LE9-NEXT:    xvcvdpsp 34, 0
-; PC64LE9-NEXT:    vmrgew 2, 2, 4
+; PC64LE9-NEXT:    mfvsrld 3, 34 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    mfvsrld 3, 35 # Vec Uses: V3(VSR35)
+; PC64LE9-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprd 1, 3 # Vec Defs: F1(VSR1)
+; PC64LE9-NEXT:    mfvsrd 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE9-NEXT:    xscvsxdsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxmrghd 0, 1, 0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE9-NEXT:    xvcvdpsp 36, 0 # Vec Defs: V4(VSR36) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    mfvsrd 3, 35 # Vec Uses: VF3(VSR3)
+; PC64LE9-NEXT:    mtfprd 1, 3 # Vec Defs: F1(VSR1)
+; PC64LE9-NEXT:    xscvsxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvsxdsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxmrghd 0, 1, 0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE9-NEXT:    xvcvdpsp 34, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    vmrgew 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x float>
            @llvm.experimental.constrained.sitofp.v4f32.v4i64(<4 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <4 x float> %result
 }
 
 define <1 x double> @constrained_vector_uitofp_v1f64_v1i32(<1 x i32> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v1f64_v1i32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mtfprwz 0, 3
-; PC64LE-NEXT:    xscvuxddp 1, 0
+; PC64LE-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    xscvuxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v1f64_v1i32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mtfprwz 0, 3
-; PC64LE9-NEXT:    xscvuxddp 1, 0
+; PC64LE9-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvuxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x double>
            @llvm.experimental.constrained.uitofp.v1f64.v1i32(<1 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <1 x double> %result
 }
 
 define <1 x float> @constrained_vector_uitofp_v1f32_v1i32(<1 x i32> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v1f32_v1i32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mtfprwz 0, 3
-; PC64LE-NEXT:    xscvuxdsp 1, 0
+; PC64LE-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    xscvuxdsp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v1f32_v1i32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mtfprwz 0, 3
-; PC64LE9-NEXT:    xscvuxdsp 1, 0
+; PC64LE9-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvuxdsp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x float>
            @llvm.experimental.constrained.uitofp.v1f32.v1i32(<1 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <1 x float> %result
 }
 
 define <1 x double> @constrained_vector_uitofp_v1f64_v1i64(<1 x i64> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v1f64_v1i64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mtfprd 0, 3
-; PC64LE-NEXT:    xscvuxddp 1, 0
+; PC64LE-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    xscvuxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v1f64_v1i64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mtfprd 0, 3
-; PC64LE9-NEXT:    xscvuxddp 1, 0
+; PC64LE9-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvuxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x double>
            @llvm.experimental.constrained.uitofp.v1f64.v1i64(<1 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <1 x double> %result
 }
 
 define <1 x float> @constrained_vector_uitofp_v1f32_v1i64(<1 x i64> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v1f32_v1i64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mtfprd 0, 3
-; PC64LE-NEXT:    xscvuxdsp 1, 0
+; PC64LE-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    xscvuxdsp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v1f32_v1i64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mtfprd 0, 3
-; PC64LE9-NEXT:    xscvuxdsp 1, 0
+; PC64LE9-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvuxdsp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x float>
            @llvm.experimental.constrained.uitofp.v1f32.v1i64(<1 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <1 x float> %result
 }
 
 define <2 x double> @constrained_vector_uitofp_v2f64_v2i16(<2 x i16> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v2f64_v2i16:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI173_0@toc@ha
-; PC64LE-NEXT:    xxlxor 36, 36, 36
+; PC64LE-NEXT:    xxlxor 36, 36, 36 # Vec Defs: V4(VSR36)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI173_0@toc@l
-; PC64LE-NEXT:    lvx 3, 0, 3
-; PC64LE-NEXT:    vperm 2, 4, 2, 3
-; PC64LE-NEXT:    xvcvuxddp 34, 34
+; PC64LE-NEXT:    lvx 3, 0, 3 # Vec Defs: V3(VSR35)
+; PC64LE-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
+; PC64LE-NEXT:    xvcvuxddp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v2f64_v2i16:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI173_0@toc@ha
-; PC64LE9-NEXT:    xxlxor 36, 36, 36
+; PC64LE9-NEXT:    xxlxor 36, 36, 36 # Vec Defs: V4(VSR36)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI173_0@toc@l
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
-; PC64LE9-NEXT:    xvcvuxddp 34, 34
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
+; PC64LE9-NEXT:    xvcvuxddp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x double>
            @llvm.experimental.constrained.uitofp.v2f64.v2i16(<2 x i16> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <2 x double> %result
 }
 
 define <2 x double> @constrained_vector_uitofp_v2f64_v2i32(<2 x i32> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v2f64_v2i32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1
-; PC64LE-NEXT:    mffprwz 3, 0
-; PC64LE-NEXT:    mffprwz 4, 1
-; PC64LE-NEXT:    mtfprwz 0, 3
-; PC64LE-NEXT:    mtfprwz 1, 4
-; PC64LE-NEXT:    xscvuxddp 0, 0
-; PC64LE-NEXT:    xscvuxddp 1, 1
-; PC64LE-NEXT:    xxmrghd 34, 1, 0
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprwz 1, 4 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    xscvuxddp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvuxddp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xxmrghd 34, 1, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL1(VSR1)VSL0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v2f64_v2i32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    li 3, 0
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    mtfprwz 0, 3
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
 ; PC64LE9-NEXT:    li 3, 4
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    xscvuxddp 0, 0
-; PC64LE9-NEXT:    mtfprwz 1, 3
-; PC64LE9-NEXT:    xscvuxddp 1, 1
-; PC64LE9-NEXT:    xxmrghd 34, 1, 0
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    xscvuxddp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprwz 1, 3 # Vec Defs: F1(VSR1)
+; PC64LE9-NEXT:    xscvuxddp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxmrghd 34, 1, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL1(VSR1)VSL0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x double>
            @llvm.experimental.constrained.uitofp.v2f64.v2i32(<2 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <2 x double> %result
 }
 
 define <2 x float> @constrained_vector_uitofp_v2f32_v2i32(<2 x i32> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v2f32_v2i32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1
-; PC64LE-NEXT:    mffprwz 3, 0
-; PC64LE-NEXT:    mffprwz 4, 1
-; PC64LE-NEXT:    mtfprwz 0, 3
-; PC64LE-NEXT:    mtfprwz 1, 4
-; PC64LE-NEXT:    xscvuxdsp 0, 0
-; PC64LE-NEXT:    xscvuxdsp 1, 1
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    xscvdpspn 35, 1
-; PC64LE-NEXT:    vmrghw 2, 3, 2
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprwz 1, 4 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvuxdsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v2f32_v2i32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    li 3, 0
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    mtfprwz 0, 3
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
 ; PC64LE9-NEXT:    li 3, 4
-; PC64LE9-NEXT:    xscvuxdsp 0, 0
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    mtfprwz 0, 3
-; PC64LE9-NEXT:    xscvuxdsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 0
-; PC64LE9-NEXT:    vmrghw 2, 2, 3
+; PC64LE9-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x float>
            @llvm.experimental.constrained.uitofp.v2f32.v2i32(<2 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <2 x float> %result
 }
 
 define <2 x double> @constrained_vector_uitofp_v2f64_v2i64(<2 x i64> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v2f64_v2i64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvcvuxddp 34, 34
+; PC64LE-NEXT:    xvcvuxddp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v2f64_v2i64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvcvuxddp 34, 34
+; PC64LE9-NEXT:    xvcvuxddp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x double>
            @llvm.experimental.constrained.uitofp.v2f64.v2i64(<2 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <2 x double> %result
 }
 
 define <2 x float> @constrained_vector_uitofp_v2f32_v2i64(<2 x i64> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v2f32_v2i64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    mfvsrd 3, 34
-; PC64LE-NEXT:    mffprd 4, 0
-; PC64LE-NEXT:    mtfprd 0, 3
-; PC64LE-NEXT:    mtfprd 1, 4
-; PC64LE-NEXT:    xscvuxdsp 0, 0
-; PC64LE-NEXT:    xscvuxdsp 1, 1
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    xscvdpspn 35, 1
-; PC64LE-NEXT:    vmrghw 2, 2, 3
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mfvsrd 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE-NEXT:    mffprd 4, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprd 1, 4 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvuxdsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v2f32_v2i64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mfvsrld 3, 34
-; PC64LE9-NEXT:    mtfprd 0, 3
-; PC64LE9-NEXT:    mfvsrd 3, 34
-; PC64LE9-NEXT:    xscvuxdsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    mtfprd 0, 3
-; PC64LE9-NEXT:    xscvuxdsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 0
-; PC64LE9-NEXT:    vmrghw 2, 2, 3
+; PC64LE9-NEXT:    mfvsrld 3, 34 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    mfvsrd 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE9-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vmrghw 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x float>
            @llvm.experimental.constrained.uitofp.v2f32.v2i64(<2 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <2 x float> %result
 }
 
 define <3 x double> @constrained_vector_uitofp_v3f64_v3i32(<3 x i32> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v3f64_v3i32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1
-; PC64LE-NEXT:    mfvsrwz 3, 34
-; PC64LE-NEXT:    mtfprwz 3, 3
-; PC64LE-NEXT:    mffprwz 3, 0
-; PC64LE-NEXT:    mffprwz 4, 1
-; PC64LE-NEXT:    mtfprwz 0, 3
-; PC64LE-NEXT:    mtfprwz 2, 4
-; PC64LE-NEXT:    xscvuxddp 1, 0
-; PC64LE-NEXT:    xscvuxddp 2, 2
-; PC64LE-NEXT:    xscvuxddp 3, 3
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mfvsrwz 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE-NEXT:    mtfprwz 3, 3 # Vec Defs: F3(VSR3)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprwz 2, 4 # Vec Defs: F2(VSR2)
+; PC64LE-NEXT:    xscvuxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvuxddp 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xscvuxddp 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v3f64_v3i32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    li 3, 0
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    mtfprwz 0, 3
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
 ; PC64LE9-NEXT:    li 3, 4
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    xscvuxddp 1, 0
-; PC64LE9-NEXT:    mtfprwz 0, 3
-; PC64LE9-NEXT:    mfvsrwz 3, 34
-; PC64LE9-NEXT:    xscvuxddp 2, 0
-; PC64LE9-NEXT:    mtfprwz 0, 3
-; PC64LE9-NEXT:    xscvuxddp 3, 0
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    xscvuxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    mfvsrwz 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE9-NEXT:    xscvuxddp 2, 0 # Vec Defs: F2(VSR2) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvuxddp 3, 0 # Vec Defs: F3(VSR3) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x double>
            @llvm.experimental.constrained.uitofp.v3f64.v3i32(<3 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <3 x double> %result
 }
 
 define <3 x float> @constrained_vector_uitofp_v3f32_v3i32(<3 x i32> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v3f32_v3i32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1
-; PC64LE-NEXT:    mffprwz 3, 0
-; PC64LE-NEXT:    mffprwz 4, 1
-; PC64LE-NEXT:    mtfprwz 0, 3
-; PC64LE-NEXT:    mtfprwz 1, 4
-; PC64LE-NEXT:    xscvuxdsp 0, 0
-; PC64LE-NEXT:    xscvuxdsp 1, 1
-; PC64LE-NEXT:    mfvsrwz 3, 34
-; PC64LE-NEXT:    mtfprwz 2, 3
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mffprwz 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprwz 1, 4 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvuxdsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mfvsrwz 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE-NEXT:    mtfprwz 2, 3 # Vec Defs: F2(VSR2)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI179_0@toc@ha
 ; PC64LE-NEXT:    addi 3, 3, .LCPI179_0@toc@l
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    lvx 4, 0, 3
-; PC64LE-NEXT:    xscvdpspn 35, 1
-; PC64LE-NEXT:    xscvuxdsp 0, 2
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    xscvdpspn 35, 0
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvuxdsp 0, 2 # Vec Defs: F0(VSR0) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v3f32_v3i32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    li 3, 0
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    mtfprwz 0, 3
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
 ; PC64LE9-NEXT:    li 3, 4
-; PC64LE9-NEXT:    xscvuxdsp 0, 0
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    mtfprwz 0, 3
+; PC64LE9-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI179_0@toc@ha
-; PC64LE9-NEXT:    xscvuxdsp 0, 0
+; PC64LE9-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI179_0@toc@l
-; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vmrghw 3, 4, 3
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    mfvsrwz 3, 34
-; PC64LE9-NEXT:    mtfprwz 0, 3
-; PC64LE9-NEXT:    xscvuxdsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 0
-; PC64LE9-NEXT:    vperm 2, 2, 3, 4
+; PC64LE9-NEXT:    xscvdpspn 36, 0 # Vec Defs: V4(VSR36) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vmrghw 3, 4, 3 # Vec Defs: V3(VSR35) Vec Uses: V4(VSR36)V3(VSR35)
+; PC64LE9-NEXT:    lxv 36, 0(3) # Vec Defs: V4(VSR36)
+; PC64LE9-NEXT:    mfvsrwz 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE9-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vperm 2, 2, 3, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)V4(VSR36)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x float>
            @llvm.experimental.constrained.uitofp.v3f32.v3i32(<3 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <3 x float> %result
 }
 
 define <3 x double> @constrained_vector_uitofp_v3f64_v3i64(<3 x i64> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v3f64_v3i64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mtfprd 0, 3
-; PC64LE-NEXT:    mtfprd 2, 4
-; PC64LE-NEXT:    mtfprd 3, 5
-; PC64LE-NEXT:    xscvuxddp 1, 0
-; PC64LE-NEXT:    xscvuxddp 2, 2
-; PC64LE-NEXT:    xscvuxddp 3, 3
+; PC64LE-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprd 2, 4 # Vec Defs: F2(VSR2)
+; PC64LE-NEXT:    mtfprd 3, 5 # Vec Defs: F3(VSR3)
+; PC64LE-NEXT:    xscvuxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvuxddp 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xscvuxddp 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v3f64_v3i64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mtfprd 0, 3
-; PC64LE9-NEXT:    xscvuxddp 1, 0
-; PC64LE9-NEXT:    mtfprd 0, 4
-; PC64LE9-NEXT:    xscvuxddp 2, 0
-; PC64LE9-NEXT:    mtfprd 0, 5
-; PC64LE9-NEXT:    xscvuxddp 3, 0
+; PC64LE9-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvuxddp 1, 0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprd 0, 4 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvuxddp 2, 0 # Vec Defs: F2(VSR2) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprd 0, 5 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvuxddp 3, 0 # Vec Defs: F3(VSR3) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x double>
            @llvm.experimental.constrained.uitofp.v3f64.v3i64(<3 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <3 x double> %result
 }
 
 define <3 x float> @constrained_vector_uitofp_v3f32_v3i64(<3 x i64> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v3f32_v3i64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mtfprd 0, 3
+; PC64LE-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI181_0@toc@ha
-; PC64LE-NEXT:    mtfprd 1, 4
+; PC64LE-NEXT:    mtfprd 1, 4 # Vec Defs: F1(VSR1)
 ; PC64LE-NEXT:    addi 3, 3, .LCPI181_0@toc@l
-; PC64LE-NEXT:    xscvuxdsp 0, 0
-; PC64LE-NEXT:    lvx 4, 0, 3
-; PC64LE-NEXT:    xscvuxdsp 1, 1
-; PC64LE-NEXT:    mtfprd 2, 5
-; PC64LE-NEXT:    xscvdpspn 34, 0
-; PC64LE-NEXT:    xscvdpspn 35, 1
-; PC64LE-NEXT:    xscvuxdsp 0, 2
-; PC64LE-NEXT:    vmrghw 2, 3, 2
-; PC64LE-NEXT:    xscvdpspn 35, 0
-; PC64LE-NEXT:    vperm 2, 3, 2, 4
+; PC64LE-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    lvx 4, 0, 3 # Vec Defs: V4(VSR36)
+; PC64LE-NEXT:    xscvuxdsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprd 2, 5 # Vec Defs: F2(VSR2)
+; PC64LE-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvdpspn 35, 1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvuxdsp 0, 2 # Vec Defs: F0(VSR0) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    vperm 2, 3, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v3f32_v3i64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mtfprd 0, 3
+; PC64LE9-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI181_0@toc@ha
-; PC64LE9-NEXT:    xscvuxdsp 0, 0
+; PC64LE9-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI181_0@toc@l
-; PC64LE9-NEXT:    xscvdpspn 34, 0
-; PC64LE9-NEXT:    mtfprd 0, 4
-; PC64LE9-NEXT:    xscvuxdsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    mtfprd 0, 5
-; PC64LE9-NEXT:    xscvuxdsp 0, 0
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xscvdpspn 34, 0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprd 0, 4 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvdpspn 35, 0 # Vec Defs: V3(VSR35) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprd 0, 5 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    lxv 35, 0(3) # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    xscvdpspn 36, 0 # Vec Defs: V4(VSR36) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    vperm 2, 4, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x float>
            @llvm.experimental.constrained.uitofp.v3f32.v3i64(<3 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <3 x float> %result
 }
 
 define <4 x double> @constrained_vector_uitofp_v4f64_v4i32(<4 x i32> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v4f64_v4i32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    mfvsrwz 3, 34
-; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1
-; PC64LE-NEXT:    mtfprwz 2, 3
-; PC64LE-NEXT:    mffprwz 3, 0
-; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3
-; PC64LE-NEXT:    mffprwz 4, 1
-; PC64LE-NEXT:    mtfprwz 1, 3
-; PC64LE-NEXT:    mffprwz 3, 0
-; PC64LE-NEXT:    mtfprwz 3, 4
-; PC64LE-NEXT:    xscvuxddp 0, 2
-; PC64LE-NEXT:    mtfprwz 2, 3
-; PC64LE-NEXT:    xscvuxddp 1, 1
-; PC64LE-NEXT:    xscvuxddp 3, 3
-; PC64LE-NEXT:    xscvuxddp 2, 2
-; PC64LE-NEXT:    xxmrghd 34, 3, 1
-; PC64LE-NEXT:    xxmrghd 35, 2, 0
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mfvsrwz 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE-NEXT:    xxsldwi 1, 34, 34, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mtfprwz 2, 3 # Vec Defs: F2(VSR2)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xxsldwi 0, 34, 34, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mffprwz 4, 1 # Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprwz 1, 3 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    mffprwz 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mtfprwz 3, 4 # Vec Defs: F3(VSR3)
+; PC64LE-NEXT:    xscvuxddp 0, 2 # Vec Defs: F0(VSR0) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    mtfprwz 2, 3 # Vec Defs: F2(VSR2)
+; PC64LE-NEXT:    xscvuxddp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    xscvuxddp 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    xscvuxddp 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xxmrghd 34, 3, 1 # Vec Defs: V2(VSR34) Vec Uses: VSL3(VSR3)VSL1(VSR1)
+; PC64LE-NEXT:    xxmrghd 35, 2, 0 # Vec Defs: V3(VSR35) Vec Uses: VSL2(VSR2)VSL0(VSR0)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v4f64_v4i32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    li 3, 0
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    mtfprwz 0, 3
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    mtfprwz 0, 3 # Vec Defs: F0(VSR0)
 ; PC64LE9-NEXT:    li 3, 4
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    xscvuxddp 0, 0
-; PC64LE9-NEXT:    mtfprwz 1, 3
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    xscvuxddp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprwz 1, 3 # Vec Defs: F1(VSR1)
 ; PC64LE9-NEXT:    li 3, 12
-; PC64LE9-NEXT:    xscvuxddp 1, 1
-; PC64LE9-NEXT:    vextuwrx 3, 3, 2
-; PC64LE9-NEXT:    xxmrghd 0, 1, 0
-; PC64LE9-NEXT:    mtfprwz 1, 3
-; PC64LE9-NEXT:    mfvsrwz 3, 34
-; PC64LE9-NEXT:    mtfprwz 2, 3
-; PC64LE9-NEXT:    xscvuxddp 1, 1
-; PC64LE9-NEXT:    xscvuxddp 2, 2
-; PC64LE9-NEXT:    xxlor 34, 0, 0
-; PC64LE9-NEXT:    xxmrghd 35, 1, 2
+; PC64LE9-NEXT:    xscvuxddp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    vextuwrx 3, 3, 2 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    xxmrghd 0, 1, 0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE9-NEXT:    mtfprwz 1, 3 # Vec Defs: F1(VSR1)
+; PC64LE9-NEXT:    mfvsrwz 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE9-NEXT:    mtfprwz 2, 3 # Vec Defs: F2(VSR2)
+; PC64LE9-NEXT:    xscvuxddp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xscvuxddp 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE9-NEXT:    xxlor 34, 0, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PC64LE9-NEXT:    xxmrghd 35, 1, 2 # Vec Defs: V3(VSR35) Vec Uses: VSL1(VSR1)VSL2(VSR2)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x double>
            @llvm.experimental.constrained.uitofp.v4f64.v4i32(<4 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <4 x double> %result
 }
 
 define <4 x float> @constrained_vector_uitofp_v4f32_v4i16(<4 x i16> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v4f32_v4i16:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxlxor 35, 35, 35
-; PC64LE-NEXT:    vmrglh 2, 3, 2
-; PC64LE-NEXT:    xvcvuxwsp 34, 34
+; PC64LE-NEXT:    xxlxor 35, 35, 35 # Vec Defs: V3(VSR35)
+; PC64LE-NEXT:    vmrglh 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE-NEXT:    xvcvuxwsp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v4f32_v4i16:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xxlxor 35, 35, 35
-; PC64LE9-NEXT:    vmrglh 2, 3, 2
-; PC64LE9-NEXT:    xvcvuxwsp 34, 34
+; PC64LE9-NEXT:    xxlxor 35, 35, 35 # Vec Defs: V3(VSR35)
+; PC64LE9-NEXT:    vmrglh 2, 3, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
+; PC64LE9-NEXT:    xvcvuxwsp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x float>
          @llvm.experimental.constrained.uitofp.v4f32.v4i16(<4 x i16> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <4 x float> %result
 }
 
 define <4 x float> @constrained_vector_uitofp_v4f32_v4i32(<4 x i32> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v4f32_v4i32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvcvuxwsp 34, 34
+; PC64LE-NEXT:    xvcvuxwsp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v4f32_v4i32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvcvuxwsp 34, 34
+; PC64LE9-NEXT:    xvcvuxwsp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x float>
            @llvm.experimental.constrained.uitofp.v4f32.v4i32(<4 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <4 x float> %result
 }
 
 define <4 x double> @constrained_vector_uitofp_v4f64_v4i64(<4 x i64> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v4f64_v4i64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xvcvuxddp 35, 35
-; PC64LE-NEXT:    xvcvuxddp 34, 34
+; PC64LE-NEXT:    xvcvuxddp 35, 35 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)
+; PC64LE-NEXT:    xvcvuxddp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v4f64_v4i64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    xvcvuxddp 35, 35
-; PC64LE9-NEXT:    xvcvuxddp 34, 34
+; PC64LE9-NEXT:    xvcvuxddp 35, 35 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)
+; PC64LE9-NEXT:    xvcvuxddp 34, 34 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x double>
            @llvm.experimental.constrained.uitofp.v4f64.v4i64(<4 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <4 x double> %result
 }
 
 define <4 x float> @constrained_vector_uitofp_v4f32_v4i64(<4 x i64> %x) #0 {
 ; PC64LE-LABEL: constrained_vector_uitofp_v4f32_v4i64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    xxswapd 0, 34
-; PC64LE-NEXT:    mfvsrd 3, 34
-; PC64LE-NEXT:    xxswapd 2, 35
-; PC64LE-NEXT:    mfvsrd 4, 35
-; PC64LE-NEXT:    mtfprd 1, 3
-; PC64LE-NEXT:    mffprd 3, 0
-; PC64LE-NEXT:    mtfprd 0, 4
-; PC64LE-NEXT:    mtfprd 3, 3
-; PC64LE-NEXT:    mffprd 3, 2
-; PC64LE-NEXT:    xscvuxdsp 1, 1
-; PC64LE-NEXT:    mtfprd 2, 3
-; PC64LE-NEXT:    xscvuxdsp 0, 0
-; PC64LE-NEXT:    xscvuxdsp 3, 3
-; PC64LE-NEXT:    xscvuxdsp 2, 2
-; PC64LE-NEXT:    xxmrghd 0, 0, 1
-; PC64LE-NEXT:    xxmrghd 1, 2, 3
-; PC64LE-NEXT:    xvcvdpsp 34, 0
-; PC64LE-NEXT:    xvcvdpsp 35, 1
-; PC64LE-NEXT:    vmrgew 2, 2, 3
+; PC64LE-NEXT:    xxswapd 0, 34 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PC64LE-NEXT:    mfvsrd 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE-NEXT:    xxswapd 2, 35 # Vec Defs: VSL2(VSR2) Vec Uses: V3(VSR35)V3(VSR35)
+; PC64LE-NEXT:    mfvsrd 4, 35 # Vec Uses: VF3(VSR3)
+; PC64LE-NEXT:    mtfprd 1, 3 # Vec Defs: F1(VSR1)
+; PC64LE-NEXT:    mffprd 3, 0 # Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    mtfprd 0, 4 # Vec Defs: F0(VSR0)
+; PC64LE-NEXT:    mtfprd 3, 3 # Vec Defs: F3(VSR3)
+; PC64LE-NEXT:    mffprd 3, 2 # Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xscvuxdsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE-NEXT:    mtfprd 2, 3 # Vec Defs: F2(VSR2)
+; PC64LE-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE-NEXT:    xscvuxdsp 3, 3 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)
+; PC64LE-NEXT:    xscvuxdsp 2, 2 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)
+; PC64LE-NEXT:    xxmrghd 0, 0, 1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PC64LE-NEXT:    xxmrghd 1, 2, 3 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL3(VSR3)
+; PC64LE-NEXT:    xvcvdpsp 34, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
+; PC64LE-NEXT:    xvcvdpsp 35, 1 # Vec Defs: V3(VSR35) Vec Uses: VSL1(VSR1)
+; PC64LE-NEXT:    vmrgew 2, 2, 3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v4f32_v4i64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mfvsrld 3, 34
-; PC64LE9-NEXT:    mtfprd 0, 3
-; PC64LE9-NEXT:    mfvsrld 3, 35
-; PC64LE9-NEXT:    xscvuxdsp 0, 0
-; PC64LE9-NEXT:    mtfprd 1, 3
-; PC64LE9-NEXT:    mfvsrd 3, 34
-; PC64LE9-NEXT:    xscvuxdsp 1, 1
-; PC64LE9-NEXT:    xxmrghd 0, 1, 0
-; PC64LE9-NEXT:    xvcvdpsp 36, 0
-; PC64LE9-NEXT:    mtfprd 0, 3
-; PC64LE9-NEXT:    mfvsrd 3, 35
-; PC64LE9-NEXT:    mtfprd 1, 3
-; PC64LE9-NEXT:    xscvuxdsp 0, 0
-; PC64LE9-NEXT:    xscvuxdsp 1, 1
-; PC64LE9-NEXT:    xxmrghd 0, 1, 0
-; PC64LE9-NEXT:    xvcvdpsp 34, 0
-; PC64LE9-NEXT:    vmrgew 2, 2, 4
+; PC64LE9-NEXT:    mfvsrld 3, 34 # Vec Uses: V2(VSR34)
+; PC64LE9-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    mfvsrld 3, 35 # Vec Uses: V3(VSR35)
+; PC64LE9-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    mtfprd 1, 3 # Vec Defs: F1(VSR1)
+; PC64LE9-NEXT:    mfvsrd 3, 34 # Vec Uses: VF2(VSR2)
+; PC64LE9-NEXT:    xscvuxdsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxmrghd 0, 1, 0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE9-NEXT:    xvcvdpsp 36, 0 # Vec Defs: V4(VSR36) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    mtfprd 0, 3 # Vec Defs: F0(VSR0)
+; PC64LE9-NEXT:    mfvsrd 3, 35 # Vec Uses: VF3(VSR3)
+; PC64LE9-NEXT:    mtfprd 1, 3 # Vec Defs: F1(VSR1)
+; PC64LE9-NEXT:    xscvuxdsp 0, 0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; PC64LE9-NEXT:    xscvuxdsp 1, 1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)
+; PC64LE9-NEXT:    xxmrghd 0, 1, 0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PC64LE9-NEXT:    xvcvdpsp 34, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
+; PC64LE9-NEXT:    vmrgew 2, 2, 4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V4(VSR36)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x float>
            @llvm.experimental.constrained.uitofp.v4f32.v4i64(<4 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <4 x float> %result
 }

llvm/test/CodeGen/PowerPC/vector-reduce-fadd.ll

 ; RUN:   FileCheck %s --check-prefix=PWR10BE
 
 ;;
 ;; Vectors of f32
 ;;
 define dso_local float @v2f32(<2 x float> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v2f32:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxsldwi vs0, v2, v2, 3
-; PWR9LE-NEXT:    xxswapd vs1, v2
-; PWR9LE-NEXT:    xscvspdpn f0, vs0
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f1, f0, f1
+; PWR9LE-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v2f32:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR9BE-NEXT:    xscvspdpn f0, v2
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f1, f0, f1
+; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f0, v2 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v2f32:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxsldwi vs0, v2, v2, 3
-; PWR10LE-NEXT:    xxswapd vs1, v2
-; PWR10LE-NEXT:    xscvspdpn f0, vs0
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f1, f0, f1
+; PWR10LE-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v2f32:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR10BE-NEXT:    xscvspdpn f0, v2
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f1, f0, f1
+; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f0, v2 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call float @llvm.vector.reduce.fadd.v2f32(float -0.000000e+00, <2 x float> %a)
   ret float %0
 }
 
 define dso_local float @v2f32_b(<2 x float> %a, float %b) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v2f32_b:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxsldwi vs0, v2, v2, 3
-; PWR9LE-NEXT:    xscvspdpn f0, vs0
-; PWR9LE-NEXT:    xsaddsp f0, f1, f0
-; PWR9LE-NEXT:    xxswapd vs1, v2
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f1, f0, f1
+; PWR9LE-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PWR9LE-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR9LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v2f32_b:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xscvspdpn f0, v2
-; PWR9BE-NEXT:    xsaddsp f0, f1, f0
-; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f1, f0, f1
+; PWR9BE-NEXT:    xscvspdpn f0, v2 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PWR9BE-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v2f32_b:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxsldwi vs0, v2, v2, 3
-; PWR10LE-NEXT:    xscvspdpn f0, vs0
-; PWR10LE-NEXT:    xsaddsp f0, f1, f0
-; PWR10LE-NEXT:    xxswapd vs1, v2
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f1, f0, f1
+; PWR10LE-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PWR10LE-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR10LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v2f32_b:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xscvspdpn f0, v2
-; PWR10BE-NEXT:    xsaddsp f0, f1, f0
-; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f1, f0, f1
+; PWR10BE-NEXT:    xscvspdpn f0, v2 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PWR10BE-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call float @llvm.vector.reduce.fadd.v2f32(float %b, <2 x float> %a)
   ret float %0
 }
 
 define dso_local float @v2f32_fast(<2 x float> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v2f32_fast:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxspltw vs0, v2, 2
-; PWR9LE-NEXT:    xvaddsp vs0, v2, vs0
-; PWR9LE-NEXT:    xxsldwi vs0, vs0, vs0, 3
-; PWR9LE-NEXT:    xscvspdpn f1, vs0
+; PWR9LE-NEXT:    xxspltw vs0, v2, 2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)
+; PWR9LE-NEXT:    xvaddsp vs0, v2, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)VSL0(VSR0)
+; PWR9LE-NEXT:    xxsldwi vs0, vs0, vs0, 3 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9LE-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v2f32_fast:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xxspltw vs0, v2, 1
-; PWR9BE-NEXT:    xvaddsp vs0, v2, vs0
-; PWR9BE-NEXT:    xscvspdpn f1, vs0
+; PWR9BE-NEXT:    xxspltw vs0, v2, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)
+; PWR9BE-NEXT:    xvaddsp vs0, v2, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)VSL0(VSR0)
+; PWR9BE-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v2f32_fast:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxspltw vs0, v2, 2
-; PWR10LE-NEXT:    xvaddsp vs0, v2, vs0
-; PWR10LE-NEXT:    xxsldwi vs0, vs0, vs0, 3
-; PWR10LE-NEXT:    xscvspdpn f1, vs0
+; PWR10LE-NEXT:    xxspltw vs0, v2, 2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)
+; PWR10LE-NEXT:    xvaddsp vs0, v2, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)VSL0(VSR0)
+; PWR10LE-NEXT:    xxsldwi vs0, vs0, vs0, 3 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10LE-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v2f32_fast:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xxspltw vs0, v2, 1
-; PWR10BE-NEXT:    xvaddsp vs0, v2, vs0
-; PWR10BE-NEXT:    xscvspdpn f1, vs0
+; PWR10BE-NEXT:    xxspltw vs0, v2, 1 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)
+; PWR10BE-NEXT:    xvaddsp vs0, v2, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)VSL0(VSR0)
+; PWR10BE-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call fast float @llvm.vector.reduce.fadd.v2f32(float -0.000000e+00, <2 x float> %a)
   ret float %0
 }
 
 define dso_local float @v4f32(<4 x float> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v4f32:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxsldwi vs0, v2, v2, 3
-; PWR9LE-NEXT:    xxswapd vs1, v2
-; PWR9LE-NEXT:    xscvspdpn f0, vs0
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xscvspdpn f1, v2
-; PWR9LE-NEXT:    xsaddsp f1, f0, f1
+; PWR9LE-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xscvspdpn f1, v2 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; PWR9LE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v4f32:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR9BE-NEXT:    xscvspdpn f0, v2
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v2
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f1, f0, f1
+; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f0, v2 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v4f32:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxsldwi vs0, v2, v2, 3
-; PWR10LE-NEXT:    xxswapd vs1, v2
-; PWR10LE-NEXT:    xscvspdpn f0, vs0
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xscvspdpn f1, v2
-; PWR10LE-NEXT:    xsaddsp f1, f0, f1
+; PWR10LE-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xscvspdpn f1, v2 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; PWR10LE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v4f32:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR10BE-NEXT:    xscvspdpn f0, v2
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v2
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f1, f0, f1
+; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f0, v2 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> %a)
   ret float %0
 }
 
 define dso_local float @v4f32_b(<4 x float> %a, float %b) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v4f32_b:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxsldwi vs0, v2, v2, 3
-; PWR9LE-NEXT:    xscvspdpn f0, vs0
-; PWR9LE-NEXT:    xsaddsp f0, f1, f0
-; PWR9LE-NEXT:    xxswapd vs1, v2
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xscvspdpn f1, v2
-; PWR9LE-NEXT:    xsaddsp f1, f0, f1
+; PWR9LE-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PWR9LE-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR9LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xscvspdpn f1, v2 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; PWR9LE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v4f32_b:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xscvspdpn f0, v2
-; PWR9BE-NEXT:    xsaddsp f0, f1, f0
-; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v2
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f1, f0, f1
+; PWR9BE-NEXT:    xscvspdpn f0, v2 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PWR9BE-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v4f32_b:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxsldwi vs0, v2, v2, 3
-; PWR10LE-NEXT:    xscvspdpn f0, vs0
-; PWR10LE-NEXT:    xsaddsp f0, f1, f0
-; PWR10LE-NEXT:    xxswapd vs1, v2
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xscvspdpn f1, v2
-; PWR10LE-NEXT:    xsaddsp f1, f0, f1
+; PWR10LE-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PWR10LE-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR10LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xscvspdpn f1, v2 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; PWR10LE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v4f32_b:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xscvspdpn f0, v2
-; PWR10BE-NEXT:    xsaddsp f0, f1, f0
-; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v2
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f1, f0, f1
+; PWR10BE-NEXT:    xscvspdpn f0, v2 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PWR10BE-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call float @llvm.vector.reduce.fadd.v4f32(float %b, <4 x float> %a)
   ret float %0
 }
 
 define dso_local float @v4f32_fast(<4 x float> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v4f32_fast:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxswapd v3, v2
-; PWR9LE-NEXT:    xvaddsp vs0, v2, v3
-; PWR9LE-NEXT:    xxspltw vs1, vs0, 2
-; PWR9LE-NEXT:    xvaddsp vs0, vs0, vs1
-; PWR9LE-NEXT:    xxsldwi vs0, vs0, vs0, 3
-; PWR9LE-NEXT:    xscvspdpn f1, vs0
+; PWR9LE-NEXT:    xxswapd v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xvaddsp vs0, v2, v3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V3(VSR35)
+; PWR9LE-NEXT:    xxspltw vs1, vs0, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)
+; PWR9LE-NEXT:    xvaddsp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs0, vs0, vs0, 3 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9LE-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v4f32_fast:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xxswapd v3, v2
-; PWR9BE-NEXT:    xvaddsp vs0, v2, v3
-; PWR9BE-NEXT:    xxspltw vs1, vs0, 1
-; PWR9BE-NEXT:    xvaddsp vs0, vs0, vs1
-; PWR9BE-NEXT:    xscvspdpn f1, vs0
+; PWR9BE-NEXT:    xxswapd v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xvaddsp vs0, v2, v3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V3(VSR35)
+; PWR9BE-NEXT:    xxspltw vs1, vs0, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)
+; PWR9BE-NEXT:    xvaddsp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR9BE-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v4f32_fast:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxswapd v3, v2
-; PWR10LE-NEXT:    xvaddsp vs0, v2, v3
-; PWR10LE-NEXT:    xxspltw vs1, vs0, 2
-; PWR10LE-NEXT:    xvaddsp vs0, vs0, vs1
-; PWR10LE-NEXT:    xxsldwi vs0, vs0, vs0, 3
-; PWR10LE-NEXT:    xscvspdpn f1, vs0
+; PWR10LE-NEXT:    xxswapd v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xvaddsp vs0, v2, v3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V3(VSR35)
+; PWR10LE-NEXT:    xxspltw vs1, vs0, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)
+; PWR10LE-NEXT:    xvaddsp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs0, vs0, vs0, 3 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10LE-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v4f32_fast:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xxswapd v3, v2
-; PWR10BE-NEXT:    xvaddsp vs0, v2, v3
-; PWR10BE-NEXT:    xxspltw vs1, vs0, 1
-; PWR10BE-NEXT:    xvaddsp vs0, vs0, vs1
-; PWR10BE-NEXT:    xscvspdpn f1, vs0
+; PWR10BE-NEXT:    xxswapd v3, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xvaddsp vs0, v2, v3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V3(VSR35)
+; PWR10BE-NEXT:    xxspltw vs1, vs0, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)
+; PWR10BE-NEXT:    xvaddsp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR10BE-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> %a)
   ret float %0
 }
 
 define dso_local float @v8f32(<8 x float> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v8f32:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxsldwi vs0, v2, v2, 3
-; PWR9LE-NEXT:    xxswapd vs1, v2
-; PWR9LE-NEXT:    xscvspdpn f0, vs0
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xscvspdpn f1, v2
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v3, v3, 3
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v3
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v3, v3, 1
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xscvspdpn f1, v3
-; PWR9LE-NEXT:    xsaddsp f1, f0, f1
+; PWR9LE-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xscvspdpn f1, v2 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v3, v3, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v3, v3, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xscvspdpn f1, v3 # Vec Defs: F1(VSR1) Vec Uses: V3(VSR35)
+; PWR9LE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v8f32:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR9BE-NEXT:    xscvspdpn f0, v2
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v2
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xscvspdpn f1, v3
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v3, v3, 1
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v3, v3, 3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f1, f0, f1
+; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f0, v2 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xscvspdpn f1, v3 # Vec Defs: F1(VSR1) Vec Uses: V3(VSR35)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v3, v3, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v3, v3, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v8f32:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxsldwi vs0, v2, v2, 3
-; PWR10LE-NEXT:    xxswapd vs1, v2
-; PWR10LE-NEXT:    xscvspdpn f0, vs0
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xscvspdpn f1, v2
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v3, v3, 3
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v3
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v3, v3, 1
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xscvspdpn f1, v3
-; PWR10LE-NEXT:    xsaddsp f1, f0, f1
+; PWR10LE-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xscvspdpn f1, v2 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v3, v3, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v3, v3, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xscvspdpn f1, v3 # Vec Defs: F1(VSR1) Vec Uses: V3(VSR35)
+; PWR10LE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v8f32:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR10BE-NEXT:    xscvspdpn f0, v2
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v2
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xscvspdpn f1, v3
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v3, v3, 1
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v3, v3, 3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f1, f0, f1
+; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f0, v2 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xscvspdpn f1, v3 # Vec Defs: F1(VSR1) Vec Uses: V3(VSR35)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v3, v3, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v3, v3, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00, <8 x float> %a)
   ret float %0
 }
 
 define dso_local float @v8f32_b(<8 x float> %a, float %b) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v8f32_b:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxsldwi vs0, v2, v2, 3
-; PWR9LE-NEXT:    xscvspdpn f0, vs0
-; PWR9LE-NEXT:    xsaddsp f0, f1, f0
-; PWR9LE-NEXT:    xxswapd vs1, v2
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xscvspdpn f1, v2
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v3, v3, 3
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v3
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v3, v3, 1
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xscvspdpn f1, v3
-; PWR9LE-NEXT:    xsaddsp f1, f0, f1
+; PWR9LE-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PWR9LE-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR9LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xscvspdpn f1, v2 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v3, v3, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v3, v3, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xscvspdpn f1, v3 # Vec Defs: F1(VSR1) Vec Uses: V3(VSR35)
+; PWR9LE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v8f32_b:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xscvspdpn f0, v2
-; PWR9BE-NEXT:    xsaddsp f0, f1, f0
-; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v2
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xscvspdpn f1, v3
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v3, v3, 1
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v3, v3, 3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f1, f0, f1
+; PWR9BE-NEXT:    xscvspdpn f0, v2 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PWR9BE-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xscvspdpn f1, v3 # Vec Defs: F1(VSR1) Vec Uses: V3(VSR35)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v3, v3, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v3, v3, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v8f32_b:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxsldwi vs0, v2, v2, 3
-; PWR10LE-NEXT:    xscvspdpn f0, vs0
-; PWR10LE-NEXT:    xsaddsp f0, f1, f0
-; PWR10LE-NEXT:    xxswapd vs1, v2
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xscvspdpn f1, v2
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v3, v3, 3
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v3
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v3, v3, 1
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xscvspdpn f1, v3
-; PWR10LE-NEXT:    xsaddsp f1, f0, f1
+; PWR10LE-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PWR10LE-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR10LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xscvspdpn f1, v2 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v3, v3, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v3, v3, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xscvspdpn f1, v3 # Vec Defs: F1(VSR1) Vec Uses: V3(VSR35)
+; PWR10LE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v8f32_b:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xscvspdpn f0, v2
-; PWR10BE-NEXT:    xsaddsp f0, f1, f0
-; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v2
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xscvspdpn f1, v3
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v3, v3, 1
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v3, v3, 3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f1, f0, f1
+; PWR10BE-NEXT:    xscvspdpn f0, v2 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PWR10BE-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xscvspdpn f1, v3 # Vec Defs: F1(VSR1) Vec Uses: V3(VSR35)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v3, v3, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v3, v3, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call float @llvm.vector.reduce.fadd.v8f32(float %b, <8 x float> %a)
   ret float %0
 }
 
 define dso_local float @v8f32_fast(<8 x float> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v8f32_fast:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xvaddsp vs0, v2, v3
-; PWR9LE-NEXT:    xxswapd v2, vs0
-; PWR9LE-NEXT:    xvaddsp vs0, vs0, v2
-; PWR9LE-NEXT:    xxspltw vs1, vs0, 2
-; PWR9LE-NEXT:    xvaddsp vs0, vs0, vs1
-; PWR9LE-NEXT:    xxsldwi vs0, vs0, vs0, 3
-; PWR9LE-NEXT:    xscvspdpn f1, vs0
+; PWR9LE-NEXT:    xvaddsp vs0, v2, v3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V3(VSR35)
+; PWR9LE-NEXT:    xxswapd v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9LE-NEXT:    xvaddsp vs0, vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)V2(VSR34)
+; PWR9LE-NEXT:    xxspltw vs1, vs0, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)
+; PWR9LE-NEXT:    xvaddsp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs0, vs0, vs0, 3 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9LE-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v8f32_fast:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xvaddsp vs0, v2, v3
-; PWR9BE-NEXT:    xxswapd v2, vs0
-; PWR9BE-NEXT:    xvaddsp vs0, vs0, v2
-; PWR9BE-NEXT:    xxspltw vs1, vs0, 1
-; PWR9BE-NEXT:    xvaddsp vs0, vs0, vs1
-; PWR9BE-NEXT:    xscvspdpn f1, vs0
+; PWR9BE-NEXT:    xvaddsp vs0, v2, v3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V3(VSR35)
+; PWR9BE-NEXT:    xxswapd v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9BE-NEXT:    xvaddsp vs0, vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)V2(VSR34)
+; PWR9BE-NEXT:    xxspltw vs1, vs0, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)
+; PWR9BE-NEXT:    xvaddsp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR9BE-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v8f32_fast:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xvaddsp vs0, v2, v3
-; PWR10LE-NEXT:    xxswapd v2, vs0
-; PWR10LE-NEXT:    xvaddsp vs0, vs0, v2
-; PWR10LE-NEXT:    xxspltw vs1, vs0, 2
-; PWR10LE-NEXT:    xvaddsp vs0, vs0, vs1
-; PWR10LE-NEXT:    xxsldwi vs0, vs0, vs0, 3
-; PWR10LE-NEXT:    xscvspdpn f1, vs0
+; PWR10LE-NEXT:    xvaddsp vs0, v2, v3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V3(VSR35)
+; PWR10LE-NEXT:    xxswapd v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10LE-NEXT:    xvaddsp vs0, vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)V2(VSR34)
+; PWR10LE-NEXT:    xxspltw vs1, vs0, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)
+; PWR10LE-NEXT:    xvaddsp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs0, vs0, vs0, 3 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10LE-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v8f32_fast:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xvaddsp vs0, v2, v3
-; PWR10BE-NEXT:    xxswapd v2, vs0
-; PWR10BE-NEXT:    xvaddsp vs0, vs0, v2
-; PWR10BE-NEXT:    xxspltw vs1, vs0, 1
-; PWR10BE-NEXT:    xvaddsp vs0, vs0, vs1
-; PWR10BE-NEXT:    xscvspdpn f1, vs0
+; PWR10BE-NEXT:    xvaddsp vs0, v2, v3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V3(VSR35)
+; PWR10BE-NEXT:    xxswapd v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10BE-NEXT:    xvaddsp vs0, vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)V2(VSR34)
+; PWR10BE-NEXT:    xxspltw vs1, vs0, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)
+; PWR10BE-NEXT:    xvaddsp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR10BE-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call fast float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00, <8 x float> %a)
   ret float %0
 }
 
 define dso_local float @v16f32(<16 x float> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v16f32:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxsldwi vs0, v2, v2, 3
-; PWR9LE-NEXT:    xxswapd vs1, v2
-; PWR9LE-NEXT:    xscvspdpn f0, vs0
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xscvspdpn f1, v2
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v3, v3, 3
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v3
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v3, v3, 1
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xscvspdpn f1, v3
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v4, v4, 3
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v4
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v4, v4, 1
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xscvspdpn f1, v4
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v5, v5, 3
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v5
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v5, v5, 1
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xscvspdpn f1, v5
-; PWR9LE-NEXT:    xsaddsp f1, f0, f1
+; PWR9LE-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xscvspdpn f1, v2 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v3, v3, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v3, v3, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xscvspdpn f1, v3 # Vec Defs: F1(VSR1) Vec Uses: V3(VSR35)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v4, v4, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v4, v4, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xscvspdpn f1, v4 # Vec Defs: F1(VSR1) Vec Uses: V4(VSR36)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v5, v5, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v5, v5, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xscvspdpn f1, v5 # Vec Defs: F1(VSR1) Vec Uses: V5(VSR37)
+; PWR9LE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v16f32:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR9BE-NEXT:    xscvspdpn f0, v2
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v2
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xscvspdpn f1, v3
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v3, v3, 1
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v3, v3, 3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xscvspdpn f1, v4
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v4, v4, 1
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v4
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v4, v4, 3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xscvspdpn f1, v5
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v5, v5, 1
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v5
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v5, v5, 3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f1, f0, f1
+; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f0, v2 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xscvspdpn f1, v3 # Vec Defs: F1(VSR1) Vec Uses: V3(VSR35)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v3, v3, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v3, v3, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xscvspdpn f1, v4 # Vec Defs: F1(VSR1) Vec Uses: V4(VSR36)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v4, v4, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v4, v4, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xscvspdpn f1, v5 # Vec Defs: F1(VSR1) Vec Uses: V5(VSR37)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v5, v5, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v5, v5, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v16f32:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxsldwi vs0, v2, v2, 3
-; PWR10LE-NEXT:    xxswapd vs1, v2
-; PWR10LE-NEXT:    xscvspdpn f0, vs0
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xscvspdpn f1, v2
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v3, v3, 3
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v3
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v3, v3, 1
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xscvspdpn f1, v3
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v4, v4, 3
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v4
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v4, v4, 1
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xscvspdpn f1, v4
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v5, v5, 3
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v5
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v5, v5, 1
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xscvspdpn f1, v5
-; PWR10LE-NEXT:    xsaddsp f1, f0, f1
+; PWR10LE-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xscvspdpn f1, v2 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v3, v3, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v3, v3, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xscvspdpn f1, v3 # Vec Defs: F1(VSR1) Vec Uses: V3(VSR35)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v4, v4, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v4, v4, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xscvspdpn f1, v4 # Vec Defs: F1(VSR1) Vec Uses: V4(VSR36)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v5, v5, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v5, v5, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xscvspdpn f1, v5 # Vec Defs: F1(VSR1) Vec Uses: V5(VSR37)
+; PWR10LE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v16f32:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR10BE-NEXT:    xscvspdpn f0, v2
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v2
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xscvspdpn f1, v3
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v3, v3, 1
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v3, v3, 3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xscvspdpn f1, v4
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v4, v4, 1
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v4
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v4, v4, 3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xscvspdpn f1, v5
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v5, v5, 1
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v5
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v5, v5, 3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f1, f0, f1
+; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f0, v2 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xscvspdpn f1, v3 # Vec Defs: F1(VSR1) Vec Uses: V3(VSR35)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v3, v3, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v3, v3, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xscvspdpn f1, v4 # Vec Defs: F1(VSR1) Vec Uses: V4(VSR36)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v4, v4, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v4, v4, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xscvspdpn f1, v5 # Vec Defs: F1(VSR1) Vec Uses: V5(VSR37)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v5, v5, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v5, v5, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call float @llvm.vector.reduce.fadd.v16f32(float -0.000000e+00, <16 x float> %a)
   ret float %0
 }
 
 define dso_local float @v16f32_b(<16 x float> %a, float %b) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v16f32_b:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxsldwi vs0, v2, v2, 3
-; PWR9LE-NEXT:    xscvspdpn f0, vs0
-; PWR9LE-NEXT:    xsaddsp f0, f1, f0
-; PWR9LE-NEXT:    xxswapd vs1, v2
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xscvspdpn f1, v2
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v3, v3, 3
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v3
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v3, v3, 1
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xscvspdpn f1, v3
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v4, v4, 3
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v4
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v4, v4, 1
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xscvspdpn f1, v4
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v5, v5, 3
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v5
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xxsldwi vs1, v5, v5, 1
-; PWR9LE-NEXT:    xscvspdpn f1, vs1
-; PWR9LE-NEXT:    xsaddsp f0, f0, f1
-; PWR9LE-NEXT:    xscvspdpn f1, v5
-; PWR9LE-NEXT:    xsaddsp f1, f0, f1
+; PWR9LE-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PWR9LE-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR9LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xscvspdpn f1, v2 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v3, v3, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v3, v3, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xscvspdpn f1, v3 # Vec Defs: F1(VSR1) Vec Uses: V3(VSR35)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v4, v4, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v4, v4, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xscvspdpn f1, v4 # Vec Defs: F1(VSR1) Vec Uses: V4(VSR36)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v5, v5, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs1, v5, v5, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xscvspdpn f1, v5 # Vec Defs: F1(VSR1) Vec Uses: V5(VSR37)
+; PWR9LE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v16f32_b:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xscvspdpn f0, v2
-; PWR9BE-NEXT:    xsaddsp f0, f1, f0
-; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v2
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xscvspdpn f1, v3
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v3, v3, 1
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v3, v3, 3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xscvspdpn f1, v4
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v4, v4, 1
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v4
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v4, v4, 3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xscvspdpn f1, v5
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v5, v5, 1
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v5
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f0, f0, f1
-; PWR9BE-NEXT:    xxsldwi vs1, v5, v5, 3
-; PWR9BE-NEXT:    xscvspdpn f1, vs1
-; PWR9BE-NEXT:    xsaddsp f1, f0, f1
+; PWR9BE-NEXT:    xscvspdpn f0, v2 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PWR9BE-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v2, v2, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xscvspdpn f1, v3 # Vec Defs: F1(VSR1) Vec Uses: V3(VSR35)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v3, v3, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v3, v3, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xscvspdpn f1, v4 # Vec Defs: F1(VSR1) Vec Uses: V4(VSR36)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v4, v4, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v4, v4, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xscvspdpn f1, v5 # Vec Defs: F1(VSR1) Vec Uses: V5(VSR37)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v5, v5, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxsldwi vs1, v5, v5, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR9BE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v16f32_b:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxsldwi vs0, v2, v2, 3
-; PWR10LE-NEXT:    xscvspdpn f0, vs0
-; PWR10LE-NEXT:    xsaddsp f0, f1, f0
-; PWR10LE-NEXT:    xxswapd vs1, v2
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xscvspdpn f1, v2
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v3, v3, 3
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v3
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v3, v3, 1
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xscvspdpn f1, v3
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v4, v4, 3
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v4
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v4, v4, 1
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xscvspdpn f1, v4
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v5, v5, 3
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v5
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xxsldwi vs1, v5, v5, 1
-; PWR10LE-NEXT:    xscvspdpn f1, vs1
-; PWR10LE-NEXT:    xsaddsp f0, f0, f1
-; PWR10LE-NEXT:    xscvspdpn f1, v5
-; PWR10LE-NEXT:    xsaddsp f1, f0, f1
+; PWR10LE-NEXT:    xxsldwi vs0, v2, v2, 3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f0, vs0 # Vec Defs: F0(VSR0) Vec Uses: VSL0(VSR0)
+; PWR10LE-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR10LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xscvspdpn f1, v2 # Vec Defs: F1(VSR1) Vec Uses: V2(VSR34)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v3, v3, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v3, v3, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xscvspdpn f1, v3 # Vec Defs: F1(VSR1) Vec Uses: V3(VSR35)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v4, v4, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v4, v4, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xscvspdpn f1, v4 # Vec Defs: F1(VSR1) Vec Uses: V4(VSR36)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v5, v5, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs1, v5, v5, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10LE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10LE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xscvspdpn f1, v5 # Vec Defs: F1(VSR1) Vec Uses: V5(VSR37)
+; PWR10LE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v16f32_b:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xscvspdpn f0, v2
-; PWR10BE-NEXT:    xsaddsp f0, f1, f0
-; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 1
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v2
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xscvspdpn f1, v3
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v3, v3, 1
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v3, v3, 3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xscvspdpn f1, v4
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v4, v4, 1
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v4
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v4, v4, 3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xscvspdpn f1, v5
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v5, v5, 1
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v5
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f0, f0, f1
-; PWR10BE-NEXT:    xxsldwi vs1, v5, v5, 3
-; PWR10BE-NEXT:    xscvspdpn f1, vs1
-; PWR10BE-NEXT:    xsaddsp f1, f0, f1
+; PWR10BE-NEXT:    xscvspdpn f0, v2 # Vec Defs: F0(VSR0) Vec Uses: V2(VSR34)
+; PWR10BE-NEXT:    xsaddsp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v2, v2, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xscvspdpn f1, v3 # Vec Defs: F1(VSR1) Vec Uses: V3(VSR35)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v3, v3, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v3, v3, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xscvspdpn f1, v4 # Vec Defs: F1(VSR1) Vec Uses: V4(VSR36)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v4, v4, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v4, v4, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xscvspdpn f1, v5 # Vec Defs: F1(VSR1) Vec Uses: V5(VSR37)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v5, v5, 1 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxsldwi vs1, v5, v5, 3 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10BE-NEXT:    xscvspdpn f1, vs1 # Vec Defs: F1(VSR1) Vec Uses: VSL1(VSR1)
+; PWR10BE-NEXT:    xsaddsp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call float @llvm.vector.reduce.fadd.v16f32(float %b, <16 x float> %a)
   ret float %0
 }
 
 define dso_local float @v16f32_fast(<16 x float> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v16f32_fast:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xvaddsp vs0, v3, v5
-; PWR9LE-NEXT:    xvaddsp vs1, v2, v4
-; PWR9LE-NEXT:    xvaddsp vs0, vs1, vs0
-; PWR9LE-NEXT:    xxswapd v2, vs0
-; PWR9LE-NEXT:    xvaddsp vs0, vs0, v2
-; PWR9LE-NEXT:    xxspltw vs1, vs0, 2
-; PWR9LE-NEXT:    xvaddsp vs0, vs0, vs1
-; PWR9LE-NEXT:    xxsldwi vs0, vs0, vs0, 3
-; PWR9LE-NEXT:    xscvspdpn f1, vs0
+; PWR9LE-NEXT:    xvaddsp vs0, v3, v5 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V5(VSR37)
+; PWR9LE-NEXT:    xvaddsp vs1, v2, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V4(VSR36)
+; PWR9LE-NEXT:    xvaddsp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR9LE-NEXT:    xxswapd v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9LE-NEXT:    xvaddsp vs0, vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)V2(VSR34)
+; PWR9LE-NEXT:    xxspltw vs1, vs0, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)
+; PWR9LE-NEXT:    xvaddsp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR9LE-NEXT:    xxsldwi vs0, vs0, vs0, 3 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9LE-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v16f32_fast:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xvaddsp vs0, v3, v5
-; PWR9BE-NEXT:    xvaddsp vs1, v2, v4
-; PWR9BE-NEXT:    xvaddsp vs0, vs1, vs0
-; PWR9BE-NEXT:    xxswapd v2, vs0
-; PWR9BE-NEXT:    xvaddsp vs0, vs0, v2
-; PWR9BE-NEXT:    xxspltw vs1, vs0, 1
-; PWR9BE-NEXT:    xvaddsp vs0, vs0, vs1
-; PWR9BE-NEXT:    xscvspdpn f1, vs0
+; PWR9BE-NEXT:    xvaddsp vs0, v3, v5 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V5(VSR37)
+; PWR9BE-NEXT:    xvaddsp vs1, v2, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V4(VSR36)
+; PWR9BE-NEXT:    xvaddsp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR9BE-NEXT:    xxswapd v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9BE-NEXT:    xvaddsp vs0, vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)V2(VSR34)
+; PWR9BE-NEXT:    xxspltw vs1, vs0, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)
+; PWR9BE-NEXT:    xvaddsp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR9BE-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v16f32_fast:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xvaddsp vs0, v3, v5
-; PWR10LE-NEXT:    xvaddsp vs1, v2, v4
-; PWR10LE-NEXT:    xvaddsp vs0, vs1, vs0
-; PWR10LE-NEXT:    xxswapd v2, vs0
-; PWR10LE-NEXT:    xvaddsp vs0, vs0, v2
-; PWR10LE-NEXT:    xxspltw vs1, vs0, 2
-; PWR10LE-NEXT:    xvaddsp vs0, vs0, vs1
-; PWR10LE-NEXT:    xxsldwi vs0, vs0, vs0, 3
-; PWR10LE-NEXT:    xscvspdpn f1, vs0
+; PWR10LE-NEXT:    xvaddsp vs0, v3, v5 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V5(VSR37)
+; PWR10LE-NEXT:    xvaddsp vs1, v2, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V4(VSR36)
+; PWR10LE-NEXT:    xvaddsp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR10LE-NEXT:    xxswapd v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10LE-NEXT:    xvaddsp vs0, vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)V2(VSR34)
+; PWR10LE-NEXT:    xxspltw vs1, vs0, 2 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)
+; PWR10LE-NEXT:    xvaddsp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR10LE-NEXT:    xxsldwi vs0, vs0, vs0, 3 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10LE-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v16f32_fast:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xvaddsp vs0, v3, v5
-; PWR10BE-NEXT:    xvaddsp vs1, v2, v4
-; PWR10BE-NEXT:    xvaddsp vs0, vs1, vs0
-; PWR10BE-NEXT:    xxswapd v2, vs0
-; PWR10BE-NEXT:    xvaddsp vs0, vs0, v2
-; PWR10BE-NEXT:    xxspltw vs1, vs0, 1
-; PWR10BE-NEXT:    xvaddsp vs0, vs0, vs1
-; PWR10BE-NEXT:    xscvspdpn f1, vs0
+; PWR10BE-NEXT:    xvaddsp vs0, v3, v5 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V5(VSR37)
+; PWR10BE-NEXT:    xvaddsp vs1, v2, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V4(VSR36)
+; PWR10BE-NEXT:    xvaddsp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR10BE-NEXT:    xxswapd v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10BE-NEXT:    xvaddsp vs0, vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)V2(VSR34)
+; PWR10BE-NEXT:    xxspltw vs1, vs0, 1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)
+; PWR10BE-NEXT:    xvaddsp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR10BE-NEXT:    xscvspdpn f1, vs0 # Vec Defs: F1(VSR1) Vec Uses: VSL0(VSR0)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call fast float @llvm.vector.reduce.fadd.v16f32(float -0.000000e+00, <16 x float> %a)
   ret float %0
 }
 
 declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>) #0
 declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>) #0
 declare float @llvm.vector.reduce.fadd.v8f32(float, <8 x float>) #0
 declare float @llvm.vector.reduce.fadd.v16f32(float, <16 x float>) #0
 
 ;;
 ;; Vectors of f64
 ;;
 define dso_local double @v2f64(<2 x double> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v2f64:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxswapd vs0, v2
-; PWR9LE-NEXT:    xsadddp f1, f0, v2
+; PWR9LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xsadddp f1, f0, v2 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)VF2(VSR2)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v2f64:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xxswapd vs0, v2
-; PWR9BE-NEXT:    xsadddp f1, v2, f0
+; PWR9BE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xsadddp f1, v2, f0 # Vec Defs: F1(VSR1) Vec Uses: VF2(VSR2)F0(VSR0)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v2f64:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxswapd vs0, v2
-; PWR10LE-NEXT:    xsadddp f1, f0, v2
+; PWR10LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xsadddp f1, f0, v2 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)VF2(VSR2)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v2f64:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xxswapd vs0, v2
-; PWR10BE-NEXT:    xsadddp f1, v2, f0
+; PWR10BE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xsadddp f1, v2, f0 # Vec Defs: F1(VSR1) Vec Uses: VF2(VSR2)F0(VSR0)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> %a)
   ret double %0
 }
 
 define dso_local double @v2f64_b(<2 x double> %a, double %b) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v2f64_b:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxswapd vs0, v2
-; PWR9LE-NEXT:    xsadddp f0, f1, f0
-; PWR9LE-NEXT:    xsadddp f1, f0, v2
+; PWR9LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xsadddp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR9LE-NEXT:    xsadddp f1, f0, v2 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)VF2(VSR2)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v2f64_b:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xsadddp f0, f1, v2
-; PWR9BE-NEXT:    xxswapd vs1, v2
-; PWR9BE-NEXT:    xsadddp f1, f0, f1
+; PWR9BE-NEXT:    xsadddp f0, f1, v2 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v2f64_b:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxswapd vs0, v2
-; PWR10LE-NEXT:    xsadddp f0, f1, f0
-; PWR10LE-NEXT:    xsadddp f1, f0, v2
+; PWR10LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xsadddp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR10LE-NEXT:    xsadddp f1, f0, v2 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)VF2(VSR2)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v2f64_b:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xsadddp f0, f1, v2
-; PWR10BE-NEXT:    xxswapd vs1, v2
-; PWR10BE-NEXT:    xsadddp f1, f0, f1
+; PWR10BE-NEXT:    xsadddp f0, f1, v2 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call double @llvm.vector.reduce.fadd.v2f64(double %b, <2 x double> %a)
   ret double %0
 }
 
 define dso_local double @v2f64_fast(<2 x double> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v2f64_fast:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxswapd vs0, v2
-; PWR9LE-NEXT:    xvadddp vs0, v2, vs0
-; PWR9LE-NEXT:    xxswapd vs1, vs0
+; PWR9LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xvadddp vs0, v2, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)VSL0(VSR0)
+; PWR9LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; PWR9LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v2f64_fast:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xxswapd vs0, v2
-; PWR9BE-NEXT:    xvadddp vs1, v2, vs0
+; PWR9BE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xvadddp vs1, v2, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)VSL0(VSR0)
 ; PWR9BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v2f64_fast:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxswapd vs0, v2
-; PWR10LE-NEXT:    xvadddp vs0, v2, vs0
-; PWR10LE-NEXT:    xxswapd vs1, vs0
+; PWR10LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xvadddp vs0, v2, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)VSL0(VSR0)
+; PWR10LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; PWR10LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v2f64_fast:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xxswapd vs0, v2
-; PWR10BE-NEXT:    xvadddp vs1, v2, vs0
+; PWR10BE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xvadddp vs1, v2, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)VSL0(VSR0)
 ; PWR10BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call fast double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> %a)
   ret double %0
 }
 
 define dso_local double @v4f64(<4 x double> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v4f64:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxswapd vs0, v2
-; PWR9LE-NEXT:    xxswapd vs1, v3
-; PWR9LE-NEXT:    xsadddp f0, f0, v2
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xsadddp f1, f0, v3
+; PWR9LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xsadddp f0, f0, v2 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF2(VSR2)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xsadddp f1, f0, v3 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)VF3(VSR3)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v4f64:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xxswapd vs0, v2
-; PWR9BE-NEXT:    xxswapd vs1, v3
-; PWR9BE-NEXT:    xsadddp f0, v2, f0
-; PWR9BE-NEXT:    xsadddp f0, f0, v3
-; PWR9BE-NEXT:    xsadddp f1, f0, f1
+; PWR9BE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xsadddp f0, v2, f0 # Vec Defs: F0(VSR0) Vec Uses: VF2(VSR2)F0(VSR0)
+; PWR9BE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR9BE-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v4f64:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxswapd vs0, v2
-; PWR10LE-NEXT:    xxswapd vs1, v3
-; PWR10LE-NEXT:    xsadddp f0, f0, v2
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xsadddp f1, f0, v3
+; PWR10LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xsadddp f0, f0, v2 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF2(VSR2)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xsadddp f1, f0, v3 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)VF3(VSR3)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v4f64:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xxswapd vs0, v2
-; PWR10BE-NEXT:    xxswapd vs1, v3
-; PWR10BE-NEXT:    xsadddp f0, v2, f0
-; PWR10BE-NEXT:    xsadddp f0, f0, v3
-; PWR10BE-NEXT:    xsadddp f1, f0, f1
+; PWR10BE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xsadddp f0, v2, f0 # Vec Defs: F0(VSR0) Vec Uses: VF2(VSR2)F0(VSR0)
+; PWR10BE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR10BE-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call double @llvm.vector.reduce.fadd.v4f64(double -0.000000e+00, <4 x double> %a)
   ret double %0
 }
 
 define dso_local double @v4f64_b(<4 x double> %a, double %b) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v4f64_b:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxswapd vs0, v2
-; PWR9LE-NEXT:    xsadddp f0, f1, f0
-; PWR9LE-NEXT:    xxswapd vs1, v3
-; PWR9LE-NEXT:    xsadddp f0, f0, v2
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xsadddp f1, f0, v3
+; PWR9LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xsadddp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR9LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xsadddp f0, f0, v2 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF2(VSR2)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xsadddp f1, f0, v3 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)VF3(VSR3)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v4f64_b:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xsadddp f0, f1, v2
-; PWR9BE-NEXT:    xxswapd vs1, v2
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v3
-; PWR9BE-NEXT:    xsadddp f0, f0, v3
-; PWR9BE-NEXT:    xsadddp f1, f0, f1
+; PWR9BE-NEXT:    xsadddp f0, f1, v2 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR9BE-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v4f64_b:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxswapd vs0, v2
-; PWR10LE-NEXT:    xsadddp f0, f1, f0
-; PWR10LE-NEXT:    xxswapd vs1, v3
-; PWR10LE-NEXT:    xsadddp f0, f0, v2
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xsadddp f1, f0, v3
+; PWR10LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xsadddp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR10LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xsadddp f0, f0, v2 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF2(VSR2)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xsadddp f1, f0, v3 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)VF3(VSR3)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v4f64_b:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xsadddp f0, f1, v2
-; PWR10BE-NEXT:    xxswapd vs1, v2
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v3
-; PWR10BE-NEXT:    xsadddp f0, f0, v3
-; PWR10BE-NEXT:    xsadddp f1, f0, f1
+; PWR10BE-NEXT:    xsadddp f0, f1, v2 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR10BE-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call double @llvm.vector.reduce.fadd.v4f64(double %b, <4 x double> %a)
   ret double %0
 }
 
 define dso_local double @v4f64_fast(<4 x double> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v4f64_fast:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xvadddp vs0, v2, v3
-; PWR9LE-NEXT:    xxswapd vs1, vs0
-; PWR9LE-NEXT:    xvadddp vs0, vs0, vs1
-; PWR9LE-NEXT:    xxswapd vs1, vs0
+; PWR9LE-NEXT:    xvadddp vs0, v2, v3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V3(VSR35)
+; PWR9LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9LE-NEXT:    xvadddp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; PWR9LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v4f64_fast:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xvadddp vs0, v2, v3
-; PWR9BE-NEXT:    xxswapd vs1, vs0
-; PWR9BE-NEXT:    xvadddp vs1, vs0, vs1
+; PWR9BE-NEXT:    xvadddp vs0, v2, v3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V3(VSR35)
+; PWR9BE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9BE-NEXT:    xvadddp vs1, vs0, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL1(VSR1)
 ; PWR9BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v4f64_fast:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xvadddp vs0, v2, v3
-; PWR10LE-NEXT:    xxswapd vs1, vs0
-; PWR10LE-NEXT:    xvadddp vs0, vs0, vs1
-; PWR10LE-NEXT:    xxswapd vs1, vs0
+; PWR10LE-NEXT:    xvadddp vs0, v2, v3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V3(VSR35)
+; PWR10LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10LE-NEXT:    xvadddp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; PWR10LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v4f64_fast:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xvadddp vs0, v2, v3
-; PWR10BE-NEXT:    xxswapd vs1, vs0
-; PWR10BE-NEXT:    xvadddp vs1, vs0, vs1
+; PWR10BE-NEXT:    xvadddp vs0, v2, v3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V3(VSR35)
+; PWR10BE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10BE-NEXT:    xvadddp vs1, vs0, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL1(VSR1)
 ; PWR10BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call fast double @llvm.vector.reduce.fadd.v4f64(double -0.000000e+00, <4 x double> %a)
   ret double %0
 }
 
 define dso_local double @v8f64(<8 x double> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v8f64:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxswapd vs0, v2
-; PWR9LE-NEXT:    xxswapd vs1, v3
-; PWR9LE-NEXT:    xsadddp f0, f0, v2
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v4
-; PWR9LE-NEXT:    xsadddp f0, f0, v3
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v5
-; PWR9LE-NEXT:    xsadddp f0, f0, v4
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xsadddp f1, f0, v5
+; PWR9LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xsadddp f0, f0, v2 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF2(VSR2)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9LE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9LE-NEXT:    xsadddp f0, f0, v4 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF4(VSR4)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xsadddp f1, f0, v5 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)VF5(VSR5)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v8f64:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xxswapd vs0, v2
-; PWR9BE-NEXT:    xxswapd vs1, v3
-; PWR9BE-NEXT:    xsadddp f0, v2, f0
-; PWR9BE-NEXT:    xsadddp f0, f0, v3
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v4
-; PWR9BE-NEXT:    xsadddp f0, f0, v4
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v5
-; PWR9BE-NEXT:    xsadddp f0, f0, v5
-; PWR9BE-NEXT:    xsadddp f1, f0, f1
+; PWR9BE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xsadddp f0, v2, f0 # Vec Defs: F0(VSR0) Vec Uses: VF2(VSR2)F0(VSR0)
+; PWR9BE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9BE-NEXT:    xsadddp f0, f0, v4 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF4(VSR4)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9BE-NEXT:    xsadddp f0, f0, v5 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF5(VSR5)
+; PWR9BE-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v8f64:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxswapd vs0, v2
-; PWR10LE-NEXT:    xxswapd vs1, v3
-; PWR10LE-NEXT:    xsadddp f0, f0, v2
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v4
-; PWR10LE-NEXT:    xsadddp f0, f0, v3
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v5
-; PWR10LE-NEXT:    xsadddp f0, f0, v4
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xsadddp f1, f0, v5
+; PWR10LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xsadddp f0, f0, v2 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF2(VSR2)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10LE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10LE-NEXT:    xsadddp f0, f0, v4 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF4(VSR4)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xsadddp f1, f0, v5 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)VF5(VSR5)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v8f64:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xxswapd vs0, v2
-; PWR10BE-NEXT:    xxswapd vs1, v3
-; PWR10BE-NEXT:    xsadddp f0, v2, f0
-; PWR10BE-NEXT:    xsadddp f0, f0, v3
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v4
-; PWR10BE-NEXT:    xsadddp f0, f0, v4
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v5
-; PWR10BE-NEXT:    xsadddp f0, f0, v5
-; PWR10BE-NEXT:    xsadddp f1, f0, f1
+; PWR10BE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xsadddp f0, v2, f0 # Vec Defs: F0(VSR0) Vec Uses: VF2(VSR2)F0(VSR0)
+; PWR10BE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10BE-NEXT:    xsadddp f0, f0, v4 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF4(VSR4)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10BE-NEXT:    xsadddp f0, f0, v5 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF5(VSR5)
+; PWR10BE-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call double @llvm.vector.reduce.fadd.v8f64(double -0.000000e+00, <8 x double> %a)
   ret double %0
 }
 
 define dso_local double @v8f64_b(<8 x double> %a, double %b) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v8f64_b:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxswapd vs0, v2
-; PWR9LE-NEXT:    xsadddp f0, f1, f0
-; PWR9LE-NEXT:    xxswapd vs1, v3
-; PWR9LE-NEXT:    xsadddp f0, f0, v2
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v4
-; PWR9LE-NEXT:    xsadddp f0, f0, v3
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v5
-; PWR9LE-NEXT:    xsadddp f0, f0, v4
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xsadddp f1, f0, v5
+; PWR9LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xsadddp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR9LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xsadddp f0, f0, v2 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF2(VSR2)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9LE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9LE-NEXT:    xsadddp f0, f0, v4 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF4(VSR4)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xsadddp f1, f0, v5 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)VF5(VSR5)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v8f64_b:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xsadddp f0, f1, v2
-; PWR9BE-NEXT:    xxswapd vs1, v2
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v3
-; PWR9BE-NEXT:    xsadddp f0, f0, v3
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v4
-; PWR9BE-NEXT:    xsadddp f0, f0, v4
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v5
-; PWR9BE-NEXT:    xsadddp f0, f0, v5
-; PWR9BE-NEXT:    xsadddp f1, f0, f1
+; PWR9BE-NEXT:    xsadddp f0, f1, v2 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9BE-NEXT:    xsadddp f0, f0, v4 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF4(VSR4)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9BE-NEXT:    xsadddp f0, f0, v5 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF5(VSR5)
+; PWR9BE-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v8f64_b:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxswapd vs0, v2
-; PWR10LE-NEXT:    xsadddp f0, f1, f0
-; PWR10LE-NEXT:    xxswapd vs1, v3
-; PWR10LE-NEXT:    xsadddp f0, f0, v2
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v4
-; PWR10LE-NEXT:    xsadddp f0, f0, v3
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v5
-; PWR10LE-NEXT:    xsadddp f0, f0, v4
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xsadddp f1, f0, v5
+; PWR10LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xsadddp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR10LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xsadddp f0, f0, v2 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF2(VSR2)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10LE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10LE-NEXT:    xsadddp f0, f0, v4 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF4(VSR4)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xsadddp f1, f0, v5 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)VF5(VSR5)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v8f64_b:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xsadddp f0, f1, v2
-; PWR10BE-NEXT:    xxswapd vs1, v2
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v3
-; PWR10BE-NEXT:    xsadddp f0, f0, v3
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v4
-; PWR10BE-NEXT:    xsadddp f0, f0, v4
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v5
-; PWR10BE-NEXT:    xsadddp f0, f0, v5
-; PWR10BE-NEXT:    xsadddp f1, f0, f1
+; PWR10BE-NEXT:    xsadddp f0, f1, v2 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10BE-NEXT:    xsadddp f0, f0, v4 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF4(VSR4)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10BE-NEXT:    xsadddp f0, f0, v5 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF5(VSR5)
+; PWR10BE-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call double @llvm.vector.reduce.fadd.v8f64(double %b, <8 x double> %a)
   ret double %0
 }
 
 define dso_local double @v8f64_fast(<8 x double> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v8f64_fast:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xvadddp vs0, v3, v5
-; PWR9LE-NEXT:    xvadddp vs1, v2, v4
-; PWR9LE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR9LE-NEXT:    xxswapd vs1, vs0
-; PWR9LE-NEXT:    xvadddp vs0, vs0, vs1
-; PWR9LE-NEXT:    xxswapd vs1, vs0
+; PWR9LE-NEXT:    xvadddp vs0, v3, v5 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V5(VSR37)
+; PWR9LE-NEXT:    xvadddp vs1, v2, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V4(VSR36)
+; PWR9LE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR9LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9LE-NEXT:    xvadddp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; PWR9LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v8f64_fast:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xvadddp vs0, v3, v5
-; PWR9BE-NEXT:    xvadddp vs1, v2, v4
-; PWR9BE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR9BE-NEXT:    xxswapd vs1, vs0
-; PWR9BE-NEXT:    xvadddp vs1, vs0, vs1
+; PWR9BE-NEXT:    xvadddp vs0, v3, v5 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V5(VSR37)
+; PWR9BE-NEXT:    xvadddp vs1, v2, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V4(VSR36)
+; PWR9BE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR9BE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9BE-NEXT:    xvadddp vs1, vs0, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL1(VSR1)
 ; PWR9BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v8f64_fast:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xvadddp vs0, v3, v5
-; PWR10LE-NEXT:    xvadddp vs1, v2, v4
-; PWR10LE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR10LE-NEXT:    xxswapd vs1, vs0
-; PWR10LE-NEXT:    xvadddp vs0, vs0, vs1
-; PWR10LE-NEXT:    xxswapd vs1, vs0
+; PWR10LE-NEXT:    xvadddp vs0, v3, v5 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V5(VSR37)
+; PWR10LE-NEXT:    xvadddp vs1, v2, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V4(VSR36)
+; PWR10LE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR10LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10LE-NEXT:    xvadddp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; PWR10LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v8f64_fast:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xvadddp vs0, v3, v5
-; PWR10BE-NEXT:    xvadddp vs1, v2, v4
-; PWR10BE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR10BE-NEXT:    xxswapd vs1, vs0
-; PWR10BE-NEXT:    xvadddp vs1, vs0, vs1
+; PWR10BE-NEXT:    xvadddp vs0, v3, v5 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V5(VSR37)
+; PWR10BE-NEXT:    xvadddp vs1, v2, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V4(VSR36)
+; PWR10BE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR10BE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10BE-NEXT:    xvadddp vs1, vs0, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL1(VSR1)
 ; PWR10BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call fast double @llvm.vector.reduce.fadd.v8f64(double -0.000000e+00, <8 x double> %a)
   ret double %0
 }
 
 define dso_local double @v16f64(<16 x double> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v16f64:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxswapd vs0, v2
-; PWR9LE-NEXT:    xxswapd vs1, v3
-; PWR9LE-NEXT:    xsadddp f0, f0, v2
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v4
-; PWR9LE-NEXT:    xsadddp f0, f0, v3
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v5
-; PWR9LE-NEXT:    xsadddp f0, f0, v4
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v6
-; PWR9LE-NEXT:    xsadddp f0, f0, v5
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v7
-; PWR9LE-NEXT:    xsadddp f0, f0, v6
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v8
-; PWR9LE-NEXT:    xsadddp f0, f0, v7
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v9
-; PWR9LE-NEXT:    xsadddp f0, f0, v8
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xsadddp f1, f0, v9
+; PWR9LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xsadddp f0, f0, v2 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF2(VSR2)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9LE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9LE-NEXT:    xsadddp f0, f0, v4 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF4(VSR4)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v6 # Vec Defs: VSL1(VSR1) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR9LE-NEXT:    xsadddp f0, f0, v5 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF5(VSR5)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v7 # Vec Defs: VSL1(VSR1) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR9LE-NEXT:    xsadddp f0, f0, v6 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF6(VSR6)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v8 # Vec Defs: VSL1(VSR1) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR9LE-NEXT:    xsadddp f0, f0, v7 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF7(VSR7)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v9 # Vec Defs: VSL1(VSR1) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR9LE-NEXT:    xsadddp f0, f0, v8 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF8(VSR8)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xsadddp f1, f0, v9 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)VF9(VSR9)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v16f64:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xxswapd vs0, v2
-; PWR9BE-NEXT:    xxswapd vs1, v3
-; PWR9BE-NEXT:    xsadddp f0, v2, f0
-; PWR9BE-NEXT:    xsadddp f0, f0, v3
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v4
-; PWR9BE-NEXT:    xsadddp f0, f0, v4
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v5
-; PWR9BE-NEXT:    xsadddp f0, f0, v5
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v6
-; PWR9BE-NEXT:    xsadddp f0, f0, v6
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v7
-; PWR9BE-NEXT:    xsadddp f0, f0, v7
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v8
-; PWR9BE-NEXT:    xsadddp f0, f0, v8
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v9
-; PWR9BE-NEXT:    xsadddp f0, f0, v9
-; PWR9BE-NEXT:    xsadddp f1, f0, f1
+; PWR9BE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xsadddp f0, v2, f0 # Vec Defs: F0(VSR0) Vec Uses: VF2(VSR2)F0(VSR0)
+; PWR9BE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9BE-NEXT:    xsadddp f0, f0, v4 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF4(VSR4)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9BE-NEXT:    xsadddp f0, f0, v5 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF5(VSR5)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v6 # Vec Defs: VSL1(VSR1) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR9BE-NEXT:    xsadddp f0, f0, v6 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF6(VSR6)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v7 # Vec Defs: VSL1(VSR1) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR9BE-NEXT:    xsadddp f0, f0, v7 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF7(VSR7)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v8 # Vec Defs: VSL1(VSR1) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR9BE-NEXT:    xsadddp f0, f0, v8 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF8(VSR8)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v9 # Vec Defs: VSL1(VSR1) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR9BE-NEXT:    xsadddp f0, f0, v9 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF9(VSR9)
+; PWR9BE-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v16f64:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxswapd vs0, v2
-; PWR10LE-NEXT:    xxswapd vs1, v3
-; PWR10LE-NEXT:    xsadddp f0, f0, v2
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v4
-; PWR10LE-NEXT:    xsadddp f0, f0, v3
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v5
-; PWR10LE-NEXT:    xsadddp f0, f0, v4
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v6
-; PWR10LE-NEXT:    xsadddp f0, f0, v5
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v7
-; PWR10LE-NEXT:    xsadddp f0, f0, v6
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v8
-; PWR10LE-NEXT:    xsadddp f0, f0, v7
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v9
-; PWR10LE-NEXT:    xsadddp f0, f0, v8
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xsadddp f1, f0, v9
+; PWR10LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xsadddp f0, f0, v2 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF2(VSR2)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10LE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10LE-NEXT:    xsadddp f0, f0, v4 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF4(VSR4)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v6 # Vec Defs: VSL1(VSR1) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR10LE-NEXT:    xsadddp f0, f0, v5 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF5(VSR5)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v7 # Vec Defs: VSL1(VSR1) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR10LE-NEXT:    xsadddp f0, f0, v6 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF6(VSR6)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v8 # Vec Defs: VSL1(VSR1) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR10LE-NEXT:    xsadddp f0, f0, v7 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF7(VSR7)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v9 # Vec Defs: VSL1(VSR1) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR10LE-NEXT:    xsadddp f0, f0, v8 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF8(VSR8)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xsadddp f1, f0, v9 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)VF9(VSR9)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v16f64:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xxswapd vs0, v2
-; PWR10BE-NEXT:    xxswapd vs1, v3
-; PWR10BE-NEXT:    xsadddp f0, v2, f0
-; PWR10BE-NEXT:    xsadddp f0, f0, v3
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v4
-; PWR10BE-NEXT:    xsadddp f0, f0, v4
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v5
-; PWR10BE-NEXT:    xsadddp f0, f0, v5
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v6
-; PWR10BE-NEXT:    xsadddp f0, f0, v6
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v7
-; PWR10BE-NEXT:    xsadddp f0, f0, v7
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v8
-; PWR10BE-NEXT:    xsadddp f0, f0, v8
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v9
-; PWR10BE-NEXT:    xsadddp f0, f0, v9
-; PWR10BE-NEXT:    xsadddp f1, f0, f1
+; PWR10BE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xsadddp f0, v2, f0 # Vec Defs: F0(VSR0) Vec Uses: VF2(VSR2)F0(VSR0)
+; PWR10BE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10BE-NEXT:    xsadddp f0, f0, v4 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF4(VSR4)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10BE-NEXT:    xsadddp f0, f0, v5 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF5(VSR5)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v6 # Vec Defs: VSL1(VSR1) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR10BE-NEXT:    xsadddp f0, f0, v6 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF6(VSR6)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v7 # Vec Defs: VSL1(VSR1) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR10BE-NEXT:    xsadddp f0, f0, v7 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF7(VSR7)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v8 # Vec Defs: VSL1(VSR1) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR10BE-NEXT:    xsadddp f0, f0, v8 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF8(VSR8)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v9 # Vec Defs: VSL1(VSR1) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR10BE-NEXT:    xsadddp f0, f0, v9 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF9(VSR9)
+; PWR10BE-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call double @llvm.vector.reduce.fadd.v16f64(double -0.000000e+00, <16 x double> %a)
   ret double %0
 }
 
 define dso_local double @v16f64_b(<16 x double> %a, double %b) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v16f64_b:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxswapd vs0, v2
-; PWR9LE-NEXT:    xsadddp f0, f1, f0
-; PWR9LE-NEXT:    xxswapd vs1, v3
-; PWR9LE-NEXT:    xsadddp f0, f0, v2
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v4
-; PWR9LE-NEXT:    xsadddp f0, f0, v3
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v5
-; PWR9LE-NEXT:    xsadddp f0, f0, v4
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v6
-; PWR9LE-NEXT:    xsadddp f0, f0, v5
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v7
-; PWR9LE-NEXT:    xsadddp f0, f0, v6
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v8
-; PWR9LE-NEXT:    xsadddp f0, f0, v7
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xxswapd vs1, v9
-; PWR9LE-NEXT:    xsadddp f0, f0, v8
-; PWR9LE-NEXT:    xsadddp f0, f0, f1
-; PWR9LE-NEXT:    xsadddp f1, f0, v9
+; PWR9LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xsadddp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR9LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xsadddp f0, f0, v2 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF2(VSR2)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9LE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9LE-NEXT:    xsadddp f0, f0, v4 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF4(VSR4)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v6 # Vec Defs: VSL1(VSR1) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR9LE-NEXT:    xsadddp f0, f0, v5 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF5(VSR5)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v7 # Vec Defs: VSL1(VSR1) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR9LE-NEXT:    xsadddp f0, f0, v6 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF6(VSR6)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v8 # Vec Defs: VSL1(VSR1) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR9LE-NEXT:    xsadddp f0, f0, v7 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF7(VSR7)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, v9 # Vec Defs: VSL1(VSR1) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR9LE-NEXT:    xsadddp f0, f0, v8 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF8(VSR8)
+; PWR9LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9LE-NEXT:    xsadddp f1, f0, v9 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)VF9(VSR9)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v16f64_b:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xsadddp f0, f1, v2
-; PWR9BE-NEXT:    xxswapd vs1, v2
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v3
-; PWR9BE-NEXT:    xsadddp f0, f0, v3
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v4
-; PWR9BE-NEXT:    xsadddp f0, f0, v4
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v5
-; PWR9BE-NEXT:    xsadddp f0, f0, v5
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v6
-; PWR9BE-NEXT:    xsadddp f0, f0, v6
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v7
-; PWR9BE-NEXT:    xsadddp f0, f0, v7
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v8
-; PWR9BE-NEXT:    xsadddp f0, f0, v8
-; PWR9BE-NEXT:    xsadddp f0, f0, f1
-; PWR9BE-NEXT:    xxswapd vs1, v9
-; PWR9BE-NEXT:    xsadddp f0, f0, v9
-; PWR9BE-NEXT:    xsadddp f1, f0, f1
+; PWR9BE-NEXT:    xsadddp f0, f1, v2 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9BE-NEXT:    xsadddp f0, f0, v4 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF4(VSR4)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9BE-NEXT:    xsadddp f0, f0, v5 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF5(VSR5)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v6 # Vec Defs: VSL1(VSR1) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR9BE-NEXT:    xsadddp f0, f0, v6 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF6(VSR6)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v7 # Vec Defs: VSL1(VSR1) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR9BE-NEXT:    xsadddp f0, f0, v7 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF7(VSR7)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v8 # Vec Defs: VSL1(VSR1) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR9BE-NEXT:    xsadddp f0, f0, v8 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF8(VSR8)
+; PWR9BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, v9 # Vec Defs: VSL1(VSR1) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR9BE-NEXT:    xsadddp f0, f0, v9 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF9(VSR9)
+; PWR9BE-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v16f64_b:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxswapd vs0, v2
-; PWR10LE-NEXT:    xsadddp f0, f1, f0
-; PWR10LE-NEXT:    xxswapd vs1, v3
-; PWR10LE-NEXT:    xsadddp f0, f0, v2
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v4
-; PWR10LE-NEXT:    xsadddp f0, f0, v3
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v5
-; PWR10LE-NEXT:    xsadddp f0, f0, v4
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v6
-; PWR10LE-NEXT:    xsadddp f0, f0, v5
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v7
-; PWR10LE-NEXT:    xsadddp f0, f0, v6
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v8
-; PWR10LE-NEXT:    xsadddp f0, f0, v7
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xxswapd vs1, v9
-; PWR10LE-NEXT:    xsadddp f0, f0, v8
-; PWR10LE-NEXT:    xsadddp f0, f0, f1
-; PWR10LE-NEXT:    xsadddp f1, f0, v9
+; PWR10LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xsadddp f0, f1, f0 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR10LE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    xsadddp f0, f0, v2 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF2(VSR2)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10LE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10LE-NEXT:    xsadddp f0, f0, v4 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF4(VSR4)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v6 # Vec Defs: VSL1(VSR1) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR10LE-NEXT:    xsadddp f0, f0, v5 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF5(VSR5)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v7 # Vec Defs: VSL1(VSR1) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR10LE-NEXT:    xsadddp f0, f0, v6 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF6(VSR6)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v8 # Vec Defs: VSL1(VSR1) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR10LE-NEXT:    xsadddp f0, f0, v7 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF7(VSR7)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, v9 # Vec Defs: VSL1(VSR1) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR10LE-NEXT:    xsadddp f0, f0, v8 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF8(VSR8)
+; PWR10LE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10LE-NEXT:    xsadddp f1, f0, v9 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)VF9(VSR9)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v16f64_b:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xsadddp f0, f1, v2
-; PWR10BE-NEXT:    xxswapd vs1, v2
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v3
-; PWR10BE-NEXT:    xsadddp f0, f0, v3
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v4
-; PWR10BE-NEXT:    xsadddp f0, f0, v4
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v5
-; PWR10BE-NEXT:    xsadddp f0, f0, v5
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v6
-; PWR10BE-NEXT:    xsadddp f0, f0, v6
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v7
-; PWR10BE-NEXT:    xsadddp f0, f0, v7
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v8
-; PWR10BE-NEXT:    xsadddp f0, f0, v8
-; PWR10BE-NEXT:    xsadddp f0, f0, f1
-; PWR10BE-NEXT:    xxswapd vs1, v9
-; PWR10BE-NEXT:    xsadddp f0, f0, v9
-; PWR10BE-NEXT:    xsadddp f1, f0, f1
+; PWR10BE-NEXT:    xsadddp f0, f1, v2 # Vec Defs: F0(VSR0) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v3 # Vec Defs: VSL1(VSR1) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    xsadddp f0, f0, v3 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF3(VSR3)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10BE-NEXT:    xsadddp f0, f0, v4 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF4(VSR4)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10BE-NEXT:    xsadddp f0, f0, v5 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF5(VSR5)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v6 # Vec Defs: VSL1(VSR1) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR10BE-NEXT:    xsadddp f0, f0, v6 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF6(VSR6)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v7 # Vec Defs: VSL1(VSR1) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR10BE-NEXT:    xsadddp f0, f0, v7 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF7(VSR7)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v8 # Vec Defs: VSL1(VSR1) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR10BE-NEXT:    xsadddp f0, f0, v8 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF8(VSR8)
+; PWR10BE-NEXT:    xsadddp f0, f0, f1 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, v9 # Vec Defs: VSL1(VSR1) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR10BE-NEXT:    xsadddp f0, f0, v9 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)VF9(VSR9)
+; PWR10BE-NEXT:    xsadddp f1, f0, f1 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)F1(VSR1)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call double @llvm.vector.reduce.fadd.v16f64(double %b, <16 x double> %a)
   ret double %0
 }
 
 define dso_local double @v16f64_fast(<16 x double> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v16f64_fast:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xvadddp vs0, v4, v8
-; PWR9LE-NEXT:    xvadddp vs1, v2, v6
-; PWR9LE-NEXT:    xvadddp vs2, v5, v9
-; PWR9LE-NEXT:    xvadddp vs3, v3, v7
-; PWR9LE-NEXT:    xvadddp vs2, vs3, vs2
-; PWR9LE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR9LE-NEXT:    xvadddp vs0, vs0, vs2
-; PWR9LE-NEXT:    xxswapd vs1, vs0
-; PWR9LE-NEXT:    xvadddp vs0, vs0, vs1
-; PWR9LE-NEXT:    xxswapd vs1, vs0
+; PWR9LE-NEXT:    xvadddp vs0, v4, v8 # Vec Defs: VSL0(VSR0) Vec Uses: V4(VSR36)V8(VSR40)
+; PWR9LE-NEXT:    xvadddp vs1, v2, v6 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V6(VSR38)
+; PWR9LE-NEXT:    xvadddp vs2, v5, v9 # Vec Defs: VSL2(VSR2) Vec Uses: V5(VSR37)V9(VSR41)
+; PWR9LE-NEXT:    xvadddp vs3, v3, v7 # Vec Defs: VSL3(VSR3) Vec Uses: V3(VSR35)V7(VSR39)
+; PWR9LE-NEXT:    xvadddp vs2, vs3, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL3(VSR3)VSL2(VSR2)
+; PWR9LE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR9LE-NEXT:    xvadddp vs0, vs0, vs2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL2(VSR2)
+; PWR9LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9LE-NEXT:    xvadddp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; PWR9LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v16f64_fast:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xvadddp vs0, v4, v8
-; PWR9BE-NEXT:    xvadddp vs1, v2, v6
-; PWR9BE-NEXT:    xvadddp vs2, v5, v9
-; PWR9BE-NEXT:    xvadddp vs3, v3, v7
-; PWR9BE-NEXT:    xvadddp vs2, vs3, vs2
-; PWR9BE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR9BE-NEXT:    xvadddp vs0, vs0, vs2
-; PWR9BE-NEXT:    xxswapd vs1, vs0
-; PWR9BE-NEXT:    xvadddp vs1, vs0, vs1
+; PWR9BE-NEXT:    xvadddp vs0, v4, v8 # Vec Defs: VSL0(VSR0) Vec Uses: V4(VSR36)V8(VSR40)
+; PWR9BE-NEXT:    xvadddp vs1, v2, v6 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V6(VSR38)
+; PWR9BE-NEXT:    xvadddp vs2, v5, v9 # Vec Defs: VSL2(VSR2) Vec Uses: V5(VSR37)V9(VSR41)
+; PWR9BE-NEXT:    xvadddp vs3, v3, v7 # Vec Defs: VSL3(VSR3) Vec Uses: V3(VSR35)V7(VSR39)
+; PWR9BE-NEXT:    xvadddp vs2, vs3, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL3(VSR3)VSL2(VSR2)
+; PWR9BE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR9BE-NEXT:    xvadddp vs0, vs0, vs2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL2(VSR2)
+; PWR9BE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9BE-NEXT:    xvadddp vs1, vs0, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL1(VSR1)
 ; PWR9BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v16f64_fast:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xvadddp vs0, v4, v8
-; PWR10LE-NEXT:    xvadddp vs1, v2, v6
-; PWR10LE-NEXT:    xvadddp vs2, v5, v9
-; PWR10LE-NEXT:    xvadddp vs3, v3, v7
-; PWR10LE-NEXT:    xvadddp vs2, vs3, vs2
-; PWR10LE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR10LE-NEXT:    xvadddp vs0, vs0, vs2
-; PWR10LE-NEXT:    xxswapd vs1, vs0
-; PWR10LE-NEXT:    xvadddp vs0, vs0, vs1
-; PWR10LE-NEXT:    xxswapd vs1, vs0
+; PWR10LE-NEXT:    xvadddp vs0, v4, v8 # Vec Defs: VSL0(VSR0) Vec Uses: V4(VSR36)V8(VSR40)
+; PWR10LE-NEXT:    xvadddp vs1, v2, v6 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V6(VSR38)
+; PWR10LE-NEXT:    xvadddp vs2, v5, v9 # Vec Defs: VSL2(VSR2) Vec Uses: V5(VSR37)V9(VSR41)
+; PWR10LE-NEXT:    xvadddp vs3, v3, v7 # Vec Defs: VSL3(VSR3) Vec Uses: V3(VSR35)V7(VSR39)
+; PWR10LE-NEXT:    xvadddp vs2, vs3, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL3(VSR3)VSL2(VSR2)
+; PWR10LE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR10LE-NEXT:    xvadddp vs0, vs0, vs2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL2(VSR2)
+; PWR10LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10LE-NEXT:    xvadddp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; PWR10LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v16f64_fast:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xvadddp vs0, v4, v8
-; PWR10BE-NEXT:    xvadddp vs1, v2, v6
-; PWR10BE-NEXT:    xvadddp vs2, v5, v9
-; PWR10BE-NEXT:    xvadddp vs3, v3, v7
-; PWR10BE-NEXT:    xvadddp vs2, vs3, vs2
-; PWR10BE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR10BE-NEXT:    xvadddp vs0, vs0, vs2
-; PWR10BE-NEXT:    xxswapd vs1, vs0
-; PWR10BE-NEXT:    xvadddp vs1, vs0, vs1
+; PWR10BE-NEXT:    xvadddp vs0, v4, v8 # Vec Defs: VSL0(VSR0) Vec Uses: V4(VSR36)V8(VSR40)
+; PWR10BE-NEXT:    xvadddp vs1, v2, v6 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V6(VSR38)
+; PWR10BE-NEXT:    xvadddp vs2, v5, v9 # Vec Defs: VSL2(VSR2) Vec Uses: V5(VSR37)V9(VSR41)
+; PWR10BE-NEXT:    xvadddp vs3, v3, v7 # Vec Defs: VSL3(VSR3) Vec Uses: V3(VSR35)V7(VSR39)
+; PWR10BE-NEXT:    xvadddp vs2, vs3, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL3(VSR3)VSL2(VSR2)
+; PWR10BE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR10BE-NEXT:    xvadddp vs0, vs0, vs2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL2(VSR2)
+; PWR10BE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10BE-NEXT:    xvadddp vs1, vs0, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL1(VSR1)
 ; PWR10BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call fast double @llvm.vector.reduce.fadd.v16f64(double -0.000000e+00, <16 x double> %a)
   ret double %0
 }
 
 define dso_local double @v32f64(<32 x double> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v32f64:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxswapd vs4, v2
-; PWR9LE-NEXT:    xxswapd vs5, v3
-; PWR9LE-NEXT:    lxv vs3, 224(r1)
-; PWR9LE-NEXT:    lxv vs2, 240(r1)
-; PWR9LE-NEXT:    lxv vs1, 256(r1)
-; PWR9LE-NEXT:    lxv vs0, 272(r1)
-; PWR9LE-NEXT:    xsadddp f4, f4, v2
-; PWR9LE-NEXT:    xsadddp f4, f4, f5
-; PWR9LE-NEXT:    xxswapd vs5, v4
-; PWR9LE-NEXT:    xsadddp f4, f4, v3
-; PWR9LE-NEXT:    xsadddp f4, f4, f5
-; PWR9LE-NEXT:    xxswapd vs5, v5
-; PWR9LE-NEXT:    xsadddp f4, f4, v4
-; PWR9LE-NEXT:    xsadddp f4, f4, f5
-; PWR9LE-NEXT:    xxswapd vs5, v6
-; PWR9LE-NEXT:    xsadddp f4, f4, v5
-; PWR9LE-NEXT:    xsadddp f4, f4, f5
-; PWR9LE-NEXT:    xxswapd vs5, v7
-; PWR9LE-NEXT:    xsadddp f4, f4, v6
-; PWR9LE-NEXT:    xsadddp f4, f4, f5
-; PWR9LE-NEXT:    xxswapd vs5, v8
-; PWR9LE-NEXT:    xsadddp f4, f4, v7
-; PWR9LE-NEXT:    xsadddp f4, f4, f5
-; PWR9LE-NEXT:    xxswapd vs5, v9
-; PWR9LE-NEXT:    xsadddp f4, f4, v8
-; PWR9LE-NEXT:    xsadddp f4, f4, f5
-; PWR9LE-NEXT:    xxswapd vs5, v10
-; PWR9LE-NEXT:    xsadddp f4, f4, v9
-; PWR9LE-NEXT:    xsadddp f4, f4, f5
-; PWR9LE-NEXT:    xxswapd vs5, v11
-; PWR9LE-NEXT:    xsadddp f4, f4, v10
-; PWR9LE-NEXT:    xsadddp f4, f4, f5
-; PWR9LE-NEXT:    xxswapd vs5, v12
-; PWR9LE-NEXT:    xsadddp f4, f4, v11
-; PWR9LE-NEXT:    xsadddp f4, f4, f5
-; PWR9LE-NEXT:    xxswapd vs5, v13
-; PWR9LE-NEXT:    xsadddp f4, f4, v12
-; PWR9LE-NEXT:    xsadddp f4, f4, f5
-; PWR9LE-NEXT:    xxswapd vs5, vs3
-; PWR9LE-NEXT:    xsadddp f4, f4, v13
-; PWR9LE-NEXT:    xsadddp f4, f4, f5
-; PWR9LE-NEXT:    xsadddp f3, f4, f3
-; PWR9LE-NEXT:    xxswapd vs4, vs2
-; PWR9LE-NEXT:    xsadddp f3, f3, f4
-; PWR9LE-NEXT:    xsadddp f2, f3, f2
-; PWR9LE-NEXT:    xxswapd vs3, vs1
-; PWR9LE-NEXT:    xsadddp f2, f2, f3
-; PWR9LE-NEXT:    xsadddp f1, f2, f1
-; PWR9LE-NEXT:    xxswapd vs2, vs0
-; PWR9LE-NEXT:    xsadddp f1, f1, f2
-; PWR9LE-NEXT:    xsadddp f1, f1, f0
+; PWR9LE-NEXT:    xxswapd vs4, v2 # Vec Defs: VSL4(VSR4) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    xxswapd vs5, v3 # Vec Defs: VSL5(VSR5) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    lxv vs3, 224(r1) # Vec Defs: VSL3(VSR3)
+; PWR9LE-NEXT:    lxv vs2, 240(r1) # Vec Defs: VSL2(VSR2)
+; PWR9LE-NEXT:    lxv vs1, 256(r1) # Vec Defs: VSL1(VSR1)
+; PWR9LE-NEXT:    lxv vs0, 272(r1) # Vec Defs: VSL0(VSR0)
+; PWR9LE-NEXT:    xsadddp f4, f4, v2 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF2(VSR2)
+; PWR9LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v4 # Vec Defs: VSL5(VSR5) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9LE-NEXT:    xsadddp f4, f4, v3 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF3(VSR3)
+; PWR9LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v5 # Vec Defs: VSL5(VSR5) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9LE-NEXT:    xsadddp f4, f4, v4 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF4(VSR4)
+; PWR9LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v6 # Vec Defs: VSL5(VSR5) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR9LE-NEXT:    xsadddp f4, f4, v5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF5(VSR5)
+; PWR9LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v7 # Vec Defs: VSL5(VSR5) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR9LE-NEXT:    xsadddp f4, f4, v6 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF6(VSR6)
+; PWR9LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v8 # Vec Defs: VSL5(VSR5) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR9LE-NEXT:    xsadddp f4, f4, v7 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF7(VSR7)
+; PWR9LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v9 # Vec Defs: VSL5(VSR5) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR9LE-NEXT:    xsadddp f4, f4, v8 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF8(VSR8)
+; PWR9LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v10 # Vec Defs: VSL5(VSR5) Vec Uses: V10(VSR42)V10(VSR42)
+; PWR9LE-NEXT:    xsadddp f4, f4, v9 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF9(VSR9)
+; PWR9LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v11 # Vec Defs: VSL5(VSR5) Vec Uses: V11(VSR43)V11(VSR43)
+; PWR9LE-NEXT:    xsadddp f4, f4, v10 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF10(VSR10)
+; PWR9LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v12 # Vec Defs: VSL5(VSR5) Vec Uses: V12(VSR44)V12(VSR44)
+; PWR9LE-NEXT:    xsadddp f4, f4, v11 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF11(VSR11)
+; PWR9LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v13 # Vec Defs: VSL5(VSR5) Vec Uses: V13(VSR45)V13(VSR45)
+; PWR9LE-NEXT:    xsadddp f4, f4, v12 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF12(VSR12)
+; PWR9LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, vs3 # Vec Defs: VSL5(VSR5) Vec Uses: VSL3(VSR3)VSL3(VSR3)
+; PWR9LE-NEXT:    xsadddp f4, f4, v13 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF13(VSR13)
+; PWR9LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9LE-NEXT:    xsadddp f3, f4, f3 # Vec Defs: F3(VSR3) Vec Uses: F4(VSR4)F3(VSR3)
+; PWR9LE-NEXT:    xxswapd vs4, vs2 # Vec Defs: VSL4(VSR4) Vec Uses: VSL2(VSR2)VSL2(VSR2)
+; PWR9LE-NEXT:    xsadddp f3, f3, f4 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)F4(VSR4)
+; PWR9LE-NEXT:    xsadddp f2, f3, f2 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)F2(VSR2)
+; PWR9LE-NEXT:    xxswapd vs3, vs1 # Vec Defs: VSL3(VSR3) Vec Uses: VSL1(VSR1)VSL1(VSR1)
+; PWR9LE-NEXT:    xsadddp f2, f2, f3 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)F3(VSR3)
+; PWR9LE-NEXT:    xsadddp f1, f2, f1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs2, vs0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9LE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR9LE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v32f64:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xxswapd vs4, v2
-; PWR9BE-NEXT:    xxswapd vs5, v3
-; PWR9BE-NEXT:    lxv vs3, 240(r1)
-; PWR9BE-NEXT:    lxv vs2, 256(r1)
-; PWR9BE-NEXT:    lxv vs1, 272(r1)
-; PWR9BE-NEXT:    lxv vs0, 288(r1)
-; PWR9BE-NEXT:    xsadddp f4, v2, f4
-; PWR9BE-NEXT:    xsadddp f4, f4, v3
-; PWR9BE-NEXT:    xsadddp f4, f4, f5
-; PWR9BE-NEXT:    xxswapd vs5, v4
-; PWR9BE-NEXT:    xsadddp f4, f4, v4
-; PWR9BE-NEXT:    xsadddp f4, f4, f5
-; PWR9BE-NEXT:    xxswapd vs5, v5
-; PWR9BE-NEXT:    xsadddp f4, f4, v5
-; PWR9BE-NEXT:    xsadddp f4, f4, f5
-; PWR9BE-NEXT:    xxswapd vs5, v6
-; PWR9BE-NEXT:    xsadddp f4, f4, v6
-; PWR9BE-NEXT:    xsadddp f4, f4, f5
-; PWR9BE-NEXT:    xxswapd vs5, v7
-; PWR9BE-NEXT:    xsadddp f4, f4, v7
-; PWR9BE-NEXT:    xsadddp f4, f4, f5
-; PWR9BE-NEXT:    xxswapd vs5, v8
-; PWR9BE-NEXT:    xsadddp f4, f4, v8
-; PWR9BE-NEXT:    xsadddp f4, f4, f5
-; PWR9BE-NEXT:    xxswapd vs5, v9
-; PWR9BE-NEXT:    xsadddp f4, f4, v9
-; PWR9BE-NEXT:    xsadddp f4, f4, f5
-; PWR9BE-NEXT:    xxswapd vs5, v10
-; PWR9BE-NEXT:    xsadddp f4, f4, v10
-; PWR9BE-NEXT:    xsadddp f4, f4, f5
-; PWR9BE-NEXT:    xxswapd vs5, v11
-; PWR9BE-NEXT:    xsadddp f4, f4, v11
-; PWR9BE-NEXT:    xsadddp f4, f4, f5
-; PWR9BE-NEXT:    xxswapd vs5, v12
-; PWR9BE-NEXT:    xsadddp f4, f4, v12
-; PWR9BE-NEXT:    xsadddp f4, f4, f5
-; PWR9BE-NEXT:    xxswapd vs5, v13
-; PWR9BE-NEXT:    xsadddp f4, f4, v13
-; PWR9BE-NEXT:    xsadddp f4, f4, f5
-; PWR9BE-NEXT:    xsadddp f4, f4, f3
-; PWR9BE-NEXT:    xxswapd vs3, vs3
-; PWR9BE-NEXT:    xsadddp f3, f4, f3
-; PWR9BE-NEXT:    xsadddp f3, f3, f2
-; PWR9BE-NEXT:    xxswapd vs2, vs2
-; PWR9BE-NEXT:    xsadddp f2, f3, f2
-; PWR9BE-NEXT:    xsadddp f2, f2, f1
-; PWR9BE-NEXT:    xxswapd vs1, vs1
-; PWR9BE-NEXT:    xsadddp f1, f2, f1
-; PWR9BE-NEXT:    xsadddp f1, f1, f0
-; PWR9BE-NEXT:    xxswapd vs0, vs0
-; PWR9BE-NEXT:    xsadddp f1, f1, f0
+; PWR9BE-NEXT:    xxswapd vs4, v2 # Vec Defs: VSL4(VSR4) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    xxswapd vs5, v3 # Vec Defs: VSL5(VSR5) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    lxv vs3, 240(r1) # Vec Defs: VSL3(VSR3)
+; PWR9BE-NEXT:    lxv vs2, 256(r1) # Vec Defs: VSL2(VSR2)
+; PWR9BE-NEXT:    lxv vs1, 272(r1) # Vec Defs: VSL1(VSR1)
+; PWR9BE-NEXT:    lxv vs0, 288(r1) # Vec Defs: VSL0(VSR0)
+; PWR9BE-NEXT:    xsadddp f4, v2, f4 # Vec Defs: F4(VSR4) Vec Uses: VF2(VSR2)F4(VSR4)
+; PWR9BE-NEXT:    xsadddp f4, f4, v3 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF3(VSR3)
+; PWR9BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v4 # Vec Defs: VSL5(VSR5) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9BE-NEXT:    xsadddp f4, f4, v4 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF4(VSR4)
+; PWR9BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v5 # Vec Defs: VSL5(VSR5) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9BE-NEXT:    xsadddp f4, f4, v5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF5(VSR5)
+; PWR9BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v6 # Vec Defs: VSL5(VSR5) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR9BE-NEXT:    xsadddp f4, f4, v6 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF6(VSR6)
+; PWR9BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v7 # Vec Defs: VSL5(VSR5) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR9BE-NEXT:    xsadddp f4, f4, v7 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF7(VSR7)
+; PWR9BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v8 # Vec Defs: VSL5(VSR5) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR9BE-NEXT:    xsadddp f4, f4, v8 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF8(VSR8)
+; PWR9BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v9 # Vec Defs: VSL5(VSR5) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR9BE-NEXT:    xsadddp f4, f4, v9 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF9(VSR9)
+; PWR9BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v10 # Vec Defs: VSL5(VSR5) Vec Uses: V10(VSR42)V10(VSR42)
+; PWR9BE-NEXT:    xsadddp f4, f4, v10 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF10(VSR10)
+; PWR9BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v11 # Vec Defs: VSL5(VSR5) Vec Uses: V11(VSR43)V11(VSR43)
+; PWR9BE-NEXT:    xsadddp f4, f4, v11 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF11(VSR11)
+; PWR9BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v12 # Vec Defs: VSL5(VSR5) Vec Uses: V12(VSR44)V12(VSR44)
+; PWR9BE-NEXT:    xsadddp f4, f4, v12 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF12(VSR12)
+; PWR9BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v13 # Vec Defs: VSL5(VSR5) Vec Uses: V13(VSR45)V13(VSR45)
+; PWR9BE-NEXT:    xsadddp f4, f4, v13 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF13(VSR13)
+; PWR9BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9BE-NEXT:    xsadddp f4, f4, f3 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F3(VSR3)
+; PWR9BE-NEXT:    xxswapd vs3, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: VSL3(VSR3)VSL3(VSR3)
+; PWR9BE-NEXT:    xsadddp f3, f4, f3 # Vec Defs: F3(VSR3) Vec Uses: F4(VSR4)F3(VSR3)
+; PWR9BE-NEXT:    xsadddp f3, f3, f2 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)F2(VSR2)
+; PWR9BE-NEXT:    xxswapd vs2, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL2(VSR2)VSL2(VSR2)
+; PWR9BE-NEXT:    xsadddp f2, f3, f2 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)F2(VSR2)
+; PWR9BE-NEXT:    xsadddp f2, f2, f1 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)VSL1(VSR1)
+; PWR9BE-NEXT:    xsadddp f1, f2, f1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PWR9BE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR9BE-NEXT:    xxswapd vs0, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9BE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v32f64:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxswapd vs4, v2
-; PWR10LE-NEXT:    xxswapd vs5, v3
-; PWR10LE-NEXT:    lxv vs3, 224(r1)
-; PWR10LE-NEXT:    lxv vs2, 240(r1)
-; PWR10LE-NEXT:    xsadddp f4, f4, v2
-; PWR10LE-NEXT:    lxv vs1, 256(r1)
-; PWR10LE-NEXT:    lxv vs0, 272(r1)
-; PWR10LE-NEXT:    xsadddp f4, f4, f5
-; PWR10LE-NEXT:    xxswapd vs5, v4
-; PWR10LE-NEXT:    xsadddp f4, f4, v3
-; PWR10LE-NEXT:    xsadddp f4, f4, f5
-; PWR10LE-NEXT:    xxswapd vs5, v5
-; PWR10LE-NEXT:    xsadddp f4, f4, v4
-; PWR10LE-NEXT:    xsadddp f4, f4, f5
-; PWR10LE-NEXT:    xxswapd vs5, v6
-; PWR10LE-NEXT:    xsadddp f4, f4, v5
-; PWR10LE-NEXT:    xsadddp f4, f4, f5
-; PWR10LE-NEXT:    xxswapd vs5, v7
-; PWR10LE-NEXT:    xsadddp f4, f4, v6
-; PWR10LE-NEXT:    xsadddp f4, f4, f5
-; PWR10LE-NEXT:    xxswapd vs5, v8
-; PWR10LE-NEXT:    xsadddp f4, f4, v7
-; PWR10LE-NEXT:    xsadddp f4, f4, f5
-; PWR10LE-NEXT:    xxswapd vs5, v9
-; PWR10LE-NEXT:    xsadddp f4, f4, v8
-; PWR10LE-NEXT:    xsadddp f4, f4, f5
-; PWR10LE-NEXT:    xxswapd vs5, v10
-; PWR10LE-NEXT:    xsadddp f4, f4, v9
-; PWR10LE-NEXT:    xsadddp f4, f4, f5
-; PWR10LE-NEXT:    xxswapd vs5, v11
-; PWR10LE-NEXT:    xsadddp f4, f4, v10
-; PWR10LE-NEXT:    xsadddp f4, f4, f5
-; PWR10LE-NEXT:    xxswapd vs5, v12
-; PWR10LE-NEXT:    xsadddp f4, f4, v11
-; PWR10LE-NEXT:    xsadddp f4, f4, f5
-; PWR10LE-NEXT:    xxswapd vs5, v13
-; PWR10LE-NEXT:    xsadddp f4, f4, v12
-; PWR10LE-NEXT:    xsadddp f4, f4, f5
-; PWR10LE-NEXT:    xxswapd vs5, vs3
-; PWR10LE-NEXT:    xsadddp f4, f4, v13
-; PWR10LE-NEXT:    xsadddp f4, f4, f5
-; PWR10LE-NEXT:    xsadddp f3, f4, f3
-; PWR10LE-NEXT:    xxswapd vs4, vs2
-; PWR10LE-NEXT:    xsadddp f3, f3, f4
-; PWR10LE-NEXT:    xsadddp f2, f3, f2
-; PWR10LE-NEXT:    xxswapd vs3, vs1
-; PWR10LE-NEXT:    xsadddp f2, f2, f3
-; PWR10LE-NEXT:    xsadddp f1, f2, f1
-; PWR10LE-NEXT:    xxswapd vs2, vs0
-; PWR10LE-NEXT:    xsadddp f1, f1, f2
-; PWR10LE-NEXT:    xsadddp f1, f1, f0
+; PWR10LE-NEXT:    xxswapd vs4, v2 # Vec Defs: VSL4(VSR4) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    xxswapd vs5, v3 # Vec Defs: VSL5(VSR5) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    lxv vs3, 224(r1) # Vec Defs: VSL3(VSR3)
+; PWR10LE-NEXT:    lxv vs2, 240(r1) # Vec Defs: VSL2(VSR2)
+; PWR10LE-NEXT:    xsadddp f4, f4, v2 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF2(VSR2)
+; PWR10LE-NEXT:    lxv vs1, 256(r1) # Vec Defs: VSL1(VSR1)
+; PWR10LE-NEXT:    lxv vs0, 272(r1) # Vec Defs: VSL0(VSR0)
+; PWR10LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v4 # Vec Defs: VSL5(VSR5) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10LE-NEXT:    xsadddp f4, f4, v3 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF3(VSR3)
+; PWR10LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v5 # Vec Defs: VSL5(VSR5) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10LE-NEXT:    xsadddp f4, f4, v4 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF4(VSR4)
+; PWR10LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v6 # Vec Defs: VSL5(VSR5) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR10LE-NEXT:    xsadddp f4, f4, v5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF5(VSR5)
+; PWR10LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v7 # Vec Defs: VSL5(VSR5) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR10LE-NEXT:    xsadddp f4, f4, v6 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF6(VSR6)
+; PWR10LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v8 # Vec Defs: VSL5(VSR5) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR10LE-NEXT:    xsadddp f4, f4, v7 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF7(VSR7)
+; PWR10LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v9 # Vec Defs: VSL5(VSR5) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR10LE-NEXT:    xsadddp f4, f4, v8 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF8(VSR8)
+; PWR10LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v10 # Vec Defs: VSL5(VSR5) Vec Uses: V10(VSR42)V10(VSR42)
+; PWR10LE-NEXT:    xsadddp f4, f4, v9 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF9(VSR9)
+; PWR10LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v11 # Vec Defs: VSL5(VSR5) Vec Uses: V11(VSR43)V11(VSR43)
+; PWR10LE-NEXT:    xsadddp f4, f4, v10 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF10(VSR10)
+; PWR10LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v12 # Vec Defs: VSL5(VSR5) Vec Uses: V12(VSR44)V12(VSR44)
+; PWR10LE-NEXT:    xsadddp f4, f4, v11 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF11(VSR11)
+; PWR10LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v13 # Vec Defs: VSL5(VSR5) Vec Uses: V13(VSR45)V13(VSR45)
+; PWR10LE-NEXT:    xsadddp f4, f4, v12 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF12(VSR12)
+; PWR10LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, vs3 # Vec Defs: VSL5(VSR5) Vec Uses: VSL3(VSR3)VSL3(VSR3)
+; PWR10LE-NEXT:    xsadddp f4, f4, v13 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF13(VSR13)
+; PWR10LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10LE-NEXT:    xsadddp f3, f4, f3 # Vec Defs: F3(VSR3) Vec Uses: F4(VSR4)F3(VSR3)
+; PWR10LE-NEXT:    xxswapd vs4, vs2 # Vec Defs: VSL4(VSR4) Vec Uses: VSL2(VSR2)VSL2(VSR2)
+; PWR10LE-NEXT:    xsadddp f3, f3, f4 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)F4(VSR4)
+; PWR10LE-NEXT:    xsadddp f2, f3, f2 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)F2(VSR2)
+; PWR10LE-NEXT:    xxswapd vs3, vs1 # Vec Defs: VSL3(VSR3) Vec Uses: VSL1(VSR1)VSL1(VSR1)
+; PWR10LE-NEXT:    xsadddp f2, f2, f3 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)F3(VSR3)
+; PWR10LE-NEXT:    xsadddp f1, f2, f1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs2, vs0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10LE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR10LE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v32f64:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xxswapd vs4, v2
-; PWR10BE-NEXT:    xxswapd vs5, v3
-; PWR10BE-NEXT:    lxv vs3, 240(r1)
-; PWR10BE-NEXT:    lxv vs2, 256(r1)
-; PWR10BE-NEXT:    xsadddp f4, v2, f4
-; PWR10BE-NEXT:    lxv vs1, 272(r1)
-; PWR10BE-NEXT:    lxv vs0, 288(r1)
-; PWR10BE-NEXT:    xsadddp f4, f4, v3
-; PWR10BE-NEXT:    xsadddp f4, f4, f5
-; PWR10BE-NEXT:    xxswapd vs5, v4
-; PWR10BE-NEXT:    xsadddp f4, f4, v4
-; PWR10BE-NEXT:    xsadddp f4, f4, f5
-; PWR10BE-NEXT:    xxswapd vs5, v5
-; PWR10BE-NEXT:    xsadddp f4, f4, v5
-; PWR10BE-NEXT:    xsadddp f4, f4, f5
-; PWR10BE-NEXT:    xxswapd vs5, v6
-; PWR10BE-NEXT:    xsadddp f4, f4, v6
-; PWR10BE-NEXT:    xsadddp f4, f4, f5
-; PWR10BE-NEXT:    xxswapd vs5, v7
-; PWR10BE-NEXT:    xsadddp f4, f4, v7
-; PWR10BE-NEXT:    xsadddp f4, f4, f5
-; PWR10BE-NEXT:    xxswapd vs5, v8
-; PWR10BE-NEXT:    xsadddp f4, f4, v8
-; PWR10BE-NEXT:    xsadddp f4, f4, f5
-; PWR10BE-NEXT:    xxswapd vs5, v9
-; PWR10BE-NEXT:    xsadddp f4, f4, v9
-; PWR10BE-NEXT:    xsadddp f4, f4, f5
-; PWR10BE-NEXT:    xxswapd vs5, v10
-; PWR10BE-NEXT:    xsadddp f4, f4, v10
-; PWR10BE-NEXT:    xsadddp f4, f4, f5
-; PWR10BE-NEXT:    xxswapd vs5, v11
-; PWR10BE-NEXT:    xsadddp f4, f4, v11
-; PWR10BE-NEXT:    xsadddp f4, f4, f5
-; PWR10BE-NEXT:    xxswapd vs5, v12
-; PWR10BE-NEXT:    xsadddp f4, f4, v12
-; PWR10BE-NEXT:    xsadddp f4, f4, f5
-; PWR10BE-NEXT:    xxswapd vs5, v13
-; PWR10BE-NEXT:    xsadddp f4, f4, v13
-; PWR10BE-NEXT:    xsadddp f4, f4, f5
-; PWR10BE-NEXT:    xsadddp f4, f4, f3
-; PWR10BE-NEXT:    xxswapd vs3, vs3
-; PWR10BE-NEXT:    xsadddp f3, f4, f3
-; PWR10BE-NEXT:    xsadddp f3, f3, f2
-; PWR10BE-NEXT:    xxswapd vs2, vs2
-; PWR10BE-NEXT:    xsadddp f2, f3, f2
-; PWR10BE-NEXT:    xsadddp f2, f2, f1
-; PWR10BE-NEXT:    xxswapd vs1, vs1
-; PWR10BE-NEXT:    xsadddp f1, f2, f1
-; PWR10BE-NEXT:    xsadddp f1, f1, f0
-; PWR10BE-NEXT:    xxswapd vs0, vs0
-; PWR10BE-NEXT:    xsadddp f1, f1, f0
+; PWR10BE-NEXT:    xxswapd vs4, v2 # Vec Defs: VSL4(VSR4) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    xxswapd vs5, v3 # Vec Defs: VSL5(VSR5) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    lxv vs3, 240(r1) # Vec Defs: VSL3(VSR3)
+; PWR10BE-NEXT:    lxv vs2, 256(r1) # Vec Defs: VSL2(VSR2)
+; PWR10BE-NEXT:    xsadddp f4, v2, f4 # Vec Defs: F4(VSR4) Vec Uses: VF2(VSR2)F4(VSR4)
+; PWR10BE-NEXT:    lxv vs1, 272(r1) # Vec Defs: VSL1(VSR1)
+; PWR10BE-NEXT:    lxv vs0, 288(r1) # Vec Defs: VSL0(VSR0)
+; PWR10BE-NEXT:    xsadddp f4, f4, v3 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF3(VSR3)
+; PWR10BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v4 # Vec Defs: VSL5(VSR5) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10BE-NEXT:    xsadddp f4, f4, v4 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF4(VSR4)
+; PWR10BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v5 # Vec Defs: VSL5(VSR5) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10BE-NEXT:    xsadddp f4, f4, v5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF5(VSR5)
+; PWR10BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v6 # Vec Defs: VSL5(VSR5) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR10BE-NEXT:    xsadddp f4, f4, v6 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF6(VSR6)
+; PWR10BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v7 # Vec Defs: VSL5(VSR5) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR10BE-NEXT:    xsadddp f4, f4, v7 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF7(VSR7)
+; PWR10BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v8 # Vec Defs: VSL5(VSR5) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR10BE-NEXT:    xsadddp f4, f4, v8 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF8(VSR8)
+; PWR10BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v9 # Vec Defs: VSL5(VSR5) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR10BE-NEXT:    xsadddp f4, f4, v9 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF9(VSR9)
+; PWR10BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v10 # Vec Defs: VSL5(VSR5) Vec Uses: V10(VSR42)V10(VSR42)
+; PWR10BE-NEXT:    xsadddp f4, f4, v10 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF10(VSR10)
+; PWR10BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v11 # Vec Defs: VSL5(VSR5) Vec Uses: V11(VSR43)V11(VSR43)
+; PWR10BE-NEXT:    xsadddp f4, f4, v11 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF11(VSR11)
+; PWR10BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v12 # Vec Defs: VSL5(VSR5) Vec Uses: V12(VSR44)V12(VSR44)
+; PWR10BE-NEXT:    xsadddp f4, f4, v12 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF12(VSR12)
+; PWR10BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v13 # Vec Defs: VSL5(VSR5) Vec Uses: V13(VSR45)V13(VSR45)
+; PWR10BE-NEXT:    xsadddp f4, f4, v13 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)VF13(VSR13)
+; PWR10BE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10BE-NEXT:    xsadddp f4, f4, f3 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F3(VSR3)
+; PWR10BE-NEXT:    xxswapd vs3, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: VSL3(VSR3)VSL3(VSR3)
+; PWR10BE-NEXT:    xsadddp f3, f4, f3 # Vec Defs: F3(VSR3) Vec Uses: F4(VSR4)F3(VSR3)
+; PWR10BE-NEXT:    xsadddp f3, f3, f2 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)F2(VSR2)
+; PWR10BE-NEXT:    xxswapd vs2, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL2(VSR2)VSL2(VSR2)
+; PWR10BE-NEXT:    xsadddp f2, f3, f2 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)F2(VSR2)
+; PWR10BE-NEXT:    xsadddp f2, f2, f1 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)VSL1(VSR1)
+; PWR10BE-NEXT:    xsadddp f1, f2, f1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PWR10BE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR10BE-NEXT:    xxswapd vs0, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10BE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call double @llvm.vector.reduce.fadd.v32f64(double -0.000000e+00, <32 x double> %a)
   ret double %0
 }
 
 define dso_local double @v32f64_b(<32 x double> %a, double %b) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v32f64_b:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxswapd vs5, v2
-; PWR9LE-NEXT:    lxv vs4, 224(r1)
-; PWR9LE-NEXT:    lxv vs3, 240(r1)
-; PWR9LE-NEXT:    lxv vs2, 256(r1)
-; PWR9LE-NEXT:    lxv vs0, 272(r1)
-; PWR9LE-NEXT:    xsadddp f1, f1, f5
-; PWR9LE-NEXT:    xxswapd vs5, v3
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xsadddp f1, f1, f5
-; PWR9LE-NEXT:    xxswapd vs5, v4
-; PWR9LE-NEXT:    xsadddp f1, f1, v3
-; PWR9LE-NEXT:    xsadddp f1, f1, f5
-; PWR9LE-NEXT:    xxswapd vs5, v5
-; PWR9LE-NEXT:    xsadddp f1, f1, v4
-; PWR9LE-NEXT:    xsadddp f1, f1, f5
-; PWR9LE-NEXT:    xxswapd vs5, v6
-; PWR9LE-NEXT:    xsadddp f1, f1, v5
-; PWR9LE-NEXT:    xsadddp f1, f1, f5
-; PWR9LE-NEXT:    xxswapd vs5, v7
-; PWR9LE-NEXT:    xsadddp f1, f1, v6
-; PWR9LE-NEXT:    xsadddp f1, f1, f5
-; PWR9LE-NEXT:    xxswapd vs5, v8
-; PWR9LE-NEXT:    xsadddp f1, f1, v7
-; PWR9LE-NEXT:    xsadddp f1, f1, f5
-; PWR9LE-NEXT:    xxswapd vs5, v9
-; PWR9LE-NEXT:    xsadddp f1, f1, v8
-; PWR9LE-NEXT:    xsadddp f1, f1, f5
-; PWR9LE-NEXT:    xxswapd vs5, v10
-; PWR9LE-NEXT:    xsadddp f1, f1, v9
-; PWR9LE-NEXT:    xsadddp f1, f1, f5
-; PWR9LE-NEXT:    xxswapd vs5, v11
-; PWR9LE-NEXT:    xsadddp f1, f1, v10
-; PWR9LE-NEXT:    xsadddp f1, f1, f5
-; PWR9LE-NEXT:    xxswapd vs5, v12
-; PWR9LE-NEXT:    xsadddp f1, f1, v11
-; PWR9LE-NEXT:    xsadddp f1, f1, f5
-; PWR9LE-NEXT:    xxswapd vs5, v13
-; PWR9LE-NEXT:    xsadddp f1, f1, v12
-; PWR9LE-NEXT:    xsadddp f1, f1, f5
-; PWR9LE-NEXT:    xxswapd vs5, vs4
-; PWR9LE-NEXT:    xsadddp f1, f1, v13
-; PWR9LE-NEXT:    xsadddp f1, f1, f5
-; PWR9LE-NEXT:    xsadddp f1, f1, f4
-; PWR9LE-NEXT:    xxswapd vs4, vs3
-; PWR9LE-NEXT:    xsadddp f1, f1, f4
-; PWR9LE-NEXT:    xsadddp f1, f1, f3
-; PWR9LE-NEXT:    xxswapd vs3, vs2
-; PWR9LE-NEXT:    xsadddp f1, f1, f3
-; PWR9LE-NEXT:    xsadddp f1, f1, f2
-; PWR9LE-NEXT:    xxswapd vs2, vs0
-; PWR9LE-NEXT:    xsadddp f1, f1, f2
-; PWR9LE-NEXT:    xsadddp f1, f1, f0
+; PWR9LE-NEXT:    xxswapd vs5, v2 # Vec Defs: VSL5(VSR5) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    lxv vs4, 224(r1) # Vec Defs: VSL4(VSR4)
+; PWR9LE-NEXT:    lxv vs3, 240(r1) # Vec Defs: VSL3(VSR3)
+; PWR9LE-NEXT:    lxv vs2, 256(r1) # Vec Defs: VSL2(VSR2)
+; PWR9LE-NEXT:    lxv vs0, 272(r1) # Vec Defs: VSL0(VSR0)
+; PWR9LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v3 # Vec Defs: VSL5(VSR5) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v4 # Vec Defs: VSL5(VSR5) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9LE-NEXT:    xsadddp f1, f1, v3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF3(VSR3)
+; PWR9LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v5 # Vec Defs: VSL5(VSR5) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9LE-NEXT:    xsadddp f1, f1, v4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF4(VSR4)
+; PWR9LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v6 # Vec Defs: VSL5(VSR5) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR9LE-NEXT:    xsadddp f1, f1, v5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF5(VSR5)
+; PWR9LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v7 # Vec Defs: VSL5(VSR5) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR9LE-NEXT:    xsadddp f1, f1, v6 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF6(VSR6)
+; PWR9LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v8 # Vec Defs: VSL5(VSR5) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR9LE-NEXT:    xsadddp f1, f1, v7 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF7(VSR7)
+; PWR9LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v9 # Vec Defs: VSL5(VSR5) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR9LE-NEXT:    xsadddp f1, f1, v8 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF8(VSR8)
+; PWR9LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v10 # Vec Defs: VSL5(VSR5) Vec Uses: V10(VSR42)V10(VSR42)
+; PWR9LE-NEXT:    xsadddp f1, f1, v9 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF9(VSR9)
+; PWR9LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v11 # Vec Defs: VSL5(VSR5) Vec Uses: V11(VSR43)V11(VSR43)
+; PWR9LE-NEXT:    xsadddp f1, f1, v10 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF10(VSR10)
+; PWR9LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v12 # Vec Defs: VSL5(VSR5) Vec Uses: V12(VSR44)V12(VSR44)
+; PWR9LE-NEXT:    xsadddp f1, f1, v11 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF11(VSR11)
+; PWR9LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, v13 # Vec Defs: VSL5(VSR5) Vec Uses: V13(VSR45)V13(VSR45)
+; PWR9LE-NEXT:    xsadddp f1, f1, v12 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF12(VSR12)
+; PWR9LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, vs4 # Vec Defs: VSL5(VSR5) Vec Uses: VSL4(VSR4)VSL4(VSR4)
+; PWR9LE-NEXT:    xsadddp f1, f1, v13 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF13(VSR13)
+; PWR9LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9LE-NEXT:    xsadddp f1, f1, f4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F4(VSR4)
+; PWR9LE-NEXT:    xxswapd vs4, vs3 # Vec Defs: VSL4(VSR4) Vec Uses: VSL3(VSR3)VSL3(VSR3)
+; PWR9LE-NEXT:    xsadddp f1, f1, f4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F4(VSR4)
+; PWR9LE-NEXT:    xsadddp f1, f1, f3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F3(VSR3)
+; PWR9LE-NEXT:    xxswapd vs3, vs2 # Vec Defs: VSL3(VSR3) Vec Uses: VSL2(VSR2)VSL2(VSR2)
+; PWR9LE-NEXT:    xsadddp f1, f1, f3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F3(VSR3)
+; PWR9LE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR9LE-NEXT:    xxswapd vs2, vs0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9LE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR9LE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v32f64_b:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd vs5, v2
-; PWR9BE-NEXT:    lxv vs4, 240(r1)
-; PWR9BE-NEXT:    lxv vs3, 256(r1)
-; PWR9BE-NEXT:    lxv vs2, 272(r1)
-; PWR9BE-NEXT:    lxv vs0, 288(r1)
-; PWR9BE-NEXT:    xsadddp f1, f1, f5
-; PWR9BE-NEXT:    xxswapd vs5, v3
-; PWR9BE-NEXT:    xsadddp f1, f1, v3
-; PWR9BE-NEXT:    xsadddp f1, f1, f5
-; PWR9BE-NEXT:    xxswapd vs5, v4
-; PWR9BE-NEXT:    xsadddp f1, f1, v4
-; PWR9BE-NEXT:    xsadddp f1, f1, f5
-; PWR9BE-NEXT:    xxswapd vs5, v5
-; PWR9BE-NEXT:    xsadddp f1, f1, v5
-; PWR9BE-NEXT:    xsadddp f1, f1, f5
-; PWR9BE-NEXT:    xxswapd vs5, v6
-; PWR9BE-NEXT:    xsadddp f1, f1, v6
-; PWR9BE-NEXT:    xsadddp f1, f1, f5
-; PWR9BE-NEXT:    xxswapd vs5, v7
-; PWR9BE-NEXT:    xsadddp f1, f1, v7
-; PWR9BE-NEXT:    xsadddp f1, f1, f5
-; PWR9BE-NEXT:    xxswapd vs5, v8
-; PWR9BE-NEXT:    xsadddp f1, f1, v8
-; PWR9BE-NEXT:    xsadddp f1, f1, f5
-; PWR9BE-NEXT:    xxswapd vs5, v9
-; PWR9BE-NEXT:    xsadddp f1, f1, v9
-; PWR9BE-NEXT:    xsadddp f1, f1, f5
-; PWR9BE-NEXT:    xxswapd vs5, v10
-; PWR9BE-NEXT:    xsadddp f1, f1, v10
-; PWR9BE-NEXT:    xsadddp f1, f1, f5
-; PWR9BE-NEXT:    xxswapd vs5, v11
-; PWR9BE-NEXT:    xsadddp f1, f1, v11
-; PWR9BE-NEXT:    xsadddp f1, f1, f5
-; PWR9BE-NEXT:    xxswapd vs5, v12
-; PWR9BE-NEXT:    xsadddp f1, f1, v12
-; PWR9BE-NEXT:    xsadddp f1, f1, f5
-; PWR9BE-NEXT:    xxswapd vs5, v13
-; PWR9BE-NEXT:    xsadddp f1, f1, v13
-; PWR9BE-NEXT:    xsadddp f1, f1, f5
-; PWR9BE-NEXT:    xsadddp f1, f1, f4
-; PWR9BE-NEXT:    xxswapd vs4, vs4
-; PWR9BE-NEXT:    xsadddp f1, f1, f4
-; PWR9BE-NEXT:    xsadddp f1, f1, f3
-; PWR9BE-NEXT:    xxswapd vs3, vs3
-; PWR9BE-NEXT:    xsadddp f1, f1, f3
-; PWR9BE-NEXT:    xsadddp f1, f1, f2
-; PWR9BE-NEXT:    xxswapd vs2, vs2
-; PWR9BE-NEXT:    xsadddp f1, f1, f2
-; PWR9BE-NEXT:    xsadddp f1, f1, f0
-; PWR9BE-NEXT:    xxswapd vs0, vs0
-; PWR9BE-NEXT:    xsadddp f1, f1, f0
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd vs5, v2 # Vec Defs: VSL5(VSR5) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    lxv vs4, 240(r1) # Vec Defs: VSL4(VSR4)
+; PWR9BE-NEXT:    lxv vs3, 256(r1) # Vec Defs: VSL3(VSR3)
+; PWR9BE-NEXT:    lxv vs2, 272(r1) # Vec Defs: VSL2(VSR2)
+; PWR9BE-NEXT:    lxv vs0, 288(r1) # Vec Defs: VSL0(VSR0)
+; PWR9BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v3 # Vec Defs: VSL5(VSR5) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    xsadddp f1, f1, v3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF3(VSR3)
+; PWR9BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v4 # Vec Defs: VSL5(VSR5) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9BE-NEXT:    xsadddp f1, f1, v4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF4(VSR4)
+; PWR9BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v5 # Vec Defs: VSL5(VSR5) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9BE-NEXT:    xsadddp f1, f1, v5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF5(VSR5)
+; PWR9BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v6 # Vec Defs: VSL5(VSR5) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR9BE-NEXT:    xsadddp f1, f1, v6 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF6(VSR6)
+; PWR9BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v7 # Vec Defs: VSL5(VSR5) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR9BE-NEXT:    xsadddp f1, f1, v7 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF7(VSR7)
+; PWR9BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v8 # Vec Defs: VSL5(VSR5) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR9BE-NEXT:    xsadddp f1, f1, v8 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF8(VSR8)
+; PWR9BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v9 # Vec Defs: VSL5(VSR5) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR9BE-NEXT:    xsadddp f1, f1, v9 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF9(VSR9)
+; PWR9BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v10 # Vec Defs: VSL5(VSR5) Vec Uses: V10(VSR42)V10(VSR42)
+; PWR9BE-NEXT:    xsadddp f1, f1, v10 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF10(VSR10)
+; PWR9BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v11 # Vec Defs: VSL5(VSR5) Vec Uses: V11(VSR43)V11(VSR43)
+; PWR9BE-NEXT:    xsadddp f1, f1, v11 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF11(VSR11)
+; PWR9BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v12 # Vec Defs: VSL5(VSR5) Vec Uses: V12(VSR44)V12(VSR44)
+; PWR9BE-NEXT:    xsadddp f1, f1, v12 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF12(VSR12)
+; PWR9BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, v13 # Vec Defs: VSL5(VSR5) Vec Uses: V13(VSR45)V13(VSR45)
+; PWR9BE-NEXT:    xsadddp f1, f1, v13 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF13(VSR13)
+; PWR9BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9BE-NEXT:    xsadddp f1, f1, f4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F4(VSR4)
+; PWR9BE-NEXT:    xxswapd vs4, vs4 # Vec Defs: VSL4(VSR4) Vec Uses: VSL4(VSR4)VSL4(VSR4)
+; PWR9BE-NEXT:    xsadddp f1, f1, f4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F4(VSR4)
+; PWR9BE-NEXT:    xsadddp f1, f1, f3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F3(VSR3)
+; PWR9BE-NEXT:    xxswapd vs3, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: VSL3(VSR3)VSL3(VSR3)
+; PWR9BE-NEXT:    xsadddp f1, f1, f3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F3(VSR3)
+; PWR9BE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR9BE-NEXT:    xxswapd vs2, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL2(VSR2)VSL2(VSR2)
+; PWR9BE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR9BE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR9BE-NEXT:    xxswapd vs0, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9BE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v32f64_b:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxswapd vs5, v2
-; PWR10LE-NEXT:    lxv vs4, 224(r1)
-; PWR10LE-NEXT:    lxv vs3, 240(r1)
-; PWR10LE-NEXT:    xsadddp f1, f1, f5
-; PWR10LE-NEXT:    xxswapd vs5, v3
-; PWR10LE-NEXT:    lxv vs2, 256(r1)
-; PWR10LE-NEXT:    lxv vs0, 272(r1)
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xsadddp f1, f1, f5
-; PWR10LE-NEXT:    xxswapd vs5, v4
-; PWR10LE-NEXT:    xsadddp f1, f1, v3
-; PWR10LE-NEXT:    xsadddp f1, f1, f5
-; PWR10LE-NEXT:    xxswapd vs5, v5
-; PWR10LE-NEXT:    xsadddp f1, f1, v4
-; PWR10LE-NEXT:    xsadddp f1, f1, f5
-; PWR10LE-NEXT:    xxswapd vs5, v6
-; PWR10LE-NEXT:    xsadddp f1, f1, v5
-; PWR10LE-NEXT:    xsadddp f1, f1, f5
-; PWR10LE-NEXT:    xxswapd vs5, v7
-; PWR10LE-NEXT:    xsadddp f1, f1, v6
-; PWR10LE-NEXT:    xsadddp f1, f1, f5
-; PWR10LE-NEXT:    xxswapd vs5, v8
-; PWR10LE-NEXT:    xsadddp f1, f1, v7
-; PWR10LE-NEXT:    xsadddp f1, f1, f5
-; PWR10LE-NEXT:    xxswapd vs5, v9
-; PWR10LE-NEXT:    xsadddp f1, f1, v8
-; PWR10LE-NEXT:    xsadddp f1, f1, f5
-; PWR10LE-NEXT:    xxswapd vs5, v10
-; PWR10LE-NEXT:    xsadddp f1, f1, v9
-; PWR10LE-NEXT:    xsadddp f1, f1, f5
-; PWR10LE-NEXT:    xxswapd vs5, v11
-; PWR10LE-NEXT:    xsadddp f1, f1, v10
-; PWR10LE-NEXT:    xsadddp f1, f1, f5
-; PWR10LE-NEXT:    xxswapd vs5, v12
-; PWR10LE-NEXT:    xsadddp f1, f1, v11
-; PWR10LE-NEXT:    xsadddp f1, f1, f5
-; PWR10LE-NEXT:    xxswapd vs5, v13
-; PWR10LE-NEXT:    xsadddp f1, f1, v12
-; PWR10LE-NEXT:    xsadddp f1, f1, f5
-; PWR10LE-NEXT:    xxswapd vs5, vs4
-; PWR10LE-NEXT:    xsadddp f1, f1, v13
-; PWR10LE-NEXT:    xsadddp f1, f1, f5
-; PWR10LE-NEXT:    xsadddp f1, f1, f4
-; PWR10LE-NEXT:    xxswapd vs4, vs3
-; PWR10LE-NEXT:    xsadddp f1, f1, f4
-; PWR10LE-NEXT:    xsadddp f1, f1, f3
-; PWR10LE-NEXT:    xxswapd vs3, vs2
-; PWR10LE-NEXT:    xsadddp f1, f1, f3
-; PWR10LE-NEXT:    xsadddp f1, f1, f2
-; PWR10LE-NEXT:    xxswapd vs2, vs0
-; PWR10LE-NEXT:    xsadddp f1, f1, f2
-; PWR10LE-NEXT:    xsadddp f1, f1, f0
+; PWR10LE-NEXT:    xxswapd vs5, v2 # Vec Defs: VSL5(VSR5) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    lxv vs4, 224(r1) # Vec Defs: VSL4(VSR4)
+; PWR10LE-NEXT:    lxv vs3, 240(r1) # Vec Defs: VSL3(VSR3)
+; PWR10LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v3 # Vec Defs: VSL5(VSR5) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    lxv vs2, 256(r1) # Vec Defs: VSL2(VSR2)
+; PWR10LE-NEXT:    lxv vs0, 272(r1) # Vec Defs: VSL0(VSR0)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v4 # Vec Defs: VSL5(VSR5) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10LE-NEXT:    xsadddp f1, f1, v3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF3(VSR3)
+; PWR10LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v5 # Vec Defs: VSL5(VSR5) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10LE-NEXT:    xsadddp f1, f1, v4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF4(VSR4)
+; PWR10LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v6 # Vec Defs: VSL5(VSR5) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR10LE-NEXT:    xsadddp f1, f1, v5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF5(VSR5)
+; PWR10LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v7 # Vec Defs: VSL5(VSR5) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR10LE-NEXT:    xsadddp f1, f1, v6 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF6(VSR6)
+; PWR10LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v8 # Vec Defs: VSL5(VSR5) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR10LE-NEXT:    xsadddp f1, f1, v7 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF7(VSR7)
+; PWR10LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v9 # Vec Defs: VSL5(VSR5) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR10LE-NEXT:    xsadddp f1, f1, v8 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF8(VSR8)
+; PWR10LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v10 # Vec Defs: VSL5(VSR5) Vec Uses: V10(VSR42)V10(VSR42)
+; PWR10LE-NEXT:    xsadddp f1, f1, v9 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF9(VSR9)
+; PWR10LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v11 # Vec Defs: VSL5(VSR5) Vec Uses: V11(VSR43)V11(VSR43)
+; PWR10LE-NEXT:    xsadddp f1, f1, v10 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF10(VSR10)
+; PWR10LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v12 # Vec Defs: VSL5(VSR5) Vec Uses: V12(VSR44)V12(VSR44)
+; PWR10LE-NEXT:    xsadddp f1, f1, v11 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF11(VSR11)
+; PWR10LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, v13 # Vec Defs: VSL5(VSR5) Vec Uses: V13(VSR45)V13(VSR45)
+; PWR10LE-NEXT:    xsadddp f1, f1, v12 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF12(VSR12)
+; PWR10LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, vs4 # Vec Defs: VSL5(VSR5) Vec Uses: VSL4(VSR4)VSL4(VSR4)
+; PWR10LE-NEXT:    xsadddp f1, f1, v13 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF13(VSR13)
+; PWR10LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10LE-NEXT:    xsadddp f1, f1, f4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F4(VSR4)
+; PWR10LE-NEXT:    xxswapd vs4, vs3 # Vec Defs: VSL4(VSR4) Vec Uses: VSL3(VSR3)VSL3(VSR3)
+; PWR10LE-NEXT:    xsadddp f1, f1, f4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F4(VSR4)
+; PWR10LE-NEXT:    xsadddp f1, f1, f3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F3(VSR3)
+; PWR10LE-NEXT:    xxswapd vs3, vs2 # Vec Defs: VSL3(VSR3) Vec Uses: VSL2(VSR2)VSL2(VSR2)
+; PWR10LE-NEXT:    xsadddp f1, f1, f3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F3(VSR3)
+; PWR10LE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR10LE-NEXT:    xxswapd vs2, vs0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10LE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR10LE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v32f64_b:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd vs5, v2
-; PWR10BE-NEXT:    lxv vs4, 240(r1)
-; PWR10BE-NEXT:    lxv vs3, 256(r1)
-; PWR10BE-NEXT:    xsadddp f1, f1, f5
-; PWR10BE-NEXT:    xxswapd vs5, v3
-; PWR10BE-NEXT:    lxv vs2, 272(r1)
-; PWR10BE-NEXT:    lxv vs0, 288(r1)
-; PWR10BE-NEXT:    xsadddp f1, f1, v3
-; PWR10BE-NEXT:    xsadddp f1, f1, f5
-; PWR10BE-NEXT:    xxswapd vs5, v4
-; PWR10BE-NEXT:    xsadddp f1, f1, v4
-; PWR10BE-NEXT:    xsadddp f1, f1, f5
-; PWR10BE-NEXT:    xxswapd vs5, v5
-; PWR10BE-NEXT:    xsadddp f1, f1, v5
-; PWR10BE-NEXT:    xsadddp f1, f1, f5
-; PWR10BE-NEXT:    xxswapd vs5, v6
-; PWR10BE-NEXT:    xsadddp f1, f1, v6
-; PWR10BE-NEXT:    xsadddp f1, f1, f5
-; PWR10BE-NEXT:    xxswapd vs5, v7
-; PWR10BE-NEXT:    xsadddp f1, f1, v7
-; PWR10BE-NEXT:    xsadddp f1, f1, f5
-; PWR10BE-NEXT:    xxswapd vs5, v8
-; PWR10BE-NEXT:    xsadddp f1, f1, v8
-; PWR10BE-NEXT:    xsadddp f1, f1, f5
-; PWR10BE-NEXT:    xxswapd vs5, v9
-; PWR10BE-NEXT:    xsadddp f1, f1, v9
-; PWR10BE-NEXT:    xsadddp f1, f1, f5
-; PWR10BE-NEXT:    xxswapd vs5, v10
-; PWR10BE-NEXT:    xsadddp f1, f1, v10
-; PWR10BE-NEXT:    xsadddp f1, f1, f5
-; PWR10BE-NEXT:    xxswapd vs5, v11
-; PWR10BE-NEXT:    xsadddp f1, f1, v11
-; PWR10BE-NEXT:    xsadddp f1, f1, f5
-; PWR10BE-NEXT:    xxswapd vs5, v12
-; PWR10BE-NEXT:    xsadddp f1, f1, v12
-; PWR10BE-NEXT:    xsadddp f1, f1, f5
-; PWR10BE-NEXT:    xxswapd vs5, v13
-; PWR10BE-NEXT:    xsadddp f1, f1, v13
-; PWR10BE-NEXT:    xsadddp f1, f1, f5
-; PWR10BE-NEXT:    xsadddp f1, f1, f4
-; PWR10BE-NEXT:    xxswapd vs4, vs4
-; PWR10BE-NEXT:    xsadddp f1, f1, f4
-; PWR10BE-NEXT:    xsadddp f1, f1, f3
-; PWR10BE-NEXT:    xxswapd vs3, vs3
-; PWR10BE-NEXT:    xsadddp f1, f1, f3
-; PWR10BE-NEXT:    xsadddp f1, f1, f2
-; PWR10BE-NEXT:    xxswapd vs2, vs2
-; PWR10BE-NEXT:    xsadddp f1, f1, f2
-; PWR10BE-NEXT:    xsadddp f1, f1, f0
-; PWR10BE-NEXT:    xxswapd vs0, vs0
-; PWR10BE-NEXT:    xsadddp f1, f1, f0
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd vs5, v2 # Vec Defs: VSL5(VSR5) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    lxv vs4, 240(r1) # Vec Defs: VSL4(VSR4)
+; PWR10BE-NEXT:    lxv vs3, 256(r1) # Vec Defs: VSL3(VSR3)
+; PWR10BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v3 # Vec Defs: VSL5(VSR5) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    lxv vs2, 272(r1) # Vec Defs: VSL2(VSR2)
+; PWR10BE-NEXT:    lxv vs0, 288(r1) # Vec Defs: VSL0(VSR0)
+; PWR10BE-NEXT:    xsadddp f1, f1, v3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF3(VSR3)
+; PWR10BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v4 # Vec Defs: VSL5(VSR5) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10BE-NEXT:    xsadddp f1, f1, v4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF4(VSR4)
+; PWR10BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v5 # Vec Defs: VSL5(VSR5) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10BE-NEXT:    xsadddp f1, f1, v5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF5(VSR5)
+; PWR10BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v6 # Vec Defs: VSL5(VSR5) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR10BE-NEXT:    xsadddp f1, f1, v6 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF6(VSR6)
+; PWR10BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v7 # Vec Defs: VSL5(VSR5) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR10BE-NEXT:    xsadddp f1, f1, v7 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF7(VSR7)
+; PWR10BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v8 # Vec Defs: VSL5(VSR5) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR10BE-NEXT:    xsadddp f1, f1, v8 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF8(VSR8)
+; PWR10BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v9 # Vec Defs: VSL5(VSR5) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR10BE-NEXT:    xsadddp f1, f1, v9 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF9(VSR9)
+; PWR10BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v10 # Vec Defs: VSL5(VSR5) Vec Uses: V10(VSR42)V10(VSR42)
+; PWR10BE-NEXT:    xsadddp f1, f1, v10 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF10(VSR10)
+; PWR10BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v11 # Vec Defs: VSL5(VSR5) Vec Uses: V11(VSR43)V11(VSR43)
+; PWR10BE-NEXT:    xsadddp f1, f1, v11 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF11(VSR11)
+; PWR10BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v12 # Vec Defs: VSL5(VSR5) Vec Uses: V12(VSR44)V12(VSR44)
+; PWR10BE-NEXT:    xsadddp f1, f1, v12 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF12(VSR12)
+; PWR10BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, v13 # Vec Defs: VSL5(VSR5) Vec Uses: V13(VSR45)V13(VSR45)
+; PWR10BE-NEXT:    xsadddp f1, f1, v13 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF13(VSR13)
+; PWR10BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10BE-NEXT:    xsadddp f1, f1, f4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F4(VSR4)
+; PWR10BE-NEXT:    xxswapd vs4, vs4 # Vec Defs: VSL4(VSR4) Vec Uses: VSL4(VSR4)VSL4(VSR4)
+; PWR10BE-NEXT:    xsadddp f1, f1, f4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F4(VSR4)
+; PWR10BE-NEXT:    xsadddp f1, f1, f3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F3(VSR3)
+; PWR10BE-NEXT:    xxswapd vs3, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: VSL3(VSR3)VSL3(VSR3)
+; PWR10BE-NEXT:    xsadddp f1, f1, f3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F3(VSR3)
+; PWR10BE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR10BE-NEXT:    xxswapd vs2, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL2(VSR2)VSL2(VSR2)
+; PWR10BE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR10BE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR10BE-NEXT:    xxswapd vs0, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10BE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call double @llvm.vector.reduce.fadd.v32f64(double %b, <32 x double> %a)
   ret double %0
 }
 
 define dso_local double @v32f64_fast(<32 x double> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v32f64_fast:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    lxv vs0, 256(r1)
-; PWR9LE-NEXT:    lxv vs1, 224(r1)
-; PWR9LE-NEXT:    lxv vs2, 272(r1)
-; PWR9LE-NEXT:    lxv vs3, 240(r1)
-; PWR9LE-NEXT:    xvadddp vs4, v3, v11
-; PWR9LE-NEXT:    xvadddp vs5, v5, v13
-; PWR9LE-NEXT:    xvadddp vs6, v2, v10
-; PWR9LE-NEXT:    xvadddp vs7, v4, v12
-; PWR9LE-NEXT:    xvadddp vs3, v7, vs3
-; PWR9LE-NEXT:    xvadddp vs2, v9, vs2
-; PWR9LE-NEXT:    xvadddp vs1, v6, vs1
-; PWR9LE-NEXT:    xvadddp vs0, v8, vs0
-; PWR9LE-NEXT:    xvadddp vs0, vs7, vs0
-; PWR9LE-NEXT:    xvadddp vs1, vs6, vs1
-; PWR9LE-NEXT:    xvadddp vs2, vs5, vs2
-; PWR9LE-NEXT:    xvadddp vs3, vs4, vs3
-; PWR9LE-NEXT:    xvadddp vs2, vs3, vs2
-; PWR9LE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR9LE-NEXT:    xvadddp vs0, vs0, vs2
-; PWR9LE-NEXT:    xxswapd vs1, vs0
-; PWR9LE-NEXT:    xvadddp vs0, vs0, vs1
-; PWR9LE-NEXT:    xxswapd vs1, vs0
+; PWR9LE-NEXT:    lxv vs0, 256(r1) # Vec Defs: VSL0(VSR0)
+; PWR9LE-NEXT:    lxv vs1, 224(r1) # Vec Defs: VSL1(VSR1)
+; PWR9LE-NEXT:    lxv vs2, 272(r1) # Vec Defs: VSL2(VSR2)
+; PWR9LE-NEXT:    lxv vs3, 240(r1) # Vec Defs: VSL3(VSR3)
+; PWR9LE-NEXT:    xvadddp vs4, v3, v11 # Vec Defs: VSL4(VSR4) Vec Uses: V3(VSR35)V11(VSR43)
+; PWR9LE-NEXT:    xvadddp vs5, v5, v13 # Vec Defs: VSL5(VSR5) Vec Uses: V5(VSR37)V13(VSR45)
+; PWR9LE-NEXT:    xvadddp vs6, v2, v10 # Vec Defs: VSL6(VSR6) Vec Uses: V2(VSR34)V10(VSR42)
+; PWR9LE-NEXT:    xvadddp vs7, v4, v12 # Vec Defs: VSL7(VSR7) Vec Uses: V4(VSR36)V12(VSR44)
+; PWR9LE-NEXT:    xvadddp vs3, v7, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: V7(VSR39)VSL3(VSR3)
+; PWR9LE-NEXT:    xvadddp vs2, v9, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: V9(VSR41)VSL2(VSR2)
+; PWR9LE-NEXT:    xvadddp vs1, v6, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: V6(VSR38)VSL1(VSR1)
+; PWR9LE-NEXT:    xvadddp vs0, v8, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: V8(VSR40)VSL0(VSR0)
+; PWR9LE-NEXT:    xvadddp vs0, vs7, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL7(VSR7)VSL0(VSR0)
+; PWR9LE-NEXT:    xvadddp vs1, vs6, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL6(VSR6)VSL1(VSR1)
+; PWR9LE-NEXT:    xvadddp vs2, vs5, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL5(VSR5)VSL2(VSR2)
+; PWR9LE-NEXT:    xvadddp vs3, vs4, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: VSL4(VSR4)VSL3(VSR3)
+; PWR9LE-NEXT:    xvadddp vs2, vs3, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL3(VSR3)VSL2(VSR2)
+; PWR9LE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR9LE-NEXT:    xvadddp vs0, vs0, vs2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL2(VSR2)
+; PWR9LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9LE-NEXT:    xvadddp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; PWR9LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v32f64_fast:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    lxv vs0, 272(r1)
-; PWR9BE-NEXT:    lxv vs1, 240(r1)
-; PWR9BE-NEXT:    lxv vs2, 288(r1)
-; PWR9BE-NEXT:    lxv vs3, 256(r1)
-; PWR9BE-NEXT:    xvadddp vs4, v3, v11
-; PWR9BE-NEXT:    xvadddp vs5, v5, v13
-; PWR9BE-NEXT:    xvadddp vs6, v2, v10
-; PWR9BE-NEXT:    xvadddp vs7, v4, v12
-; PWR9BE-NEXT:    xvadddp vs3, v7, vs3
-; PWR9BE-NEXT:    xvadddp vs2, v9, vs2
-; PWR9BE-NEXT:    xvadddp vs1, v6, vs1
-; PWR9BE-NEXT:    xvadddp vs0, v8, vs0
-; PWR9BE-NEXT:    xvadddp vs0, vs7, vs0
-; PWR9BE-NEXT:    xvadddp vs1, vs6, vs1
-; PWR9BE-NEXT:    xvadddp vs2, vs5, vs2
-; PWR9BE-NEXT:    xvadddp vs3, vs4, vs3
-; PWR9BE-NEXT:    xvadddp vs2, vs3, vs2
-; PWR9BE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR9BE-NEXT:    xvadddp vs0, vs0, vs2
-; PWR9BE-NEXT:    xxswapd vs1, vs0
-; PWR9BE-NEXT:    xvadddp vs1, vs0, vs1
+; PWR9BE-NEXT:    lxv vs0, 272(r1) # Vec Defs: VSL0(VSR0)
+; PWR9BE-NEXT:    lxv vs1, 240(r1) # Vec Defs: VSL1(VSR1)
+; PWR9BE-NEXT:    lxv vs2, 288(r1) # Vec Defs: VSL2(VSR2)
+; PWR9BE-NEXT:    lxv vs3, 256(r1) # Vec Defs: VSL3(VSR3)
+; PWR9BE-NEXT:    xvadddp vs4, v3, v11 # Vec Defs: VSL4(VSR4) Vec Uses: V3(VSR35)V11(VSR43)
+; PWR9BE-NEXT:    xvadddp vs5, v5, v13 # Vec Defs: VSL5(VSR5) Vec Uses: V5(VSR37)V13(VSR45)
+; PWR9BE-NEXT:    xvadddp vs6, v2, v10 # Vec Defs: VSL6(VSR6) Vec Uses: V2(VSR34)V10(VSR42)
+; PWR9BE-NEXT:    xvadddp vs7, v4, v12 # Vec Defs: VSL7(VSR7) Vec Uses: V4(VSR36)V12(VSR44)
+; PWR9BE-NEXT:    xvadddp vs3, v7, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: V7(VSR39)VSL3(VSR3)
+; PWR9BE-NEXT:    xvadddp vs2, v9, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: V9(VSR41)VSL2(VSR2)
+; PWR9BE-NEXT:    xvadddp vs1, v6, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: V6(VSR38)VSL1(VSR1)
+; PWR9BE-NEXT:    xvadddp vs0, v8, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: V8(VSR40)VSL0(VSR0)
+; PWR9BE-NEXT:    xvadddp vs0, vs7, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL7(VSR7)VSL0(VSR0)
+; PWR9BE-NEXT:    xvadddp vs1, vs6, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL6(VSR6)VSL1(VSR1)
+; PWR9BE-NEXT:    xvadddp vs2, vs5, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL5(VSR5)VSL2(VSR2)
+; PWR9BE-NEXT:    xvadddp vs3, vs4, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: VSL4(VSR4)VSL3(VSR3)
+; PWR9BE-NEXT:    xvadddp vs2, vs3, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL3(VSR3)VSL2(VSR2)
+; PWR9BE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR9BE-NEXT:    xvadddp vs0, vs0, vs2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL2(VSR2)
+; PWR9BE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9BE-NEXT:    xvadddp vs1, vs0, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL1(VSR1)
 ; PWR9BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v32f64_fast:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    lxv vs0, 256(r1)
-; PWR10LE-NEXT:    lxv vs1, 224(r1)
-; PWR10LE-NEXT:    xvadddp vs4, v3, v11
-; PWR10LE-NEXT:    xvadddp vs5, v5, v13
-; PWR10LE-NEXT:    xvadddp vs6, v2, v10
-; PWR10LE-NEXT:    xvadddp vs7, v4, v12
-; PWR10LE-NEXT:    xvadddp vs1, v6, vs1
-; PWR10LE-NEXT:    lxv vs2, 272(r1)
-; PWR10LE-NEXT:    lxv vs3, 240(r1)
-; PWR10LE-NEXT:    xvadddp vs3, v7, vs3
-; PWR10LE-NEXT:    xvadddp vs2, v9, vs2
-; PWR10LE-NEXT:    xvadddp vs0, v8, vs0
-; PWR10LE-NEXT:    xvadddp vs0, vs7, vs0
-; PWR10LE-NEXT:    xvadddp vs1, vs6, vs1
-; PWR10LE-NEXT:    xvadddp vs2, vs5, vs2
-; PWR10LE-NEXT:    xvadddp vs3, vs4, vs3
-; PWR10LE-NEXT:    xvadddp vs2, vs3, vs2
-; PWR10LE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR10LE-NEXT:    xvadddp vs0, vs0, vs2
-; PWR10LE-NEXT:    xxswapd vs1, vs0
-; PWR10LE-NEXT:    xvadddp vs0, vs0, vs1
-; PWR10LE-NEXT:    xxswapd vs1, vs0
+; PWR10LE-NEXT:    lxv vs0, 256(r1) # Vec Defs: VSL0(VSR0)
+; PWR10LE-NEXT:    lxv vs1, 224(r1) # Vec Defs: VSL1(VSR1)
+; PWR10LE-NEXT:    xvadddp vs4, v3, v11 # Vec Defs: VSL4(VSR4) Vec Uses: V3(VSR35)V11(VSR43)
+; PWR10LE-NEXT:    xvadddp vs5, v5, v13 # Vec Defs: VSL5(VSR5) Vec Uses: V5(VSR37)V13(VSR45)
+; PWR10LE-NEXT:    xvadddp vs6, v2, v10 # Vec Defs: VSL6(VSR6) Vec Uses: V2(VSR34)V10(VSR42)
+; PWR10LE-NEXT:    xvadddp vs7, v4, v12 # Vec Defs: VSL7(VSR7) Vec Uses: V4(VSR36)V12(VSR44)
+; PWR10LE-NEXT:    xvadddp vs1, v6, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: V6(VSR38)VSL1(VSR1)
+; PWR10LE-NEXT:    lxv vs2, 272(r1) # Vec Defs: VSL2(VSR2)
+; PWR10LE-NEXT:    lxv vs3, 240(r1) # Vec Defs: VSL3(VSR3)
+; PWR10LE-NEXT:    xvadddp vs3, v7, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: V7(VSR39)VSL3(VSR3)
+; PWR10LE-NEXT:    xvadddp vs2, v9, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: V9(VSR41)VSL2(VSR2)
+; PWR10LE-NEXT:    xvadddp vs0, v8, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: V8(VSR40)VSL0(VSR0)
+; PWR10LE-NEXT:    xvadddp vs0, vs7, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL7(VSR7)VSL0(VSR0)
+; PWR10LE-NEXT:    xvadddp vs1, vs6, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL6(VSR6)VSL1(VSR1)
+; PWR10LE-NEXT:    xvadddp vs2, vs5, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL5(VSR5)VSL2(VSR2)
+; PWR10LE-NEXT:    xvadddp vs3, vs4, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: VSL4(VSR4)VSL3(VSR3)
+; PWR10LE-NEXT:    xvadddp vs2, vs3, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL3(VSR3)VSL2(VSR2)
+; PWR10LE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR10LE-NEXT:    xvadddp vs0, vs0, vs2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL2(VSR2)
+; PWR10LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10LE-NEXT:    xvadddp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; PWR10LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v32f64_fast:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    lxv vs0, 272(r1)
-; PWR10BE-NEXT:    lxv vs1, 240(r1)
-; PWR10BE-NEXT:    xvadddp vs4, v3, v11
-; PWR10BE-NEXT:    xvadddp vs5, v5, v13
-; PWR10BE-NEXT:    xvadddp vs6, v2, v10
-; PWR10BE-NEXT:    xvadddp vs7, v4, v12
-; PWR10BE-NEXT:    xvadddp vs1, v6, vs1
-; PWR10BE-NEXT:    lxv vs2, 288(r1)
-; PWR10BE-NEXT:    lxv vs3, 256(r1)
-; PWR10BE-NEXT:    xvadddp vs3, v7, vs3
-; PWR10BE-NEXT:    xvadddp vs2, v9, vs2
-; PWR10BE-NEXT:    xvadddp vs0, v8, vs0
-; PWR10BE-NEXT:    xvadddp vs0, vs7, vs0
-; PWR10BE-NEXT:    xvadddp vs1, vs6, vs1
-; PWR10BE-NEXT:    xvadddp vs2, vs5, vs2
-; PWR10BE-NEXT:    xvadddp vs3, vs4, vs3
-; PWR10BE-NEXT:    xvadddp vs2, vs3, vs2
-; PWR10BE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR10BE-NEXT:    xvadddp vs0, vs0, vs2
-; PWR10BE-NEXT:    xxswapd vs1, vs0
-; PWR10BE-NEXT:    xvadddp vs1, vs0, vs1
+; PWR10BE-NEXT:    lxv vs0, 272(r1) # Vec Defs: VSL0(VSR0)
+; PWR10BE-NEXT:    lxv vs1, 240(r1) # Vec Defs: VSL1(VSR1)
+; PWR10BE-NEXT:    xvadddp vs4, v3, v11 # Vec Defs: VSL4(VSR4) Vec Uses: V3(VSR35)V11(VSR43)
+; PWR10BE-NEXT:    xvadddp vs5, v5, v13 # Vec Defs: VSL5(VSR5) Vec Uses: V5(VSR37)V13(VSR45)
+; PWR10BE-NEXT:    xvadddp vs6, v2, v10 # Vec Defs: VSL6(VSR6) Vec Uses: V2(VSR34)V10(VSR42)
+; PWR10BE-NEXT:    xvadddp vs7, v4, v12 # Vec Defs: VSL7(VSR7) Vec Uses: V4(VSR36)V12(VSR44)
+; PWR10BE-NEXT:    xvadddp vs1, v6, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: V6(VSR38)VSL1(VSR1)
+; PWR10BE-NEXT:    lxv vs2, 288(r1) # Vec Defs: VSL2(VSR2)
+; PWR10BE-NEXT:    lxv vs3, 256(r1) # Vec Defs: VSL3(VSR3)
+; PWR10BE-NEXT:    xvadddp vs3, v7, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: V7(VSR39)VSL3(VSR3)
+; PWR10BE-NEXT:    xvadddp vs2, v9, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: V9(VSR41)VSL2(VSR2)
+; PWR10BE-NEXT:    xvadddp vs0, v8, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: V8(VSR40)VSL0(VSR0)
+; PWR10BE-NEXT:    xvadddp vs0, vs7, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL7(VSR7)VSL0(VSR0)
+; PWR10BE-NEXT:    xvadddp vs1, vs6, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL6(VSR6)VSL1(VSR1)
+; PWR10BE-NEXT:    xvadddp vs2, vs5, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL5(VSR5)VSL2(VSR2)
+; PWR10BE-NEXT:    xvadddp vs3, vs4, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: VSL4(VSR4)VSL3(VSR3)
+; PWR10BE-NEXT:    xvadddp vs2, vs3, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL3(VSR3)VSL2(VSR2)
+; PWR10BE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR10BE-NEXT:    xvadddp vs0, vs0, vs2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL2(VSR2)
+; PWR10BE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10BE-NEXT:    xvadddp vs1, vs0, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL1(VSR1)
 ; PWR10BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call fast double @llvm.vector.reduce.fadd.v32f64(double -0.000000e+00, <32 x double> %a)
   ret double %0
 }
 
 define dso_local double @v64f64(<64 x double> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v64f64:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxswapd v18, v2
-; PWR9LE-NEXT:    lxv v17, 224(r1)
-; PWR9LE-NEXT:    lxv v16, 240(r1)
-; PWR9LE-NEXT:    lxv v15, 256(r1)
-; PWR9LE-NEXT:    lxv v14, 272(r1)
-; PWR9LE-NEXT:    xsadddp v2, v18, v2
-; PWR9LE-NEXT:    xxswapd v18, v3
-; PWR9LE-NEXT:    lxv v1, 288(r1)
-; PWR9LE-NEXT:    lxv v0, 304(r1)
-; PWR9LE-NEXT:    lxv vs13, 320(r1)
-; PWR9LE-NEXT:    lxv vs12, 336(r1)
-; PWR9LE-NEXT:    lxv vs11, 352(r1)
-; PWR9LE-NEXT:    lxv vs10, 368(r1)
-; PWR9LE-NEXT:    lxv vs9, 384(r1)
-; PWR9LE-NEXT:    lxv vs8, 400(r1)
-; PWR9LE-NEXT:    lxv vs7, 416(r1)
-; PWR9LE-NEXT:    lxv vs6, 432(r1)
-; PWR9LE-NEXT:    lxv vs5, 448(r1)
-; PWR9LE-NEXT:    lxv vs4, 464(r1)
-; PWR9LE-NEXT:    xsadddp v2, v2, v18
-; PWR9LE-NEXT:    lxv vs3, 480(r1)
-; PWR9LE-NEXT:    lxv vs2, 496(r1)
-; PWR9LE-NEXT:    lxv vs1, 512(r1)
-; PWR9LE-NEXT:    lxv vs0, 528(r1)
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, v4
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, v5
-; PWR9LE-NEXT:    xsadddp v2, v2, v4
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, v6
-; PWR9LE-NEXT:    xsadddp v2, v2, v5
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, v7
-; PWR9LE-NEXT:    xsadddp v2, v2, v6
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, v8
-; PWR9LE-NEXT:    xsadddp v2, v2, v7
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, v9
-; PWR9LE-NEXT:    xsadddp v2, v2, v8
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, v10
-; PWR9LE-NEXT:    xsadddp v2, v2, v9
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, v11
-; PWR9LE-NEXT:    xsadddp v2, v2, v10
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, v12
-; PWR9LE-NEXT:    xsadddp v2, v2, v11
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, v13
-; PWR9LE-NEXT:    xsadddp v2, v2, v12
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, v17
-; PWR9LE-NEXT:    xsadddp v2, v2, v13
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, v16
-; PWR9LE-NEXT:    xsadddp v2, v2, v17
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, v15
-; PWR9LE-NEXT:    xsadddp v2, v2, v16
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, v14
-; PWR9LE-NEXT:    xsadddp v2, v2, v15
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, v1
-; PWR9LE-NEXT:    xsadddp v2, v2, v14
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, v0
-; PWR9LE-NEXT:    xsadddp v2, v2, v1
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xxswapd v3, vs13
-; PWR9LE-NEXT:    xsadddp v2, v2, v0
-; PWR9LE-NEXT:    xsadddp v2, v2, v3
-; PWR9LE-NEXT:    xsadddp f13, v2, f13
-; PWR9LE-NEXT:    xxswapd v2, vs12
-; PWR9LE-NEXT:    xsadddp f13, f13, v2
-; PWR9LE-NEXT:    xsadddp f12, f13, f12
-; PWR9LE-NEXT:    xxswapd vs13, vs11
-; PWR9LE-NEXT:    xsadddp f12, f12, f13
-; PWR9LE-NEXT:    xsadddp f11, f12, f11
-; PWR9LE-NEXT:    xxswapd vs12, vs10
-; PWR9LE-NEXT:    xsadddp f11, f11, f12
-; PWR9LE-NEXT:    xsadddp f10, f11, f10
-; PWR9LE-NEXT:    xxswapd vs11, vs9
-; PWR9LE-NEXT:    xsadddp f10, f10, f11
-; PWR9LE-NEXT:    xsadddp f9, f10, f9
-; PWR9LE-NEXT:    xxswapd vs10, vs8
-; PWR9LE-NEXT:    xsadddp f9, f9, f10
-; PWR9LE-NEXT:    xsadddp f8, f9, f8
-; PWR9LE-NEXT:    xxswapd vs9, vs7
-; PWR9LE-NEXT:    xsadddp f8, f8, f9
-; PWR9LE-NEXT:    xsadddp f7, f8, f7
-; PWR9LE-NEXT:    xxswapd vs8, vs6
-; PWR9LE-NEXT:    xsadddp f7, f7, f8
-; PWR9LE-NEXT:    xsadddp f6, f7, f6
-; PWR9LE-NEXT:    xxswapd vs7, vs5
-; PWR9LE-NEXT:    xsadddp f6, f6, f7
-; PWR9LE-NEXT:    xsadddp f5, f6, f5
-; PWR9LE-NEXT:    xxswapd vs6, vs4
-; PWR9LE-NEXT:    xsadddp f5, f5, f6
-; PWR9LE-NEXT:    xsadddp f4, f5, f4
-; PWR9LE-NEXT:    xxswapd vs5, vs3
-; PWR9LE-NEXT:    xsadddp f4, f4, f5
-; PWR9LE-NEXT:    xsadddp f3, f4, f3
-; PWR9LE-NEXT:    xxswapd vs4, vs2
-; PWR9LE-NEXT:    xsadddp f3, f3, f4
-; PWR9LE-NEXT:    xsadddp f2, f3, f2
-; PWR9LE-NEXT:    xxswapd vs3, vs1
-; PWR9LE-NEXT:    xsadddp f2, f2, f3
-; PWR9LE-NEXT:    xsadddp f1, f2, f1
-; PWR9LE-NEXT:    xxswapd vs2, vs0
-; PWR9LE-NEXT:    xsadddp f1, f1, f2
-; PWR9LE-NEXT:    xsadddp f1, f1, f0
+; PWR9LE-NEXT:    xxswapd v18, v2 # Vec Defs: V18(VSR50) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    lxv v17, 224(r1) # Vec Defs: V17(VSR49)
+; PWR9LE-NEXT:    lxv v16, 240(r1) # Vec Defs: V16(VSR48)
+; PWR9LE-NEXT:    lxv v15, 256(r1) # Vec Defs: V15(VSR47)
+; PWR9LE-NEXT:    lxv v14, 272(r1) # Vec Defs: V14(VSR46)
+; PWR9LE-NEXT:    xsadddp v2, v18, v2 # Vec Defs: VF2(VSR2) Vec Uses: VF18(VSR18)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v18, v3 # Vec Defs: V18(VSR50) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    lxv v1, 288(r1) # Vec Defs: V1(VSR33)
+; PWR9LE-NEXT:    lxv v0, 304(r1) # Vec Defs: V0(VSR32)
+; PWR9LE-NEXT:    lxv vs13, 320(r1) # Vec Defs: VSL13(VSR13)
+; PWR9LE-NEXT:    lxv vs12, 336(r1) # Vec Defs: VSL12(VSR12)
+; PWR9LE-NEXT:    lxv vs11, 352(r1) # Vec Defs: VSL11(VSR11)
+; PWR9LE-NEXT:    lxv vs10, 368(r1) # Vec Defs: VSL10(VSR10)
+; PWR9LE-NEXT:    lxv vs9, 384(r1) # Vec Defs: VSL9(VSR9)
+; PWR9LE-NEXT:    lxv vs8, 400(r1) # Vec Defs: VSL8(VSR8)
+; PWR9LE-NEXT:    lxv vs7, 416(r1) # Vec Defs: VSL7(VSR7)
+; PWR9LE-NEXT:    lxv vs6, 432(r1) # Vec Defs: VSL6(VSR6)
+; PWR9LE-NEXT:    lxv vs5, 448(r1) # Vec Defs: VSL5(VSR5)
+; PWR9LE-NEXT:    lxv vs4, 464(r1) # Vec Defs: VSL4(VSR4)
+; PWR9LE-NEXT:    xsadddp v2, v2, v18 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF18(VSR18)
+; PWR9LE-NEXT:    lxv vs3, 480(r1) # Vec Defs: VSL3(VSR3)
+; PWR9LE-NEXT:    lxv vs2, 496(r1) # Vec Defs: VSL2(VSR2)
+; PWR9LE-NEXT:    lxv vs1, 512(r1) # Vec Defs: VSL1(VSR1)
+; PWR9LE-NEXT:    lxv vs0, 528(r1) # Vec Defs: VSL0(VSR0)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, v4 # Vec Defs: V3(VSR35) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, v5 # Vec Defs: V3(VSR35) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9LE-NEXT:    xsadddp v2, v2, v4 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF4(VSR4)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, v6 # Vec Defs: V3(VSR35) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR9LE-NEXT:    xsadddp v2, v2, v5 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF5(VSR5)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, v7 # Vec Defs: V3(VSR35) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR9LE-NEXT:    xsadddp v2, v2, v6 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF6(VSR6)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, v8 # Vec Defs: V3(VSR35) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR9LE-NEXT:    xsadddp v2, v2, v7 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF7(VSR7)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, v9 # Vec Defs: V3(VSR35) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR9LE-NEXT:    xsadddp v2, v2, v8 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF8(VSR8)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, v10 # Vec Defs: V3(VSR35) Vec Uses: V10(VSR42)V10(VSR42)
+; PWR9LE-NEXT:    xsadddp v2, v2, v9 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF9(VSR9)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, v11 # Vec Defs: V3(VSR35) Vec Uses: V11(VSR43)V11(VSR43)
+; PWR9LE-NEXT:    xsadddp v2, v2, v10 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF10(VSR10)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, v12 # Vec Defs: V3(VSR35) Vec Uses: V12(VSR44)V12(VSR44)
+; PWR9LE-NEXT:    xsadddp v2, v2, v11 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF11(VSR11)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, v13 # Vec Defs: V3(VSR35) Vec Uses: V13(VSR45)V13(VSR45)
+; PWR9LE-NEXT:    xsadddp v2, v2, v12 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF12(VSR12)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, v17 # Vec Defs: V3(VSR35) Vec Uses: V17(VSR49)V17(VSR49)
+; PWR9LE-NEXT:    xsadddp v2, v2, v13 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF13(VSR13)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, v16 # Vec Defs: V3(VSR35) Vec Uses: V16(VSR48)V16(VSR48)
+; PWR9LE-NEXT:    xsadddp v2, v2, v17 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF17(VSR17)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, v15 # Vec Defs: V3(VSR35) Vec Uses: V15(VSR47)V15(VSR47)
+; PWR9LE-NEXT:    xsadddp v2, v2, v16 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF16(VSR16)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, v14 # Vec Defs: V3(VSR35) Vec Uses: V14(VSR46)V14(VSR46)
+; PWR9LE-NEXT:    xsadddp v2, v2, v15 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF15(VSR15)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, v1 # Vec Defs: V3(VSR35) Vec Uses: V1(VSR33)V1(VSR33)
+; PWR9LE-NEXT:    xsadddp v2, v2, v14 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF14(VSR14)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, v0 # Vec Defs: V3(VSR35) Vec Uses: V0(VSR32)V0(VSR32)
+; PWR9LE-NEXT:    xsadddp v2, v2, v1 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF1(VSR1)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xxswapd v3, vs13 # Vec Defs: V3(VSR35) Vec Uses: VSL13(VSR13)VSL13(VSR13)
+; PWR9LE-NEXT:    xsadddp v2, v2, v0 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF0(VSR0)
+; PWR9LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9LE-NEXT:    xsadddp f13, v2, f13 # Vec Defs: F13(VSR13) Vec Uses: VF2(VSR2)F13(VSR13)
+; PWR9LE-NEXT:    xxswapd v2, vs12 # Vec Defs: V2(VSR34) Vec Uses: VSL12(VSR12)VSL12(VSR12)
+; PWR9LE-NEXT:    xsadddp f13, f13, v2 # Vec Defs: F13(VSR13) Vec Uses: F13(VSR13)VF2(VSR2)
+; PWR9LE-NEXT:    xsadddp f12, f13, f12 # Vec Defs: F12(VSR12) Vec Uses: F13(VSR13)F12(VSR12)
+; PWR9LE-NEXT:    xxswapd vs13, vs11 # Vec Defs: VSL13(VSR13) Vec Uses: VSL11(VSR11)VSL11(VSR11)
+; PWR9LE-NEXT:    xsadddp f12, f12, f13 # Vec Defs: F12(VSR12) Vec Uses: F12(VSR12)F13(VSR13)
+; PWR9LE-NEXT:    xsadddp f11, f12, f11 # Vec Defs: F11(VSR11) Vec Uses: F12(VSR12)F11(VSR11)
+; PWR9LE-NEXT:    xxswapd vs12, vs10 # Vec Defs: VSL12(VSR12) Vec Uses: VSL10(VSR10)VSL10(VSR10)
+; PWR9LE-NEXT:    xsadddp f11, f11, f12 # Vec Defs: F11(VSR11) Vec Uses: F11(VSR11)F12(VSR12)
+; PWR9LE-NEXT:    xsadddp f10, f11, f10 # Vec Defs: F10(VSR10) Vec Uses: F11(VSR11)F10(VSR10)
+; PWR9LE-NEXT:    xxswapd vs11, vs9 # Vec Defs: VSL11(VSR11) Vec Uses: VSL9(VSR9)VSL9(VSR9)
+; PWR9LE-NEXT:    xsadddp f10, f10, f11 # Vec Defs: F10(VSR10) Vec Uses: F10(VSR10)F11(VSR11)
+; PWR9LE-NEXT:    xsadddp f9, f10, f9 # Vec Defs: F9(VSR9) Vec Uses: F10(VSR10)F9(VSR9)
+; PWR9LE-NEXT:    xxswapd vs10, vs8 # Vec Defs: VSL10(VSR10) Vec Uses: VSL8(VSR8)VSL8(VSR8)
+; PWR9LE-NEXT:    xsadddp f9, f9, f10 # Vec Defs: F9(VSR9) Vec Uses: F9(VSR9)F10(VSR10)
+; PWR9LE-NEXT:    xsadddp f8, f9, f8 # Vec Defs: F8(VSR8) Vec Uses: F9(VSR9)F8(VSR8)
+; PWR9LE-NEXT:    xxswapd vs9, vs7 # Vec Defs: VSL9(VSR9) Vec Uses: VSL7(VSR7)VSL7(VSR7)
+; PWR9LE-NEXT:    xsadddp f8, f8, f9 # Vec Defs: F8(VSR8) Vec Uses: F8(VSR8)F9(VSR9)
+; PWR9LE-NEXT:    xsadddp f7, f8, f7 # Vec Defs: F7(VSR7) Vec Uses: F8(VSR8)F7(VSR7)
+; PWR9LE-NEXT:    xxswapd vs8, vs6 # Vec Defs: VSL8(VSR8) Vec Uses: VSL6(VSR6)VSL6(VSR6)
+; PWR9LE-NEXT:    xsadddp f7, f7, f8 # Vec Defs: F7(VSR7) Vec Uses: F7(VSR7)F8(VSR8)
+; PWR9LE-NEXT:    xsadddp f6, f7, f6 # Vec Defs: F6(VSR6) Vec Uses: F7(VSR7)F6(VSR6)
+; PWR9LE-NEXT:    xxswapd vs7, vs5 # Vec Defs: VSL7(VSR7) Vec Uses: VSL5(VSR5)VSL5(VSR5)
+; PWR9LE-NEXT:    xsadddp f6, f6, f7 # Vec Defs: F6(VSR6) Vec Uses: F6(VSR6)F7(VSR7)
+; PWR9LE-NEXT:    xsadddp f5, f6, f5 # Vec Defs: F5(VSR5) Vec Uses: F6(VSR6)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs6, vs4 # Vec Defs: VSL6(VSR6) Vec Uses: VSL4(VSR4)VSL4(VSR4)
+; PWR9LE-NEXT:    xsadddp f5, f5, f6 # Vec Defs: F5(VSR5) Vec Uses: F5(VSR5)F6(VSR6)
+; PWR9LE-NEXT:    xsadddp f4, f5, f4 # Vec Defs: F4(VSR4) Vec Uses: F5(VSR5)F4(VSR4)
+; PWR9LE-NEXT:    xxswapd vs5, vs3 # Vec Defs: VSL5(VSR5) Vec Uses: VSL3(VSR3)VSL3(VSR3)
+; PWR9LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR9LE-NEXT:    xsadddp f3, f4, f3 # Vec Defs: F3(VSR3) Vec Uses: F4(VSR4)F3(VSR3)
+; PWR9LE-NEXT:    xxswapd vs4, vs2 # Vec Defs: VSL4(VSR4) Vec Uses: VSL2(VSR2)VSL2(VSR2)
+; PWR9LE-NEXT:    xsadddp f3, f3, f4 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)F4(VSR4)
+; PWR9LE-NEXT:    xsadddp f2, f3, f2 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)F2(VSR2)
+; PWR9LE-NEXT:    xxswapd vs3, vs1 # Vec Defs: VSL3(VSR3) Vec Uses: VSL1(VSR1)VSL1(VSR1)
+; PWR9LE-NEXT:    xsadddp f2, f2, f3 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)F3(VSR3)
+; PWR9LE-NEXT:    xsadddp f1, f2, f1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs2, vs0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9LE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR9LE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v64f64:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xxswapd v18, v2
-; PWR9BE-NEXT:    lxv v17, 240(r1)
-; PWR9BE-NEXT:    lxv v16, 256(r1)
-; PWR9BE-NEXT:    lxv v15, 272(r1)
-; PWR9BE-NEXT:    lxv v14, 288(r1)
-; PWR9BE-NEXT:    xsadddp v2, v2, v18
-; PWR9BE-NEXT:    lxv v1, 304(r1)
-; PWR9BE-NEXT:    lxv v0, 320(r1)
-; PWR9BE-NEXT:    lxv vs13, 336(r1)
-; PWR9BE-NEXT:    lxv vs12, 352(r1)
-; PWR9BE-NEXT:    lxv vs11, 368(r1)
-; PWR9BE-NEXT:    lxv vs10, 384(r1)
-; PWR9BE-NEXT:    lxv vs9, 400(r1)
-; PWR9BE-NEXT:    lxv vs8, 416(r1)
-; PWR9BE-NEXT:    lxv vs7, 432(r1)
-; PWR9BE-NEXT:    lxv vs6, 448(r1)
-; PWR9BE-NEXT:    lxv vs5, 464(r1)
-; PWR9BE-NEXT:    lxv vs4, 480(r1)
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v3
-; PWR9BE-NEXT:    lxv vs3, 496(r1)
-; PWR9BE-NEXT:    lxv vs2, 512(r1)
-; PWR9BE-NEXT:    lxv vs1, 528(r1)
-; PWR9BE-NEXT:    lxv vs0, 544(r1)
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v4
-; PWR9BE-NEXT:    xsadddp v2, v2, v4
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v5
-; PWR9BE-NEXT:    xsadddp v2, v2, v5
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v6
-; PWR9BE-NEXT:    xsadddp v2, v2, v6
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v7
-; PWR9BE-NEXT:    xsadddp v2, v2, v7
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v8
-; PWR9BE-NEXT:    xsadddp v2, v2, v8
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v9
-; PWR9BE-NEXT:    xsadddp v2, v2, v9
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v10
-; PWR9BE-NEXT:    xsadddp v2, v2, v10
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v11
-; PWR9BE-NEXT:    xsadddp v2, v2, v11
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v12
-; PWR9BE-NEXT:    xsadddp v2, v2, v12
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v13
-; PWR9BE-NEXT:    xsadddp v2, v2, v13
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v17
-; PWR9BE-NEXT:    xsadddp v2, v2, v17
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v16
-; PWR9BE-NEXT:    xsadddp v2, v2, v16
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v15
-; PWR9BE-NEXT:    xsadddp v2, v2, v15
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v14
-; PWR9BE-NEXT:    xsadddp v2, v2, v14
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v1
-; PWR9BE-NEXT:    xsadddp v2, v2, v1
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xxswapd v3, v0
-; PWR9BE-NEXT:    xsadddp v2, v2, v0
-; PWR9BE-NEXT:    xsadddp v2, v2, v3
-; PWR9BE-NEXT:    xsadddp v2, v2, f13
-; PWR9BE-NEXT:    xxswapd vs13, vs13
-; PWR9BE-NEXT:    xsadddp f13, v2, f13
-; PWR9BE-NEXT:    xsadddp f13, f13, f12
-; PWR9BE-NEXT:    xxswapd vs12, vs12
-; PWR9BE-NEXT:    xsadddp f12, f13, f12
-; PWR9BE-NEXT:    xsadddp f12, f12, f11
-; PWR9BE-NEXT:    xxswapd vs11, vs11
-; PWR9BE-NEXT:    xsadddp f11, f12, f11
-; PWR9BE-NEXT:    xsadddp f11, f11, f10
-; PWR9BE-NEXT:    xxswapd vs10, vs10
-; PWR9BE-NEXT:    xsadddp f10, f11, f10
-; PWR9BE-NEXT:    xsadddp f10, f10, f9
-; PWR9BE-NEXT:    xxswapd vs9, vs9
-; PWR9BE-NEXT:    xsadddp f9, f10, f9
-; PWR9BE-NEXT:    xsadddp f9, f9, f8
-; PWR9BE-NEXT:    xxswapd vs8, vs8
-; PWR9BE-NEXT:    xsadddp f8, f9, f8
-; PWR9BE-NEXT:    xsadddp f8, f8, f7
-; PWR9BE-NEXT:    xxswapd vs7, vs7
-; PWR9BE-NEXT:    xsadddp f7, f8, f7
-; PWR9BE-NEXT:    xsadddp f7, f7, f6
-; PWR9BE-NEXT:    xxswapd vs6, vs6
-; PWR9BE-NEXT:    xsadddp f6, f7, f6
-; PWR9BE-NEXT:    xsadddp f6, f6, f5
-; PWR9BE-NEXT:    xxswapd vs5, vs5
-; PWR9BE-NEXT:    xsadddp f5, f6, f5
-; PWR9BE-NEXT:    xsadddp f5, f5, f4
-; PWR9BE-NEXT:    xxswapd vs4, vs4
-; PWR9BE-NEXT:    xsadddp f4, f5, f4
-; PWR9BE-NEXT:    xsadddp f4, f4, f3
-; PWR9BE-NEXT:    xxswapd vs3, vs3
-; PWR9BE-NEXT:    xsadddp f3, f4, f3
-; PWR9BE-NEXT:    xsadddp f3, f3, f2
-; PWR9BE-NEXT:    xxswapd vs2, vs2
-; PWR9BE-NEXT:    xsadddp f2, f3, f2
-; PWR9BE-NEXT:    xsadddp f2, f2, f1
-; PWR9BE-NEXT:    xxswapd vs1, vs1
-; PWR9BE-NEXT:    xsadddp f1, f2, f1
-; PWR9BE-NEXT:    xsadddp f1, f1, f0
-; PWR9BE-NEXT:    xxswapd vs0, vs0
-; PWR9BE-NEXT:    xsadddp f1, f1, f0
+; PWR9BE-NEXT:    xxswapd v18, v2 # Vec Defs: V18(VSR50) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    lxv v17, 240(r1) # Vec Defs: V17(VSR49)
+; PWR9BE-NEXT:    lxv v16, 256(r1) # Vec Defs: V16(VSR48)
+; PWR9BE-NEXT:    lxv v15, 272(r1) # Vec Defs: V15(VSR47)
+; PWR9BE-NEXT:    lxv v14, 288(r1) # Vec Defs: V14(VSR46)
+; PWR9BE-NEXT:    xsadddp v2, v2, v18 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF18(VSR18)
+; PWR9BE-NEXT:    lxv v1, 304(r1) # Vec Defs: V1(VSR33)
+; PWR9BE-NEXT:    lxv v0, 320(r1) # Vec Defs: V0(VSR32)
+; PWR9BE-NEXT:    lxv vs13, 336(r1) # Vec Defs: VSL13(VSR13)
+; PWR9BE-NEXT:    lxv vs12, 352(r1) # Vec Defs: VSL12(VSR12)
+; PWR9BE-NEXT:    lxv vs11, 368(r1) # Vec Defs: VSL11(VSR11)
+; PWR9BE-NEXT:    lxv vs10, 384(r1) # Vec Defs: VSL10(VSR10)
+; PWR9BE-NEXT:    lxv vs9, 400(r1) # Vec Defs: VSL9(VSR9)
+; PWR9BE-NEXT:    lxv vs8, 416(r1) # Vec Defs: VSL8(VSR8)
+; PWR9BE-NEXT:    lxv vs7, 432(r1) # Vec Defs: VSL7(VSR7)
+; PWR9BE-NEXT:    lxv vs6, 448(r1) # Vec Defs: VSL6(VSR6)
+; PWR9BE-NEXT:    lxv vs5, 464(r1) # Vec Defs: VSL5(VSR5)
+; PWR9BE-NEXT:    lxv vs4, 480(r1) # Vec Defs: VSL4(VSR4)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v3 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    lxv vs3, 496(r1) # Vec Defs: VSL3(VSR3)
+; PWR9BE-NEXT:    lxv vs2, 512(r1) # Vec Defs: VSL2(VSR2)
+; PWR9BE-NEXT:    lxv vs1, 528(r1) # Vec Defs: VSL1(VSR1)
+; PWR9BE-NEXT:    lxv vs0, 544(r1) # Vec Defs: VSL0(VSR0)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v4 # Vec Defs: V3(VSR35) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9BE-NEXT:    xsadddp v2, v2, v4 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF4(VSR4)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v5 # Vec Defs: V3(VSR35) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9BE-NEXT:    xsadddp v2, v2, v5 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF5(VSR5)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v6 # Vec Defs: V3(VSR35) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR9BE-NEXT:    xsadddp v2, v2, v6 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF6(VSR6)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v7 # Vec Defs: V3(VSR35) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR9BE-NEXT:    xsadddp v2, v2, v7 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF7(VSR7)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v8 # Vec Defs: V3(VSR35) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR9BE-NEXT:    xsadddp v2, v2, v8 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF8(VSR8)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v9 # Vec Defs: V3(VSR35) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR9BE-NEXT:    xsadddp v2, v2, v9 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF9(VSR9)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v10 # Vec Defs: V3(VSR35) Vec Uses: V10(VSR42)V10(VSR42)
+; PWR9BE-NEXT:    xsadddp v2, v2, v10 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF10(VSR10)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v11 # Vec Defs: V3(VSR35) Vec Uses: V11(VSR43)V11(VSR43)
+; PWR9BE-NEXT:    xsadddp v2, v2, v11 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF11(VSR11)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v12 # Vec Defs: V3(VSR35) Vec Uses: V12(VSR44)V12(VSR44)
+; PWR9BE-NEXT:    xsadddp v2, v2, v12 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF12(VSR12)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v13 # Vec Defs: V3(VSR35) Vec Uses: V13(VSR45)V13(VSR45)
+; PWR9BE-NEXT:    xsadddp v2, v2, v13 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF13(VSR13)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v17 # Vec Defs: V3(VSR35) Vec Uses: V17(VSR49)V17(VSR49)
+; PWR9BE-NEXT:    xsadddp v2, v2, v17 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF17(VSR17)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v16 # Vec Defs: V3(VSR35) Vec Uses: V16(VSR48)V16(VSR48)
+; PWR9BE-NEXT:    xsadddp v2, v2, v16 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF16(VSR16)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v15 # Vec Defs: V3(VSR35) Vec Uses: V15(VSR47)V15(VSR47)
+; PWR9BE-NEXT:    xsadddp v2, v2, v15 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF15(VSR15)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v14 # Vec Defs: V3(VSR35) Vec Uses: V14(VSR46)V14(VSR46)
+; PWR9BE-NEXT:    xsadddp v2, v2, v14 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF14(VSR14)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v1 # Vec Defs: V3(VSR35) Vec Uses: V1(VSR33)V1(VSR33)
+; PWR9BE-NEXT:    xsadddp v2, v2, v1 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF1(VSR1)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xxswapd v3, v0 # Vec Defs: V3(VSR35) Vec Uses: V0(VSR32)V0(VSR32)
+; PWR9BE-NEXT:    xsadddp v2, v2, v0 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF0(VSR0)
+; PWR9BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR9BE-NEXT:    xsadddp v2, v2, f13 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)F13(VSR13)
+; PWR9BE-NEXT:    xxswapd vs13, vs13 # Vec Defs: VSL13(VSR13) Vec Uses: VSL13(VSR13)VSL13(VSR13)
+; PWR9BE-NEXT:    xsadddp f13, v2, f13 # Vec Defs: F13(VSR13) Vec Uses: VF2(VSR2)F13(VSR13)
+; PWR9BE-NEXT:    xsadddp f13, f13, f12 # Vec Defs: F13(VSR13) Vec Uses: F13(VSR13)F12(VSR12)
+; PWR9BE-NEXT:    xxswapd vs12, vs12 # Vec Defs: VSL12(VSR12) Vec Uses: VSL12(VSR12)VSL12(VSR12)
+; PWR9BE-NEXT:    xsadddp f12, f13, f12 # Vec Defs: F12(VSR12) Vec Uses: F13(VSR13)F12(VSR12)
+; PWR9BE-NEXT:    xsadddp f12, f12, f11 # Vec Defs: F12(VSR12) Vec Uses: F12(VSR12)F11(VSR11)
+; PWR9BE-NEXT:    xxswapd vs11, vs11 # Vec Defs: VSL11(VSR11) Vec Uses: VSL11(VSR11)VSL11(VSR11)
+; PWR9BE-NEXT:    xsadddp f11, f12, f11 # Vec Defs: F11(VSR11) Vec Uses: F12(VSR12)F11(VSR11)
+; PWR9BE-NEXT:    xsadddp f11, f11, f10 # Vec Defs: F11(VSR11) Vec Uses: F11(VSR11)F10(VSR10)
+; PWR9BE-NEXT:    xxswapd vs10, vs10 # Vec Defs: VSL10(VSR10) Vec Uses: VSL10(VSR10)VSL10(VSR10)
+; PWR9BE-NEXT:    xsadddp f10, f11, f10 # Vec Defs: F10(VSR10) Vec Uses: F11(VSR11)F10(VSR10)
+; PWR9BE-NEXT:    xsadddp f10, f10, f9 # Vec Defs: F10(VSR10) Vec Uses: F10(VSR10)F9(VSR9)
+; PWR9BE-NEXT:    xxswapd vs9, vs9 # Vec Defs: VSL9(VSR9) Vec Uses: VSL9(VSR9)VSL9(VSR9)
+; PWR9BE-NEXT:    xsadddp f9, f10, f9 # Vec Defs: F9(VSR9) Vec Uses: F10(VSR10)F9(VSR9)
+; PWR9BE-NEXT:    xsadddp f9, f9, f8 # Vec Defs: F9(VSR9) Vec Uses: F9(VSR9)F8(VSR8)
+; PWR9BE-NEXT:    xxswapd vs8, vs8 # Vec Defs: VSL8(VSR8) Vec Uses: VSL8(VSR8)VSL8(VSR8)
+; PWR9BE-NEXT:    xsadddp f8, f9, f8 # Vec Defs: F8(VSR8) Vec Uses: F9(VSR9)F8(VSR8)
+; PWR9BE-NEXT:    xsadddp f8, f8, f7 # Vec Defs: F8(VSR8) Vec Uses: F8(VSR8)F7(VSR7)
+; PWR9BE-NEXT:    xxswapd vs7, vs7 # Vec Defs: VSL7(VSR7) Vec Uses: VSL7(VSR7)VSL7(VSR7)
+; PWR9BE-NEXT:    xsadddp f7, f8, f7 # Vec Defs: F7(VSR7) Vec Uses: F8(VSR8)F7(VSR7)
+; PWR9BE-NEXT:    xsadddp f7, f7, f6 # Vec Defs: F7(VSR7) Vec Uses: F7(VSR7)F6(VSR6)
+; PWR9BE-NEXT:    xxswapd vs6, vs6 # Vec Defs: VSL6(VSR6) Vec Uses: VSL6(VSR6)VSL6(VSR6)
+; PWR9BE-NEXT:    xsadddp f6, f7, f6 # Vec Defs: F6(VSR6) Vec Uses: F7(VSR7)F6(VSR6)
+; PWR9BE-NEXT:    xsadddp f6, f6, f5 # Vec Defs: F6(VSR6) Vec Uses: F6(VSR6)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, vs5 # Vec Defs: VSL5(VSR5) Vec Uses: VSL5(VSR5)VSL5(VSR5)
+; PWR9BE-NEXT:    xsadddp f5, f6, f5 # Vec Defs: F5(VSR5) Vec Uses: F6(VSR6)F5(VSR5)
+; PWR9BE-NEXT:    xsadddp f5, f5, f4 # Vec Defs: F5(VSR5) Vec Uses: F5(VSR5)F4(VSR4)
+; PWR9BE-NEXT:    xxswapd vs4, vs4 # Vec Defs: VSL4(VSR4) Vec Uses: VSL4(VSR4)VSL4(VSR4)
+; PWR9BE-NEXT:    xsadddp f4, f5, f4 # Vec Defs: F4(VSR4) Vec Uses: F5(VSR5)F4(VSR4)
+; PWR9BE-NEXT:    xsadddp f4, f4, f3 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F3(VSR3)
+; PWR9BE-NEXT:    xxswapd vs3, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: VSL3(VSR3)VSL3(VSR3)
+; PWR9BE-NEXT:    xsadddp f3, f4, f3 # Vec Defs: F3(VSR3) Vec Uses: F4(VSR4)F3(VSR3)
+; PWR9BE-NEXT:    xsadddp f3, f3, f2 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)F2(VSR2)
+; PWR9BE-NEXT:    xxswapd vs2, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL2(VSR2)VSL2(VSR2)
+; PWR9BE-NEXT:    xsadddp f2, f3, f2 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)F2(VSR2)
+; PWR9BE-NEXT:    xsadddp f2, f2, f1 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)F1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs1, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)VSL1(VSR1)
+; PWR9BE-NEXT:    xsadddp f1, f2, f1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PWR9BE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR9BE-NEXT:    xxswapd vs0, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9BE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v64f64:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxswapd v18, v2
-; PWR10LE-NEXT:    lxv v17, 224(r1)
-; PWR10LE-NEXT:    lxv v16, 240(r1)
-; PWR10LE-NEXT:    xsadddp v2, v18, v2
-; PWR10LE-NEXT:    xxswapd v18, v3
-; PWR10LE-NEXT:    lxv v15, 256(r1)
-; PWR10LE-NEXT:    lxv v14, 272(r1)
-; PWR10LE-NEXT:    lxv v1, 288(r1)
-; PWR10LE-NEXT:    lxv v0, 304(r1)
-; PWR10LE-NEXT:    lxv vs13, 320(r1)
-; PWR10LE-NEXT:    lxv vs12, 336(r1)
-; PWR10LE-NEXT:    lxv vs11, 352(r1)
-; PWR10LE-NEXT:    lxv vs10, 368(r1)
-; PWR10LE-NEXT:    xsadddp v2, v2, v18
-; PWR10LE-NEXT:    lxv vs9, 384(r1)
-; PWR10LE-NEXT:    lxv vs8, 400(r1)
-; PWR10LE-NEXT:    lxv vs7, 416(r1)
-; PWR10LE-NEXT:    lxv vs6, 432(r1)
-; PWR10LE-NEXT:    lxv vs5, 448(r1)
-; PWR10LE-NEXT:    lxv vs4, 464(r1)
-; PWR10LE-NEXT:    lxv vs3, 480(r1)
-; PWR10LE-NEXT:    lxv vs2, 496(r1)
-; PWR10LE-NEXT:    lxv vs1, 512(r1)
-; PWR10LE-NEXT:    lxv vs0, 528(r1)
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, v4
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, v5
-; PWR10LE-NEXT:    xsadddp v2, v2, v4
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, v6
-; PWR10LE-NEXT:    xsadddp v2, v2, v5
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, v7
-; PWR10LE-NEXT:    xsadddp v2, v2, v6
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, v8
-; PWR10LE-NEXT:    xsadddp v2, v2, v7
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, v9
-; PWR10LE-NEXT:    xsadddp v2, v2, v8
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, v10
-; PWR10LE-NEXT:    xsadddp v2, v2, v9
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, v11
-; PWR10LE-NEXT:    xsadddp v2, v2, v10
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, v12
-; PWR10LE-NEXT:    xsadddp v2, v2, v11
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, v13
-; PWR10LE-NEXT:    xsadddp v2, v2, v12
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, v17
-; PWR10LE-NEXT:    xsadddp v2, v2, v13
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, v16
-; PWR10LE-NEXT:    xsadddp v2, v2, v17
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, v15
-; PWR10LE-NEXT:    xsadddp v2, v2, v16
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, v14
-; PWR10LE-NEXT:    xsadddp v2, v2, v15
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, v1
-; PWR10LE-NEXT:    xsadddp v2, v2, v14
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, v0
-; PWR10LE-NEXT:    xsadddp v2, v2, v1
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xxswapd v3, vs13
-; PWR10LE-NEXT:    xsadddp v2, v2, v0
-; PWR10LE-NEXT:    xsadddp v2, v2, v3
-; PWR10LE-NEXT:    xsadddp f13, v2, f13
-; PWR10LE-NEXT:    xxswapd v2, vs12
-; PWR10LE-NEXT:    xsadddp f13, f13, v2
-; PWR10LE-NEXT:    xsadddp f12, f13, f12
-; PWR10LE-NEXT:    xxswapd vs13, vs11
-; PWR10LE-NEXT:    xsadddp f12, f12, f13
-; PWR10LE-NEXT:    xsadddp f11, f12, f11
-; PWR10LE-NEXT:    xxswapd vs12, vs10
-; PWR10LE-NEXT:    xsadddp f11, f11, f12
-; PWR10LE-NEXT:    xsadddp f10, f11, f10
-; PWR10LE-NEXT:    xxswapd vs11, vs9
-; PWR10LE-NEXT:    xsadddp f10, f10, f11
-; PWR10LE-NEXT:    xsadddp f9, f10, f9
-; PWR10LE-NEXT:    xxswapd vs10, vs8
-; PWR10LE-NEXT:    xsadddp f9, f9, f10
-; PWR10LE-NEXT:    xsadddp f8, f9, f8
-; PWR10LE-NEXT:    xxswapd vs9, vs7
-; PWR10LE-NEXT:    xsadddp f8, f8, f9
-; PWR10LE-NEXT:    xsadddp f7, f8, f7
-; PWR10LE-NEXT:    xxswapd vs8, vs6
-; PWR10LE-NEXT:    xsadddp f7, f7, f8
-; PWR10LE-NEXT:    xsadddp f6, f7, f6
-; PWR10LE-NEXT:    xxswapd vs7, vs5
-; PWR10LE-NEXT:    xsadddp f6, f6, f7
-; PWR10LE-NEXT:    xsadddp f5, f6, f5
-; PWR10LE-NEXT:    xxswapd vs6, vs4
-; PWR10LE-NEXT:    xsadddp f5, f5, f6
-; PWR10LE-NEXT:    xsadddp f4, f5, f4
-; PWR10LE-NEXT:    xxswapd vs5, vs3
-; PWR10LE-NEXT:    xsadddp f4, f4, f5
-; PWR10LE-NEXT:    xsadddp f3, f4, f3
-; PWR10LE-NEXT:    xxswapd vs4, vs2
-; PWR10LE-NEXT:    xsadddp f3, f3, f4
-; PWR10LE-NEXT:    xsadddp f2, f3, f2
-; PWR10LE-NEXT:    xxswapd vs3, vs1
-; PWR10LE-NEXT:    xsadddp f2, f2, f3
-; PWR10LE-NEXT:    xsadddp f1, f2, f1
-; PWR10LE-NEXT:    xxswapd vs2, vs0
-; PWR10LE-NEXT:    xsadddp f1, f1, f2
-; PWR10LE-NEXT:    xsadddp f1, f1, f0
+; PWR10LE-NEXT:    xxswapd v18, v2 # Vec Defs: V18(VSR50) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    lxv v17, 224(r1) # Vec Defs: V17(VSR49)
+; PWR10LE-NEXT:    lxv v16, 240(r1) # Vec Defs: V16(VSR48)
+; PWR10LE-NEXT:    xsadddp v2, v18, v2 # Vec Defs: VF2(VSR2) Vec Uses: VF18(VSR18)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v18, v3 # Vec Defs: V18(VSR50) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    lxv v15, 256(r1) # Vec Defs: V15(VSR47)
+; PWR10LE-NEXT:    lxv v14, 272(r1) # Vec Defs: V14(VSR46)
+; PWR10LE-NEXT:    lxv v1, 288(r1) # Vec Defs: V1(VSR33)
+; PWR10LE-NEXT:    lxv v0, 304(r1) # Vec Defs: V0(VSR32)
+; PWR10LE-NEXT:    lxv vs13, 320(r1) # Vec Defs: VSL13(VSR13)
+; PWR10LE-NEXT:    lxv vs12, 336(r1) # Vec Defs: VSL12(VSR12)
+; PWR10LE-NEXT:    lxv vs11, 352(r1) # Vec Defs: VSL11(VSR11)
+; PWR10LE-NEXT:    lxv vs10, 368(r1) # Vec Defs: VSL10(VSR10)
+; PWR10LE-NEXT:    xsadddp v2, v2, v18 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF18(VSR18)
+; PWR10LE-NEXT:    lxv vs9, 384(r1) # Vec Defs: VSL9(VSR9)
+; PWR10LE-NEXT:    lxv vs8, 400(r1) # Vec Defs: VSL8(VSR8)
+; PWR10LE-NEXT:    lxv vs7, 416(r1) # Vec Defs: VSL7(VSR7)
+; PWR10LE-NEXT:    lxv vs6, 432(r1) # Vec Defs: VSL6(VSR6)
+; PWR10LE-NEXT:    lxv vs5, 448(r1) # Vec Defs: VSL5(VSR5)
+; PWR10LE-NEXT:    lxv vs4, 464(r1) # Vec Defs: VSL4(VSR4)
+; PWR10LE-NEXT:    lxv vs3, 480(r1) # Vec Defs: VSL3(VSR3)
+; PWR10LE-NEXT:    lxv vs2, 496(r1) # Vec Defs: VSL2(VSR2)
+; PWR10LE-NEXT:    lxv vs1, 512(r1) # Vec Defs: VSL1(VSR1)
+; PWR10LE-NEXT:    lxv vs0, 528(r1) # Vec Defs: VSL0(VSR0)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, v4 # Vec Defs: V3(VSR35) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, v5 # Vec Defs: V3(VSR35) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10LE-NEXT:    xsadddp v2, v2, v4 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF4(VSR4)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, v6 # Vec Defs: V3(VSR35) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR10LE-NEXT:    xsadddp v2, v2, v5 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF5(VSR5)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, v7 # Vec Defs: V3(VSR35) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR10LE-NEXT:    xsadddp v2, v2, v6 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF6(VSR6)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, v8 # Vec Defs: V3(VSR35) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR10LE-NEXT:    xsadddp v2, v2, v7 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF7(VSR7)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, v9 # Vec Defs: V3(VSR35) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR10LE-NEXT:    xsadddp v2, v2, v8 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF8(VSR8)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, v10 # Vec Defs: V3(VSR35) Vec Uses: V10(VSR42)V10(VSR42)
+; PWR10LE-NEXT:    xsadddp v2, v2, v9 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF9(VSR9)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, v11 # Vec Defs: V3(VSR35) Vec Uses: V11(VSR43)V11(VSR43)
+; PWR10LE-NEXT:    xsadddp v2, v2, v10 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF10(VSR10)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, v12 # Vec Defs: V3(VSR35) Vec Uses: V12(VSR44)V12(VSR44)
+; PWR10LE-NEXT:    xsadddp v2, v2, v11 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF11(VSR11)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, v13 # Vec Defs: V3(VSR35) Vec Uses: V13(VSR45)V13(VSR45)
+; PWR10LE-NEXT:    xsadddp v2, v2, v12 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF12(VSR12)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, v17 # Vec Defs: V3(VSR35) Vec Uses: V17(VSR49)V17(VSR49)
+; PWR10LE-NEXT:    xsadddp v2, v2, v13 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF13(VSR13)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, v16 # Vec Defs: V3(VSR35) Vec Uses: V16(VSR48)V16(VSR48)
+; PWR10LE-NEXT:    xsadddp v2, v2, v17 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF17(VSR17)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, v15 # Vec Defs: V3(VSR35) Vec Uses: V15(VSR47)V15(VSR47)
+; PWR10LE-NEXT:    xsadddp v2, v2, v16 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF16(VSR16)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, v14 # Vec Defs: V3(VSR35) Vec Uses: V14(VSR46)V14(VSR46)
+; PWR10LE-NEXT:    xsadddp v2, v2, v15 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF15(VSR15)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, v1 # Vec Defs: V3(VSR35) Vec Uses: V1(VSR33)V1(VSR33)
+; PWR10LE-NEXT:    xsadddp v2, v2, v14 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF14(VSR14)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, v0 # Vec Defs: V3(VSR35) Vec Uses: V0(VSR32)V0(VSR32)
+; PWR10LE-NEXT:    xsadddp v2, v2, v1 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF1(VSR1)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xxswapd v3, vs13 # Vec Defs: V3(VSR35) Vec Uses: VSL13(VSR13)VSL13(VSR13)
+; PWR10LE-NEXT:    xsadddp v2, v2, v0 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF0(VSR0)
+; PWR10LE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10LE-NEXT:    xsadddp f13, v2, f13 # Vec Defs: F13(VSR13) Vec Uses: VF2(VSR2)F13(VSR13)
+; PWR10LE-NEXT:    xxswapd v2, vs12 # Vec Defs: V2(VSR34) Vec Uses: VSL12(VSR12)VSL12(VSR12)
+; PWR10LE-NEXT:    xsadddp f13, f13, v2 # Vec Defs: F13(VSR13) Vec Uses: F13(VSR13)VF2(VSR2)
+; PWR10LE-NEXT:    xsadddp f12, f13, f12 # Vec Defs: F12(VSR12) Vec Uses: F13(VSR13)F12(VSR12)
+; PWR10LE-NEXT:    xxswapd vs13, vs11 # Vec Defs: VSL13(VSR13) Vec Uses: VSL11(VSR11)VSL11(VSR11)
+; PWR10LE-NEXT:    xsadddp f12, f12, f13 # Vec Defs: F12(VSR12) Vec Uses: F12(VSR12)F13(VSR13)
+; PWR10LE-NEXT:    xsadddp f11, f12, f11 # Vec Defs: F11(VSR11) Vec Uses: F12(VSR12)F11(VSR11)
+; PWR10LE-NEXT:    xxswapd vs12, vs10 # Vec Defs: VSL12(VSR12) Vec Uses: VSL10(VSR10)VSL10(VSR10)
+; PWR10LE-NEXT:    xsadddp f11, f11, f12 # Vec Defs: F11(VSR11) Vec Uses: F11(VSR11)F12(VSR12)
+; PWR10LE-NEXT:    xsadddp f10, f11, f10 # Vec Defs: F10(VSR10) Vec Uses: F11(VSR11)F10(VSR10)
+; PWR10LE-NEXT:    xxswapd vs11, vs9 # Vec Defs: VSL11(VSR11) Vec Uses: VSL9(VSR9)VSL9(VSR9)
+; PWR10LE-NEXT:    xsadddp f10, f10, f11 # Vec Defs: F10(VSR10) Vec Uses: F10(VSR10)F11(VSR11)
+; PWR10LE-NEXT:    xsadddp f9, f10, f9 # Vec Defs: F9(VSR9) Vec Uses: F10(VSR10)F9(VSR9)
+; PWR10LE-NEXT:    xxswapd vs10, vs8 # Vec Defs: VSL10(VSR10) Vec Uses: VSL8(VSR8)VSL8(VSR8)
+; PWR10LE-NEXT:    xsadddp f9, f9, f10 # Vec Defs: F9(VSR9) Vec Uses: F9(VSR9)F10(VSR10)
+; PWR10LE-NEXT:    xsadddp f8, f9, f8 # Vec Defs: F8(VSR8) Vec Uses: F9(VSR9)F8(VSR8)
+; PWR10LE-NEXT:    xxswapd vs9, vs7 # Vec Defs: VSL9(VSR9) Vec Uses: VSL7(VSR7)VSL7(VSR7)
+; PWR10LE-NEXT:    xsadddp f8, f8, f9 # Vec Defs: F8(VSR8) Vec Uses: F8(VSR8)F9(VSR9)
+; PWR10LE-NEXT:    xsadddp f7, f8, f7 # Vec Defs: F7(VSR7) Vec Uses: F8(VSR8)F7(VSR7)
+; PWR10LE-NEXT:    xxswapd vs8, vs6 # Vec Defs: VSL8(VSR8) Vec Uses: VSL6(VSR6)VSL6(VSR6)
+; PWR10LE-NEXT:    xsadddp f7, f7, f8 # Vec Defs: F7(VSR7) Vec Uses: F7(VSR7)F8(VSR8)
+; PWR10LE-NEXT:    xsadddp f6, f7, f6 # Vec Defs: F6(VSR6) Vec Uses: F7(VSR7)F6(VSR6)
+; PWR10LE-NEXT:    xxswapd vs7, vs5 # Vec Defs: VSL7(VSR7) Vec Uses: VSL5(VSR5)VSL5(VSR5)
+; PWR10LE-NEXT:    xsadddp f6, f6, f7 # Vec Defs: F6(VSR6) Vec Uses: F6(VSR6)F7(VSR7)
+; PWR10LE-NEXT:    xsadddp f5, f6, f5 # Vec Defs: F5(VSR5) Vec Uses: F6(VSR6)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs6, vs4 # Vec Defs: VSL6(VSR6) Vec Uses: VSL4(VSR4)VSL4(VSR4)
+; PWR10LE-NEXT:    xsadddp f5, f5, f6 # Vec Defs: F5(VSR5) Vec Uses: F5(VSR5)F6(VSR6)
+; PWR10LE-NEXT:    xsadddp f4, f5, f4 # Vec Defs: F4(VSR4) Vec Uses: F5(VSR5)F4(VSR4)
+; PWR10LE-NEXT:    xxswapd vs5, vs3 # Vec Defs: VSL5(VSR5) Vec Uses: VSL3(VSR3)VSL3(VSR3)
+; PWR10LE-NEXT:    xsadddp f4, f4, f5 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F5(VSR5)
+; PWR10LE-NEXT:    xsadddp f3, f4, f3 # Vec Defs: F3(VSR3) Vec Uses: F4(VSR4)F3(VSR3)
+; PWR10LE-NEXT:    xxswapd vs4, vs2 # Vec Defs: VSL4(VSR4) Vec Uses: VSL2(VSR2)VSL2(VSR2)
+; PWR10LE-NEXT:    xsadddp f3, f3, f4 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)F4(VSR4)
+; PWR10LE-NEXT:    xsadddp f2, f3, f2 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)F2(VSR2)
+; PWR10LE-NEXT:    xxswapd vs3, vs1 # Vec Defs: VSL3(VSR3) Vec Uses: VSL1(VSR1)VSL1(VSR1)
+; PWR10LE-NEXT:    xsadddp f2, f2, f3 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)F3(VSR3)
+; PWR10LE-NEXT:    xsadddp f1, f2, f1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs2, vs0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10LE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR10LE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v64f64:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xxswapd v18, v2
-; PWR10BE-NEXT:    lxv v17, 240(r1)
-; PWR10BE-NEXT:    lxv v16, 256(r1)
-; PWR10BE-NEXT:    xsadddp v2, v2, v18
-; PWR10BE-NEXT:    lxv v15, 272(r1)
-; PWR10BE-NEXT:    lxv v14, 288(r1)
-; PWR10BE-NEXT:    lxv v1, 304(r1)
-; PWR10BE-NEXT:    lxv v0, 320(r1)
-; PWR10BE-NEXT:    lxv vs13, 336(r1)
-; PWR10BE-NEXT:    lxv vs12, 352(r1)
-; PWR10BE-NEXT:    lxv vs11, 368(r1)
-; PWR10BE-NEXT:    lxv vs10, 384(r1)
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v3
-; PWR10BE-NEXT:    lxv vs9, 400(r1)
-; PWR10BE-NEXT:    lxv vs8, 416(r1)
-; PWR10BE-NEXT:    lxv vs7, 432(r1)
-; PWR10BE-NEXT:    lxv vs6, 448(r1)
-; PWR10BE-NEXT:    lxv vs5, 464(r1)
-; PWR10BE-NEXT:    lxv vs4, 480(r1)
-; PWR10BE-NEXT:    lxv vs3, 496(r1)
-; PWR10BE-NEXT:    lxv vs2, 512(r1)
-; PWR10BE-NEXT:    lxv vs1, 528(r1)
-; PWR10BE-NEXT:    lxv vs0, 544(r1)
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v4
-; PWR10BE-NEXT:    xsadddp v2, v2, v4
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v5
-; PWR10BE-NEXT:    xsadddp v2, v2, v5
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v6
-; PWR10BE-NEXT:    xsadddp v2, v2, v6
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v7
-; PWR10BE-NEXT:    xsadddp v2, v2, v7
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v8
-; PWR10BE-NEXT:    xsadddp v2, v2, v8
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v9
-; PWR10BE-NEXT:    xsadddp v2, v2, v9
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v10
-; PWR10BE-NEXT:    xsadddp v2, v2, v10
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v11
-; PWR10BE-NEXT:    xsadddp v2, v2, v11
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v12
-; PWR10BE-NEXT:    xsadddp v2, v2, v12
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v13
-; PWR10BE-NEXT:    xsadddp v2, v2, v13
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v17
-; PWR10BE-NEXT:    xsadddp v2, v2, v17
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v16
-; PWR10BE-NEXT:    xsadddp v2, v2, v16
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v15
-; PWR10BE-NEXT:    xsadddp v2, v2, v15
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v14
-; PWR10BE-NEXT:    xsadddp v2, v2, v14
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v1
-; PWR10BE-NEXT:    xsadddp v2, v2, v1
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xxswapd v3, v0
-; PWR10BE-NEXT:    xsadddp v2, v2, v0
-; PWR10BE-NEXT:    xsadddp v2, v2, v3
-; PWR10BE-NEXT:    xsadddp v2, v2, f13
-; PWR10BE-NEXT:    xxswapd vs13, vs13
-; PWR10BE-NEXT:    xsadddp f13, v2, f13
-; PWR10BE-NEXT:    xsadddp f13, f13, f12
-; PWR10BE-NEXT:    xxswapd vs12, vs12
-; PWR10BE-NEXT:    xsadddp f12, f13, f12
-; PWR10BE-NEXT:    xsadddp f12, f12, f11
-; PWR10BE-NEXT:    xxswapd vs11, vs11
-; PWR10BE-NEXT:    xsadddp f11, f12, f11
-; PWR10BE-NEXT:    xsadddp f11, f11, f10
-; PWR10BE-NEXT:    xxswapd vs10, vs10
-; PWR10BE-NEXT:    xsadddp f10, f11, f10
-; PWR10BE-NEXT:    xsadddp f10, f10, f9
-; PWR10BE-NEXT:    xxswapd vs9, vs9
-; PWR10BE-NEXT:    xsadddp f9, f10, f9
-; PWR10BE-NEXT:    xsadddp f9, f9, f8
-; PWR10BE-NEXT:    xxswapd vs8, vs8
-; PWR10BE-NEXT:    xsadddp f8, f9, f8
-; PWR10BE-NEXT:    xsadddp f8, f8, f7
-; PWR10BE-NEXT:    xxswapd vs7, vs7
-; PWR10BE-NEXT:    xsadddp f7, f8, f7
-; PWR10BE-NEXT:    xsadddp f7, f7, f6
-; PWR10BE-NEXT:    xxswapd vs6, vs6
-; PWR10BE-NEXT:    xsadddp f6, f7, f6
-; PWR10BE-NEXT:    xsadddp f6, f6, f5
-; PWR10BE-NEXT:    xxswapd vs5, vs5
-; PWR10BE-NEXT:    xsadddp f5, f6, f5
-; PWR10BE-NEXT:    xsadddp f5, f5, f4
-; PWR10BE-NEXT:    xxswapd vs4, vs4
-; PWR10BE-NEXT:    xsadddp f4, f5, f4
-; PWR10BE-NEXT:    xsadddp f4, f4, f3
-; PWR10BE-NEXT:    xxswapd vs3, vs3
-; PWR10BE-NEXT:    xsadddp f3, f4, f3
-; PWR10BE-NEXT:    xsadddp f3, f3, f2
-; PWR10BE-NEXT:    xxswapd vs2, vs2
-; PWR10BE-NEXT:    xsadddp f2, f3, f2
-; PWR10BE-NEXT:    xsadddp f2, f2, f1
-; PWR10BE-NEXT:    xxswapd vs1, vs1
-; PWR10BE-NEXT:    xsadddp f1, f2, f1
-; PWR10BE-NEXT:    xsadddp f1, f1, f0
-; PWR10BE-NEXT:    xxswapd vs0, vs0
-; PWR10BE-NEXT:    xsadddp f1, f1, f0
+; PWR10BE-NEXT:    xxswapd v18, v2 # Vec Defs: V18(VSR50) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    lxv v17, 240(r1) # Vec Defs: V17(VSR49)
+; PWR10BE-NEXT:    lxv v16, 256(r1) # Vec Defs: V16(VSR48)
+; PWR10BE-NEXT:    xsadddp v2, v2, v18 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF18(VSR18)
+; PWR10BE-NEXT:    lxv v15, 272(r1) # Vec Defs: V15(VSR47)
+; PWR10BE-NEXT:    lxv v14, 288(r1) # Vec Defs: V14(VSR46)
+; PWR10BE-NEXT:    lxv v1, 304(r1) # Vec Defs: V1(VSR33)
+; PWR10BE-NEXT:    lxv v0, 320(r1) # Vec Defs: V0(VSR32)
+; PWR10BE-NEXT:    lxv vs13, 336(r1) # Vec Defs: VSL13(VSR13)
+; PWR10BE-NEXT:    lxv vs12, 352(r1) # Vec Defs: VSL12(VSR12)
+; PWR10BE-NEXT:    lxv vs11, 368(r1) # Vec Defs: VSL11(VSR11)
+; PWR10BE-NEXT:    lxv vs10, 384(r1) # Vec Defs: VSL10(VSR10)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v3 # Vec Defs: V3(VSR35) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    lxv vs9, 400(r1) # Vec Defs: VSL9(VSR9)
+; PWR10BE-NEXT:    lxv vs8, 416(r1) # Vec Defs: VSL8(VSR8)
+; PWR10BE-NEXT:    lxv vs7, 432(r1) # Vec Defs: VSL7(VSR7)
+; PWR10BE-NEXT:    lxv vs6, 448(r1) # Vec Defs: VSL6(VSR6)
+; PWR10BE-NEXT:    lxv vs5, 464(r1) # Vec Defs: VSL5(VSR5)
+; PWR10BE-NEXT:    lxv vs4, 480(r1) # Vec Defs: VSL4(VSR4)
+; PWR10BE-NEXT:    lxv vs3, 496(r1) # Vec Defs: VSL3(VSR3)
+; PWR10BE-NEXT:    lxv vs2, 512(r1) # Vec Defs: VSL2(VSR2)
+; PWR10BE-NEXT:    lxv vs1, 528(r1) # Vec Defs: VSL1(VSR1)
+; PWR10BE-NEXT:    lxv vs0, 544(r1) # Vec Defs: VSL0(VSR0)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v4 # Vec Defs: V3(VSR35) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10BE-NEXT:    xsadddp v2, v2, v4 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF4(VSR4)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v5 # Vec Defs: V3(VSR35) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10BE-NEXT:    xsadddp v2, v2, v5 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF5(VSR5)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v6 # Vec Defs: V3(VSR35) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR10BE-NEXT:    xsadddp v2, v2, v6 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF6(VSR6)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v7 # Vec Defs: V3(VSR35) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR10BE-NEXT:    xsadddp v2, v2, v7 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF7(VSR7)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v8 # Vec Defs: V3(VSR35) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR10BE-NEXT:    xsadddp v2, v2, v8 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF8(VSR8)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v9 # Vec Defs: V3(VSR35) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR10BE-NEXT:    xsadddp v2, v2, v9 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF9(VSR9)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v10 # Vec Defs: V3(VSR35) Vec Uses: V10(VSR42)V10(VSR42)
+; PWR10BE-NEXT:    xsadddp v2, v2, v10 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF10(VSR10)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v11 # Vec Defs: V3(VSR35) Vec Uses: V11(VSR43)V11(VSR43)
+; PWR10BE-NEXT:    xsadddp v2, v2, v11 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF11(VSR11)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v12 # Vec Defs: V3(VSR35) Vec Uses: V12(VSR44)V12(VSR44)
+; PWR10BE-NEXT:    xsadddp v2, v2, v12 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF12(VSR12)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v13 # Vec Defs: V3(VSR35) Vec Uses: V13(VSR45)V13(VSR45)
+; PWR10BE-NEXT:    xsadddp v2, v2, v13 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF13(VSR13)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v17 # Vec Defs: V3(VSR35) Vec Uses: V17(VSR49)V17(VSR49)
+; PWR10BE-NEXT:    xsadddp v2, v2, v17 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF17(VSR17)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v16 # Vec Defs: V3(VSR35) Vec Uses: V16(VSR48)V16(VSR48)
+; PWR10BE-NEXT:    xsadddp v2, v2, v16 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF16(VSR16)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v15 # Vec Defs: V3(VSR35) Vec Uses: V15(VSR47)V15(VSR47)
+; PWR10BE-NEXT:    xsadddp v2, v2, v15 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF15(VSR15)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v14 # Vec Defs: V3(VSR35) Vec Uses: V14(VSR46)V14(VSR46)
+; PWR10BE-NEXT:    xsadddp v2, v2, v14 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF14(VSR14)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v1 # Vec Defs: V3(VSR35) Vec Uses: V1(VSR33)V1(VSR33)
+; PWR10BE-NEXT:    xsadddp v2, v2, v1 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF1(VSR1)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xxswapd v3, v0 # Vec Defs: V3(VSR35) Vec Uses: V0(VSR32)V0(VSR32)
+; PWR10BE-NEXT:    xsadddp v2, v2, v0 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF0(VSR0)
+; PWR10BE-NEXT:    xsadddp v2, v2, v3 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)VF3(VSR3)
+; PWR10BE-NEXT:    xsadddp v2, v2, f13 # Vec Defs: VF2(VSR2) Vec Uses: VF2(VSR2)F13(VSR13)
+; PWR10BE-NEXT:    xxswapd vs13, vs13 # Vec Defs: VSL13(VSR13) Vec Uses: VSL13(VSR13)VSL13(VSR13)
+; PWR10BE-NEXT:    xsadddp f13, v2, f13 # Vec Defs: F13(VSR13) Vec Uses: VF2(VSR2)F13(VSR13)
+; PWR10BE-NEXT:    xsadddp f13, f13, f12 # Vec Defs: F13(VSR13) Vec Uses: F13(VSR13)F12(VSR12)
+; PWR10BE-NEXT:    xxswapd vs12, vs12 # Vec Defs: VSL12(VSR12) Vec Uses: VSL12(VSR12)VSL12(VSR12)
+; PWR10BE-NEXT:    xsadddp f12, f13, f12 # Vec Defs: F12(VSR12) Vec Uses: F13(VSR13)F12(VSR12)
+; PWR10BE-NEXT:    xsadddp f12, f12, f11 # Vec Defs: F12(VSR12) Vec Uses: F12(VSR12)F11(VSR11)
+; PWR10BE-NEXT:    xxswapd vs11, vs11 # Vec Defs: VSL11(VSR11) Vec Uses: VSL11(VSR11)VSL11(VSR11)
+; PWR10BE-NEXT:    xsadddp f11, f12, f11 # Vec Defs: F11(VSR11) Vec Uses: F12(VSR12)F11(VSR11)
+; PWR10BE-NEXT:    xsadddp f11, f11, f10 # Vec Defs: F11(VSR11) Vec Uses: F11(VSR11)F10(VSR10)
+; PWR10BE-NEXT:    xxswapd vs10, vs10 # Vec Defs: VSL10(VSR10) Vec Uses: VSL10(VSR10)VSL10(VSR10)
+; PWR10BE-NEXT:    xsadddp f10, f11, f10 # Vec Defs: F10(VSR10) Vec Uses: F11(VSR11)F10(VSR10)
+; PWR10BE-NEXT:    xsadddp f10, f10, f9 # Vec Defs: F10(VSR10) Vec Uses: F10(VSR10)F9(VSR9)
+; PWR10BE-NEXT:    xxswapd vs9, vs9 # Vec Defs: VSL9(VSR9) Vec Uses: VSL9(VSR9)VSL9(VSR9)
+; PWR10BE-NEXT:    xsadddp f9, f10, f9 # Vec Defs: F9(VSR9) Vec Uses: F10(VSR10)F9(VSR9)
+; PWR10BE-NEXT:    xsadddp f9, f9, f8 # Vec Defs: F9(VSR9) Vec Uses: F9(VSR9)F8(VSR8)
+; PWR10BE-NEXT:    xxswapd vs8, vs8 # Vec Defs: VSL8(VSR8) Vec Uses: VSL8(VSR8)VSL8(VSR8)
+; PWR10BE-NEXT:    xsadddp f8, f9, f8 # Vec Defs: F8(VSR8) Vec Uses: F9(VSR9)F8(VSR8)
+; PWR10BE-NEXT:    xsadddp f8, f8, f7 # Vec Defs: F8(VSR8) Vec Uses: F8(VSR8)F7(VSR7)
+; PWR10BE-NEXT:    xxswapd vs7, vs7 # Vec Defs: VSL7(VSR7) Vec Uses: VSL7(VSR7)VSL7(VSR7)
+; PWR10BE-NEXT:    xsadddp f7, f8, f7 # Vec Defs: F7(VSR7) Vec Uses: F8(VSR8)F7(VSR7)
+; PWR10BE-NEXT:    xsadddp f7, f7, f6 # Vec Defs: F7(VSR7) Vec Uses: F7(VSR7)F6(VSR6)
+; PWR10BE-NEXT:    xxswapd vs6, vs6 # Vec Defs: VSL6(VSR6) Vec Uses: VSL6(VSR6)VSL6(VSR6)
+; PWR10BE-NEXT:    xsadddp f6, f7, f6 # Vec Defs: F6(VSR6) Vec Uses: F7(VSR7)F6(VSR6)
+; PWR10BE-NEXT:    xsadddp f6, f6, f5 # Vec Defs: F6(VSR6) Vec Uses: F6(VSR6)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, vs5 # Vec Defs: VSL5(VSR5) Vec Uses: VSL5(VSR5)VSL5(VSR5)
+; PWR10BE-NEXT:    xsadddp f5, f6, f5 # Vec Defs: F5(VSR5) Vec Uses: F6(VSR6)F5(VSR5)
+; PWR10BE-NEXT:    xsadddp f5, f5, f4 # Vec Defs: F5(VSR5) Vec Uses: F5(VSR5)F4(VSR4)
+; PWR10BE-NEXT:    xxswapd vs4, vs4 # Vec Defs: VSL4(VSR4) Vec Uses: VSL4(VSR4)VSL4(VSR4)
+; PWR10BE-NEXT:    xsadddp f4, f5, f4 # Vec Defs: F4(VSR4) Vec Uses: F5(VSR5)F4(VSR4)
+; PWR10BE-NEXT:    xsadddp f4, f4, f3 # Vec Defs: F4(VSR4) Vec Uses: F4(VSR4)F3(VSR3)
+; PWR10BE-NEXT:    xxswapd vs3, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: VSL3(VSR3)VSL3(VSR3)
+; PWR10BE-NEXT:    xsadddp f3, f4, f3 # Vec Defs: F3(VSR3) Vec Uses: F4(VSR4)F3(VSR3)
+; PWR10BE-NEXT:    xsadddp f3, f3, f2 # Vec Defs: F3(VSR3) Vec Uses: F3(VSR3)F2(VSR2)
+; PWR10BE-NEXT:    xxswapd vs2, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL2(VSR2)VSL2(VSR2)
+; PWR10BE-NEXT:    xsadddp f2, f3, f2 # Vec Defs: F2(VSR2) Vec Uses: F3(VSR3)F2(VSR2)
+; PWR10BE-NEXT:    xsadddp f2, f2, f1 # Vec Defs: F2(VSR2) Vec Uses: F2(VSR2)F1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs1, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL1(VSR1)VSL1(VSR1)
+; PWR10BE-NEXT:    xsadddp f1, f2, f1 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)F1(VSR1)
+; PWR10BE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR10BE-NEXT:    xxswapd vs0, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10BE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call double @llvm.vector.reduce.fadd.v64f64(double -0.000000e+00, <64 x double> %a)
   ret double %0
 }
 
 define dso_local double @v64f64_b(<64 x double> %a, double %b) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v64f64_b:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    xxswapd v19, v2
-; PWR9LE-NEXT:    lxv v18, 224(r1)
-; PWR9LE-NEXT:    lxv v17, 240(r1)
-; PWR9LE-NEXT:    lxv v16, 256(r1)
-; PWR9LE-NEXT:    lxv v15, 272(r1)
-; PWR9LE-NEXT:    xsadddp f1, f1, v19
-; PWR9LE-NEXT:    lxv v14, 288(r1)
-; PWR9LE-NEXT:    lxv v1, 304(r1)
-; PWR9LE-NEXT:    lxv v0, 320(r1)
-; PWR9LE-NEXT:    lxv vs13, 336(r1)
-; PWR9LE-NEXT:    lxv vs12, 352(r1)
-; PWR9LE-NEXT:    lxv vs11, 368(r1)
-; PWR9LE-NEXT:    lxv vs10, 384(r1)
-; PWR9LE-NEXT:    lxv vs9, 400(r1)
-; PWR9LE-NEXT:    lxv vs8, 416(r1)
-; PWR9LE-NEXT:    lxv vs7, 432(r1)
-; PWR9LE-NEXT:    lxv vs6, 448(r1)
-; PWR9LE-NEXT:    lxv vs5, 464(r1)
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v3
-; PWR9LE-NEXT:    lxv vs4, 480(r1)
-; PWR9LE-NEXT:    lxv vs3, 496(r1)
-; PWR9LE-NEXT:    lxv vs2, 512(r1)
-; PWR9LE-NEXT:    lxv vs0, 528(r1)
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v4
-; PWR9LE-NEXT:    xsadddp f1, f1, v3
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v5
-; PWR9LE-NEXT:    xsadddp f1, f1, v4
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v6
-; PWR9LE-NEXT:    xsadddp f1, f1, v5
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v7
-; PWR9LE-NEXT:    xsadddp f1, f1, v6
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v8
-; PWR9LE-NEXT:    xsadddp f1, f1, v7
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v9
-; PWR9LE-NEXT:    xsadddp f1, f1, v8
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v10
-; PWR9LE-NEXT:    xsadddp f1, f1, v9
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v11
-; PWR9LE-NEXT:    xsadddp f1, f1, v10
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v12
-; PWR9LE-NEXT:    xsadddp f1, f1, v11
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v13
-; PWR9LE-NEXT:    xsadddp f1, f1, v12
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v18
-; PWR9LE-NEXT:    xsadddp f1, f1, v13
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v17
-; PWR9LE-NEXT:    xsadddp f1, f1, v18
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v16
-; PWR9LE-NEXT:    xsadddp f1, f1, v17
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v15
-; PWR9LE-NEXT:    xsadddp f1, f1, v16
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v14
-; PWR9LE-NEXT:    xsadddp f1, f1, v15
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v1
-; PWR9LE-NEXT:    xsadddp f1, f1, v14
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, v0
-; PWR9LE-NEXT:    xsadddp f1, f1, v1
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xxswapd v2, vs13
-; PWR9LE-NEXT:    xsadddp f1, f1, v0
-; PWR9LE-NEXT:    xsadddp f1, f1, v2
-; PWR9LE-NEXT:    xsadddp f1, f1, f13
-; PWR9LE-NEXT:    xxswapd vs13, vs12
-; PWR9LE-NEXT:    xsadddp f1, f1, f13
-; PWR9LE-NEXT:    xsadddp f1, f1, f12
-; PWR9LE-NEXT:    xxswapd vs12, vs11
-; PWR9LE-NEXT:    xsadddp f1, f1, f12
-; PWR9LE-NEXT:    xsadddp f1, f1, f11
-; PWR9LE-NEXT:    xxswapd vs11, vs10
-; PWR9LE-NEXT:    xsadddp f1, f1, f11
-; PWR9LE-NEXT:    xsadddp f1, f1, f10
-; PWR9LE-NEXT:    xxswapd vs10, vs9
-; PWR9LE-NEXT:    xsadddp f1, f1, f10
-; PWR9LE-NEXT:    xsadddp f1, f1, f9
-; PWR9LE-NEXT:    xxswapd vs9, vs8
-; PWR9LE-NEXT:    xsadddp f1, f1, f9
-; PWR9LE-NEXT:    xsadddp f1, f1, f8
-; PWR9LE-NEXT:    xxswapd vs8, vs7
-; PWR9LE-NEXT:    xsadddp f1, f1, f8
-; PWR9LE-NEXT:    xsadddp f1, f1, f7
-; PWR9LE-NEXT:    xxswapd vs7, vs6
-; PWR9LE-NEXT:    xsadddp f1, f1, f7
-; PWR9LE-NEXT:    xsadddp f1, f1, f6
-; PWR9LE-NEXT:    xxswapd vs6, vs5
-; PWR9LE-NEXT:    xsadddp f1, f1, f6
-; PWR9LE-NEXT:    xsadddp f1, f1, f5
-; PWR9LE-NEXT:    xxswapd vs5, vs4
-; PWR9LE-NEXT:    xsadddp f1, f1, f5
-; PWR9LE-NEXT:    xsadddp f1, f1, f4
-; PWR9LE-NEXT:    xxswapd vs4, vs3
-; PWR9LE-NEXT:    xsadddp f1, f1, f4
-; PWR9LE-NEXT:    xsadddp f1, f1, f3
-; PWR9LE-NEXT:    xxswapd vs3, vs2
-; PWR9LE-NEXT:    xsadddp f1, f1, f3
-; PWR9LE-NEXT:    xsadddp f1, f1, f2
-; PWR9LE-NEXT:    xxswapd vs2, vs0
-; PWR9LE-NEXT:    xsadddp f1, f1, f2
-; PWR9LE-NEXT:    xsadddp f1, f1, f0
+; PWR9LE-NEXT:    xxswapd v19, v2 # Vec Defs: V19(VSR51) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9LE-NEXT:    lxv v18, 224(r1) # Vec Defs: V18(VSR50)
+; PWR9LE-NEXT:    lxv v17, 240(r1) # Vec Defs: V17(VSR49)
+; PWR9LE-NEXT:    lxv v16, 256(r1) # Vec Defs: V16(VSR48)
+; PWR9LE-NEXT:    lxv v15, 272(r1) # Vec Defs: V15(VSR47)
+; PWR9LE-NEXT:    xsadddp f1, f1, v19 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF19(VSR19)
+; PWR9LE-NEXT:    lxv v14, 288(r1) # Vec Defs: V14(VSR46)
+; PWR9LE-NEXT:    lxv v1, 304(r1) # Vec Defs: V1(VSR33)
+; PWR9LE-NEXT:    lxv v0, 320(r1) # Vec Defs: V0(VSR32)
+; PWR9LE-NEXT:    lxv vs13, 336(r1) # Vec Defs: VSL13(VSR13)
+; PWR9LE-NEXT:    lxv vs12, 352(r1) # Vec Defs: VSL12(VSR12)
+; PWR9LE-NEXT:    lxv vs11, 368(r1) # Vec Defs: VSL11(VSR11)
+; PWR9LE-NEXT:    lxv vs10, 384(r1) # Vec Defs: VSL10(VSR10)
+; PWR9LE-NEXT:    lxv vs9, 400(r1) # Vec Defs: VSL9(VSR9)
+; PWR9LE-NEXT:    lxv vs8, 416(r1) # Vec Defs: VSL8(VSR8)
+; PWR9LE-NEXT:    lxv vs7, 432(r1) # Vec Defs: VSL7(VSR7)
+; PWR9LE-NEXT:    lxv vs6, 448(r1) # Vec Defs: VSL6(VSR6)
+; PWR9LE-NEXT:    lxv vs5, 464(r1) # Vec Defs: VSL5(VSR5)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9LE-NEXT:    lxv vs4, 480(r1) # Vec Defs: VSL4(VSR4)
+; PWR9LE-NEXT:    lxv vs3, 496(r1) # Vec Defs: VSL3(VSR3)
+; PWR9LE-NEXT:    lxv vs2, 512(r1) # Vec Defs: VSL2(VSR2)
+; PWR9LE-NEXT:    lxv vs0, 528(r1) # Vec Defs: VSL0(VSR0)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9LE-NEXT:    xsadddp f1, f1, v3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF3(VSR3)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v5 # Vec Defs: V2(VSR34) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9LE-NEXT:    xsadddp f1, f1, v4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF4(VSR4)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v6 # Vec Defs: V2(VSR34) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR9LE-NEXT:    xsadddp f1, f1, v5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF5(VSR5)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v7 # Vec Defs: V2(VSR34) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR9LE-NEXT:    xsadddp f1, f1, v6 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF6(VSR6)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v8 # Vec Defs: V2(VSR34) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR9LE-NEXT:    xsadddp f1, f1, v7 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF7(VSR7)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v9 # Vec Defs: V2(VSR34) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR9LE-NEXT:    xsadddp f1, f1, v8 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF8(VSR8)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v10 # Vec Defs: V2(VSR34) Vec Uses: V10(VSR42)V10(VSR42)
+; PWR9LE-NEXT:    xsadddp f1, f1, v9 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF9(VSR9)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v11 # Vec Defs: V2(VSR34) Vec Uses: V11(VSR43)V11(VSR43)
+; PWR9LE-NEXT:    xsadddp f1, f1, v10 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF10(VSR10)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v12 # Vec Defs: V2(VSR34) Vec Uses: V12(VSR44)V12(VSR44)
+; PWR9LE-NEXT:    xsadddp f1, f1, v11 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF11(VSR11)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v13 # Vec Defs: V2(VSR34) Vec Uses: V13(VSR45)V13(VSR45)
+; PWR9LE-NEXT:    xsadddp f1, f1, v12 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF12(VSR12)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v18 # Vec Defs: V2(VSR34) Vec Uses: V18(VSR50)V18(VSR50)
+; PWR9LE-NEXT:    xsadddp f1, f1, v13 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF13(VSR13)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v17 # Vec Defs: V2(VSR34) Vec Uses: V17(VSR49)V17(VSR49)
+; PWR9LE-NEXT:    xsadddp f1, f1, v18 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF18(VSR18)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v16 # Vec Defs: V2(VSR34) Vec Uses: V16(VSR48)V16(VSR48)
+; PWR9LE-NEXT:    xsadddp f1, f1, v17 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF17(VSR17)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v15 # Vec Defs: V2(VSR34) Vec Uses: V15(VSR47)V15(VSR47)
+; PWR9LE-NEXT:    xsadddp f1, f1, v16 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF16(VSR16)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v14 # Vec Defs: V2(VSR34) Vec Uses: V14(VSR46)V14(VSR46)
+; PWR9LE-NEXT:    xsadddp f1, f1, v15 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF15(VSR15)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v1 # Vec Defs: V2(VSR34) Vec Uses: V1(VSR33)V1(VSR33)
+; PWR9LE-NEXT:    xsadddp f1, f1, v14 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF14(VSR14)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, v0 # Vec Defs: V2(VSR34) Vec Uses: V0(VSR32)V0(VSR32)
+; PWR9LE-NEXT:    xsadddp f1, f1, v1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF1(VSR1)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xxswapd v2, vs13 # Vec Defs: V2(VSR34) Vec Uses: VSL13(VSR13)VSL13(VSR13)
+; PWR9LE-NEXT:    xsadddp f1, f1, v0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF0(VSR0)
+; PWR9LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9LE-NEXT:    xsadddp f1, f1, f13 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F13(VSR13)
+; PWR9LE-NEXT:    xxswapd vs13, vs12 # Vec Defs: VSL13(VSR13) Vec Uses: VSL12(VSR12)VSL12(VSR12)
+; PWR9LE-NEXT:    xsadddp f1, f1, f13 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F13(VSR13)
+; PWR9LE-NEXT:    xsadddp f1, f1, f12 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F12(VSR12)
+; PWR9LE-NEXT:    xxswapd vs12, vs11 # Vec Defs: VSL12(VSR12) Vec Uses: VSL11(VSR11)VSL11(VSR11)
+; PWR9LE-NEXT:    xsadddp f1, f1, f12 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F12(VSR12)
+; PWR9LE-NEXT:    xsadddp f1, f1, f11 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F11(VSR11)
+; PWR9LE-NEXT:    xxswapd vs11, vs10 # Vec Defs: VSL11(VSR11) Vec Uses: VSL10(VSR10)VSL10(VSR10)
+; PWR9LE-NEXT:    xsadddp f1, f1, f11 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F11(VSR11)
+; PWR9LE-NEXT:    xsadddp f1, f1, f10 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F10(VSR10)
+; PWR9LE-NEXT:    xxswapd vs10, vs9 # Vec Defs: VSL10(VSR10) Vec Uses: VSL9(VSR9)VSL9(VSR9)
+; PWR9LE-NEXT:    xsadddp f1, f1, f10 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F10(VSR10)
+; PWR9LE-NEXT:    xsadddp f1, f1, f9 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F9(VSR9)
+; PWR9LE-NEXT:    xxswapd vs9, vs8 # Vec Defs: VSL9(VSR9) Vec Uses: VSL8(VSR8)VSL8(VSR8)
+; PWR9LE-NEXT:    xsadddp f1, f1, f9 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F9(VSR9)
+; PWR9LE-NEXT:    xsadddp f1, f1, f8 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F8(VSR8)
+; PWR9LE-NEXT:    xxswapd vs8, vs7 # Vec Defs: VSL8(VSR8) Vec Uses: VSL7(VSR7)VSL7(VSR7)
+; PWR9LE-NEXT:    xsadddp f1, f1, f8 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F8(VSR8)
+; PWR9LE-NEXT:    xsadddp f1, f1, f7 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F7(VSR7)
+; PWR9LE-NEXT:    xxswapd vs7, vs6 # Vec Defs: VSL7(VSR7) Vec Uses: VSL6(VSR6)VSL6(VSR6)
+; PWR9LE-NEXT:    xsadddp f1, f1, f7 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F7(VSR7)
+; PWR9LE-NEXT:    xsadddp f1, f1, f6 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F6(VSR6)
+; PWR9LE-NEXT:    xxswapd vs6, vs5 # Vec Defs: VSL6(VSR6) Vec Uses: VSL5(VSR5)VSL5(VSR5)
+; PWR9LE-NEXT:    xsadddp f1, f1, f6 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F6(VSR6)
+; PWR9LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9LE-NEXT:    xxswapd vs5, vs4 # Vec Defs: VSL5(VSR5) Vec Uses: VSL4(VSR4)VSL4(VSR4)
+; PWR9LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9LE-NEXT:    xsadddp f1, f1, f4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F4(VSR4)
+; PWR9LE-NEXT:    xxswapd vs4, vs3 # Vec Defs: VSL4(VSR4) Vec Uses: VSL3(VSR3)VSL3(VSR3)
+; PWR9LE-NEXT:    xsadddp f1, f1, f4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F4(VSR4)
+; PWR9LE-NEXT:    xsadddp f1, f1, f3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F3(VSR3)
+; PWR9LE-NEXT:    xxswapd vs3, vs2 # Vec Defs: VSL3(VSR3) Vec Uses: VSL2(VSR2)VSL2(VSR2)
+; PWR9LE-NEXT:    xsadddp f1, f1, f3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F3(VSR3)
+; PWR9LE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR9LE-NEXT:    xxswapd vs2, vs0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9LE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR9LE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v64f64_b:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v2
-; PWR9BE-NEXT:    lxv v18, 240(r1)
-; PWR9BE-NEXT:    lxv v17, 256(r1)
-; PWR9BE-NEXT:    lxv v16, 272(r1)
-; PWR9BE-NEXT:    lxv v15, 288(r1)
-; PWR9BE-NEXT:    lxv v14, 304(r1)
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v3
-; PWR9BE-NEXT:    lxv v1, 320(r1)
-; PWR9BE-NEXT:    lxv v0, 336(r1)
-; PWR9BE-NEXT:    lxv vs13, 352(r1)
-; PWR9BE-NEXT:    lxv vs12, 368(r1)
-; PWR9BE-NEXT:    lxv vs11, 384(r1)
-; PWR9BE-NEXT:    lxv vs10, 400(r1)
-; PWR9BE-NEXT:    lxv vs9, 416(r1)
-; PWR9BE-NEXT:    lxv vs8, 432(r1)
-; PWR9BE-NEXT:    lxv vs7, 448(r1)
-; PWR9BE-NEXT:    lxv vs6, 464(r1)
-; PWR9BE-NEXT:    lxv vs5, 480(r1)
-; PWR9BE-NEXT:    lxv vs4, 496(r1)
-; PWR9BE-NEXT:    lxv vs3, 512(r1)
-; PWR9BE-NEXT:    lxv vs2, 528(r1)
-; PWR9BE-NEXT:    lxv vs0, 544(r1)
-; PWR9BE-NEXT:    xsadddp f1, f1, v3
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v4
-; PWR9BE-NEXT:    xsadddp f1, f1, v4
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v5
-; PWR9BE-NEXT:    xsadddp f1, f1, v5
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v6
-; PWR9BE-NEXT:    xsadddp f1, f1, v6
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v7
-; PWR9BE-NEXT:    xsadddp f1, f1, v7
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v8
-; PWR9BE-NEXT:    xsadddp f1, f1, v8
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v9
-; PWR9BE-NEXT:    xsadddp f1, f1, v9
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v10
-; PWR9BE-NEXT:    xsadddp f1, f1, v10
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v11
-; PWR9BE-NEXT:    xsadddp f1, f1, v11
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v12
-; PWR9BE-NEXT:    xsadddp f1, f1, v12
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v13
-; PWR9BE-NEXT:    xsadddp f1, f1, v13
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v18
-; PWR9BE-NEXT:    xsadddp f1, f1, v18
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v17
-; PWR9BE-NEXT:    xsadddp f1, f1, v17
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v16
-; PWR9BE-NEXT:    xsadddp f1, f1, v16
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v15
-; PWR9BE-NEXT:    xsadddp f1, f1, v15
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v14
-; PWR9BE-NEXT:    xsadddp f1, f1, v14
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v1
-; PWR9BE-NEXT:    xsadddp f1, f1, v1
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xxswapd v2, v0
-; PWR9BE-NEXT:    xsadddp f1, f1, v0
-; PWR9BE-NEXT:    xsadddp f1, f1, v2
-; PWR9BE-NEXT:    xsadddp f1, f1, f13
-; PWR9BE-NEXT:    xxswapd vs13, vs13
-; PWR9BE-NEXT:    xsadddp f1, f1, f13
-; PWR9BE-NEXT:    xsadddp f1, f1, f12
-; PWR9BE-NEXT:    xxswapd vs12, vs12
-; PWR9BE-NEXT:    xsadddp f1, f1, f12
-; PWR9BE-NEXT:    xsadddp f1, f1, f11
-; PWR9BE-NEXT:    xxswapd vs11, vs11
-; PWR9BE-NEXT:    xsadddp f1, f1, f11
-; PWR9BE-NEXT:    xsadddp f1, f1, f10
-; PWR9BE-NEXT:    xxswapd vs10, vs10
-; PWR9BE-NEXT:    xsadddp f1, f1, f10
-; PWR9BE-NEXT:    xsadddp f1, f1, f9
-; PWR9BE-NEXT:    xxswapd vs9, vs9
-; PWR9BE-NEXT:    xsadddp f1, f1, f9
-; PWR9BE-NEXT:    xsadddp f1, f1, f8
-; PWR9BE-NEXT:    xxswapd vs8, vs8
-; PWR9BE-NEXT:    xsadddp f1, f1, f8
-; PWR9BE-NEXT:    xsadddp f1, f1, f7
-; PWR9BE-NEXT:    xxswapd vs7, vs7
-; PWR9BE-NEXT:    xsadddp f1, f1, f7
-; PWR9BE-NEXT:    xsadddp f1, f1, f6
-; PWR9BE-NEXT:    xxswapd vs6, vs6
-; PWR9BE-NEXT:    xsadddp f1, f1, f6
-; PWR9BE-NEXT:    xsadddp f1, f1, f5
-; PWR9BE-NEXT:    xxswapd vs5, vs5
-; PWR9BE-NEXT:    xsadddp f1, f1, f5
-; PWR9BE-NEXT:    xsadddp f1, f1, f4
-; PWR9BE-NEXT:    xxswapd vs4, vs4
-; PWR9BE-NEXT:    xsadddp f1, f1, f4
-; PWR9BE-NEXT:    xsadddp f1, f1, f3
-; PWR9BE-NEXT:    xxswapd vs3, vs3
-; PWR9BE-NEXT:    xsadddp f1, f1, f3
-; PWR9BE-NEXT:    xsadddp f1, f1, f2
-; PWR9BE-NEXT:    xxswapd vs2, vs2
-; PWR9BE-NEXT:    xsadddp f1, f1, f2
-; PWR9BE-NEXT:    xsadddp f1, f1, f0
-; PWR9BE-NEXT:    xxswapd vs0, vs0
-; PWR9BE-NEXT:    xsadddp f1, f1, f0
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR9BE-NEXT:    lxv v18, 240(r1) # Vec Defs: V18(VSR50)
+; PWR9BE-NEXT:    lxv v17, 256(r1) # Vec Defs: V17(VSR49)
+; PWR9BE-NEXT:    lxv v16, 272(r1) # Vec Defs: V16(VSR48)
+; PWR9BE-NEXT:    lxv v15, 288(r1) # Vec Defs: V15(VSR47)
+; PWR9BE-NEXT:    lxv v14, 304(r1) # Vec Defs: V14(VSR46)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR9BE-NEXT:    lxv v1, 320(r1) # Vec Defs: V1(VSR33)
+; PWR9BE-NEXT:    lxv v0, 336(r1) # Vec Defs: V0(VSR32)
+; PWR9BE-NEXT:    lxv vs13, 352(r1) # Vec Defs: VSL13(VSR13)
+; PWR9BE-NEXT:    lxv vs12, 368(r1) # Vec Defs: VSL12(VSR12)
+; PWR9BE-NEXT:    lxv vs11, 384(r1) # Vec Defs: VSL11(VSR11)
+; PWR9BE-NEXT:    lxv vs10, 400(r1) # Vec Defs: VSL10(VSR10)
+; PWR9BE-NEXT:    lxv vs9, 416(r1) # Vec Defs: VSL9(VSR9)
+; PWR9BE-NEXT:    lxv vs8, 432(r1) # Vec Defs: VSL8(VSR8)
+; PWR9BE-NEXT:    lxv vs7, 448(r1) # Vec Defs: VSL7(VSR7)
+; PWR9BE-NEXT:    lxv vs6, 464(r1) # Vec Defs: VSL6(VSR6)
+; PWR9BE-NEXT:    lxv vs5, 480(r1) # Vec Defs: VSL5(VSR5)
+; PWR9BE-NEXT:    lxv vs4, 496(r1) # Vec Defs: VSL4(VSR4)
+; PWR9BE-NEXT:    lxv vs3, 512(r1) # Vec Defs: VSL3(VSR3)
+; PWR9BE-NEXT:    lxv vs2, 528(r1) # Vec Defs: VSL2(VSR2)
+; PWR9BE-NEXT:    lxv vs0, 544(r1) # Vec Defs: VSL0(VSR0)
+; PWR9BE-NEXT:    xsadddp f1, f1, v3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF3(VSR3)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR9BE-NEXT:    xsadddp f1, f1, v4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF4(VSR4)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v5 # Vec Defs: V2(VSR34) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR9BE-NEXT:    xsadddp f1, f1, v5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF5(VSR5)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v6 # Vec Defs: V2(VSR34) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR9BE-NEXT:    xsadddp f1, f1, v6 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF6(VSR6)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v7 # Vec Defs: V2(VSR34) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR9BE-NEXT:    xsadddp f1, f1, v7 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF7(VSR7)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v8 # Vec Defs: V2(VSR34) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR9BE-NEXT:    xsadddp f1, f1, v8 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF8(VSR8)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v9 # Vec Defs: V2(VSR34) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR9BE-NEXT:    xsadddp f1, f1, v9 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF9(VSR9)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v10 # Vec Defs: V2(VSR34) Vec Uses: V10(VSR42)V10(VSR42)
+; PWR9BE-NEXT:    xsadddp f1, f1, v10 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF10(VSR10)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v11 # Vec Defs: V2(VSR34) Vec Uses: V11(VSR43)V11(VSR43)
+; PWR9BE-NEXT:    xsadddp f1, f1, v11 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF11(VSR11)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v12 # Vec Defs: V2(VSR34) Vec Uses: V12(VSR44)V12(VSR44)
+; PWR9BE-NEXT:    xsadddp f1, f1, v12 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF12(VSR12)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v13 # Vec Defs: V2(VSR34) Vec Uses: V13(VSR45)V13(VSR45)
+; PWR9BE-NEXT:    xsadddp f1, f1, v13 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF13(VSR13)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v18 # Vec Defs: V2(VSR34) Vec Uses: V18(VSR50)V18(VSR50)
+; PWR9BE-NEXT:    xsadddp f1, f1, v18 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF18(VSR18)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v17 # Vec Defs: V2(VSR34) Vec Uses: V17(VSR49)V17(VSR49)
+; PWR9BE-NEXT:    xsadddp f1, f1, v17 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF17(VSR17)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v16 # Vec Defs: V2(VSR34) Vec Uses: V16(VSR48)V16(VSR48)
+; PWR9BE-NEXT:    xsadddp f1, f1, v16 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF16(VSR16)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v15 # Vec Defs: V2(VSR34) Vec Uses: V15(VSR47)V15(VSR47)
+; PWR9BE-NEXT:    xsadddp f1, f1, v15 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF15(VSR15)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v14 # Vec Defs: V2(VSR34) Vec Uses: V14(VSR46)V14(VSR46)
+; PWR9BE-NEXT:    xsadddp f1, f1, v14 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF14(VSR14)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v1 # Vec Defs: V2(VSR34) Vec Uses: V1(VSR33)V1(VSR33)
+; PWR9BE-NEXT:    xsadddp f1, f1, v1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF1(VSR1)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xxswapd v2, v0 # Vec Defs: V2(VSR34) Vec Uses: V0(VSR32)V0(VSR32)
+; PWR9BE-NEXT:    xsadddp f1, f1, v0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF0(VSR0)
+; PWR9BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR9BE-NEXT:    xsadddp f1, f1, f13 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F13(VSR13)
+; PWR9BE-NEXT:    xxswapd vs13, vs13 # Vec Defs: VSL13(VSR13) Vec Uses: VSL13(VSR13)VSL13(VSR13)
+; PWR9BE-NEXT:    xsadddp f1, f1, f13 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F13(VSR13)
+; PWR9BE-NEXT:    xsadddp f1, f1, f12 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F12(VSR12)
+; PWR9BE-NEXT:    xxswapd vs12, vs12 # Vec Defs: VSL12(VSR12) Vec Uses: VSL12(VSR12)VSL12(VSR12)
+; PWR9BE-NEXT:    xsadddp f1, f1, f12 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F12(VSR12)
+; PWR9BE-NEXT:    xsadddp f1, f1, f11 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F11(VSR11)
+; PWR9BE-NEXT:    xxswapd vs11, vs11 # Vec Defs: VSL11(VSR11) Vec Uses: VSL11(VSR11)VSL11(VSR11)
+; PWR9BE-NEXT:    xsadddp f1, f1, f11 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F11(VSR11)
+; PWR9BE-NEXT:    xsadddp f1, f1, f10 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F10(VSR10)
+; PWR9BE-NEXT:    xxswapd vs10, vs10 # Vec Defs: VSL10(VSR10) Vec Uses: VSL10(VSR10)VSL10(VSR10)
+; PWR9BE-NEXT:    xsadddp f1, f1, f10 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F10(VSR10)
+; PWR9BE-NEXT:    xsadddp f1, f1, f9 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F9(VSR9)
+; PWR9BE-NEXT:    xxswapd vs9, vs9 # Vec Defs: VSL9(VSR9) Vec Uses: VSL9(VSR9)VSL9(VSR9)
+; PWR9BE-NEXT:    xsadddp f1, f1, f9 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F9(VSR9)
+; PWR9BE-NEXT:    xsadddp f1, f1, f8 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F8(VSR8)
+; PWR9BE-NEXT:    xxswapd vs8, vs8 # Vec Defs: VSL8(VSR8) Vec Uses: VSL8(VSR8)VSL8(VSR8)
+; PWR9BE-NEXT:    xsadddp f1, f1, f8 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F8(VSR8)
+; PWR9BE-NEXT:    xsadddp f1, f1, f7 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F7(VSR7)
+; PWR9BE-NEXT:    xxswapd vs7, vs7 # Vec Defs: VSL7(VSR7) Vec Uses: VSL7(VSR7)VSL7(VSR7)
+; PWR9BE-NEXT:    xsadddp f1, f1, f7 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F7(VSR7)
+; PWR9BE-NEXT:    xsadddp f1, f1, f6 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F6(VSR6)
+; PWR9BE-NEXT:    xxswapd vs6, vs6 # Vec Defs: VSL6(VSR6) Vec Uses: VSL6(VSR6)VSL6(VSR6)
+; PWR9BE-NEXT:    xsadddp f1, f1, f6 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F6(VSR6)
+; PWR9BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9BE-NEXT:    xxswapd vs5, vs5 # Vec Defs: VSL5(VSR5) Vec Uses: VSL5(VSR5)VSL5(VSR5)
+; PWR9BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR9BE-NEXT:    xsadddp f1, f1, f4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F4(VSR4)
+; PWR9BE-NEXT:    xxswapd vs4, vs4 # Vec Defs: VSL4(VSR4) Vec Uses: VSL4(VSR4)VSL4(VSR4)
+; PWR9BE-NEXT:    xsadddp f1, f1, f4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F4(VSR4)
+; PWR9BE-NEXT:    xsadddp f1, f1, f3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F3(VSR3)
+; PWR9BE-NEXT:    xxswapd vs3, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: VSL3(VSR3)VSL3(VSR3)
+; PWR9BE-NEXT:    xsadddp f1, f1, f3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F3(VSR3)
+; PWR9BE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR9BE-NEXT:    xxswapd vs2, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL2(VSR2)VSL2(VSR2)
+; PWR9BE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR9BE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR9BE-NEXT:    xxswapd vs0, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9BE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v64f64_b:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    xxswapd v19, v2
-; PWR10LE-NEXT:    lxv v18, 224(r1)
-; PWR10LE-NEXT:    lxv v17, 240(r1)
-; PWR10LE-NEXT:    xsadddp f1, f1, v19
-; PWR10LE-NEXT:    lxv v16, 256(r1)
-; PWR10LE-NEXT:    lxv v15, 272(r1)
-; PWR10LE-NEXT:    lxv v14, 288(r1)
-; PWR10LE-NEXT:    lxv v1, 304(r1)
-; PWR10LE-NEXT:    lxv v0, 320(r1)
-; PWR10LE-NEXT:    lxv vs13, 336(r1)
-; PWR10LE-NEXT:    lxv vs12, 352(r1)
-; PWR10LE-NEXT:    lxv vs11, 368(r1)
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v3
-; PWR10LE-NEXT:    lxv vs10, 384(r1)
-; PWR10LE-NEXT:    lxv vs9, 400(r1)
-; PWR10LE-NEXT:    lxv vs8, 416(r1)
-; PWR10LE-NEXT:    lxv vs7, 432(r1)
-; PWR10LE-NEXT:    lxv vs6, 448(r1)
-; PWR10LE-NEXT:    lxv vs5, 464(r1)
-; PWR10LE-NEXT:    lxv vs4, 480(r1)
-; PWR10LE-NEXT:    lxv vs3, 496(r1)
-; PWR10LE-NEXT:    lxv vs2, 512(r1)
-; PWR10LE-NEXT:    lxv vs0, 528(r1)
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v4
-; PWR10LE-NEXT:    xsadddp f1, f1, v3
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v5
-; PWR10LE-NEXT:    xsadddp f1, f1, v4
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v6
-; PWR10LE-NEXT:    xsadddp f1, f1, v5
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v7
-; PWR10LE-NEXT:    xsadddp f1, f1, v6
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v8
-; PWR10LE-NEXT:    xsadddp f1, f1, v7
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v9
-; PWR10LE-NEXT:    xsadddp f1, f1, v8
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v10
-; PWR10LE-NEXT:    xsadddp f1, f1, v9
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v11
-; PWR10LE-NEXT:    xsadddp f1, f1, v10
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v12
-; PWR10LE-NEXT:    xsadddp f1, f1, v11
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v13
-; PWR10LE-NEXT:    xsadddp f1, f1, v12
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v18
-; PWR10LE-NEXT:    xsadddp f1, f1, v13
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v17
-; PWR10LE-NEXT:    xsadddp f1, f1, v18
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v16
-; PWR10LE-NEXT:    xsadddp f1, f1, v17
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v15
-; PWR10LE-NEXT:    xsadddp f1, f1, v16
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v14
-; PWR10LE-NEXT:    xsadddp f1, f1, v15
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v1
-; PWR10LE-NEXT:    xsadddp f1, f1, v14
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, v0
-; PWR10LE-NEXT:    xsadddp f1, f1, v1
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xxswapd v2, vs13
-; PWR10LE-NEXT:    xsadddp f1, f1, v0
-; PWR10LE-NEXT:    xsadddp f1, f1, v2
-; PWR10LE-NEXT:    xsadddp f1, f1, f13
-; PWR10LE-NEXT:    xxswapd vs13, vs12
-; PWR10LE-NEXT:    xsadddp f1, f1, f13
-; PWR10LE-NEXT:    xsadddp f1, f1, f12
-; PWR10LE-NEXT:    xxswapd vs12, vs11
-; PWR10LE-NEXT:    xsadddp f1, f1, f12
-; PWR10LE-NEXT:    xsadddp f1, f1, f11
-; PWR10LE-NEXT:    xxswapd vs11, vs10
-; PWR10LE-NEXT:    xsadddp f1, f1, f11
-; PWR10LE-NEXT:    xsadddp f1, f1, f10
-; PWR10LE-NEXT:    xxswapd vs10, vs9
-; PWR10LE-NEXT:    xsadddp f1, f1, f10
-; PWR10LE-NEXT:    xsadddp f1, f1, f9
-; PWR10LE-NEXT:    xxswapd vs9, vs8
-; PWR10LE-NEXT:    xsadddp f1, f1, f9
-; PWR10LE-NEXT:    xsadddp f1, f1, f8
-; PWR10LE-NEXT:    xxswapd vs8, vs7
-; PWR10LE-NEXT:    xsadddp f1, f1, f8
-; PWR10LE-NEXT:    xsadddp f1, f1, f7
-; PWR10LE-NEXT:    xxswapd vs7, vs6
-; PWR10LE-NEXT:    xsadddp f1, f1, f7
-; PWR10LE-NEXT:    xsadddp f1, f1, f6
-; PWR10LE-NEXT:    xxswapd vs6, vs5
-; PWR10LE-NEXT:    xsadddp f1, f1, f6
-; PWR10LE-NEXT:    xsadddp f1, f1, f5
-; PWR10LE-NEXT:    xxswapd vs5, vs4
-; PWR10LE-NEXT:    xsadddp f1, f1, f5
-; PWR10LE-NEXT:    xsadddp f1, f1, f4
-; PWR10LE-NEXT:    xxswapd vs4, vs3
-; PWR10LE-NEXT:    xsadddp f1, f1, f4
-; PWR10LE-NEXT:    xsadddp f1, f1, f3
-; PWR10LE-NEXT:    xxswapd vs3, vs2
-; PWR10LE-NEXT:    xsadddp f1, f1, f3
-; PWR10LE-NEXT:    xsadddp f1, f1, f2
-; PWR10LE-NEXT:    xxswapd vs2, vs0
-; PWR10LE-NEXT:    xsadddp f1, f1, f2
-; PWR10LE-NEXT:    xsadddp f1, f1, f0
+; PWR10LE-NEXT:    xxswapd v19, v2 # Vec Defs: V19(VSR51) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10LE-NEXT:    lxv v18, 224(r1) # Vec Defs: V18(VSR50)
+; PWR10LE-NEXT:    lxv v17, 240(r1) # Vec Defs: V17(VSR49)
+; PWR10LE-NEXT:    xsadddp f1, f1, v19 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF19(VSR19)
+; PWR10LE-NEXT:    lxv v16, 256(r1) # Vec Defs: V16(VSR48)
+; PWR10LE-NEXT:    lxv v15, 272(r1) # Vec Defs: V15(VSR47)
+; PWR10LE-NEXT:    lxv v14, 288(r1) # Vec Defs: V14(VSR46)
+; PWR10LE-NEXT:    lxv v1, 304(r1) # Vec Defs: V1(VSR33)
+; PWR10LE-NEXT:    lxv v0, 320(r1) # Vec Defs: V0(VSR32)
+; PWR10LE-NEXT:    lxv vs13, 336(r1) # Vec Defs: VSL13(VSR13)
+; PWR10LE-NEXT:    lxv vs12, 352(r1) # Vec Defs: VSL12(VSR12)
+; PWR10LE-NEXT:    lxv vs11, 368(r1) # Vec Defs: VSL11(VSR11)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10LE-NEXT:    lxv vs10, 384(r1) # Vec Defs: VSL10(VSR10)
+; PWR10LE-NEXT:    lxv vs9, 400(r1) # Vec Defs: VSL9(VSR9)
+; PWR10LE-NEXT:    lxv vs8, 416(r1) # Vec Defs: VSL8(VSR8)
+; PWR10LE-NEXT:    lxv vs7, 432(r1) # Vec Defs: VSL7(VSR7)
+; PWR10LE-NEXT:    lxv vs6, 448(r1) # Vec Defs: VSL6(VSR6)
+; PWR10LE-NEXT:    lxv vs5, 464(r1) # Vec Defs: VSL5(VSR5)
+; PWR10LE-NEXT:    lxv vs4, 480(r1) # Vec Defs: VSL4(VSR4)
+; PWR10LE-NEXT:    lxv vs3, 496(r1) # Vec Defs: VSL3(VSR3)
+; PWR10LE-NEXT:    lxv vs2, 512(r1) # Vec Defs: VSL2(VSR2)
+; PWR10LE-NEXT:    lxv vs0, 528(r1) # Vec Defs: VSL0(VSR0)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10LE-NEXT:    xsadddp f1, f1, v3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF3(VSR3)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v5 # Vec Defs: V2(VSR34) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10LE-NEXT:    xsadddp f1, f1, v4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF4(VSR4)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v6 # Vec Defs: V2(VSR34) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR10LE-NEXT:    xsadddp f1, f1, v5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF5(VSR5)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v7 # Vec Defs: V2(VSR34) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR10LE-NEXT:    xsadddp f1, f1, v6 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF6(VSR6)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v8 # Vec Defs: V2(VSR34) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR10LE-NEXT:    xsadddp f1, f1, v7 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF7(VSR7)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v9 # Vec Defs: V2(VSR34) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR10LE-NEXT:    xsadddp f1, f1, v8 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF8(VSR8)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v10 # Vec Defs: V2(VSR34) Vec Uses: V10(VSR42)V10(VSR42)
+; PWR10LE-NEXT:    xsadddp f1, f1, v9 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF9(VSR9)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v11 # Vec Defs: V2(VSR34) Vec Uses: V11(VSR43)V11(VSR43)
+; PWR10LE-NEXT:    xsadddp f1, f1, v10 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF10(VSR10)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v12 # Vec Defs: V2(VSR34) Vec Uses: V12(VSR44)V12(VSR44)
+; PWR10LE-NEXT:    xsadddp f1, f1, v11 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF11(VSR11)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v13 # Vec Defs: V2(VSR34) Vec Uses: V13(VSR45)V13(VSR45)
+; PWR10LE-NEXT:    xsadddp f1, f1, v12 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF12(VSR12)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v18 # Vec Defs: V2(VSR34) Vec Uses: V18(VSR50)V18(VSR50)
+; PWR10LE-NEXT:    xsadddp f1, f1, v13 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF13(VSR13)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v17 # Vec Defs: V2(VSR34) Vec Uses: V17(VSR49)V17(VSR49)
+; PWR10LE-NEXT:    xsadddp f1, f1, v18 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF18(VSR18)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v16 # Vec Defs: V2(VSR34) Vec Uses: V16(VSR48)V16(VSR48)
+; PWR10LE-NEXT:    xsadddp f1, f1, v17 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF17(VSR17)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v15 # Vec Defs: V2(VSR34) Vec Uses: V15(VSR47)V15(VSR47)
+; PWR10LE-NEXT:    xsadddp f1, f1, v16 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF16(VSR16)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v14 # Vec Defs: V2(VSR34) Vec Uses: V14(VSR46)V14(VSR46)
+; PWR10LE-NEXT:    xsadddp f1, f1, v15 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF15(VSR15)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v1 # Vec Defs: V2(VSR34) Vec Uses: V1(VSR33)V1(VSR33)
+; PWR10LE-NEXT:    xsadddp f1, f1, v14 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF14(VSR14)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, v0 # Vec Defs: V2(VSR34) Vec Uses: V0(VSR32)V0(VSR32)
+; PWR10LE-NEXT:    xsadddp f1, f1, v1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF1(VSR1)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xxswapd v2, vs13 # Vec Defs: V2(VSR34) Vec Uses: VSL13(VSR13)VSL13(VSR13)
+; PWR10LE-NEXT:    xsadddp f1, f1, v0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF0(VSR0)
+; PWR10LE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10LE-NEXT:    xsadddp f1, f1, f13 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F13(VSR13)
+; PWR10LE-NEXT:    xxswapd vs13, vs12 # Vec Defs: VSL13(VSR13) Vec Uses: VSL12(VSR12)VSL12(VSR12)
+; PWR10LE-NEXT:    xsadddp f1, f1, f13 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F13(VSR13)
+; PWR10LE-NEXT:    xsadddp f1, f1, f12 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F12(VSR12)
+; PWR10LE-NEXT:    xxswapd vs12, vs11 # Vec Defs: VSL12(VSR12) Vec Uses: VSL11(VSR11)VSL11(VSR11)
+; PWR10LE-NEXT:    xsadddp f1, f1, f12 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F12(VSR12)
+; PWR10LE-NEXT:    xsadddp f1, f1, f11 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F11(VSR11)
+; PWR10LE-NEXT:    xxswapd vs11, vs10 # Vec Defs: VSL11(VSR11) Vec Uses: VSL10(VSR10)VSL10(VSR10)
+; PWR10LE-NEXT:    xsadddp f1, f1, f11 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F11(VSR11)
+; PWR10LE-NEXT:    xsadddp f1, f1, f10 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F10(VSR10)
+; PWR10LE-NEXT:    xxswapd vs10, vs9 # Vec Defs: VSL10(VSR10) Vec Uses: VSL9(VSR9)VSL9(VSR9)
+; PWR10LE-NEXT:    xsadddp f1, f1, f10 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F10(VSR10)
+; PWR10LE-NEXT:    xsadddp f1, f1, f9 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F9(VSR9)
+; PWR10LE-NEXT:    xxswapd vs9, vs8 # Vec Defs: VSL9(VSR9) Vec Uses: VSL8(VSR8)VSL8(VSR8)
+; PWR10LE-NEXT:    xsadddp f1, f1, f9 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F9(VSR9)
+; PWR10LE-NEXT:    xsadddp f1, f1, f8 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F8(VSR8)
+; PWR10LE-NEXT:    xxswapd vs8, vs7 # Vec Defs: VSL8(VSR8) Vec Uses: VSL7(VSR7)VSL7(VSR7)
+; PWR10LE-NEXT:    xsadddp f1, f1, f8 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F8(VSR8)
+; PWR10LE-NEXT:    xsadddp f1, f1, f7 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F7(VSR7)
+; PWR10LE-NEXT:    xxswapd vs7, vs6 # Vec Defs: VSL7(VSR7) Vec Uses: VSL6(VSR6)VSL6(VSR6)
+; PWR10LE-NEXT:    xsadddp f1, f1, f7 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F7(VSR7)
+; PWR10LE-NEXT:    xsadddp f1, f1, f6 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F6(VSR6)
+; PWR10LE-NEXT:    xxswapd vs6, vs5 # Vec Defs: VSL6(VSR6) Vec Uses: VSL5(VSR5)VSL5(VSR5)
+; PWR10LE-NEXT:    xsadddp f1, f1, f6 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F6(VSR6)
+; PWR10LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10LE-NEXT:    xxswapd vs5, vs4 # Vec Defs: VSL5(VSR5) Vec Uses: VSL4(VSR4)VSL4(VSR4)
+; PWR10LE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10LE-NEXT:    xsadddp f1, f1, f4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F4(VSR4)
+; PWR10LE-NEXT:    xxswapd vs4, vs3 # Vec Defs: VSL4(VSR4) Vec Uses: VSL3(VSR3)VSL3(VSR3)
+; PWR10LE-NEXT:    xsadddp f1, f1, f4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F4(VSR4)
+; PWR10LE-NEXT:    xsadddp f1, f1, f3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F3(VSR3)
+; PWR10LE-NEXT:    xxswapd vs3, vs2 # Vec Defs: VSL3(VSR3) Vec Uses: VSL2(VSR2)VSL2(VSR2)
+; PWR10LE-NEXT:    xsadddp f1, f1, f3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F3(VSR3)
+; PWR10LE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR10LE-NEXT:    xxswapd vs2, vs0 # Vec Defs: VSL2(VSR2) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10LE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR10LE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v64f64_b:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v2
-; PWR10BE-NEXT:    lxv v18, 240(r1)
-; PWR10BE-NEXT:    lxv v17, 256(r1)
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v3
-; PWR10BE-NEXT:    lxv v16, 272(r1)
-; PWR10BE-NEXT:    lxv v15, 288(r1)
-; PWR10BE-NEXT:    lxv v14, 304(r1)
-; PWR10BE-NEXT:    lxv v1, 320(r1)
-; PWR10BE-NEXT:    lxv v0, 336(r1)
-; PWR10BE-NEXT:    lxv vs13, 352(r1)
-; PWR10BE-NEXT:    lxv vs12, 368(r1)
-; PWR10BE-NEXT:    lxv vs11, 384(r1)
-; PWR10BE-NEXT:    lxv vs10, 400(r1)
-; PWR10BE-NEXT:    lxv vs9, 416(r1)
-; PWR10BE-NEXT:    xsadddp f1, f1, v3
-; PWR10BE-NEXT:    lxv vs8, 432(r1)
-; PWR10BE-NEXT:    lxv vs7, 448(r1)
-; PWR10BE-NEXT:    lxv vs6, 464(r1)
-; PWR10BE-NEXT:    lxv vs5, 480(r1)
-; PWR10BE-NEXT:    lxv vs4, 496(r1)
-; PWR10BE-NEXT:    lxv vs3, 512(r1)
-; PWR10BE-NEXT:    lxv vs2, 528(r1)
-; PWR10BE-NEXT:    lxv vs0, 544(r1)
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v4
-; PWR10BE-NEXT:    xsadddp f1, f1, v4
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v5
-; PWR10BE-NEXT:    xsadddp f1, f1, v5
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v6
-; PWR10BE-NEXT:    xsadddp f1, f1, v6
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v7
-; PWR10BE-NEXT:    xsadddp f1, f1, v7
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v8
-; PWR10BE-NEXT:    xsadddp f1, f1, v8
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v9
-; PWR10BE-NEXT:    xsadddp f1, f1, v9
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v10
-; PWR10BE-NEXT:    xsadddp f1, f1, v10
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v11
-; PWR10BE-NEXT:    xsadddp f1, f1, v11
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v12
-; PWR10BE-NEXT:    xsadddp f1, f1, v12
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v13
-; PWR10BE-NEXT:    xsadddp f1, f1, v13
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v18
-; PWR10BE-NEXT:    xsadddp f1, f1, v18
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v17
-; PWR10BE-NEXT:    xsadddp f1, f1, v17
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v16
-; PWR10BE-NEXT:    xsadddp f1, f1, v16
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v15
-; PWR10BE-NEXT:    xsadddp f1, f1, v15
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v14
-; PWR10BE-NEXT:    xsadddp f1, f1, v14
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v1
-; PWR10BE-NEXT:    xsadddp f1, f1, v1
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xxswapd v2, v0
-; PWR10BE-NEXT:    xsadddp f1, f1, v0
-; PWR10BE-NEXT:    xsadddp f1, f1, v2
-; PWR10BE-NEXT:    xsadddp f1, f1, f13
-; PWR10BE-NEXT:    xxswapd vs13, vs13
-; PWR10BE-NEXT:    xsadddp f1, f1, f13
-; PWR10BE-NEXT:    xsadddp f1, f1, f12
-; PWR10BE-NEXT:    xxswapd vs12, vs12
-; PWR10BE-NEXT:    xsadddp f1, f1, f12
-; PWR10BE-NEXT:    xsadddp f1, f1, f11
-; PWR10BE-NEXT:    xxswapd vs11, vs11
-; PWR10BE-NEXT:    xsadddp f1, f1, f11
-; PWR10BE-NEXT:    xsadddp f1, f1, f10
-; PWR10BE-NEXT:    xxswapd vs10, vs10
-; PWR10BE-NEXT:    xsadddp f1, f1, f10
-; PWR10BE-NEXT:    xsadddp f1, f1, f9
-; PWR10BE-NEXT:    xxswapd vs9, vs9
-; PWR10BE-NEXT:    xsadddp f1, f1, f9
-; PWR10BE-NEXT:    xsadddp f1, f1, f8
-; PWR10BE-NEXT:    xxswapd vs8, vs8
-; PWR10BE-NEXT:    xsadddp f1, f1, f8
-; PWR10BE-NEXT:    xsadddp f1, f1, f7
-; PWR10BE-NEXT:    xxswapd vs7, vs7
-; PWR10BE-NEXT:    xsadddp f1, f1, f7
-; PWR10BE-NEXT:    xsadddp f1, f1, f6
-; PWR10BE-NEXT:    xxswapd vs6, vs6
-; PWR10BE-NEXT:    xsadddp f1, f1, f6
-; PWR10BE-NEXT:    xsadddp f1, f1, f5
-; PWR10BE-NEXT:    xxswapd vs5, vs5
-; PWR10BE-NEXT:    xsadddp f1, f1, f5
-; PWR10BE-NEXT:    xsadddp f1, f1, f4
-; PWR10BE-NEXT:    xxswapd vs4, vs4
-; PWR10BE-NEXT:    xsadddp f1, f1, f4
-; PWR10BE-NEXT:    xsadddp f1, f1, f3
-; PWR10BE-NEXT:    xxswapd vs3, vs3
-; PWR10BE-NEXT:    xsadddp f1, f1, f3
-; PWR10BE-NEXT:    xsadddp f1, f1, f2
-; PWR10BE-NEXT:    xxswapd vs2, vs2
-; PWR10BE-NEXT:    xsadddp f1, f1, f2
-; PWR10BE-NEXT:    xsadddp f1, f1, f0
-; PWR10BE-NEXT:    xxswapd vs0, vs0
-; PWR10BE-NEXT:    xsadddp f1, f1, f0
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; PWR10BE-NEXT:    lxv v18, 240(r1) # Vec Defs: V18(VSR50)
+; PWR10BE-NEXT:    lxv v17, 256(r1) # Vec Defs: V17(VSR49)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)
+; PWR10BE-NEXT:    lxv v16, 272(r1) # Vec Defs: V16(VSR48)
+; PWR10BE-NEXT:    lxv v15, 288(r1) # Vec Defs: V15(VSR47)
+; PWR10BE-NEXT:    lxv v14, 304(r1) # Vec Defs: V14(VSR46)
+; PWR10BE-NEXT:    lxv v1, 320(r1) # Vec Defs: V1(VSR33)
+; PWR10BE-NEXT:    lxv v0, 336(r1) # Vec Defs: V0(VSR32)
+; PWR10BE-NEXT:    lxv vs13, 352(r1) # Vec Defs: VSL13(VSR13)
+; PWR10BE-NEXT:    lxv vs12, 368(r1) # Vec Defs: VSL12(VSR12)
+; PWR10BE-NEXT:    lxv vs11, 384(r1) # Vec Defs: VSL11(VSR11)
+; PWR10BE-NEXT:    lxv vs10, 400(r1) # Vec Defs: VSL10(VSR10)
+; PWR10BE-NEXT:    lxv vs9, 416(r1) # Vec Defs: VSL9(VSR9)
+; PWR10BE-NEXT:    xsadddp f1, f1, v3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF3(VSR3)
+; PWR10BE-NEXT:    lxv vs8, 432(r1) # Vec Defs: VSL8(VSR8)
+; PWR10BE-NEXT:    lxv vs7, 448(r1) # Vec Defs: VSL7(VSR7)
+; PWR10BE-NEXT:    lxv vs6, 464(r1) # Vec Defs: VSL6(VSR6)
+; PWR10BE-NEXT:    lxv vs5, 480(r1) # Vec Defs: VSL5(VSR5)
+; PWR10BE-NEXT:    lxv vs4, 496(r1) # Vec Defs: VSL4(VSR4)
+; PWR10BE-NEXT:    lxv vs3, 512(r1) # Vec Defs: VSL3(VSR3)
+; PWR10BE-NEXT:    lxv vs2, 528(r1) # Vec Defs: VSL2(VSR2)
+; PWR10BE-NEXT:    lxv vs0, 544(r1) # Vec Defs: VSL0(VSR0)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V4(VSR36)
+; PWR10BE-NEXT:    xsadddp f1, f1, v4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF4(VSR4)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v5 # Vec Defs: V2(VSR34) Vec Uses: V5(VSR37)V5(VSR37)
+; PWR10BE-NEXT:    xsadddp f1, f1, v5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF5(VSR5)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v6 # Vec Defs: V2(VSR34) Vec Uses: V6(VSR38)V6(VSR38)
+; PWR10BE-NEXT:    xsadddp f1, f1, v6 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF6(VSR6)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v7 # Vec Defs: V2(VSR34) Vec Uses: V7(VSR39)V7(VSR39)
+; PWR10BE-NEXT:    xsadddp f1, f1, v7 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF7(VSR7)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v8 # Vec Defs: V2(VSR34) Vec Uses: V8(VSR40)V8(VSR40)
+; PWR10BE-NEXT:    xsadddp f1, f1, v8 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF8(VSR8)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v9 # Vec Defs: V2(VSR34) Vec Uses: V9(VSR41)V9(VSR41)
+; PWR10BE-NEXT:    xsadddp f1, f1, v9 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF9(VSR9)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v10 # Vec Defs: V2(VSR34) Vec Uses: V10(VSR42)V10(VSR42)
+; PWR10BE-NEXT:    xsadddp f1, f1, v10 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF10(VSR10)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v11 # Vec Defs: V2(VSR34) Vec Uses: V11(VSR43)V11(VSR43)
+; PWR10BE-NEXT:    xsadddp f1, f1, v11 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF11(VSR11)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v12 # Vec Defs: V2(VSR34) Vec Uses: V12(VSR44)V12(VSR44)
+; PWR10BE-NEXT:    xsadddp f1, f1, v12 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF12(VSR12)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v13 # Vec Defs: V2(VSR34) Vec Uses: V13(VSR45)V13(VSR45)
+; PWR10BE-NEXT:    xsadddp f1, f1, v13 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF13(VSR13)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v18 # Vec Defs: V2(VSR34) Vec Uses: V18(VSR50)V18(VSR50)
+; PWR10BE-NEXT:    xsadddp f1, f1, v18 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF18(VSR18)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v17 # Vec Defs: V2(VSR34) Vec Uses: V17(VSR49)V17(VSR49)
+; PWR10BE-NEXT:    xsadddp f1, f1, v17 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF17(VSR17)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v16 # Vec Defs: V2(VSR34) Vec Uses: V16(VSR48)V16(VSR48)
+; PWR10BE-NEXT:    xsadddp f1, f1, v16 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF16(VSR16)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v15 # Vec Defs: V2(VSR34) Vec Uses: V15(VSR47)V15(VSR47)
+; PWR10BE-NEXT:    xsadddp f1, f1, v15 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF15(VSR15)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v14 # Vec Defs: V2(VSR34) Vec Uses: V14(VSR46)V14(VSR46)
+; PWR10BE-NEXT:    xsadddp f1, f1, v14 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF14(VSR14)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v1 # Vec Defs: V2(VSR34) Vec Uses: V1(VSR33)V1(VSR33)
+; PWR10BE-NEXT:    xsadddp f1, f1, v1 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF1(VSR1)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xxswapd v2, v0 # Vec Defs: V2(VSR34) Vec Uses: V0(VSR32)V0(VSR32)
+; PWR10BE-NEXT:    xsadddp f1, f1, v0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF0(VSR0)
+; PWR10BE-NEXT:    xsadddp f1, f1, v2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)VF2(VSR2)
+; PWR10BE-NEXT:    xsadddp f1, f1, f13 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F13(VSR13)
+; PWR10BE-NEXT:    xxswapd vs13, vs13 # Vec Defs: VSL13(VSR13) Vec Uses: VSL13(VSR13)VSL13(VSR13)
+; PWR10BE-NEXT:    xsadddp f1, f1, f13 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F13(VSR13)
+; PWR10BE-NEXT:    xsadddp f1, f1, f12 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F12(VSR12)
+; PWR10BE-NEXT:    xxswapd vs12, vs12 # Vec Defs: VSL12(VSR12) Vec Uses: VSL12(VSR12)VSL12(VSR12)
+; PWR10BE-NEXT:    xsadddp f1, f1, f12 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F12(VSR12)
+; PWR10BE-NEXT:    xsadddp f1, f1, f11 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F11(VSR11)
+; PWR10BE-NEXT:    xxswapd vs11, vs11 # Vec Defs: VSL11(VSR11) Vec Uses: VSL11(VSR11)VSL11(VSR11)
+; PWR10BE-NEXT:    xsadddp f1, f1, f11 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F11(VSR11)
+; PWR10BE-NEXT:    xsadddp f1, f1, f10 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F10(VSR10)
+; PWR10BE-NEXT:    xxswapd vs10, vs10 # Vec Defs: VSL10(VSR10) Vec Uses: VSL10(VSR10)VSL10(VSR10)
+; PWR10BE-NEXT:    xsadddp f1, f1, f10 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F10(VSR10)
+; PWR10BE-NEXT:    xsadddp f1, f1, f9 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F9(VSR9)
+; PWR10BE-NEXT:    xxswapd vs9, vs9 # Vec Defs: VSL9(VSR9) Vec Uses: VSL9(VSR9)VSL9(VSR9)
+; PWR10BE-NEXT:    xsadddp f1, f1, f9 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F9(VSR9)
+; PWR10BE-NEXT:    xsadddp f1, f1, f8 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F8(VSR8)
+; PWR10BE-NEXT:    xxswapd vs8, vs8 # Vec Defs: VSL8(VSR8) Vec Uses: VSL8(VSR8)VSL8(VSR8)
+; PWR10BE-NEXT:    xsadddp f1, f1, f8 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F8(VSR8)
+; PWR10BE-NEXT:    xsadddp f1, f1, f7 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F7(VSR7)
+; PWR10BE-NEXT:    xxswapd vs7, vs7 # Vec Defs: VSL7(VSR7) Vec Uses: VSL7(VSR7)VSL7(VSR7)
+; PWR10BE-NEXT:    xsadddp f1, f1, f7 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F7(VSR7)
+; PWR10BE-NEXT:    xsadddp f1, f1, f6 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F6(VSR6)
+; PWR10BE-NEXT:    xxswapd vs6, vs6 # Vec Defs: VSL6(VSR6) Vec Uses: VSL6(VSR6)VSL6(VSR6)
+; PWR10BE-NEXT:    xsadddp f1, f1, f6 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F6(VSR6)
+; PWR10BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10BE-NEXT:    xxswapd vs5, vs5 # Vec Defs: VSL5(VSR5) Vec Uses: VSL5(VSR5)VSL5(VSR5)
+; PWR10BE-NEXT:    xsadddp f1, f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F5(VSR5)
+; PWR10BE-NEXT:    xsadddp f1, f1, f4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F4(VSR4)
+; PWR10BE-NEXT:    xxswapd vs4, vs4 # Vec Defs: VSL4(VSR4) Vec Uses: VSL4(VSR4)VSL4(VSR4)
+; PWR10BE-NEXT:    xsadddp f1, f1, f4 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F4(VSR4)
+; PWR10BE-NEXT:    xsadddp f1, f1, f3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F3(VSR3)
+; PWR10BE-NEXT:    xxswapd vs3, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: VSL3(VSR3)VSL3(VSR3)
+; PWR10BE-NEXT:    xsadddp f1, f1, f3 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F3(VSR3)
+; PWR10BE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR10BE-NEXT:    xxswapd vs2, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL2(VSR2)VSL2(VSR2)
+; PWR10BE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
+; PWR10BE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
+; PWR10BE-NEXT:    xxswapd vs0, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10BE-NEXT:    xsadddp f1, f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F0(VSR0)
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call double @llvm.vector.reduce.fadd.v64f64(double %b, <64 x double> %a)
   ret double %0
 }
 
 define dso_local double @v64f64_fast(<64 x double> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v64f64_fast:
 ; PWR9LE:       # %bb.0: # %entry
-; PWR9LE-NEXT:    lxv vs0, 368(r1)
-; PWR9LE-NEXT:    lxv vs1, 496(r1)
-; PWR9LE-NEXT:    lxv vs2, 240(r1)
-; PWR9LE-NEXT:    lxv vs3, 304(r1)
-; PWR9LE-NEXT:    xvadddp vs3, v3, vs3
-; PWR9LE-NEXT:    lxv vs4, 432(r1)
-; PWR9LE-NEXT:    lxv vs5, 400(r1)
-; PWR9LE-NEXT:    lxv vs6, 528(r1)
-; PWR9LE-NEXT:    lxv vs7, 272(r1)
-; PWR9LE-NEXT:    lxv vs8, 336(r1)
-; PWR9LE-NEXT:    lxv vs9, 464(r1)
-; PWR9LE-NEXT:    lxv vs10, 352(r1)
-; PWR9LE-NEXT:    lxv vs11, 480(r1)
-; PWR9LE-NEXT:    lxv vs12, 224(r1)
-; PWR9LE-NEXT:    lxv vs13, 288(r1)
-; PWR9LE-NEXT:    lxv v0, 416(r1)
-; PWR9LE-NEXT:    lxv v1, 384(r1)
-; PWR9LE-NEXT:    lxv v14, 512(r1)
-; PWR9LE-NEXT:    lxv v15, 256(r1)
-; PWR9LE-NEXT:    lxv v16, 320(r1)
-; PWR9LE-NEXT:    lxv v17, 448(r1)
-; PWR9LE-NEXT:    xvadddp v12, v12, v17
-; PWR9LE-NEXT:    xvadddp v4, v4, v16
-; PWR9LE-NEXT:    xvadddp v14, v15, v14
-; PWR9LE-NEXT:    xvadddp v1, v8, v1
-; PWR9LE-NEXT:    xvadddp v0, v10, v0
-; PWR9LE-NEXT:    xvadddp vs13, v2, vs13
-; PWR9LE-NEXT:    xvadddp vs11, vs12, vs11
-; PWR9LE-NEXT:    xvadddp vs10, v6, vs10
-; PWR9LE-NEXT:    xvadddp vs9, v13, vs9
-; PWR9LE-NEXT:    xvadddp vs8, v5, vs8
-; PWR9LE-NEXT:    xvadddp vs6, vs7, vs6
-; PWR9LE-NEXT:    xvadddp vs5, v9, vs5
-; PWR9LE-NEXT:    xvadddp vs4, v11, vs4
-; PWR9LE-NEXT:    xvadddp vs1, vs2, vs1
-; PWR9LE-NEXT:    xvadddp vs0, v7, vs0
-; PWR9LE-NEXT:    xvadddp vs0, vs0, vs1
-; PWR9LE-NEXT:    xvadddp vs1, vs3, vs4
-; PWR9LE-NEXT:    xvadddp vs2, vs5, vs6
-; PWR9LE-NEXT:    xvadddp vs3, vs8, vs9
-; PWR9LE-NEXT:    xvadddp vs4, vs10, vs11
-; PWR9LE-NEXT:    xvadddp vs5, vs13, v0
-; PWR9LE-NEXT:    xvadddp vs6, v1, v14
-; PWR9LE-NEXT:    xvadddp vs7, v4, v12
-; PWR9LE-NEXT:    xvadddp vs6, vs7, vs6
-; PWR9LE-NEXT:    xvadddp vs4, vs5, vs4
-; PWR9LE-NEXT:    xvadddp vs2, vs3, vs2
-; PWR9LE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR9LE-NEXT:    xvadddp vs0, vs0, vs2
-; PWR9LE-NEXT:    xvadddp vs1, vs4, vs6
-; PWR9LE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR9LE-NEXT:    xxswapd vs1, vs0
-; PWR9LE-NEXT:    xvadddp vs0, vs0, vs1
-; PWR9LE-NEXT:    xxswapd vs1, vs0
+; PWR9LE-NEXT:    lxv vs0, 368(r1) # Vec Defs: VSL0(VSR0)
+; PWR9LE-NEXT:    lxv vs1, 496(r1) # Vec Defs: VSL1(VSR1)
+; PWR9LE-NEXT:    lxv vs2, 240(r1) # Vec Defs: VSL2(VSR2)
+; PWR9LE-NEXT:    lxv vs3, 304(r1) # Vec Defs: VSL3(VSR3)
+; PWR9LE-NEXT:    xvadddp vs3, v3, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: V3(VSR35)VSL3(VSR3)
+; PWR9LE-NEXT:    lxv vs4, 432(r1) # Vec Defs: VSL4(VSR4)
+; PWR9LE-NEXT:    lxv vs5, 400(r1) # Vec Defs: VSL5(VSR5)
+; PWR9LE-NEXT:    lxv vs6, 528(r1) # Vec Defs: VSL6(VSR6)
+; PWR9LE-NEXT:    lxv vs7, 272(r1) # Vec Defs: VSL7(VSR7)
+; PWR9LE-NEXT:    lxv vs8, 336(r1) # Vec Defs: VSL8(VSR8)
+; PWR9LE-NEXT:    lxv vs9, 464(r1) # Vec Defs: VSL9(VSR9)
+; PWR9LE-NEXT:    lxv vs10, 352(r1) # Vec Defs: VSL10(VSR10)
+; PWR9LE-NEXT:    lxv vs11, 480(r1) # Vec Defs: VSL11(VSR11)
+; PWR9LE-NEXT:    lxv vs12, 224(r1) # Vec Defs: VSL12(VSR12)
+; PWR9LE-NEXT:    lxv vs13, 288(r1) # Vec Defs: VSL13(VSR13)
+; PWR9LE-NEXT:    lxv v0, 416(r1) # Vec Defs: V0(VSR32)
+; PWR9LE-NEXT:    lxv v1, 384(r1) # Vec Defs: V1(VSR33)
+; PWR9LE-NEXT:    lxv v14, 512(r1) # Vec Defs: V14(VSR46)
+; PWR9LE-NEXT:    lxv v15, 256(r1) # Vec Defs: V15(VSR47)
+; PWR9LE-NEXT:    lxv v16, 320(r1) # Vec Defs: V16(VSR48)
+; PWR9LE-NEXT:    lxv v17, 448(r1) # Vec Defs: V17(VSR49)
+; PWR9LE-NEXT:    xvadddp v12, v12, v17 # Vec Defs: V12(VSR44) Vec Uses: V12(VSR44)V17(VSR49)
+; PWR9LE-NEXT:    xvadddp v4, v4, v16 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V16(VSR48)
+; PWR9LE-NEXT:    xvadddp v14, v15, v14 # Vec Defs: V14(VSR46) Vec Uses: V15(VSR47)V14(VSR46)
+; PWR9LE-NEXT:    xvadddp v1, v8, v1 # Vec Defs: V1(VSR33) Vec Uses: V8(VSR40)V1(VSR33)
+; PWR9LE-NEXT:    xvadddp v0, v10, v0 # Vec Defs: V0(VSR32) Vec Uses: V10(VSR42)V0(VSR32)
+; PWR9LE-NEXT:    xvadddp vs13, v2, vs13 # Vec Defs: VSL13(VSR13) Vec Uses: V2(VSR34)VSL13(VSR13)
+; PWR9LE-NEXT:    xvadddp vs11, vs12, vs11 # Vec Defs: VSL11(VSR11) Vec Uses: VSL12(VSR12)VSL11(VSR11)
+; PWR9LE-NEXT:    xvadddp vs10, v6, vs10 # Vec Defs: VSL10(VSR10) Vec Uses: V6(VSR38)VSL10(VSR10)
+; PWR9LE-NEXT:    xvadddp vs9, v13, vs9 # Vec Defs: VSL9(VSR9) Vec Uses: V13(VSR45)VSL9(VSR9)
+; PWR9LE-NEXT:    xvadddp vs8, v5, vs8 # Vec Defs: VSL8(VSR8) Vec Uses: V5(VSR37)VSL8(VSR8)
+; PWR9LE-NEXT:    xvadddp vs6, vs7, vs6 # Vec Defs: VSL6(VSR6) Vec Uses: VSL7(VSR7)VSL6(VSR6)
+; PWR9LE-NEXT:    xvadddp vs5, v9, vs5 # Vec Defs: VSL5(VSR5) Vec Uses: V9(VSR41)VSL5(VSR5)
+; PWR9LE-NEXT:    xvadddp vs4, v11, vs4 # Vec Defs: VSL4(VSR4) Vec Uses: V11(VSR43)VSL4(VSR4)
+; PWR9LE-NEXT:    xvadddp vs1, vs2, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PWR9LE-NEXT:    xvadddp vs0, v7, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: V7(VSR39)VSL0(VSR0)
+; PWR9LE-NEXT:    xvadddp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR9LE-NEXT:    xvadddp vs1, vs3, vs4 # Vec Defs: VSL1(VSR1) Vec Uses: VSL3(VSR3)VSL4(VSR4)
+; PWR9LE-NEXT:    xvadddp vs2, vs5, vs6 # Vec Defs: VSL2(VSR2) Vec Uses: VSL5(VSR5)VSL6(VSR6)
+; PWR9LE-NEXT:    xvadddp vs3, vs8, vs9 # Vec Defs: VSL3(VSR3) Vec Uses: VSL8(VSR8)VSL9(VSR9)
+; PWR9LE-NEXT:    xvadddp vs4, vs10, vs11 # Vec Defs: VSL4(VSR4) Vec Uses: VSL10(VSR10)VSL11(VSR11)
+; PWR9LE-NEXT:    xvadddp vs5, vs13, v0 # Vec Defs: VSL5(VSR5) Vec Uses: VSL13(VSR13)V0(VSR32)
+; PWR9LE-NEXT:    xvadddp vs6, v1, v14 # Vec Defs: VSL6(VSR6) Vec Uses: V1(VSR33)V14(VSR46)
+; PWR9LE-NEXT:    xvadddp vs7, v4, v12 # Vec Defs: VSL7(VSR7) Vec Uses: V4(VSR36)V12(VSR44)
+; PWR9LE-NEXT:    xvadddp vs6, vs7, vs6 # Vec Defs: VSL6(VSR6) Vec Uses: VSL7(VSR7)VSL6(VSR6)
+; PWR9LE-NEXT:    xvadddp vs4, vs5, vs4 # Vec Defs: VSL4(VSR4) Vec Uses: VSL5(VSR5)VSL4(VSR4)
+; PWR9LE-NEXT:    xvadddp vs2, vs3, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL3(VSR3)VSL2(VSR2)
+; PWR9LE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR9LE-NEXT:    xvadddp vs0, vs0, vs2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL2(VSR2)
+; PWR9LE-NEXT:    xvadddp vs1, vs4, vs6 # Vec Defs: VSL1(VSR1) Vec Uses: VSL4(VSR4)VSL6(VSR6)
+; PWR9LE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR9LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9LE-NEXT:    xvadddp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; PWR9LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v64f64_fast:
 ; PWR9BE:       # %bb.0: # %entry
-; PWR9BE-NEXT:    lxv vs0, 384(r1)
-; PWR9BE-NEXT:    lxv vs1, 512(r1)
-; PWR9BE-NEXT:    lxv vs2, 256(r1)
-; PWR9BE-NEXT:    lxv vs3, 320(r1)
-; PWR9BE-NEXT:    xvadddp vs3, v3, vs3
-; PWR9BE-NEXT:    lxv vs4, 448(r1)
-; PWR9BE-NEXT:    lxv vs5, 416(r1)
-; PWR9BE-NEXT:    lxv vs6, 544(r1)
-; PWR9BE-NEXT:    lxv vs7, 288(r1)
-; PWR9BE-NEXT:    lxv vs8, 352(r1)
-; PWR9BE-NEXT:    lxv vs9, 480(r1)
-; PWR9BE-NEXT:    lxv vs10, 368(r1)
-; PWR9BE-NEXT:    lxv vs11, 496(r1)
-; PWR9BE-NEXT:    lxv vs12, 240(r1)
-; PWR9BE-NEXT:    lxv vs13, 304(r1)
-; PWR9BE-NEXT:    lxv v0, 432(r1)
-; PWR9BE-NEXT:    lxv v1, 400(r1)
-; PWR9BE-NEXT:    lxv v14, 528(r1)
-; PWR9BE-NEXT:    lxv v15, 272(r1)
-; PWR9BE-NEXT:    lxv v16, 336(r1)
-; PWR9BE-NEXT:    lxv v17, 464(r1)
-; PWR9BE-NEXT:    xvadddp v12, v12, v17
-; PWR9BE-NEXT:    xvadddp v4, v4, v16
-; PWR9BE-NEXT:    xvadddp v14, v15, v14
-; PWR9BE-NEXT:    xvadddp v1, v8, v1
-; PWR9BE-NEXT:    xvadddp v0, v10, v0
-; PWR9BE-NEXT:    xvadddp vs13, v2, vs13
-; PWR9BE-NEXT:    xvadddp vs11, vs12, vs11
-; PWR9BE-NEXT:    xvadddp vs10, v6, vs10
-; PWR9BE-NEXT:    xvadddp vs9, v13, vs9
-; PWR9BE-NEXT:    xvadddp vs8, v5, vs8
-; PWR9BE-NEXT:    xvadddp vs6, vs7, vs6
-; PWR9BE-NEXT:    xvadddp vs5, v9, vs5
-; PWR9BE-NEXT:    xvadddp vs4, v11, vs4
-; PWR9BE-NEXT:    xvadddp vs1, vs2, vs1
-; PWR9BE-NEXT:    xvadddp vs0, v7, vs0
-; PWR9BE-NEXT:    xvadddp vs0, vs0, vs1
-; PWR9BE-NEXT:    xvadddp vs1, vs3, vs4
-; PWR9BE-NEXT:    xvadddp vs2, vs5, vs6
-; PWR9BE-NEXT:    xvadddp vs3, vs8, vs9
-; PWR9BE-NEXT:    xvadddp vs4, vs10, vs11
-; PWR9BE-NEXT:    xvadddp vs5, vs13, v0
-; PWR9BE-NEXT:    xvadddp vs6, v1, v14
-; PWR9BE-NEXT:    xvadddp vs7, v4, v12
-; PWR9BE-NEXT:    xvadddp vs6, vs7, vs6
-; PWR9BE-NEXT:    xvadddp vs4, vs5, vs4
-; PWR9BE-NEXT:    xvadddp vs2, vs3, vs2
-; PWR9BE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR9BE-NEXT:    xvadddp vs0, vs0, vs2
-; PWR9BE-NEXT:    xvadddp vs1, vs4, vs6
-; PWR9BE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR9BE-NEXT:    xxswapd vs1, vs0
-; PWR9BE-NEXT:    xvadddp vs1, vs0, vs1
+; PWR9BE-NEXT:    lxv vs0, 384(r1) # Vec Defs: VSL0(VSR0)
+; PWR9BE-NEXT:    lxv vs1, 512(r1) # Vec Defs: VSL1(VSR1)
+; PWR9BE-NEXT:    lxv vs2, 256(r1) # Vec Defs: VSL2(VSR2)
+; PWR9BE-NEXT:    lxv vs3, 320(r1) # Vec Defs: VSL3(VSR3)
+; PWR9BE-NEXT:    xvadddp vs3, v3, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: V3(VSR35)VSL3(VSR3)
+; PWR9BE-NEXT:    lxv vs4, 448(r1) # Vec Defs: VSL4(VSR4)
+; PWR9BE-NEXT:    lxv vs5, 416(r1) # Vec Defs: VSL5(VSR5)
+; PWR9BE-NEXT:    lxv vs6, 544(r1) # Vec Defs: VSL6(VSR6)
+; PWR9BE-NEXT:    lxv vs7, 288(r1) # Vec Defs: VSL7(VSR7)
+; PWR9BE-NEXT:    lxv vs8, 352(r1) # Vec Defs: VSL8(VSR8)
+; PWR9BE-NEXT:    lxv vs9, 480(r1) # Vec Defs: VSL9(VSR9)
+; PWR9BE-NEXT:    lxv vs10, 368(r1) # Vec Defs: VSL10(VSR10)
+; PWR9BE-NEXT:    lxv vs11, 496(r1) # Vec Defs: VSL11(VSR11)
+; PWR9BE-NEXT:    lxv vs12, 240(r1) # Vec Defs: VSL12(VSR12)
+; PWR9BE-NEXT:    lxv vs13, 304(r1) # Vec Defs: VSL13(VSR13)
+; PWR9BE-NEXT:    lxv v0, 432(r1) # Vec Defs: V0(VSR32)
+; PWR9BE-NEXT:    lxv v1, 400(r1) # Vec Defs: V1(VSR33)
+; PWR9BE-NEXT:    lxv v14, 528(r1) # Vec Defs: V14(VSR46)
+; PWR9BE-NEXT:    lxv v15, 272(r1) # Vec Defs: V15(VSR47)
+; PWR9BE-NEXT:    lxv v16, 336(r1) # Vec Defs: V16(VSR48)
+; PWR9BE-NEXT:    lxv v17, 464(r1) # Vec Defs: V17(VSR49)
+; PWR9BE-NEXT:    xvadddp v12, v12, v17 # Vec Defs: V12(VSR44) Vec Uses: V12(VSR44)V17(VSR49)
+; PWR9BE-NEXT:    xvadddp v4, v4, v16 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V16(VSR48)
+; PWR9BE-NEXT:    xvadddp v14, v15, v14 # Vec Defs: V14(VSR46) Vec Uses: V15(VSR47)V14(VSR46)
+; PWR9BE-NEXT:    xvadddp v1, v8, v1 # Vec Defs: V1(VSR33) Vec Uses: V8(VSR40)V1(VSR33)
+; PWR9BE-NEXT:    xvadddp v0, v10, v0 # Vec Defs: V0(VSR32) Vec Uses: V10(VSR42)V0(VSR32)
+; PWR9BE-NEXT:    xvadddp vs13, v2, vs13 # Vec Defs: VSL13(VSR13) Vec Uses: V2(VSR34)VSL13(VSR13)
+; PWR9BE-NEXT:    xvadddp vs11, vs12, vs11 # Vec Defs: VSL11(VSR11) Vec Uses: VSL12(VSR12)VSL11(VSR11)
+; PWR9BE-NEXT:    xvadddp vs10, v6, vs10 # Vec Defs: VSL10(VSR10) Vec Uses: V6(VSR38)VSL10(VSR10)
+; PWR9BE-NEXT:    xvadddp vs9, v13, vs9 # Vec Defs: VSL9(VSR9) Vec Uses: V13(VSR45)VSL9(VSR9)
+; PWR9BE-NEXT:    xvadddp vs8, v5, vs8 # Vec Defs: VSL8(VSR8) Vec Uses: V5(VSR37)VSL8(VSR8)
+; PWR9BE-NEXT:    xvadddp vs6, vs7, vs6 # Vec Defs: VSL6(VSR6) Vec Uses: VSL7(VSR7)VSL6(VSR6)
+; PWR9BE-NEXT:    xvadddp vs5, v9, vs5 # Vec Defs: VSL5(VSR5) Vec Uses: V9(VSR41)VSL5(VSR5)
+; PWR9BE-NEXT:    xvadddp vs4, v11, vs4 # Vec Defs: VSL4(VSR4) Vec Uses: V11(VSR43)VSL4(VSR4)
+; PWR9BE-NEXT:    xvadddp vs1, vs2, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PWR9BE-NEXT:    xvadddp vs0, v7, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: V7(VSR39)VSL0(VSR0)
+; PWR9BE-NEXT:    xvadddp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR9BE-NEXT:    xvadddp vs1, vs3, vs4 # Vec Defs: VSL1(VSR1) Vec Uses: VSL3(VSR3)VSL4(VSR4)
+; PWR9BE-NEXT:    xvadddp vs2, vs5, vs6 # Vec Defs: VSL2(VSR2) Vec Uses: VSL5(VSR5)VSL6(VSR6)
+; PWR9BE-NEXT:    xvadddp vs3, vs8, vs9 # Vec Defs: VSL3(VSR3) Vec Uses: VSL8(VSR8)VSL9(VSR9)
+; PWR9BE-NEXT:    xvadddp vs4, vs10, vs11 # Vec Defs: VSL4(VSR4) Vec Uses: VSL10(VSR10)VSL11(VSR11)
+; PWR9BE-NEXT:    xvadddp vs5, vs13, v0 # Vec Defs: VSL5(VSR5) Vec Uses: VSL13(VSR13)V0(VSR32)
+; PWR9BE-NEXT:    xvadddp vs6, v1, v14 # Vec Defs: VSL6(VSR6) Vec Uses: V1(VSR33)V14(VSR46)
+; PWR9BE-NEXT:    xvadddp vs7, v4, v12 # Vec Defs: VSL7(VSR7) Vec Uses: V4(VSR36)V12(VSR44)
+; PWR9BE-NEXT:    xvadddp vs6, vs7, vs6 # Vec Defs: VSL6(VSR6) Vec Uses: VSL7(VSR7)VSL6(VSR6)
+; PWR9BE-NEXT:    xvadddp vs4, vs5, vs4 # Vec Defs: VSL4(VSR4) Vec Uses: VSL5(VSR5)VSL4(VSR4)
+; PWR9BE-NEXT:    xvadddp vs2, vs3, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL3(VSR3)VSL2(VSR2)
+; PWR9BE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR9BE-NEXT:    xvadddp vs0, vs0, vs2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL2(VSR2)
+; PWR9BE-NEXT:    xvadddp vs1, vs4, vs6 # Vec Defs: VSL1(VSR1) Vec Uses: VSL4(VSR4)VSL6(VSR6)
+; PWR9BE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR9BE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR9BE-NEXT:    xvadddp vs1, vs0, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL1(VSR1)
 ; PWR9BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v64f64_fast:
 ; PWR10LE:       # %bb.0: # %entry
-; PWR10LE-NEXT:    lxv vs0, 368(r1)
-; PWR10LE-NEXT:    lxv vs1, 496(r1)
-; PWR10LE-NEXT:    xvadddp vs0, v7, vs0
-; PWR10LE-NEXT:    lxv vs2, 240(r1)
-; PWR10LE-NEXT:    lxv vs3, 304(r1)
-; PWR10LE-NEXT:    lxv vs4, 432(r1)
-; PWR10LE-NEXT:    lxv vs5, 400(r1)
-; PWR10LE-NEXT:    lxv vs6, 528(r1)
-; PWR10LE-NEXT:    lxv vs7, 272(r1)
-; PWR10LE-NEXT:    lxv vs8, 336(r1)
-; PWR10LE-NEXT:    lxv vs9, 464(r1)
-; PWR10LE-NEXT:    lxv vs10, 352(r1)
-; PWR10LE-NEXT:    lxv vs11, 480(r1)
-; PWR10LE-NEXT:    lxv vs12, 224(r1)
-; PWR10LE-NEXT:    lxv vs13, 288(r1)
-; PWR10LE-NEXT:    xvadddp vs13, v2, vs13
-; PWR10LE-NEXT:    xvadddp vs11, vs12, vs11
-; PWR10LE-NEXT:    xvadddp vs10, v6, vs10
-; PWR10LE-NEXT:    xvadddp vs9, v13, vs9
-; PWR10LE-NEXT:    xvadddp vs8, v5, vs8
-; PWR10LE-NEXT:    xvadddp vs6, vs7, vs6
-; PWR10LE-NEXT:    xvadddp vs5, v9, vs5
-; PWR10LE-NEXT:    xvadddp vs4, v11, vs4
-; PWR10LE-NEXT:    xvadddp vs3, v3, vs3
-; PWR10LE-NEXT:    xvadddp vs1, vs2, vs1
-; PWR10LE-NEXT:    xvadddp vs0, vs0, vs1
-; PWR10LE-NEXT:    lxv v0, 416(r1)
-; PWR10LE-NEXT:    lxv v1, 384(r1)
-; PWR10LE-NEXT:    lxv v14, 512(r1)
-; PWR10LE-NEXT:    lxv v15, 256(r1)
-; PWR10LE-NEXT:    lxv v16, 320(r1)
-; PWR10LE-NEXT:    lxv v17, 448(r1)
-; PWR10LE-NEXT:    xvadddp v12, v12, v17
-; PWR10LE-NEXT:    xvadddp v4, v4, v16
-; PWR10LE-NEXT:    xvadddp v14, v15, v14
-; PWR10LE-NEXT:    xvadddp v1, v8, v1
-; PWR10LE-NEXT:    xvadddp v0, v10, v0
-; PWR10LE-NEXT:    xvadddp vs1, vs3, vs4
-; PWR10LE-NEXT:    xvadddp vs2, vs5, vs6
-; PWR10LE-NEXT:    xvadddp vs3, vs8, vs9
-; PWR10LE-NEXT:    xvadddp vs4, vs10, vs11
-; PWR10LE-NEXT:    xvadddp vs5, vs13, v0
-; PWR10LE-NEXT:    xvadddp vs6, v1, v14
-; PWR10LE-NEXT:    xvadddp vs7, v4, v12
-; PWR10LE-NEXT:    xvadddp vs6, vs7, vs6
-; PWR10LE-NEXT:    xvadddp vs4, vs5, vs4
-; PWR10LE-NEXT:    xvadddp vs2, vs3, vs2
-; PWR10LE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR10LE-NEXT:    xvadddp vs0, vs0, vs2
-; PWR10LE-NEXT:    xvadddp vs1, vs4, vs6
-; PWR10LE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR10LE-NEXT:    xxswapd vs1, vs0
-; PWR10LE-NEXT:    xvadddp vs0, vs0, vs1
-; PWR10LE-NEXT:    xxswapd vs1, vs0
+; PWR10LE-NEXT:    lxv vs0, 368(r1) # Vec Defs: VSL0(VSR0)
+; PWR10LE-NEXT:    lxv vs1, 496(r1) # Vec Defs: VSL1(VSR1)
+; PWR10LE-NEXT:    xvadddp vs0, v7, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: V7(VSR39)VSL0(VSR0)
+; PWR10LE-NEXT:    lxv vs2, 240(r1) # Vec Defs: VSL2(VSR2)
+; PWR10LE-NEXT:    lxv vs3, 304(r1) # Vec Defs: VSL3(VSR3)
+; PWR10LE-NEXT:    lxv vs4, 432(r1) # Vec Defs: VSL4(VSR4)
+; PWR10LE-NEXT:    lxv vs5, 400(r1) # Vec Defs: VSL5(VSR5)
+; PWR10LE-NEXT:    lxv vs6, 528(r1) # Vec Defs: VSL6(VSR6)
+; PWR10LE-NEXT:    lxv vs7, 272(r1) # Vec Defs: VSL7(VSR7)
+; PWR10LE-NEXT:    lxv vs8, 336(r1) # Vec Defs: VSL8(VSR8)
+; PWR10LE-NEXT:    lxv vs9, 464(r1) # Vec Defs: VSL9(VSR9)
+; PWR10LE-NEXT:    lxv vs10, 352(r1) # Vec Defs: VSL10(VSR10)
+; PWR10LE-NEXT:    lxv vs11, 480(r1) # Vec Defs: VSL11(VSR11)
+; PWR10LE-NEXT:    lxv vs12, 224(r1) # Vec Defs: VSL12(VSR12)
+; PWR10LE-NEXT:    lxv vs13, 288(r1) # Vec Defs: VSL13(VSR13)
+; PWR10LE-NEXT:    xvadddp vs13, v2, vs13 # Vec Defs: VSL13(VSR13) Vec Uses: V2(VSR34)VSL13(VSR13)
+; PWR10LE-NEXT:    xvadddp vs11, vs12, vs11 # Vec Defs: VSL11(VSR11) Vec Uses: VSL12(VSR12)VSL11(VSR11)
+; PWR10LE-NEXT:    xvadddp vs10, v6, vs10 # Vec Defs: VSL10(VSR10) Vec Uses: V6(VSR38)VSL10(VSR10)
+; PWR10LE-NEXT:    xvadddp vs9, v13, vs9 # Vec Defs: VSL9(VSR9) Vec Uses: V13(VSR45)VSL9(VSR9)
+; PWR10LE-NEXT:    xvadddp vs8, v5, vs8 # Vec Defs: VSL8(VSR8) Vec Uses: V5(VSR37)VSL8(VSR8)
+; PWR10LE-NEXT:    xvadddp vs6, vs7, vs6 # Vec Defs: VSL6(VSR6) Vec Uses: VSL7(VSR7)VSL6(VSR6)
+; PWR10LE-NEXT:    xvadddp vs5, v9, vs5 # Vec Defs: VSL5(VSR5) Vec Uses: V9(VSR41)VSL5(VSR5)
+; PWR10LE-NEXT:    xvadddp vs4, v11, vs4 # Vec Defs: VSL4(VSR4) Vec Uses: V11(VSR43)VSL4(VSR4)
+; PWR10LE-NEXT:    xvadddp vs3, v3, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: V3(VSR35)VSL3(VSR3)
+; PWR10LE-NEXT:    xvadddp vs1, vs2, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PWR10LE-NEXT:    xvadddp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR10LE-NEXT:    lxv v0, 416(r1) # Vec Defs: V0(VSR32)
+; PWR10LE-NEXT:    lxv v1, 384(r1) # Vec Defs: V1(VSR33)
+; PWR10LE-NEXT:    lxv v14, 512(r1) # Vec Defs: V14(VSR46)
+; PWR10LE-NEXT:    lxv v15, 256(r1) # Vec Defs: V15(VSR47)
+; PWR10LE-NEXT:    lxv v16, 320(r1) # Vec Defs: V16(VSR48)
+; PWR10LE-NEXT:    lxv v17, 448(r1) # Vec Defs: V17(VSR49)
+; PWR10LE-NEXT:    xvadddp v12, v12, v17 # Vec Defs: V12(VSR44) Vec Uses: V12(VSR44)V17(VSR49)
+; PWR10LE-NEXT:    xvadddp v4, v4, v16 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V16(VSR48)
+; PWR10LE-NEXT:    xvadddp v14, v15, v14 # Vec Defs: V14(VSR46) Vec Uses: V15(VSR47)V14(VSR46)
+; PWR10LE-NEXT:    xvadddp v1, v8, v1 # Vec Defs: V1(VSR33) Vec Uses: V8(VSR40)V1(VSR33)
+; PWR10LE-NEXT:    xvadddp v0, v10, v0 # Vec Defs: V0(VSR32) Vec Uses: V10(VSR42)V0(VSR32)
+; PWR10LE-NEXT:    xvadddp vs1, vs3, vs4 # Vec Defs: VSL1(VSR1) Vec Uses: VSL3(VSR3)VSL4(VSR4)
+; PWR10LE-NEXT:    xvadddp vs2, vs5, vs6 # Vec Defs: VSL2(VSR2) Vec Uses: VSL5(VSR5)VSL6(VSR6)
+; PWR10LE-NEXT:    xvadddp vs3, vs8, vs9 # Vec Defs: VSL3(VSR3) Vec Uses: VSL8(VSR8)VSL9(VSR9)
+; PWR10LE-NEXT:    xvadddp vs4, vs10, vs11 # Vec Defs: VSL4(VSR4) Vec Uses: VSL10(VSR10)VSL11(VSR11)
+; PWR10LE-NEXT:    xvadddp vs5, vs13, v0 # Vec Defs: VSL5(VSR5) Vec Uses: VSL13(VSR13)V0(VSR32)
+; PWR10LE-NEXT:    xvadddp vs6, v1, v14 # Vec Defs: VSL6(VSR6) Vec Uses: V1(VSR33)V14(VSR46)
+; PWR10LE-NEXT:    xvadddp vs7, v4, v12 # Vec Defs: VSL7(VSR7) Vec Uses: V4(VSR36)V12(VSR44)
+; PWR10LE-NEXT:    xvadddp vs6, vs7, vs6 # Vec Defs: VSL6(VSR6) Vec Uses: VSL7(VSR7)VSL6(VSR6)
+; PWR10LE-NEXT:    xvadddp vs4, vs5, vs4 # Vec Defs: VSL4(VSR4) Vec Uses: VSL5(VSR5)VSL4(VSR4)
+; PWR10LE-NEXT:    xvadddp vs2, vs3, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL3(VSR3)VSL2(VSR2)
+; PWR10LE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR10LE-NEXT:    xvadddp vs0, vs0, vs2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL2(VSR2)
+; PWR10LE-NEXT:    xvadddp vs1, vs4, vs6 # Vec Defs: VSL1(VSR1) Vec Uses: VSL4(VSR4)VSL6(VSR6)
+; PWR10LE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR10LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10LE-NEXT:    xvadddp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; PWR10LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v64f64_fast:
 ; PWR10BE:       # %bb.0: # %entry
-; PWR10BE-NEXT:    lxv vs0, 384(r1)
-; PWR10BE-NEXT:    lxv vs1, 512(r1)
-; PWR10BE-NEXT:    xvadddp vs0, v7, vs0
-; PWR10BE-NEXT:    lxv vs2, 256(r1)
-; PWR10BE-NEXT:    lxv vs3, 320(r1)
-; PWR10BE-NEXT:    lxv vs4, 448(r1)
-; PWR10BE-NEXT:    lxv vs5, 416(r1)
-; PWR10BE-NEXT:    lxv vs6, 544(r1)
-; PWR10BE-NEXT:    lxv vs7, 288(r1)
-; PWR10BE-NEXT:    lxv vs8, 352(r1)
-; PWR10BE-NEXT:    lxv vs9, 480(r1)
-; PWR10BE-NEXT:    lxv vs10, 368(r1)
-; PWR10BE-NEXT:    lxv vs11, 496(r1)
-; PWR10BE-NEXT:    lxv vs12, 240(r1)
-; PWR10BE-NEXT:    lxv vs13, 304(r1)
-; PWR10BE-NEXT:    xvadddp vs13, v2, vs13
-; PWR10BE-NEXT:    xvadddp vs11, vs12, vs11
-; PWR10BE-NEXT:    xvadddp vs10, v6, vs10
-; PWR10BE-NEXT:    xvadddp vs9, v13, vs9
-; PWR10BE-NEXT:    xvadddp vs8, v5, vs8
-; PWR10BE-NEXT:    xvadddp vs6, vs7, vs6
-; PWR10BE-NEXT:    xvadddp vs5, v9, vs5
-; PWR10BE-NEXT:    xvadddp vs4, v11, vs4
-; PWR10BE-NEXT:    xvadddp vs3, v3, vs3
-; PWR10BE-NEXT:    xvadddp vs1, vs2, vs1
-; PWR10BE-NEXT:    xvadddp vs0, vs0, vs1
-; PWR10BE-NEXT:    lxv v0, 432(r1)
-; PWR10BE-NEXT:    lxv v1, 400(r1)
-; PWR10BE-NEXT:    lxv v14, 528(r1)
-; PWR10BE-NEXT:    lxv v15, 272(r1)
-; PWR10BE-NEXT:    lxv v16, 336(r1)
-; PWR10BE-NEXT:    lxv v17, 464(r1)
-; PWR10BE-NEXT:    xvadddp v12, v12, v17
-; PWR10BE-NEXT:    xvadddp v4, v4, v16
-; PWR10BE-NEXT:    xvadddp v14, v15, v14
-; PWR10BE-NEXT:    xvadddp v1, v8, v1
-; PWR10BE-NEXT:    xvadddp v0, v10, v0
-; PWR10BE-NEXT:    xvadddp vs1, vs3, vs4
-; PWR10BE-NEXT:    xvadddp vs2, vs5, vs6
-; PWR10BE-NEXT:    xvadddp vs3, vs8, vs9
-; PWR10BE-NEXT:    xvadddp vs4, vs10, vs11
-; PWR10BE-NEXT:    xvadddp vs5, vs13, v0
-; PWR10BE-NEXT:    xvadddp vs6, v1, v14
-; PWR10BE-NEXT:    xvadddp vs7, v4, v12
-; PWR10BE-NEXT:    xvadddp vs6, vs7, vs6
-; PWR10BE-NEXT:    xvadddp vs4, vs5, vs4
-; PWR10BE-NEXT:    xvadddp vs2, vs3, vs2
-; PWR10BE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR10BE-NEXT:    xvadddp vs0, vs0, vs2
-; PWR10BE-NEXT:    xvadddp vs1, vs4, vs6
-; PWR10BE-NEXT:    xvadddp vs0, vs1, vs0
-; PWR10BE-NEXT:    xxswapd vs1, vs0
-; PWR10BE-NEXT:    xvadddp vs1, vs0, vs1
+; PWR10BE-NEXT:    lxv vs0, 384(r1) # Vec Defs: VSL0(VSR0)
+; PWR10BE-NEXT:    lxv vs1, 512(r1) # Vec Defs: VSL1(VSR1)
+; PWR10BE-NEXT:    xvadddp vs0, v7, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: V7(VSR39)VSL0(VSR0)
+; PWR10BE-NEXT:    lxv vs2, 256(r1) # Vec Defs: VSL2(VSR2)
+; PWR10BE-NEXT:    lxv vs3, 320(r1) # Vec Defs: VSL3(VSR3)
+; PWR10BE-NEXT:    lxv vs4, 448(r1) # Vec Defs: VSL4(VSR4)
+; PWR10BE-NEXT:    lxv vs5, 416(r1) # Vec Defs: VSL5(VSR5)
+; PWR10BE-NEXT:    lxv vs6, 544(r1) # Vec Defs: VSL6(VSR6)
+; PWR10BE-NEXT:    lxv vs7, 288(r1) # Vec Defs: VSL7(VSR7)
+; PWR10BE-NEXT:    lxv vs8, 352(r1) # Vec Defs: VSL8(VSR8)
+; PWR10BE-NEXT:    lxv vs9, 480(r1) # Vec Defs: VSL9(VSR9)
+; PWR10BE-NEXT:    lxv vs10, 368(r1) # Vec Defs: VSL10(VSR10)
+; PWR10BE-NEXT:    lxv vs11, 496(r1) # Vec Defs: VSL11(VSR11)
+; PWR10BE-NEXT:    lxv vs12, 240(r1) # Vec Defs: VSL12(VSR12)
+; PWR10BE-NEXT:    lxv vs13, 304(r1) # Vec Defs: VSL13(VSR13)
+; PWR10BE-NEXT:    xvadddp vs13, v2, vs13 # Vec Defs: VSL13(VSR13) Vec Uses: V2(VSR34)VSL13(VSR13)
+; PWR10BE-NEXT:    xvadddp vs11, vs12, vs11 # Vec Defs: VSL11(VSR11) Vec Uses: VSL12(VSR12)VSL11(VSR11)
+; PWR10BE-NEXT:    xvadddp vs10, v6, vs10 # Vec Defs: VSL10(VSR10) Vec Uses: V6(VSR38)VSL10(VSR10)
+; PWR10BE-NEXT:    xvadddp vs9, v13, vs9 # Vec Defs: VSL9(VSR9) Vec Uses: V13(VSR45)VSL9(VSR9)
+; PWR10BE-NEXT:    xvadddp vs8, v5, vs8 # Vec Defs: VSL8(VSR8) Vec Uses: V5(VSR37)VSL8(VSR8)
+; PWR10BE-NEXT:    xvadddp vs6, vs7, vs6 # Vec Defs: VSL6(VSR6) Vec Uses: VSL7(VSR7)VSL6(VSR6)
+; PWR10BE-NEXT:    xvadddp vs5, v9, vs5 # Vec Defs: VSL5(VSR5) Vec Uses: V9(VSR41)VSL5(VSR5)
+; PWR10BE-NEXT:    xvadddp vs4, v11, vs4 # Vec Defs: VSL4(VSR4) Vec Uses: V11(VSR43)VSL4(VSR4)
+; PWR10BE-NEXT:    xvadddp vs3, v3, vs3 # Vec Defs: VSL3(VSR3) Vec Uses: V3(VSR35)VSL3(VSR3)
+; PWR10BE-NEXT:    xvadddp vs1, vs2, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL2(VSR2)VSL1(VSR1)
+; PWR10BE-NEXT:    xvadddp vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; PWR10BE-NEXT:    lxv v0, 432(r1) # Vec Defs: V0(VSR32)
+; PWR10BE-NEXT:    lxv v1, 400(r1) # Vec Defs: V1(VSR33)
+; PWR10BE-NEXT:    lxv v14, 528(r1) # Vec Defs: V14(VSR46)
+; PWR10BE-NEXT:    lxv v15, 272(r1) # Vec Defs: V15(VSR47)
+; PWR10BE-NEXT:    lxv v16, 336(r1) # Vec Defs: V16(VSR48)
+; PWR10BE-NEXT:    lxv v17, 464(r1) # Vec Defs: V17(VSR49)
+; PWR10BE-NEXT:    xvadddp v12, v12, v17 # Vec Defs: V12(VSR44) Vec Uses: V12(VSR44)V17(VSR49)
+; PWR10BE-NEXT:    xvadddp v4, v4, v16 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V16(VSR48)
+; PWR10BE-NEXT:    xvadddp v14, v15, v14 # Vec Defs: V14(VSR46) Vec Uses: V15(VSR47)V14(VSR46)
+; PWR10BE-NEXT:    xvadddp v1, v8, v1 # Vec Defs: V1(VSR33) Vec Uses: V8(VSR40)V1(VSR33)
+; PWR10BE-NEXT:    xvadddp v0, v10, v0 # Vec Defs: V0(VSR32) Vec Uses: V10(VSR42)V0(VSR32)
+; PWR10BE-NEXT:    xvadddp vs1, vs3, vs4 # Vec Defs: VSL1(VSR1) Vec Uses: VSL3(VSR3)VSL4(VSR4)
+; PWR10BE-NEXT:    xvadddp vs2, vs5, vs6 # Vec Defs: VSL2(VSR2) Vec Uses: VSL5(VSR5)VSL6(VSR6)
+; PWR10BE-NEXT:    xvadddp vs3, vs8, vs9 # Vec Defs: VSL3(VSR3) Vec Uses: VSL8(VSR8)VSL9(VSR9)
+; PWR10BE-NEXT:    xvadddp vs4, vs10, vs11 # Vec Defs: VSL4(VSR4) Vec Uses: VSL10(VSR10)VSL11(VSR11)
+; PWR10BE-NEXT:    xvadddp vs5, vs13, v0 # Vec Defs: VSL5(VSR5) Vec Uses: VSL13(VSR13)V0(VSR32)
+; PWR10BE-NEXT:    xvadddp vs6, v1, v14 # Vec Defs: VSL6(VSR6) Vec Uses: V1(VSR33)V14(VSR46)
+; PWR10BE-NEXT:    xvadddp vs7, v4, v12 # Vec Defs: VSL7(VSR7) Vec Uses: V4(VSR36)V12(VSR44)
+; PWR10BE-NEXT:    xvadddp vs6, vs7, vs6 # Vec Defs: VSL6(VSR6) Vec Uses: VSL7(VSR7)VSL6(VSR6)
+; PWR10BE-NEXT:    xvadddp vs4, vs5, vs4 # Vec Defs: VSL4(VSR4) Vec Uses: VSL5(VSR5)VSL4(VSR4)
+; PWR10BE-NEXT:    xvadddp vs2, vs3, vs2 # Vec Defs: VSL2(VSR2) Vec Uses: VSL3(VSR3)VSL2(VSR2)
+; PWR10BE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR10BE-NEXT:    xvadddp vs0, vs0, vs2 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL2(VSR2)
+; PWR10BE-NEXT:    xvadddp vs1, vs4, vs6 # Vec Defs: VSL1(VSR1) Vec Uses: VSL4(VSR4)VSL6(VSR6)
+; PWR10BE-NEXT:    xvadddp vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; PWR10BE-NEXT:    xxswapd vs1, vs0 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; PWR10BE-NEXT:    xvadddp vs1, vs0, vs1 # Vec Defs: VSL1(VSR1) Vec Uses: VSL0(VSR0)VSL1(VSR1)
 ; PWR10BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call fast double @llvm.vector.reduce.fadd.v64f64(double -0.000000e+00, <64 x double> %a)
   ret double %0
 }
 
 declare double @llvm.vector.reduce.fadd.v2f64(double, <2 x double>) #0
entry:
   ret ppc_fp128 %0
 }
 
 define dso_local ppc_fp128 @v2ppcf128_b(<2 x ppc_fp128> %a, ppc_fp128 %b) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v2ppcf128_b:
 ; PWR9LE:       # %bb.0: # %entry
 ; PWR9LE-NEXT:    mflr r0
 ; PWR9LE-NEXT:    stfd f30, -16(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PWR9LE-NEXT:    stfd f31, -8(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PWR9LE-NEXT:    std r0, 16(r1)
 ; PWR9LE-NEXT:    stdu r1, -48(r1)
-; PWR9LE-NEXT:    fmr f31, f4
-; PWR9LE-NEXT:    fmr f30, f3
-; PWR9LE-NEXT:    fmr f4, f2
-; PWR9LE-NEXT:    fmr f3, f1
-; PWR9LE-NEXT:    fmr f1, f5
-; PWR9LE-NEXT:    fmr f2, f6
+; PWR9LE-NEXT:    fmr f31, f4 # Vec Defs: F31(VSR31) Vec Uses: F4(VSR4)
+; PWR9LE-NEXT:    fmr f30, f3 # Vec Defs: F30(VSR30) Vec Uses: F3(VSR3)
+; PWR9LE-NEXT:    fmr f4, f2 # Vec Defs: F4(VSR4) Vec Uses: F2(VSR2)
+; PWR9LE-NEXT:    fmr f3, f1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PWR9LE-NEXT:    fmr f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F5(VSR5)
+; PWR9LE-NEXT:    fmr f2, f6 # Vec Defs: F2(VSR2) Vec Uses: F6(VSR6)
 ; PWR9LE-NEXT:    bl __gcc_qadd
 ; PWR9LE-NEXT:    nop
-; PWR9LE-NEXT:    fmr f3, f30
-; PWR9LE-NEXT:    fmr f4, f31
+; PWR9LE-NEXT:    fmr f3, f30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
+; PWR9LE-NEXT:    fmr f4, f31 # Vec Defs: F4(VSR4) Vec Uses: F31(VSR31)
 ; PWR9LE-NEXT:    bl __gcc_qadd
 ; PWR9LE-NEXT:    nop
 ; PWR9LE-NEXT:    addi r1, r1, 48
 ; PWR9LE-NEXT:    ld r0, 16(r1)
 ; PWR9LE-NEXT:    lfd f31, -8(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PWR9LE-NEXT:    lfd f30, -16(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PWR9LE-NEXT:    mtlr r0
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v2ppcf128_b:
 ; PWR9BE:       # %bb.0: # %entry
 ; PWR9BE-NEXT:    mflr r0
 ; PWR9BE-NEXT:    std r0, 16(r1)
 ; PWR9BE-NEXT:    stdu r1, -128(r1)
 ; PWR9BE-NEXT:    stfd f30, 112(r1) # 8-byte Folded Spill
+; PWR9BE-NEXT:    # Vec Uses: F30(VSR30)
 ; PWR9BE-NEXT:    stfd f31, 120(r1) # 8-byte Folded Spill
-; PWR9BE-NEXT:    fmr f31, f4
-; PWR9BE-NEXT:    fmr f30, f3
-; PWR9BE-NEXT:    fmr f4, f2
-; PWR9BE-NEXT:    fmr f3, f1
-; PWR9BE-NEXT:    fmr f1, f5
-; PWR9BE-NEXT:    fmr f2, f6
+; PWR9BE-NEXT:    # Vec Uses: F31(VSR31)
+; PWR9BE-NEXT:    fmr f31, f4 # Vec Defs: F31(VSR31) Vec Uses: F4(VSR4)
+; PWR9BE-NEXT:    fmr f30, f3 # Vec Defs: F30(VSR30) Vec Uses: F3(VSR3)
+; PWR9BE-NEXT:    fmr f4, f2 # Vec Defs: F4(VSR4) Vec Uses: F2(VSR2)
+; PWR9BE-NEXT:    fmr f3, f1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PWR9BE-NEXT:    fmr f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F5(VSR5)
+; PWR9BE-NEXT:    fmr f2, f6 # Vec Defs: F2(VSR2) Vec Uses: F6(VSR6)
 ; PWR9BE-NEXT:    bl __gcc_qadd
 ; PWR9BE-NEXT:    nop
-; PWR9BE-NEXT:    fmr f3, f30
-; PWR9BE-NEXT:    fmr f4, f31
+; PWR9BE-NEXT:    fmr f3, f30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
+; PWR9BE-NEXT:    fmr f4, f31 # Vec Defs: F4(VSR4) Vec Uses: F31(VSR31)
 ; PWR9BE-NEXT:    bl __gcc_qadd
 ; PWR9BE-NEXT:    nop
 ; PWR9BE-NEXT:    lfd f31, 120(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F31(VSR31)
 ; PWR9BE-NEXT:    lfd f30, 112(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F30(VSR30)
 ; PWR9BE-NEXT:    addi r1, r1, 128
 ; PWR9BE-NEXT:    ld r0, 16(r1)
 ; PWR9BE-NEXT:    mtlr r0
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v2ppcf128_b:
 ; PWR10LE:       # %bb.0: # %entry
 ; PWR10LE-NEXT:    mflr r0
 ; PWR10LE-NEXT:    stfd f30, -16(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PWR10LE-NEXT:    stfd f31, -8(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PWR10LE-NEXT:    std r0, 16(r1)
 ; PWR10LE-NEXT:    stdu r1, -48(r1)
-; PWR10LE-NEXT:    fmr f31, f4
-; PWR10LE-NEXT:    fmr f30, f3
-; PWR10LE-NEXT:    fmr f4, f2
-; PWR10LE-NEXT:    fmr f3, f1
-; PWR10LE-NEXT:    fmr f1, f5
-; PWR10LE-NEXT:    fmr f2, f6
+; PWR10LE-NEXT:    fmr f31, f4 # Vec Defs: F31(VSR31) Vec Uses: F4(VSR4)
+; PWR10LE-NEXT:    fmr f30, f3 # Vec Defs: F30(VSR30) Vec Uses: F3(VSR3)
+; PWR10LE-NEXT:    fmr f4, f2 # Vec Defs: F4(VSR4) Vec Uses: F2(VSR2)
+; PWR10LE-NEXT:    fmr f3, f1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PWR10LE-NEXT:    fmr f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F5(VSR5)
+; PWR10LE-NEXT:    fmr f2, f6 # Vec Defs: F2(VSR2) Vec Uses: F6(VSR6)
 ; PWR10LE-NEXT:    bl __gcc_qadd@notoc
-; PWR10LE-NEXT:    fmr f3, f30
-; PWR10LE-NEXT:    fmr f4, f31
+; PWR10LE-NEXT:    fmr f3, f30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
+; PWR10LE-NEXT:    fmr f4, f31 # Vec Defs: F4(VSR4) Vec Uses: F31(VSR31)
 ; PWR10LE-NEXT:    bl __gcc_qadd@notoc
 ; PWR10LE-NEXT:    addi r1, r1, 48
 ; PWR10LE-NEXT:    ld r0, 16(r1)
 ; PWR10LE-NEXT:    lfd f31, -8(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PWR10LE-NEXT:    mtlr r0
 ; PWR10LE-NEXT:    lfd f30, -16(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v2ppcf128_b:
 ; PWR10BE:       # %bb.0: # %entry
 ; PWR10BE-NEXT:    mflr r0
 ; PWR10BE-NEXT:    std r0, 16(r1)
 ; PWR10BE-NEXT:    stdu r1, -128(r1)
 ; PWR10BE-NEXT:    stfd f30, 112(r1) # 8-byte Folded Spill
+; PWR10BE-NEXT:    # Vec Uses: F30(VSR30)
 ; PWR10BE-NEXT:    stfd f31, 120(r1) # 8-byte Folded Spill
-; PWR10BE-NEXT:    fmr f31, f4
-; PWR10BE-NEXT:    fmr f30, f3
-; PWR10BE-NEXT:    fmr f4, f2
-; PWR10BE-NEXT:    fmr f3, f1
-; PWR10BE-NEXT:    fmr f1, f5
-; PWR10BE-NEXT:    fmr f2, f6
+; PWR10BE-NEXT:    # Vec Uses: F31(VSR31)
+; PWR10BE-NEXT:    fmr f31, f4 # Vec Defs: F31(VSR31) Vec Uses: F4(VSR4)
+; PWR10BE-NEXT:    fmr f30, f3 # Vec Defs: F30(VSR30) Vec Uses: F3(VSR3)
+; PWR10BE-NEXT:    fmr f4, f2 # Vec Defs: F4(VSR4) Vec Uses: F2(VSR2)
+; PWR10BE-NEXT:    fmr f3, f1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PWR10BE-NEXT:    fmr f1, f5 # Vec Defs: F1(VSR1) Vec Uses: F5(VSR5)
+; PWR10BE-NEXT:    fmr f2, f6 # Vec Defs: F2(VSR2) Vec Uses: F6(VSR6)
 ; PWR10BE-NEXT:    bl __gcc_qadd
 ; PWR10BE-NEXT:    nop
-; PWR10BE-NEXT:    fmr f3, f30
-; PWR10BE-NEXT:    fmr f4, f31
+; PWR10BE-NEXT:    fmr f3, f30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
+; PWR10BE-NEXT:    fmr f4, f31 # Vec Defs: F4(VSR4) Vec Uses: F31(VSR31)
 ; PWR10BE-NEXT:    bl __gcc_qadd
 ; PWR10BE-NEXT:    nop
 ; PWR10BE-NEXT:    lfd f31, 120(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F31(VSR31)
 ; PWR10BE-NEXT:    lfd f30, 112(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F30(VSR30)
 ; PWR10BE-NEXT:    addi r1, r1, 128
 ; PWR10BE-NEXT:    ld r0, 16(r1)
 ; PWR10BE-NEXT:    mtlr r0
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call ppc_fp128 @llvm.vector.reduce.fadd.v2ppcf128(ppc_fp128 %b, <2 x ppc_fp128> %a)
   ret ppc_fp128 %0
 }
 
 define dso_local ppc_fp128 @v2ppcf128_fast(<2 x ppc_fp128> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v2ppcf128_fast:
 ; PWR9LE:       # %bb.0: # %entry
 ; PWR9LE-NEXT:    mflr r0
 ; PWR9LE-NEXT:    std r0, 16(r1)
 ; PWR9LE-NEXT:    stdu r1, -64(r1)
 ; PWR9LE-NEXT:    bl __gcc_qadd
 ; PWR9LE-NEXT:    nop
-; PWR9LE-NEXT:    stfd f2, 40(r1)
-; PWR9LE-NEXT:    stfd f1, 32(r1)
-; PWR9LE-NEXT:    lxv vs1, 32(r1)
-; PWR9LE-NEXT:    xxswapd vs2, vs1
+; PWR9LE-NEXT:    stfd f2, 40(r1) # Vec Uses: F2(VSR2)
+; PWR9LE-NEXT:    stfd f1, 32(r1) # Vec Uses: F1(VSR1)
+; PWR9LE-NEXT:    lxv vs1, 32(r1) # Vec Defs: VSL1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs2, vs1 # Vec Defs: VSL2(VSR2) Vec Uses: VSL1(VSR1)VSL1(VSR1)
 ; PWR9LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR9LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PWR9LE-NEXT:    addi r1, r1, 64
 ; PWR9LE-NEXT:    ld r0, 16(r1)
 ; PWR9LE-NEXT:    mtlr r0
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v2ppcf128_fast:
 ; PWR9BE:       # %bb.0: # %entry
 ; PWR9BE-NEXT:    mflr r0
 ; PWR9BE-NEXT:    std r0, 16(r1)
 ; PWR9BE-NEXT:    stdu r1, -144(r1)
 ; PWR9BE-NEXT:    bl __gcc_qadd
 ; PWR9BE-NEXT:    nop
-; PWR9BE-NEXT:    stfd f2, 120(r1)
-; PWR9BE-NEXT:    stfd f1, 112(r1)
-; PWR9BE-NEXT:    lxv vs1, 112(r1)
-; PWR9BE-NEXT:    xxswapd vs2, vs1
+; PWR9BE-NEXT:    stfd f2, 120(r1) # Vec Uses: F2(VSR2)
+; PWR9BE-NEXT:    stfd f1, 112(r1) # Vec Uses: F1(VSR1)
+; PWR9BE-NEXT:    lxv vs1, 112(r1) # Vec Defs: VSL1(VSR1)
+; PWR9BE-NEXT:    xxswapd vs2, vs1 # Vec Defs: VSL2(VSR2) Vec Uses: VSL1(VSR1)VSL1(VSR1)
 ; PWR9BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR9BE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PWR9BE-NEXT:    addi r1, r1, 144
 ; PWR9BE-NEXT:    ld r0, 16(r1)
 ; PWR9BE-NEXT:    mtlr r0
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v2ppcf128_fast:
 ; PWR10LE:       # %bb.0: # %entry
 ; PWR10LE-NEXT:    mflr r0
 ; PWR10LE-NEXT:    std r0, 16(r1)
 ; PWR10LE-NEXT:    stdu r1, -64(r1)
 ; PWR10LE-NEXT:    bl __gcc_qadd@notoc
-; PWR10LE-NEXT:    stfd f2, 40(r1)
-; PWR10LE-NEXT:    stfd f1, 32(r1)
-; PWR10LE-NEXT:    lxv vs1, 32(r1)
-; PWR10LE-NEXT:    xxswapd vs2, vs1
+; PWR10LE-NEXT:    stfd f2, 40(r1) # Vec Uses: F2(VSR2)
+; PWR10LE-NEXT:    stfd f1, 32(r1) # Vec Uses: F1(VSR1)
+; PWR10LE-NEXT:    lxv vs1, 32(r1) # Vec Defs: VSL1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs2, vs1 # Vec Defs: VSL2(VSR2) Vec Uses: VSL1(VSR1)VSL1(VSR1)
 ; PWR10LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR10LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PWR10LE-NEXT:    addi r1, r1, 64
 ; PWR10LE-NEXT:    ld r0, 16(r1)
 ; PWR10LE-NEXT:    mtlr r0
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v2ppcf128_fast:
 ; PWR10BE:       # %bb.0: # %entry
 ; PWR10BE-NEXT:    mflr r0
 ; PWR10BE-NEXT:    std r0, 16(r1)
 ; PWR10BE-NEXT:    stdu r1, -144(r1)
 ; PWR10BE-NEXT:    bl __gcc_qadd
 ; PWR10BE-NEXT:    nop
-; PWR10BE-NEXT:    stfd f2, 120(r1)
-; PWR10BE-NEXT:    stfd f1, 112(r1)
-; PWR10BE-NEXT:    lxv vs1, 112(r1)
-; PWR10BE-NEXT:    xxswapd vs2, vs1
+; PWR10BE-NEXT:    stfd f2, 120(r1) # Vec Uses: F2(VSR2)
+; PWR10BE-NEXT:    stfd f1, 112(r1) # Vec Uses: F1(VSR1)
+; PWR10BE-NEXT:    lxv vs1, 112(r1) # Vec Defs: VSL1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs2, vs1 # Vec Defs: VSL2(VSR2) Vec Uses: VSL1(VSR1)VSL1(VSR1)
 ; PWR10BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR10BE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PWR10BE-NEXT:    addi r1, r1, 144
 ; PWR10BE-NEXT:    ld r0, 16(r1)
 ; PWR10BE-NEXT:    mtlr r0
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call fast ppc_fp128 @llvm.vector.reduce.fadd.v2ppcf128(ppc_fp128 0xM80000000000000000000000000000000, <2 x ppc_fp128> %a)
   ret ppc_fp128 %0
 }
 
 define dso_local ppc_fp128 @v4ppcf128(<4 x ppc_fp128> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v4ppcf128:
 ; PWR9LE:       # %bb.0: # %entry
 ; PWR9LE-NEXT:    mflr r0
 ; PWR9LE-NEXT:    stfd f28, -32(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F28(VSR28)
 ; PWR9LE-NEXT:    stfd f29, -24(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F29(VSR29)
 ; PWR9LE-NEXT:    stfd f30, -16(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PWR9LE-NEXT:    stfd f31, -8(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PWR9LE-NEXT:    std r0, 16(r1)
 ; PWR9LE-NEXT:    stdu r1, -64(r1)
-; PWR9LE-NEXT:    fmr f31, f8
-; PWR9LE-NEXT:    fmr f30, f7
-; PWR9LE-NEXT:    fmr f29, f6
-; PWR9LE-NEXT:    fmr f28, f5
+; PWR9LE-NEXT:    fmr f31, f8 # Vec Defs: F31(VSR31) Vec Uses: F8(VSR8)
+; PWR9LE-NEXT:    fmr f30, f7 # Vec Defs: F30(VSR30) Vec Uses: F7(VSR7)
+; PWR9LE-NEXT:    fmr f29, f6 # Vec Defs: F29(VSR29) Vec Uses: F6(VSR6)
+; PWR9LE-NEXT:    fmr f28, f5 # Vec Defs: F28(VSR28) Vec Uses: F5(VSR5)
 ; PWR9LE-NEXT:    bl __gcc_qadd
 ; PWR9LE-NEXT:    nop
-; PWR9LE-NEXT:    fmr f3, f28
-; PWR9LE-NEXT:    fmr f4, f29
+; PWR9LE-NEXT:    fmr f3, f28 # Vec Defs: F3(VSR3) Vec Uses: F28(VSR28)
+; PWR9LE-NEXT:    fmr f4, f29 # Vec Defs: F4(VSR4) Vec Uses: F29(VSR29)
 ; PWR9LE-NEXT:    bl __gcc_qadd
 ; PWR9LE-NEXT:    nop
-; PWR9LE-NEXT:    fmr f3, f30
-; PWR9LE-NEXT:    fmr f4, f31
+; PWR9LE-NEXT:    fmr f3, f30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
+; PWR9LE-NEXT:    fmr f4, f31 # Vec Defs: F4(VSR4) Vec Uses: F31(VSR31)
 ; PWR9LE-NEXT:    bl __gcc_qadd
 ; PWR9LE-NEXT:    nop
 ; PWR9LE-NEXT:    addi r1, r1, 64
 ; PWR9LE-NEXT:    ld r0, 16(r1)
 ; PWR9LE-NEXT:    lfd f31, -8(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PWR9LE-NEXT:    lfd f30, -16(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PWR9LE-NEXT:    mtlr r0
 ; PWR9LE-NEXT:    lfd f29, -24(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F29(VSR29)
 ; PWR9LE-NEXT:    lfd f28, -32(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F28(VSR28)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v4ppcf128:
 ; PWR9BE:       # %bb.0: # %entry
 ; PWR9BE-NEXT:    mflr r0
 ; PWR9BE-NEXT:    std r0, 16(r1)
 ; PWR9BE-NEXT:    stdu r1, -144(r1)
 ; PWR9BE-NEXT:    stfd f28, 112(r1) # 8-byte Folded Spill
+; PWR9BE-NEXT:    # Vec Uses: F28(VSR28)
 ; PWR9BE-NEXT:    stfd f29, 120(r1) # 8-byte Folded Spill
+; PWR9BE-NEXT:    # Vec Uses: F29(VSR29)
 ; PWR9BE-NEXT:    stfd f30, 128(r1) # 8-byte Folded Spill
+; PWR9BE-NEXT:    # Vec Uses: F30(VSR30)
 ; PWR9BE-NEXT:    stfd f31, 136(r1) # 8-byte Folded Spill
-; PWR9BE-NEXT:    fmr f31, f8
-; PWR9BE-NEXT:    fmr f30, f7
-; PWR9BE-NEXT:    fmr f29, f6
-; PWR9BE-NEXT:    fmr f28, f5
+; PWR9BE-NEXT:    # Vec Uses: F31(VSR31)
+; PWR9BE-NEXT:    fmr f31, f8 # Vec Defs: F31(VSR31) Vec Uses: F8(VSR8)
+; PWR9BE-NEXT:    fmr f30, f7 # Vec Defs: F30(VSR30) Vec Uses: F7(VSR7)
+; PWR9BE-NEXT:    fmr f29, f6 # Vec Defs: F29(VSR29) Vec Uses: F6(VSR6)
+; PWR9BE-NEXT:    fmr f28, f5 # Vec Defs: F28(VSR28) Vec Uses: F5(VSR5)
 ; PWR9BE-NEXT:    bl __gcc_qadd
 ; PWR9BE-NEXT:    nop
-; PWR9BE-NEXT:    fmr f3, f28
-; PWR9BE-NEXT:    fmr f4, f29
+; PWR9BE-NEXT:    fmr f3, f28 # Vec Defs: F3(VSR3) Vec Uses: F28(VSR28)
+; PWR9BE-NEXT:    fmr f4, f29 # Vec Defs: F4(VSR4) Vec Uses: F29(VSR29)
 ; PWR9BE-NEXT:    bl __gcc_qadd
 ; PWR9BE-NEXT:    nop
-; PWR9BE-NEXT:    fmr f3, f30
-; PWR9BE-NEXT:    fmr f4, f31
+; PWR9BE-NEXT:    fmr f3, f30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
+; PWR9BE-NEXT:    fmr f4, f31 # Vec Defs: F4(VSR4) Vec Uses: F31(VSR31)
 ; PWR9BE-NEXT:    bl __gcc_qadd
 ; PWR9BE-NEXT:    nop
 ; PWR9BE-NEXT:    lfd f31, 136(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F31(VSR31)
 ; PWR9BE-NEXT:    lfd f30, 128(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F30(VSR30)
 ; PWR9BE-NEXT:    lfd f29, 120(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F29(VSR29)
 ; PWR9BE-NEXT:    lfd f28, 112(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F28(VSR28)
 ; PWR9BE-NEXT:    addi r1, r1, 144
 ; PWR9BE-NEXT:    ld r0, 16(r1)
 ; PWR9BE-NEXT:    mtlr r0
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v4ppcf128:
 ; PWR10LE:       # %bb.0: # %entry
 ; PWR10LE-NEXT:    mflr r0
 ; PWR10LE-NEXT:    stfd f28, -32(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F28(VSR28)
 ; PWR10LE-NEXT:    stfd f29, -24(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F29(VSR29)
 ; PWR10LE-NEXT:    stfd f30, -16(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PWR10LE-NEXT:    stfd f31, -8(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PWR10LE-NEXT:    std r0, 16(r1)
 ; PWR10LE-NEXT:    stdu r1, -64(r1)
-; PWR10LE-NEXT:    fmr f31, f8
-; PWR10LE-NEXT:    fmr f30, f7
-; PWR10LE-NEXT:    fmr f29, f6
-; PWR10LE-NEXT:    fmr f28, f5
+; PWR10LE-NEXT:    fmr f31, f8 # Vec Defs: F31(VSR31) Vec Uses: F8(VSR8)
+; PWR10LE-NEXT:    fmr f30, f7 # Vec Defs: F30(VSR30) Vec Uses: F7(VSR7)
+; PWR10LE-NEXT:    fmr f29, f6 # Vec Defs: F29(VSR29) Vec Uses: F6(VSR6)
+; PWR10LE-NEXT:    fmr f28, f5 # Vec Defs: F28(VSR28) Vec Uses: F5(VSR5)
 ; PWR10LE-NEXT:    bl __gcc_qadd@notoc
-; PWR10LE-NEXT:    fmr f3, f28
-; PWR10LE-NEXT:    fmr f4, f29
+; PWR10LE-NEXT:    fmr f3, f28 # Vec Defs: F3(VSR3) Vec Uses: F28(VSR28)
+; PWR10LE-NEXT:    fmr f4, f29 # Vec Defs: F4(VSR4) Vec Uses: F29(VSR29)
 ; PWR10LE-NEXT:    bl __gcc_qadd@notoc
-; PWR10LE-NEXT:    fmr f3, f30
-; PWR10LE-NEXT:    fmr f4, f31
+; PWR10LE-NEXT:    fmr f3, f30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
+; PWR10LE-NEXT:    fmr f4, f31 # Vec Defs: F4(VSR4) Vec Uses: F31(VSR31)
 ; PWR10LE-NEXT:    bl __gcc_qadd@notoc
 ; PWR10LE-NEXT:    addi r1, r1, 64
 ; PWR10LE-NEXT:    ld r0, 16(r1)
 ; PWR10LE-NEXT:    lfd f31, -8(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PWR10LE-NEXT:    mtlr r0
 ; PWR10LE-NEXT:    lfd f30, -16(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PWR10LE-NEXT:    lfd f29, -24(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F29(VSR29)
 ; PWR10LE-NEXT:    lfd f28, -32(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F28(VSR28)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v4ppcf128:
 ; PWR10BE:       # %bb.0: # %entry
 ; PWR10BE-NEXT:    mflr r0
 ; PWR10BE-NEXT:    std r0, 16(r1)
 ; PWR10BE-NEXT:    stdu r1, -144(r1)
 ; PWR10BE-NEXT:    stfd f28, 112(r1) # 8-byte Folded Spill
+; PWR10BE-NEXT:    # Vec Uses: F28(VSR28)
 ; PWR10BE-NEXT:    stfd f29, 120(r1) # 8-byte Folded Spill
-; PWR10BE-NEXT:    fmr f29, f6
-; PWR10BE-NEXT:    fmr f28, f5
+; PWR10BE-NEXT:    # Vec Uses: F29(VSR29)
+; PWR10BE-NEXT:    fmr f29, f6 # Vec Defs: F29(VSR29) Vec Uses: F6(VSR6)
+; PWR10BE-NEXT:    fmr f28, f5 # Vec Defs: F28(VSR28) Vec Uses: F5(VSR5)
 ; PWR10BE-NEXT:    stfd f30, 128(r1) # 8-byte Folded Spill
+; PWR10BE-NEXT:    # Vec Uses: F30(VSR30)
 ; PWR10BE-NEXT:    stfd f31, 136(r1) # 8-byte Folded Spill
-; PWR10BE-NEXT:    fmr f31, f8
-; PWR10BE-NEXT:    fmr f30, f7
+; PWR10BE-NEXT:    # Vec Uses: F31(VSR31)
+; PWR10BE-NEXT:    fmr f31, f8 # Vec Defs: F31(VSR31) Vec Uses: F8(VSR8)
+; PWR10BE-NEXT:    fmr f30, f7 # Vec Defs: F30(VSR30) Vec Uses: F7(VSR7)
 ; PWR10BE-NEXT:    bl __gcc_qadd
 ; PWR10BE-NEXT:    nop
-; PWR10BE-NEXT:    fmr f3, f28
-; PWR10BE-NEXT:    fmr f4, f29
+; PWR10BE-NEXT:    fmr f3, f28 # Vec Defs: F3(VSR3) Vec Uses: F28(VSR28)
+; PWR10BE-NEXT:    fmr f4, f29 # Vec Defs: F4(VSR4) Vec Uses: F29(VSR29)
 ; PWR10BE-NEXT:    bl __gcc_qadd
 ; PWR10BE-NEXT:    nop
-; PWR10BE-NEXT:    fmr f3, f30
-; PWR10BE-NEXT:    fmr f4, f31
+; PWR10BE-NEXT:    fmr f3, f30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
+; PWR10BE-NEXT:    fmr f4, f31 # Vec Defs: F4(VSR4) Vec Uses: F31(VSR31)
 ; PWR10BE-NEXT:    bl __gcc_qadd
 ; PWR10BE-NEXT:    nop
 ; PWR10BE-NEXT:    lfd f31, 136(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F31(VSR31)
 ; PWR10BE-NEXT:    lfd f30, 128(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F30(VSR30)
 ; PWR10BE-NEXT:    lfd f29, 120(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F29(VSR29)
 ; PWR10BE-NEXT:    lfd f28, 112(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F28(VSR28)
 ; PWR10BE-NEXT:    addi r1, r1, 144
 ; PWR10BE-NEXT:    ld r0, 16(r1)
 ; PWR10BE-NEXT:    mtlr r0
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call ppc_fp128 @llvm.vector.reduce.fadd.v4ppcf128(ppc_fp128 0xM80000000000000000000000000000000, <4 x ppc_fp128> %a)
   ret ppc_fp128 %0
 }
 
 define dso_local ppc_fp128 @v4ppcf128_b(<4 x ppc_fp128> %a, ppc_fp128 %b) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v4ppcf128_b:
 ; PWR9LE:       # %bb.0: # %entry
 ; PWR9LE-NEXT:    mflr r0
 ; PWR9LE-NEXT:    stfd f26, -48(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F26(VSR26)
 ; PWR9LE-NEXT:    stfd f27, -40(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F27(VSR27)
 ; PWR9LE-NEXT:    stfd f28, -32(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F28(VSR28)
 ; PWR9LE-NEXT:    stfd f29, -24(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F29(VSR29)
 ; PWR9LE-NEXT:    stfd f30, -16(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PWR9LE-NEXT:    stfd f31, -8(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PWR9LE-NEXT:    std r0, 16(r1)
 ; PWR9LE-NEXT:    stdu r1, -80(r1)
-; PWR9LE-NEXT:    fmr f27, f4
-; PWR9LE-NEXT:    fmr f26, f3
-; PWR9LE-NEXT:    fmr f4, f2
-; PWR9LE-NEXT:    fmr f3, f1
-; PWR9LE-NEXT:    fmr f1, f9
-; PWR9LE-NEXT:    fmr f2, f10
-; PWR9LE-NEXT:    fmr f31, f8
-; PWR9LE-NEXT:    fmr f30, f7
-; PWR9LE-NEXT:    fmr f29, f6
-; PWR9LE-NEXT:    fmr f28, f5
+; PWR9LE-NEXT:    fmr f27, f4 # Vec Defs: F27(VSR27) Vec Uses: F4(VSR4)
+; PWR9LE-NEXT:    fmr f26, f3 # Vec Defs: F26(VSR26) Vec Uses: F3(VSR3)
+; PWR9LE-NEXT:    fmr f4, f2 # Vec Defs: F4(VSR4) Vec Uses: F2(VSR2)
+; PWR9LE-NEXT:    fmr f3, f1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PWR9LE-NEXT:    fmr f1, f9 # Vec Defs: F1(VSR1) Vec Uses: F9(VSR9)
+; PWR9LE-NEXT:    fmr f2, f10 # Vec Defs: F2(VSR2) Vec Uses: F10(VSR10)
+; PWR9LE-NEXT:    fmr f31, f8 # Vec Defs: F31(VSR31) Vec Uses: F8(VSR8)
+; PWR9LE-NEXT:    fmr f30, f7 # Vec Defs: F30(VSR30) Vec Uses: F7(VSR7)
+; PWR9LE-NEXT:    fmr f29, f6 # Vec Defs: F29(VSR29) Vec Uses: F6(VSR6)
+; PWR9LE-NEXT:    fmr f28, f5 # Vec Defs: F28(VSR28) Vec Uses: F5(VSR5)
 ; PWR9LE-NEXT:    bl __gcc_qadd
 ; PWR9LE-NEXT:    nop
-; PWR9LE-NEXT:    fmr f3, f26
-; PWR9LE-NEXT:    fmr f4, f27
+; PWR9LE-NEXT:    fmr f3, f26 # Vec Defs: F3(VSR3) Vec Uses: F26(VSR26)
+; PWR9LE-NEXT:    fmr f4, f27 # Vec Defs: F4(VSR4) Vec Uses: F27(VSR27)
 ; PWR9LE-NEXT:    bl __gcc_qadd
 ; PWR9LE-NEXT:    nop
-; PWR9LE-NEXT:    fmr f3, f28
-; PWR9LE-NEXT:    fmr f4, f29
+; PWR9LE-NEXT:    fmr f3, f28 # Vec Defs: F3(VSR3) Vec Uses: F28(VSR28)
+; PWR9LE-NEXT:    fmr f4, f29 # Vec Defs: F4(VSR4) Vec Uses: F29(VSR29)
 ; PWR9LE-NEXT:    bl __gcc_qadd
 ; PWR9LE-NEXT:    nop
-; PWR9LE-NEXT:    fmr f3, f30
-; PWR9LE-NEXT:    fmr f4, f31
+; PWR9LE-NEXT:    fmr f3, f30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
+; PWR9LE-NEXT:    fmr f4, f31 # Vec Defs: F4(VSR4) Vec Uses: F31(VSR31)
 ; PWR9LE-NEXT:    bl __gcc_qadd
 ; PWR9LE-NEXT:    nop
 ; PWR9LE-NEXT:    addi r1, r1, 80
 ; PWR9LE-NEXT:    ld r0, 16(r1)
 ; PWR9LE-NEXT:    lfd f31, -8(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PWR9LE-NEXT:    lfd f30, -16(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PWR9LE-NEXT:    mtlr r0
 ; PWR9LE-NEXT:    lfd f29, -24(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F29(VSR29)
 ; PWR9LE-NEXT:    lfd f28, -32(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F28(VSR28)
 ; PWR9LE-NEXT:    lfd f27, -40(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F27(VSR27)
 ; PWR9LE-NEXT:    lfd f26, -48(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F26(VSR26)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v4ppcf128_b:
 ; PWR9BE:       # %bb.0: # %entry
 ; PWR9BE-NEXT:    mflr r0
 ; PWR9BE-NEXT:    std r0, 16(r1)
 ; PWR9BE-NEXT:    stdu r1, -160(r1)
 ; PWR9BE-NEXT:    stfd f26, 112(r1) # 8-byte Folded Spill
+; PWR9BE-NEXT:    # Vec Uses: F26(VSR26)
 ; PWR9BE-NEXT:    stfd f27, 120(r1) # 8-byte Folded Spill
-; PWR9BE-NEXT:    fmr f27, f4
-; PWR9BE-NEXT:    fmr f26, f3
-; PWR9BE-NEXT:    fmr f4, f2
-; PWR9BE-NEXT:    fmr f3, f1
-; PWR9BE-NEXT:    fmr f1, f9
-; PWR9BE-NEXT:    fmr f2, f10
+; PWR9BE-NEXT:    # Vec Uses: F27(VSR27)
+; PWR9BE-NEXT:    fmr f27, f4 # Vec Defs: F27(VSR27) Vec Uses: F4(VSR4)
+; PWR9BE-NEXT:    fmr f26, f3 # Vec Defs: F26(VSR26) Vec Uses: F3(VSR3)
+; PWR9BE-NEXT:    fmr f4, f2 # Vec Defs: F4(VSR4) Vec Uses: F2(VSR2)
+; PWR9BE-NEXT:    fmr f3, f1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PWR9BE-NEXT:    fmr f1, f9 # Vec Defs: F1(VSR1) Vec Uses: F9(VSR9)
+; PWR9BE-NEXT:    fmr f2, f10 # Vec Defs: F2(VSR2) Vec Uses: F10(VSR10)
 ; PWR9BE-NEXT:    stfd f28, 128(r1) # 8-byte Folded Spill
+; PWR9BE-NEXT:    # Vec Uses: F28(VSR28)
 ; PWR9BE-NEXT:    stfd f29, 136(r1) # 8-byte Folded Spill
+; PWR9BE-NEXT:    # Vec Uses: F29(VSR29)
 ; PWR9BE-NEXT:    stfd f30, 144(r1) # 8-byte Folded Spill
+; PWR9BE-NEXT:    # Vec Uses: F30(VSR30)
 ; PWR9BE-NEXT:    stfd f31, 152(r1) # 8-byte Folded Spill
-; PWR9BE-NEXT:    fmr f31, f8
-; PWR9BE-NEXT:    fmr f30, f7
-; PWR9BE-NEXT:    fmr f29, f6
-; PWR9BE-NEXT:    fmr f28, f5
+; PWR9BE-NEXT:    # Vec Uses: F31(VSR31)
+; PWR9BE-NEXT:    fmr f31, f8 # Vec Defs: F31(VSR31) Vec Uses: F8(VSR8)
+; PWR9BE-NEXT:    fmr f30, f7 # Vec Defs: F30(VSR30) Vec Uses: F7(VSR7)
+; PWR9BE-NEXT:    fmr f29, f6 # Vec Defs: F29(VSR29) Vec Uses: F6(VSR6)
+; PWR9BE-NEXT:    fmr f28, f5 # Vec Defs: F28(VSR28) Vec Uses: F5(VSR5)
 ; PWR9BE-NEXT:    bl __gcc_qadd
 ; PWR9BE-NEXT:    nop
-; PWR9BE-NEXT:    fmr f3, f26
-; PWR9BE-NEXT:    fmr f4, f27
+; PWR9BE-NEXT:    fmr f3, f26 # Vec Defs: F3(VSR3) Vec Uses: F26(VSR26)
+; PWR9BE-NEXT:    fmr f4, f27 # Vec Defs: F4(VSR4) Vec Uses: F27(VSR27)
 ; PWR9BE-NEXT:    bl __gcc_qadd
 ; PWR9BE-NEXT:    nop
-; PWR9BE-NEXT:    fmr f3, f28
-; PWR9BE-NEXT:    fmr f4, f29
+; PWR9BE-NEXT:    fmr f3, f28 # Vec Defs: F3(VSR3) Vec Uses: F28(VSR28)
+; PWR9BE-NEXT:    fmr f4, f29 # Vec Defs: F4(VSR4) Vec Uses: F29(VSR29)
 ; PWR9BE-NEXT:    bl __gcc_qadd
 ; PWR9BE-NEXT:    nop
-; PWR9BE-NEXT:    fmr f3, f30
-; PWR9BE-NEXT:    fmr f4, f31
+; PWR9BE-NEXT:    fmr f3, f30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
+; PWR9BE-NEXT:    fmr f4, f31 # Vec Defs: F4(VSR4) Vec Uses: F31(VSR31)
 ; PWR9BE-NEXT:    bl __gcc_qadd
 ; PWR9BE-NEXT:    nop
 ; PWR9BE-NEXT:    lfd f31, 152(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F31(VSR31)
 ; PWR9BE-NEXT:    lfd f30, 144(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F30(VSR30)
 ; PWR9BE-NEXT:    lfd f29, 136(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F29(VSR29)
 ; PWR9BE-NEXT:    lfd f28, 128(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F28(VSR28)
 ; PWR9BE-NEXT:    lfd f27, 120(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F27(VSR27)
 ; PWR9BE-NEXT:    lfd f26, 112(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F26(VSR26)
 ; PWR9BE-NEXT:    addi r1, r1, 160
 ; PWR9BE-NEXT:    ld r0, 16(r1)
 ; PWR9BE-NEXT:    mtlr r0
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v4ppcf128_b:
 ; PWR10LE:       # %bb.0: # %entry
 ; PWR10LE-NEXT:    mflr r0
 ; PWR10LE-NEXT:    stfd f26, -48(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F26(VSR26)
 ; PWR10LE-NEXT:    stfd f27, -40(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F27(VSR27)
 ; PWR10LE-NEXT:    stfd f28, -32(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F28(VSR28)
 ; PWR10LE-NEXT:    stfd f29, -24(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F29(VSR29)
 ; PWR10LE-NEXT:    stfd f30, -16(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PWR10LE-NEXT:    stfd f31, -8(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PWR10LE-NEXT:    std r0, 16(r1)
 ; PWR10LE-NEXT:    stdu r1, -80(r1)
-; PWR10LE-NEXT:    fmr f27, f4
-; PWR10LE-NEXT:    fmr f26, f3
-; PWR10LE-NEXT:    fmr f4, f2
-; PWR10LE-NEXT:    fmr f3, f1
-; PWR10LE-NEXT:    fmr f1, f9
-; PWR10LE-NEXT:    fmr f2, f10
-; PWR10LE-NEXT:    fmr f31, f8
-; PWR10LE-NEXT:    fmr f30, f7
-; PWR10LE-NEXT:    fmr f29, f6
-; PWR10LE-NEXT:    fmr f28, f5
+; PWR10LE-NEXT:    fmr f27, f4 # Vec Defs: F27(VSR27) Vec Uses: F4(VSR4)
+; PWR10LE-NEXT:    fmr f26, f3 # Vec Defs: F26(VSR26) Vec Uses: F3(VSR3)
+; PWR10LE-NEXT:    fmr f4, f2 # Vec Defs: F4(VSR4) Vec Uses: F2(VSR2)
+; PWR10LE-NEXT:    fmr f3, f1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PWR10LE-NEXT:    fmr f1, f9 # Vec Defs: F1(VSR1) Vec Uses: F9(VSR9)
+; PWR10LE-NEXT:    fmr f2, f10 # Vec Defs: F2(VSR2) Vec Uses: F10(VSR10)
+; PWR10LE-NEXT:    fmr f31, f8 # Vec Defs: F31(VSR31) Vec Uses: F8(VSR8)
+; PWR10LE-NEXT:    fmr f30, f7 # Vec Defs: F30(VSR30) Vec Uses: F7(VSR7)
+; PWR10LE-NEXT:    fmr f29, f6 # Vec Defs: F29(VSR29) Vec Uses: F6(VSR6)
+; PWR10LE-NEXT:    fmr f28, f5 # Vec Defs: F28(VSR28) Vec Uses: F5(VSR5)
 ; PWR10LE-NEXT:    bl __gcc_qadd@notoc
-; PWR10LE-NEXT:    fmr f3, f26
-; PWR10LE-NEXT:    fmr f4, f27
+; PWR10LE-NEXT:    fmr f3, f26 # Vec Defs: F3(VSR3) Vec Uses: F26(VSR26)
+; PWR10LE-NEXT:    fmr f4, f27 # Vec Defs: F4(VSR4) Vec Uses: F27(VSR27)
 ; PWR10LE-NEXT:    bl __gcc_qadd@notoc
-; PWR10LE-NEXT:    fmr f3, f28
-; PWR10LE-NEXT:    fmr f4, f29
+; PWR10LE-NEXT:    fmr f3, f28 # Vec Defs: F3(VSR3) Vec Uses: F28(VSR28)
+; PWR10LE-NEXT:    fmr f4, f29 # Vec Defs: F4(VSR4) Vec Uses: F29(VSR29)
 ; PWR10LE-NEXT:    bl __gcc_qadd@notoc
-; PWR10LE-NEXT:    fmr f3, f30
-; PWR10LE-NEXT:    fmr f4, f31
+; PWR10LE-NEXT:    fmr f3, f30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
+; PWR10LE-NEXT:    fmr f4, f31 # Vec Defs: F4(VSR4) Vec Uses: F31(VSR31)
 ; PWR10LE-NEXT:    bl __gcc_qadd@notoc
 ; PWR10LE-NEXT:    addi r1, r1, 80
 ; PWR10LE-NEXT:    ld r0, 16(r1)
 ; PWR10LE-NEXT:    lfd f31, -8(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PWR10LE-NEXT:    mtlr r0
 ; PWR10LE-NEXT:    lfd f30, -16(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PWR10LE-NEXT:    lfd f29, -24(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F29(VSR29)
 ; PWR10LE-NEXT:    lfd f28, -32(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F28(VSR28)
 ; PWR10LE-NEXT:    lfd f27, -40(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F27(VSR27)
 ; PWR10LE-NEXT:    lfd f26, -48(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F26(VSR26)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v4ppcf128_b:
 ; PWR10BE:       # %bb.0: # %entry
 ; PWR10BE-NEXT:    mflr r0
 ; PWR10BE-NEXT:    std r0, 16(r1)
 ; PWR10BE-NEXT:    stdu r1, -160(r1)
 ; PWR10BE-NEXT:    stfd f26, 112(r1) # 8-byte Folded Spill
+; PWR10BE-NEXT:    # Vec Uses: F26(VSR26)
 ; PWR10BE-NEXT:    stfd f27, 120(r1) # 8-byte Folded Spill
-; PWR10BE-NEXT:    fmr f27, f4
-; PWR10BE-NEXT:    fmr f26, f3
-; PWR10BE-NEXT:    fmr f4, f2
-; PWR10BE-NEXT:    fmr f3, f1
-; PWR10BE-NEXT:    fmr f1, f9
+; PWR10BE-NEXT:    # Vec Uses: F27(VSR27)
+; PWR10BE-NEXT:    fmr f27, f4 # Vec Defs: F27(VSR27) Vec Uses: F4(VSR4)
+; PWR10BE-NEXT:    fmr f26, f3 # Vec Defs: F26(VSR26) Vec Uses: F3(VSR3)
+; PWR10BE-NEXT:    fmr f4, f2 # Vec Defs: F4(VSR4) Vec Uses: F2(VSR2)
+; PWR10BE-NEXT:    fmr f3, f1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PWR10BE-NEXT:    fmr f1, f9 # Vec Defs: F1(VSR1) Vec Uses: F9(VSR9)
 ; PWR10BE-NEXT:    stfd f28, 128(r1) # 8-byte Folded Spill
+; PWR10BE-NEXT:    # Vec Uses: F28(VSR28)
 ; PWR10BE-NEXT:    stfd f29, 136(r1) # 8-byte Folded Spill
-; PWR10BE-NEXT:    fmr f2, f10
-; PWR10BE-NEXT:    fmr f29, f6
-; PWR10BE-NEXT:    fmr f28, f5
+; PWR10BE-NEXT:    # Vec Uses: F29(VSR29)
+; PWR10BE-NEXT:    fmr f2, f10 # Vec Defs: F2(VSR2) Vec Uses: F10(VSR10)
+; PWR10BE-NEXT:    fmr f29, f6 # Vec Defs: F29(VSR29) Vec Uses: F6(VSR6)
+; PWR10BE-NEXT:    fmr f28, f5 # Vec Defs: F28(VSR28) Vec Uses: F5(VSR5)
 ; PWR10BE-NEXT:    stfd f30, 144(r1) # 8-byte Folded Spill
+; PWR10BE-NEXT:    # Vec Uses: F30(VSR30)
 ; PWR10BE-NEXT:    stfd f31, 152(r1) # 8-byte Folded Spill
-; PWR10BE-NEXT:    fmr f31, f8
-; PWR10BE-NEXT:    fmr f30, f7
+; PWR10BE-NEXT:    # Vec Uses: F31(VSR31)
+; PWR10BE-NEXT:    fmr f31, f8 # Vec Defs: F31(VSR31) Vec Uses: F8(VSR8)
+; PWR10BE-NEXT:    fmr f30, f7 # Vec Defs: F30(VSR30) Vec Uses: F7(VSR7)
 ; PWR10BE-NEXT:    bl __gcc_qadd
 ; PWR10BE-NEXT:    nop
-; PWR10BE-NEXT:    fmr f3, f26
-; PWR10BE-NEXT:    fmr f4, f27
+; PWR10BE-NEXT:    fmr f3, f26 # Vec Defs: F3(VSR3) Vec Uses: F26(VSR26)
+; PWR10BE-NEXT:    fmr f4, f27 # Vec Defs: F4(VSR4) Vec Uses: F27(VSR27)
 ; PWR10BE-NEXT:    bl __gcc_qadd
 ; PWR10BE-NEXT:    nop
-; PWR10BE-NEXT:    fmr f3, f28
-; PWR10BE-NEXT:    fmr f4, f29
+; PWR10BE-NEXT:    fmr f3, f28 # Vec Defs: F3(VSR3) Vec Uses: F28(VSR28)
+; PWR10BE-NEXT:    fmr f4, f29 # Vec Defs: F4(VSR4) Vec Uses: F29(VSR29)
 ; PWR10BE-NEXT:    bl __gcc_qadd
 ; PWR10BE-NEXT:    nop
-; PWR10BE-NEXT:    fmr f3, f30
-; PWR10BE-NEXT:    fmr f4, f31
+; PWR10BE-NEXT:    fmr f3, f30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
+; PWR10BE-NEXT:    fmr f4, f31 # Vec Defs: F4(VSR4) Vec Uses: F31(VSR31)
 ; PWR10BE-NEXT:    bl __gcc_qadd
 ; PWR10BE-NEXT:    nop
 ; PWR10BE-NEXT:    lfd f31, 152(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F31(VSR31)
 ; PWR10BE-NEXT:    lfd f30, 144(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F30(VSR30)
 ; PWR10BE-NEXT:    lfd f29, 136(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F29(VSR29)
 ; PWR10BE-NEXT:    lfd f28, 128(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F28(VSR28)
 ; PWR10BE-NEXT:    lfd f27, 120(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F27(VSR27)
 ; PWR10BE-NEXT:    lfd f26, 112(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F26(VSR26)
 ; PWR10BE-NEXT:    addi r1, r1, 160
 ; PWR10BE-NEXT:    ld r0, 16(r1)
 ; PWR10BE-NEXT:    mtlr r0
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call ppc_fp128 @llvm.vector.reduce.fadd.v4ppcf128(ppc_fp128 %b, <4 x ppc_fp128> %a)
   ret ppc_fp128 %0
 }
 
 define dso_local ppc_fp128 @v4ppcf128_fast(<4 x ppc_fp128> %a) local_unnamed_addr #0 {
 ; PWR9LE-LABEL: v4ppcf128_fast:
 ; PWR9LE:       # %bb.0: # %entry
 ; PWR9LE-NEXT:    mflr r0
 ; PWR9LE-NEXT:    stfd f26, -48(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F26(VSR26)
 ; PWR9LE-NEXT:    stfd f27, -40(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F27(VSR27)
 ; PWR9LE-NEXT:    stfd f28, -32(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F28(VSR28)
 ; PWR9LE-NEXT:    stfd f29, -24(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F29(VSR29)
 ; PWR9LE-NEXT:    stfd f30, -16(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PWR9LE-NEXT:    stfd f31, -8(r1) # 8-byte Folded Spill
+; PWR9LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PWR9LE-NEXT:    std r0, 16(r1)
 ; PWR9LE-NEXT:    stdu r1, -96(r1)
-; PWR9LE-NEXT:    fmr f29, f4
-; PWR9LE-NEXT:    fmr f28, f3
-; PWR9LE-NEXT:    fmr f3, f5
-; PWR9LE-NEXT:    fmr f4, f6
-; PWR9LE-NEXT:    fmr f31, f8
-; PWR9LE-NEXT:    fmr f30, f7
+; PWR9LE-NEXT:    fmr f29, f4 # Vec Defs: F29(VSR29) Vec Uses: F4(VSR4)
+; PWR9LE-NEXT:    fmr f28, f3 # Vec Defs: F28(VSR28) Vec Uses: F3(VSR3)
+; PWR9LE-NEXT:    fmr f3, f5 # Vec Defs: F3(VSR3) Vec Uses: F5(VSR5)
+; PWR9LE-NEXT:    fmr f4, f6 # Vec Defs: F4(VSR4) Vec Uses: F6(VSR6)
+; PWR9LE-NEXT:    fmr f31, f8 # Vec Defs: F31(VSR31) Vec Uses: F8(VSR8)
+; PWR9LE-NEXT:    fmr f30, f7 # Vec Defs: F30(VSR30) Vec Uses: F7(VSR7)
 ; PWR9LE-NEXT:    bl __gcc_qadd
 ; PWR9LE-NEXT:    nop
-; PWR9LE-NEXT:    fmr f27, f1
-; PWR9LE-NEXT:    fmr f26, f2
-; PWR9LE-NEXT:    fmr f1, f28
-; PWR9LE-NEXT:    fmr f2, f29
-; PWR9LE-NEXT:    fmr f3, f30
-; PWR9LE-NEXT:    fmr f4, f31
+; PWR9LE-NEXT:    fmr f27, f1 # Vec Defs: F27(VSR27) Vec Uses: F1(VSR1)
+; PWR9LE-NEXT:    fmr f26, f2 # Vec Defs: F26(VSR26) Vec Uses: F2(VSR2)
+; PWR9LE-NEXT:    fmr f1, f28 # Vec Defs: F1(VSR1) Vec Uses: F28(VSR28)
+; PWR9LE-NEXT:    fmr f2, f29 # Vec Defs: F2(VSR2) Vec Uses: F29(VSR29)
+; PWR9LE-NEXT:    fmr f3, f30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
+; PWR9LE-NEXT:    fmr f4, f31 # Vec Defs: F4(VSR4) Vec Uses: F31(VSR31)
 ; PWR9LE-NEXT:    bl __gcc_qadd
 ; PWR9LE-NEXT:    nop
-; PWR9LE-NEXT:    fmr f3, f1
-; PWR9LE-NEXT:    fmr f4, f2
-; PWR9LE-NEXT:    fmr f1, f27
-; PWR9LE-NEXT:    fmr f2, f26
+; PWR9LE-NEXT:    fmr f3, f1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PWR9LE-NEXT:    fmr f4, f2 # Vec Defs: F4(VSR4) Vec Uses: F2(VSR2)
+; PWR9LE-NEXT:    fmr f1, f27 # Vec Defs: F1(VSR1) Vec Uses: F27(VSR27)
+; PWR9LE-NEXT:    fmr f2, f26 # Vec Defs: F2(VSR2) Vec Uses: F26(VSR26)
 ; PWR9LE-NEXT:    bl __gcc_qadd
 ; PWR9LE-NEXT:    nop
-; PWR9LE-NEXT:    stfd f2, 40(r1)
-; PWR9LE-NEXT:    stfd f1, 32(r1)
-; PWR9LE-NEXT:    lxv vs1, 32(r1)
-; PWR9LE-NEXT:    xxswapd vs2, vs1
+; PWR9LE-NEXT:    stfd f2, 40(r1) # Vec Uses: F2(VSR2)
+; PWR9LE-NEXT:    stfd f1, 32(r1) # Vec Uses: F1(VSR1)
+; PWR9LE-NEXT:    lxv vs1, 32(r1) # Vec Defs: VSL1(VSR1)
+; PWR9LE-NEXT:    xxswapd vs2, vs1 # Vec Defs: VSL2(VSR2) Vec Uses: VSL1(VSR1)VSL1(VSR1)
 ; PWR9LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR9LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PWR9LE-NEXT:    addi r1, r1, 96
 ; PWR9LE-NEXT:    ld r0, 16(r1)
 ; PWR9LE-NEXT:    lfd f31, -8(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PWR9LE-NEXT:    lfd f30, -16(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PWR9LE-NEXT:    mtlr r0
 ; PWR9LE-NEXT:    lfd f29, -24(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F29(VSR29)
 ; PWR9LE-NEXT:    lfd f28, -32(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F28(VSR28)
 ; PWR9LE-NEXT:    lfd f27, -40(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F27(VSR27)
 ; PWR9LE-NEXT:    lfd f26, -48(r1) # 8-byte Folded Reload
+; PWR9LE-NEXT:    # Vec Defs: F26(VSR26)
 ; PWR9LE-NEXT:    blr
 ;
 ; PWR9BE-LABEL: v4ppcf128_fast:
 ; PWR9BE:       # %bb.0: # %entry
 ; PWR9BE-NEXT:    mflr r0
 ; PWR9BE-NEXT:    std r0, 16(r1)
 ; PWR9BE-NEXT:    stdu r1, -176(r1)
 ; PWR9BE-NEXT:    stfd f28, 144(r1) # 8-byte Folded Spill
+; PWR9BE-NEXT:    # Vec Uses: F28(VSR28)
 ; PWR9BE-NEXT:    stfd f29, 152(r1) # 8-byte Folded Spill
-; PWR9BE-NEXT:    fmr f29, f4
-; PWR9BE-NEXT:    fmr f28, f3
-; PWR9BE-NEXT:    fmr f3, f5
-; PWR9BE-NEXT:    fmr f4, f6
+; PWR9BE-NEXT:    # Vec Uses: F29(VSR29)
+; PWR9BE-NEXT:    fmr f29, f4 # Vec Defs: F29(VSR29) Vec Uses: F4(VSR4)
+; PWR9BE-NEXT:    fmr f28, f3 # Vec Defs: F28(VSR28) Vec Uses: F3(VSR3)
+; PWR9BE-NEXT:    fmr f3, f5 # Vec Defs: F3(VSR3) Vec Uses: F5(VSR5)
+; PWR9BE-NEXT:    fmr f4, f6 # Vec Defs: F4(VSR4) Vec Uses: F6(VSR6)
 ; PWR9BE-NEXT:    stfd f26, 128(r1) # 8-byte Folded Spill
+; PWR9BE-NEXT:    # Vec Uses: F26(VSR26)
 ; PWR9BE-NEXT:    stfd f27, 136(r1) # 8-byte Folded Spill
+; PWR9BE-NEXT:    # Vec Uses: F27(VSR27)
 ; PWR9BE-NEXT:    stfd f30, 160(r1) # 8-byte Folded Spill
+; PWR9BE-NEXT:    # Vec Uses: F30(VSR30)
 ; PWR9BE-NEXT:    stfd f31, 168(r1) # 8-byte Folded Spill
-; PWR9BE-NEXT:    fmr f31, f8
-; PWR9BE-NEXT:    fmr f30, f7
+; PWR9BE-NEXT:    # Vec Uses: F31(VSR31)
+; PWR9BE-NEXT:    fmr f31, f8 # Vec Defs: F31(VSR31) Vec Uses: F8(VSR8)
+; PWR9BE-NEXT:    fmr f30, f7 # Vec Defs: F30(VSR30) Vec Uses: F7(VSR7)
 ; PWR9BE-NEXT:    bl __gcc_qadd
 ; PWR9BE-NEXT:    nop
-; PWR9BE-NEXT:    fmr f27, f1
-; PWR9BE-NEXT:    fmr f26, f2
-; PWR9BE-NEXT:    fmr f1, f28
-; PWR9BE-NEXT:    fmr f2, f29
-; PWR9BE-NEXT:    fmr f3, f30
-; PWR9BE-NEXT:    fmr f4, f31
+; PWR9BE-NEXT:    fmr f27, f1 # Vec Defs: F27(VSR27) Vec Uses: F1(VSR1)
+; PWR9BE-NEXT:    fmr f26, f2 # Vec Defs: F26(VSR26) Vec Uses: F2(VSR2)
+; PWR9BE-NEXT:    fmr f1, f28 # Vec Defs: F1(VSR1) Vec Uses: F28(VSR28)
+; PWR9BE-NEXT:    fmr f2, f29 # Vec Defs: F2(VSR2) Vec Uses: F29(VSR29)
+; PWR9BE-NEXT:    fmr f3, f30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
+; PWR9BE-NEXT:    fmr f4, f31 # Vec Defs: F4(VSR4) Vec Uses: F31(VSR31)
 ; PWR9BE-NEXT:    bl __gcc_qadd
 ; PWR9BE-NEXT:    nop
-; PWR9BE-NEXT:    fmr f3, f1
-; PWR9BE-NEXT:    fmr f4, f2
-; PWR9BE-NEXT:    fmr f1, f27
-; PWR9BE-NEXT:    fmr f2, f26
+; PWR9BE-NEXT:    fmr f3, f1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PWR9BE-NEXT:    fmr f4, f2 # Vec Defs: F4(VSR4) Vec Uses: F2(VSR2)
+; PWR9BE-NEXT:    fmr f1, f27 # Vec Defs: F1(VSR1) Vec Uses: F27(VSR27)
+; PWR9BE-NEXT:    fmr f2, f26 # Vec Defs: F2(VSR2) Vec Uses: F26(VSR26)
 ; PWR9BE-NEXT:    bl __gcc_qadd
 ; PWR9BE-NEXT:    nop
-; PWR9BE-NEXT:    stfd f2, 120(r1)
-; PWR9BE-NEXT:    stfd f1, 112(r1)
-; PWR9BE-NEXT:    lxv vs1, 112(r1)
+; PWR9BE-NEXT:    stfd f2, 120(r1) # Vec Uses: F2(VSR2)
+; PWR9BE-NEXT:    stfd f1, 112(r1) # Vec Uses: F1(VSR1)
+; PWR9BE-NEXT:    lxv vs1, 112(r1) # Vec Defs: VSL1(VSR1)
 ; PWR9BE-NEXT:    lfd f31, 168(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F31(VSR31)
 ; PWR9BE-NEXT:    lfd f30, 160(r1) # 8-byte Folded Reload
-; PWR9BE-NEXT:    xxswapd vs2, vs1
+; PWR9BE-NEXT:    # Vec Defs: F30(VSR30)
+; PWR9BE-NEXT:    xxswapd vs2, vs1 # Vec Defs: VSL2(VSR2) Vec Uses: VSL1(VSR1)VSL1(VSR1)
 ; PWR9BE-NEXT:    lfd f29, 152(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F29(VSR29)
 ; PWR9BE-NEXT:    lfd f28, 144(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F28(VSR28)
 ; PWR9BE-NEXT:    lfd f27, 136(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F27(VSR27)
 ; PWR9BE-NEXT:    lfd f26, 128(r1) # 8-byte Folded Reload
+; PWR9BE-NEXT:    # Vec Defs: F26(VSR26)
 ; PWR9BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR9BE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PWR9BE-NEXT:    addi r1, r1, 176
 ; PWR9BE-NEXT:    ld r0, 16(r1)
 ; PWR9BE-NEXT:    mtlr r0
 ; PWR9BE-NEXT:    blr
 ;
 ; PWR10LE-LABEL: v4ppcf128_fast:
 ; PWR10LE:       # %bb.0: # %entry
 ; PWR10LE-NEXT:    mflr r0
 ; PWR10LE-NEXT:    stfd f26, -48(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F26(VSR26)
 ; PWR10LE-NEXT:    stfd f27, -40(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F27(VSR27)
 ; PWR10LE-NEXT:    stfd f28, -32(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F28(VSR28)
 ; PWR10LE-NEXT:    stfd f29, -24(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F29(VSR29)
 ; PWR10LE-NEXT:    stfd f30, -16(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F30(VSR30)
 ; PWR10LE-NEXT:    stfd f31, -8(r1) # 8-byte Folded Spill
+; PWR10LE-NEXT:    # Vec Uses: F31(VSR31)
 ; PWR10LE-NEXT:    std r0, 16(r1)
 ; PWR10LE-NEXT:    stdu r1, -96(r1)
-; PWR10LE-NEXT:    fmr f29, f4
-; PWR10LE-NEXT:    fmr f28, f3
-; PWR10LE-NEXT:    fmr f3, f5
-; PWR10LE-NEXT:    fmr f4, f6
-; PWR10LE-NEXT:    fmr f31, f8
-; PWR10LE-NEXT:    fmr f30, f7
+; PWR10LE-NEXT:    fmr f29, f4 # Vec Defs: F29(VSR29) Vec Uses: F4(VSR4)
+; PWR10LE-NEXT:    fmr f28, f3 # Vec Defs: F28(VSR28) Vec Uses: F3(VSR3)
+; PWR10LE-NEXT:    fmr f3, f5 # Vec Defs: F3(VSR3) Vec Uses: F5(VSR5)
+; PWR10LE-NEXT:    fmr f4, f6 # Vec Defs: F4(VSR4) Vec Uses: F6(VSR6)
+; PWR10LE-NEXT:    fmr f31, f8 # Vec Defs: F31(VSR31) Vec Uses: F8(VSR8)
+; PWR10LE-NEXT:    fmr f30, f7 # Vec Defs: F30(VSR30) Vec Uses: F7(VSR7)
 ; PWR10LE-NEXT:    bl __gcc_qadd@notoc
-; PWR10LE-NEXT:    fmr f27, f1
-; PWR10LE-NEXT:    fmr f26, f2
-; PWR10LE-NEXT:    fmr f1, f28
-; PWR10LE-NEXT:    fmr f2, f29
-; PWR10LE-NEXT:    fmr f3, f30
-; PWR10LE-NEXT:    fmr f4, f31
+; PWR10LE-NEXT:    fmr f27, f1 # Vec Defs: F27(VSR27) Vec Uses: F1(VSR1)
+; PWR10LE-NEXT:    fmr f26, f2 # Vec Defs: F26(VSR26) Vec Uses: F2(VSR2)
+; PWR10LE-NEXT:    fmr f1, f28 # Vec Defs: F1(VSR1) Vec Uses: F28(VSR28)
+; PWR10LE-NEXT:    fmr f2, f29 # Vec Defs: F2(VSR2) Vec Uses: F29(VSR29)
+; PWR10LE-NEXT:    fmr f3, f30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
+; PWR10LE-NEXT:    fmr f4, f31 # Vec Defs: F4(VSR4) Vec Uses: F31(VSR31)
 ; PWR10LE-NEXT:    bl __gcc_qadd@notoc
-; PWR10LE-NEXT:    fmr f3, f1
-; PWR10LE-NEXT:    fmr f4, f2
-; PWR10LE-NEXT:    fmr f1, f27
-; PWR10LE-NEXT:    fmr f2, f26
+; PWR10LE-NEXT:    fmr f3, f1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PWR10LE-NEXT:    fmr f4, f2 # Vec Defs: F4(VSR4) Vec Uses: F2(VSR2)
+; PWR10LE-NEXT:    fmr f1, f27 # Vec Defs: F1(VSR1) Vec Uses: F27(VSR27)
+; PWR10LE-NEXT:    fmr f2, f26 # Vec Defs: F2(VSR2) Vec Uses: F26(VSR26)
 ; PWR10LE-NEXT:    bl __gcc_qadd@notoc
-; PWR10LE-NEXT:    stfd f2, 40(r1)
-; PWR10LE-NEXT:    stfd f1, 32(r1)
-; PWR10LE-NEXT:    lxv vs1, 32(r1)
-; PWR10LE-NEXT:    xxswapd vs2, vs1
+; PWR10LE-NEXT:    stfd f2, 40(r1) # Vec Uses: F2(VSR2)
+; PWR10LE-NEXT:    stfd f1, 32(r1) # Vec Uses: F1(VSR1)
+; PWR10LE-NEXT:    lxv vs1, 32(r1) # Vec Defs: VSL1(VSR1)
+; PWR10LE-NEXT:    xxswapd vs2, vs1 # Vec Defs: VSL2(VSR2) Vec Uses: VSL1(VSR1)VSL1(VSR1)
 ; PWR10LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR10LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PWR10LE-NEXT:    addi r1, r1, 96
 ; PWR10LE-NEXT:    ld r0, 16(r1)
 ; PWR10LE-NEXT:    lfd f31, -8(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F31(VSR31)
 ; PWR10LE-NEXT:    mtlr r0
 ; PWR10LE-NEXT:    lfd f30, -16(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F30(VSR30)
 ; PWR10LE-NEXT:    lfd f29, -24(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F29(VSR29)
 ; PWR10LE-NEXT:    lfd f28, -32(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F28(VSR28)
 ; PWR10LE-NEXT:    lfd f27, -40(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F27(VSR27)
 ; PWR10LE-NEXT:    lfd f26, -48(r1) # 8-byte Folded Reload
+; PWR10LE-NEXT:    # Vec Defs: F26(VSR26)
 ; PWR10LE-NEXT:    blr
 ;
 ; PWR10BE-LABEL: v4ppcf128_fast:
 ; PWR10BE:       # %bb.0: # %entry
 ; PWR10BE-NEXT:    mflr r0
 ; PWR10BE-NEXT:    std r0, 16(r1)
 ; PWR10BE-NEXT:    stdu r1, -176(r1)
 ; PWR10BE-NEXT:    stfd f28, 144(r1) # 8-byte Folded Spill
+; PWR10BE-NEXT:    # Vec Uses: F28(VSR28)
 ; PWR10BE-NEXT:    stfd f29, 152(r1) # 8-byte Folded Spill
-; PWR10BE-NEXT:    fmr f29, f4
-; PWR10BE-NEXT:    fmr f28, f3
-; PWR10BE-NEXT:    fmr f3, f5
-; PWR10BE-NEXT:    fmr f4, f6
+; PWR10BE-NEXT:    # Vec Uses: F29(VSR29)
+; PWR10BE-NEXT:    fmr f29, f4 # Vec Defs: F29(VSR29) Vec Uses: F4(VSR4)
+; PWR10BE-NEXT:    fmr f28, f3 # Vec Defs: F28(VSR28) Vec Uses: F3(VSR3)
+; PWR10BE-NEXT:    fmr f3, f5 # Vec Defs: F3(VSR3) Vec Uses: F5(VSR5)
+; PWR10BE-NEXT:    fmr f4, f6 # Vec Defs: F4(VSR4) Vec Uses: F6(VSR6)
 ; PWR10BE-NEXT:    stfd f26, 128(r1) # 8-byte Folded Spill
+; PWR10BE-NEXT:    # Vec Uses: F26(VSR26)
 ; PWR10BE-NEXT:    stfd f27, 136(r1) # 8-byte Folded Spill
+; PWR10BE-NEXT:    # Vec Uses: F27(VSR27)
 ; PWR10BE-NEXT:    stfd f30, 160(r1) # 8-byte Folded Spill
+; PWR10BE-NEXT:    # Vec Uses: F30(VSR30)
 ; PWR10BE-NEXT:    stfd f31, 168(r1) # 8-byte Folded Spill
-; PWR10BE-NEXT:    fmr f31, f8
-; PWR10BE-NEXT:    fmr f30, f7
+; PWR10BE-NEXT:    # Vec Uses: F31(VSR31)
+; PWR10BE-NEXT:    fmr f31, f8 # Vec Defs: F31(VSR31) Vec Uses: F8(VSR8)
+; PWR10BE-NEXT:    fmr f30, f7 # Vec Defs: F30(VSR30) Vec Uses: F7(VSR7)
 ; PWR10BE-NEXT:    bl __gcc_qadd
 ; PWR10BE-NEXT:    nop
-; PWR10BE-NEXT:    fmr f27, f1
-; PWR10BE-NEXT:    fmr f26, f2
-; PWR10BE-NEXT:    fmr f1, f28
-; PWR10BE-NEXT:    fmr f2, f29
-; PWR10BE-NEXT:    fmr f3, f30
-; PWR10BE-NEXT:    fmr f4, f31
+; PWR10BE-NEXT:    fmr f27, f1 # Vec Defs: F27(VSR27) Vec Uses: F1(VSR1)
+; PWR10BE-NEXT:    fmr f26, f2 # Vec Defs: F26(VSR26) Vec Uses: F2(VSR2)
+; PWR10BE-NEXT:    fmr f1, f28 # Vec Defs: F1(VSR1) Vec Uses: F28(VSR28)
+; PWR10BE-NEXT:    fmr f2, f29 # Vec Defs: F2(VSR2) Vec Uses: F29(VSR29)
+; PWR10BE-NEXT:    fmr f3, f30 # Vec Defs: F3(VSR3) Vec Uses: F30(VSR30)
+; PWR10BE-NEXT:    fmr f4, f31 # Vec Defs: F4(VSR4) Vec Uses: F31(VSR31)
 ; PWR10BE-NEXT:    bl __gcc_qadd
 ; PWR10BE-NEXT:    nop
-; PWR10BE-NEXT:    fmr f3, f1
-; PWR10BE-NEXT:    fmr f4, f2
-; PWR10BE-NEXT:    fmr f1, f27
-; PWR10BE-NEXT:    fmr f2, f26
+; PWR10BE-NEXT:    fmr f3, f1 # Vec Defs: F3(VSR3) Vec Uses: F1(VSR1)
+; PWR10BE-NEXT:    fmr f4, f2 # Vec Defs: F4(VSR4) Vec Uses: F2(VSR2)
+; PWR10BE-NEXT:    fmr f1, f27 # Vec Defs: F1(VSR1) Vec Uses: F27(VSR27)
+; PWR10BE-NEXT:    fmr f2, f26 # Vec Defs: F2(VSR2) Vec Uses: F26(VSR26)
 ; PWR10BE-NEXT:    bl __gcc_qadd
 ; PWR10BE-NEXT:    nop
-; PWR10BE-NEXT:    stfd f2, 120(r1)
-; PWR10BE-NEXT:    stfd f1, 112(r1)
+; PWR10BE-NEXT:    stfd f2, 120(r1) # Vec Uses: F2(VSR2)
+; PWR10BE-NEXT:    stfd f1, 112(r1) # Vec Uses: F1(VSR1)
 ; PWR10BE-NEXT:    lfd f31, 168(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F31(VSR31)
 ; PWR10BE-NEXT:    lfd f30, 160(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F30(VSR30)
 ; PWR10BE-NEXT:    lfd f29, 152(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F29(VSR29)
 ; PWR10BE-NEXT:    lfd f28, 144(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F28(VSR28)
 ; PWR10BE-NEXT:    lfd f27, 136(r1) # 8-byte Folded Reload
+; PWR10BE-NEXT:    # Vec Defs: F27(VSR27)
 ; PWR10BE-NEXT:    lfd f26, 128(r1) # 8-byte Folded Reload
-; PWR10BE-NEXT:    lxv vs1, 112(r1)
-; PWR10BE-NEXT:    xxswapd vs2, vs1
+; PWR10BE-NEXT:    # Vec Defs: F26(VSR26)
+; PWR10BE-NEXT:    lxv vs1, 112(r1) # Vec Defs: VSL1(VSR1)
+; PWR10BE-NEXT:    xxswapd vs2, vs1 # Vec Defs: VSL2(VSR2) Vec Uses: VSL1(VSR1)VSL1(VSR1)
 ; PWR10BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PWR10BE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PWR10BE-NEXT:    addi r1, r1, 176
 ; PWR10BE-NEXT:    ld r0, 16(r1)
 ; PWR10BE-NEXT:    mtlr r0
 ; PWR10BE-NEXT:    blr
 entry:
   %0 = call fast ppc_fp128 @llvm.vector.reduce.fadd.v4ppcf128(ppc_fp128 0xM80000000000000000000000000000000, <4 x ppc_fp128> %a)
   ret ppc_fp128 %0
 }
 
 declare ppc_fp128 @llvm.vector.reduce.fadd.v2ppcf128(ppc_fp128, <2 x ppc_fp128>) #0
 declare ppc_fp128 @llvm.vector.reduce.fadd.v4ppcf128(ppc_fp128, <4 x ppc_fp128>) #0
 
 attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/vsx.ll

 ; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr8 \
 ; RUN:     -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx \
 ; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
 ; RUN:     -check-prefix=CHECK-LE %s
 
 define double @test1(double %a, double %b) {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xsmuldp f1, f1, f2
+; CHECK-NEXT:    xsmuldp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test1:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xsmuldp f1, f1, f2
+; CHECK-REG-NEXT:    xsmuldp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test1:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xsmuldp f1, f1, f2
+; CHECK-FISL-NEXT:    xsmuldp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test1:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xsmuldp f1, f1, f2
+; CHECK-LE-NEXT:    xsmuldp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-LE-NEXT:    blr
 entry:
   %v = fmul double %a, %b
   ret double %v
 
 
 }
 
 define double @test2(double %a, double %b) {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xsdivdp f1, f1, f2
+; CHECK-NEXT:    xsdivdp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test2:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xsdivdp f1, f1, f2
+; CHECK-REG-NEXT:    xsdivdp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test2:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xsdivdp f1, f1, f2
+; CHECK-FISL-NEXT:    xsdivdp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test2:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xsdivdp f1, f1, f2
+; CHECK-LE-NEXT:    xsdivdp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-LE-NEXT:    blr
 entry:
   %v = fdiv double %a, %b
   ret double %v
 
 
 }
 
 define double @test3(double %a, double %b) {
 ; CHECK-LABEL: test3:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xsadddp f1, f1, f2
+; CHECK-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test3:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xsadddp f1, f1, f2
+; CHECK-REG-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test3:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xsadddp f1, f1, f2
+; CHECK-FISL-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test3:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xsadddp f1, f1, f2
+; CHECK-LE-NEXT:    xsadddp f1, f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F1(VSR1)F2(VSR2)
 ; CHECK-LE-NEXT:    blr
 entry:
   %v = fadd double %a, %b
   ret double %v
 
 
 }
 
 define <2 x double> @test4(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: test4:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xvadddp v2, v2, v3
+; CHECK-NEXT:    xvadddp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test4:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xvadddp v2, v2, v3
+; CHECK-REG-NEXT:    xvadddp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test4:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xvadddp v2, v2, v3
+; CHECK-FISL-NEXT:    xvadddp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test4:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xvadddp v2, v2, v3
+; CHECK-LE-NEXT:    xvadddp v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
 entry:
   %v = fadd <2 x double> %a, %b
   ret <2 x double> %v
 
 
 }
 
 define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test5:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlxor v2, v2, v3
+; CHECK-NEXT:    xxlxor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test5:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xxlxor v2, v2, v3
+; CHECK-REG-NEXT:    xxlxor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test5:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xxlxor v2, v2, v3
+; CHECK-FISL-NEXT:    xxlxor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test5:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxlxor v2, v2, v3
+; CHECK-LE-NEXT:    xxlxor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
 entry:
   %v = xor <4 x i32> %a, %b
   ret <4 x i32> %v
 
 
 
 }
 
 define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test6:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlxor v2, v2, v3
+; CHECK-NEXT:    xxlxor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test6:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xxlxor v2, v2, v3
+; CHECK-REG-NEXT:    xxlxor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test6:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xxlxor v2, v2, v3
+; CHECK-FISL-NEXT:    xxlxor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test6:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxlxor v2, v2, v3
+; CHECK-LE-NEXT:    xxlxor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
 entry:
   %v = xor <8 x i16> %a, %b
   ret <8 x i16> %v
 
 
 
 }
 
 define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test7:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlxor v2, v2, v3
+; CHECK-NEXT:    xxlxor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test7:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xxlxor v2, v2, v3
+; CHECK-REG-NEXT:    xxlxor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test7:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xxlxor v2, v2, v3
+; CHECK-FISL-NEXT:    xxlxor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test7:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxlxor v2, v2, v3
+; CHECK-LE-NEXT:    xxlxor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
 entry:
   %v = xor <16 x i8> %a, %b
   ret <16 x i8> %v
 
 
 
 }
 
 define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor v2, v2, v3
+; CHECK-NEXT:    xxlor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test8:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xxlor v2, v2, v3
+; CHECK-REG-NEXT:    xxlor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test8:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xxlor v2, v2, v3
+; CHECK-FISL-NEXT:    xxlor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test8:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxlor v2, v2, v3
+; CHECK-LE-NEXT:    xxlor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
 entry:
   %v = or <4 x i32> %a, %b
   ret <4 x i32> %v
 
 
 
 }
 
 define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test9:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor v2, v2, v3
+; CHECK-NEXT:    xxlor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test9:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xxlor v2, v2, v3
+; CHECK-REG-NEXT:    xxlor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test9:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xxlor v2, v2, v3
+; CHECK-FISL-NEXT:    xxlor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test9:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxlor v2, v2, v3
+; CHECK-LE-NEXT:    xxlor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
 entry:
   %v = or <8 x i16> %a, %b
   ret <8 x i16> %v
 
 
 
 }
 
 define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test10:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor v2, v2, v3
+; CHECK-NEXT:    xxlor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test10:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xxlor v2, v2, v3
+; CHECK-REG-NEXT:    xxlor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test10:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xxlor v2, v2, v3
+; CHECK-FISL-NEXT:    xxlor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test10:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxlor v2, v2, v3
+; CHECK-LE-NEXT:    xxlor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
 entry:
   %v = or <16 x i8> %a, %b
   ret <16 x i8> %v
 
 
 
 }
 
 define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test11:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxland v2, v2, v3
+; CHECK-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test11:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xxland v2, v2, v3
+; CHECK-REG-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test11:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xxland v2, v2, v3
+; CHECK-FISL-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test11:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxland v2, v2, v3
+; CHECK-LE-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
 entry:
   %v = and <4 x i32> %a, %b
   ret <4 x i32> %v
 
 
 
 }
 
 define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test12:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxland v2, v2, v3
+; CHECK-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test12:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xxland v2, v2, v3
+; CHECK-REG-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test12:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xxland v2, v2, v3
+; CHECK-FISL-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test12:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxland v2, v2, v3
+; CHECK-LE-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
 entry:
   %v = and <8 x i16> %a, %b
   ret <8 x i16> %v
 
 
 
 }
 
 define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test13:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxland v2, v2, v3
+; CHECK-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test13:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xxland v2, v2, v3
+; CHECK-REG-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test13:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xxland v2, v2, v3
+; CHECK-FISL-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test13:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxland v2, v2, v3
+; CHECK-LE-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
 entry:
   %v = and <16 x i8> %a, %b
   ret <16 x i8> %v
 
 
 
 }
 
 define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test14:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlnor v2, v2, v3
+; CHECK-NEXT:    xxlnor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test14:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xxlnor v2, v2, v3
+; CHECK-REG-NEXT:    xxlnor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test14:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xxlor vs0, v2, v3
-; CHECK-FISL-NEXT:    xxlnor v2, v2, v3
+; CHECK-FISL-NEXT:    xxlor vs0, v2, v3 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-FISL-NEXT:    xxlnor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test14:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxlnor v2, v2, v3
+; CHECK-LE-NEXT:    xxlnor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
 entry:
   %v = or <4 x i32> %a, %b
   %w = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1>
   ret <4 x i32> %w
 
 
 
 }
 
 define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test15:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlnor v2, v2, v3
+; CHECK-NEXT:    xxlnor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test15:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xxlnor v2, v2, v3
+; CHECK-REG-NEXT:    xxlnor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test15:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xxlor v4, v2, v3
-; CHECK-FISL-NEXT:    xxlnor v2, v2, v3
+; CHECK-FISL-NEXT:    xxlor v4, v2, v3 # Vec Defs: V4(VSR36) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-FISL-NEXT:    xxlnor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test15:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxlnor v2, v2, v3
+; CHECK-LE-NEXT:    xxlnor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
 entry:
   %v = or <8 x i16> %a, %b
   %w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
   ret <8 x i16> %w
 
 
 
 }
 
 define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlnor v2, v2, v3
+; CHECK-NEXT:    xxlnor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test16:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xxlnor v2, v2, v3
+; CHECK-REG-NEXT:    xxlnor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test16:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xxlor v4, v2, v3
-; CHECK-FISL-NEXT:    xxlnor v2, v2, v3
+; CHECK-FISL-NEXT:    xxlor v4, v2, v3 # Vec Defs: V4(VSR36) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-FISL-NEXT:    xxlnor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test16:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxlnor v2, v2, v3
+; CHECK-LE-NEXT:    xxlnor v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
 entry:
   %v = or <16 x i8> %a, %b
   %w = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
   ret <16 x i8> %w
 
 
 
 }
 
 define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test17:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlandc v2, v2, v3
+; CHECK-NEXT:    xxlandc v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test17:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xxlandc v2, v2, v3
+; CHECK-REG-NEXT:    xxlandc v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test17:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xxlnor vs0, v3, v3
-; CHECK-FISL-NEXT:    xxland v2, v2, vs0
+; CHECK-FISL-NEXT:    xxlnor vs0, v3, v3 # Vec Defs: VSL0(VSR0) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-FISL-NEXT:    xxland v2, v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)VSL0(VSR0)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test17:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxlandc v2, v2, v3
+; CHECK-LE-NEXT:    xxlandc v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
 entry:
   %w = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
   %v = and <4 x i32> %a, %w
   ret <4 x i32> %v
 
 
 
 }
 
 define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test18:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlandc v2, v2, v3
+; CHECK-NEXT:    xxlandc v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test18:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xxlandc v2, v2, v3
+; CHECK-REG-NEXT:    xxlandc v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test18:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xxlnor v4, v3, v3
-; CHECK-FISL-NEXT:    xxlandc v2, v2, v3
+; CHECK-FISL-NEXT:    xxlnor v4, v3, v3 # Vec Defs: V4(VSR36) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-FISL-NEXT:    xxlandc v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test18:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxlandc v2, v2, v3
+; CHECK-LE-NEXT:    xxlandc v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
 entry:
   %w = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
   %v = and <8 x i16> %a, %w
   ret <8 x i16> %v
 
 
 
 }
 
 define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test19:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlandc v2, v2, v3
+; CHECK-NEXT:    xxlandc v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test19:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xxlandc v2, v2, v3
+; CHECK-REG-NEXT:    xxlandc v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test19:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xxlnor v4, v3, v3
-; CHECK-FISL-NEXT:    xxlandc v2, v2, v3
+; CHECK-FISL-NEXT:    xxlnor v4, v3, v3 # Vec Defs: V4(VSR36) Vec Uses: V3(VSR35)V3(VSR35)
+; CHECK-FISL-NEXT:    xxlandc v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test19:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xxlandc v2, v2, v3
+; CHECK-LE-NEXT:    xxlandc v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
 entry:
   %w = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
   %v = and <16 x i8> %a, %w
   ret <16 x i8> %v
 
 
 
 }
 
 define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
 ; CHECK-LABEL: test20:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vcmpequw v4, v4, v5
-; CHECK-NEXT:    xxsel v2, v3, v2, v4
+; CHECK-NEXT:    vcmpequw v4, v4, v5 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-NEXT:    xxsel v2, v3, v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test20:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    vcmpequw v4, v4, v5
-; CHECK-REG-NEXT:    xxsel v2, v3, v2, v4
+; CHECK-REG-NEXT:    vcmpequw v4, v4, v5 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-REG-NEXT:    xxsel v2, v3, v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test20:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    vcmpequw v4, v4, v5
-; CHECK-FISL-NEXT:    xxsel v2, v3, v2, v4
+; CHECK-FISL-NEXT:    vcmpequw v4, v4, v5 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-FISL-NEXT:    xxsel v2, v3, v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test20:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    vcmpequw v4, v4, v5
-; CHECK-LE-NEXT:    xxsel v2, v3, v2, v4
+; CHECK-LE-NEXT:    vcmpequw v4, v4, v5 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-LE-NEXT:    xxsel v2, v3, v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; CHECK-LE-NEXT:    blr
 entry:
   %m = icmp eq <4 x i32> %c, %d
   %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
   ret <4 x i32> %v
 
 
 
 }
 
 define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
 ; CHECK-LABEL: test21:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xvcmpeqsp vs0, v4, v5
-; CHECK-NEXT:    xxsel v2, v3, v2, vs0
+; CHECK-NEXT:    xvcmpeqsp vs0, v4, v5 # Vec Defs: VSL0(VSR0) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-NEXT:    xxsel v2, v3, v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)VSL0(VSR0)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test21:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xvcmpeqsp vs0, v4, v5
-; CHECK-REG-NEXT:    xxsel v2, v3, v2, vs0
+; CHECK-REG-NEXT:    xvcmpeqsp vs0, v4, v5 # Vec Defs: VSL0(VSR0) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-REG-NEXT:    xxsel v2, v3, v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)VSL0(VSR0)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test21:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xvcmpeqsp vs0, v4, v5
-; CHECK-FISL-NEXT:    xxsel v2, v3, v2, vs0
+; CHECK-FISL-NEXT:    xvcmpeqsp vs0, v4, v5 # Vec Defs: VSL0(VSR0) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-FISL-NEXT:    xxsel v2, v3, v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)VSL0(VSR0)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test21:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xvcmpeqsp vs0, v4, v5
-; CHECK-LE-NEXT:    xxsel v2, v3, v2, vs0
+; CHECK-LE-NEXT:    xvcmpeqsp vs0, v4, v5 # Vec Defs: VSL0(VSR0) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-LE-NEXT:    xxsel v2, v3, v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)VSL0(VSR0)
 ; CHECK-LE-NEXT:    blr
 entry:
   %m = fcmp oeq <4 x float> %c, %d
   %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
   ret <4 x float> %v
 
 
 
 }
 
 define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
 ; CHECK-LABEL: test22:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xvcmpgtsp vs0, v5, v4
-; CHECK-NEXT:    xvcmpgtsp vs1, v4, v5
-; CHECK-NEXT:    xxlor vs0, vs1, vs0
-; CHECK-NEXT:    xxsel v2, v2, v3, vs0
+; CHECK-NEXT:    xvcmpgtsp vs0, v5, v4 # Vec Defs: VSL0(VSR0) Vec Uses: V5(VSR37)V4(VSR36)
+; CHECK-NEXT:    xvcmpgtsp vs1, v4, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-NEXT:    xxlor vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; CHECK-NEXT:    xxsel v2, v2, v3, vs0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)VSL0(VSR0)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test22:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xvcmpgtsp vs0, v5, v4
-; CHECK-REG-NEXT:    xvcmpgtsp vs1, v4, v5
-; CHECK-REG-NEXT:    xxlor vs0, vs1, vs0
-; CHECK-REG-NEXT:    xxsel v2, v2, v3, vs0
+; CHECK-REG-NEXT:    xvcmpgtsp vs0, v5, v4 # Vec Defs: VSL0(VSR0) Vec Uses: V5(VSR37)V4(VSR36)
+; CHECK-REG-NEXT:    xvcmpgtsp vs1, v4, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-REG-NEXT:    xxlor vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; CHECK-REG-NEXT:    xxsel v2, v2, v3, vs0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)VSL0(VSR0)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test22:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xvcmpgtsp vs1, v5, v4
-; CHECK-FISL-NEXT:    xvcmpgtsp vs0, v4, v5
-; CHECK-FISL-NEXT:    xxlor vs0, vs0, vs1
-; CHECK-FISL-NEXT:    xxsel v2, v2, v3, vs0
+; CHECK-FISL-NEXT:    xvcmpgtsp vs1, v5, v4 # Vec Defs: VSL1(VSR1) Vec Uses: V5(VSR37)V4(VSR36)
+; CHECK-FISL-NEXT:    xvcmpgtsp vs0, v4, v5 # Vec Defs: VSL0(VSR0) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-FISL-NEXT:    xxlor vs0, vs0, vs1 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)VSL1(VSR1)
+; CHECK-FISL-NEXT:    xxsel v2, v2, v3, vs0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)VSL0(VSR0)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test22:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xvcmpgtsp vs0, v5, v4
-; CHECK-LE-NEXT:    xvcmpgtsp vs1, v4, v5
-; CHECK-LE-NEXT:    xxlor vs0, vs1, vs0
-; CHECK-LE-NEXT:    xxsel v2, v2, v3, vs0
+; CHECK-LE-NEXT:    xvcmpgtsp vs0, v5, v4 # Vec Defs: VSL0(VSR0) Vec Uses: V5(VSR37)V4(VSR36)
+; CHECK-LE-NEXT:    xvcmpgtsp vs1, v4, v5 # Vec Defs: VSL1(VSR1) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-LE-NEXT:    xxlor vs0, vs1, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL1(VSR1)VSL0(VSR0)
+; CHECK-LE-NEXT:    xxsel v2, v2, v3, vs0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)VSL0(VSR0)
 ; CHECK-LE-NEXT:    blr
 entry:
   %m = fcmp ueq <4 x float> %c, %d
   %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
   ret <4 x float> %v
 
 
 
 }
 
 define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
 ; CHECK-LABEL: test23:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vcmpequh v4, v4, v5
-; CHECK-NEXT:    xxsel v2, v3, v2, v4
+; CHECK-NEXT:    vcmpequh v4, v4, v5 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-NEXT:    xxsel v2, v3, v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test23:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    vcmpequh v4, v4, v5
-; CHECK-REG-NEXT:    xxsel v2, v3, v2, v4
+; CHECK-REG-NEXT:    vcmpequh v4, v4, v5 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-REG-NEXT:    xxsel v2, v3, v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test23:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    vcmpequh v4, v4, v5
-; CHECK-FISL-NEXT:    xxlor vs0, v4, v4
-; CHECK-FISL-NEXT:    xxsel v2, v3, v2, vs0
+; CHECK-FISL-NEXT:    vcmpequh v4, v4, v5 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-FISL-NEXT:    xxlor vs0, v4, v4 # Vec Defs: VSL0(VSR0) Vec Uses: V4(VSR36)V4(VSR36)
+; CHECK-FISL-NEXT:    xxsel v2, v3, v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)VSL0(VSR0)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test23:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    vcmpequh v4, v4, v5
-; CHECK-LE-NEXT:    xxsel v2, v3, v2, v4
+; CHECK-LE-NEXT:    vcmpequh v4, v4, v5 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-LE-NEXT:    xxsel v2, v3, v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; CHECK-LE-NEXT:    blr
 entry:
   %m = icmp eq <8 x i16> %c, %d
   %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
   ret <8 x i16> %v
 
 
 
 }
 
 define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
 ; CHECK-LABEL: test24:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vcmpequb v4, v4, v5
-; CHECK-NEXT:    xxsel v2, v3, v2, v4
+; CHECK-NEXT:    vcmpequb v4, v4, v5 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-NEXT:    xxsel v2, v3, v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test24:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    vcmpequb v4, v4, v5
-; CHECK-REG-NEXT:    xxsel v2, v3, v2, v4
+; CHECK-REG-NEXT:    vcmpequb v4, v4, v5 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-REG-NEXT:    xxsel v2, v3, v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test24:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    vcmpequb v4, v4, v5
-; CHECK-FISL-NEXT:    xxlor vs0, v4, v4
-; CHECK-FISL-NEXT:    xxsel v2, v3, v2, vs0
+; CHECK-FISL-NEXT:    vcmpequb v4, v4, v5 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-FISL-NEXT:    xxlor vs0, v4, v4 # Vec Defs: VSL0(VSR0) Vec Uses: V4(VSR36)V4(VSR36)
+; CHECK-FISL-NEXT:    xxsel v2, v3, v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)VSL0(VSR0)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test24:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    vcmpequb v4, v4, v5
-; CHECK-LE-NEXT:    xxsel v2, v3, v2, v4
+; CHECK-LE-NEXT:    vcmpequb v4, v4, v5 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-LE-NEXT:    xxsel v2, v3, v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; CHECK-LE-NEXT:    blr
 entry:
   %m = icmp eq <16 x i8> %c, %d
   %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
   ret <16 x i8> %v
 
 
 
 }
 
 define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
 ; CHECK-LABEL: test25:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xvcmpeqdp vs0, v4, v5
-; CHECK-NEXT:    xxsel v2, v3, v2, vs0
+; CHECK-NEXT:    xvcmpeqdp vs0, v4, v5 # Vec Defs: VSL0(VSR0) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-NEXT:    xxsel v2, v3, v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)VSL0(VSR0)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test25:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xvcmpeqdp vs0, v4, v5
-; CHECK-REG-NEXT:    xxsel v2, v3, v2, vs0
+; CHECK-REG-NEXT:    xvcmpeqdp vs0, v4, v5 # Vec Defs: VSL0(VSR0) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-REG-NEXT:    xxsel v2, v3, v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)VSL0(VSR0)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test25:
 ; CHECK-FISL:       # %bb.0: # %entry
-; CHECK-FISL-NEXT:    xvcmpeqdp vs0, v4, v5
-; CHECK-FISL-NEXT:    xxsel v2, v3, v2, vs0
+; CHECK-FISL-NEXT:    xvcmpeqdp vs0, v4, v5 # Vec Defs: VSL0(VSR0) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-FISL-NEXT:    xxsel v2, v3, v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)VSL0(VSR0)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test25:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xvcmpeqdp v4, v4, v5
-; CHECK-LE-NEXT:    xxsel v2, v3, v2, v4
+; CHECK-LE-NEXT:    xvcmpeqdp v4, v4, v5 # Vec Defs: V4(VSR36) Vec Uses: V4(VSR36)V5(VSR37)
+; CHECK-LE-NEXT:    xxsel v2, v3, v2, v4 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)V4(VSR36)
 ; CHECK-LE-NEXT:    blr
 entry:
   %m = fcmp oeq <2 x double> %c, %d
   %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
   ret <2 x double> %v
 
 
 }
 
 define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test26:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -32
 ; CHECK-NEXT:    addi r4, r1, -48
-; CHECK-NEXT:    stxvd2x v3, 0, r3
-; CHECK-NEXT:    stxvd2x v2, 0, r4
+; CHECK-NEXT:    stxvd2x v3, 0, r3 # Vec Uses: V3(VSR35)
+; CHECK-NEXT:    stxvd2x v2, 0, r4 # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    ld r3, -24(r1)
 ; CHECK-NEXT:    ld r4, -40(r1)
 ; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    ld r4, -48(r1)
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    ld r3, -32(r1)
 ; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
-; CHECK-NEXT:    lxvd2x v2, 0, r3
+; CHECK-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test26:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -32
 ; CHECK-REG-NEXT:    addi r4, r1, -48
-; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
+; CHECK-REG-NEXT:    stxvd2x v3, 0, r3 # Vec Uses: V3(VSR35)
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r4 # Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    ld r3, -24(r1)
 ; CHECK-REG-NEXT:    ld r4, -40(r1)
 ; CHECK-REG-NEXT:    add r3, r4, r3
 ; CHECK-REG-NEXT:    ld r4, -48(r1)
 ; CHECK-REG-NEXT:    std r3, -8(r1)
 ; CHECK-REG-NEXT:    ld r3, -32(r1)
 ; CHECK-REG-NEXT:    add r3, r4, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
-; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test26:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    addi r3, r1, -32
-; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3 # Vec Uses: V3(VSR35)
 ; CHECK-FISL-NEXT:    addi r3, r1, -48
-; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    ld r4, -24(r1)
 ; CHECK-FISL-NEXT:    ld r3, -40(r1)
 ; CHECK-FISL-NEXT:    add r3, r3, r4
 ; CHECK-FISL-NEXT:    std r3, -8(r1)
 ; CHECK-FISL-NEXT:    ld r4, -32(r1)
 ; CHECK-FISL-NEXT:    ld r3, -48(r1)
 ; CHECK-FISL-NEXT:    add r3, r3, r4
 ; CHECK-FISL-NEXT:    std r3, -16(r1)
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
-; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test26:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    vaddudm v2, v2, v3
+; CHECK-LE-NEXT:    vaddudm v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
   %v = add <2 x i64> %a, %b
   ret <2 x i64> %v
 
 
 ; Make sure we use only two stores (one for each operand).
 
 ; FIXME: The code quality here is not good; just make sure we do something for now.
 
 }
 
 define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test27:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxland v2, v2, v3
+; CHECK-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test27:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    xxland v2, v2, v3
+; CHECK-REG-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test27:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    xxland v2, v2, v3
+; CHECK-FISL-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test27:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxland v2, v2, v3
+; CHECK-LE-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
   %v = and <2 x i64> %a, %b
   ret <2 x i64> %v
 
 
 }
 
 define <2 x double> @test28(<2 x double>* %a) {
 ; CHECK-LABEL: test28:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lxvd2x v2, 0, r3
+; CHECK-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test28:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test28:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test28:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
-; CHECK-LE-NEXT:    xxswapd v2, vs0
+; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3 # Vec Defs: VSL0(VSR0)
+; CHECK-LE-NEXT:    xxswapd v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; CHECK-LE-NEXT:    blr
   %v = load <2 x double>, <2 x double>* %a, align 16
   ret <2 x double> %v
 
 
 }
 
 define void @test29(<2 x double>* %a, <2 x double> %b) {
 ; CHECK-LABEL: test29:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    stxvd2x v2, 0, r3
+; CHECK-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test29:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test29:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test29:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxswapd vs0, v2
-; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3
+; CHECK-LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3 # Vec Uses: VSL0(VSR0)
 ; CHECK-LE-NEXT:    blr
   store <2 x double> %b, <2 x double>* %a, align 16
   ret void
 
 
 }
 
 define <2 x double> @test28u(<2 x double>* %a) {
 ; CHECK-LABEL: test28u:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lxvd2x v2, 0, r3
+; CHECK-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test28u:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test28u:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test28u:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
-; CHECK-LE-NEXT:    xxswapd v2, vs0
+; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3 # Vec Defs: VSL0(VSR0)
+; CHECK-LE-NEXT:    xxswapd v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; CHECK-LE-NEXT:    blr
   %v = load <2 x double>, <2 x double>* %a, align 8
   ret <2 x double> %v
 
 
 }
 
 define void @test29u(<2 x double>* %a, <2 x double> %b) {
 ; CHECK-LABEL: test29u:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    stxvd2x v2, 0, r3
+; CHECK-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test29u:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test29u:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test29u:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxswapd vs0, v2
-; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3
+; CHECK-LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3 # Vec Uses: VSL0(VSR0)
 ; CHECK-LE-NEXT:    blr
   store <2 x double> %b, <2 x double>* %a, align 8
   ret void
 
 
 }
 
 define <2 x i64> @test30(<2 x i64>* %a) {
 ; CHECK-LABEL: test30:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lxvd2x v2, 0, r3
+; CHECK-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test30:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test30:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test30:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
-; CHECK-LE-NEXT:    xxswapd v2, vs0
+; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3 # Vec Defs: VSL0(VSR0)
+; CHECK-LE-NEXT:    xxswapd v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; CHECK-LE-NEXT:    blr
   %v = load <2 x i64>, <2 x i64>* %a, align 16
   ret <2 x i64> %v
 
 
 
 }
 
 define void @test31(<2 x i64>* %a, <2 x i64> %b) {
 ; CHECK-LABEL: test31:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    stxvd2x v2, 0, r3
+; CHECK-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test31:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test31:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test31:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxswapd vs0, v2
-; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3
+; CHECK-LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3 # Vec Uses: VSL0(VSR0)
 ; CHECK-LE-NEXT:    blr
   store <2 x i64> %b, <2 x i64>* %a, align 16
   ret void
 
 
 }
 
 define <4 x float> @test32(<4 x float>* %a) {
 ; CHECK-LABEL: test32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lxvw4x v2, 0, r3
+; CHECK-NEXT:    lxvw4x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test32:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    lxvw4x v2, 0, r3
+; CHECK-REG-NEXT:    lxvw4x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test32:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3
+; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test32:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    lvx v2, 0, r3
+; CHECK-LE-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %v = load <4 x float>, <4 x float>* %a, align 16
   ret <4 x float> %v
 
 
 
 }
 
 define void @test33(<4 x float>* %a, <4 x float> %b) {
 ; CHECK-LABEL: test33:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    stxvw4x v2, 0, r3
+; CHECK-NEXT:    stxvw4x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test33:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    stxvw4x v2, 0, r3
+; CHECK-REG-NEXT:    stxvw4x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test33:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3
+; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test33:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    stvx v2, 0, r3
+; CHECK-LE-NEXT:    stvx v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   store <4 x float> %b, <4 x float>* %a, align 16
   ret void
 
 
 
 }
 
 define <4 x float> @test32u(<4 x float>* %a) {
 ; CHECK-LABEL: test32u:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li r4, 15
-; CHECK-NEXT:    lvsl v3, 0, r3
-; CHECK-NEXT:    lvx v2, r3, r4
-; CHECK-NEXT:    lvx v4, 0, r3
-; CHECK-NEXT:    vperm v2, v4, v2, v3
+; CHECK-NEXT:    lvsl v3, 0, r3 # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    lvx v2, r3, r4 # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    lvx v4, 0, r3 # Vec Defs: V4(VSR36)
+; CHECK-NEXT:    vperm v2, v4, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test32u:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    li r4, 15
-; CHECK-REG-NEXT:    lvsl v3, 0, r3
-; CHECK-REG-NEXT:    lvx v2, r3, r4
-; CHECK-REG-NEXT:    lvx v4, 0, r3
-; CHECK-REG-NEXT:    vperm v2, v4, v2, v3
+; CHECK-REG-NEXT:    lvsl v3, 0, r3 # Vec Defs: V3(VSR35)
+; CHECK-REG-NEXT:    lvx v2, r3, r4 # Vec Defs: V2(VSR34)
+; CHECK-REG-NEXT:    lvx v4, 0, r3 # Vec Defs: V4(VSR36)
+; CHECK-REG-NEXT:    vperm v2, v4, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V4(VSR36)V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test32u:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    li r4, 15
-; CHECK-FISL-NEXT:    lvx v3, r3, r4
-; CHECK-FISL-NEXT:    lvsl v4, 0, r3
-; CHECK-FISL-NEXT:    lvx v2, 0, r3
-; CHECK-FISL-NEXT:    vperm v2, v2, v3, v4
+; CHECK-FISL-NEXT:    lvx v3, r3, r4 # Vec Defs: V3(VSR35)
+; CHECK-FISL-NEXT:    lvsl v4, 0, r3 # Vec Defs: V4(VSR36)
+; CHECK-FISL-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-FISL-NEXT:    vperm v2, v2, v3, v4 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)V4(VSR36)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test32u:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
-; CHECK-LE-NEXT:    xxswapd v2, vs0
+; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3 # Vec Defs: VSL0(VSR0)
+; CHECK-LE-NEXT:    xxswapd v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)VSL0(VSR0)
 ; CHECK-LE-NEXT:    blr
   %v = load <4 x float>, <4 x float>* %a, align 8
   ret <4 x float> %v
 
 
 }
 
 define void @test33u(<4 x float>* %a, <4 x float> %b) {
 ; CHECK-LABEL: test33u:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    stxvw4x v2, 0, r3
+; CHECK-NEXT:    stxvw4x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test33u:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    stxvw4x v2, 0, r3
+; CHECK-REG-NEXT:    stxvw4x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test33u:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3
+; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test33u:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxswapd vs0, v2
-; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3
+; CHECK-LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3 # Vec Uses: VSL0(VSR0)
 ; CHECK-LE-NEXT:    blr
   store <4 x float> %b, <4 x float>* %a, align 8
   ret void
 
 
 
 }
 
 define <4 x i32> @test34(<4 x i32>* %a) {
 ; CHECK-LABEL: test34:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lxvw4x v2, 0, r3
+; CHECK-NEXT:    lxvw4x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test34:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    lxvw4x v2, 0, r3
+; CHECK-REG-NEXT:    lxvw4x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test34:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3
+; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test34:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    lvx v2, 0, r3
+; CHECK-LE-NEXT:    lvx v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %v = load <4 x i32>, <4 x i32>* %a, align 16
   ret <4 x i32> %v
 
 
 
 }
 
 define void @test35(<4 x i32>* %a, <4 x i32> %b) {
 ; CHECK-LABEL: test35:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    stxvw4x v2, 0, r3
+; CHECK-NEXT:    stxvw4x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test35:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    stxvw4x v2, 0, r3
+; CHECK-REG-NEXT:    stxvw4x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test35:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3
+; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test35:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    stvx v2, 0, r3
+; CHECK-LE-NEXT:    stvx v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   store <4 x i32> %b, <4 x i32>* %a, align 16
   ret void
 
 
 
 }
 
 define <2 x double> @test40(<2 x i64> %a) {
 ; CHECK-LABEL: test40:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xvcvuxddp v2, v2
+; CHECK-NEXT:    xvcvuxddp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test40:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    xvcvuxddp v2, v2
+; CHECK-REG-NEXT:    xvcvuxddp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test40:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    xvcvuxddp v2, v2
+; CHECK-FISL-NEXT:    xvcvuxddp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test40:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xvcvuxddp v2, v2
+; CHECK-LE-NEXT:    xvcvuxddp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %v = uitofp <2 x i64> %a to <2 x double>
   ret <2 x double> %v
 
 
 }
 
 define <2 x double> @test41(<2 x i64> %a) {
 ; CHECK-LABEL: test41:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xvcvsxddp v2, v2
+; CHECK-NEXT:    xvcvsxddp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test41:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    xvcvsxddp v2, v2
+; CHECK-REG-NEXT:    xvcvsxddp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test41:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    xvcvsxddp v2, v2
+; CHECK-FISL-NEXT:    xvcvsxddp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test41:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xvcvsxddp v2, v2
+; CHECK-LE-NEXT:    xvcvsxddp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %v = sitofp <2 x i64> %a to <2 x double>
   ret <2 x double> %v
 
 
 }
 
 define <2 x i64> @test42(<2 x double> %a) {
 ; CHECK-LABEL: test42:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xvcvdpuxds v2, v2
+; CHECK-NEXT:    xvcvdpuxds v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test42:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    xvcvdpuxds v2, v2
+; CHECK-REG-NEXT:    xvcvdpuxds v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test42:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    xvcvdpuxds v2, v2
+; CHECK-FISL-NEXT:    xvcvdpuxds v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test42:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xvcvdpuxds v2, v2
+; CHECK-LE-NEXT:    xvcvdpuxds v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %v = fptoui <2 x double> %a to <2 x i64>
   ret <2 x i64> %v
 
 
 }
 
 define <2 x i64> @test43(<2 x double> %a) {
 ; CHECK-LABEL: test43:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xvcvdpsxds v2, v2
+; CHECK-NEXT:    xvcvdpsxds v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test43:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    xvcvdpsxds v2, v2
+; CHECK-REG-NEXT:    xvcvdpsxds v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test43:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    xvcvdpsxds v2, v2
+; CHECK-FISL-NEXT:    xvcvdpsxds v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test43:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xvcvdpsxds v2, v2
+; CHECK-LE-NEXT:    xvcvdpsxds v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %v = fptosi <2 x double> %a to <2 x i64>
   ret <2 x i64> %v
 
 
 }
 
 define <2 x float> @test44(<2 x i64> %a) {
 ; CHECK-LABEL: test44:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    addi r4, r1, -64
-; CHECK-NEXT:    stxvd2x v2, 0, r3
+; CHECK-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    ld r3, -8(r1)
 ; CHECK-NEXT:    std r3, -24(r1)
 ; CHECK-NEXT:    ld r3, -16(r1)
-; CHECK-NEXT:    lfd f0, -24(r1)
+; CHECK-NEXT:    lfd f0, -24(r1) # Vec Defs: F0(VSR0)
 ; CHECK-NEXT:    std r3, -32(r1)
 ; CHECK-NEXT:    addi r3, r1, -48
-; CHECK-NEXT:    fcfidus f0, f0
-; CHECK-NEXT:    stfs f0, -48(r1)
-; CHECK-NEXT:    lfd f0, -32(r1)
-; CHECK-NEXT:    fcfidus f0, f0
-; CHECK-NEXT:    stfs f0, -64(r1)
-; CHECK-NEXT:    lxvw4x v2, 0, r3
-; CHECK-NEXT:    lxvw4x v3, 0, r4
-; CHECK-NEXT:    vmrghw v2, v3, v2
+; CHECK-NEXT:    fcfidus f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    stfs f0, -48(r1) # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    lfd f0, -32(r1) # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    fcfidus f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    stfs f0, -64(r1) # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    lxvw4x v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    lxvw4x v3, 0, r4 # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    vmrghw v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test44:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -16
 ; CHECK-REG-NEXT:    addi r4, r1, -64
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    ld r3, -8(r1)
 ; CHECK-REG-NEXT:    std r3, -24(r1)
 ; CHECK-REG-NEXT:    ld r3, -16(r1)
-; CHECK-REG-NEXT:    lfd f0, -24(r1)
+; CHECK-REG-NEXT:    lfd f0, -24(r1) # Vec Defs: F0(VSR0)
 ; CHECK-REG-NEXT:    std r3, -32(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -48
-; CHECK-REG-NEXT:    fcfidus f0, f0
-; CHECK-REG-NEXT:    stfs f0, -48(r1)
-; CHECK-REG-NEXT:    lfd f0, -32(r1)
-; CHECK-REG-NEXT:    fcfidus f0, f0
-; CHECK-REG-NEXT:    stfs f0, -64(r1)
-; CHECK-REG-NEXT:    lxvw4x v2, 0, r3
-; CHECK-REG-NEXT:    lxvw4x v3, 0, r4
-; CHECK-REG-NEXT:    vmrghw v2, v3, v2
+; CHECK-REG-NEXT:    fcfidus f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-REG-NEXT:    stfs f0, -48(r1) # Vec Uses: F0(VSR0)
+; CHECK-REG-NEXT:    lfd f0, -32(r1) # Vec Defs: F0(VSR0)
+; CHECK-REG-NEXT:    fcfidus f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-REG-NEXT:    stfs f0, -64(r1) # Vec Uses: F0(VSR0)
+; CHECK-REG-NEXT:    lxvw4x v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-REG-NEXT:    lxvw4x v3, 0, r4 # Vec Defs: V3(VSR35)
+; CHECK-REG-NEXT:    vmrghw v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test44:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
-; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    ld r3, -8(r1)
 ; CHECK-FISL-NEXT:    std r3, -24(r1)
 ; CHECK-FISL-NEXT:    ld r3, -16(r1)
 ; CHECK-FISL-NEXT:    std r3, -32(r1)
-; CHECK-FISL-NEXT:    lfd f0, -24(r1)
-; CHECK-FISL-NEXT:    fcfidus f0, f0
-; CHECK-FISL-NEXT:    stfs f0, -48(r1)
-; CHECK-FISL-NEXT:    lfd f0, -32(r1)
-; CHECK-FISL-NEXT:    fcfidus f0, f0
-; CHECK-FISL-NEXT:    stfs f0, -64(r1)
+; CHECK-FISL-NEXT:    lfd f0, -24(r1) # Vec Defs: F0(VSR0)
+; CHECK-FISL-NEXT:    fcfidus f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-FISL-NEXT:    stfs f0, -48(r1) # Vec Uses: F0(VSR0)
+; CHECK-FISL-NEXT:    lfd f0, -32(r1) # Vec Defs: F0(VSR0)
+; CHECK-FISL-NEXT:    fcfidus f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-FISL-NEXT:    stfs f0, -64(r1) # Vec Uses: F0(VSR0)
 ; CHECK-FISL-NEXT:    addi r3, r1, -48
-; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3
+; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3 # Vec Defs: V3(VSR35)
 ; CHECK-FISL-NEXT:    addi r3, r1, -64
-; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3
-; CHECK-FISL-NEXT:    vmrghw v2, v2, v3
+; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-FISL-NEXT:    vmrghw v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test44:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxswapd vs0, v2
-; CHECK-LE-NEXT:    xscvuxdsp f1, v2
-; CHECK-LE-NEXT:    xscvuxdsp f0, f0
-; CHECK-LE-NEXT:    xscvdpspn v3, f1
-; CHECK-LE-NEXT:    xscvdpspn v2, f0
-; CHECK-LE-NEXT:    vmrghw v2, v3, v2
+; CHECK-LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-LE-NEXT:    xscvuxdsp f1, v2 # Vec Defs: F1(VSR1) Vec Uses: VF2(VSR2)
+; CHECK-LE-NEXT:    xscvuxdsp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-LE-NEXT:    xscvdpspn v3, f1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; CHECK-LE-NEXT:    xscvdpspn v2, f0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; CHECK-LE-NEXT:    vmrghw v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %v = uitofp <2 x i64> %a to <2 x float>
   ret <2 x float> %v
 
 ; FIXME: The code quality here looks pretty bad.
 }
 
 define <2 x float> @test45(<2 x i64> %a) {
 ; CHECK-LABEL: test45:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    addi r4, r1, -64
-; CHECK-NEXT:    stxvd2x v2, 0, r3
+; CHECK-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    ld r3, -8(r1)
 ; CHECK-NEXT:    std r3, -24(r1)
 ; CHECK-NEXT:    ld r3, -16(r1)
-; CHECK-NEXT:    lfd f0, -24(r1)
+; CHECK-NEXT:    lfd f0, -24(r1) # Vec Defs: F0(VSR0)
 ; CHECK-NEXT:    std r3, -32(r1)
 ; CHECK-NEXT:    addi r3, r1, -48
-; CHECK-NEXT:    fcfids f0, f0
-; CHECK-NEXT:    stfs f0, -48(r1)
-; CHECK-NEXT:    lfd f0, -32(r1)
-; CHECK-NEXT:    fcfids f0, f0
-; CHECK-NEXT:    stfs f0, -64(r1)
-; CHECK-NEXT:    lxvw4x v2, 0, r3
-; CHECK-NEXT:    lxvw4x v3, 0, r4
-; CHECK-NEXT:    vmrghw v2, v3, v2
+; CHECK-NEXT:    fcfids f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    stfs f0, -48(r1) # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    lfd f0, -32(r1) # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    fcfids f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    stfs f0, -64(r1) # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    lxvw4x v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    lxvw4x v3, 0, r4 # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    vmrghw v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test45:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -16
 ; CHECK-REG-NEXT:    addi r4, r1, -64
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    ld r3, -8(r1)
 ; CHECK-REG-NEXT:    std r3, -24(r1)
 ; CHECK-REG-NEXT:    ld r3, -16(r1)
-; CHECK-REG-NEXT:    lfd f0, -24(r1)
+; CHECK-REG-NEXT:    lfd f0, -24(r1) # Vec Defs: F0(VSR0)
 ; CHECK-REG-NEXT:    std r3, -32(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -48
-; CHECK-REG-NEXT:    fcfids f0, f0
-; CHECK-REG-NEXT:    stfs f0, -48(r1)
-; CHECK-REG-NEXT:    lfd f0, -32(r1)
-; CHECK-REG-NEXT:    fcfids f0, f0
-; CHECK-REG-NEXT:    stfs f0, -64(r1)
-; CHECK-REG-NEXT:    lxvw4x v2, 0, r3
-; CHECK-REG-NEXT:    lxvw4x v3, 0, r4
-; CHECK-REG-NEXT:    vmrghw v2, v3, v2
+; CHECK-REG-NEXT:    fcfids f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-REG-NEXT:    stfs f0, -48(r1) # Vec Uses: F0(VSR0)
+; CHECK-REG-NEXT:    lfd f0, -32(r1) # Vec Defs: F0(VSR0)
+; CHECK-REG-NEXT:    fcfids f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-REG-NEXT:    stfs f0, -64(r1) # Vec Uses: F0(VSR0)
+; CHECK-REG-NEXT:    lxvw4x v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-REG-NEXT:    lxvw4x v3, 0, r4 # Vec Defs: V3(VSR35)
+; CHECK-REG-NEXT:    vmrghw v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test45:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
-; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    ld r3, -8(r1)
 ; CHECK-FISL-NEXT:    std r3, -24(r1)
 ; CHECK-FISL-NEXT:    ld r3, -16(r1)
 ; CHECK-FISL-NEXT:    std r3, -32(r1)
-; CHECK-FISL-NEXT:    lfd f0, -24(r1)
-; CHECK-FISL-NEXT:    fcfids f0, f0
-; CHECK-FISL-NEXT:    stfs f0, -48(r1)
-; CHECK-FISL-NEXT:    lfd f0, -32(r1)
-; CHECK-FISL-NEXT:    fcfids f0, f0
-; CHECK-FISL-NEXT:    stfs f0, -64(r1)
+; CHECK-FISL-NEXT:    lfd f0, -24(r1) # Vec Defs: F0(VSR0)
+; CHECK-FISL-NEXT:    fcfids f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-FISL-NEXT:    stfs f0, -48(r1) # Vec Uses: F0(VSR0)
+; CHECK-FISL-NEXT:    lfd f0, -32(r1) # Vec Defs: F0(VSR0)
+; CHECK-FISL-NEXT:    fcfids f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-FISL-NEXT:    stfs f0, -64(r1) # Vec Uses: F0(VSR0)
 ; CHECK-FISL-NEXT:    addi r3, r1, -48
-; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3
+; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3 # Vec Defs: V3(VSR35)
 ; CHECK-FISL-NEXT:    addi r3, r1, -64
-; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3
-; CHECK-FISL-NEXT:    vmrghw v2, v2, v3
+; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-FISL-NEXT:    vmrghw v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test45:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxswapd vs0, v2
-; CHECK-LE-NEXT:    xscvsxdsp f1, v2
-; CHECK-LE-NEXT:    xscvsxdsp f0, f0
-; CHECK-LE-NEXT:    xscvdpspn v3, f1
-; CHECK-LE-NEXT:    xscvdpspn v2, f0
-; CHECK-LE-NEXT:    vmrghw v2, v3, v2
+; CHECK-LE-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-LE-NEXT:    xscvsxdsp f1, v2 # Vec Defs: F1(VSR1) Vec Uses: VF2(VSR2)
+; CHECK-LE-NEXT:    xscvsxdsp f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-LE-NEXT:    xscvdpspn v3, f1 # Vec Defs: V3(VSR35) Vec Uses: F1(VSR1)
+; CHECK-LE-NEXT:    xscvdpspn v2, f0 # Vec Defs: V2(VSR34) Vec Uses: F0(VSR0)
+; CHECK-LE-NEXT:    vmrghw v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %v = sitofp <2 x i64> %a to <2 x float>
   ret <2 x float> %v
 
 ; FIXME: The code quality here looks pretty bad.
 }
 
 define <2 x i64> @test46(<2 x float> %a) {
 ; CHECK-LABEL: test46:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -48
-; CHECK-NEXT:    stxvw4x v2, 0, r3
-; CHECK-NEXT:    lfs f0, -44(r1)
-; CHECK-NEXT:    xscvdpuxds f0, f0
-; CHECK-NEXT:    stfd f0, -32(r1)
-; CHECK-NEXT:    lfs f0, -48(r1)
+; CHECK-NEXT:    stxvw4x v2, 0, r3 # Vec Uses: V2(VSR34)
+; CHECK-NEXT:    lfs f0, -44(r1) # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    xscvdpuxds f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    stfd f0, -32(r1) # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    lfs f0, -48(r1) # Vec Defs: F0(VSR0)
 ; CHECK-NEXT:    ld r3, -32(r1)
-; CHECK-NEXT:    xscvdpuxds f0, f0
+; CHECK-NEXT:    xscvdpuxds f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    std r3, -8(r1)
-; CHECK-NEXT:    stfd f0, -24(r1)
+; CHECK-NEXT:    stfd f0, -24(r1) # Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    ld r3, -24(r1)
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
-; CHECK-NEXT:    lxvd2x v2, 0, r3
+; CHECK-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test46:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -48
-; CHECK-REG-NEXT:    stxvw4x v2, 0, r3
-; CHECK-REG-NEXT:    lfs f0, -44(r1)
-; CHECK-REG-NEXT:    xscvdpuxds f0, f0
-; CHECK-REG-NEXT:    stfd f0, -32(r1)
-; CHECK-REG-NEXT:    lfs f0, -48(r1)
+; CHECK-REG-NEXT:    stxvw4x v2, 0, r3 # Vec Uses: V2(VSR34)
+; CHECK-REG-NEXT:    lfs f0, -44(r1) # Vec Defs: F0(VSR0)
+; CHECK-REG-NEXT:    xscvdpuxds f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-REG-NEXT:    stfd f0, -32(r1) # Vec Uses: F0(VSR0)
+; CHECK-REG-NEXT:    lfs f0, -48(r1) # Vec Defs: F0(VSR0)
 ; CHECK-REG-NEXT:    ld r3, -32(r1)
-; CHECK-REG-NEXT:    xscvdpuxds f0, f0
+; CHECK-REG-NEXT:    xscvdpuxds f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
 ; CHECK-REG-NEXT:    std r3, -8(r1)
-; CHECK-REG-NEXT:    stfd f0, -24(r1)
+; CHECK-REG-NEXT:    stfd f0, -24(r1) # Vec Uses: F0(VSR0)
 ; CHECK-REG-NEXT:    ld r3, -24(r1)
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
-; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test46:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    addi r3, r1, -48
-; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3
-; CHECK-FISL-NEXT:    lfs f0, -44(r1)
-; CHECK-FISL-NEXT:    xscvdpuxds f0, f0
-; CHECK-FISL-NEXT:    stfd f0, -32(r1)
-; CHECK-FISL-NEXT:    lfs f0, -48(r1)
-; CHECK-FISL-NEXT:    xscvdpuxds f0, f0
-; CHECK-FISL-NEXT:    stfd f0, -24(r1)
+; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3 # Vec Uses: V2(VSR34)
+; CHECK-FISL-NEXT:    lfs f0, -44(r1) # Vec Defs: F0(VSR0)
+; CHECK-FISL-NEXT:    xscvdpuxds f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-FISL-NEXT:    stfd f0, -32(r1) # Vec Uses: F0(VSR0)
+; CHECK-FISL-NEXT:    lfs f0, -48(r1) # Vec Defs: F0(VSR0)
+; CHECK-FISL-NEXT:    xscvdpuxds f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-FISL-NEXT:    stfd f0, -24(r1) # Vec Uses: F0(VSR0)
 ; CHECK-FISL-NEXT:    ld r3, -32(r1)
 ; CHECK-FISL-NEXT:    std r3, -8(r1)
 ; CHECK-FISL-NEXT:    ld r3, -24(r1)
 ; CHECK-FISL-NEXT:    std r3, -16(r1)
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
-; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test46:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxmrglw vs0, v2, v2
-; CHECK-LE-NEXT:    xvcvspdp vs0, vs0
-; CHECK-LE-NEXT:    xvcvdpuxds v2, vs0
+; CHECK-LE-NEXT:    xxmrglw vs0, v2, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-LE-NEXT:    xvcvspdp vs0, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)
+; CHECK-LE-NEXT:    xvcvdpuxds v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
 ; CHECK-LE-NEXT:    blr
   %v = fptoui <2 x float> %a to <2 x i64>
   ret <2 x i64> %v
 
 ; FIXME: The code quality here looks pretty bad.
 }
 
 define <2 x i64> @test47(<2 x float> %a) {
 ; CHECK-LABEL: test47:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -48
-; CHECK-NEXT:    stxvw4x v2, 0, r3
-; CHECK-NEXT:    lfs f0, -44(r1)
-; CHECK-NEXT:    xscvdpsxds f0, f0
-; CHECK-NEXT:    stfd f0, -32(r1)
-; CHECK-NEXT:    lfs f0, -48(r1)
+; CHECK-NEXT:    stxvw4x v2, 0, r3 # Vec Uses: V2(VSR34)
+; CHECK-NEXT:    lfs f0, -44(r1) # Vec Defs: F0(VSR0)
+; CHECK-NEXT:    xscvdpsxds f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-NEXT:    stfd f0, -32(r1) # Vec Uses: F0(VSR0)
+; CHECK-NEXT:    lfs f0, -48(r1) # Vec Defs: F0(VSR0)
 ; CHECK-NEXT:    ld r3, -32(r1)
-; CHECK-NEXT:    xscvdpsxds f0, f0
+; CHECK-NEXT:    xscvdpsxds f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    std r3, -8(r1)
-; CHECK-NEXT:    stfd f0, -24(r1)
+; CHECK-NEXT:    stfd f0, -24(r1) # Vec Uses: F0(VSR0)
 ; CHECK-NEXT:    ld r3, -24(r1)
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
-; CHECK-NEXT:    lxvd2x v2, 0, r3
+; CHECK-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test47:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -48
-; CHECK-REG-NEXT:    stxvw4x v2, 0, r3
-; CHECK-REG-NEXT:    lfs f0, -44(r1)
-; CHECK-REG-NEXT:    xscvdpsxds f0, f0
-; CHECK-REG-NEXT:    stfd f0, -32(r1)
-; CHECK-REG-NEXT:    lfs f0, -48(r1)
+; CHECK-REG-NEXT:    stxvw4x v2, 0, r3 # Vec Uses: V2(VSR34)
+; CHECK-REG-NEXT:    lfs f0, -44(r1) # Vec Defs: F0(VSR0)
+; CHECK-REG-NEXT:    xscvdpsxds f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-REG-NEXT:    stfd f0, -32(r1) # Vec Uses: F0(VSR0)
+; CHECK-REG-NEXT:    lfs f0, -48(r1) # Vec Defs: F0(VSR0)
 ; CHECK-REG-NEXT:    ld r3, -32(r1)
-; CHECK-REG-NEXT:    xscvdpsxds f0, f0
+; CHECK-REG-NEXT:    xscvdpsxds f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
 ; CHECK-REG-NEXT:    std r3, -8(r1)
-; CHECK-REG-NEXT:    stfd f0, -24(r1)
+; CHECK-REG-NEXT:    stfd f0, -24(r1) # Vec Uses: F0(VSR0)
 ; CHECK-REG-NEXT:    ld r3, -24(r1)
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
-; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test47:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    addi r3, r1, -48
-; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3
-; CHECK-FISL-NEXT:    lfs f0, -44(r1)
-; CHECK-FISL-NEXT:    xscvdpsxds f0, f0
-; CHECK-FISL-NEXT:    stfd f0, -32(r1)
-; CHECK-FISL-NEXT:    lfs f0, -48(r1)
-; CHECK-FISL-NEXT:    xscvdpsxds f0, f0
-; CHECK-FISL-NEXT:    stfd f0, -24(r1)
+; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3 # Vec Uses: V2(VSR34)
+; CHECK-FISL-NEXT:    lfs f0, -44(r1) # Vec Defs: F0(VSR0)
+; CHECK-FISL-NEXT:    xscvdpsxds f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-FISL-NEXT:    stfd f0, -32(r1) # Vec Uses: F0(VSR0)
+; CHECK-FISL-NEXT:    lfs f0, -48(r1) # Vec Defs: F0(VSR0)
+; CHECK-FISL-NEXT:    xscvdpsxds f0, f0 # Vec Defs: F0(VSR0) Vec Uses: F0(VSR0)
+; CHECK-FISL-NEXT:    stfd f0, -24(r1) # Vec Uses: F0(VSR0)
 ; CHECK-FISL-NEXT:    ld r3, -32(r1)
 ; CHECK-FISL-NEXT:    std r3, -8(r1)
 ; CHECK-FISL-NEXT:    ld r3, -24(r1)
 ; CHECK-FISL-NEXT:    std r3, -16(r1)
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
-; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test47:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxmrglw vs0, v2, v2
-; CHECK-LE-NEXT:    xvcvspdp vs0, vs0
-; CHECK-LE-NEXT:    xvcvdpsxds v2, vs0
+; CHECK-LE-NEXT:    xxmrglw vs0, v2, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-LE-NEXT:    xvcvspdp vs0, vs0 # Vec Defs: VSL0(VSR0) Vec Uses: VSL0(VSR0)
+; CHECK-LE-NEXT:    xvcvdpsxds v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
 ; CHECK-LE-NEXT:    blr
   %v = fptosi <2 x float> %a to <2 x i64>
   ret <2 x i64> %v
 
 ; FIXME: The code quality here looks pretty bad.
 }
 
 define <2 x double> @test50(double* %a) {
 ; CHECK-LABEL: test50:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lxvdsx v2, 0, r3
+; CHECK-NEXT:    lxvdsx v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test50:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    lxvdsx v2, 0, r3
+; CHECK-REG-NEXT:    lxvdsx v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test50:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    lxvdsx v2, 0, r3
+; CHECK-FISL-NEXT:    lxvdsx v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test50:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    lxvdsx v2, 0, r3
+; CHECK-LE-NEXT:    lxvdsx v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %v = load double, double* %a, align 8
   %w = insertelement <2 x double> undef, double %v, i32 0
   %x = insertelement <2 x double> %w, double %v, i32 1
   ret <2 x double> %x
 
 
 }
 
 define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: test51:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxspltd v2, v2, 0
+; CHECK-NEXT:    xxspltd v2, v2, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test51:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    xxspltd v2, v2, 0
+; CHECK-REG-NEXT:    xxspltd v2, v2, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test51:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    xxspltd v2, v2, 0
+; CHECK-FISL-NEXT:    xxspltd v2, v2, 0 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test51:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxspltd v2, v2, 1
+; CHECK-LE-NEXT:    xxspltd v2, v2, 1 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 0>
   ret <2 x double> %v
 
 
 }
 
 define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: test52:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxmrghd v2, v2, v3
+; CHECK-NEXT:    xxmrghd v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test52:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    xxmrghd v2, v2, v3
+; CHECK-REG-NEXT:    xxmrghd v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test52:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    xxmrghd v2, v2, v3
+; CHECK-FISL-NEXT:    xxmrghd v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test52:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxmrgld v2, v3, v2
+; CHECK-LE-NEXT:    xxmrgld v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2>
   ret <2 x double> %v
 
 
 }
 
 define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: test53:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxmrghd v2, v3, v2
+; CHECK-NEXT:    xxmrghd v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test53:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    xxmrghd v2, v3, v2
+; CHECK-REG-NEXT:    xxmrghd v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test53:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    xxmrghd v2, v3, v2
+; CHECK-FISL-NEXT:    xxmrghd v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test53:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxmrgld v2, v2, v3
+; CHECK-LE-NEXT:    xxmrgld v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
   %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 2, i32 0>
   ret <2 x double> %v
 
 
 }
 
 define <2 x double> @test54(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: test54:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxpermdi v2, v2, v3, 2
+; CHECK-NEXT:    xxpermdi v2, v2, v3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test54:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    xxpermdi v2, v2, v3, 2
+; CHECK-REG-NEXT:    xxpermdi v2, v2, v3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test54:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    xxpermdi v2, v2, v3, 2
+; CHECK-FISL-NEXT:    xxpermdi v2, v2, v3, 2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test54:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxpermdi v2, v3, v2, 2
+; CHECK-LE-NEXT:    xxpermdi v2, v3, v2, 2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2>
   ret <2 x double> %v
 
 
 }
 
 define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: test55:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxmrgld v2, v2, v3
+; CHECK-NEXT:    xxmrgld v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test55:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    xxmrgld v2, v2, v3
+; CHECK-REG-NEXT:    xxmrgld v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test55:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    xxmrgld v2, v2, v3
+; CHECK-FISL-NEXT:    xxmrgld v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test55:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxmrghd v2, v3, v2
+; CHECK-LE-NEXT:    xxmrghd v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3>
   ret <2 x double> %v
 
 
 }
 
 define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test56:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxmrgld v2, v2, v3
+; CHECK-NEXT:    xxmrgld v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test56:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    xxmrgld v2, v2, v3
+; CHECK-REG-NEXT:    xxmrgld v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test56:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    xxmrgld v2, v2, v3
+; CHECK-FISL-NEXT:    xxmrgld v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test56:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxmrghd v2, v3, v2
+; CHECK-LE-NEXT:    xxmrghd v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %v = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
   ret <2 x i64> %v
 
 
 }
 
 define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test60:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -32
 ; CHECK-NEXT:    addi r4, r1, -48
-; CHECK-NEXT:    stxvd2x v3, 0, r3
-; CHECK-NEXT:    stxvd2x v2, 0, r4
+; CHECK-NEXT:    stxvd2x v3, 0, r3 # Vec Uses: V3(VSR35)
+; CHECK-NEXT:    stxvd2x v2, 0, r4 # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    lwz r3, -20(r1)
 ; CHECK-NEXT:    ld r4, -40(r1)
 ; CHECK-NEXT:    sld r3, r4, r3
 ; CHECK-NEXT:    ld r4, -48(r1)
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    lwz r3, -28(r1)
 ; CHECK-NEXT:    sld r3, r4, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
-; CHECK-NEXT:    lxvd2x v2, 0, r3
+; CHECK-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test60:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -32
 ; CHECK-REG-NEXT:    addi r4, r1, -48
-; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
+; CHECK-REG-NEXT:    stxvd2x v3, 0, r3 # Vec Uses: V3(VSR35)
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r4 # Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    lwz r3, -20(r1)
 ; CHECK-REG-NEXT:    ld r4, -40(r1)
 ; CHECK-REG-NEXT:    sld r3, r4, r3
 ; CHECK-REG-NEXT:    ld r4, -48(r1)
 ; CHECK-REG-NEXT:    std r3, -8(r1)
 ; CHECK-REG-NEXT:    lwz r3, -28(r1)
 ; CHECK-REG-NEXT:    sld r3, r4, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
-; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test60:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    addi r3, r1, -32
-; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3 # Vec Uses: V3(VSR35)
 ; CHECK-FISL-NEXT:    addi r3, r1, -48
-; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    lwz r4, -20(r1)
 ; CHECK-FISL-NEXT:    ld r3, -40(r1)
 ; CHECK-FISL-NEXT:    sld r3, r3, r4
 ; CHECK-FISL-NEXT:    std r3, -8(r1)
 ; CHECK-FISL-NEXT:    lwz r4, -28(r1)
 ; CHECK-FISL-NEXT:    ld r3, -48(r1)
 ; CHECK-FISL-NEXT:    sld r3, r3, r4
 ; CHECK-FISL-NEXT:    std r3, -16(r1)
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
-; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test60:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    vsld v2, v2, v3
+; CHECK-LE-NEXT:    vsld v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
   %v = shl <2 x i64> %a, %b
   ret <2 x i64> %v
 
 ; This should scalarize, and the current code quality is not good.
 }
 
 define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test61:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -32
 ; CHECK-NEXT:    addi r4, r1, -48
-; CHECK-NEXT:    stxvd2x v3, 0, r3
-; CHECK-NEXT:    stxvd2x v2, 0, r4
+; CHECK-NEXT:    stxvd2x v3, 0, r3 # Vec Uses: V3(VSR35)
+; CHECK-NEXT:    stxvd2x v2, 0, r4 # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    lwz r3, -20(r1)
 ; CHECK-NEXT:    ld r4, -40(r1)
 ; CHECK-NEXT:    srd r3, r4, r3
 ; CHECK-NEXT:    ld r4, -48(r1)
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    lwz r3, -28(r1)
 ; CHECK-NEXT:    srd r3, r4, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
-; CHECK-NEXT:    lxvd2x v2, 0, r3
+; CHECK-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test61:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -32
 ; CHECK-REG-NEXT:    addi r4, r1, -48
-; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
+; CHECK-REG-NEXT:    stxvd2x v3, 0, r3 # Vec Uses: V3(VSR35)
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r4 # Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    lwz r3, -20(r1)
 ; CHECK-REG-NEXT:    ld r4, -40(r1)
 ; CHECK-REG-NEXT:    srd r3, r4, r3
 ; CHECK-REG-NEXT:    ld r4, -48(r1)
 ; CHECK-REG-NEXT:    std r3, -8(r1)
 ; CHECK-REG-NEXT:    lwz r3, -28(r1)
 ; CHECK-REG-NEXT:    srd r3, r4, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
-; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test61:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    addi r3, r1, -32
-; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3 # Vec Uses: V3(VSR35)
 ; CHECK-FISL-NEXT:    addi r3, r1, -48
-; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    lwz r4, -20(r1)
 ; CHECK-FISL-NEXT:    ld r3, -40(r1)
 ; CHECK-FISL-NEXT:    srd r3, r3, r4
 ; CHECK-FISL-NEXT:    std r3, -8(r1)
 ; CHECK-FISL-NEXT:    lwz r4, -28(r1)
 ; CHECK-FISL-NEXT:    ld r3, -48(r1)
 ; CHECK-FISL-NEXT:    srd r3, r3, r4
 ; CHECK-FISL-NEXT:    std r3, -16(r1)
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
-; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test61:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    vsrd v2, v2, v3
+; CHECK-LE-NEXT:    vsrd v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
   %v = lshr <2 x i64> %a, %b
   ret <2 x i64> %v
 
 ; This should scalarize, and the current code quality is not good.
 }
 
 define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test62:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -32
 ; CHECK-NEXT:    addi r4, r1, -48
-; CHECK-NEXT:    stxvd2x v3, 0, r3
-; CHECK-NEXT:    stxvd2x v2, 0, r4
+; CHECK-NEXT:    stxvd2x v3, 0, r3 # Vec Uses: V3(VSR35)
+; CHECK-NEXT:    stxvd2x v2, 0, r4 # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    lwz r3, -20(r1)
 ; CHECK-NEXT:    ld r4, -40(r1)
 ; CHECK-NEXT:    srad r3, r4, r3
 ; CHECK-NEXT:    ld r4, -48(r1)
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    lwz r3, -28(r1)
 ; CHECK-NEXT:    srad r3, r4, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
-; CHECK-NEXT:    lxvd2x v2, 0, r3
+; CHECK-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test62:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -32
 ; CHECK-REG-NEXT:    addi r4, r1, -48
-; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
+; CHECK-REG-NEXT:    stxvd2x v3, 0, r3 # Vec Uses: V3(VSR35)
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r4 # Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    lwz r3, -20(r1)
 ; CHECK-REG-NEXT:    ld r4, -40(r1)
 ; CHECK-REG-NEXT:    srad r3, r4, r3
 ; CHECK-REG-NEXT:    ld r4, -48(r1)
 ; CHECK-REG-NEXT:    std r3, -8(r1)
 ; CHECK-REG-NEXT:    lwz r3, -28(r1)
 ; CHECK-REG-NEXT:    srad r3, r4, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
-; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test62:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    addi r3, r1, -32
-; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3 # Vec Uses: V3(VSR35)
 ; CHECK-FISL-NEXT:    addi r3, r1, -48
-; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    lwz r4, -20(r1)
 ; CHECK-FISL-NEXT:    ld r3, -40(r1)
 ; CHECK-FISL-NEXT:    srad r3, r3, r4
 ; CHECK-FISL-NEXT:    std r3, -8(r1)
 ; CHECK-FISL-NEXT:    lwz r4, -28(r1)
 ; CHECK-FISL-NEXT:    ld r3, -48(r1)
 ; CHECK-FISL-NEXT:    srad r3, r3, r4
 ; CHECK-FISL-NEXT:    std r3, -16(r1)
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
-; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test62:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    vsrad v2, v2, v3
+; CHECK-LE-NEXT:    vsrad v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
   %v = ashr <2 x i64> %a, %b
   ret <2 x i64> %v
 
 ; This should scalarize, and the current code quality is not good.
 }
 
 define double @test63(<2 x double> %a) {
 ; CHECK-LABEL: test63:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxlor f1, v2, v2
+; CHECK-NEXT:    xxlor f1, v2, v2 # Vec Defs: F1(VSR1) Vec Uses: VF2(VSR2)VF2(VSR2)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test63:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    xxlor f1, v2, v2
+; CHECK-REG-NEXT:    xxlor f1, v2, v2 # Vec Defs: F1(VSR1) Vec Uses: VF2(VSR2)VF2(VSR2)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test63:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    xxlor f1, v2, v2
+; CHECK-FISL-NEXT:    xxlor f1, v2, v2 # Vec Defs: F1(VSR1) Vec Uses: VF2(VSR2)VF2(VSR2)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test63:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxswapd vs1, v2
+; CHECK-LE-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-LE-NEXT:    blr
   %v = extractelement <2 x double> %a, i32 0
   ret double %v
 
 
 
 }
 
 define double @test64(<2 x double> %a) {
 ; CHECK-LABEL: test64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxswapd vs1, v2
+; CHECK-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test64:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    xxswapd vs1, v2
+; CHECK-REG-NEXT:    xxswapd vs1, v2 # Vec Defs: VSL1(VSR1) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-REG-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test64:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    xxswapd vs0, v2
-; CHECK-FISL-NEXT:    fmr f1, f0
+; CHECK-FISL-NEXT:    xxswapd vs0, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-FISL-NEXT:    fmr f1, f0 # Vec Defs: F1(VSR1) Vec Uses: F0(VSR0)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test64:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxlor f1, v2, v2
+; CHECK-LE-NEXT:    xxlor f1, v2, v2 # Vec Defs: F1(VSR1) Vec Uses: VF2(VSR2)VF2(VSR2)
 ; CHECK-LE-NEXT:    blr
   %v = extractelement <2 x double> %a, i32 1
   ret double %v
 
 
 
 }
 
 define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test65:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vcmpequw v2, v2, v3
+; CHECK-NEXT:    vcmpequw v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    addis r3, r2, .LCPI59_0@toc@ha
 ; CHECK-NEXT:    addi r3, r3, .LCPI59_0@toc@l
-; CHECK-NEXT:    lxvw4x v3, 0, r3
-; CHECK-NEXT:    vperm v3, v2, v2, v3
-; CHECK-NEXT:    xxland v2, v3, v2
+; CHECK-NEXT:    lxvw4x v3, 0, r3 # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    vperm v3, v2, v2, v3 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
+; CHECK-NEXT:    xxland v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test65:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    vcmpequw v2, v2, v3
+; CHECK-REG-NEXT:    vcmpequw v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    addis r3, r2, .LCPI59_0@toc@ha
 ; CHECK-REG-NEXT:    addi r3, r3, .LCPI59_0@toc@l
-; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
-; CHECK-REG-NEXT:    vperm v3, v2, v2, v3
-; CHECK-REG-NEXT:    xxland v2, v3, v2
+; CHECK-REG-NEXT:    lxvw4x v3, 0, r3 # Vec Defs: V3(VSR35)
+; CHECK-REG-NEXT:    vperm v3, v2, v2, v3 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
+; CHECK-REG-NEXT:    xxland v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test65:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    vcmpequw v3, v2, v3
+; CHECK-FISL-NEXT:    vcmpequw v3, v2, v3 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    addis r3, r2, .LCPI59_0@toc@ha
 ; CHECK-FISL-NEXT:    addi r3, r3, .LCPI59_0@toc@l
-; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3
-; CHECK-FISL-NEXT:    vperm v2, v3, v3, v2
-; CHECK-FISL-NEXT:    xxland v2, v2, v3
+; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-FISL-NEXT:    vperm v2, v3, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)V2(VSR34)
+; CHECK-FISL-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test65:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    vcmpequd v2, v2, v3
+; CHECK-LE-NEXT:    vcmpequd v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
   %w = icmp eq <2 x i64> %a, %b
   ret <2 x i1> %w
 
 
 
 }
 
 define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test66:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vcmpequw v2, v2, v3
+; CHECK-NEXT:    vcmpequw v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    addis r3, r2, .LCPI60_0@toc@ha
 ; CHECK-NEXT:    addi r3, r3, .LCPI60_0@toc@l
-; CHECK-NEXT:    lxvw4x v3, 0, r3
-; CHECK-NEXT:    xxlnor v2, v2, v2
-; CHECK-NEXT:    vperm v3, v2, v2, v3
-; CHECK-NEXT:    xxland v2, v3, v2
+; CHECK-NEXT:    lxvw4x v3, 0, r3 # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    xxlnor v2, v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    vperm v3, v2, v2, v3 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
+; CHECK-NEXT:    xxland v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test66:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    vcmpequw v2, v2, v3
+; CHECK-REG-NEXT:    vcmpequw v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    addis r3, r2, .LCPI60_0@toc@ha
 ; CHECK-REG-NEXT:    addi r3, r3, .LCPI60_0@toc@l
-; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
-; CHECK-REG-NEXT:    xxlnor v2, v2, v2
-; CHECK-REG-NEXT:    vperm v3, v2, v2, v3
-; CHECK-REG-NEXT:    xxland v2, v3, v2
+; CHECK-REG-NEXT:    lxvw4x v3, 0, r3 # Vec Defs: V3(VSR35)
+; CHECK-REG-NEXT:    xxlnor v2, v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-REG-NEXT:    vperm v3, v2, v2, v3 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
+; CHECK-REG-NEXT:    xxland v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test66:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    vcmpequw v2, v2, v3
-; CHECK-FISL-NEXT:    xxlnor v3, v2, v2
+; CHECK-FISL-NEXT:    vcmpequw v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-FISL-NEXT:    xxlnor v3, v2, v2 # Vec Defs: V3(VSR35) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-FISL-NEXT:    addis r3, r2, .LCPI60_0@toc@ha
 ; CHECK-FISL-NEXT:    addi r3, r3, .LCPI60_0@toc@l
-; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3
-; CHECK-FISL-NEXT:    vperm v2, v3, v3, v2
-; CHECK-FISL-NEXT:    xxland v2, v2, v3
+; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-FISL-NEXT:    vperm v2, v3, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V3(VSR35)V2(VSR34)
+; CHECK-FISL-NEXT:    xxland v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test66:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    vcmpequd v2, v2, v3
-; CHECK-LE-NEXT:    xxlnor v2, v2, v2
+; CHECK-LE-NEXT:    vcmpequd v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-LE-NEXT:    xxlnor v2, v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %w = icmp ne <2 x i64> %a, %b
   ret <2 x i1> %w
 
 
 
 }
 
 define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test67:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -32
 ; CHECK-NEXT:    addi r4, r1, -48
-; CHECK-NEXT:    stxvd2x v3, 0, r3
-; CHECK-NEXT:    stxvd2x v2, 0, r4
+; CHECK-NEXT:    stxvd2x v3, 0, r3 # Vec Uses: V3(VSR35)
+; CHECK-NEXT:    stxvd2x v2, 0, r4 # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    ld r3, -24(r1)
 ; CHECK-NEXT:    ld r4, -40(r1)
 ; CHECK-NEXT:    ld r6, -48(r1)
 ; CHECK-NEXT:    cmpld r4, r3
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    li r4, -1
 ; CHECK-NEXT:    isellt r5, r4, r3
 ; CHECK-NEXT:    std r5, -8(r1)
 ; CHECK-NEXT:    ld r5, -32(r1)
 ; CHECK-NEXT:    cmpld r6, r5
 ; CHECK-NEXT:    isellt r3, r4, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
-; CHECK-NEXT:    lxvd2x v2, 0, r3
+; CHECK-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test67:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -32
 ; CHECK-REG-NEXT:    addi r4, r1, -48
-; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
+; CHECK-REG-NEXT:    stxvd2x v3, 0, r3 # Vec Uses: V3(VSR35)
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r4 # Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    ld r3, -24(r1)
 ; CHECK-REG-NEXT:    ld r4, -40(r1)
 ; CHECK-REG-NEXT:    ld r6, -48(r1)
 ; CHECK-REG-NEXT:    cmpld r4, r3
 ; CHECK-REG-NEXT:    li r3, 0
 ; CHECK-REG-NEXT:    li r4, -1
 ; CHECK-REG-NEXT:    isellt r5, r4, r3
 ; CHECK-REG-NEXT:    std r5, -8(r1)
 ; CHECK-REG-NEXT:    ld r5, -32(r1)
 ; CHECK-REG-NEXT:    cmpld r6, r5
 ; CHECK-REG-NEXT:    isellt r3, r4, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
-; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test67:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    addi r3, r1, -32
-; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3 # Vec Uses: V3(VSR35)
 ; CHECK-FISL-NEXT:    addi r3, r1, -48
-; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    ld r4, -24(r1)
 ; CHECK-FISL-NEXT:    ld r3, -40(r1)
 ; CHECK-FISL-NEXT:    cmpld r3, r4
 ; CHECK-FISL-NEXT:    li r4, 0
 ; CHECK-FISL-NEXT:    li r3, -1
 ; CHECK-FISL-NEXT:    isellt r5, r3, r4
 ; CHECK-FISL-NEXT:    std r5, -8(r1)
 ; CHECK-FISL-NEXT:    ld r6, -32(r1)
 ; CHECK-FISL-NEXT:    ld r5, -48(r1)
 ; CHECK-FISL-NEXT:    cmpld r5, r6
 ; CHECK-FISL-NEXT:    isellt r3, r3, r4
 ; CHECK-FISL-NEXT:    std r3, -16(r1)
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
-; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
+; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test67:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    vcmpgtud v2, v3, v2
+; CHECK-LE-NEXT:    vcmpgtud v2, v3, v2 # Vec Defs: V2(VSR34) Vec Uses: V3(VSR35)V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %w = icmp ult <2 x i64> %a, %b
   ret <2 x i1> %w
 
 ; This should scalarize, and the current code quality is not good.
 
 }
 
 define <2 x double> @test68(<2 x i32> %a) {
 ; CHECK-LABEL: test68:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxmrghw vs0, v2, v2
-; CHECK-NEXT:    xvcvsxwdp v2, vs0
+; CHECK-NEXT:    xxmrghw vs0, v2, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-NEXT:    xvcvsxwdp v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test68:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    xxmrghw vs0, v2, v2
-; CHECK-REG-NEXT:    xvcvsxwdp v2, vs0
+; CHECK-REG-NEXT:    xxmrghw vs0, v2, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-REG-NEXT:    xvcvsxwdp v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test68:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    xxmrghw vs0, v2, v2
-; CHECK-FISL-NEXT:    xvcvsxwdp v2, vs0
+; CHECK-FISL-NEXT:    xxmrghw vs0, v2, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-FISL-NEXT:    xvcvsxwdp v2, vs0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test68:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    xxmrglw v2, v2, v2
-; CHECK-LE-NEXT:    xvcvsxwdp v2, v2
+; CHECK-LE-NEXT:    xxmrglw v2, v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)
+; CHECK-LE-NEXT:    xvcvsxwdp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %w = sitofp <2 x i32> %a to <2 x double>
   ret <2 x double> %w
 
 
 }
 
 ; This gets scalarized so the code isn't great
 define <2 x double> @test69(<2 x i16> %a) {
 ; CHECK-LABEL: test69:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
 ; CHECK-NEXT:    addi r3, r3, .LCPI63_0@toc@l
-; CHECK-NEXT:    lxvw4x v3, 0, r3
+; CHECK-NEXT:    lxvw4x v3, 0, r3 # Vec Defs: V3(VSR35)
 ; CHECK-NEXT:    addi r3, r1, -32
-; CHECK-NEXT:    vperm v2, v2, v2, v3
-; CHECK-NEXT:    stxvd2x v2, 0, r3
+; CHECK-NEXT:    vperm v2, v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
+; CHECK-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    lha r3, -18(r1)
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    lha r3, -26(r1)
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
-; CHECK-NEXT:    lxvd2x v2, 0, r3
-; CHECK-NEXT:    xvcvsxddp v2, v2
+; CHECK-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    xvcvsxddp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test69:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
 ; CHECK-REG-NEXT:    addi r3, r3, .LCPI63_0@toc@l
-; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
+; CHECK-REG-NEXT:    lxvw4x v3, 0, r3 # Vec Defs: V3(VSR35)
 ; CHECK-REG-NEXT:    addi r3, r1, -32
-; CHECK-REG-NEXT:    vperm v2, v2, v2, v3
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    vperm v2, v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    lha r3, -18(r1)
 ; CHECK-REG-NEXT:    std r3, -8(r1)
 ; CHECK-REG-NEXT:    lha r3, -26(r1)
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
-; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
-; CHECK-REG-NEXT:    xvcvsxddp v2, v2
+; CHECK-REG-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-REG-NEXT:    xvcvsxddp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test69:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
 ; CHECK-FISL-NEXT:    addi r3, r3, .LCPI63_0@toc@l
-; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3
-; CHECK-FISL-NEXT:    vperm v2, v2, v2, v3
-; CHECK-FISL-NEXT:    xxlor vs0, v2, v2
+; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3 # Vec Defs: V3(VSR35)
+; CHECK-FISL-NEXT:    vperm v2, v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
+; CHECK-FISL-NEXT:    xxlor vs0, v2, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-FISL-NEXT:    addi r3, r1, -32
-; CHECK-FISL-NEXT:    stxvd2x vs0, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x vs0, 0, r3 # Vec Uses: VSL0(VSR0)
 ; CHECK-FISL-NEXT:    lha r3, -18(r1)
 ; CHECK-FISL-NEXT:    std r3, -8(r1)
 ; CHECK-FISL-NEXT:    lha r3, -26(r1)
 ; CHECK-FISL-NEXT:    std r3, -16(r1)
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
-; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
-; CHECK-FISL-NEXT:    xvcvsxddp v2, v2
+; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-FISL-NEXT:    xvcvsxddp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test69:
 ; CHECK-LE:       # %bb.0:
 ; CHECK-LE-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
 ; CHECK-LE-NEXT:    addi r3, r3, .LCPI63_0@toc@l
-; CHECK-LE-NEXT:    lvx v3, 0, r3
+; CHECK-LE-NEXT:    lvx v3, 0, r3 # Vec Defs: V3(VSR35)
 ; CHECK-LE-NEXT:    addis r3, r2, .LCPI63_1@toc@ha
 ; CHECK-LE-NEXT:    addi r3, r3, .LCPI63_1@toc@l
-; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
-; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
-; CHECK-LE-NEXT:    xxswapd v3, vs0
-; CHECK-LE-NEXT:    vsld v2, v2, v3
-; CHECK-LE-NEXT:    vsrad v2, v2, v3
-; CHECK-LE-NEXT:    xvcvsxddp v2, v2
+; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3 # Vec Defs: VSL0(VSR0)
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
+; CHECK-LE-NEXT:    xxswapd v3, vs0 # Vec Defs: V3(VSR35) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; CHECK-LE-NEXT:    vsld v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-LE-NEXT:    vsrad v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-LE-NEXT:    xvcvsxddp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %w = sitofp <2 x i16> %a to <2 x double>
   ret <2 x double> %w
 
 
 }
 
 ; This gets scalarized so the code isn't great
 define <2 x double> @test70(<2 x i8> %a) {
 ; CHECK-LABEL: test70:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
 ; CHECK-NEXT:    addi r3, r3, .LCPI64_0@toc@l
-; CHECK-NEXT:    lxvw4x v3, 0, r3
+; CHECK-NEXT:    lxvw4x v3, 0, r3 # Vec Defs: V3(VSR35)
 ; CHECK-NEXT:    addi r3, r1, -32
-; CHECK-NEXT:    vperm v2, v2, v2, v3
-; CHECK-NEXT:    stxvd2x v2, 0, r3
+; CHECK-NEXT:    vperm v2, v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
+; CHECK-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    ld r3, -24(r1)
 ; CHECK-NEXT:    extsb r3, r3
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    ld r3, -32(r1)
 ; CHECK-NEXT:    extsb r3, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
-; CHECK-NEXT:    lxvd2x v2, 0, r3
-; CHECK-NEXT:    xvcvsxddp v2, v2
+; CHECK-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-NEXT:    xvcvsxddp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test70:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
 ; CHECK-REG-NEXT:    addi r3, r3, .LCPI64_0@toc@l
-; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
+; CHECK-REG-NEXT:    lxvw4x v3, 0, r3 # Vec Defs: V3(VSR35)
 ; CHECK-REG-NEXT:    addi r3, r1, -32
-; CHECK-REG-NEXT:    vperm v2, v2, v2, v3
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
+; CHECK-REG-NEXT:    vperm v2, v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r3 # Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    ld r3, -24(r1)
 ; CHECK-REG-NEXT:    extsb r3, r3
 ; CHECK-REG-NEXT:    std r3, -8(r1)
 ; CHECK-REG-NEXT:    ld r3, -32(r1)
 ; CHECK-REG-NEXT:    extsb r3, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
-; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
-; CHECK-REG-NEXT:    xvcvsxddp v2, v2
+; CHECK-REG-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-REG-NEXT:    xvcvsxddp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test70:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
 ; CHECK-FISL-NEXT:    addi r3, r3, .LCPI64_0@toc@l
-; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3
-; CHECK-FISL-NEXT:    vperm v2, v2, v2, v3
-; CHECK-FISL-NEXT:    xxlor vs0, v2, v2
+; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3 # Vec Defs: V3(VSR35)
+; CHECK-FISL-NEXT:    vperm v2, v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
+; CHECK-FISL-NEXT:    xxlor vs0, v2, v2 # Vec Defs: VSL0(VSR0) Vec Uses: V2(VSR34)V2(VSR34)
 ; CHECK-FISL-NEXT:    addi r3, r1, -32
-; CHECK-FISL-NEXT:    stxvd2x vs0, 0, r3
+; CHECK-FISL-NEXT:    stxvd2x vs0, 0, r3 # Vec Uses: VSL0(VSR0)
 ; CHECK-FISL-NEXT:    ld r3, -24(r1)
 ; CHECK-FISL-NEXT:    extsb r3, r3
 ; CHECK-FISL-NEXT:    std r3, -8(r1)
 ; CHECK-FISL-NEXT:    ld r3, -32(r1)
 ; CHECK-FISL-NEXT:    extsb r3, r3
 ; CHECK-FISL-NEXT:    std r3, -16(r1)
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
-; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
-; CHECK-FISL-NEXT:    xvcvsxddp v2, v2
+; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3 # Vec Defs: V2(VSR34)
+; CHECK-FISL-NEXT:    xvcvsxddp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test70:
 ; CHECK-LE:       # %bb.0:
 ; CHECK-LE-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
 ; CHECK-LE-NEXT:    addi r3, r3, .LCPI64_0@toc@l
-; CHECK-LE-NEXT:    lvx v3, 0, r3
+; CHECK-LE-NEXT:    lvx v3, 0, r3 # Vec Defs: V3(VSR35)
 ; CHECK-LE-NEXT:    addis r3, r2, .LCPI64_1@toc@ha
 ; CHECK-LE-NEXT:    addi r3, r3, .LCPI64_1@toc@l
-; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
-; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
-; CHECK-LE-NEXT:    xxswapd v3, vs0
-; CHECK-LE-NEXT:    vsld v2, v2, v3
-; CHECK-LE-NEXT:    vsrad v2, v2, v3
-; CHECK-LE-NEXT:    xvcvsxddp v2, v2
+; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3 # Vec Defs: VSL0(VSR0)
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V2(VSR34)V3(VSR35)
+; CHECK-LE-NEXT:    xxswapd v3, vs0 # Vec Defs: V3(VSR35) Vec Uses: VSL0(VSR0)VSL0(VSR0)
+; CHECK-LE-NEXT:    vsld v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-LE-NEXT:    vsrad v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
+; CHECK-LE-NEXT:    xvcvsxddp v2, v2 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)
 ; CHECK-LE-NEXT:    blr
   %w = sitofp <2 x i8> %a to <2 x double>
   ret <2 x double> %w
 
 
 }
 
 ; This gets scalarized so the code isn't great
 define <2 x i32> @test80(i32 %v) {
 ; CHECK-LABEL: test80:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r4, r1, -16
 ; CHECK-NEXT:    stw r3, -16(r1)
 ; CHECK-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
-; CHECK-NEXT:    lxvw4x vs0, 0, r4
+; CHECK-NEXT:    lxvw4x vs0, 0, r4 # Vec Defs: VSL0(VSR0)
 ; CHECK-NEXT:    addi r3, r3, .LCPI65_0@toc@l
-; CHECK-NEXT:    lxvw4x v3, 0, r3
-; CHECK-NEXT:    xxspltw v2, vs0, 0
-; CHECK-NEXT:    vadduwm v2, v2, v3
+; CHECK-NEXT:    lxvw4x v3, 0, r3 # Vec Defs: V3(VSR35)
+; CHECK-NEXT:    xxspltw v2, vs0, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
+; CHECK-NEXT:    vadduwm v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test80:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r4, r1, -16
 ; CHECK-REG-NEXT:    stw r3, -16(r1)
 ; CHECK-REG-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
-; CHECK-REG-NEXT:    lxvw4x vs0, 0, r4
+; CHECK-REG-NEXT:    lxvw4x vs0, 0, r4 # Vec Defs: VSL0(VSR0)
 ; CHECK-REG-NEXT:    addi r3, r3, .LCPI65_0@toc@l
-; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
-; CHECK-REG-NEXT:    xxspltw v2, vs0, 0
-; CHECK-REG-NEXT:    vadduwm v2, v2, v3
+; CHECK-REG-NEXT:    lxvw4x v3, 0, r3 # Vec Defs: V3(VSR35)
+; CHECK-REG-NEXT:    xxspltw v2, vs0, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
+; CHECK-REG-NEXT:    vadduwm v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test80:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    # kill: def $r3 killed $r3 killed $x3
 ; CHECK-FISL-NEXT:    stw r3, -16(r1)
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
-; CHECK-FISL-NEXT:    lxvw4x vs0, 0, r3
-; CHECK-FISL-NEXT:    xxspltw v2, vs0, 0
+; CHECK-FISL-NEXT:    lxvw4x vs0, 0, r3 # Vec Defs: VSL0(VSR0)
+; CHECK-FISL-NEXT:    xxspltw v2, vs0, 0 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
 ; CHECK-FISL-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
 ; CHECK-FISL-NEXT:    addi r3, r3, .LCPI65_0@toc@l
-; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3
-; CHECK-FISL-NEXT:    vadduwm v2, v2, v3
+; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3 # Vec Defs: V3(VSR35)
+; CHECK-FISL-NEXT:    vadduwm v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test80:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    mtfprwz f0, r3
+; CHECK-LE-NEXT:    mtfprwz f0, r3 # Vec Defs: F0(VSR0)
 ; CHECK-LE-NEXT:    addis r4, r2, .LCPI65_0@toc@ha
 ; CHECK-LE-NEXT:    addi r3, r4, .LCPI65_0@toc@l
-; CHECK-LE-NEXT:    xxspltw v2, vs0, 1
-; CHECK-LE-NEXT:    lvx v3, 0, r3
-; CHECK-LE-NEXT:    vadduwm v2, v2, v3
+; CHECK-LE-NEXT:    xxspltw v2, vs0, 1 # Vec Defs: V2(VSR34) Vec Uses: VSL0(VSR0)
+; CHECK-LE-NEXT:    lvx v3, 0, r3 # Vec Defs: V3(VSR35)
+; CHECK-LE-NEXT:    vadduwm v2, v2, v3 # Vec Defs: V2(VSR34) Vec Uses: V2(VSR34)V3(VSR35)
 ; CHECK-LE-NEXT:    blr
   %b1 = insertelement <2 x i32> undef, i32 %v, i32 0
   %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer
   %i = add <2 x i32> %b2, <i32 2, i32 3>
   ret <2 x i32> %i
 
 
 
; CHECK-LE-NEXT:    blr
   ret <2 x double> %w
 
 
 }
 
 define double @test82(double %a, double %b, double %c, double %d) {
 ; CHECK-LABEL: test82:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xscmpudp cr0, f3, f4
+; CHECK-NEXT:    xscmpudp cr0, f3, f4 # Vec Uses: F3(VSR3)F4(VSR4)
 ; CHECK-NEXT:    beqlr cr0
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    fmr f1, f2
+; CHECK-NEXT:    fmr f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test82:
 ; CHECK-REG:       # %bb.0: # %entry
-; CHECK-REG-NEXT:    xscmpudp cr0, f3, f4
+; CHECK-REG-NEXT:    xscmpudp cr0, f3, f4 # Vec Uses: F3(VSR3)F4(VSR4)
 ; CHECK-REG-NEXT:    beqlr cr0
 ; CHECK-REG-NEXT:  # %bb.1: # %entry
-; CHECK-REG-NEXT:    fmr f1, f2
+; CHECK-REG-NEXT:    fmr f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test82:
 ; CHECK-FISL:       # %bb.0: # %entry
 ; CHECK-FISL-NEXT:    stfd f2, -16(r1) # 8-byte Folded Spill
-; CHECK-FISL-NEXT:    fmr f2, f1
-; CHECK-FISL-NEXT:    xscmpudp cr0, f3, f4
+; CHECK-FISL-NEXT:    # Vec Uses: F2(VSR2)
+; CHECK-FISL-NEXT:    fmr f2, f1 # Vec Defs: F2(VSR2) Vec Uses: F1(VSR1)
+; CHECK-FISL-NEXT:    xscmpudp cr0, f3, f4 # Vec Uses: F3(VSR3)F4(VSR4)
 ; CHECK-FISL-NEXT:    stfd f2, -8(r1) # 8-byte Folded Spill
+; CHECK-FISL-NEXT:    # Vec Uses: F2(VSR2)
 ; CHECK-FISL-NEXT:    beq cr0, .LBB67_2
 ; CHECK-FISL-NEXT:  # %bb.1: # %entry
 ; CHECK-FISL-NEXT:    lfd f0, -16(r1) # 8-byte Folded Reload
+; CHECK-FISL-NEXT:    # Vec Defs: F0(VSR0)
 ; CHECK-FISL-NEXT:    stfd f0, -8(r1) # 8-byte Folded Spill
+; CHECK-FISL-NEXT:    # Vec Uses: F0(VSR0)
 ; CHECK-FISL-NEXT:  .LBB67_2: # %entry
 ; CHECK-FISL-NEXT:    lfd f1, -8(r1) # 8-byte Folded Reload
+; CHECK-FISL-NEXT:    # Vec Defs: F1(VSR1)
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test82:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    xscmpudp cr0, f3, f4
+; CHECK-LE-NEXT:    xscmpudp cr0, f3, f4 # Vec Uses: F3(VSR3)F4(VSR4)
 ; CHECK-LE-NEXT:    beqlr cr0
 ; CHECK-LE-NEXT:  # %bb.1: # %entry
-; CHECK-LE-NEXT:    fmr f1, f2
+; CHECK-LE-NEXT:    fmr f1, f2 # Vec Defs: F1(VSR1) Vec Uses: F2(VSR2)
 ; CHECK-LE-NEXT:    blr
 entry:
   %m = fcmp oeq double %c, %d
   %v = select i1 %m, double %a, double %b
   ret double %v
 
 
 
 }