This is an archive of the discontinued LLVM Phabricator instance.

Differential D11639

[ARM. AArch64]Handle generic cpus in the gcc-compatible manner (llvm part)
AbandonedPublic

Authored by rengolin on Jul 30 2015, 2:58 AM.

Details

Reviewers
vsukharev
t.p.northover
Summary

The patch mimics GCC's behaviour for the following:

  • default -march is "armv4t"
  • if an architecture is targeted, just a "generic" cpu is used with minimal sane set of features, instead of some specific real default cpu name.
  • LLVM's specific exceptions:
    • for specific vendors, OSes, environments, or arches - add the minimally required features, or even pick a real cpu.
  • build attributes for generic cpus:
    • asm: ".arch armv<ArchName>"
    • ELF: "Tag_CPU_name = "<ArchName>""
  • default "-mfloat-abi" is "soft".
  • if case of "-mfloat-abi=hard", and no "-mfpu" provided -> default "vfp2" is used.

Some revealed LLVM bugs had to be fixed along the patch preparation, because of test fails.

  • Crypto feature did not include Neon feature. This was not visible, because Neon was always on.
  • Despite requirements for minimal cpus were provided in Triple::getARMCPUForArch(), they did not always work.

Because of the latter fix and default arch upgrade, tests for codegen were also adjusted.

Diff Detail

Repository
rL LLVM

Event Timeline

vsukharev updated this revision to Diff 31009.Jul 30 2015, 2:58 AM
vsukharev retitled this revision from to Handle generic cpus in the gcc-compatible manner (llvm part).
vsukharev updated this object.
vsukharev added reviewers: t.p.northover, rengolin.
vsukharev set the repository for this revision to rL LLVM.
vsukharev added subscribers: labrinea, richard.barton.arm.
Herald added subscribers: srhines, danalbert, qcolombet and 4 others. · View Herald TranscriptJul 30 2015, 2:58 AM
vsukharev retitled this revision from Handle generic cpus in the gcc-compatible manner (llvm part) to [ARM. AArch64]Handle generic cpus in the gcc-compatible manner (llvm part).Jul 30 2015, 2:59 AM
vsukharev added a child revision: D11640: [ARM] Proper handling generic cpus.
jfb added inline comments.Jul 30 2015, 8:07 AM
lib/Support/Triple.cpp
1330

NaCl mandates that the CPU be at least v7 with VFPv3 and NEON, so I think we want to have "cortex-a8" as it was before. NaCl does support integer division when available, so we could handle that too, but it doesn't currently handle features that are new in v8.

vsukharev added a comment.EditedJul 30 2015, 11:27 AM

Hi, it's great to have an NaCl expert around.
About architectures, lower than v7:
If armv6 or below is explicitly asked, should we emit a fault like "NaCl requires at least v7 architecture"?

Hmm, let's check, which CPU is in current output of the following line?

clang  -target armv6-unknown-nacl-gnueabihf -### /work/llvm/tools/clang/test/Driver/arm-alignment.c

I got "-target-cpu" "arm1136jf-s"...

  1. When I left only "cortex-a8", one test failed: tools/clang/test/Driver/arm-alignment.c, line 59 - it assumes CPU might be lower than v7, as you said...
// RUN: %clang -target armv6-unknown-nacl-gnueabihf -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ALIGNED-ARM < %t %s
// CHECK-ALIGNED-ARM: "-target-feature" "+strict-align"
  1. Whilst tools/clang/lib/Driver/Tools.cpp, line 834 explicitly prohibits such an emission for cortex-a8, that is of v7 architecture.
else if (Triple.isOSLinux() || Triple.isOSNaCl()) {
      if (VersionNum < 7)
        Features.push_back("+strict-align");

This snippet also implies NaCl supports CPUs lower than v7

If "armv6-unknown-nacl-gnueabihf " must have not "arm1136jf-s", but "cortex-a8" (that is quite weird for me, because it's not v6),
so either one of the following needs correction

  • lib/Driver/Tools.cpp, line 834
  • test/Driver/arm-alignment.c, line 59

What's your vision?

vsukharev added a comment.Jul 30 2015, 11:55 AM

About v8 architecture:
thank you for the information on NaCl, I was in doubt, which one of Cortex-A53 or Cortex-A8 should I use. Based on absence of relevant tests, I decided that NaCl doesn't support v8, and any decision would be right.
In next patch revision I could leave Cortex-A8 for v8 as well, with an appropriate comment.

jfb added a comment.Jul 30 2015, 1:07 PM
In D11639#215434, @vsukharev wrote:

Hi, it's great to have an NaCl expert around.
About architectures, lower than v7:
If armv6 or below is explicitly asked, should we emit a fault like "NaCl requires at least v7 architecture"?

Hmm, let's check, which CPU is in current output of the following line?

clang  -target armv6-unknown-nacl-gnueabihf -### /work/llvm/tools/clang/test/Driver/arm-alignment.c

I got "-target-cpu" "arm1136jf-s"...

  1. When I left only "cortex-a8", one test failed: tools/clang/test/Driver/arm-alignment.c, line 59 - it assumes CPU might be lower than v7, as you said...
// RUN: %clang -target armv6-unknown-nacl-gnueabihf -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ALIGNED-ARM < %t %s
// CHECK-ALIGNED-ARM: "-target-feature" "+strict-align"
  1. Whilst tools/clang/lib/Driver/Tools.cpp, line 834 explicitly prohibits such an emission for cortex-a8, that is of v7 architecture.
else if (Triple.isOSLinux() || Triple.isOSNaCl()) {
      if (VersionNum < 7)
        Features.push_back("+strict-align");

This snippet also implies NaCl supports CPUs lower than v7

If "armv6-unknown-nacl-gnueabihf " must have not "arm1136jf-s", but "cortex-a8" (that is quite weird for me, because it's not v6),
so either one of the following needs correction

  • lib/Driver/Tools.cpp, line 834
  • test/Driver/arm-alignment.c, line 59

What's your vision?

Agreed with what you suggest: if a developer asks for v6 on NaCl then let's honor this (since it's mostly a subset of what v7 has), instead of bailing out. So I'm now OK with your change :-)

Just to be sure: if the user doesn't specify v7 or v6 (e.g. arm-unknown-nacl), what do they get? v7 and cortex-a8 should be what they get.

Also note: NaCl doesn't support Thumb or Thumb2.

In D11639#215477, @vsukharev wrote:

About v8 architecture:
thank you for the information on NaCl, I was in doubt, which one of Cortex-A53 or Cortex-A8 should I use. Based on absence of relevant tests, I decided that NaCl doesn't support v8, and any decision would be right.
In next patch revision I could leave Cortex-A8 for v8 as well, with an appropriate comment.

I think it may be better to error out if v8 is specified with NaCl.

jfb added a subscriber: dschuff.Jul 30 2015, 1:07 PM
rengolin edited edge metadata.Jul 30 2015, 1:38 PM

I haven't looked at the code entirely, but the way we're dealing with default features is by getting the CPU name and then its features.

To get a base default, just make the default arch ARMv4T and you got it. I can't see why you would want to add yet another way to find the default features to the existing one.

Also, the CPU name in the target-features is an internal thing to Clang/LLVM, and I don't think we should make it identical to GCC. There is no way that any GNU tool will understand those options, so it actually doesn't matter.

Having a named CPU, not just the correct set of target-features, is a good way to test, and also helps on constructing build attributes, and interacting with GNU tools at a later stage without relying on the fact that they understand the "generic" with the same features as we do.

At least we know that the specific CPU features are close enough to work well for all these years. I wouldn't bet on the "generic" model to be accurate, since we never used that. Ie. I wouldnt' just change it in production without a large system validation to make sure it does work well with all LLVM and GNU tools.

rengolin added a comment.Jul 30 2015, 1:41 PM

Just to be clear, the target parser code desperately needs to be table-genned. Adding more and more complex logic to it will make it harder, and eventually impossible to generate code at table-gen time.

rengolin requested changes to this revision.Jul 31 2015, 4:31 AM
rengolin edited edge metadata.

Hi Vladmir,

There are too many issues with this patch to consider merging it at all.

This is a big decision that affects all users, OS distributions, IDEs, integrated products, etc. You cannot send a merge request of that magnitude without getting consensus from the community first. I'm against such a change, so if you really want to see this through, you'll have to gain enough momentum in the rest of the community first. That includes Windows, Darwin, FreeBSD and Linux folks, as well as at least Apple and Google, which ship products with LLVM-ARM, and other tools, like LLD, LLDB, etc, which will invariably be affected, at least on their command-line interface.

This request also has too many changes in one go, and most of them reach further than you can see. It'll be virtually impossible to steer around problems that are found by validation or trial and error outside of the buildbot arena. And that's only after all the buildbots have calmed down, which due to the magnitude of this patch, I believe it'll take a while, and many patches, and mane reverts. We tend to avoid that kind of situation as much as possible, because we rely on the bots to be green, and having them unstable for a week or so means other failures will be harder to pinpoint, bisect, and fix.

As it stands, I'm rejecting this patch wholesale on the grounds of lack of consensus, proper testing and overall design decisions.

cheers,
-renato

lib/Support/TargetParser.cpp
425

This will have consequences in Clang. Have you ran "make check-all" with clang builtin?

lib/Support/Triple.cpp
1330

This is not true just for NaCl, but for almost every architecture. Your change makes no sense in the grand scheme of things.

lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
142

This change makes no sense. If you want to make it proper, you'll have to iterate through the target features, either from the user info (command-line options, not available here yet), or from the table-gen description (via hasFeatureXXX methods).

This change is just making it hard-coded in a different way. Not worth the change.

This revision now requires changes to proceed.Jul 31 2015, 4:31 AM
rengolin commandeered this revision.Jun 27 2016, 6:44 AM
rengolin edited reviewers, added: vsukharev; removed: rengolin.
Herald added a subscriber: rengolin. · View Herald TranscriptJun 27 2016, 6:44 AM
rengolin abandoned this revision.Jun 27 2016, 6:44 AM

Revision Contents

PathSize
include/
llvm/
MC/
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Support/
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lib/
Support/
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Target/
ARM/
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MCTargetDesc/
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test/
CodeGen/
ARM/
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Windows/
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Thumb/
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MC/
ARM/
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Disassembler/
ARM/
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ARM/
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Diff 31009

include/llvm/MC/MCStreamer.h

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Linespublic:
virtual void emitPad(int64_t Offset); virtual void emitPad(int64_t Offset);
virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList, virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
bool isVector); bool isVector);
virtual void emitUnwindRaw(int64_t StackOffset, virtual void emitUnwindRaw(int64_t StackOffset,
const SmallVectorImpl<uint8_t> &Opcodes); const SmallVectorImpl<uint8_t> &Opcodes);
virtual void switchVendor(StringRef Vendor); virtual void switchVendor(StringRef Vendor);
virtual void emitAttribute(unsigned Attribute, unsigned Value); virtual void emitAttribute(unsigned Attribute, unsigned Value);
virtual void emitCPUAttribute(StringRef CPUName, StringRef ArchName);
virtual void emitTextAttribute(unsigned Attribute, StringRef String); virtual void emitTextAttribute(unsigned Attribute, StringRef String);
virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue, virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
StringRef StringValue = ""); StringRef StringValue = "");
virtual void emitFPU(unsigned FPU); virtual void emitFPU(unsigned FPU);
virtual void emitArch(unsigned Arch); virtual void emitArch(unsigned Arch);
virtual void emitArchExtension(unsigned ArchExt); virtual void emitArchExtension(unsigned ArchExt);
virtual void emitObjectArch(unsigned Arch); virtual void emitObjectArch(unsigned Arch);
virtual void finishAttributeSection(); virtual void finishAttributeSection();
▲ Show 20 Lines • Show All 622 Lines • Show Last 20 Lines

include/llvm/Support/TargetParser.h

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines enum FPUKind {
FK_FPV5_SP_D16, FK_FPV5_SP_D16,
FK_FP_ARMV8, FK_FP_ARMV8,
FK_NEON, FK_NEON,
FK_NEON_FP16, FK_NEON_FP16,
FK_NEON_VFPV4, FK_NEON_VFPV4,
FK_NEON_FP_ARMV8, FK_NEON_FP_ARMV8,
FK_CRYPTO_NEON_FP_ARMV8, FK_CRYPTO_NEON_FP_ARMV8,
FK_SOFTVFP, FK_SOFTVFP,
FK_LAST FK_LAST,
FK_DEFAULT = FK_VFPV2, //default gcc's vfp for eabihf and -mfloat-abi=hard
}; };
// FPU Version // FPU Version
enum FPUVersion { enum FPUVersion {
FV_NONE = 0, FV_NONE = 0,
FV_VFPV2, FV_VFPV2,
FV_VFPV3, FV_VFPV3,
FV_VFPV3_FP16, FV_VFPV3_FP16,
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines enum ArchKind {
AK_ARMV5, AK_ARMV5,
AK_ARMV5E, AK_ARMV5E,
AK_ARMV6J, AK_ARMV6J,
AK_ARMV6HL, AK_ARMV6HL,
AK_ARMV7, AK_ARMV7,
AK_ARMV7L, AK_ARMV7L,
AK_ARMV7HL, AK_ARMV7HL,
AK_ARMV7S, AK_ARMV7S,
AK_LAST AK_LAST,
AK_DEFAULT = AK_ARMV4T, // default gcc's subarch
}; };
// Arch extension modifiers for CPUs. // Arch extension modifiers for CPUs.
enum ArchExtKind : unsigned { enum ArchExtKind : unsigned {
AEK_INVALID = 0x0, AEK_INVALID = 0x0,
AEK_NONE = 0x1, AEK_NONE = 0x1,
AEK_CRC = 0x2, AEK_CRC = 0x2,
AEK_CRYPTO = 0x4, AEK_CRYPTO = 0x4,
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines static bool getHWDivFeatures(unsigned HWDivKind,
std::vector<const char*> &Features); std::vector<const char*> &Features);
static const char * getArchName(unsigned ArchKind); static const char * getArchName(unsigned ArchKind);
static unsigned getArchAttr(unsigned ArchKind); static unsigned getArchAttr(unsigned ArchKind);
static const char * getCPUAttr(unsigned ArchKind); static const char * getCPUAttr(unsigned ArchKind);
static const char * getSubArch(unsigned ArchKind); static const char * getSubArch(unsigned ArchKind);
static const char * getArchExtName(unsigned ArchExtKind); static const char * getArchExtName(unsigned ArchExtKind);
static const char * getHWDivName(unsigned HWDivKind); static const char * getHWDivName(unsigned HWDivKind);
static const char * getDefaultCPU(StringRef Arch); static const char * getDefaultCPU(StringRef Arch);
static const char * getGenericCPU(StringRef Arch);
// Parser // Parser
static unsigned parseHWDiv(StringRef HWDiv); static unsigned parseHWDiv(StringRef HWDiv);
static unsigned parseFPU(StringRef FPU); static unsigned parseFPU(StringRef FPU);
static unsigned parseArch(StringRef Arch); static unsigned parseArch(StringRef Arch);
static unsigned parseArchExt(StringRef ArchExt); static unsigned parseArchExt(StringRef ArchExt);
static unsigned parseCPUArch(StringRef CPU); static unsigned parseCPUArch(StringRef CPU, StringRef Arch);
static unsigned parseArchISA(StringRef Arch); static unsigned parseArchISA(StringRef Arch);
static unsigned parseArchEndian(StringRef Arch); static unsigned parseArchEndian(StringRef Arch);
static unsigned parseArchProfile(StringRef Arch); static unsigned parseArchProfile(StringRef Arch);
static unsigned parseArchVersion(StringRef Arch); static unsigned parseArchVersion(StringRef Arch);
}; };
} // namespace llvm } // namespace llvm
#endif #endif

lib/Support/TargetParser.cpp

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
// When this becomes table-generated, we'd probably need two tables. // When this becomes table-generated, we'd probably need two tables.
// FIXME: TableGen this. // FIXME: TableGen this.
struct { struct {
const char *Name; const char *Name;
ARM::ArchKind ArchID; ARM::ArchKind ArchID;
ARM::FPUKind DefaultFPU; ARM::FPUKind DefaultFPU;
bool Default; // is $Name the default CPU for $ArchID ? bool Default; // is $Name the default CPU for $ArchID ?
} CPUNames[] = { } CPUNames[] = {
{ "arm2", ARM::AK_ARMV2, ARM::FK_NONE, true }, { "arm2", ARM::AK_ARMV2, ARM::FK_NONE, false },
{ "arm3", ARM::AK_ARMV2A, ARM::FK_NONE, true }, { "arm3", ARM::AK_ARMV2A, ARM::FK_NONE, false },
{ "arm6", ARM::AK_ARMV3, ARM::FK_NONE, true }, { "arm6", ARM::AK_ARMV3, ARM::FK_NONE, false },
{ "arm7m", ARM::AK_ARMV3M, ARM::FK_NONE, true }, { "arm7m", ARM::AK_ARMV3M, ARM::FK_NONE, false },
{ "arm8", ARM::AK_ARMV4, ARM::FK_NONE, false }, { "arm8", ARM::AK_ARMV4, ARM::FK_NONE, false },
{ "arm810", ARM::AK_ARMV4, ARM::FK_NONE, false }, { "arm810", ARM::AK_ARMV4, ARM::FK_NONE, false },
{ "strongarm", ARM::AK_ARMV4, ARM::FK_NONE, true }, { "strongarm", ARM::AK_ARMV4, ARM::FK_NONE, false },
{ "strongarm110", ARM::AK_ARMV4, ARM::FK_NONE, false }, { "strongarm110", ARM::AK_ARMV4, ARM::FK_NONE, false },
{ "strongarm1100", ARM::AK_ARMV4, ARM::FK_NONE, false }, { "strongarm1100", ARM::AK_ARMV4, ARM::FK_NONE, false },
{ "strongarm1110", ARM::AK_ARMV4, ARM::FK_NONE, false }, { "strongarm1110", ARM::AK_ARMV4, ARM::FK_NONE, false },
{ "arm7tdmi", ARM::AK_ARMV4T, ARM::FK_NONE, true }, { "arm7tdmi", ARM::AK_ARMV4T, ARM::FK_NONE, false },
{ "arm7tdmi-s", ARM::AK_ARMV4T, ARM::FK_NONE, false }, { "arm7tdmi-s", ARM::AK_ARMV4T, ARM::FK_NONE, false },
{ "arm710t", ARM::AK_ARMV4T, ARM::FK_NONE, false }, { "arm710t", ARM::AK_ARMV4T, ARM::FK_NONE, false },
{ "arm720t", ARM::AK_ARMV4T, ARM::FK_NONE, false }, { "arm720t", ARM::AK_ARMV4T, ARM::FK_NONE, false },
{ "arm9", ARM::AK_ARMV4T, ARM::FK_NONE, false }, { "arm9", ARM::AK_ARMV4T, ARM::FK_NONE, false },
{ "arm9tdmi", ARM::AK_ARMV4T, ARM::FK_NONE, false }, { "arm9tdmi", ARM::AK_ARMV4T, ARM::FK_NONE, false },
{ "arm920", ARM::AK_ARMV4T, ARM::FK_NONE, false }, { "arm920", ARM::AK_ARMV4T, ARM::FK_NONE, false },
{ "arm920t", ARM::AK_ARMV4T, ARM::FK_NONE, false }, { "arm920t", ARM::AK_ARMV4T, ARM::FK_NONE, false },
{ "arm922t", ARM::AK_ARMV4T, ARM::FK_NONE, false }, { "arm922t", ARM::AK_ARMV4T, ARM::FK_NONE, false },
{ "arm9312", ARM::AK_ARMV4T, ARM::FK_NONE, false }, { "arm9312", ARM::AK_ARMV4T, ARM::FK_NONE, false },
{ "arm940t", ARM::AK_ARMV4T, ARM::FK_NONE, false }, { "arm940t", ARM::AK_ARMV4T, ARM::FK_NONE, false },
{ "ep9312", ARM::AK_ARMV4T, ARM::FK_NONE, false }, { "ep9312", ARM::AK_ARMV4T, ARM::FK_NONE, false },
{ "arm10tdmi", ARM::AK_ARMV5T, ARM::FK_NONE, true }, { "arm10tdmi", ARM::AK_ARMV5T, ARM::FK_NONE, false },
{ "arm1020t", ARM::AK_ARMV5T, ARM::FK_NONE, false }, { "arm1020t", ARM::AK_ARMV5T, ARM::FK_NONE, false },
{ "arm9e", ARM::AK_ARMV5TE, ARM::FK_NONE, false }, { "arm9e", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
{ "arm946e-s", ARM::AK_ARMV5TE, ARM::FK_NONE, false }, { "arm946e-s", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
{ "arm966e-s", ARM::AK_ARMV5TE, ARM::FK_NONE, false }, { "arm966e-s", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
{ "arm968e-s", ARM::AK_ARMV5TE, ARM::FK_NONE, false }, { "arm968e-s", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
{ "arm10e", ARM::AK_ARMV5TE, ARM::FK_NONE, false }, { "arm10e", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
{ "arm1020e", ARM::AK_ARMV5TE, ARM::FK_NONE, false }, { "arm1020e", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
{ "arm1022e", ARM::AK_ARMV5TE, ARM::FK_NONE, true }, { "arm1022e", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
{ "iwmmxt", ARM::AK_ARMV5TE, ARM::FK_NONE, false }, { "iwmmxt", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
{ "xscale", ARM::AK_ARMV5TE, ARM::FK_NONE, false }, { "xscale", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
{ "arm926ej-s", ARM::AK_ARMV5TEJ, ARM::FK_NONE, true }, { "arm926ej-s", ARM::AK_ARMV5TEJ, ARM::FK_NONE, false },
{ "arm1136jf-s", ARM::AK_ARMV6, ARM::FK_VFPV2, true }, { "arm1136jf-s", ARM::AK_ARMV6, ARM::FK_VFPV2, false },
{ "arm1176j-s", ARM::AK_ARMV6K, ARM::FK_NONE, false }, { "arm1176j-s", ARM::AK_ARMV6K, ARM::FK_NONE, false },
{ "arm1176jz-s", ARM::AK_ARMV6K, ARM::FK_NONE, false }, { "arm1176jz-s", ARM::AK_ARMV6K, ARM::FK_NONE, false },
{ "mpcore", ARM::AK_ARMV6K, ARM::FK_VFPV2, false }, { "mpcore", ARM::AK_ARMV6K, ARM::FK_VFPV2, false },
{ "mpcorenovfp", ARM::AK_ARMV6K, ARM::FK_NONE, false }, { "mpcorenovfp", ARM::AK_ARMV6K, ARM::FK_NONE, false },
{ "arm1176jzf-s", ARM::AK_ARMV6K, ARM::FK_VFPV2, true }, { "arm1176jzf-s", ARM::AK_ARMV6K, ARM::FK_VFPV2, false },
{ "arm1176jzf-s", ARM::AK_ARMV6Z, ARM::FK_VFPV2, true }, { "arm1176jzf-s", ARM::AK_ARMV6Z, ARM::FK_VFPV2, false },
{ "arm1176jzf-s", ARM::AK_ARMV6ZK, ARM::FK_VFPV2, true }, { "arm1176jzf-s", ARM::AK_ARMV6ZK, ARM::FK_VFPV2, false },
{ "arm1156t2-s", ARM::AK_ARMV6T2, ARM::FK_NONE, true }, { "arm1156t2-s", ARM::AK_ARMV6T2, ARM::FK_NONE, false },
{ "arm1156t2f-s", ARM::AK_ARMV6T2, ARM::FK_VFPV2, false }, { "arm1156t2f-s", ARM::AK_ARMV6T2, ARM::FK_VFPV2, false },
{ "cortex-m0", ARM::AK_ARMV6M, ARM::FK_NONE, true }, { "cortex-m0", ARM::AK_ARMV6M, ARM::FK_NONE, false },
{ "cortex-m0plus", ARM::AK_ARMV6M, ARM::FK_NONE, false }, { "cortex-m0plus", ARM::AK_ARMV6M, ARM::FK_NONE, false },
{ "cortex-m1", ARM::AK_ARMV6M, ARM::FK_NONE, false }, { "cortex-m1", ARM::AK_ARMV6M, ARM::FK_NONE, false },
{ "sc000", ARM::AK_ARMV6M, ARM::FK_NONE, false }, { "sc000", ARM::AK_ARMV6M, ARM::FK_NONE, false },
{ "cortex-a5", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false }, { "cortex-a5", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },
{ "cortex-a7", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false }, { "cortex-a7", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },
{ "cortex-a8", ARM::AK_ARMV7A, ARM::FK_NEON, true }, { "cortex-a8", ARM::AK_ARMV7A, ARM::FK_NEON, false },
{ "cortex-a9", ARM::AK_ARMV7A, ARM::FK_NEON_FP16, false }, { "cortex-a9", ARM::AK_ARMV7A, ARM::FK_NEON_FP16, false },
{ "cortex-a12", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false }, { "cortex-a12", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },
{ "cortex-a15", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false }, { "cortex-a15", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },
{ "cortex-a17", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false }, { "cortex-a17", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },
{ "krait", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false }, { "krait", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },
{ "cortex-r4", ARM::AK_ARMV7R, ARM::FK_NONE, true }, { "cortex-r4", ARM::AK_ARMV7R, ARM::FK_NONE, false },
{ "cortex-r4f", ARM::AK_ARMV7R, ARM::FK_VFPV3_D16, false }, { "cortex-r4f", ARM::AK_ARMV7R, ARM::FK_VFPV3_D16, false },
{ "cortex-r5", ARM::AK_ARMV7R, ARM::FK_VFPV3_D16, false }, { "cortex-r5", ARM::AK_ARMV7R, ARM::FK_VFPV3_D16, false },
{ "cortex-r7", ARM::AK_ARMV7R, ARM::FK_VFPV3_D16_FP16, false }, { "cortex-r7", ARM::AK_ARMV7R, ARM::FK_VFPV3_D16_FP16, false },
{ "sc300", ARM::AK_ARMV7M, ARM::FK_NONE, false }, { "sc300", ARM::AK_ARMV7M, ARM::FK_NONE, false },
{ "cortex-m3", ARM::AK_ARMV7M, ARM::FK_NONE, true }, { "cortex-m3", ARM::AK_ARMV7M, ARM::FK_NONE, false },
{ "cortex-m4", ARM::AK_ARMV7EM, ARM::FK_FPV4_SP_D16, true }, { "cortex-m4", ARM::AK_ARMV7EM, ARM::FK_FPV4_SP_D16, false },
{ "cortex-m7", ARM::AK_ARMV7EM, ARM::FK_FPV5_D16, false }, { "cortex-m7", ARM::AK_ARMV7EM, ARM::FK_FPV5_D16, false },
{ "cortex-a53", ARM::AK_ARMV8A, ARM::FK_CRYPTO_NEON_FP_ARMV8, true }, { "cortex-a53", ARM::AK_ARMV8A, ARM::FK_CRYPTO_NEON_FP_ARMV8, false },
{ "cortex-a57", ARM::AK_ARMV8A, ARM::FK_CRYPTO_NEON_FP_ARMV8, false }, { "cortex-a57", ARM::AK_ARMV8A, ARM::FK_CRYPTO_NEON_FP_ARMV8, false },
{ "cortex-a72", ARM::AK_ARMV8A, ARM::FK_CRYPTO_NEON_FP_ARMV8, false }, { "cortex-a72", ARM::AK_ARMV8A, ARM::FK_CRYPTO_NEON_FP_ARMV8, false },
{ "cyclone", ARM::AK_ARMV8A, ARM::FK_CRYPTO_NEON_FP_ARMV8, false }, { "cyclone", ARM::AK_ARMV8A, ARM::FK_CRYPTO_NEON_FP_ARMV8, false },
{ "generic", ARM::AK_ARMV8_1A, ARM::FK_NEON_FP_ARMV8, true },
// Non-standard Arch names. // Non-standard Arch names.
{ "iwmmxt", ARM::AK_IWMMXT, ARM::FK_NONE, true }, { "iwmmxt", ARM::AK_IWMMXT, ARM::FK_NONE, false },
{ "xscale", ARM::AK_XSCALE, ARM::FK_NONE, true }, { "xscale", ARM::AK_XSCALE, ARM::FK_NONE, false },
{ "arm10tdmi", ARM::AK_ARMV5, ARM::FK_NONE, true }, { "arm10tdmi", ARM::AK_ARMV5, ARM::FK_NONE, false },
{ "arm1022e", ARM::AK_ARMV5E, ARM::FK_NONE, true }, { "arm1022e", ARM::AK_ARMV5E, ARM::FK_NONE, false },
{ "arm1136j-s", ARM::AK_ARMV6J, ARM::FK_NONE, true }, { "arm1136j-s", ARM::AK_ARMV6J, ARM::FK_NONE, false },
{ "arm1136jz-s", ARM::AK_ARMV6J, ARM::FK_NONE, false }, { "arm1136jz-s", ARM::AK_ARMV6J, ARM::FK_NONE, false },
{ "cortex-m0", ARM::AK_ARMV6SM, ARM::FK_NONE, true }, { "cortex-m0", ARM::AK_ARMV6SM, ARM::FK_NONE, false },
{ "arm1176jzf-s", ARM::AK_ARMV6HL, ARM::FK_VFPV2, true }, { "arm1176jzf-s", ARM::AK_ARMV6HL, ARM::FK_VFPV2, false },
{ "cortex-a8", ARM::AK_ARMV7, ARM::FK_NEON, true }, { "cortex-a8", ARM::AK_ARMV7, ARM::FK_NEON, false },
{ "cortex-a8", ARM::AK_ARMV7L, ARM::FK_NEON, true }, { "cortex-a8", ARM::AK_ARMV7L, ARM::FK_NEON, false },
{ "cortex-a8", ARM::AK_ARMV7HL, ARM::FK_NEON, true }, { "cortex-a8", ARM::AK_ARMV7HL, ARM::FK_NEON, false },
{ "cortex-m4", ARM::AK_ARMV7EM, ARM::FK_NONE, true },
{ "swift", ARM::AK_ARMV7S, ARM::FK_NEON_VFPV4, true }, { "swift", ARM::AK_ARMV7S, ARM::FK_NEON_VFPV4, true },
// Invalid CPU // Invalid CPU
{ "invalid", ARM::AK_INVALID, ARM::FK_INVALID, true } { "invalid", ARM::AK_INVALID, ARM::FK_INVALID, true }
}; };
} // namespace } // namespace
// ======================================================= // // ======================================================= //
// Information by ID // Information by ID
▲ Show 20 Lines • Show All 169 Lines • ▼ Show 20 Lines if (HWDivKind == D.ID)
return D.Name; return D.Name;
} }
return nullptr; return nullptr;
} }
const char *ARMTargetParser::getDefaultCPU(StringRef Arch) { const char *ARMTargetParser::getDefaultCPU(StringRef Arch) {
unsigned AK = parseArch(Arch); unsigned AK = parseArch(Arch);
if (AK == ARM::AK_INVALID) if (AK == ARM::AK_INVALID)
return nullptr; return getGenericCPU(Arch);
rengolinAuthorUnsubmitted
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This will have consequences in Clang. Have you ran "make check-all" with clang builtin?

rengolin: This will have consequences in Clang. Have you ran "make check-all" with clang builtin?
// Look for multiple AKs to find the default for pair AK+Name. // Look for multiple AKs to find the default for pair AK+Name.
for (const auto CPU : CPUNames) { for (const auto CPU : CPUNames) {
if (CPU.ArchID == AK && CPU.Default) if (CPU.ArchID == AK && CPU.Default)
return CPU.Name; return CPU.Name;
} }
return nullptr; // Likewise GCC, for common arches, default cpu is generic
return getGenericCPU(Arch);
}
const char *ARMTargetParser::getGenericCPU(StringRef Arch) {
return "generic";
} }
// ======================================================= // // ======================================================= //
// Parsers // Parsers
// ======================================================= // // ======================================================= //
StringRef ARMTargetParser::getHWDivSynonym(StringRef HWDiv) { StringRef ARMTargetParser::getHWDivSynonym(StringRef HWDiv) {
return StringSwitch<StringRef>(HWDiv) return StringSwitch<StringRef>(HWDiv)
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 LinesStringRef ARMTargetParser::getCanonicalArchName(StringRef Arch) {
else if (A.endswith("eb")) else if (A.endswith("eb"))
A = A.substr(0, A.size() - 2); A = A.substr(0, A.size() - 2);
// Trim the head // Trim the head
if (offset != StringRef::npos) if (offset != StringRef::npos)
A = A.substr(offset); A = A.substr(offset);
// Empty string means offset reached the end, which means it's valid. // Empty string means offset reached the end, which means it's valid.
if (A.empty()) if (A.empty())
return Arch; return getSubArch(ARM::AK_DEFAULT);
// Only match non-marketing names // Only match non-marketing names
if (offset != StringRef::npos) { if (offset != StringRef::npos) {
// Must start with 'vN'. // Must start with 'vN'.
if (A[0] != 'v' || !std::isdigit(A[1])) if (A[0] != 'v' || !std::isdigit(A[1]))
return Error; return Error;
// Can't have an extra 'eb'. // Can't have an extra 'eb'.
if (A.find("eb") != StringRef::npos) if (A.find("eb") != StringRef::npos)
Show All 36 Lines
unsigned ARMTargetParser::parseArchExt(StringRef ArchExt) { unsigned ARMTargetParser::parseArchExt(StringRef ArchExt) {
for (const auto A : ARCHExtNames) { for (const auto A : ARCHExtNames) {
if (ArchExt == A.Name) if (ArchExt == A.Name)
return A.ID; return A.ID;
} }
return ARM::AEK_INVALID; return ARM::AEK_INVALID;
} }
unsigned ARMTargetParser::parseCPUArch(StringRef CPU) { unsigned ARMTargetParser::parseCPUArch(StringRef CPU, StringRef Arch) {
if (CPU == getGenericCPU(Arch))
return parseArch(Arch);
for (const auto C : CPUNames) { for (const auto C : CPUNames) {
if (CPU == C.Name) if (CPU == C.Name)
return C.ArchID; return C.ArchID;
} }
return ARM::AK_INVALID; return ARM::AK_INVALID;
} }
// ARM, Thumb, AArch64 // ARM, Thumb, AArch64
▲ Show 20 Lines • Show All 97 Lines • Show Last 20 Lines

lib/Support/Triple.cpp

Show First 20 Lines • Show All 1,297 Lines • ▼ Show 20 Lines case llvm::Triple::Win32:
return "cortex-a9"; return "cortex-a9";
default: default:
break; break;
} }
if (MArch.empty()) if (MArch.empty())
return nullptr; return nullptr;
const char *CPU = ARMTargetParser::getDefaultCPU(MArch); const char *DefaultCPU = ARMTargetParser::getDefaultCPU(MArch);
if (CPU) if (strcmp(DefaultCPU, ARMTargetParser::getGenericCPU(MArch)))
return CPU; return DefaultCPU;
// If no specific architecture version is requested, return the minimum CPU // If architecture version requested is too low, return the minimum CPU
// required by the OS and environment. // required by the OS and environment.
unsigned ArchVersion = ARMTargetParser::parseArchVersion(MArch);
switch (getOS()) { switch (getOS()) {
case llvm::Triple::NetBSD: case llvm::Triple::NetBSD:
switch (getEnvironment()) { switch (getEnvironment()) {
case llvm::Triple::GNUEABIHF: case llvm::Triple::GNUEABIHF:
case llvm::Triple::GNUEABI: case llvm::Triple::GNUEABI:
case llvm::Triple::EABIHF: case llvm::Triple::EABIHF:
case llvm::Triple::EABI: case llvm::Triple::EABI:
if (ArchVersion <= 6)
return "arm926ej-s"; return "arm926ej-s";
return DefaultCPU;
default: default:
if (ArchVersion <= 4)
return "strongarm"; return "strongarm";
return DefaultCPU;
} }
case llvm::Triple::NaCl: case llvm::Triple::NaCl:
return "cortex-a8"; switch (ArchVersion) {
jfbUnsubmitted
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NaCl mandates that the CPU be at least v7 with VFPv3 and NEON, so I think we want to have "cortex-a8" as it was before. NaCl does support integer division when available, so we could handle that too, but it doesn't currently handle features that are new in v8.

jfb: NaCl mandates that the CPU be at least v7 with VFPv3 and NEON, so I think we want to have…
rengolinAuthorUnsubmitted
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This is not true just for NaCl, but for almost every architecture. Your change makes no sense in the grand scheme of things.

rengolin: This is not true just for NaCl, but for almost every architecture. Your change makes no sense…
case 6:
return "arm1136jf-s";
default: default:
switch (getEnvironment()) { return "cortex-a8";
case llvm::Triple::EABIHF:
case llvm::Triple::GNUEABIHF:
return "arm1176jzf-s";
default:
return "arm7tdmi";
} }
default:
return DefaultCPU;
} }
llvm_unreachable("invalid arch name"); llvm_unreachable("invalid arch name");
} }

lib/Target/ARM/ARM.td

Show First 20 Lines • Show All 355 Lines • ▼ Show 20 Lines
def : Processor<"cortex-m0plus", ARMV6Itineraries, [HasV6MOps, FeatureNoARM, def : Processor<"cortex-m0plus", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
FeatureDB, FeatureMClass]>; FeatureDB, FeatureMClass]>;
def : Processor<"cortex-m1", ARMV6Itineraries, [HasV6MOps, FeatureNoARM, def : Processor<"cortex-m1", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
FeatureDB, FeatureMClass]>; FeatureDB, FeatureMClass]>;
def : Processor<"sc000", ARMV6Itineraries, [HasV6MOps, FeatureNoARM, def : Processor<"sc000", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
FeatureDB, FeatureMClass]>; FeatureDB, FeatureMClass]>;
// V6K Processors. // V6K Processors.
def : Processor<"arm1176j-s", ARMV6Itineraries, [HasV6KOps]>;
def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6KOps]>; def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6KOps]>;
def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6KOps, FeatureVFP2, def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
FeatureHasSlowFPVMLx]>; FeatureHasSlowFPVMLx]>;
def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6KOps]>; def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6KOps]>;
def : Processor<"mpcore", ARMV6Itineraries, [HasV6KOps, FeatureVFP2, def : Processor<"mpcore", ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
FeatureHasSlowFPVMLx]>; FeatureHasSlowFPVMLx]>;
// V6T2 Processors. // V6T2 Processors.
▲ Show 20 Lines • Show All 153 Lines • Show Last 20 Lines

lib/Target/ARM/ARMAsmPrinter.cpp

Show First 20 Lines • Show All 550 Lines • ▼ Show 20 Linesvoid ARMAsmPrinter::emitAttributes() {
ATS.switchVendor("aeabi"); ATS.switchVendor("aeabi");
// Compute ARM ELF Attributes based on the default subtarget that // Compute ARM ELF Attributes based on the default subtarget that
// we'd have constructed. The existing ARM behavior isn't LTO clean // we'd have constructed. The existing ARM behavior isn't LTO clean
// anyhow. // anyhow.
// FIXME: For ifunc related functions we could iterate over and look // FIXME: For ifunc related functions we could iterate over and look
// for a feature string that doesn't match the default one. // for a feature string that doesn't match the default one.
const Triple &TT = TM.getTargetTriple(); const Triple &TT = TM.getTargetTriple();
StringRef Arch = TT.getArchName();
StringRef CPU = TM.getTargetCPU(); StringRef CPU = TM.getTargetCPU();
StringRef FS = TM.getTargetFeatureString(); StringRef FS = TM.getTargetFeatureString();
std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU); std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
if (!FS.empty()) { if (!FS.empty()) {
if (!ArchFS.empty()) if (!ArchFS.empty())
ArchFS = (Twine(ArchFS) + "," + FS).str(); ArchFS = (Twine(ArchFS) + "," + FS).str();
else else
ArchFS = FS; ArchFS = FS;
} }
const ARMBaseTargetMachine &ATM = const ARMBaseTargetMachine &ATM =
static_cast<const ARMBaseTargetMachine &>(TM); static_cast<const ARMBaseTargetMachine &>(TM);
const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian()); const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
std::string CPUString = STI.getCPUString(); std::string CPUString = STI.getCPUString();
if (CPUString.find("generic") != 0) { //CPUString doesn't start with "generic"
// FIXME: remove krait check when GNU tools support krait cpu // FIXME: remove krait check when GNU tools support krait cpu
if (STI.isKrait()) { if (STI.isKrait()) {
ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9"); ATS.emitCPUAttribute("cortex-a9", Arch);
// We consider krait as a "cortex-a9" + hwdiv CPU // We consider krait as a "cortex-a9" + hwdiv CPU
// Enable hwdiv through ".arch_extension idiv" // Enable hwdiv through ".arch_extension idiv"
if (STI.hasDivide() || STI.hasDivideInARMMode()) if (STI.hasDivide() || STI.hasDivideInARMMode())
ATS.emitArchExtension(ARM::AEK_HWDIV | ARM::AEK_HWDIVARM); ATS.emitArchExtension(ARM::AEK_HWDIV | ARM::AEK_HWDIVARM);
} else } else
ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString); ATS.emitCPUAttribute(CPUString, Arch);
}
ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI)); ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
// Tag_CPU_arch_profile must have the default value of 0 when "Architecture // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
// profile is not applicable (e.g. pre v7, or cross-profile code)". // profile is not applicable (e.g. pre v7, or cross-profile code)".
if (STI.hasV7Ops()) { if (STI.hasV7Ops()) {
if (STI.isAClass()) { if (STI.isAClass()) {
ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile, ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
▲ Show 20 Lines • Show All 1,276 Lines • Show Last 20 Lines

lib/Target/ARM/ARMSubtarget.cpp

Show All 21 Lines
#include "Thumb1FrameLowering.h" #include "Thumb1FrameLowering.h"
#include "Thumb1InstrInfo.h" #include "Thumb1InstrInfo.h"
#include "Thumb2InstrInfo.h" #include "Thumb2InstrInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Attributes.h" #include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h" #include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h" #include "llvm/IR/GlobalValue.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/TargetParser.h"
#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "arm-subtarget" #define DEBUG_TYPE "arm-subtarget"
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Linesvoid ARMSubtarget::initializeEnvironment() {
StrictAlign = false; StrictAlign = false;
Thumb2DSP = false; Thumb2DSP = false;
UseNaClTrap = false; UseNaClTrap = false;
GenLongCalls = false; GenLongCalls = false;
UnsafeFPMath = false; UnsafeFPMath = false;
} }
void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
if (CPUString.empty()) { StringRef ArchName = TargetTriple.getArchName();
if (isTargetDarwin() && TargetTriple.getArchName().endswith("v7s")) if (CPUString.empty() ||
// Default to the Swift CPU when targeting armv7s/thumbv7s. CPUString == ARMTargetParser::getGenericCPU(ArchName))
CPUString = "swift"; // change "generic" for default CPU. This makes sense for ex, for armv7s,
else // or forced minimum OS/ABI requirements
CPUString = "generic"; CPUString = TargetTriple.getARMCPUForArch(ArchName);
}
// Insert the architecture feature derived from the target triple into the // Insert the architecture feature derived from the target triple into the
// feature string. This is important for setting features that are implied // feature string. This is important for setting features that are implied
// based on the architecture version. // based on the architecture version.
std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString); std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
if (!FS.empty()) { if (!FS.empty()) {
if (!ArchFS.empty()) if (!ArchFS.empty())
ArchFS = (Twine(ArchFS) + "," + FS).str(); ArchFS = (Twine(ArchFS) + "," + FS).str();
▲ Show 20 Lines • Show All 137 Lines • Show Last 20 Lines

lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Linesclass ARMTargetAsmStreamer : public ARMTargetStreamer {
void emitPad(int64_t Offset) override; void emitPad(int64_t Offset) override;
void emitRegSave(const SmallVectorImpl<unsigned> &RegList, void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
bool isVector) override; bool isVector) override;
void emitUnwindRaw(int64_t Offset, void emitUnwindRaw(int64_t Offset,
const SmallVectorImpl<uint8_t> &Opcodes) override; const SmallVectorImpl<uint8_t> &Opcodes) override;
void switchVendor(StringRef Vendor) override; void switchVendor(StringRef Vendor) override;
void emitAttribute(unsigned Attribute, unsigned Value) override; void emitAttribute(unsigned Attribute, unsigned Value) override;
void emitCPUAttribute(StringRef CPUName, StringRef ArchName) override;
void emitTextAttribute(unsigned Attribute, StringRef String) override; void emitTextAttribute(unsigned Attribute, StringRef String) override;
void emitIntTextAttribute(unsigned Attribute, unsigned IntValue, void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
StringRef StrinValue) override; StringRef StrinValue) override;
void emitArch(unsigned Arch) override; void emitArch(unsigned Arch) override;
void emitArchExtension(unsigned ArchExt) override; void emitArchExtension(unsigned ArchExt) override;
void emitObjectArch(unsigned Arch) override; void emitObjectArch(unsigned Arch) override;
void emitFPU(unsigned FPU) override; void emitFPU(unsigned FPU) override;
void emitInst(uint32_t Inst, char Suffix = '\0') override; void emitInst(uint32_t Inst, char Suffix = '\0') override;
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Linesvoid ARMTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
OS << "\t.eabi_attribute\t" << Attribute << ", " << Twine(Value); OS << "\t.eabi_attribute\t" << Attribute << ", " << Twine(Value);
if (IsVerboseAsm) { if (IsVerboseAsm) {
StringRef Name = ARMBuildAttrs::AttrTypeAsString(Attribute); StringRef Name = ARMBuildAttrs::AttrTypeAsString(Attribute);
if (!Name.empty()) if (!Name.empty())
OS << "\t@ " << Name; OS << "\t@ " << Name;
} }
OS << "\n"; OS << "\n";
} }
void ARMTargetAsmStreamer::emitCPUAttribute(StringRef CPUName,
StringRef ArchName) {
if (CPUName == ARMTargetParser::getGenericCPU(ArchName)) {
// emit armXXX instead of thumbXXX
OS << "\t.arch\tarmv";
const char * CPUAttr = ARMTargetParser::getCPUAttr(
ARMTargetParser::parseCPUArch(CPUName, ArchName));
OS << StringRef(CPUAttr).lower() << "\n";
} else
OS << "\t.cpu\t" << CPUName.lower() << "\n";
}
void ARMTargetAsmStreamer::emitTextAttribute(unsigned Attribute, void ARMTargetAsmStreamer::emitTextAttribute(unsigned Attribute,
StringRef String) { StringRef String) {
switch (Attribute) { switch (Attribute) {
case ARMBuildAttrs::CPU_name: case ARMBuildAttrs::CPU_name:
OS << "\t.cpu\t" << String.lower(); OS << "\t.cpu\t" << String.lower();
break; break;
default: default:
OS << "\t.eabi_attribute\t" << Attribute << ", \"" << String << "\""; OS << "\t.eabi_attribute\t" << Attribute << ", \"" << String << "\"";
▲ Show 20 Lines • Show All 195 Lines • ▼ Show 20 Linesprivate:
void emitPad(int64_t Offset) override; void emitPad(int64_t Offset) override;
void emitRegSave(const SmallVectorImpl<unsigned> &RegList, void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
bool isVector) override; bool isVector) override;
void emitUnwindRaw(int64_t Offset, void emitUnwindRaw(int64_t Offset,
const SmallVectorImpl<uint8_t> &Opcodes) override; const SmallVectorImpl<uint8_t> &Opcodes) override;
void switchVendor(StringRef Vendor) override; void switchVendor(StringRef Vendor) override;
void emitAttribute(unsigned Attribute, unsigned Value) override; void emitAttribute(unsigned Attribute, unsigned Value) override;
void emitCPUAttribute(StringRef CPUName, StringRef ArchName) override;
void emitTextAttribute(unsigned Attribute, StringRef String) override; void emitTextAttribute(unsigned Attribute, StringRef String) override;
void emitIntTextAttribute(unsigned Attribute, unsigned IntValue, void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
StringRef StringValue) override; StringRef StringValue) override;
void emitArch(unsigned Arch) override; void emitArch(unsigned Arch) override;
void emitObjectArch(unsigned Arch) override; void emitObjectArch(unsigned Arch) override;
void emitFPU(unsigned FPU) override; void emitFPU(unsigned FPU) override;
void emitInst(uint32_t Inst, char Suffix = '\0') override; void emitInst(uint32_t Inst, char Suffix = '\0') override;
void finishAttributeSection() override; void finishAttributeSection() override;
▲ Show 20 Lines • Show All 275 Lines • ▼ Show 20 Linesvoid ARMTargetELFStreamer::switchVendor(StringRef Vendor) {
assert(Contents.empty() && assert(Contents.empty() &&
".ARM.attributes should be flushed before changing vendor"); ".ARM.attributes should be flushed before changing vendor");
CurrentVendor = Vendor; CurrentVendor = Vendor;
} }
void ARMTargetELFStreamer::emitAttribute(unsigned Attribute, unsigned Value) { void ARMTargetELFStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
setAttributeItem(Attribute, Value, /* OverwriteExisting= */ true); setAttributeItem(Attribute, Value, /* OverwriteExisting= */ true);
} }
void ARMTargetELFStreamer::emitCPUAttribute(StringRef CPUName,
StringRef ArchName) {
if (CPUName == ARMTargetParser::getGenericCPU(ArchName))
CPUName =
ARMTargetParser::getCPUAttr(ARMTargetParser::parseCPUArch(CPUName,
ArchName));
setAttributeItem(ARMBuildAttrs::CPU_name, CPUName,
/* OverwriteExisting= */ true);
}
void ARMTargetELFStreamer::emitTextAttribute(unsigned Attribute, void ARMTargetELFStreamer::emitTextAttribute(unsigned Attribute,
StringRef Value) { StringRef Value) {
setAttributeItem(Attribute, Value, /* OverwriteExisting= */ true); setAttributeItem(Attribute, Value, /* OverwriteExisting= */ true);
} }
void ARMTargetELFStreamer::emitIntTextAttribute(unsigned Attribute, void ARMTargetELFStreamer::emitIntTextAttribute(unsigned Attribute,
unsigned IntValue, unsigned IntValue,
StringRef StringValue) { StringRef StringValue) {
setAttributeItems(Attribute, IntValue, StringValue, setAttributeItems(Attribute, IntValue, StringValue,
▲ Show 20 Lines • Show All 713 Lines • Show Last 20 Lines

lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

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#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrAnalysis.h"
#include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetParser.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
#define GET_REGINFO_MC_DESC #define GET_REGINFO_MC_DESC
#include "ARMGenRegisterInfo.inc" #include "ARMGenRegisterInfo.inc"
static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
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#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_MC_DESC
#include "ARMGenSubtargetInfo.inc" #include "ARMGenSubtargetInfo.inc"
std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) { std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
bool isThumb = bool isThumb =
TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb; TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb;
bool NoCPU = CPU == "generic" || CPU.empty(); StringRef ArchName = TT.getArchName();
bool NoCPU = CPU.empty() ||
CPU == llvm::ARMTargetParser::getGenericCPU(ArchName);
std::string ARMArchFeature; std::string ARMArchFeature;
if (NoCPU) {
rengolinAuthorUnsubmitted
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This change makes no sense. If you want to make it proper, you'll have to iterate through the target features, either from the user info (command-line options, not available here yet), or from the table-gen description (via hasFeatureXXX methods).

This change is just making it hard-coded in a different way. Not worth the change.

rengolin: This change makes no sense. If you want to make it proper, you'll have to iterate through the…
switch (TT.getSubArch()) { switch (TT.getSubArch()) {
default: default:
llvm_unreachable("invalid sub-architecture for ARM"); llvm_unreachable("invalid sub-architecture for ARM");
case Triple::ARMSubArch_v8: case Triple::ARMSubArch_v8:
if (NoCPU) ARMArchFeature = "+v8,+aclass,+db,+trustzone";
// v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
// FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
// FeatureT2XtPk, FeatureCrypto, FeatureCRC
ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
"+trustzone,+t2xtpk,+crypto,+crc";
else
// Use CPU to figure out the exact features
ARMArchFeature = "+v8";
break; break;
case Triple::ARMSubArch_v8_1a: case Triple::ARMSubArch_v8_1a:
if (NoCPU) ARMArchFeature = "+v8.1a,+aclass,+db,+trustzone";
// v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
// FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
// FeatureT2XtPk, FeatureCrypto, FeatureCRC, FeatureV8_1a
ARMArchFeature = "+v8.1a,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
"+trustzone,+t2xtpk,+crypto,+crc";
else
// Use CPU to figure out the exact features
ARMArchFeature = "+v8.1a";
break; break;
case Triple::ARMSubArch_v7m: case Triple::ARMSubArch_v7m:
isThumb = true; isThumb = true;
if (NoCPU) ARMArchFeature = "+v7,+mclass,+db,+noarm";
// v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
else
// Use CPU to figure out the exact features.
ARMArchFeature = "+v7";
break; break;
case Triple::ARMSubArch_v7em: case Triple::ARMSubArch_v7em:
if (NoCPU) isThumb = true;
// v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2, ARMArchFeature = "+v7,+mclass,+db,+noarm,+t2dsp,+t2xtpk";
// FeatureT2XtPk, FeatureMClass
ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,+t2xtpk,+mclass";
else
// Use CPU to figure out the exact features.
ARMArchFeature = "+v7";
break; break;
case Triple::ARMSubArch_v7s: case Triple::ARMSubArch_v7s:
if (NoCPU) ARMArchFeature = "+v7,+swift,+db,+neon,+t2dsp,+ras";
// v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
// Swift
ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
else
// Use CPU to figure out the exact features.
ARMArchFeature = "+v7";
break; break;
case Triple::ARMSubArch_v7: case Triple::ARMSubArch_v7:
// v7 CPUs have lots of different feature sets. If no CPU is specified, ARMArchFeature = "+v7,+db";
// then assume v7a (e.g. cortex-a8) feature set. Otherwise, return switch (ARMTargetParser::parseArch(ArchName)){
// the "minimum" feature set and use CPU string to figure out the exact default:
// features. break;
if (NoCPU) case ARM::AK_ARMV7A:
// v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk ARMArchFeature += ",+aclass";
ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk"; break;
else case ARM::AK_ARMV7R:
// Use CPU to figure out the exact features. ARMArchFeature += ",+rclass";
ARMArchFeature = "+v7"; break;
}
break; break;
case Triple::ARMSubArch_v6t2: case Triple::ARMSubArch_v6t2:
ARMArchFeature = "+v6t2"; ARMArchFeature = "+v6t2";
break; break;
case Triple::ARMSubArch_v6k: case Triple::ARMSubArch_v6k:
ARMArchFeature = "+v6k"; ARMArchFeature = "+v6k";
break; break;
case Triple::ARMSubArch_v6m: case Triple::ARMSubArch_v6m:
isThumb = true; isThumb = true;
if (NoCPU) ARMArchFeature = "+v6m,+mclass,+db,+noarm";
// v6m: FeatureNoARM, FeatureMClass
ARMArchFeature = "+v6m,+noarm,+mclass";
else
ARMArchFeature = "+v6";
break; break;
case Triple::ARMSubArch_v6: case Triple::ARMSubArch_v6:
ARMArchFeature = "+v6"; ARMArchFeature = "+v6";
break; break;
case Triple::ARMSubArch_v5te: case Triple::ARMSubArch_v5te:
ARMArchFeature = "+v5te"; ARMArchFeature = "+v5te";
break; break;
case Triple::ARMSubArch_v5: case Triple::ARMSubArch_v5:
ARMArchFeature = "+v5t"; ARMArchFeature = "+v5t";
break; break;
case Triple::ARMSubArch_v4t: case Triple::ARMSubArch_v4t:
ARMArchFeature = "+v4t"; ARMArchFeature = "+v4t";
break; break;
case Triple::NoSubArch: case Triple::NoSubArch:
break; break;
} }
if (TT.getVendor() == Triple::Apple)
switch (TT.getSubArch()) {
default:
break;
case Triple::ARMSubArch_v8:
case Triple::ARMSubArch_v8_1a:
if (!ARMArchFeature.empty())
ARMArchFeature += ",";
ARMArchFeature += "+neon,+fp-armv8,+fp16";
break;
case Triple::ARMSubArch_v7:
if (!ARMArchFeature.empty())
ARMArchFeature += ",";
ARMArchFeature += "+neon,+vfp3";
break;
}
}
switch (TT.getEnvironment()) {
default:
break;
case llvm::Triple::GNUEABIHF:
case llvm::Triple::EABIHF:
if (!ARMArchFeature.empty())
ARMArchFeature += ",";
switch (ARMTargetParser::parseArchVersion(ArchName)) {
default:
ARMArchFeature += "+vfp2";
break;
case 7:
ARMArchFeature += "+vfp3";
break;
case 8:
ARMArchFeature += "+fp-armv8";
break;
}
}
if (isThumb) { if (isThumb) {
if (ARMArchFeature.empty()) if (ARMArchFeature.empty())
ARMArchFeature = "+thumb-mode"; ARMArchFeature = "+thumb-mode";
else else
ARMArchFeature += ",+thumb-mode"; ARMArchFeature += ",+thumb-mode";
} }
if (TT.isOSNaCl()) { if (TT.isOSNaCl()) {
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lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp

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void ARMTargetStreamer::emitPad(int64_t Offset) {} void ARMTargetStreamer::emitPad(int64_t Offset) {}
void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
bool isVector) {} bool isVector) {}
void ARMTargetStreamer::emitUnwindRaw(int64_t StackOffset, void ARMTargetStreamer::emitUnwindRaw(int64_t StackOffset,
const SmallVectorImpl<uint8_t> &Opcodes) { const SmallVectorImpl<uint8_t> &Opcodes) {
} }
void ARMTargetStreamer::switchVendor(StringRef Vendor) {} void ARMTargetStreamer::switchVendor(StringRef Vendor) {}
void ARMTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {} void ARMTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
void ARMTargetStreamer::emitCPUAttribute(StringRef CPUName,
StringRef ArchName) {}
void ARMTargetStreamer::emitTextAttribute(unsigned Attribute, void ARMTargetStreamer::emitTextAttribute(unsigned Attribute,
StringRef String) {} StringRef String) {}
void ARMTargetStreamer::emitIntTextAttribute(unsigned Attribute, void ARMTargetStreamer::emitIntTextAttribute(unsigned Attribute,
unsigned IntValue, unsigned IntValue,
StringRef StringValue) {} StringRef StringValue) {}
void ARMTargetStreamer::emitArch(unsigned Arch) {} void ARMTargetStreamer::emitArch(unsigned Arch) {}
void ARMTargetStreamer::emitArchExtension(unsigned ArchExt) {} void ARMTargetStreamer::emitArchExtension(unsigned ArchExt) {}
void ARMTargetStreamer::emitObjectArch(unsigned Arch) {} void ARMTargetStreamer::emitObjectArch(unsigned Arch) {}
void ARMTargetStreamer::emitFPU(unsigned FPU) {} void ARMTargetStreamer::emitFPU(unsigned FPU) {}
void ARMTargetStreamer::finishAttributeSection() {} void ARMTargetStreamer::finishAttributeSection() {}
void ARMTargetStreamer::emitInst(uint32_t Inst, char Suffix) {} void ARMTargetStreamer::emitInst(uint32_t Inst, char Suffix) {}
void void
ARMTargetStreamer::AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) {} ARMTargetStreamer::AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) {}
void ARMTargetStreamer::emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) {} void ARMTargetStreamer::emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) {}

test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll

; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=fast ; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=fast -mattr=+neon
; Previously we'd crash as out of registers on this input by clobbering all of ; Previously we'd crash as out of registers on this input by clobbering all of
; the aliases. ; the aliases.
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
target triple = "thumbv7-apple-darwin10.0.0" target triple = "thumbv7-apple-darwin10.0.0"
define void @_Z8TestCasev() nounwind ssp { define void @_Z8TestCasev() nounwind ssp {
entry: entry:
%a = alloca float, align 4 %a = alloca float, align 4
%tmp = load float, float* %a, align 4 %tmp = load float, float* %a, align 4
call void asm sideeffect "", "w,~{s0},~{s16}"(float %tmp) nounwind, !srcloc !0 call void asm sideeffect "", "w,~{s0},~{s16}"(float %tmp) nounwind, !srcloc !0
ret void ret void
} }
!0 = !{i32 109} !0 = !{i32 109}

test/CodeGen/ARM/2012-08-09-neon-extload.ll

; RUN: llc -mtriple=armv7-none-linux-gnueabi < %s | FileCheck %s ; RUN: llc -mtriple=armv7-none-linux-gnueabi -mattr=+neon < %s | FileCheck %s
@var_v2i8 = global <2 x i8> zeroinitializer @var_v2i8 = global <2 x i8> zeroinitializer
@var_v4i8 = global <4 x i8> zeroinitializer @var_v4i8 = global <4 x i8> zeroinitializer
@var_v2i16 = global <2 x i16> zeroinitializer @var_v2i16 = global <2 x i16> zeroinitializer
@var_v4i16 = global <4 x i16> zeroinitializer @var_v4i16 = global <4 x i16> zeroinitializer
@var_v2i32 = global <2 x i32> zeroinitializer @var_v2i32 = global <2 x i32> zeroinitializer
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test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll

; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=+neon| FileCheck %s
; Test that we correctly use registers and align elements when using va_arg ; Test that we correctly use registers and align elements when using va_arg
%struct_t = type { double, double, double } %struct_t = type { double, double, double }
@static_val = constant %struct_t { double 1.0, double 2.0, double 3.0 } @static_val = constant %struct_t { double 1.0, double 2.0, double 3.0 }
declare void @llvm.va_start(i8*) nounwind declare void @llvm.va_start(i8*) nounwind
declare void @llvm.va_end(i8*) nounwind declare void @llvm.va_end(i8*) nounwind
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test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll

; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=+neon| FileCheck %s
@.str = private unnamed_addr constant [12 x i8] c"val.a = %f\0A\00" @.str = private unnamed_addr constant [12 x i8] c"val.a = %f\0A\00"
%struct_t = type { double, double, double } %struct_t = type { double, double, double }
@static_val = constant %struct_t { double 1.0, double 2.0, double 3.0 } @static_val = constant %struct_t { double 1.0, double 2.0, double 3.0 }
declare i32 @printf(i8*, ...) declare i32 @printf(i8*, ...)
; CHECK-LABEL: test_byval_usage_scheduling: ; CHECK-LABEL: test_byval_usage_scheduling:
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test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll

;PR15293: ARM codegen ice - expected larger existing stack allocation ;PR15293: ARM codegen ice - expected larger existing stack allocation
;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s ;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
;CHECK-LABEL: foo: ;CHECK-LABEL: foo:
;CHECK: sub sp, sp, #16 ;CHECK: sub sp, sp, #16
;CHECK: push {r11, lr} ;CHECK: push {r11, lr}
;CHECK: str r0, [sp, #8] ;CHECK: str r0, [sp, #8]
;CHECK: add r0, sp, #8 ;CHECK: add r0, sp, #8
;CHECK: bl fooUseParam ;CHECK: bl fooUseParam
;CHECK: pop {r11, lr} ;CHECK: pop {r11, lr}
;CHECK: add sp, sp, #16 ;CHECK: add sp, sp, #16
;CHECK: mov pc, lr ;CHECK: bx lr
;CHECK-LABEL: foo2: ;CHECK-LABEL: foo2:
;CHECK: sub sp, sp, #16 ;CHECK: sub sp, sp, #16
;CHECK: push {r11, lr} ;CHECK: push {r11, lr}
;CHECK: str r0, [sp, #8] ;CHECK: str r0, [sp, #8]
;CHECK: add r0, sp, #8 ;CHECK: add r0, sp, #8
;CHECK: str r2, [sp, #16] ;CHECK: str r2, [sp, #16]
;CHECK: bl fooUseParam ;CHECK: bl fooUseParam
;CHECK: add r0, sp, #16 ;CHECK: add r0, sp, #16
;CHECK: bl fooUseParam ;CHECK: bl fooUseParam
;CHECK: pop {r11, lr} ;CHECK: pop {r11, lr}
;CHECK: add sp, sp, #16 ;CHECK: add sp, sp, #16
;CHECK: mov pc, lr ;CHECK: bx lr
;CHECK-LABEL: doFoo: ;CHECK-LABEL: doFoo:
;CHECK: push {r11, lr} ;CHECK: push {r11, lr}
;CHECK: ldr r0, ;CHECK: ldr r0,
;CHECK: ldr r0, [r0] ;CHECK: ldr r0, [r0]
;CHECK: bl foo ;CHECK: bl foo
;CHECK: pop {r11, lr} ;CHECK: pop {r11, lr}
;CHECK: mov pc, lr ;CHECK: bx lr
;CHECK-LABEL: doFoo2: ;CHECK-LABEL: doFoo2:
;CHECK: push {r11, lr} ;CHECK: push {r11, lr}
;CHECK: ldr r0, ;CHECK: ldr r0,
;CHECK: mov r1, #0 ;CHECK: mov r1, #0
;CHECK: ldr r0, [r0] ;CHECK: ldr r0, [r0]
;CHECK: mov r2, r0 ;CHECK: mov r2, r0
;CHECK: bl foo2 ;CHECK: bl foo2
;CHECK: pop {r11, lr} ;CHECK: pop {r11, lr}
;CHECK: mov pc, lr ;CHECK: bx lr
%artz = type { i32 } %artz = type { i32 }
@static_val = constant %artz { i32 777 } @static_val = constant %artz { i32 777 }
declare void @fooUseParam(%artz* ) declare void @fooUseParam(%artz* )
define void @foo(%artz* byval %s) { define void @foo(%artz* byval %s) {
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test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll

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; unsigned p9) { ; unsigned p9) {
; fooUseI32(p9); ; fooUseI32(p9);
;} ;}
; ;
;void doFoo() { ;void doFoo() {
; foo( 1,2,3,4,5,6,7,8,9, 43 ); ; foo( 1,2,3,4,5,6,7,8,9, 43 );
;} ;}
;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s ;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard -mattr=+neon< %s | FileCheck %s
; ;
;CHECK-LABEL: foo: ;CHECK-LABEL: foo:
;CHECK-NOT: mov r0 ;CHECK-NOT: mov r0
;CHECK-NOT: ldr r0 ;CHECK-NOT: ldr r0
;CHECK: bl fooUseI32 ;CHECK: bl fooUseI32
;CHECK-LABEL: doFoo: ;CHECK-LABEL: doFoo:
;CHECK: movs r0, #43 ;CHECK: movs r0, #43
;CHECK: bl foo ;CHECK: bl foo
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test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll

;Check 5.5 Parameter Passing --> Stage C --> C.5 statement, when NSAA is not ;Check 5.5 Parameter Passing --> Stage C --> C.5 statement, when NSAA is not
;equal to SP. ;equal to SP.
; ;
; Our purpose: make NSAA != SP, and only after start to use GPRs, then pass ; Our purpose: make NSAA != SP, and only after start to use GPRs, then pass
; byval parameter and check that it goes to stack only. ; byval parameter and check that it goes to stack only.
; ;
;Co-Processor register candidates may be either in VFP or in stack, so after ;Co-Processor register candidates may be either in VFP or in stack, so after
;all VFP are allocated, stack is used. We can use stack without GPR allocation ;all VFP are allocated, stack is used. We can use stack without GPR allocation
;in that case, passing 9 f64 params, for example. ;in that case, passing 9 f64 params, for example.
;First eight params goes to d0-d7, ninth one goes to the stack. ;First eight params goes to d0-d7, ninth one goes to the stack.
;Now, as 10th parameter, we pass i32, and it must go to R0. ;Now, as 10th parameter, we pass i32, and it must go to R0.
; ;
;For more information, ;For more information,
;please, read 5.5 Parameter Passing, Stage C, stages C.2.cp, C.4 and C.5 ;please, read 5.5 Parameter Passing, Stage C, stages C.2.cp, C.4 and C.5
; ;
; ;
;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s ;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard -mattr=+neon < %s | FileCheck %s
%struct_t = type { i32, i32, i32, i32 } %struct_t = type { i32, i32, i32, i32 }
@static_val = constant %struct_t { i32 777, i32 888, i32 999, i32 1000 } @static_val = constant %struct_t { i32 777, i32 888, i32 999, i32 1000 }
declare void @fooUseStruct(%struct_t*) declare void @fooUseStruct(%struct_t*)
define void @foo2(double %p0, ; --> D0 define void @foo2(double %p0, ; --> D0
double %p1, ; --> D1 double %p1, ; --> D1
double %p2, ; --> D2 double %p2, ; --> D2
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test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll

;Check 5.5 Parameter Passing --> Stage C --> C.1.cp statement for VA functions. ;Check 5.5 Parameter Passing --> Stage C --> C.1.cp statement for VA functions.
;Note: There are no VFP CPRCs in a variadic procedure. ;Note: There are no VFP CPRCs in a variadic procedure.
;Check that after %C was sent to stack, we set Next Core Register Number to R4. ;Check that after %C was sent to stack, we set Next Core Register Number to R4.
;This test is simplified IR version of ;This test is simplified IR version of
;test-suite/SingleSource/UnitTests/2002-05-02-ManyArguments.c ;test-suite/SingleSource/UnitTests/2002-05-02-ManyArguments.c
;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s ;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard -mattr=+neon < %s | FileCheck %s
@.str = private unnamed_addr constant [13 x i8] c"%d %d %f %i\0A\00", align 1 @.str = private unnamed_addr constant [13 x i8] c"%d %d %f %i\0A\00", align 1
;CHECK-LABEL: printfn: ;CHECK-LABEL: printfn:
define void @printfn(i32 %a, i16 signext %b, double %C, i8 signext %E) { define void @printfn(i32 %a, i16 signext %b, double %C, i8 signext %E) {
entry: entry:
%conv = sext i16 %b to i32 %conv = sext i16 %b to i32
%conv1 = sext i8 %E to i32 %conv1 = sext i8 %E to i32
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test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll

;Check AAPCS, 5.5 Parameters Passing, C4 and C5 rules. ;Check AAPCS, 5.5 Parameters Passing, C4 and C5 rules.
;Check case when NSAA != 0, and NCRN < R4, NCRN+ParamSize < R4 ;Check case when NSAA != 0, and NCRN < R4, NCRN+ParamSize < R4
;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s ;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard -mattr=+neon < %s | FileCheck %s
%st_t = type { i32, i32 } %st_t = type { i32, i32 }
@static_val = constant %st_t { i32 777, i32 888} @static_val = constant %st_t { i32 777, i32 888}
declare void @fooUseStruct(%st_t*) declare void @fooUseStruct(%st_t*)
define void @foo(double %vfp0, ; --> D0, NSAA=SP define void @foo(double %vfp0, ; --> D0, NSAA=SP
double %vfp1, ; --> D1, NSAA=SP double %vfp1, ; --> D1, NSAA=SP
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test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll

;Check AAPCS, 5.5 Parameters Passing, C4 and C5 rules. ;Check AAPCS, 5.5 Parameters Passing, C4 and C5 rules.
;Check case when NSAA != 0, and NCRN < R4, NCRN+ParamSize > R4 ;Check case when NSAA != 0, and NCRN < R4, NCRN+ParamSize > R4
;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s ;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard -mattr=+neon< %s | FileCheck %s
%st_t = type { i32, i32, i32, i32 } %st_t = type { i32, i32, i32, i32 }
@static_val = constant %st_t { i32 777, i32 888, i32 787, i32 878} @static_val = constant %st_t { i32 777, i32 888, i32 787, i32 878}
define void @foo(double %vfp0, ; --> D0, NSAA=SP define void @foo(double %vfp0, ; --> D0, NSAA=SP
double %vfp1, ; --> D1, NSAA=SP double %vfp1, ; --> D1, NSAA=SP
double %vfp2, ; --> D2, NSAA=SP double %vfp2, ; --> D2, NSAA=SP
double %vfp3, ; --> D3, NSAA=SP double %vfp3, ; --> D3, NSAA=SP
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test/CodeGen/ARM/2014-02-05-vfp-regs-after-stack.ll

; RUN: llc < %s -o - -filetype=asm | FileCheck %s ; RUN: llc < %s -o - -filetype=asm -mattr=+neon | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"
target triple = "armv8-none--eabi" target triple = "armv8-none--eabi"
; CHECK-LABEL: fn1: ; CHECK-LABEL: fn1:
define arm_aapcs_vfpcc float @fn1(double %a, double %b, double %c, double %d, double %e, double %f, double %g, float %h, double %i, float %j) { define arm_aapcs_vfpcc float @fn1(double %a, double %b, double %c, double %d, double %e, double %f, double %g, float %h, double %i, float %j) {
ret float %j ret float %j
; CHECK: vldr s0, [sp, #8] ; CHECK: vldr s0, [sp, #8]
Show All 13 Lines

test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
; CHECK: push {r11, lr} ; CHECK: push {r11, lr}
; CHECK: str r0, [sp, #8] ; CHECK: str r0, [sp, #8]
; CHECK: add r0, sp, #16 ; CHECK: add r0, sp, #16
; CHECK: str r3, [sp, #20] ; CHECK: str r3, [sp, #20]
; CHECK: str r2, [sp, #16] ; CHECK: str r2, [sp, #16]
; CHECK: bl usePtr ; CHECK: bl usePtr
; CHECK: pop {r11, lr} ; CHECK: pop {r11, lr}
; CHECK: add sp, sp, #16 ; CHECK: add sp, sp, #16
; CHECK: mov pc, lr ; CHECK: bx lr
call void @usePtr(%struct8bytes8align* %b) call void @usePtr(%struct8bytes8align* %b)
ret void ret void
} }
; a -> r0..r1 ; a -> r0..r1
; b -> r2 ; b -> r2
; c -> r3 ; c -> r3
define void @foo5(%struct8bytes8align* byval %a, %struct4bytes* byval %b, %struct4bytes* byval %c) { define void @foo5(%struct8bytes8align* byval %a, %struct4bytes* byval %b, %struct4bytes* byval %c) {
; CHECK-LABEL: foo5 ; CHECK-LABEL: foo5
; CHECK: sub sp, sp, #16 ; CHECK: sub sp, sp, #16
; CHECK: push {r11, lr} ; CHECK: push {r11, lr}
; CHECK: add [[SCRATCH:r[0-9]+]], sp, #8 ; CHECK: add [[SCRATCH:r[0-9]+]], sp, #8
; CHECK: stm [[SCRATCH]], {r0, r1, r2, r3} ; CHECK: stm [[SCRATCH]], {r0, r1, r2, r3}
; CHECK: add r0, sp, #8 ; CHECK: add r0, sp, #8
; CHECK: bl usePtr ; CHECK: bl usePtr
; CHECK: pop {r11, lr} ; CHECK: pop {r11, lr}
; CHECK: add sp, sp, #16 ; CHECK: add sp, sp, #16
; CHECK: mov pc, lr ; CHECK: bx lr
call void @usePtr(%struct8bytes8align* %a) call void @usePtr(%struct8bytes8align* %a)
ret void ret void
} }
; a..c -> r0..r2 ; a..c -> r0..r2
; d -> sp+0..sp+7 ; d -> sp+0..sp+7
define void @foo6(i32 %a, i32 %b, i32 %c, %struct8bytes8align* byval %d) { define void @foo6(i32 %a, i32 %b, i32 %c, %struct8bytes8align* byval %d) {
; CHECK-LABEL: foo6 ; CHECK-LABEL: foo6
; CHECK: push {r11, lr} ; CHECK: push {r11, lr}
; CHECK: add r0, sp, #8 ; CHECK: add r0, sp, #8
; CHECK: bl usePtr ; CHECK: bl usePtr
; CHECK: pop {r11, lr} ; CHECK: pop {r11, lr}
; CHECK: mov pc, lr ; CHECK: bx lr
call void @usePtr(%struct8bytes8align* %d) call void @usePtr(%struct8bytes8align* %d)
ret void ret void
} }

test/CodeGen/ARM/Windows/alloca.ll

; RUN: llc -O0 -mtriple thumbv7-windows-itanium -filetype asm -o - %s | FileCheck %s ; RUN: llc -O0 -mtriple thumbv7-windows-itanium -mattr=+neon -filetype asm -o - %s | FileCheck %s
declare arm_aapcs_vfpcc i32 @num_entries() declare arm_aapcs_vfpcc i32 @num_entries()
define arm_aapcs_vfpcc void @test___builtin_alloca() { define arm_aapcs_vfpcc void @test___builtin_alloca() {
entry: entry:
%array = alloca i8*, align 4 %array = alloca i8*, align 4
%call = call arm_aapcs_vfpcc i32 @num_entries() %call = call arm_aapcs_vfpcc i32 @num_entries()
%mul = mul i32 4, %call %mul = mul i32 4, %call
%0 = alloca i8, i32 %mul %0 = alloca i8, i32 %mul
store i8* %0, i8** %array, align 4 store i8* %0, i8** %array, align 4
ret void ret void
} }
; CHECK: bl num_entries ; CHECK: bl num_entries
; CHECK: movs [[R1:r[0-9]+]], #7 ; CHECK: movs [[R1:r[0-9]+]], #7
; CHECK: add.w [[R0:r[0-9]+]], [[R1]], [[R0]], lsl #2 ; CHECK: add.w [[R0:r[0-9]+]], [[R1]], [[R0]], lsl #2
; CHECK: bic [[R0]], [[R0]], #7 ; CHECK: bic [[R0]], [[R0]], #7
; CHECK: lsrs r4, [[R0]], #2 ; CHECK: lsr.w r4, [[R0]], #2
; CHECK: bl __chkstk ; CHECK: bl __chkstk
; CHECK: sub.w sp, sp, r4 ; CHECK: sub.w sp, sp, r4

test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll

Show All 13 Linesentry:
%rem = urem i32 %0, 4096 %rem = urem i32 %0, 4096
%arrayidx = getelementptr inbounds [4096 x i8], [4096 x i8]* %buffer, i32 0, i32 %rem %arrayidx = getelementptr inbounds [4096 x i8], [4096 x i8]* %buffer, i32 0, i32 %rem
%1 = load volatile i8, i8* %arrayidx, align 1 %1 = load volatile i8, i8* %arrayidx, align 1
ret i8 %1 ret i8 %1
} }
; CHECK-LABEL: isel ; CHECK-LABEL: isel
; CHECK: push {r4, r5} ; CHECK: push {r4, r5}
; CHECK: movw r4, #{{\d*}}
; CHECK: movw r12, #0 ; CHECK: movw r12, #0
; CHECK: movt r12, #0 ; CHECK: movt r12, #0
; CHECK: movw r4, #{{\d*}}
; CHECK: blx r12 ; CHECK: blx r12
; CHECK: sub.w sp, sp, r4 ; CHECK: sub.w sp, sp, r4

test/CodeGen/ARM/aapcs-hfa-code.ll

; RUN: llc < %s -mtriple=armv7-linux-gnueabihf -o - | FileCheck %s ; RUN: llc < %s -mtriple=armv7-linux-gnueabihf -mattr=+neon -o - | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7em-none-eabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CHECK-M4F ; RUN: llc < %s -mtriple=thumbv7em-none-eabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CHECK-M4F
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"
define arm_aapcs_vfpcc void @test_1float({ float } %a) { define arm_aapcs_vfpcc void @test_1float({ float } %a) {
call arm_aapcs_vfpcc void @test_1float({ float } { float 1.0 }) call arm_aapcs_vfpcc void @test_1float({ float } { float 1.0 })
ret void ret void
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test/CodeGen/ARM/aapcs-hfa.ll

; RUN: llc < %s -float-abi=hard -debug-only arm-isel 2>&1 | FileCheck %s ; RUN: llc < %s -float-abi=hard -mattr=+neon -debug-only arm-isel 2>&1 | FileCheck %s
; RUN: llc < %s -float-abi=soft -debug-only arm-isel 2>&1 | FileCheck %s --check-prefix=SOFT ; RUN: llc < %s -float-abi=soft -mattr=+neon -debug-only arm-isel 2>&1 | FileCheck %s --check-prefix=SOFT
; REQUIRES: asserts ; REQUIRES: asserts
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"
target triple = "armv7-none--eabi" target triple = "armv7-none--eabi"
; SOFT-NOT: isHA ; SOFT-NOT: isHA
; CHECK: isHA: 1 { float } ; CHECK: isHA: 1 { float }
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test/CodeGen/ARM/aggregate-padding.ll

; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s ; RUN: llc -mtriple=armv7-linux-gnueabihf -mattr=+neon %s -o - | FileCheck %s
; [2 x i64] should be contiguous when split (e.g. we shouldn't try to align all ; [2 x i64] should be contiguous when split (e.g. we shouldn't try to align all
; i32 components to 64 bits). Also makes sure i64 based types are properly ; i32 components to 64 bits). Also makes sure i64 based types are properly
; aligned on the stack. ; aligned on the stack.
define i64 @test_i64_contiguous_on_stack([8 x double], float, i32 %in, [2 x i64] %arg) nounwind { define i64 @test_i64_contiguous_on_stack([8 x double], float, i32 %in, [2 x i64] %arg) nounwind {
; CHECK-LABEL: test_i64_contiguous_on_stack: ; CHECK-LABEL: test_i64_contiguous_on_stack:
; CHECK-DAG: ldr [[LO0:r[0-9]+]], [sp, #8] ; CHECK-DAG: ldr [[LO0:r[0-9]+]], [sp, #8]
; CHECK-DAG: ldr [[HI0:r[0-9]+]], [sp, #12] ; CHECK-DAG: ldr [[HI0:r[0-9]+]], [sp, #12]
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test/CodeGen/ARM/arguments.ll

Show All 22 Linesentry:
%.0 = zext i1 %not. to i32 ; <i32> [#uses=1] %.0 = zext i1 %not. to i32 ; <i32> [#uses=1]
ret i32 %.0 ret i32 %.0
} }
; test that on gnueabi a 64 bit value at this position will cause r3 to go ; test that on gnueabi a 64 bit value at this position will cause r3 to go
; unused and the value stored in [sp] ; unused and the value stored in [sp]
; ELF-LABEL: f3: ; ELF-LABEL: f3:
; ELF: ldr r0, [sp] ; ELF: ldr r0, [sp]
; ELF-NEXT: mov pc, lr ; ELF-NEXT: bx lr
; DARWIN-LABEL: f3: ; DARWIN-LABEL: f3:
; DARWIN: mov r0, r3 ; DARWIN: mov r0, r3
; DARWIN-NEXT: mov pc, lr ; DARWIN-NEXT: bx lr
define i32 @f3(i32 %i, i32 %j, i32 %k, i64 %l, ...) { define i32 @f3(i32 %i, i32 %j, i32 %k, i64 %l, ...) {
entry: entry:
%0 = trunc i64 %l to i32 %0 = trunc i64 %l to i32
ret i32 %0 ret i32 %0
} }
declare i32 @g1(i64) declare i32 @g1(i64)
declare i32 @g2(i32 %i, ...) declare i32 @g2(i32 %i, ...)

test/CodeGen/ARM/arm-shrink-wrapping.ll

Show First 20 Lines • Show All 509 Lines • ▼ Show 20 Lines
; ENABLE-NEXT: bx lr ; ENABLE-NEXT: bx lr
; ;
; DISABLE-NEXT: pop ; DISABLE-NEXT: pop
;; ;;
; CHECK: [[ABORT]]: @ %if.abort ; CHECK: [[ABORT]]: @ %if.abort
; ;
; ENABLE: push ; ENABLE: push
; ;
; CHECK: bl{{x?}} _abort ; CHECK: b{{l?}}{{x?}} _abort
; ENABLE-NOT: pop ; ENABLE-NOT: pop
define i32 @noreturn(i8 signext %bad_thing) { define i32 @noreturn(i8 signext %bad_thing) {
entry: entry:
%tobool = icmp eq i8 %bad_thing, 0 %tobool = icmp eq i8 %bad_thing, 0
br i1 %tobool, label %if.end, label %if.abort br i1 %tobool, label %if.end, label %if.abort
if.abort: if.abort:
%call = tail call i32 asm sideeffect "mov $0, #1", "=r,~{r4}"() %call = tail call i32 asm sideeffect "mov $0, #1", "=r,~{r4}"()
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test/CodeGen/ARM/build-attributes.ll

; This tests that MC/asm header conversion is smooth and that the ; This tests that MC/asm header conversion is smooth and that the
; build attributes are correct ; build attributes are correct
; RUN: llc < %s -mtriple=thumbv5-linux-gnueabi -mcpu=xscale -mattr=+strict-align | FileCheck %s --check-prefix=XSCALE ; RUN: llc < %s -mtriple=thumbv5-linux-gnueabi -mcpu=xscale -mattr=+strict-align | FileCheck %s --check-prefix=XSCALE
; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=V6 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=V6
; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6-FAST ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6-FAST
; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=V6M ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=V6M
; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST
; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=V6M ; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=V6SM
; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST ; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6SM-FAST
; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -mattr=+strict-align | FileCheck %s --check-prefix=ARM1156T2F-S ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -mattr=+strict-align | FileCheck %s --check-prefix=ARM1156T2F-S
; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=ARM1156T2F-S-FAST ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=ARM1156T2F-S-FAST
; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi | FileCheck %s --check-prefix=V7M ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi | FileCheck %s --check-prefix=V7M
; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V7M-FAST ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V7M-FAST
; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=V7 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=V7
; RUN: llc < %s -mtriple=armv7a-linux-gnueabi | FileCheck %s --check-prefix=V7A
; RUN: llc < %s -mtriple=armv7r-linux-gnueabi | FileCheck %s --check-prefix=V7R
; RUN: llc < %s -mtriple=armv7s-linux-gnueabi | FileCheck %s --check-prefix=V7S
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V7-FAST ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V7-FAST
; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V8-FAST ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V8-FAST
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi | FileCheck %s --check-prefix=Vt8 ; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi | FileCheck %s --check-prefix=Vt8
; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-neon,-crypto | FileCheck %s --check-prefix=V8-FPARMv8 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+fp-armv8,-neon,-crypto | FileCheck %s --check-prefix=V8-FPARMv8
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-fp-armv8,-crypto | FileCheck %s --check-prefix=V8-NEON ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-fp-armv8,+neon,-crypto | FileCheck %s --check-prefix=V8-NEON
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-crypto | FileCheck %s --check-prefix=V8-FPARMv8-NEON ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+fp-armv8,+neon,-crypto | FileCheck %s --check-prefix=V8-FPARMv8-NEON
; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8-FPARMv8-NEON-CRYPTO ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+fp-armv8,+neon,+crypto | FileCheck %s --check-prefix=V8-FPARMv8-NEON-CRYPTO
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT-FAST ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT-FAST
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-neon,+d16 | FileCheck %s --check-prefix=CORTEX-A5-NONEON ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-neon,+d16 | FileCheck %s --check-prefix=CORTEX-A5-NONEON
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A5-NOFPU ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A5-NOFPU
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-NOFPU-FAST ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-NOFPU-FAST
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A9-SOFT ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A9-SOFT
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A9-SOFT-FAST ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A9-SOFT-FAST
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; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A53-FAST ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A53-FAST
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A57-FAST ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A57-FAST
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 | FileCheck %s --check-prefix=CORTEX-A72 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 | FileCheck %s --check-prefix=CORTEX-A72
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A72-FAST ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A72-FAST
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi | FileCheck %s --check-prefix=GENERIC-ARMV8_1-A ; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi | FileCheck %s --check-prefix=V8_1A
; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=GENERIC-ARMV8_1-A-FAST ; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -mattr=+fp-armv8,-neon,-crypto | FileCheck %s --check-prefix=V8_1A-FPARMv8
; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -mattr=-fp-armv8,+neon,-crypto | FileCheck %s --check-prefix=V8_1A-NEON
; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -mattr=+fp-armv8,+neon,-crypto | FileCheck %s --check-prefix=V8_1A-FPARMv8-NEON
; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -mattr=+fp-armv8,+neon,+crypto | FileCheck %s --check-prefix=V8_1A-FPARMv8-NEON-CRYPTO
; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V8_1A-FAST
; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s --check-prefix=CORTEX-A7-CHECK ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s --check-prefix=CORTEX-A7-CHECK
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-CHECK-FAST ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-CHECK-FAST
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2,-vfp3,-vfp4,-neon,-fp16 | FileCheck %s --check-prefix=CORTEX-A7-NOFPU ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2,-vfp3,-vfp4,-neon,-fp16 | FileCheck %s --check-prefix=CORTEX-A7-NOFPU
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2,-vfp3,-vfp4,-neon,-fp16 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-NOFPU-FAST ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2,-vfp3,-vfp4,-neon,-fp16 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-NOFPU-FAST
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,-neon | FileCheck %s --check-prefix=CORTEX-A7-FPUV4 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,-neon | FileCheck %s --check-prefix=CORTEX-A7-FPUV4
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,-neon -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-FPUV4-FAST ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,-neon -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-FPUV4-FAST
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; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
; XSCALE: .eabi_attribute 6, 5 ; XSCALE: .eabi_attribute 6, 5
; XSCALE: .eabi_attribute 8, 1 ; XSCALE: .eabi_attribute 8, 1
; XSCALE: .eabi_attribute 9, 1 ; XSCALE: .eabi_attribute 9, 1
; DYN-ROUNDING: .eabi_attribute 19, 1 ; DYN-ROUNDING: .eabi_attribute 19, 1
; V6: .arch armv6
; V6: .eabi_attribute 6, 6 ; V6: .eabi_attribute 6, 6
; V6: .eabi_attribute 8, 1 ; V6: .eabi_attribute 8, 1
;; We assume round-to-nearest by default (matches GCC) ;; We assume round-to-nearest by default (matches GCC)
; V6-NOT: .eabi_attribute 19 ; V6-NOT: .eabi_attribute 19
;; The default choice made by llc is for a V6 CPU without an FPU. ;; The default choice made by llc is for a V6 CPU without an FPU.
;; This is not an interesting detail, but for such CPUs, the default intention is to use ;; This is not an interesting detail, but for such CPUs, the default intention is to use
;; software floating-point support. The choice is not important for targets without ;; software floating-point support. The choice is not important for targets without
;; FPU support! ;; FPU support!
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;; fast maths software library might. ;; fast maths software library might.
; V6-FAST-NOT: .eabi_attribute 20 ; V6-FAST-NOT: .eabi_attribute 20
; V6-FAST-NOT: .eabi_attribute 21 ; V6-FAST-NOT: .eabi_attribute 21
; V6-FAST-NOT: .eabi_attribute 22 ; V6-FAST-NOT: .eabi_attribute 22
; V6-FAST: .eabi_attribute 23, 1 ; V6-FAST: .eabi_attribute 23, 1
;; We emit 6, 12 for both v6-M and v6S-M, technically this is incorrect for ;; We emit 6, 12 for both v6-M and v6S-M, technically this is incorrect for
;; V6-M, however we don't model the OS extension so this is fine. ;; V6-M, however we don't model the OS extension so this is fine.
; V6M: .arch armv6-m
; V6M: .eabi_attribute 6, 12 ; V6M: .eabi_attribute 6, 12
; V6M-NOT: .eabi_attribute 7 ; V6M-NOT: .eabi_attribute 7
; V6M: .eabi_attribute 8, 0 ; V6M: .eabi_attribute 8, 0
; V6M: .eabi_attribute 9, 1 ; V6M: .eabi_attribute 9, 1
; V6M-NOT: .eabi_attribute 19 ; V6M-NOT: .eabi_attribute 19
;; The default choice made by llc is for a V6M CPU without an FPU. ;; The default choice made by llc is for a V6M CPU without an FPU.
;; This is not an interesting detail, but for such CPUs, the default intention is to use ;; This is not an interesting detail, but for such CPUs, the default intention is to use
;; software floating-point support. The choice is not important for targets without ;; software floating-point support. The choice is not important for targets without
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;; Despite the V6M CPU having no FPU by default, we chose to flush to ;; Despite the V6M CPU having no FPU by default, we chose to flush to
;; positive zero here. There's no hardware support doing this, but the ;; positive zero here. There's no hardware support doing this, but the
;; fast maths software library might. ;; fast maths software library might.
; V6M-FAST-NOT: .eabi_attribute 20 ; V6M-FAST-NOT: .eabi_attribute 20
; V6M-FAST-NOT: .eabi_attribute 21 ; V6M-FAST-NOT: .eabi_attribute 21
; V6M-FAST-NOT: .eabi_attribute 22 ; V6M-FAST-NOT: .eabi_attribute 22
; V6M-FAST: .eabi_attribute 23, 1 ; V6M-FAST: .eabi_attribute 23, 1
; V6SM: .arch armv6s-m
; V6SM: .eabi_attribute 6, 12
; V6SM-NOT: .eabi_attribute 7
; V6SM: .eabi_attribute 8, 0
; V6SM: .eabi_attribute 9, 1
; V6SM-NOT: .eabi_attribute 19
;; The default choice made by llc is for a V6M CPU without an FPU.
;; This is not an interesting detail, but for such CPUs, the default intention is to use
;; software floating-point support. The choice is not important for targets without
;; FPU support!
; V6SM: .eabi_attribute 20, 1
; V6SM: .eabi_attribute 21, 1
; V6SM-NOT: .eabi_attribute 22
; V6SM: .eabi_attribute 23, 3
; V6SM: .eabi_attribute 24, 1
; V6SM: .eabi_attribute 25, 1
; V6SM-NOT: .eabi_attribute 27
; V6SM-NOT: .eabi_attribute 28
; V6SM-NOT: .eabi_attribute 36
; V6SM: .eabi_attribute 38, 1
; V6SM-NOT: .eabi_attribute 42
; V6SM-NOT: .eabi_attribute 44
; V6SM-NOT: .eabi_attribute 68
; V6SM-FAST-NOT: .eabi_attribute 19
;; Despite the V6M CPU having no FPU by default, we chose to flush to
;; positive zero here. There's no hardware support doing this, but the
;; fast maths software library might.
; V6SM-FAST-NOT: .eabi_attribute 20
; V6SM-FAST-NOT: .eabi_attribute 21
; V6SM-FAST-NOT: .eabi_attribute 22
; V6SM-FAST: .eabi_attribute 23, 1
; ARM1156T2F-S: .cpu arm1156t2f-s ; ARM1156T2F-S: .cpu arm1156t2f-s
; ARM1156T2F-S: .eabi_attribute 6, 8 ; ARM1156T2F-S: .eabi_attribute 6, 8
; ARM1156T2F-S: .eabi_attribute 8, 1 ; ARM1156T2F-S: .eabi_attribute 8, 1
; ARM1156T2F-S: .eabi_attribute 9, 2 ; ARM1156T2F-S: .eabi_attribute 9, 2
; ARM1156T2F-S: .fpu vfpv2 ; ARM1156T2F-S: .fpu vfpv2
; ARM1156T2F-S-NOT: .eabi_attribute 19 ; ARM1156T2F-S-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance ;; We default to IEEE 754 compliance
; ARM1156T2F-S: .eabi_attribute 20, 1 ; ARM1156T2F-S: .eabi_attribute 20, 1
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;; V6 cores default to flush to positive zero (value 0). Note that value 2 is also equally ;; V6 cores default to flush to positive zero (value 0). Note that value 2 is also equally
;; valid for this core, it's an implementation defined question as to which of 0 and 2 you ;; valid for this core, it's an implementation defined question as to which of 0 and 2 you
;; select. LLVM historically picks 0. ;; select. LLVM historically picks 0.
; ARM1156T2F-S-FAST-NOT: .eabi_attribute 20 ; ARM1156T2F-S-FAST-NOT: .eabi_attribute 20
; ARM1156T2F-S-FAST-NOT: .eabi_attribute 21 ; ARM1156T2F-S-FAST-NOT: .eabi_attribute 21
; ARM1156T2F-S-FAST-NOT: .eabi_attribute 22 ; ARM1156T2F-S-FAST-NOT: .eabi_attribute 22
; ARM1156T2F-S-FAST: .eabi_attribute 23, 1 ; ARM1156T2F-S-FAST: .eabi_attribute 23, 1
; V7M: .arch armv7-m
; V7M: .eabi_attribute 6, 10 ; V7M: .eabi_attribute 6, 10
; V7M: .eabi_attribute 7, 77 ; V7M: .eabi_attribute 7, 77
; V7M: .eabi_attribute 8, 0 ; V7M: .eabi_attribute 8, 0
; V7M: .eabi_attribute 9, 2 ; V7M: .eabi_attribute 9, 2
; V7M-NOT: .eabi_attribute 19 ; V7M-NOT: .eabi_attribute 19
;; The default choice made by llc is for a V7M CPU without an FPU. ;; The default choice made by llc is for a V7M CPU without an FPU.
;; This is not an interesting detail, but for such CPUs, the default intention is to use ;; This is not an interesting detail, but for such CPUs, the default intention is to use
;; software floating-point support. The choice is not important for targets without ;; software floating-point support. The choice is not important for targets without
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;; preserving sign. This matches what the hardware would do in the ;; preserving sign. This matches what the hardware would do in the
;; architecture revision were to exist on the current target. ;; architecture revision were to exist on the current target.
; V7M-FAST: .eabi_attribute 20, 2 ; V7M-FAST: .eabi_attribute 20, 2
; V7M-FAST-NOT: .eabi_attribute 21 ; V7M-FAST-NOT: .eabi_attribute 21
; V7M-FAST-NOT: .eabi_attribute 22 ; V7M-FAST-NOT: .eabi_attribute 22
; V7M-FAST: .eabi_attribute 23, 1 ; V7M-FAST: .eabi_attribute 23, 1
; V7: .syntax unified ; V7: .syntax unified
; V7: .arch armv7
; V7: .eabi_attribute 6, 10 ; V7: .eabi_attribute 6, 10
; V7A-NOT: .eabi_attribute 7
; V7-NOT: .eabi_attribute 19 ; V7-NOT: .eabi_attribute 19
; V7-NOT: .fpu
;; In safe-maths mode we default to an IEEE 754 compliant choice. ;; In safe-maths mode we default to an IEEE 754 compliant choice.
; V7: .eabi_attribute 20, 1 ; V7: .eabi_attribute 20, 1
; V7: .eabi_attribute 21, 1 ; V7: .eabi_attribute 21, 1
; V7-NOT: .eabi_attribute 22 ; V7-NOT: .eabi_attribute 22
; V7: .eabi_attribute 23, 3 ; V7: .eabi_attribute 23, 3
; V7: .eabi_attribute 24, 1 ; V7: .eabi_attribute 24, 1
; V7: .eabi_attribute 25, 1 ; V7: .eabi_attribute 25, 1
; V7-NOT: .eabi_attribute 27 ; V7-NOT: .eabi_attribute 27
; V7-NOT: .eabi_attribute 28 ; V7-NOT: .eabi_attribute 28
; V7-NOT: .eabi_attribute 36 ; V7-NOT: .eabi_attribute 36
; V7: .eabi_attribute 38, 1 ; V7: .eabi_attribute 38, 1
; V7-NOT: .eabi_attribute 42 ; V7-NOT: .eabi_attribute 42
; V7-NOT: .eabi_attribute 44 ; V7-NOT: .eabi_attribute 44
; V7-NOT: .eabi_attribute 68 ; V7-NOT: .eabi_attribute 68
; V7A: .syntax unified
; V7A: .arch armv7-a
; V7A: .eabi_attribute 6, 10
; V7A: .eabi_attribute 7, 65
; V7A-NOT: .eabi_attribute 19
; V7A-NOT: .fpu
;; In safe-maths mode we default to an IEEE 754 compliant choice.
; V7A: .eabi_attribute 20, 1
; V7A: .eabi_attribute 21, 1
; V7A-NOT: .eabi_attribute 22
; V7A: .eabi_attribute 23, 3
; V7A: .eabi_attribute 24, 1
; V7A: .eabi_attribute 25, 1
; V7A-NOT: .eabi_attribute 27
; V7A-NOT: .eabi_attribute 28
; V7A-NOT: .eabi_attribute 36
; V7A: .eabi_attribute 38, 1
; V7A-NOT: .eabi_attribute 42
; V7A-NOT: .eabi_attribute 44
; V7A-NOT: .eabi_attribute 68
; V7R: .syntax unified
; V7R: .arch armv7-r
; V7R: .eabi_attribute 6, 10
; V7R: .eabi_attribute 7, 82
; V7R-NOT: .eabi_attribute 19
; V7R-NOT: .fpu
;; In safe-maths mode we default to an IEEE 754 compliant choice.
; V7R: .eabi_attribute 20, 1
; V7R: .eabi_attribute 21, 1
; V7R-NOT: .eabi_attribute 22
; V7R: .eabi_attribute 23, 3
; V7R: .eabi_attribute 24, 1
; V7R: .eabi_attribute 25, 1
; V7R-NOT: .eabi_attribute 27
; V7R-NOT: .eabi_attribute 28
; V7R-NOT: .eabi_attribute 36
; V7R: .eabi_attribute 38, 1
; V7R-NOT: .eabi_attribute 42
; V7R-NOT: .eabi_attribute 44
; V7R-NOT: .eabi_attribute 68
; V7-FAST-NOT: .eabi_attribute 19 ; V7-FAST-NOT: .eabi_attribute 19
;; The default CPU does have an FPU and it must be VFPv3 or better, so it flushes ;; The default CPU does have an FPU and it must be VFPv3 or better, so it flushes
;; denormals to zero preserving the sign. ;; denormals to zero preserving the sign.
; V7-FAST: .eabi_attribute 20, 2 ; V7-FAST: .eabi_attribute 20, 2
; V7-FAST-NOT: .eabi_attribute 21 ; V7-FAST-NOT: .eabi_attribute 21
; V7-FAST-NOT: .eabi_attribute 22 ; V7-FAST-NOT: .eabi_attribute 22
; V7-FAST: .eabi_attribute 23, 1 ; V7-FAST: .eabi_attribute 23, 1
; V7S: .syntax unified
; V7S: .cpu swift
; V7S: .eabi_attribute 6, 10
; V7S: .eabi_attribute 7, 65
; V7S-NOT: .eabi_attribute 19
; V7S: .fpu neon-vfpv4
;; In safe-maths mode we default to an IEEE 754 compliant choice.
; V7s: .eabi_attribute 20, 1
; V7S: .eabi_attribute 21, 1
; V7S-NOT: .eabi_attribute 22
; V7S: .eabi_attribute 23, 3
; V7S: .eabi_attribute 24, 1
; V7S: .eabi_attribute 25, 1
; V7S-NOT: .eabi_attribute 27
; V7S-NOT: .eabi_attribute 28
; V7S: .eabi_attribute 36, 1
; V7S: .eabi_attribute 38, 1
; V7S: .eabi_attribute 42, 1
; V7S: .eabi_attribute 44, 2
; V7S: .eabi_attribute 68, 1
; V8: .syntax unified ; V8: .syntax unified
; V8: .eabi_attribute 67, "2.09" ; V8: .eabi_attribute 67, "2.09"
; V8: .arch armv8-a
; V8: .eabi_attribute 6, 14 ; V8: .eabi_attribute 6, 14
; V8: .eabi_attribute 7, 65
; V8-NOT: .eabi_attribute 19 ; V8-NOT: .eabi_attribute 19
; V8: .eabi_attribute 20, 1 ; V8: .eabi_attribute 20, 1
; V8: .eabi_attribute 21, 1 ; V8: .eabi_attribute 21, 1
; V8-NOT: .eabi_attribute 22 ; V8-NOT: .eabi_attribute 22
; V8: .eabi_attribute 23, 3 ; V8: .eabi_attribute 23, 3
; V8-NOT: .eabi_attribute 44 ; V8-NOT: .eabi_attribute 44
; V8-FAST-NOT: .eabi_attribute 19 ; V8-FAST-NOT: .eabi_attribute 19
;; The default does have an FPU, and for V8-A, it flushes preserving sign. ;; The default does have an FPU, and for V8-A, it flushes preserving sign.
; V8-FAST: .eabi_attribute 20, 2 ; V8-FAST: .eabi_attribute 20, 2
; V8-FAST-NOT: .eabi_attribute 21 ; V8-FAST-NOT: .eabi_attribute 21
; V8-FAST-NOT: .eabi_attribute 22 ; V8-FAST-NOT: .eabi_attribute 22
; V8-FAST: .eabi_attribute 23, 1 ; V8-FAST: .eabi_attribute 23, 1
; Vt8: .syntax unified ; Vt8: .syntax unified
; Vt8: .eabi_attribute 6, 14 ; Vt8: .eabi_attribute 6, 14
; Vt8-NOT: .eabi_attribute 19 ; Vt8-NOT: .eabi_attribute 19
; Vt8: .eabi_attribute 20, 1 ; Vt8: .eabi_attribute 20, 1
; Vt8: .eabi_attribute 21, 1 ; Vt8: .eabi_attribute 21, 1
; Vt8-NOT: .eabi_attribute 22 ; Vt8-NOT: .eabi_attribute 22
; Vt8: .eabi_attribute 23, 3 ; Vt8: .eabi_attribute 23, 3
; V8-FPARMv8: .syntax unified ; V8-FPARMv8: .syntax unified
; V8-FPARMv8: .arch armv8-a
; V8-FPARMv8: .eabi_attribute 6, 14 ; V8-FPARMv8: .eabi_attribute 6, 14
; V8-FPARMv8: .fpu fp-armv8 ; V8-FPARMv8: .fpu fp-armv8
; V8-NEON: .syntax unified ; V8-NEON: .syntax unified
; V8-NEON: .arch armv8-a
; V8-NEON: .eabi_attribute 6, 14 ; V8-NEON: .eabi_attribute 6, 14
; V8-NEON: .fpu neon ; V8-NEON: .fpu neon
; V8-NEON: .eabi_attribute 12, 3 ; V8-NEON: .eabi_attribute 12, 3
; V8-FPARMv8-NEON: .syntax unified ; V8-FPARMv8-NEON: .syntax unified
; V8-FPARMv8-NEON: .arch armv8-a
; V8-FPARMv8-NEON: .eabi_attribute 6, 14 ; V8-FPARMv8-NEON: .eabi_attribute 6, 14
; V8-FPARMv8-NEON: .fpu neon-fp-armv8 ; V8-FPARMv8-NEON: .fpu neon-fp-armv8
; V8-FPARMv8-NEON: .eabi_attribute 12, 3 ; V8-FPARMv8-NEON: .eabi_attribute 12, 3
; V8-FPARMv8-NEON-CRYPTO: .syntax unified ; V8-FPARMv8-NEON-CRYPTO: .syntax unified
; V8-FPARMv8-NEON-CRYPTO: .arch armv8-a
; V8-FPARMv8-NEON-CRYPTO: .eabi_attribute 6, 14 ; V8-FPARMv8-NEON-CRYPTO: .eabi_attribute 6, 14
; V8-FPARMv8-NEON-CRYPTO: .fpu crypto-neon-fp-armv8 ; V8-FPARMv8-NEON-CRYPTO: .fpu crypto-neon-fp-armv8
; V8-FPARMv8-NEON-CRYPTO: .eabi_attribute 12, 3 ; V8-FPARMv8-NEON-CRYPTO: .eabi_attribute 12, 3
; Tag_CPU_unaligned_access ; Tag_CPU_unaligned_access
; NO-STRICT-ALIGN: .eabi_attribute 34, 1 ; NO-STRICT-ALIGN: .eabi_attribute 34, 1
; STRICT-ALIGN: .eabi_attribute 34, 0 ; STRICT-ALIGN: .eabi_attribute 34, 0
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; CORTEX-A72-FAST: .eabi_attribute 23, 1 ; CORTEX-A72-FAST: .eabi_attribute 23, 1
; GENERIC-FPU-VFPV3-FP16: .fpu vfpv3-fp16 ; GENERIC-FPU-VFPV3-FP16: .fpu vfpv3-fp16
; GENERIC-FPU-VFPV3-D16-FP16: .fpu vfpv3-d16-fp16 ; GENERIC-FPU-VFPV3-D16-FP16: .fpu vfpv3-d16-fp16
; GENERIC-FPU-VFPV3XD: .fpu vfpv3xd ; GENERIC-FPU-VFPV3XD: .fpu vfpv3xd
; GENERIC-FPU-VFPV3XD-FP16: .fpu vfpv3xd-fp16 ; GENERIC-FPU-VFPV3XD-FP16: .fpu vfpv3xd-fp16
; GENERIC-FPU-NEON-FP16: .fpu neon-fp16 ; GENERIC-FPU-NEON-FP16: .fpu neon-fp16
; GENERIC-ARMV8_1-A: .eabi_attribute 6, 14 ; V8_1A: .arch armv8.1-a
; GENERIC-ARMV8_1-A: .eabi_attribute 7, 65 ; V8_1A: .eabi_attribute 6, 14
; GENERIC-ARMV8_1-A: .eabi_attribute 8, 1 ; V8_1A: .eabi_attribute 7, 65
; GENERIC-ARMV8_1-A: .eabi_attribute 9, 2 ; V8_1A: .eabi_attribute 8, 1
; GENERIC-ARMV8_1-A: .fpu crypto-neon-fp-armv8 ; V8_1A: .eabi_attribute 9, 2
; GENERIC-ARMV8_1-A: .eabi_attribute 12, 4 ; V8_1A-NOT: .fpu
; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 19 ; V8_1A-NOT: .eabi_attribute 12
;; We default to IEEE 754 compliance ; V8_1A-NOT: .eabi_attribute 19
; GENERIC-ARMV8_1-A: .eabi_attribute 20, 1 ;; We default to IEEE 754 compliance
; GENERIC-ARMV8_1-A: .eabi_attribute 21, 1 ; V8_1A: .eabi_attribute 20, 1
; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 22 ; V8_1A: .eabi_attribute 21, 1
; GENERIC-ARMV8_1-A: .eabi_attribute 23, 3 ; V8_1A-NOT: .eabi_attribute 22
; GENERIC-ARMV8_1-A: .eabi_attribute 24, 1 ; V8_1A: .eabi_attribute 23, 3
; GENERIC-ARMV8_1-A: .eabi_attribute 25, 1 ; V8_1A: .eabi_attribute 24, 1
; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 27 ; V8_1A: .eabi_attribute 25, 1
; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 28 ; V8_1A-NOT: .eabi_attribute 27
; GENERIC-ARMV8_1-A: .eabi_attribute 36, 1 ; V8_1A-NOT: .eabi_attribute 28
; GENERIC-ARMV8_1-A: .eabi_attribute 38, 1 ; V8_1A-NOT: .eabi_attribute 36, 1
; GENERIC-ARMV8_1-A: .eabi_attribute 42, 1 ; V8_1A: .eabi_attribute 38, 1
; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 44 ; V8_1A: .eabi_attribute 42, 1
; GENERIC-ARMV8_1-A: .eabi_attribute 68, 3 ; V8_1A-NOT: .eabi_attribute 44
; V8_1A: .eabi_attribute 68, 3
; GENERIC-ARMV8_1-A-FAST-NOT: .eabi_attribute 19
;; GENERIC-ARMV8_1-A has the ARMv8 FP unit, which always flushes preserving sign. ; V8_1A-FPARMv8: .arch armv8.1-a
; GENERIC-ARMV8_1-A-FAST: .eabi_attribute 20, 2 ; V8_1A-FPARMv8: .eabi_attribute 6, 14
; GENERIC-ARMV8_1-A-FAST-NOT: .eabi_attribute 21 ; V8_1A-FPARMv8: .eabi_attribute 7, 65
; GENERIC-ARMV8_1-A-FAST-NOT: .eabi_attribute 22 ; V8_1A-FPARMv8: .eabi_attribute 8, 1
; GENERIC-ARMV8_1-A-FAST: .eabi_attribute 23, 1 ; V8_1A-FPARMv8: .eabi_attribute 9, 2
; V8_1A-FPARMv8: .fpu fp-armv8
;; Tag_Advanced_SIMD_arch
; V8_1A-FPARMv8-NOT: .eabi_attribute 12, 4
; V8_1A-FPARMv8-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; V8_1A-FPARMv8: .eabi_attribute 20, 1
; V8_1A-FPARMv8: .eabi_attribute 21, 1
; V8_1A-FPARMv8-NOT: .eabi_attribute 22
; V8_1A-FPARMv8: .eabi_attribute 23, 3
; V8_1A-FPARMv8: .eabi_attribute 24, 1
; V8_1A-FPARMv8: .eabi_attribute 25, 1
; V8_1A-FPARMv8-NOT: .eabi_attribute 27
; V8_1A-FPARMv8-NOT: .eabi_attribute 28
; V8_1A-FPARMv8: .eabi_attribute 36, 1
; V8_1A-FPARMv8: .eabi_attribute 38, 1
; V8_1A-FPARMv8: .eabi_attribute 42, 1
; V8_1A-FPARMv8-NOT: .eabi_attribute 44
; V8_1A-FPARMv8: .eabi_attribute 68, 3
; V8_1A-NEON: .arch armv8.1-a
; V8_1A-NEON: .eabi_attribute 6, 14
; V8_1A-NEON: .eabi_attribute 7, 65
; V8_1A-NEON: .eabi_attribute 8, 1
; V8_1A-NEON: .eabi_attribute 9, 2
; V8_1A-NEON: .fpu neon
;; Tag_Advanced_SIMD_arch
; V8_1A-NEON: .eabi_attribute 12, 4
; V8_1A-NEON-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; V8_1A-NEON: .eabi_attribute 20, 1
; V8_1A-NEON: .eabi_attribute 21, 1
; V8_1A-NEON-NOT: .eabi_attribute 22
; V8_1A-NEON: .eabi_attribute 23, 3
; V8_1A-NEON: .eabi_attribute 24, 1
; V8_1A-NEON: .eabi_attribute 25, 1
; V8_1A-NEON-NOT: .eabi_attribute 27
; V8_1A-NEON-NOT: .eabi_attribute 28
; V8_1A-NEON-NOT: .eabi_attribute 36, 1
; V8_1A-NEON: .eabi_attribute 38, 1
; V8_1A-NEON: .eabi_attribute 42, 1
; V8_1A-NEON-NOT: .eabi_attribute 44
; V8_1A-NEON: .eabi_attribute 68, 3
; V8_1A-FPARMv8-NEON: .arch armv8.1-a
; V8_1A-FPARMv8-NEON: .eabi_attribute 6, 14
; V8_1A-FPARMv8-NEON: .eabi_attribute 7, 65
; V8_1A-FPARMv8-NEON: .eabi_attribute 8, 1
; V8_1A-FPARMv8-NEON: .eabi_attribute 9, 2
; V8_1A-FPARMv8-NEON: .fpu neon-fp-armv8
;; Tag_Advanced_SIMD_arch
; V8_1A-FPARMv8-NEON: .eabi_attribute 12, 4
; V8_1A-FPARMv8-NEON-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; V8_1A-FPARMv8-NEON: .eabi_attribute 20, 1
; V8_1A-FPARMv8-NEON: .eabi_attribute 21, 1
; V8_1A-FPARMv8-NEON-NOT: .eabi_attribute 22
; V8_1A-FPARMv8-NEON: .eabi_attribute 23, 3
; V8_1A-FPARMv8-NEON: .eabi_attribute 24, 1
; V8_1A-FPARMv8-NEON: .eabi_attribute 25, 1
; V8_1A-FPARMv8-NEON-NOT: .eabi_attribute 27
; V8_1A-FPARMv8-NEON-NOT: .eabi_attribute 28
; V8_1A-FPARMv8-NEON: .eabi_attribute 36, 1
; V8_1A-FPARMv8-NEON: .eabi_attribute 38, 1
; V8_1A-FPARMv8-NEON: .eabi_attribute 42, 1
; V8_1A-FPARMv8-NEON-NOT: .eabi_attribute 44
; V8_1A-FPARMv8-NEON: .eabi_attribute 68, 3
; V8_1A-FPARMv8-NEON-CRYPTO: .arch armv8.1-a
; V8_1A-FPARMv8-NEON-CRYPTO: .eabi_attribute 6, 14
; V8_1A-FPARMv8-NEON-CRYPTO: .eabi_attribute 7, 65
; V8_1A-FPARMv8-NEON-CRYPTO: .eabi_attribute 8, 1
; V8_1A-FPARMv8-NEON-CRYPTO: .eabi_attribute 9, 2
; V8_1A-FPARMv8-NEON-CRYPTO: .fpu crypto-neon-fp-armv8
;; Tag_Advanced_SIMD_arch
; V8_1A-FPARMv8-NEON-CRYPTO: .eabi_attribute 12, 4
; V8_1A-FPARMv8-NEON-CRYPTO-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; V8_1A-FPARMv8-NEON-CRYPTO: .eabi_attribute 20, 1
; V8_1A-FPARMv8-NEON-CRYPTO: .eabi_attribute 21, 1
; V8_1A-FPARMv8-NEON-CRYPTO-NOT: .eabi_attribute 22
; V8_1A-FPARMv8-NEON-CRYPTO: .eabi_attribute 23, 3
; V8_1A-FPARMv8-NEON-CRYPTO: .eabi_attribute 24, 1
; V8_1A-FPARMv8-NEON-CRYPTO: .eabi_attribute 25, 1
; V8_1A-FPARMv8-NEON-CRYPTO-NOT: .eabi_attribute 27
; V8_1A-FPARMv8-NEON-CRYPTO-NOT: .eabi_attribute 28
; V8_1A-FPARMv8-NEON-CRYPTO: .eabi_attribute 36, 1
; V8_1A-FPARMv8-NEON-CRYPTO: .eabi_attribute 38, 1
; V8_1A-FPARMv8-NEON-CRYPTO: .eabi_attribute 42, 1
; V8_1A-FPARMv8-NEON-CRYPTO-NOT: .eabi_attribute 44
; V8_1A-FPARMv8-NEON-CRYPTO: .eabi_attribute 68, 3
; V8_1A-FAST-NOT: .eabi_attribute 19
;; V8_1A has the ARMv8 FP unit, which always flushes preserving sign.
; V8_1A-FAST: .eabi_attribute 20, 2
; V8_1A-FAST-NOT: .eabi_attribute 21
; V8_1A-FAST-NOT: .eabi_attribute 22
; V8_1A-FAST: .eabi_attribute 23, 1
; RELOC-PIC: .eabi_attribute 15, 1 ; RELOC-PIC: .eabi_attribute 15, 1
; RELOC-PIC: .eabi_attribute 16, 1 ; RELOC-PIC: .eabi_attribute 16, 1
; RELOC-PIC: .eabi_attribute 17, 2 ; RELOC-PIC: .eabi_attribute 17, 2
; RELOC-OTHER: .eabi_attribute 17, 1 ; RELOC-OTHER: .eabi_attribute 17, 1
; PCS-R9-USE: .eabi_attribute 14, 0 ; PCS-R9-USE: .eabi_attribute 14, 0
; PCS-R9-RESERVE: .eabi_attribute 14, 3 ; PCS-R9-RESERVE: .eabi_attribute 14, 3
define i32 @f(i64 %z) { define i32 @f(i64 %z) {
ret i32 0 ret i32 0
} }

test/CodeGen/ARM/call_nolink.ll

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} }
define void @PR15520(void ()* %fn) { define void @PR15520(void ()* %fn) {
call void %fn() call void %fn()
ret void ret void
; CHECK-LABEL: PR15520: ; CHECK-LABEL: PR15520:
; CHECK: mov lr, pc ; CHECK: mov lr, pc
; CHECK: mov pc, r0 ; CHECK: bx r0
} }

test/CodeGen/ARM/constant-islands.ll

; RUN: llc -mtriple=thumbv7-linux-gnueabihf -O0 -fast-isel=0 -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv7-linux-gnueabihf -mattr=+neon -O0 -fast-isel=0 -o - %s | FileCheck %s
define void @test_no_duplicate_branches(float %in) { define void @test_no_duplicate_branches(float %in) {
; CHECK-LABEL: test_no_duplicate_branches: ; CHECK-LABEL: test_no_duplicate_branches:
; CHECK: vldr {{s[0-9]+}}, [[CONST:\.LCPI[0-9]+_[0-9]+]] ; CHECK: vldr {{s[0-9]+}}, [[CONST:\.LCPI[0-9]+_[0-9]+]]
; CHECK: b .LBB ; CHECK: b .LBB
; CHECK-NOT: b .LBB ; CHECK-NOT: b .LBB
; CHECK: [[CONST]]: ; CHECK: [[CONST]]:
; CHECK-NEXT: .long 1150963712 ; CHECK-NEXT: .long 1150963712
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test/CodeGen/ARM/crc32.ll

; RUN: llc -mtriple=thumbv8 -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv8 -mattr=+crc -o - %s | FileCheck %s
define i32 @test_crc32b(i32 %cur, i8 %next) { define i32 @test_crc32b(i32 %cur, i8 %next) {
; CHECK-LABEL: test_crc32b: ; CHECK-LABEL: test_crc32b:
; CHECK: crc32b r0, r0, r1 ; CHECK: crc32b r0, r0, r1
%bits = zext i8 %next to i32 %bits = zext i8 %next to i32
%val = call i32 @llvm.arm.crc32b(i32 %cur, i32 %bits) %val = call i32 @llvm.arm.crc32b(i32 %cur, i32 %bits)
ret i32 %val ret i32 %val
} }
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test/CodeGen/ARM/dagcombine-anyexttozeroext.ll

; RUN: llc -mtriple armv7 %s -o - | FileCheck %s ; RUN: llc -mtriple armv7 -mattr=+neon %s -o - | FileCheck %s
; CHECK-LABEL: f: ; CHECK-LABEL: f:
define float @f(<4 x i16>* nocapture %in) { define float @f(<4 x i16>* nocapture %in) {
; CHECK: vld1 ; CHECK: vld1
; CHECK: vmovl.u16 ; CHECK: vmovl.u16
; CHECK-NOT: vand ; CHECK-NOT: vand
%1 = load <4 x i16>, <4 x i16>* %in %1 = load <4 x i16>, <4 x i16>* %in
; CHECK: vcvt.f32.u32 ; CHECK: vcvt.f32.u32
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test/CodeGen/ARM/dagcombine-concatvector.ll

; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 -mcpu=generic | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE ; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 -mcpu=generic | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
; RUN: llc < %s -mtriple=thumbeb -target-abi apcs -mattr=v7,neon | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE ; RUN: llc < %s -mtriple=thumbeb -target-abi apcs -mattr=+v7,+neon | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
; PR15525 ; PR15525
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: ldr.w [[REG:r[0-9]+]], [sp] ; CHECK: ldr.w [[REG:r[0-9]+]], [sp]
; CHECK-LE-NEXT: vmov {{d[0-9]+}}, r1, r2 ; CHECK-LE-NEXT: vmov {{d[0-9]+}}, r1, r2
; CHECK-LE-NEXT: vmov {{d[0-9]+}}, r3, [[REG]] ; CHECK-LE-NEXT: vmov {{d[0-9]+}}, r3, [[REG]]
; CHECK-BE-NEXT: vmov {{d[0-9]+}}, r2, r1 ; CHECK-BE-NEXT: vmov {{d[0-9]+}}, r2, r1
; CHECK-BE: vmov {{d[0-9]+}}, [[REG]], r3 ; CHECK-BE: vmov {{d[0-9]+}}, [[REG]], r3
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test/CodeGen/ARM/data-in-code-annotations.ll

; RUN: llc < %s -mtriple=armv7-apple-darwin -arm-atomic-cfg-tidy=0 | FileCheck %s ; RUN: llc < %s -mtriple=armv7-apple-darwin -mattr=+neon -arm-atomic-cfg-tidy=0 | FileCheck %s
define double @f1() nounwind { define double @f1() nounwind {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: .data_region ; CHECK: .data_region
; CHECK: .long 1413754129 ; CHECK: .long 1413754129
; CHECK: .long 1074340347 ; CHECK: .long 1074340347
; CHECK: .end_data_region ; CHECK: .end_data_region
ret double 0x400921FB54442D11 ret double 0x400921FB54442D11
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test/CodeGen/ARM/debug-frame.ll

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; RUN: llc -mtriple arm-unknown-linux-gnueabi \ ; RUN: llc -mtriple arm-unknown-linux-gnueabi \
; RUN: -disable-fp-elim -filetype=asm -o - %s \ ; RUN: -disable-fp-elim -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-FP ; RUN: | FileCheck %s --check-prefix=CHECK-FP
; RUN: llc -mtriple arm-unknown-linux-gnueabi \ ; RUN: llc -mtriple arm-unknown-linux-gnueabi \
; RUN: -filetype=asm -o - %s \ ; RUN: -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-FP-ELIM ; RUN: | FileCheck %s --check-prefix=CHECK-FP-ELIM
; RUN: llc -mtriple armv7-unknown-linux-gnueabi \ ; RUN: llc -mtriple armv7-unknown-linux-gnueabi -mattr=+neon \
; RUN: -disable-fp-elim -filetype=asm -o - %s \ ; RUN: -disable-fp-elim -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP ; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP
; RUN: llc -mtriple armv7-unknown-linux-gnueabi \ ; RUN: llc -mtriple armv7-unknown-linux-gnueabi -mattr=+neon \
; RUN: -filetype=asm -o - %s \ ; RUN: -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP-ELIM ; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP-ELIM
; RUN: llc -mtriple thumb-unknown-linux-gnueabi \ ; RUN: llc -mtriple thumb-unknown-linux-gnueabi \
; RUN: -disable-fp-elim -filetype=asm -o - %s \ ; RUN: -disable-fp-elim -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-THUMB-FP ; RUN: | FileCheck %s --check-prefix=CHECK-THUMB-FP
; RUN: llc -mtriple thumb-unknown-linux-gnueabi \ ; RUN: llc -mtriple thumb-unknown-linux-gnueabi \
; RUN: -filetype=asm -o - %s \ ; RUN: -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-THUMB-FP-ELIM ; RUN: | FileCheck %s --check-prefix=CHECK-THUMB-FP-ELIM
; RUN: llc -mtriple thumbv7-unknown-linux-gnueabi \ ; RUN: llc -mtriple thumbv7-unknown-linux-gnueabi -mattr=+neon \
; RUN: -disable-fp-elim -filetype=asm -o - %s \ ; RUN: -disable-fp-elim -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-THUMB-V7-FP ; RUN: | FileCheck %s --check-prefix=CHECK-THUMB-V7-FP
; RUN: llc -mtriple thumbv7-unknown-linux-gnueabi \ ; RUN: llc -mtriple thumbv7-unknown-linux-gnueabi -mattr=+neon \
; RUN: -filetype=asm -o - %s \ ; RUN: -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-THUMB-V7-FP-ELIM ; RUN: | FileCheck %s --check-prefix=CHECK-THUMB-V7-FP-ELIM
; RUN: llc -mtriple thumbv7-unknown-linux-gnueabi \ ; RUN: llc -mtriple thumbv7-unknown-linux-gnueabi -mattr=+neon \
; RUN: -disable-fp-elim -no-integrated-as -filetype=asm -o - %s \ ; RUN: -disable-fp-elim -no-integrated-as -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-THUMB-V7-FP-NOIAS ; RUN: | FileCheck %s --check-prefix=CHECK-THUMB-V7-FP-NOIAS
;------------------------------------------------------------------------------- ;-------------------------------------------------------------------------------
; Test 1 ; Test 1
;------------------------------------------------------------------------------- ;-------------------------------------------------------------------------------
; This is the LLVM assembly generated from following C++ code: ; This is the LLVM assembly generated from following C++ code:
; ;
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; CHECK-FP: .cfi_startproc ; CHECK-FP: .cfi_startproc
; CHECK-FP: push {r11, lr} ; CHECK-FP: push {r11, lr}
; CHECK-FP: .cfi_def_cfa_offset 8 ; CHECK-FP: .cfi_def_cfa_offset 8
; CHECK-FP: .cfi_offset lr, -4 ; CHECK-FP: .cfi_offset lr, -4
; CHECK-FP: .cfi_offset r11, -8 ; CHECK-FP: .cfi_offset r11, -8
; CHECK-FP: mov r11, sp ; CHECK-FP: mov r11, sp
; CHECK-FP: .cfi_def_cfa_register r11 ; CHECK-FP: .cfi_def_cfa_register r11
; CHECK-FP: pop {r11, lr} ; CHECK-FP: pop {r11, lr}
; CHECK-FP: mov pc, lr ; CHECK-FP: bx lr
; CHECK-FP: .cfi_endproc ; CHECK-FP: .cfi_endproc
; CHECK-FP-ELIM-LABEL: test2: ; CHECK-FP-ELIM-LABEL: test2:
; CHECK-FP-ELIM: .cfi_startproc ; CHECK-FP-ELIM: .cfi_startproc
; CHECK-FP-ELIM: push {r11, lr} ; CHECK-FP-ELIM: push {r11, lr}
; CHECK-FP-ELIM: .cfi_def_cfa_offset 8 ; CHECK-FP-ELIM: .cfi_def_cfa_offset 8
; CHECK-FP-ELIM: .cfi_offset lr, -4 ; CHECK-FP-ELIM: .cfi_offset lr, -4
; CHECK-FP-ELIM: .cfi_offset r11, -8 ; CHECK-FP-ELIM: .cfi_offset r11, -8
; CHECK-FP-ELIM: pop {r11, lr} ; CHECK-FP-ELIM: pop {r11, lr}
; CHECK-FP-ELIM: mov pc, lr ; CHECK-FP-ELIM: bx lr
; CHECK-FP-ELIM: .cfi_endproc ; CHECK-FP-ELIM: .cfi_endproc
; CHECK-V7-FP-LABEL: test2: ; CHECK-V7-FP-LABEL: test2:
; CHECK-V7-FP: .cfi_startproc ; CHECK-V7-FP: .cfi_startproc
; CHECK-V7-FP: push {r11, lr} ; CHECK-V7-FP: push {r11, lr}
; CHECK-V7-FP: .cfi_def_cfa_offset 8 ; CHECK-V7-FP: .cfi_def_cfa_offset 8
; CHECK-V7-FP: .cfi_offset lr, -4 ; CHECK-V7-FP: .cfi_offset lr, -4
; CHECK-V7-FP: .cfi_offset r11, -8 ; CHECK-V7-FP: .cfi_offset r11, -8
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; CHECK-THUMB-FP-LABEL: test2: ; CHECK-THUMB-FP-LABEL: test2:
; CHECK-THUMB-FP: .cfi_startproc ; CHECK-THUMB-FP: .cfi_startproc
; CHECK-THUMB-FP: push {r7, lr} ; CHECK-THUMB-FP: push {r7, lr}
; CHECK-THUMB-FP: .cfi_def_cfa_offset 8 ; CHECK-THUMB-FP: .cfi_def_cfa_offset 8
; CHECK-THUMB-FP: .cfi_offset lr, -4 ; CHECK-THUMB-FP: .cfi_offset lr, -4
; CHECK-THUMB-FP: .cfi_offset r7, -8 ; CHECK-THUMB-FP: .cfi_offset r7, -8
; CHECK-THUMB-FP: add r7, sp, #0 ; CHECK-THUMB-FP: add r7, sp, #0
; CHECK-THUMB-FP: .cfi_def_cfa_register r7 ; CHECK-THUMB-FP: .cfi_def_cfa_register r7
; CHECK-THUMB-FP: pop {r7, pc} ; CHECK-THUMB-FP: pop {r7}
; CHECK-THUMB-FP: pop {pc}
; CHECK-THUMB-FP: .cfi_endproc ; CHECK-THUMB-FP: .cfi_endproc
; CHECK-THUMB-FP-ELIM-LABEL: test2: ; CHECK-THUMB-FP-ELIM-LABEL: test2:
; CHECK-THUMB-FP-ELIM: .cfi_startproc ; CHECK-THUMB-FP-ELIM: .cfi_startproc
; CHECK-THUMB-FP-ELIM: push {r7, lr} ; CHECK-THUMB-FP-ELIM: push {r7, lr}
; CHECK-THUMB-FP-ELIM: .cfi_def_cfa_offset 8 ; CHECK-THUMB-FP-ELIM: .cfi_def_cfa_offset 8
; CHECK-THUMB-FP-ELIM: .cfi_offset lr, -4 ; CHECK-THUMB-FP-ELIM: .cfi_offset lr, -4
; CHECK-THUMB-FP-ELIM: .cfi_offset r7, -8 ; CHECK-THUMB-FP-ELIM: .cfi_offset r7, -8
; CHECK-THUMB-FP-ELIM: pop {r7, pc} ; CHECK-THUMB-FP-ELIM: pop {r7}
; CHECK-THUMB-FP-ELIM: pop {pc}
; CHECK-THUMB-FP-ELIM: .cfi_endproc ; CHECK-THUMB-FP-ELIM: .cfi_endproc
; CHECK-THUMB-V7-FP-LABEL: test2: ; CHECK-THUMB-V7-FP-LABEL: test2:
; CHECK-THUMB-V7-FP: .cfi_startproc ; CHECK-THUMB-V7-FP: .cfi_startproc
; CHECK-THUMB-V7-FP: push {r7, lr} ; CHECK-THUMB-V7-FP: push {r7, lr}
; CHECK-THUMB-V7-FP: .cfi_def_cfa_offset 8 ; CHECK-THUMB-V7-FP: .cfi_def_cfa_offset 8
; CHECK-THUMB-V7-FP: .cfi_offset lr, -4 ; CHECK-THUMB-V7-FP: .cfi_offset lr, -4
; CHECK-THUMB-V7-FP: .cfi_offset r7, -8 ; CHECK-THUMB-V7-FP: .cfi_offset r7, -8
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; CHECK-FP: .cfi_def_cfa_offset 16 ; CHECK-FP: .cfi_def_cfa_offset 16
; CHECK-FP: .cfi_offset lr, -4 ; CHECK-FP: .cfi_offset lr, -4
; CHECK-FP: .cfi_offset r11, -8 ; CHECK-FP: .cfi_offset r11, -8
; CHECK-FP: .cfi_offset r5, -12 ; CHECK-FP: .cfi_offset r5, -12
; CHECK-FP: .cfi_offset r4, -16 ; CHECK-FP: .cfi_offset r4, -16
; CHECK-FP: add r11, sp, #8 ; CHECK-FP: add r11, sp, #8
; CHECK-FP: .cfi_def_cfa r11, 8 ; CHECK-FP: .cfi_def_cfa r11, 8
; CHECK-FP: pop {r4, r5, r11, lr} ; CHECK-FP: pop {r4, r5, r11, lr}
; CHECK-FP: mov pc, lr ; CHECK-FP: bx lr
; CHECK-FP: .cfi_endproc ; CHECK-FP: .cfi_endproc
; CHECK-FP-ELIM-LABEL: test3: ; CHECK-FP-ELIM-LABEL: test3:
; CHECK-FP-ELIM: .cfi_startproc ; CHECK-FP-ELIM: .cfi_startproc
; CHECK-FP-ELIM: push {r4, r5, r11, lr} ; CHECK-FP-ELIM: push {r4, r5, r11, lr}
; CHECK-FP-ELIM: .cfi_def_cfa_offset 16 ; CHECK-FP-ELIM: .cfi_def_cfa_offset 16
; CHECK-FP-ELIM: .cfi_offset lr, -4 ; CHECK-FP-ELIM: .cfi_offset lr, -4
; CHECK-FP-ELIM: .cfi_offset r11, -8 ; CHECK-FP-ELIM: .cfi_offset r11, -8
; CHECK-FP-ELIM: .cfi_offset r5, -12 ; CHECK-FP-ELIM: .cfi_offset r5, -12
; CHECK-FP-ELIM: .cfi_offset r4, -16 ; CHECK-FP-ELIM: .cfi_offset r4, -16
; CHECK-FP-ELIM: pop {r4, r5, r11, lr} ; CHECK-FP-ELIM: pop {r4, r5, r11, lr}
; CHECK-FP-ELIM: mov pc, lr ; CHECK-FP-ELIM: bx lr
; CHECK-FP-ELIM: .cfi_endproc ; CHECK-FP-ELIM: .cfi_endproc
; CHECK-V7-FP-LABEL: test3: ; CHECK-V7-FP-LABEL: test3:
; CHECK-V7-FP: .cfi_startproc ; CHECK-V7-FP: .cfi_startproc
; CHECK-V7-FP: push {r4, r5, r11, lr} ; CHECK-V7-FP: push {r4, r5, r11, lr}
; CHECK-V7-FP: .cfi_def_cfa_offset 16 ; CHECK-V7-FP: .cfi_def_cfa_offset 16
; CHECK-V7-FP: .cfi_offset lr, -4 ; CHECK-V7-FP: .cfi_offset lr, -4
; CHECK-V7-FP: .cfi_offset r11, -8 ; CHECK-V7-FP: .cfi_offset r11, -8
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; CHECK-THUMB-FP: push {r4, r5, r7, lr} ; CHECK-THUMB-FP: push {r4, r5, r7, lr}
; CHECK-THUMB-FP: .cfi_def_cfa_offset 16 ; CHECK-THUMB-FP: .cfi_def_cfa_offset 16
; CHECK-THUMB-FP: .cfi_offset lr, -4 ; CHECK-THUMB-FP: .cfi_offset lr, -4
; CHECK-THUMB-FP: .cfi_offset r7, -8 ; CHECK-THUMB-FP: .cfi_offset r7, -8
; CHECK-THUMB-FP: .cfi_offset r5, -12 ; CHECK-THUMB-FP: .cfi_offset r5, -12
; CHECK-THUMB-FP: .cfi_offset r4, -16 ; CHECK-THUMB-FP: .cfi_offset r4, -16
; CHECK-THUMB-FP: add r7, sp, #8 ; CHECK-THUMB-FP: add r7, sp, #8
; CHECK-THUMB-FP: .cfi_def_cfa r7, 8 ; CHECK-THUMB-FP: .cfi_def_cfa r7, 8
; CHECK-THUMB-FP: pop {r4, r5, r7, pc} ; CHECK-THUMB-FP: pop {r4, r5, r7}
; CHECK-THUMB-FP: pop {pc}
; CHECK-THUMB-FP: .cfi_endproc ; CHECK-THUMB-FP: .cfi_endproc
; CHECK-THUMB-FP-ELIM-LABEL: test3: ; CHECK-THUMB-FP-ELIM-LABEL: test3:
; CHECK-THUMB-FP-ELIM: .cfi_startproc ; CHECK-THUMB-FP-ELIM: .cfi_startproc
; CHECK-THUMB-FP-ELIM: push {r4, r5, r7, lr} ; CHECK-THUMB-FP-ELIM: push {r4, r5, r7, lr}
; CHECK-THUMB-FP-ELIM: .cfi_def_cfa_offset 16 ; CHECK-THUMB-FP-ELIM: .cfi_def_cfa_offset 16
; CHECK-THUMB-FP-ELIM: .cfi_offset lr, -4 ; CHECK-THUMB-FP-ELIM: .cfi_offset lr, -4
; CHECK-THUMB-FP-ELIM: .cfi_offset r7, -8 ; CHECK-THUMB-FP-ELIM: .cfi_offset r7, -8
; CHECK-THUMB-FP-ELIM: .cfi_offset r5, -12 ; CHECK-THUMB-FP-ELIM: .cfi_offset r5, -12
; CHECK-THUMB-FP-ELIM: .cfi_offset r4, -16 ; CHECK-THUMB-FP-ELIM: .cfi_offset r4, -16
; CHECK-THUMB-FP-ELIM: pop {r4, r5, r7, pc} ; CHECK-THUMB-FP-ELIM: pop {r4, r5, r7}
; CHECK-THUMB-FP-ELIM: pop {pc}
; CHECK-THUMB-FP-ELIM: .cfi_endproc ; CHECK-THUMB-FP-ELIM: .cfi_endproc
; CHECK-THUMB-V7-FP-LABEL: test3: ; CHECK-THUMB-V7-FP-LABEL: test3:
; CHECK-THUMB-V7-FP: .cfi_startproc ; CHECK-THUMB-V7-FP: .cfi_startproc
; CHECK-THUMB-V7-FP: push {r4, r5, r7, lr} ; CHECK-THUMB-V7-FP: push {r4, r5, r7, lr}
; CHECK-THUMB-V7-FP: .cfi_def_cfa_offset 16 ; CHECK-THUMB-V7-FP: .cfi_def_cfa_offset 16
; CHECK-THUMB-V7-FP: .cfi_offset lr, -4 ; CHECK-THUMB-V7-FP: .cfi_offset lr, -4
; CHECK-THUMB-V7-FP: .cfi_offset r7, -8 ; CHECK-THUMB-V7-FP: .cfi_offset r7, -8
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;------------------------------------------------------------------------------- ;-------------------------------------------------------------------------------
define void @test4() nounwind { define void @test4() nounwind {
entry: entry:
ret void ret void
} }
; CHECK-FP-LABEL: test4: ; CHECK-FP-LABEL: test4:
; CHECK-FP: mov pc, lr ; CHECK-FP: bx lr
; CHECK-FP-NOT: .cfi_def_cfa_offset ; CHECK-FP-NOT: .cfi_def_cfa_offset
; CHECK-FP-ELIM-LABEL: test4: ; CHECK-FP-ELIM-LABEL: test4:
; CHECK-FP-ELIM: mov pc, lr ; CHECK-FP-ELIM: bx lr
; CHECK-FP-ELIM-NOT: .cfi_def_cfa_offset ; CHECK-FP-ELIM-NOT: .cfi_def_cfa_offset
; CHECK-V7-FP-LABEL: test4: ; CHECK-V7-FP-LABEL: test4:
; CHECK-V7-FP: bx lr ; CHECK-V7-FP: bx lr
; CHECK-V7-FP-NOT: .cfi_def_cfa_offset ; CHECK-V7-FP-NOT: .cfi_def_cfa_offset
; CHECK-V7-FP-ELIM-LABEL: test4: ; CHECK-V7-FP-ELIM-LABEL: test4:
; CHECK-V7-FP-ELIM: bx lr ; CHECK-V7-FP-ELIM: bx lr
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test/CodeGen/ARM/debug-info-branch-folding.ll

; RUN: llc < %s - | FileCheck %s ; RUN: llc -mattr=+neon < %s - | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
target triple = "thumbv7-apple-macosx10.6.7" target triple = "thumbv7-apple-macosx10.6.7"
;CHECK: vadd.f32 q4, q8, q8 ;CHECK: vadd.f32 q4, q8, q8
;CHECK-NEXT: Ltmp1 ;CHECK-NEXT: Ltmp1
;CHECK-NEXT: LBB0_1 ;CHECK-NEXT: LBB0_1
;CHECK:@DEBUG_VALUE: x <- Q4{{$}} ;CHECK:@DEBUG_VALUE: x <- Q4{{$}}
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test/CodeGen/ARM/debug-info-d16-reg.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc -mattr=+neon < %s | FileCheck %s
; Radar 9309221 ; Radar 9309221
; Test dwarf reg no for d16 ; Test dwarf reg no for d16
;CHECK: DW_OP_regx ;CHECK: DW_OP_regx
;CHECK-NEXT: 272 ;CHECK-NEXT: 272
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32"
target triple = "thumbv7-apple-darwin10" target triple = "thumbv7-apple-darwin10"
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test/CodeGen/ARM/debug-info-qreg.ll

; RUN: llc < %s - | FileCheck %s ; RUN: llc -mattr=+neon < %s - | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
target triple = "thumbv7-apple-macosx10.6.7" target triple = "thumbv7-apple-macosx10.6.7"
;CHECK: sub-register DW_OP_regx ;CHECK: sub-register DW_OP_regx
;CHECK-NEXT: 256 ;CHECK-NEXT: 256
;CHECK-NEXT: DW_OP_piece ;CHECK-NEXT: DW_OP_piece
;CHECK-NEXT: 8 ;CHECK-NEXT: 8
;CHECK-NEXT: sub-register DW_OP_regx ;CHECK-NEXT: sub-register DW_OP_regx
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test/CodeGen/ARM/debug-info-s16-reg.ll

; RUN: llc < %s - | FileCheck %s ; RUN: llc -mattr=+neon < %s - | FileCheck %s
; Radar 9309221 ; Radar 9309221
; Test dwarf reg no for s16 ; Test dwarf reg no for s16
;CHECK: super-register DW_OP_regx ;CHECK: super-register DW_OP_regx
;CHECK-NEXT: 264 ;CHECK-NEXT: 264
;CHECK-NEXT: DW_OP_piece ;CHECK-NEXT: DW_OP_piece
;CHECK-NEXT: 4 ;CHECK-NEXT: 4
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
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test/CodeGen/ARM/debug-info-sreg2.ll

; RUN: llc < %s - -filetype=obj | llvm-dwarfdump -debug-dump=loc - | FileCheck %s ; RUN: llc -mattr=+neon < %s - -filetype=obj | llvm-dwarfdump -debug-dump=loc - | FileCheck %s
; Radar 9376013 ; Radar 9376013
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
target triple = "thumbv7-apple-macosx10.6.7" target triple = "thumbv7-apple-macosx10.6.7"
; Just making sure the first part of the location isn't a repetition ; Just making sure the first part of the location isn't a repetition
; of the size of the location description. ; of the size of the location description.
; ;
; 0x90 DW_OP_regx of super-register ; 0x90 DW_OP_regx of super-register
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test/CodeGen/ARM/default-float-abi.ll

; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s --check-prefix=CHECK-HARD ; RUN: llc -mtriple=armv7-linux-gnueabihf -mattr=+neon %s -o - | FileCheck %s --check-prefix=CHECK-HARD
; RUN: llc -mtriple=armv7-linux-eabihf %s -o - | FileCheck %s --check-prefix=CHECK-HARD ; RUN: llc -mtriple=armv7-linux-eabihf -mattr=+neon %s -o - | FileCheck %s --check-prefix=CHECK-HARD
; RUN: llc -mtriple=armv7-linux-gnueabihf -float-abi=soft %s -o - | FileCheck %s --check-prefix=CHECK-SOFT ; RUN: llc -mtriple=armv7-linux-gnueabihf -mattr=+neon -float-abi=soft %s -o - | FileCheck %s --check-prefix=CHECK-SOFT
; RUN: llc -mtriple=armv7-linux-gnueabi %s -o - | FileCheck %s --check-prefix=CHECK-SOFT ; RUN: llc -mtriple=armv7-linux-gnueabi -mattr=+neon %s -o - | FileCheck %s --check-prefix=CHECK-SOFT
; RUN: llc -mtriple=armv7-linux-eabi -float-abi=hard %s -o - | FileCheck %s --check-prefix=CHECK-HARD ; RUN: llc -mtriple=armv7-linux-eabi -mattr=+neon -float-abi=hard %s -o - | FileCheck %s --check-prefix=CHECK-HARD
; RUN: llc -mtriple=thumbv7-apple-ios6.0 %s -o - | FileCheck %s --check-prefix=CHECK-SOFT ; RUN: llc -mtriple=thumbv7-apple-ios6.0 %s -o - | FileCheck %s --check-prefix=CHECK-SOFT
define float @test_abi(float %lhs, float %rhs) { define float @test_abi(float %lhs, float %rhs) {
%sum = fadd float %lhs, %rhs %sum = fadd float %lhs, %rhs
ret float %sum ret float %sum
; CHECK-HARD-LABEL: test_abi: ; CHECK-HARD-LABEL: test_abi:
; CHECK-HARD-NOT: vmov ; CHECK-HARD-NOT: vmov
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test/CodeGen/ARM/dwarf-unwind.ll

; RUN: llc -mtriple=thumbv7-netbsd-eabi -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv7-netbsd-eabi -mattr=+neon -o - %s | FileCheck %s
declare void @bar() declare void @bar()
; ARM's frame lowering attempts to tack another callee-saved register onto the ; ARM's frame lowering attempts to tack another callee-saved register onto the
; list when it detects a potential misaligned VFP store. However, if there are ; list when it detects a potential misaligned VFP store. However, if there are
; none available it used to just vpush anyway and misreport the location of the ; none available it used to just vpush anyway and misreport the location of the
; registers in unwind info. Since there are benefits to aligned stores, it's ; registers in unwind info. Since there are benefits to aligned stores, it's
; better to correct the code than the .cfi_offset directive. ; better to correct the code than the .cfi_offset directive.
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; CHECK: .cfi_def_cfa_offset 40 ; CHECK: .cfi_def_cfa_offset 40
; CHECK: add r7, sp, #16 ; CHECK: add r7, sp, #16
; CHECK: .cfi_def_cfa r7, 24 ; CHECK: .cfi_def_cfa r7, 24
; CHECK-NOT: .cfi_def_cfa_offset ; CHECK-NOT: .cfi_def_cfa_offset
call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"() call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"()
call void @bar() call void @bar()
ret void ret void
} }
No newline at end of file No newline at end of file

test/CodeGen/ARM/ehabi.ll

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; RUN: llc -mtriple arm-unknown-linux-gnueabi \ ; RUN: llc -mtriple arm-unknown-linux-gnueabi \
; RUN: -disable-fp-elim -filetype=asm -o - %s \ ; RUN: -disable-fp-elim -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-FP ; RUN: | FileCheck %s --check-prefix=CHECK-FP
; RUN: llc -mtriple arm-unknown-linux-gnueabi \ ; RUN: llc -mtriple arm-unknown-linux-gnueabi \
; RUN: -filetype=asm -o - %s \ ; RUN: -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-FP-ELIM ; RUN: | FileCheck %s --check-prefix=CHECK-FP-ELIM
; RUN: llc -mtriple armv7-unknown-linux-gnueabi \ ; RUN: llc -mtriple armv7-unknown-linux-gnueabi -mattr=+neon \
; RUN: -disable-fp-elim -filetype=asm -o - %s \ ; RUN: -disable-fp-elim -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP ; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP
; RUN: llc -mtriple armv7-unknown-linux-gnueabi \ ; RUN: llc -mtriple armv7-unknown-linux-gnueabi -mattr=+neon \
; RUN: -filetype=asm -o - %s \ ; RUN: -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP-ELIM ; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP-ELIM
; RUN: llc -mtriple arm-unknown-linux-androideabi \ ; RUN: llc -mtriple arm-unknown-linux-androideabi \
; RUN: -disable-fp-elim -filetype=asm -o - %s \ ; RUN: -disable-fp-elim -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-FP ; RUN: | FileCheck %s --check-prefix=CHECK-FP
; RUN: llc -mtriple arm-unknown-linux-androideabi \ ; RUN: llc -mtriple arm-unknown-linux-androideabi \
; RUN: -filetype=asm -o - %s \ ; RUN: -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-FP-ELIM ; RUN: | FileCheck %s --check-prefix=CHECK-FP-ELIM
; RUN: llc -mtriple armv7-unknown-linux-androideabi \ ; RUN: llc -mtriple armv7-unknown-linux-androideabi -mattr=+neon \
; RUN: -disable-fp-elim -filetype=asm -o - %s \ ; RUN: -disable-fp-elim -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP ; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP
; RUN: llc -mtriple armv7-unknown-linux-androideabi \ ; RUN: llc -mtriple armv7-unknown-linux-androideabi -mattr=+neon \
; RUN: -filetype=asm -o - %s \ ; RUN: -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP-ELIM ; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP-ELIM
; RUN: llc -mtriple arm-unknown-netbsd-eabi \ ; RUN: llc -mtriple arm-unknown-netbsd-eabi \
; RUN: -disable-fp-elim -filetype=asm -o - %s \ ; RUN: -disable-fp-elim -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=DWARF-FP ; RUN: | FileCheck %s --check-prefix=DWARF-FP
; RUN: llc -mtriple arm-unknown-netbsd-eabi \ ; RUN: llc -mtriple arm-unknown-netbsd-eabi \
; RUN: -filetype=asm -o - %s \ ; RUN: -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=DWARF-FP-ELIM ; RUN: | FileCheck %s --check-prefix=DWARF-FP-ELIM
; RUN: llc -mtriple armv7-unknown-netbsd-eabi \ ; RUN: llc -mtriple armv7-unknown-netbsd-eabi -mattr=+neon \
; RUN: -disable-fp-elim -filetype=asm -o - %s \ ; RUN: -disable-fp-elim -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=DWARF-V7-FP ; RUN: | FileCheck %s --check-prefix=DWARF-V7-FP
; RUN: llc -mtriple armv7-unknown-netbsd-eabi \ ; RUN: llc -mtriple armv7-unknown-netbsd-eabi -mattr=+neon \
; RUN: -filetype=asm -o - %s \ ; RUN: -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=DWARF-V7-FP-ELIM ; RUN: | FileCheck %s --check-prefix=DWARF-V7-FP-ELIM
;------------------------------------------------------------------------------- ;-------------------------------------------------------------------------------
; Test 1 ; Test 1
;------------------------------------------------------------------------------- ;-------------------------------------------------------------------------------
; This is the LLVM assembly generated from following C++ code: ; This is the LLVM assembly generated from following C++ code:
; ;
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; DWARF-FP: .cfi_offset r7, -24 ; DWARF-FP: .cfi_offset r7, -24
; DWARF-FP: .cfi_offset r6, -28 ; DWARF-FP: .cfi_offset r6, -28
; DWARF-FP: .cfi_offset r5, -32 ; DWARF-FP: .cfi_offset r5, -32
; DWARF-FP: .cfi_offset r4, -36 ; DWARF-FP: .cfi_offset r4, -36
; DWARF-FP: add r11, sp, #28 ; DWARF-FP: add r11, sp, #28
; DWARF-FP: .cfi_def_cfa r11, 8 ; DWARF-FP: .cfi_def_cfa r11, 8
; DWARF-FP: sub sp, sp, #44 ; DWARF-FP: sub sp, sp, #44
; DWARF-FP: sub sp, r11, #28 ; DWARF-FP: sub sp, r11, #28
; DWARF-FP: pop {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; DWARF-FP: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; DWARF-FP: mov pc, lr
; DWARF-FP: .cfi_endproc ; DWARF-FP: .cfi_endproc
; DWARF-FP-ELIM-LABEL: _Z4testiiiiiddddd: ; DWARF-FP-ELIM-LABEL: _Z4testiiiiiddddd:
; DWARF-FP-ELIM: .cfi_startproc ; DWARF-FP-ELIM: .cfi_startproc
; DWARF-FP-ELIM: .cfi_personality 0, __gxx_personality_v0 ; DWARF-FP-ELIM: .cfi_personality 0, __gxx_personality_v0
; DWARF-FP-ELIM: .cfi_lsda 0, .Lexception0 ; DWARF-FP-ELIM: .cfi_lsda 0, .Lexception0
; DWARF-FP-ELIM: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; DWARF-FP-ELIM: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; DWARF-FP-ELIM: .cfi_def_cfa_offset 36 ; DWARF-FP-ELIM: .cfi_def_cfa_offset 36
; DWARF-FP-ELIM: .cfi_offset lr, -4 ; DWARF-FP-ELIM: .cfi_offset lr, -4
; DWARF-FP-ELIM: .cfi_offset r11, -8 ; DWARF-FP-ELIM: .cfi_offset r11, -8
; DWARF-FP-ELIM: .cfi_offset r10, -12 ; DWARF-FP-ELIM: .cfi_offset r10, -12
; DWARF-FP-ELIM: .cfi_offset r9, -16 ; DWARF-FP-ELIM: .cfi_offset r9, -16
; DWARF-FP-ELIM: .cfi_offset r8, -20 ; DWARF-FP-ELIM: .cfi_offset r8, -20
; DWARF-FP-ELIM: .cfi_offset r7, -24 ; DWARF-FP-ELIM: .cfi_offset r7, -24
; DWARF-FP-ELIM: .cfi_offset r6, -28 ; DWARF-FP-ELIM: .cfi_offset r6, -28
; DWARF-FP-ELIM: .cfi_offset r5, -32 ; DWARF-FP-ELIM: .cfi_offset r5, -32
; DWARF-FP-ELIM: .cfi_offset r4, -36 ; DWARF-FP-ELIM: .cfi_offset r4, -36
; DWARF-FP-ELIM: sub sp, sp, #36 ; DWARF-FP-ELIM: sub sp, sp, #36
; DWARF-FP-ELIM: .cfi_def_cfa_offset 72 ; DWARF-FP-ELIM: .cfi_def_cfa_offset 72
; DWARF-FP-ELIM: add sp, sp, #36 ; DWARF-FP-ELIM: add sp, sp, #36
; DWARF-FP-ELIM: pop {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; DWARF-FP-ELIM: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; DWARF-FP-ELIM: mov pc, lr
; DWARF-FP-ELIM: .cfi_endproc ; DWARF-FP-ELIM: .cfi_endproc
; DWARF-V7-FP-LABEL: _Z4testiiiiiddddd: ; DWARF-V7-FP-LABEL: _Z4testiiiiiddddd:
; DWARF-V7-FP: .cfi_startproc ; DWARF-V7-FP: .cfi_startproc
; DWARF-V7-FP: .cfi_personality 0, __gxx_personality_v0 ; DWARF-V7-FP: .cfi_personality 0, __gxx_personality_v0
; DWARF-V7-FP: .cfi_lsda 0, .Lexception0 ; DWARF-V7-FP: .cfi_lsda 0, .Lexception0
; DWARF-V7-FP: push {r4, r10, r11, lr} ; DWARF-V7-FP: push {r4, r10, r11, lr}
; DWARF-V7-FP: .cfi_def_cfa_offset 16 ; DWARF-V7-FP: .cfi_def_cfa_offset 16
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; CHECK-FP-LABEL: test2: ; CHECK-FP-LABEL: test2:
; CHECK-FP: .fnstart ; CHECK-FP: .fnstart
; CHECK-FP: .save {r11, lr} ; CHECK-FP: .save {r11, lr}
; CHECK-FP: push {r11, lr} ; CHECK-FP: push {r11, lr}
; CHECK-FP: .setfp r11, sp ; CHECK-FP: .setfp r11, sp
; CHECK-FP: mov r11, sp ; CHECK-FP: mov r11, sp
; CHECK-FP: pop {r11, lr} ; CHECK-FP: pop {r11, lr}
; CHECK-FP: mov pc, lr ; CHECK-FP: bx lr
; CHECK-FP: .fnend ; CHECK-FP: .fnend
; CHECK-FP-ELIM-LABEL: test2: ; CHECK-FP-ELIM-LABEL: test2:
; CHECK-FP-ELIM: .fnstart ; CHECK-FP-ELIM: .fnstart
; CHECK-FP-ELIM: .save {r11, lr} ; CHECK-FP-ELIM: .save {r11, lr}
; CHECK-FP-ELIM: push {r11, lr} ; CHECK-FP-ELIM: push {r11, lr}
; CHECK-FP-ELIM: pop {r11, lr} ; CHECK-FP-ELIM: pop {r11, lr}
; CHECK-FP-ELIM: mov pc, lr ; CHECK-FP-ELIM: bx lr
; CHECK-FP-ELIM: .fnend ; CHECK-FP-ELIM: .fnend
; CHECK-V7-FP-LABEL: test2: ; CHECK-V7-FP-LABEL: test2:
; CHECK-V7-FP: .fnstart ; CHECK-V7-FP: .fnstart
; CHECK-V7-FP: .save {r11, lr} ; CHECK-V7-FP: .save {r11, lr}
; CHECK-V7-FP: push {r11, lr} ; CHECK-V7-FP: push {r11, lr}
; CHECK-V7-FP: .setfp r11, sp ; CHECK-V7-FP: .setfp r11, sp
; CHECK-V7-FP: mov r11, sp ; CHECK-V7-FP: mov r11, sp
Show All 10 Lines
; DWARF-FP-LABEL: test2: ; DWARF-FP-LABEL: test2:
; DWARF-FP: .cfi_startproc ; DWARF-FP: .cfi_startproc
; DWARF-FP: push {r11, lr} ; DWARF-FP: push {r11, lr}
; DWARF-FP: .cfi_def_cfa_offset 8 ; DWARF-FP: .cfi_def_cfa_offset 8
; DWARF-FP: .cfi_offset lr, -4 ; DWARF-FP: .cfi_offset lr, -4
; DWARF-FP: .cfi_offset r11, -8 ; DWARF-FP: .cfi_offset r11, -8
; DWARF-FP: mov r11, sp ; DWARF-FP: mov r11, sp
; DWARF-FP: .cfi_def_cfa_register r11 ; DWARF-FP: .cfi_def_cfa_register r11
; DWARF-FP: pop {r11, lr} ; DWARF-FP: pop {r11, pc}
; DWARF-FP: mov pc, lr
; DWARF-FP: .cfi_endproc ; DWARF-FP: .cfi_endproc
; DWARF-FP-ELIM-LABEL: test2: ; DWARF-FP-ELIM-LABEL: test2:
; DWARF-FP-ELIM: .cfi_startproc ; DWARF-FP-ELIM: .cfi_startproc
; DWARF-FP-ELIM: push {r11, lr} ; DWARF-FP-ELIM: push {r11, lr}
; DWARF-FP-ELIM: .cfi_def_cfa_offset 8 ; DWARF-FP-ELIM: .cfi_def_cfa_offset 8
; DWARF-FP-ELIM: .cfi_offset lr, -4 ; DWARF-FP-ELIM: .cfi_offset lr, -4
; DWARF-FP-ELIM: .cfi_offset r11, -8 ; DWARF-FP-ELIM: .cfi_offset r11, -8
; DWARF-FP-ELIM: pop {r11, lr} ; DWARF-FP-ELIM: pop {r11, pc}
; DWARF-FP-ELIM: mov pc, lr
; DWARF-FP-ELIM: .cfi_endproc ; DWARF-FP-ELIM: .cfi_endproc
; DWARF-V7-FP-LABEL: test2: ; DWARF-V7-FP-LABEL: test2:
; DWARF-V7-FP: .cfi_startproc ; DWARF-V7-FP: .cfi_startproc
; DWARF-V7-FP: push {r11, lr} ; DWARF-V7-FP: push {r11, lr}
; DWARF-V7-FP: .cfi_def_cfa_offset 8 ; DWARF-V7-FP: .cfi_def_cfa_offset 8
; DWARF-V7-FP: .cfi_offset lr, -4 ; DWARF-V7-FP: .cfi_offset lr, -4
; DWARF-V7-FP: .cfi_offset r11, -8 ; DWARF-V7-FP: .cfi_offset r11, -8
Show All 35 Lines
; CHECK-FP-LABEL: test3: ; CHECK-FP-LABEL: test3:
; CHECK-FP: .fnstart ; CHECK-FP: .fnstart
; CHECK-FP: .save {r4, r5, r11, lr} ; CHECK-FP: .save {r4, r5, r11, lr}
; CHECK-FP: push {r4, r5, r11, lr} ; CHECK-FP: push {r4, r5, r11, lr}
; CHECK-FP: .setfp r11, sp, #8 ; CHECK-FP: .setfp r11, sp, #8
; CHECK-FP: add r11, sp, #8 ; CHECK-FP: add r11, sp, #8
; CHECK-FP: pop {r4, r5, r11, lr} ; CHECK-FP: pop {r4, r5, r11, lr}
; CHECK-FP: mov pc, lr ; CHECK-FP: bx lr
; CHECK-FP: .fnend ; CHECK-FP: .fnend
; CHECK-FP-ELIM-LABEL: test3: ; CHECK-FP-ELIM-LABEL: test3:
; CHECK-FP-ELIM: .fnstart ; CHECK-FP-ELIM: .fnstart
; CHECK-FP-ELIM: .save {r4, r5, r11, lr} ; CHECK-FP-ELIM: .save {r4, r5, r11, lr}
; CHECK-FP-ELIM: push {r4, r5, r11, lr} ; CHECK-FP-ELIM: push {r4, r5, r11, lr}
; CHECK-FP-ELIM: pop {r4, r5, r11, lr} ; CHECK-FP-ELIM: pop {r4, r5, r11, lr}
; CHECK-FP-ELIM: mov pc, lr ; CHECK-FP-ELIM: bx lr
; CHECK-FP-ELIM: .fnend ; CHECK-FP-ELIM: .fnend
; CHECK-V7-FP-LABEL: test3: ; CHECK-V7-FP-LABEL: test3:
; CHECK-V7-FP: .fnstart ; CHECK-V7-FP: .fnstart
; CHECK-V7-FP: .save {r4, r5, r11, lr} ; CHECK-V7-FP: .save {r4, r5, r11, lr}
; CHECK-V7-FP: push {r4, r5, r11, lr} ; CHECK-V7-FP: push {r4, r5, r11, lr}
; CHECK-V7-FP: .setfp r11, sp, #8 ; CHECK-V7-FP: .setfp r11, sp, #8
; CHECK-V7-FP: add r11, sp, #8 ; CHECK-V7-FP: add r11, sp, #8
Show All 12 Lines
; DWARF-FP: push {r4, r5, r11, lr} ; DWARF-FP: push {r4, r5, r11, lr}
; DWARF-FP: .cfi_def_cfa_offset 16 ; DWARF-FP: .cfi_def_cfa_offset 16
; DWARF-FP: .cfi_offset lr, -4 ; DWARF-FP: .cfi_offset lr, -4
; DWARF-FP: .cfi_offset r11, -8 ; DWARF-FP: .cfi_offset r11, -8
; DWARF-FP: .cfi_offset r5, -12 ; DWARF-FP: .cfi_offset r5, -12
; DWARF-FP: .cfi_offset r4, -16 ; DWARF-FP: .cfi_offset r4, -16
; DWARF-FP: add r11, sp, #8 ; DWARF-FP: add r11, sp, #8
; DWARF-FP: .cfi_def_cfa r11, 8 ; DWARF-FP: .cfi_def_cfa r11, 8
; DWARF-FP: pop {r4, r5, r11, lr} ; DWARF-FP: pop {r4, r5, r11, pc}
; DWARF-FP: mov pc, lr
; DWARF-FP: .cfi_endproc ; DWARF-FP: .cfi_endproc
; DWARF-FP-ELIM-LABEL: test3: ; DWARF-FP-ELIM-LABEL: test3:
; DWARF-FP-ELIM: .cfi_startproc ; DWARF-FP-ELIM: .cfi_startproc
; DWARF-FP-ELIM: push {r4, r5, r11, lr} ; DWARF-FP-ELIM: push {r4, r5, r11, lr}
; DWARF-FP-ELIM: .cfi_def_cfa_offset 16 ; DWARF-FP-ELIM: .cfi_def_cfa_offset 16
; DWARF-FP-ELIM: .cfi_offset lr, -4 ; DWARF-FP-ELIM: .cfi_offset lr, -4
; DWARF-FP-ELIM: .cfi_offset r11, -8 ; DWARF-FP-ELIM: .cfi_offset r11, -8
; DWARF-FP-ELIM: .cfi_offset r5, -12 ; DWARF-FP-ELIM: .cfi_offset r5, -12
; DWARF-FP-ELIM: .cfi_offset r4, -16 ; DWARF-FP-ELIM: .cfi_offset r4, -16
; DWARF-FP-ELIM: pop {r4, r5, r11, lr} ; DWARF-FP-ELIM: pop {r4, r5, r11, pc}
; DWARF-FP-ELIM: mov pc, lr
; DWARF-FP-ELIM: .cfi_endproc ; DWARF-FP-ELIM: .cfi_endproc
; DWARF-V7-FP-LABEL: test3: ; DWARF-V7-FP-LABEL: test3:
; DWARF-V7-FP: .cfi_startproc ; DWARF-V7-FP: .cfi_startproc
; DWARF-V7-FP: push {r4, r5, r11, lr} ; DWARF-V7-FP: push {r4, r5, r11, lr}
; DWARF-V7-FP: .cfi_def_cfa_offset 16 ; DWARF-V7-FP: .cfi_def_cfa_offset 16
; DWARF-V7-FP: .cfi_offset lr, -4 ; DWARF-V7-FP: .cfi_offset lr, -4
; DWARF-V7-FP: .cfi_offset r11, -8 ; DWARF-V7-FP: .cfi_offset r11, -8
Show All 22 Lines
define void @test4() nounwind { define void @test4() nounwind {
entry: entry:
ret void ret void
} }
; CHECK-FP-LABEL: test4: ; CHECK-FP-LABEL: test4:
; CHECK-FP: .fnstart ; CHECK-FP: .fnstart
; CHECK-FP: mov pc, lr ; CHECK-FP: bx lr
; CHECK-FP: .cantunwind ; CHECK-FP: .cantunwind
; CHECK-FP: .fnend ; CHECK-FP: .fnend
; CHECK-FP-ELIM-LABEL: test4: ; CHECK-FP-ELIM-LABEL: test4:
; CHECK-FP-ELIM: .fnstart ; CHECK-FP-ELIM: .fnstart
; CHECK-FP-ELIM: mov pc, lr ; CHECK-FP-ELIM: bx lr
; CHECK-FP-ELIM: .cantunwind ; CHECK-FP-ELIM: .cantunwind
; CHECK-FP-ELIM: .fnend ; CHECK-FP-ELIM: .fnend
; CHECK-V7-FP-LABEL: test4: ; CHECK-V7-FP-LABEL: test4:
; CHECK-V7-FP: .fnstart ; CHECK-V7-FP: .fnstart
; CHECK-V7-FP: bx lr ; CHECK-V7-FP: bx lr
; CHECK-V7-FP: .cantunwind ; CHECK-V7-FP: .cantunwind
; CHECK-V7-FP: .fnend ; CHECK-V7-FP: .fnend
; CHECK-V7-FP-ELIM-LABEL: test4: ; CHECK-V7-FP-ELIM-LABEL: test4:
; CHECK-V7-FP-ELIM: .fnstart ; CHECK-V7-FP-ELIM: .fnstart
; CHECK-V7-FP-ELIM: bx lr ; CHECK-V7-FP-ELIM: bx lr
; CHECK-V7-FP-ELIM: .cantunwind ; CHECK-V7-FP-ELIM: .cantunwind
; CHECK-V7-FP-ELIM: .fnend ; CHECK-V7-FP-ELIM: .fnend
; DWARF-FP-LABEL: test4: ; DWARF-FP-LABEL: test4:
; DWARF-FP-NOT: .cfi_startproc ; DWARF-FP-NOT: .cfi_startproc
; DWARF-FP: mov pc, lr ; DWARF-FP: bx lr
; DWARF-FP-NOT: .cfi_endproc ; DWARF-FP-NOT: .cfi_endproc
; DWARF-FP: .size test4, ; DWARF-FP: .size test4,
; DWARF-FP-ELIM-LABEL: test4: ; DWARF-FP-ELIM-LABEL: test4:
; DWARF-FP-ELIM-NOT: .cfi_startproc ; DWARF-FP-ELIM-NOT: .cfi_startproc
; DWARF-FP-ELIM: mov pc, lr ; DWARF-FP-ELIM: bx lr
; DWARF-FP-ELIM-NOT: .cfi_endproc ; DWARF-FP-ELIM-NOT: .cfi_endproc
; DWARF-FP-ELIM: .size test4, ; DWARF-FP-ELIM: .size test4,
; DWARF-V7-FP-LABEL: test4: ; DWARF-V7-FP-LABEL: test4:
; DWARF-V7-FP-NOT: .cfi_startproc ; DWARF-V7-FP-NOT: .cfi_startproc
; DWARF-V7-FP: bx lr ; DWARF-V7-FP: bx lr
; DWARF-V7-FP-NOT: .cfi_endproc ; DWARF-V7-FP-NOT: .cfi_endproc
; DWARF-V7-FP: .size test4, ; DWARF-V7-FP: .size test4,
; DWARF-V7-FP-ELIM-LABEL: test4: ; DWARF-V7-FP-ELIM-LABEL: test4:
; DWARF-V7-FP-ELIM-NOT: .cfi_startproc ; DWARF-V7-FP-ELIM-NOT: .cfi_startproc
; DWARF-V7-FP-ELIM: bx lr ; DWARF-V7-FP-ELIM: bx lr
; DWARF-V7-FP-ELIM-NOT: .cfi_endproc ; DWARF-V7-FP-ELIM-NOT: .cfi_endproc
; DWARF-V7-FP-ELIM: .size test4, ; DWARF-V7-FP-ELIM: .size test4,

test/CodeGen/ARM/fast-isel-align.ll

; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN ; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN ; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -mattr=+neon -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -mattr=+neon -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN ; RUN: llc < %s -O0 -mattr=+neon,+strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN ; RUN: llc < %s -O0 -mattr=+neon,+strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -mattr=+neon -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN ; RUN: llc < %s -O0 -mattr=+neon,+strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
; RUN: llc < %s -O0 -mattr=+strict-align -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN ; RUN: llc < %s -O0 -mattr=+neon,+strict-align -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -mattr=+strict-align -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN ; RUN: llc < %s -O0 -mattr=+neon,+strict-align -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -mattr=+neon -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -mattr=+neon -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -mattr=+strict-align -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN ; RUN: llc < %s -O0 -mattr=+neon,+strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -mattr=+strict-align -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN ; RUN: llc < %s -O0 -mattr=+neon,+strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
; Check unaligned stores ; Check unaligned stores
%struct.anon = type <{ float }> %struct.anon = type <{ float }>
@a = common global %struct.anon* null, align 4 @a = common global %struct.anon* null, align 4
define void @unaligned_store(float %x, float %y) nounwind { define void @unaligned_store(float %x, float %y) nounwind {
entry: entry:
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test/CodeGen/ARM/fast-isel-call.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=+neon | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=+long-calls | FileCheck %s --check-prefix=ARM-LONG ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=+long-calls | FileCheck %s --check-prefix=ARM-LONG
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=+long-calls | FileCheck %s --check-prefix=ARM-LONG ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=+long-calls,+neon | FileCheck %s --check-prefix=ARM-LONG
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=+long-calls | FileCheck %s --check-prefix=THUMB-LONG ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=+long-calls | FileCheck %s --check-prefix=THUMB-LONG
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP
; Note that some of these tests assume that relocations are either ; Note that some of these tests assume that relocations are either
; movw/movt or constant pool loads. Different platforms will select ; movw/movt or constant pool loads. Different platforms will select
; different approaches. ; different approaches.
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test/CodeGen/ARM/fast-isel-cmp-imm.ll

; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=+neon -verify-machineinstrs | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
define void @t1a(float %a) uwtable ssp { define void @t1a(float %a) uwtable ssp {
entry: entry:
; ARM: t1a ; ARM: t1a
; THUMB: t1a ; THUMB: t1a
%cmp = fcmp oeq float %a, 0.000000e+00 %cmp = fcmp oeq float %a, 0.000000e+00
; ARM: vcmpe.f32 s{{[0-9]+}}, #0 ; ARM: vcmpe.f32 s{{[0-9]+}}, #0
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test/CodeGen/ARM/fast-isel-conversion.ll

; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=+neon | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; Test sitofp ; Test sitofp
define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp { define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp {
entry: entry:
; ARM: sitofp_single_i32 ; ARM: sitofp_single_i32
; ARM: vmov s0, r0 ; ARM: vmov s0, r0
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test/CodeGen/ARM/fast-isel-static.ll

; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static -mattr=+long-calls | FileCheck -check-prefix=CHECK-LONG %s ; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static -mattr=+long-calls | FileCheck -check-prefix=CHECK-LONG %s
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static -mattr=+long-calls | FileCheck -check-prefix=CHECK-LONG %s ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static -mattr=+long-calls,+neon | FileCheck -check-prefix=CHECK-LONG %s
; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s ; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static -mattr=+neon | FileCheck -check-prefix=CHECK-NORM %s
define void @myadd(float* %sum, float* %addend) nounwind { define void @myadd(float* %sum, float* %addend) nounwind {
entry: entry:
%sum.addr = alloca float*, align 4 %sum.addr = alloca float*, align 4
%addend.addr = alloca float*, align 4 %addend.addr = alloca float*, align 4
store float* %sum, float** %sum.addr, align 4 store float* %sum, float** %sum.addr, align 4
store float* %addend, float** %addend.addr, align 4 store float* %addend, float** %addend.addr, align 4
%tmp = load float*, float** %sum.addr, align 4 %tmp = load float*, float** %sum.addr, align 4
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test/CodeGen/ARM/fold-stack-adjust.ll

; RUN: llc -mtriple=thumbv7-apple-none-macho < %s | FileCheck %s ; RUN: llc -mtriple=thumbv7-apple-none-macho -mattr=+neon < %s | FileCheck %s
; RUN: llc -mtriple=thumbv6m-apple-none-macho -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-T1 ; RUN: llc -mtriple=thumbv6m-apple-none-macho -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-T1
; RUN: llc -mtriple=thumbv7-apple-darwin-ios -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-IOS ; RUN: llc -mtriple=thumbv7-apple-darwin-ios -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-IOS
; RUN: llc -mtriple=thumbv7--linux-gnueabi -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-LINUX ; RUN: llc -mtriple=thumbv7--linux-gnueabi -mattr=+neon -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-LINUX
declare void @bar(i8*) declare void @bar(i8*)
%bigVec = type [2 x double] %bigVec = type [2 x double]
@var = global %bigVec zeroinitializer @var = global %bigVec zeroinitializer
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test/CodeGen/ARM/fp16-promote.ll

; RUN: llc -asm-verbose=false < %s -mattr=+vfp3,+fp16 | FileCheck %s -check-prefix=CHECK-FP16 -check-prefix=CHECK-ALL ; RUN: llc -asm-verbose=false < %s -mattr=+neon,+vfp3,+fp16 | FileCheck %s -check-prefix=CHECK-FP16 -check-prefix=CHECK-ALL
; RUN: llc -asm-verbose=false < %s | FileCheck %s -check-prefix=CHECK-LIBCALL -check-prefix=CHECK-ALL ; RUN: llc -asm-verbose=false < %s -mattr=+neon | FileCheck %s -check-prefix=CHECK-LIBCALL -check-prefix=CHECK-ALL
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
target triple = "armv7-eabihf" target triple = "armv7-eabihf"
; CHECK-FP16-LABEL: test_fadd: ; CHECK-FP16-LABEL: test_fadd:
; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: vcvtb.f32.f16
; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: vcvtb.f32.f16
; CHECK-FP16: vadd.f32 ; CHECK-FP16: vadd.f32
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test/CodeGen/ARM/fp16.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc -mattr=+neon < %s | FileCheck %s
; RUN: llc -mattr=+vfp3,+fp16 < %s | FileCheck --check-prefix=CHECK-FP16 %s ; RUN: llc -mattr=+vfp3,+fp16 < %s | FileCheck --check-prefix=CHECK-FP16 %s
; RUN: llc -mtriple=armv8-eabihf < %s | FileCheck --check-prefix=CHECK-ARMV8 %s ; RUN: llc -mtriple=armv8-eabihf -mattr=+fp16 < %s | FileCheck --check-prefix=CHECK-ARMV8 %s
; RUN: llc -mtriple=thumbv7m-eabi < %s | FileCheck --check-prefix=CHECK-SOFTFLOAT %s ; RUN: llc -mtriple=thumbv7m-eabi < %s | FileCheck --check-prefix=CHECK-SOFTFLOAT %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
target triple = "armv7---eabihf" target triple = "armv7---eabihf"
@x = global i16 12902 @x = global i16 12902
@y = global i16 0 @y = global i16 0
@z = common global i16 0 @z = common global i16 0
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test/CodeGen/ARM/inlineasm-ldr-pseudo.ll

; PR18354 ; PR18354
; We actually need to use -filetype=obj in this test because if we output ; We actually need to use -filetype=obj in this test because if we output
; assembly, the current code path will bypass the parser and just write the ; assembly, the current code path will bypass the parser and just write the
; raw text out to the Streamer. We need to actually parse the inlineasm to ; raw text out to the Streamer. We need to actually parse the inlineasm to
; demonstrate the bug. Going the asm->obj route does not show the issue. ; demonstrate the bug. Going the asm->obj route does not show the issue.
; RUN: llc -mtriple=arm-none-linux < %s -filetype=obj | llvm-objdump -d - | FileCheck %s ; RUN: llc -mtriple=arm-none-linux < %s -filetype=obj | llvm-objdump -d - | FileCheck %s
; RUN: llc -mtriple=arm-apple-darwin < %s -filetype=obj | llvm-objdump -d - | FileCheck %s ; RUN: llc -mtriple=arm-apple-darwin < %s -filetype=obj | llvm-objdump -d - | FileCheck %s
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: 0: 00 00 9f e5 ldr r0, [pc] ; CHECK: 0: 00 00 9f e5 ldr r0, [pc]
; CHECK: 4: 0e f0 a0 e1 mov pc, lr ; CHECK: 4: 1e ff 2f e1 bx lr
; Make sure the constant pool entry comes after the return ; Make sure the constant pool entry comes after the return
; CHECK: 8: 01 00 00 00 ; CHECK: 8: 01 00 00 00
define i32 @foo() nounwind { define i32 @foo() nounwind {
entry: entry:
%0 = tail call i32 asm sideeffect "ldr $0,=1", "=r"() nounwind %0 = tail call i32 asm sideeffect "ldr $0,=1", "=r"() nounwind
ret i32 %0 ret i32 %0
} }

test/CodeGen/ARM/integer_insertelement.ll

; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
; This test checks that when inserting one (integer) element into a vector, ; This test checks that when inserting one (integer) element into a vector,
; the vector is not spuriously copied. "vorr dX, dY, dY" is the way of moving ; the vector is not spuriously copied. "vorr dX, dY, dY" is the way of moving
; one DPR to another that we check for. ; one DPR to another that we check for.
; CHECK: @f ; CHECK: @f
; CHECK-NOT: vorr d ; CHECK-NOT: vorr d
; CHECK: vmov.32 d ; CHECK: vmov.32 d
; CHECK-NOT: vorr d ; CHECK-NOT: vorr d
; CHECK: mov pc, lr ; CHECK: bx lr
define <4 x i32> @f(<4 x i32> %in) { define <4 x i32> @f(<4 x i32> %in) {
%1 = insertelement <4 x i32> %in, i32 255, i32 3 %1 = insertelement <4 x i32> %in, i32 255, i32 3
ret <4 x i32> %1 ret <4 x i32> %1
} }
; CHECK: @g ; CHECK: @g
; CHECK-NOT: vorr d ; CHECK-NOT: vorr d
; CHECK: vmov.16 d ; CHECK: vmov.16 d
; CHECK-NOT: vorr d ; CHECK-NOT: vorr d
; CHECK: mov pc, lr ; CHECK: bx lr
define <8 x i16> @g(<8 x i16> %in) { define <8 x i16> @g(<8 x i16> %in) {
%1 = insertelement <8 x i16> %in, i16 255, i32 7 %1 = insertelement <8 x i16> %in, i16 255, i32 7
ret <8 x i16> %1 ret <8 x i16> %1
} }
; CHECK: @h ; CHECK: @h
; CHECK-NOT: vorr d ; CHECK-NOT: vorr d
; CHECK: vmov.8 d ; CHECK: vmov.8 d
; CHECK-NOT: vorr d ; CHECK-NOT: vorr d
; CHECK: mov pc, lr ; CHECK: bx lr
define <16 x i8> @h(<16 x i8> %in) { define <16 x i8> @h(<16 x i8> %in) {
%1 = insertelement <16 x i8> %in, i8 255, i32 15 %1 = insertelement <16 x i8> %in, i8 255, i32 15
ret <16 x i8> %1 ret <16 x i8> %1
} }

test/CodeGen/ARM/isel-v8i32-crash.ll

; RUN: llc < %s -mtriple=armv7-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=armv7-linux-gnu -mattr=+neon | FileCheck %s
; Check we don't crash when trying to combine: ; Check we don't crash when trying to combine:
; (d1 = <float 8.000000e+00, float 8.000000e+00, ...>) (power of 2) ; (d1 = <float 8.000000e+00, float 8.000000e+00, ...>) (power of 2)
; vmul.f32 d0, d1, d0 ; vmul.f32 d0, d1, d0
; vcvt.s32.f32 d0, d0 ; vcvt.s32.f32 d0, d0
; into: ; into:
; vcvt.s32.f32 d0, d0, #3 ; vcvt.s32.f32 d0, d0, #3
; when we have a vector length of 8, due to use of v8i32 types. ; when we have a vector length of 8, due to use of v8i32 types.
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test/CodeGen/ARM/neon-v8.1a.ll

; RUN: llc < %s -mtriple=armv8 -mattr=+v8.1a | FileCheck %s ; RUN: llc < %s -mtriple=armv8 -mattr=+v8.1a,+neon | FileCheck %s
;----------------------------------------------------------------------------- ;-----------------------------------------------------------------------------
; RDMA Vector ; RDMA Vector
declare <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16>, <4 x i16>) declare <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16>, <4 x i16>)
declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>)
declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>) declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>)
declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>)
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test/CodeGen/ARM/neon_spill.ll

; RUN: llc < %s -verify-machineinstrs ; RUN: llc < %s -mattr=+neon -verify-machineinstrs
; RUN: llc < %s -verify-machineinstrs -O0 ; RUN: llc < %s -mattr=+neon -verify-machineinstrs -O0
; PR12177 ; PR12177
; ;
; This test case spills a QQQQ register. ; This test case spills a QQQQ register.
; ;
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
target triple = "armv7-none-linux-gnueabi" target triple = "armv7-none-linux-gnueabi"
%0 = type { %1*, i32, i32, i32, i8 } %0 = type { %1*, i32, i32, i32, i8 }
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test/CodeGen/ARM/nest-register.ll

; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
; Tests that the 'nest' parameter attribute causes the relevant parameter to be ; Tests that the 'nest' parameter attribute causes the relevant parameter to be
; passed in the right register. ; passed in the right register.
define i8* @nest_receiver(i8* nest %arg) nounwind { define i8* @nest_receiver(i8* nest %arg) nounwind {
; CHECK-LABEL: nest_receiver: ; CHECK-LABEL: nest_receiver:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: mov r0, r12 ; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
ret i8* %arg ret i8* %arg
} }
define i8* @nest_caller(i8* %arg) nounwind { define i8* @nest_caller(i8* %arg) nounwind {
; CHECK-LABEL: nest_caller: ; CHECK-LABEL: nest_caller:
; CHECK: mov r12, r0 ; CHECK: mov r12, r0
; CHECK-NEXT: bl nest_receiver ; CHECK-NEXT: bl nest_receiver
; CHECK: mov pc, lr ; CHECK: bx lr
%result = call i8* @nest_receiver(i8* nest %arg) %result = call i8* @nest_receiver(i8* nest %arg)
ret i8* %result ret i8* %result
} }

test/CodeGen/ARM/out-of-registers.ll

; RUN: llc -O3 %s -o - | FileCheck %s ; RUN: llc -mattr=+neon -O3 %s -o - | FileCheck %s
; ModuleID = 'fo.c' ; ModuleID = 'fo.c'
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:32-n8:16:32-S64" target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:32-n8:16:32-S64"
target triple = "thumbv7-none-linux-gnueabi" target triple = "thumbv7-none-linux-gnueabi"
; CHECK: vpush ; CHECK: vpush
; CHECK: vpop ; CHECK: vpop
define void @foo(float* nocapture %A) #0 { define void @foo(float* nocapture %A) #0 {
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test/CodeGen/ARM/setcc-type-mismatch.ll

; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s ; RUN: llc -mtriple=armv7-linux-gnueabihf -mattr=+neon %s -o - | FileCheck %s
define void @test_mismatched_setcc(<4 x i22> %l, <4 x i22> %r, <4 x i1>* %addr) { define void @test_mismatched_setcc(<4 x i22> %l, <4 x i22> %r, <4 x i1>* %addr) {
; CHECK-LABEL: test_mismatched_setcc: ; CHECK-LABEL: test_mismatched_setcc:
; CHECK: vceq.i32 [[CMP128:q[0-9]+]], {{q[0-9]+}}, {{q[0-9]+}} ; CHECK: vceq.i32 [[CMP128:q[0-9]+]], {{q[0-9]+}}, {{q[0-9]+}}
; CHECK: vmovn.i32 {{d[0-9]+}}, [[CMP128]] ; CHECK: vmovn.i32 {{d[0-9]+}}, [[CMP128]]
%tst = icmp eq <4 x i22> %l, %r %tst = icmp eq <4 x i22> %l, %r
store <4 x i1> %tst, <4 x i1>* %addr store <4 x i1> %tst, <4 x i1>* %addr
ret void ret void
} }

test/CodeGen/ARM/struct_byval.ll

; RUN: llc < %s -mtriple=armv7-apple-ios6.0 | FileCheck %s ; RUN: llc < %s -mtriple=armv7-apple-ios6.0 | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7-apple-ios6.0 | FileCheck %s -check-prefix=THUMB ; RUN: llc < %s -mtriple=thumbv7-apple-ios6.0 | FileCheck %s -check-prefix=THUMB
; RUN: llc < %s -mtriple=armv7-unknown-nacl-gnueabi | FileCheck %s -check-prefix=NACL ; RUN: llc < %s -mtriple=armv7-unknown-nacl-gnueabi -mattr=+neon | FileCheck %s -check-prefix=NACL
; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi | FileCheck %s -check-prefix=NOMOVT ; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mattr=+neon | FileCheck %s -check-prefix=NOMOVT
; NOMOVT-NOT: movt ; NOMOVT-NOT: movt
; rdar://9877866 ; rdar://9877866
%struct.SmallStruct = type { i32, [8 x i32], [37 x i8] } %struct.SmallStruct = type { i32, [8 x i32], [37 x i8] }
%struct.LargeStruct = type { i32, [1001 x i8], [300 x i32] } %struct.LargeStruct = type { i32, [1001 x i8], [300 x i32] }
define i32 @f() nounwind ssp { define i32 @f() nounwind ssp {
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test/CodeGen/ARM/struct_byval_arm_t1_t2.ll

;RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=+neon -verify-machineinstrs -filetype=obj | llvm-objdump -triple armv7-none-linux-gnueabi -disassemble - | FileCheck %s --check-prefix=ARM ;RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=+neon -verify-machineinstrs -filetype=obj | llvm-objdump -triple armv7-none-linux-gnueabi -mattr=+neon -disassemble - | FileCheck %s --check-prefix=ARM
;RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabi -mattr=+neon -verify-machineinstrs -filetype=obj | llvm-objdump -triple thumbv7-none-linux-gnueabi -disassemble - | FileCheck %s --check-prefix=THUMB2 ;RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabi -mattr=+neon -verify-machineinstrs -filetype=obj | llvm-objdump -triple thumbv7-none-linux-gnueabi -mattr=+neon -disassemble - | FileCheck %s --check-prefix=THUMB2
;RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=-neon -verify-machineinstrs -filetype=obj | llvm-objdump -triple armv7-none-linux-gnueabi -disassemble - | FileCheck %s --check-prefix=NO_NEON ;RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=-neon -verify-machineinstrs -filetype=obj | llvm-objdump -triple armv7-none-linux-gnueabi -mattr=+neon -disassemble - | FileCheck %s --check-prefix=NO_NEON
;We want to have both positive and negative checks for thumb1. These checks ;We want to have both positive and negative checks for thumb1. These checks
;are not easy to do in a single pass so we generate the output once to a ;are not easy to do in a single pass so we generate the output once to a
;temp file and run filecheck twice with different prefixes. ;temp file and run filecheck twice with different prefixes.
;RUN: llc < %s -mtriple=thumbv5-none-linux-gnueabi -verify-machineinstrs -filetype=obj | llvm-objdump -triple thumbv5-none-linux-gnueabi -disassemble - > %t ;RUN: llc < %s -mtriple=thumbv5-none-linux-gnueabi -verify-machineinstrs -filetype=obj | llvm-objdump -triple thumbv5-none-linux-gnueabi -disassemble - > %t
;RUN: cat %t | FileCheck %s --check-prefix=THUMB1 ;RUN: cat %t | FileCheck %s --check-prefix=THUMB1
;RUN: cat %t | FileCheck %s --check-prefix=T1POST ;RUN: cat %t | FileCheck %s --check-prefix=T1POST
;This file contains auto generated tests for the lowering of passing structs ;This file contains auto generated tests for the lowering of passing structs
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test/CodeGen/ARM/sub-cmp-peephole.ll

; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s --check-prefix=V7 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s --check-prefix=V7
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi | FileCheck %s -check-prefix=V8 ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mattr=+fp-armv8 | FileCheck %s -check-prefix=V8
define i32 @f(i32 %a, i32 %b) nounwind ssp { define i32 @f(i32 %a, i32 %b) nounwind ssp {
entry: entry:
; CHECK-LABEL: f: ; CHECK-LABEL: f:
; CHECK: subs ; CHECK: subs
; CHECK-NOT: cmp ; CHECK-NOT: cmp
%cmp = icmp sgt i32 %a, %b %cmp = icmp sgt i32 %a, %b
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test/CodeGen/ARM/vector-extend-narrow.ll

; RUN: llc -mtriple armv7 %s -o - | FileCheck %s ; RUN: llc -mtriple armv7 -mattr=+neon %s -o - | FileCheck %s
; CHECK-LABEL: f: ; CHECK-LABEL: f:
define float @f(<4 x i16>* nocapture %in) { define float @f(<4 x i16>* nocapture %in) {
; CHECK: vld1 ; CHECK: vld1
; CHECK: vmovl.u16 ; CHECK: vmovl.u16
%1 = load <4 x i16>, <4 x i16>* %in %1 = load <4 x i16>, <4 x i16>* %in
; CHECK: vcvt.f32.u32 ; CHECK: vcvt.f32.u32
%2 = uitofp <4 x i16> %1 to <4 x float> %2 = uitofp <4 x i16> %1 to <4 x float>
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test/CodeGen/ARM/vtrn.ll

; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vtrni8: ; CHECK-LABEL: vtrni8:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vtrn.8 d17, d16 ; CHECK-NEXT: vtrn.8 d17, d16
; CHECK-NEXT: vadd.i8 d16, d17, d16 ; CHECK-NEXT: vadd.i8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
%tmp5 = add <8 x i8> %tmp3, %tmp4 %tmp5 = add <8 x i8> %tmp3, %tmp4
ret <8 x i8> %tmp5 ret <8 x i8> %tmp5
} }
define <16 x i8> @vtrni8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vtrni8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vtrni8_Qres: ; CHECK-LABEL: vtrni8_Qres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d17, [r1]
; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vtrn.8 d16, d17 ; CHECK-NEXT: vtrn.8 d16, d17
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
ret <16 x i8> %tmp3 ret <16 x i8> %tmp3
} }
define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: vtrni16: ; CHECK-LABEL: vtrni16:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vtrn.16 d17, d16 ; CHECK-NEXT: vtrn.16 d17, d16
; CHECK-NEXT: vadd.i16 d16, d17, d16 ; CHECK-NEXT: vadd.i16 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x i16>, <4 x i16>* %A %tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B %tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6> %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7> %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
%tmp5 = add <4 x i16> %tmp3, %tmp4 %tmp5 = add <4 x i16> %tmp3, %tmp4
ret <4 x i16> %tmp5 ret <4 x i16> %tmp5
} }
define <8 x i16> @vtrni16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @vtrni16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: vtrni16_Qres: ; CHECK-LABEL: vtrni16_Qres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d17, [r1]
; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vtrn.16 d16, d17 ; CHECK-NEXT: vtrn.16 d16, d17
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x i16>, <4 x i16>* %A %tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B %tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7> %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>
ret <8 x i16> %tmp3 ret <8 x i16> %tmp3
} }
define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-LABEL: vtrni32: ; CHECK-LABEL: vtrni32:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vtrn.32 d17, d16 ; CHECK-NEXT: vtrn.32 d17, d16
; CHECK-NEXT: vadd.i32 d16, d17, d16 ; CHECK-NEXT: vadd.i32 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <2 x i32>, <2 x i32>* %A %tmp1 = load <2 x i32>, <2 x i32>* %A
%tmp2 = load <2 x i32>, <2 x i32>* %B %tmp2 = load <2 x i32>, <2 x i32>* %B
%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2> %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2>
%tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3> %tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3>
%tmp5 = add <2 x i32> %tmp3, %tmp4 %tmp5 = add <2 x i32> %tmp3, %tmp4
ret <2 x i32> %tmp5 ret <2 x i32> %tmp5
} }
define <4 x i32> @vtrni32_Qres(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @vtrni32_Qres(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-LABEL: vtrni32_Qres: ; CHECK-LABEL: vtrni32_Qres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d17, [r1]
; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vtrn.32 d16, d17 ; CHECK-NEXT: vtrn.32 d16, d17
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <2 x i32>, <2 x i32>* %A %tmp1 = load <2 x i32>, <2 x i32>* %A
%tmp2 = load <2 x i32>, <2 x i32>* %B %tmp2 = load <2 x i32>, <2 x i32>* %B
%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 1, i32 3> %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
ret <4 x i32> %tmp3 ret <4 x i32> %tmp3
} }
define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind { define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
; CHECK-LABEL: vtrnf: ; CHECK-LABEL: vtrnf:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vtrn.32 d17, d16 ; CHECK-NEXT: vtrn.32 d17, d16
; CHECK-NEXT: vadd.f32 d16, d17, d16 ; CHECK-NEXT: vadd.f32 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <2 x float>, <2 x float>* %A %tmp1 = load <2 x float>, <2 x float>* %A
%tmp2 = load <2 x float>, <2 x float>* %B %tmp2 = load <2 x float>, <2 x float>* %B
%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2> %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2>
%tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3> %tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3>
%tmp5 = fadd <2 x float> %tmp3, %tmp4 %tmp5 = fadd <2 x float> %tmp3, %tmp4
ret <2 x float> %tmp5 ret <2 x float> %tmp5
} }
define <4 x float> @vtrnf_Qres(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @vtrnf_Qres(<2 x float>* %A, <2 x float>* %B) nounwind {
; CHECK-LABEL: vtrnf_Qres: ; CHECK-LABEL: vtrnf_Qres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d17, [r1]
; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vtrn.32 d16, d17 ; CHECK-NEXT: vtrn.32 d16, d17
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <2 x float>, <2 x float>* %A %tmp1 = load <2 x float>, <2 x float>* %A
%tmp2 = load <2 x float>, <2 x float>* %B %tmp2 = load <2 x float>, <2 x float>* %B
%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 1, i32 3> %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
ret <4 x float> %tmp3 ret <4 x float> %tmp3
} }
define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-LABEL: vtrnQi8: ; CHECK-LABEL: vtrnQi8:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vtrn.8 q9, q8 ; CHECK-NEXT: vtrn.8 q9, q8
; CHECK-NEXT: vadd.i8 q8, q9, q8 ; CHECK-NEXT: vadd.i8 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <16 x i8>, <16 x i8>* %A %tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B %tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30> %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31> %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
%tmp5 = add <16 x i8> %tmp3, %tmp4 %tmp5 = add <16 x i8> %tmp3, %tmp4
ret <16 x i8> %tmp5 ret <16 x i8> %tmp5
} }
define <32 x i8> @vtrnQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <32 x i8> @vtrnQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-LABEL: vtrnQi8_QQres: ; CHECK-LABEL: vtrnQi8_QQres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vtrn.8 q9, q8 ; CHECK-NEXT: vtrn.8 q9, q8
; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]! ; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <16 x i8>, <16 x i8>* %A %tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B %tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30, i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31> %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30, i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
ret <32 x i8> %tmp3 ret <32 x i8> %tmp3
} }
define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: vtrnQi16: ; CHECK-LABEL: vtrnQi16:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vtrn.16 q9, q8 ; CHECK-NEXT: vtrn.16 q9, q8
; CHECK-NEXT: vadd.i16 q8, q9, q8 ; CHECK-NEXT: vadd.i16 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i16>, <8 x i16>* %A %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B %tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
%tmp5 = add <8 x i16> %tmp3, %tmp4 %tmp5 = add <8 x i16> %tmp3, %tmp4
ret <8 x i16> %tmp5 ret <8 x i16> %tmp5
} }
define <16 x i16> @vtrnQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <16 x i16> @vtrnQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: vtrnQi16_QQres: ; CHECK-LABEL: vtrnQi16_QQres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vtrn.16 q9, q8 ; CHECK-NEXT: vtrn.16 q9, q8
; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]! ; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i16>, <8 x i16>* %A %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B %tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
ret <16 x i16> %tmp3 ret <16 x i16> %tmp3
} }
define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-LABEL: vtrnQi32: ; CHECK-LABEL: vtrnQi32:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vtrn.32 q9, q8 ; CHECK-NEXT: vtrn.32 q9, q8
; CHECK-NEXT: vadd.i32 q8, q9, q8 ; CHECK-NEXT: vadd.i32 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x i32>, <4 x i32>* %A %tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i32>, <4 x i32>* %B %tmp2 = load <4 x i32>, <4 x i32>* %B
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6> %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7> %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
%tmp5 = add <4 x i32> %tmp3, %tmp4 %tmp5 = add <4 x i32> %tmp3, %tmp4
ret <4 x i32> %tmp5 ret <4 x i32> %tmp5
} }
define <8 x i32> @vtrnQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <8 x i32> @vtrnQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-LABEL: vtrnQi32_QQres: ; CHECK-LABEL: vtrnQi32_QQres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vtrn.32 q9, q8 ; CHECK-NEXT: vtrn.32 q9, q8
; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]! ; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x i32>, <4 x i32>* %A %tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i32>, <4 x i32>* %B %tmp2 = load <4 x i32>, <4 x i32>* %B
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7> %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>
ret <8 x i32> %tmp3 ret <8 x i32> %tmp3
} }
define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind { define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK-LABEL: vtrnQf: ; CHECK-LABEL: vtrnQf:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vtrn.32 q9, q8 ; CHECK-NEXT: vtrn.32 q9, q8
; CHECK-NEXT: vadd.f32 q8, q9, q8 ; CHECK-NEXT: vadd.f32 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x float>, <4 x float>* %A %tmp1 = load <4 x float>, <4 x float>* %A
%tmp2 = load <4 x float>, <4 x float>* %B %tmp2 = load <4 x float>, <4 x float>* %B
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6> %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7> %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
%tmp5 = fadd <4 x float> %tmp3, %tmp4 %tmp5 = fadd <4 x float> %tmp3, %tmp4
ret <4 x float> %tmp5 ret <4 x float> %tmp5
} }
define <8 x float> @vtrnQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind { define <8 x float> @vtrnQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK-LABEL: vtrnQf_QQres: ; CHECK-LABEL: vtrnQf_QQres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vtrn.32 q9, q8 ; CHECK-NEXT: vtrn.32 q9, q8
; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]! ; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x float>, <4 x float>* %A %tmp1 = load <4 x float>, <4 x float>* %A
%tmp2 = load <4 x float>, <4 x float>* %B %tmp2 = load <4 x float>, <4 x float>* %B
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7> %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>
ret <8 x float> %tmp3 ret <8 x float> %tmp3
} }
define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vtrni8_undef: ; CHECK-LABEL: vtrni8_undef:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vtrn.8 d17, d16 ; CHECK-NEXT: vtrn.8 d17, d16
; CHECK-NEXT: vadd.i8 d16, d17, d16 ; CHECK-NEXT: vadd.i8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14> %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14>
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
%tmp5 = add <8 x i8> %tmp3, %tmp4 %tmp5 = add <8 x i8> %tmp3, %tmp4
ret <8 x i8> %tmp5 ret <8 x i8> %tmp5
} }
define <16 x i8> @vtrni8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vtrni8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vtrni8_undef_Qres: ; CHECK-LABEL: vtrni8_undef_Qres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d17, [r1]
; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vtrn.8 d16, d17 ; CHECK-NEXT: vtrn.8 d16, d17
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15> %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
ret <16 x i8> %tmp3 ret <16 x i8> %tmp3
} }
define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: vtrnQi16_undef: ; CHECK-LABEL: vtrnQi16_undef:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vtrn.16 q9, q8 ; CHECK-NEXT: vtrn.16 q9, q8
; CHECK-NEXT: vadd.i16 q8, q9, q8 ; CHECK-NEXT: vadd.i16 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i16>, <8 x i16>* %A %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B %tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14> %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14>
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
%tmp5 = add <8 x i16> %tmp3, %tmp4 %tmp5 = add <8 x i16> %tmp3, %tmp4
ret <8 x i16> %tmp5 ret <8 x i16> %tmp5
} }
define <16 x i16> @vtrnQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <16 x i16> @vtrnQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: vtrnQi16_undef_QQres: ; CHECK-LABEL: vtrnQi16_undef_QQres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vtrn.16 q9, q8 ; CHECK-NEXT: vtrn.16 q9, q8
; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]! ; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i16>, <8 x i16>* %A %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B %tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14, i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef> %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14, i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
ret <16 x i16> %tmp3 ret <16 x i16> %tmp3
} }
define <8 x i16> @vtrn_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) { define <8 x i16> @vtrn_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) {
entry: entry:
; CHECK-LABEL: vtrn_lower_shufflemask_undef ; CHECK-LABEL: vtrn_lower_shufflemask_undef
; CHECK: vtrn ; CHECK: vtrn
%tmp1 = load <4 x i16>, <4 x i16>* %A %tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B %tmp2 = load <4 x i16>, <4 x i16>* %B
%0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 5, i32 3, i32 7> %0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 5, i32 3, i32 7>
ret <8 x i16> %0 ret <8 x i16> %0
} }

test/CodeGen/ARM/vuzp.ll

; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vuzpi8: ; CHECK-LABEL: vuzpi8:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vuzp.8 d17, d16 ; CHECK-NEXT: vuzp.8 d17, d16
; CHECK-NEXT: vadd.i8 d16, d17, d16 ; CHECK-NEXT: vadd.i8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%tmp5 = add <8 x i8> %tmp3, %tmp4 %tmp5 = add <8 x i8> %tmp3, %tmp4
ret <8 x i8> %tmp5 ret <8 x i8> %tmp5
} }
define <16 x i8> @vuzpi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vuzpi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vuzpi8_Qres: ; CHECK-LABEL: vuzpi8_Qres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d17, [r1]
; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vuzp.8 d16, d17 ; CHECK-NEXT: vuzp.8 d16, d17
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
ret <16 x i8> %tmp3 ret <16 x i8> %tmp3
} }
define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: vuzpi16: ; CHECK-LABEL: vuzpi16:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vuzp.16 d17, d16 ; CHECK-NEXT: vuzp.16 d17, d16
; CHECK-NEXT: vadd.i16 d16, d17, d16 ; CHECK-NEXT: vadd.i16 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x i16>, <4 x i16>* %A %tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B %tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%tmp5 = add <4 x i16> %tmp3, %tmp4 %tmp5 = add <4 x i16> %tmp3, %tmp4
ret <4 x i16> %tmp5 ret <4 x i16> %tmp5
} }
define <8 x i16> @vuzpi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @vuzpi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: vuzpi16_Qres: ; CHECK-LABEL: vuzpi16_Qres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d17, [r1]
; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vuzp.16 d16, d17 ; CHECK-NEXT: vuzp.16 d16, d17
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x i16>, <4 x i16>* %A %tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B %tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
ret <8 x i16> %tmp3 ret <8 x i16> %tmp3
} }
; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors. ; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-LABEL: vuzpQi8: ; CHECK-LABEL: vuzpQi8:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vuzp.8 q9, q8 ; CHECK-NEXT: vuzp.8 q9, q8
; CHECK-NEXT: vadd.i8 q8, q9, q8 ; CHECK-NEXT: vadd.i8 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <16 x i8>, <16 x i8>* %A %tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B %tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
%tmp5 = add <16 x i8> %tmp3, %tmp4 %tmp5 = add <16 x i8> %tmp3, %tmp4
ret <16 x i8> %tmp5 ret <16 x i8> %tmp5
} }
define <32 x i8> @vuzpQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <32 x i8> @vuzpQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-LABEL: vuzpQi8_QQres: ; CHECK-LABEL: vuzpQi8_QQres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vuzp.8 q9, q8 ; CHECK-NEXT: vuzp.8 q9, q8
; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]! ; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <16 x i8>, <16 x i8>* %A %tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B %tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
ret <32 x i8> %tmp3 ret <32 x i8> %tmp3
} }
define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: vuzpQi16: ; CHECK-LABEL: vuzpQi16:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vuzp.16 q9, q8 ; CHECK-NEXT: vuzp.16 q9, q8
; CHECK-NEXT: vadd.i16 q8, q9, q8 ; CHECK-NEXT: vadd.i16 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i16>, <8 x i16>* %A %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B %tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%tmp5 = add <8 x i16> %tmp3, %tmp4 %tmp5 = add <8 x i16> %tmp3, %tmp4
ret <8 x i16> %tmp5 ret <8 x i16> %tmp5
} }
define <16 x i16> @vuzpQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <16 x i16> @vuzpQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: vuzpQi16_QQres: ; CHECK-LABEL: vuzpQi16_QQres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vuzp.16 q9, q8 ; CHECK-NEXT: vuzp.16 q9, q8
; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]! ; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i16>, <8 x i16>* %A %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B %tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
ret <16 x i16> %tmp3 ret <16 x i16> %tmp3
} }
define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-LABEL: vuzpQi32: ; CHECK-LABEL: vuzpQi32:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vuzp.32 q9, q8 ; CHECK-NEXT: vuzp.32 q9, q8
; CHECK-NEXT: vadd.i32 q8, q9, q8 ; CHECK-NEXT: vadd.i32 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x i32>, <4 x i32>* %A %tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i32>, <4 x i32>* %B %tmp2 = load <4 x i32>, <4 x i32>* %B
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%tmp5 = add <4 x i32> %tmp3, %tmp4 %tmp5 = add <4 x i32> %tmp3, %tmp4
ret <4 x i32> %tmp5 ret <4 x i32> %tmp5
} }
define <8 x i32> @vuzpQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <8 x i32> @vuzpQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-LABEL: vuzpQi32_QQres: ; CHECK-LABEL: vuzpQi32_QQres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vuzp.32 q9, q8 ; CHECK-NEXT: vuzp.32 q9, q8
; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]! ; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x i32>, <4 x i32>* %A %tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i32>, <4 x i32>* %B %tmp2 = load <4 x i32>, <4 x i32>* %B
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
ret <8 x i32> %tmp3 ret <8 x i32> %tmp3
} }
define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind { define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK-LABEL: vuzpQf: ; CHECK-LABEL: vuzpQf:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vuzp.32 q9, q8 ; CHECK-NEXT: vuzp.32 q9, q8
; CHECK-NEXT: vadd.f32 q8, q9, q8 ; CHECK-NEXT: vadd.f32 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x float>, <4 x float>* %A %tmp1 = load <4 x float>, <4 x float>* %A
%tmp2 = load <4 x float>, <4 x float>* %B %tmp2 = load <4 x float>, <4 x float>* %B
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%tmp5 = fadd <4 x float> %tmp3, %tmp4 %tmp5 = fadd <4 x float> %tmp3, %tmp4
ret <4 x float> %tmp5 ret <4 x float> %tmp5
} }
define <8 x float> @vuzpQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind { define <8 x float> @vuzpQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK-LABEL: vuzpQf_QQres: ; CHECK-LABEL: vuzpQf_QQres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vuzp.32 q9, q8 ; CHECK-NEXT: vuzp.32 q9, q8
; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]! ; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x float>, <4 x float>* %A %tmp1 = load <4 x float>, <4 x float>* %A
%tmp2 = load <4 x float>, <4 x float>* %B %tmp2 = load <4 x float>, <4 x float>* %B
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
ret <8 x float> %tmp3 ret <8 x float> %tmp3
} }
; Undef shuffle indices should not prevent matching to VUZP: ; Undef shuffle indices should not prevent matching to VUZP:
define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vuzpi8_undef: ; CHECK-LABEL: vuzpi8_undef:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vuzp.8 d17, d16 ; CHECK-NEXT: vuzp.8 d17, d16
; CHECK-NEXT: vadd.i8 d16, d17, d16 ; CHECK-NEXT: vadd.i8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14> %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14>
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15>
%tmp5 = add <8 x i8> %tmp3, %tmp4 %tmp5 = add <8 x i8> %tmp3, %tmp4
ret <8 x i8> %tmp5 ret <8 x i8> %tmp5
} }
define <16 x i8> @vuzpi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vuzpi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vuzpi8_undef_Qres: ; CHECK-LABEL: vuzpi8_undef_Qres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d17, [r1]
; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vuzp.8 d16, d17 ; CHECK-NEXT: vuzp.8 d16, d17
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15> %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15>
ret <16 x i8> %tmp3 ret <16 x i8> %tmp3
} }
define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: vuzpQi16_undef: ; CHECK-LABEL: vuzpQi16_undef:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vuzp.16 q9, q8 ; CHECK-NEXT: vuzp.16 q9, q8
; CHECK-NEXT: vadd.i16 q8, q9, q8 ; CHECK-NEXT: vadd.i16 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i16>, <8 x i16>* %A %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B %tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14> %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14>
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15>
%tmp5 = add <8 x i16> %tmp3, %tmp4 %tmp5 = add <8 x i16> %tmp3, %tmp4
ret <8 x i16> %tmp5 ret <8 x i16> %tmp5
} }
define <16 x i16> @vuzpQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <16 x i16> @vuzpQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: vuzpQi16_undef_QQres: ; CHECK-LABEL: vuzpQi16_undef_QQres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vuzp.16 q9, q8 ; CHECK-NEXT: vuzp.16 q9, q8
; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]! ; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i16>, <8 x i16>* %A %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B %tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15> %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15>
ret <16 x i16> %tmp3 ret <16 x i16> %tmp3
} }
define <8 x i16> @vuzp_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) { define <8 x i16> @vuzp_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) {
entry: entry:
Show All 18 Lines

test/CodeGen/ARM/vzip.ll

; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vzipi8: ; CHECK-LABEL: vzipi8:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vzip.8 d17, d16 ; CHECK-NEXT: vzip.8 d17, d16
; CHECK-NEXT: vadd.i8 d16, d17, d16 ; CHECK-NEXT: vadd.i8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
%tmp5 = add <8 x i8> %tmp3, %tmp4 %tmp5 = add <8 x i8> %tmp3, %tmp4
ret <8 x i8> %tmp5 ret <8 x i8> %tmp5
} }
define <16 x i8> @vzipi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vzipi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vzipi8_Qres: ; CHECK-LABEL: vzipi8_Qres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d17, [r1]
; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vzip.8 d16, d17 ; CHECK-NEXT: vzip.8 d16, d17
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
ret <16 x i8> %tmp3 ret <16 x i8> %tmp3
} }
define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: vzipi16: ; CHECK-LABEL: vzipi16:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vzip.16 d17, d16 ; CHECK-NEXT: vzip.16 d17, d16
; CHECK-NEXT: vadd.i16 d16, d17, d16 ; CHECK-NEXT: vadd.i16 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x i16>, <4 x i16>* %A %tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B %tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5> %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7> %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
%tmp5 = add <4 x i16> %tmp3, %tmp4 %tmp5 = add <4 x i16> %tmp3, %tmp4
ret <4 x i16> %tmp5 ret <4 x i16> %tmp5
} }
define <8 x i16> @vzipi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @vzipi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: vzipi16_Qres: ; CHECK-LABEL: vzipi16_Qres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d17, [r1]
; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vzip.16 d16, d17 ; CHECK-NEXT: vzip.16 d16, d17
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x i16>, <4 x i16>* %A %tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B %tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
ret <8 x i16> %tmp3 ret <8 x i16> %tmp3
} }
; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors. ; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-LABEL: vzipQi8: ; CHECK-LABEL: vzipQi8:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vzip.8 q9, q8 ; CHECK-NEXT: vzip.8 q9, q8
; CHECK-NEXT: vadd.i8 q8, q9, q8 ; CHECK-NEXT: vadd.i8 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <16 x i8>, <16 x i8>* %A %tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B %tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
%tmp5 = add <16 x i8> %tmp3, %tmp4 %tmp5 = add <16 x i8> %tmp3, %tmp4
ret <16 x i8> %tmp5 ret <16 x i8> %tmp5
} }
define <32 x i8> @vzipQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <32 x i8> @vzipQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-LABEL: vzipQi8_QQres: ; CHECK-LABEL: vzipQi8_QQres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vzip.8 q9, q8 ; CHECK-NEXT: vzip.8 q9, q8
; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]! ; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <16 x i8>, <16 x i8>* %A %tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B %tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
ret <32 x i8> %tmp3 ret <32 x i8> %tmp3
} }
define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: vzipQi16: ; CHECK-LABEL: vzipQi16:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vzip.16 q9, q8 ; CHECK-NEXT: vzip.16 q9, q8
; CHECK-NEXT: vadd.i16 q8, q9, q8 ; CHECK-NEXT: vadd.i16 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i16>, <8 x i16>* %A %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B %tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
%tmp5 = add <8 x i16> %tmp3, %tmp4 %tmp5 = add <8 x i16> %tmp3, %tmp4
ret <8 x i16> %tmp5 ret <8 x i16> %tmp5
} }
define <16 x i16> @vzipQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <16 x i16> @vzipQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: vzipQi16_QQres: ; CHECK-LABEL: vzipQi16_QQres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vzip.16 q9, q8 ; CHECK-NEXT: vzip.16 q9, q8
; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]! ; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i16>, <8 x i16>* %A %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B %tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
ret <16 x i16> %tmp3 ret <16 x i16> %tmp3
} }
define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-LABEL: vzipQi32: ; CHECK-LABEL: vzipQi32:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vzip.32 q9, q8 ; CHECK-NEXT: vzip.32 q9, q8
; CHECK-NEXT: vadd.i32 q8, q9, q8 ; CHECK-NEXT: vadd.i32 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x i32>, <4 x i32>* %A %tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i32>, <4 x i32>* %B %tmp2 = load <4 x i32>, <4 x i32>* %B
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5> %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7> %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
%tmp5 = add <4 x i32> %tmp3, %tmp4 %tmp5 = add <4 x i32> %tmp3, %tmp4
ret <4 x i32> %tmp5 ret <4 x i32> %tmp5
} }
define <8 x i32> @vzipQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <8 x i32> @vzipQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-LABEL: vzipQi32_QQres: ; CHECK-LABEL: vzipQi32_QQres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vzip.32 q9, q8 ; CHECK-NEXT: vzip.32 q9, q8
; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]! ; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x i32>, <4 x i32>* %A %tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i32>, <4 x i32>* %B %tmp2 = load <4 x i32>, <4 x i32>* %B
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
ret <8 x i32> %tmp3 ret <8 x i32> %tmp3
} }
define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind { define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK-LABEL: vzipQf: ; CHECK-LABEL: vzipQf:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vzip.32 q9, q8 ; CHECK-NEXT: vzip.32 q9, q8
; CHECK-NEXT: vadd.f32 q8, q9, q8 ; CHECK-NEXT: vadd.f32 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x float>, <4 x float>* %A %tmp1 = load <4 x float>, <4 x float>* %A
%tmp2 = load <4 x float>, <4 x float>* %B %tmp2 = load <4 x float>, <4 x float>* %B
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5> %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7> %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
%tmp5 = fadd <4 x float> %tmp3, %tmp4 %tmp5 = fadd <4 x float> %tmp3, %tmp4
ret <4 x float> %tmp5 ret <4 x float> %tmp5
} }
define <8 x float> @vzipQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind { define <8 x float> @vzipQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK-LABEL: vzipQf_QQres: ; CHECK-LABEL: vzipQf_QQres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vzip.32 q9, q8 ; CHECK-NEXT: vzip.32 q9, q8
; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]! ; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <4 x float>, <4 x float>* %A %tmp1 = load <4 x float>, <4 x float>* %A
%tmp2 = load <4 x float>, <4 x float>* %B %tmp2 = load <4 x float>, <4 x float>* %B
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
ret <8 x float> %tmp3 ret <8 x float> %tmp3
} }
; Undef shuffle indices should not prevent matching to VZIP: ; Undef shuffle indices should not prevent matching to VZIP:
define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vzipi8_undef: ; CHECK-LABEL: vzipi8_undef:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vzip.8 d17, d16 ; CHECK-NEXT: vzip.8 d17, d16
; CHECK-NEXT: vadd.i8 d16, d17, d16 ; CHECK-NEXT: vadd.i8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 undef, i32 10, i32 3, i32 11> %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 undef, i32 10, i32 3, i32 11>
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 undef, i32 undef, i32 15> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 undef, i32 undef, i32 15>
%tmp5 = add <8 x i8> %tmp3, %tmp4 %tmp5 = add <8 x i8> %tmp3, %tmp4
ret <8 x i8> %tmp5 ret <8 x i8> %tmp5
} }
define <16 x i8> @vzipi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vzipi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vzipi8_undef_Qres: ; CHECK-LABEL: vzipi8_undef_Qres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d17, [r1]
; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vzip.8 d16, d17 ; CHECK-NEXT: vzip.8 d16, d17
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 undef, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 undef, i32 undef, i32 15> %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 undef, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 undef, i32 undef, i32 15>
ret <16 x i8> %tmp3 ret <16 x i8> %tmp3
} }
define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-LABEL: vzipQi8_undef: ; CHECK-LABEL: vzipQi8_undef:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vzip.8 q9, q8 ; CHECK-NEXT: vzip.8 q9, q8
; CHECK-NEXT: vadd.i8 q8, q9, q8 ; CHECK-NEXT: vadd.i8 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <16 x i8>, <16 x i8>* %A %tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B %tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31> %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31>
%tmp5 = add <16 x i8> %tmp3, %tmp4 %tmp5 = add <16 x i8> %tmp3, %tmp4
ret <16 x i8> %tmp5 ret <16 x i8> %tmp5
} }
define <32 x i8> @vzipQi8_undef_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <32 x i8> @vzipQi8_undef_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-LABEL: vzipQi8_undef_QQres: ; CHECK-LABEL: vzipQi8_undef_QQres:
; CHECK: @ BB#0: ; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vzip.8 q9, q8 ; CHECK-NEXT: vzip.8 q9, q8
; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]! ; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: bx lr
%tmp1 = load <16 x i8>, <16 x i8>* %A %tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B %tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31> %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31>
ret <32 x i8> %tmp3 ret <32 x i8> %tmp3
} }
define <8 x i16> @vzip_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) { define <8 x i16> @vzip_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) {
entry: entry:
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test/CodeGen/Thumb/thumb-shrink-wrapping.ll

; RUN: llc %s -o - -enable-shrink-wrap=true -ifcvt-fn-start=1 -ifcvt-fn-stop=0 -mtriple=thumb-macho \ ; RUN: llc %s -o - -enable-shrink-wrap=true -ifcvt-fn-start=1 -ifcvt-fn-stop=0 -mtriple=thumb-macho \
; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE ; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
; RUN: llc %s -o - -enable-shrink-wrap=false -ifcvt-fn-start=1 -ifcvt-fn-stop=0 -mtriple=thumb-macho \ ; rUN: llc %s -o - -enable-shrink-wrap=false -ifcvt-fn-start=1 -ifcvt-fn-stop=0 -mtriple=thumb-macho \
; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE ; rUN: | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
; ;
; Note: Lots of tests use inline asm instead of regular calls. ; Note: Lots of tests use inline asm instead of regular calls.
; This allows to have a better control on what the allocation will do. ; This allows to have a better control on what the allocation will do.
; Otherwise, we may have spill right in the entry block, defeating ; Otherwise, we may have spill right in the entry block, defeating
; shrink-wrapping. Moreover, some of the inline asm statements (nop) ; shrink-wrapping. Moreover, some of the inline asm statements (nop)
; are here to ensure that the related paths do not end up as critical ; are here to ensure that the related paths do not end up as critical
; edges. ; edges.
; Also disable the late if-converter as it makes harder to reason on ; Also disable the late if-converter as it makes harder to reason on
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; ENABLE-NEXT: add sp, #8 ; ENABLE-NEXT: add sp, #8
; ENABLE-NEXT: pop {r7, lr} ; ENABLE-NEXT: pop {r7, lr}
; ;
; CHECK: [[EXIT_LABEL]]: ; CHECK: [[EXIT_LABEL]]:
; ;
; Without shrink-wrapping, epilogue is in the exit block. ; Without shrink-wrapping, epilogue is in the exit block.
; Epilogue code. (What we pop does not matter.) ; Epilogue code. (What we pop does not matter.)
; DISABLE: add sp, #8 ; DISABLE: add sp, #8
; DISABLE-NEXT: pop {r7, pc} ; DISABLE-NEXT: pop {r7}
; DISABLE-NEXT: pop {pc}
; ;
; ENABLE-NEXT: bx lr ; ENABLE-NEXT: bx lr
define i32 @foo(i32 %a, i32 %b) { define i32 @foo(i32 %a, i32 %b) {
%tmp = alloca i32, align 4 %tmp = alloca i32, align 4
%tmp2 = icmp slt i32 %a, %b %tmp2 = icmp slt i32 %a, %b
br i1 %tmp2, label %true, label %false br i1 %tmp2, label %true, label %false
true: true:
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; CHECK-NEXT: cmp [[IV]], #0 ; CHECK-NEXT: cmp [[IV]], #0
; CHECK-NEXT: bne [[LOOP]] ; CHECK-NEXT: bne [[LOOP]]
; ;
; Next BB. ; Next BB.
; SUM << 3. ; SUM << 3.
; CHECK: lsls [[SUM]], [[SUM]], #3 ; CHECK: lsls [[SUM]], [[SUM]], #3
; ;
; Duplicated epilogue. ; Duplicated epilogue.
; DISABLE: pop {r4, pc} ; DISABLE: pop {r4}
; DISABLE: pop {pc}
; ;
; CHECK: [[ELSE_LABEL]]: @ %if.else ; CHECK: [[ELSE_LABEL]]: @ %if.else
; Shift second argument by one and store into returned register. ; Shift second argument by one and store into returned register.
; CHECK: lsls r0, r1, #1 ; CHECK: lsls r0, r1, #1
; DISABLE-NEXT: pop {r4, pc} ; DISABLE-NEXT: pop {r4}
; DISABLE-NEXT: pop {pc}
; ;
; ENABLE-NEXT: bx lr ; ENABLE-NEXT: bx lr
define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) { define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) {
entry: entry:
%tobool = icmp eq i32 %cond, 0 %tobool = icmp eq i32 %cond, 0
br i1 %tobool, label %if.else, label %for.preheader br i1 %tobool, label %if.else, label %for.preheader
for.preheader: for.preheader:
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; CHECK-NEXT: bne [[LOOP]] ; CHECK-NEXT: bne [[LOOP]]
; ;
; Next BB. ; Next BB.
; SUM << 3. ; SUM << 3.
; CHECK: lsls [[SUM]], [[SUM]], #3 ; CHECK: lsls [[SUM]], [[SUM]], #3
; ENABLE-NEXT: pop {r4, lr} ; ENABLE-NEXT: pop {r4, lr}
; ;
; Duplicated epilogue. ; Duplicated epilogue.
; DISABLE: pop {r4, pc} ; DISABLE: pop {r4}
; DISABLE: pop {pc}
; ;
; CHECK: [[ELSE_LABEL]]: @ %if.else ; CHECK: [[ELSE_LABEL]]: @ %if.else
; Shift second argument by one and store into returned register. ; Shift second argument by one and store into returned register.
; CHECK: lsls r0, r1, #1 ; CHECK: lsls r0, r1, #1
; DISABLE-NEXT: pop {r4, pc} ; DISABLE-NEXT: pop {r4}
; DISABLE-NEXT: pop {pc}
; ;
; ENABLE-NEXT: bx lr ; ENABLE-NEXT: bx lr
define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) { define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) {
entry: entry:
%tobool = icmp eq i32 %cond, 0 %tobool = icmp eq i32 %cond, 0
br i1 %tobool, label %if.else, label %for.preheader br i1 %tobool, label %if.else, label %for.preheader
for.preheader: for.preheader:
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; CHECK-NEXT: bne [[LOOP]] ; CHECK-NEXT: bne [[LOOP]]
; ;
; Next BB. ; Next BB.
; SUM << 3. ; SUM << 3.
; CHECK: lsls [[SUM]], [[SUM]], #3 ; CHECK: lsls [[SUM]], [[SUM]], #3
; ENABLE: pop {r4, lr} ; ENABLE: pop {r4, lr}
; ;
; Duplicated epilogue. ; Duplicated epilogue.
; DISABLE: pop {r4, pc} ; DISABLE: pop {r4}
; DISABLE: pop {pc}
; ;
; CHECK: [[ELSE_LABEL]]: @ %if.else ; CHECK: [[ELSE_LABEL]]: @ %if.else
; Shift second argument by one and store into returned register. ; Shift second argument by one and store into returned register.
; CHECK: lsls r0, r1, #1 ; CHECK: lsls r0, r1, #1
; DISABLE-NEXT: pop {r4, pc} ; DISABLE-NEXT: pop {r4}
; DISABLE-NEXT: pop {pc}
; ;
; ENABLE-NEXT: bx lr ; ENABLE-NEXT: bx lr
define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) #0 { define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) #0 {
entry: entry:
%tobool = icmp eq i32 %cond, 0 %tobool = icmp eq i32 %cond, 0
br i1 %tobool, label %if.else, label %if.then br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
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; CHECK-NEXT: cmp [[IV]], #0 ; CHECK-NEXT: cmp [[IV]], #0
; CHECK-NEXT: bne [[LOOP]] ; CHECK-NEXT: bne [[LOOP]]
; ;
; Next BB. ; Next BB.
; CHECK: movs r0, #0 ; CHECK: movs r0, #0
; ENABLE-NEXT: pop {r4, lr} ; ENABLE-NEXT: pop {r4, lr}
; ;
; Duplicated epilogue. ; Duplicated epilogue.
; DISABLE-NEXT: pop {r4, pc} ; DISABLE-NEXT: pop {r4}
; DISABLE-NEXT: pop {pc}
; ;
; CHECK: [[ELSE_LABEL]]: @ %if.else ; CHECK: [[ELSE_LABEL]]: @ %if.else
; Shift second argument by one and store into returned register. ; Shift second argument by one and store into returned register.
; CHECK: lsls r0, r1, #1 ; CHECK: lsls r0, r1, #1
; DISABLE-NEXT: pop {r4, pc} ; DISABLE-NEXT: pop {r4}
; DISABLE-NEXT: pop {pc}
; ;
; ENABLE-NEXT: bx lr ; ENABLE-NEXT: bx lr
define i32 @inlineAsm(i32 %cond, i32 %N) { define i32 @inlineAsm(i32 %cond, i32 %N) {
entry: entry:
%tobool = icmp eq i32 %cond, 0 %tobool = icmp eq i32 %cond, 0
br i1 %tobool, label %if.else, label %for.preheader br i1 %tobool, label %if.else, label %for.preheader
for.preheader: for.preheader:
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; CHECK: push {r1} ; CHECK: push {r1}
; CHECK-NEXT: pop {r0} ; CHECK-NEXT: pop {r0}
; CHECK: push {r1} ; CHECK: push {r1}
; CHECK-NEXT: pop {r2} ; CHECK-NEXT: pop {r2}
; CHECK: push {r1} ; CHECK: push {r1}
; CHECK-NEXT: pop {r3} ; CHECK-NEXT: pop {r3}
; CHECK-NEXT: bl ; CHECK-NEXT: bl
; CHECK-NEXT: lsls r0, r0, #3 ; CHECK-NEXT: lsls r0, r0, #3
; CHECK-NEXT: add sp, #16 ; ENABLE-NEXT: add sp, #16
; DISABLE: [[ELSE_LABEL]]: @ %if.else
; DISABLE-NEXT: lsls r0, r1, #1
; DISABLE-NEXT: [[END_LABEL:LBB[0-9_]+]]: @ %if.end
; DISABLE-NEXT: add sp, #16
; ;
; ENABLE-NEXT: pop {[[TMP]], lr} ; ENABLE-NEXT: pop {[[TMP]], lr}
; ;
; Duplicated epilogue. ; Duplicated epilogue.
; DISABLE-NEXT: pop {[[TMP]], pc} ; DISABLE-NEXT: pop {[[TMP]]}
; DISABLE-NEXT: pop {pc}
; ;
; CHECK: [[ELSE_LABEL]]: @ %if.else ; ENABLE: [[ELSE_LABEL]]: @ %if.else
; Shift second argument by one and store into returned register. ; Shift second argument by one and store into returned register.
; CHECK: lsls r0, r1, #1 ; ENABLE-NEXT: lsls r0, r1, #1
; ;
; Epilogue code. ; Epilogue code.
; ENABLE-NEXT: bx lr ; ENABLE-NEXT: bx lr
; ;
; DISABLE-NEXT: add sp, #16
; DISABLE-NEXT: pop {[[TMP]], pc}
define i32 @callVariadicFunc(i32 %cond, i32 %N) { define i32 @callVariadicFunc(i32 %cond, i32 %N) {
entry: entry:
%tobool = icmp eq i32 %cond, 0 %tobool = icmp eq i32 %cond, 0
br i1 %tobool, label %if.else, label %if.then br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
%call = tail call i32 (i32, ...) @someVariadicFunc(i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N) %call = tail call i32 (i32, ...) @someVariadicFunc(i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N)
%shl = shl i32 %call, 3 %shl = shl i32 %call, 3
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test/MC/ARM/arm-thumb-cpus.s

@ RUN: not llvm-mc -show-encoding -triple=arm-eabi < %s 2>&1 \ @ RUN: not llvm-mc -show-encoding -triple=armv2 < %s 2>&1 \
@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-ONLY @ RUN: | FileCheck %s --check-prefix=CHECK-ARM-ONLY
@ RUN: not llvm-mc -show-encoding -triple=armv3 < %s 2>&1 \
@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-ONLY
@ RUN: not llvm-mc -show-encoding -triple=armv4 < %s 2>&1 \
@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-ONLY
@ RUN: llvm-mc -show-encoding -triple=arm-eabi < %s 2>&1 \
@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-THUMB
@ RUN: llvm-mc -show-encoding -triple=armv4t < %s 2>&1 \ @ RUN: llvm-mc -show-encoding -triple=armv4t < %s 2>&1 \
@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-THUMB @ RUN: | FileCheck %s --check-prefix=CHECK-ARM-THUMB
@ RUN: llvm-mc -show-encoding -triple=arm-eabi -mcpu=cortex-a15 < %s 2>&1 \ @ RUN: llvm-mc -show-encoding -triple=arm-eabi -mcpu=cortex-a15 < %s 2>&1 \
@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-THUMB @ RUN: | FileCheck %s --check-prefix=CHECK-ARM-THUMB
@ RUN: not llvm-mc -show-encoding -triple=arm-eabi -mcpu=cortex-m3 < %s 2>&1 \ @ RUN: not llvm-mc -show-encoding -triple=arm-eabi -mcpu=cortex-m3 < %s 2>&1 \
@ RUN: | FileCheck %s --check-prefix=CHECK-THUMB-ONLY @ RUN: | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
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test/MC/ARM/crc32-thumb.s

@ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s | FileCheck %s @ RUN: llvm-mc -triple=thumbv8 -mattr=+crc -show-encoding < %s | FileCheck %s
@ RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7 @ RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
@ RUN: not llvm-mc -triple=thumbv7 -mattr=+crc -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOV8
@ RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOCRC
@ RUN: not llvm-mc -triple=thumbv8 -mattr=-crc -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOCRC @ RUN: not llvm-mc -triple=thumbv8 -mattr=-crc -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOCRC
crc32b r0, r1, r2 crc32b r0, r1, r2
crc32h r0, r1, r2 crc32h r0, r1, r2
crc32w r0, r1, r2 crc32w r0, r1, r2
@ CHECK: crc32b r0, r1, r2 @ encoding: [0xc1,0xfa,0x82,0xf0] @ CHECK: crc32b r0, r1, r2 @ encoding: [0xc1,0xfa,0x82,0xf0]
@ CHECK: crc32h r0, r1, r2 @ encoding: [0xc1,0xfa,0x92,0xf0] @ CHECK: crc32h r0, r1, r2 @ encoding: [0xc1,0xfa,0x92,0xf0]
@ CHECK: crc32w r0, r1, r2 @ encoding: [0xc1,0xfa,0xa2,0xf0] @ CHECK: crc32w r0, r1, r2 @ encoding: [0xc1,0xfa,0xa2,0xf0]
@ CHECK-V7: error: instruction requires: crc armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: crc armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: crc armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-NOV8: error: instruction requires: armv8
@ CHECK-NOV8: error: instruction requires: armv8
@ CHECK-NOV8: error: instruction requires: armv8
@ CHECK-NOCRC: error: instruction requires: crc @ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc @ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc @ CHECK-NOCRC: error: instruction requires: crc
crc32cb r0, r1, r2 crc32cb r0, r1, r2
crc32ch r0, r1, r2 crc32ch r0, r1, r2
crc32cw r0, r1, r2 crc32cw r0, r1, r2
@ CHECK: crc32cb r0, r1, r2 @ encoding: [0xd1,0xfa,0x82,0xf0] @ CHECK: crc32cb r0, r1, r2 @ encoding: [0xd1,0xfa,0x82,0xf0]
@ CHECK: crc32ch r0, r1, r2 @ encoding: [0xd1,0xfa,0x92,0xf0] @ CHECK: crc32ch r0, r1, r2 @ encoding: [0xd1,0xfa,0x92,0xf0]
@ CHECK: crc32cw r0, r1, r2 @ encoding: [0xd1,0xfa,0xa2,0xf0] @ CHECK: crc32cw r0, r1, r2 @ encoding: [0xd1,0xfa,0xa2,0xf0]
@ CHECK-V7: error: instruction requires: crc armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: crc armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: crc armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-NOV8: error: instruction requires: armv8
@ CHECK-NOV8: error: instruction requires: armv8
@ CHECK-NOV8: error: instruction requires: armv8
@ CHECK-NOCRC: error: instruction requires: crc @ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc @ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc @ CHECK-NOCRC: error: instruction requires: crc

test/MC/ARM/crc32.s

@ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s @ RUN: llvm-mc -triple=armv8 -mattr=+crc -show-encoding < %s | FileCheck %s
@ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7 @ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
@ RUN: not llvm-mc -triple=armv7 -mattr=+crc -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOV8
@ RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOCRC
@ RUN: not llvm-mc -triple=thumbv8 -mattr=-crc -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOCRC @ RUN: not llvm-mc -triple=thumbv8 -mattr=-crc -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOCRC
crc32b r0, r1, r2 crc32b r0, r1, r2
crc32h r0, r1, r2 crc32h r0, r1, r2
crc32w r0, r1, r2 crc32w r0, r1, r2
@ CHECK: crc32b r0, r1, r2 @ encoding: [0x42,0x00,0x01,0xe1] @ CHECK: crc32b r0, r1, r2 @ encoding: [0x42,0x00,0x01,0xe1]
@ CHECK: crc32h r0, r1, r2 @ encoding: [0x42,0x00,0x21,0xe1] @ CHECK: crc32h r0, r1, r2 @ encoding: [0x42,0x00,0x21,0xe1]
@ CHECK: crc32w r0, r1, r2 @ encoding: [0x42,0x00,0x41,0xe1] @ CHECK: crc32w r0, r1, r2 @ encoding: [0x42,0x00,0x41,0xe1]
@ CHECK-V7: error: instruction requires: crc armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: crc armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: crc armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-NOV8: error: instruction requires: armv8
@ CHECK-NOV8: error: instruction requires: armv8
@ CHECK-NOV8: error: instruction requires: armv8
@ CHECK-NOCRC: error: instruction requires: crc @ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc @ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc @ CHECK-NOCRC: error: instruction requires: crc
crc32cb r0, r1, r2 crc32cb r0, r1, r2
crc32ch r0, r1, r2 crc32ch r0, r1, r2
crc32cw r0, r1, r2 crc32cw r0, r1, r2
@ CHECK: crc32cb r0, r1, r2 @ encoding: [0x42,0x02,0x01,0xe1] @ CHECK: crc32cb r0, r1, r2 @ encoding: [0x42,0x02,0x01,0xe1]
@ CHECK: crc32ch r0, r1, r2 @ encoding: [0x42,0x02,0x21,0xe1] @ CHECK: crc32ch r0, r1, r2 @ encoding: [0x42,0x02,0x21,0xe1]
@ CHECK: crc32cw r0, r1, r2 @ encoding: [0x42,0x02,0x41,0xe1] @ CHECK: crc32cw r0, r1, r2 @ encoding: [0x42,0x02,0x41,0xe1]
@ CHECK-V7: error: instruction requires: crc armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: crc armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: crc armv8 @ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-NOV8: error: instruction requires: armv8
@ CHECK-NOV8: error: instruction requires: armv8
@ CHECK-NOV8: error: instruction requires: armv8
@ CHECK-NOCRC: error: instruction requires: crc @ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc @ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc @ CHECK-NOCRC: error: instruction requires: crc

test/MC/ARM/eh-directive-integrated-test.s

Show All 13 Lines
@ print(m, n, p, q, r); @ print(m, n, p, q, r);
@ } @ }
@ } @ }
@ @
@ This test case should check the unwind opcode to adjust the opcode and @ This test case should check the unwind opcode to adjust the opcode and
@ restore the general-purpose and VFP registers. @ restore the general-purpose and VFP registers.
@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \ @ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -mattr=+vfp2 -filetype=obj -o - \
@ RUN: | llvm-readobj -s -sd | FileCheck %s @ RUN: | llvm-readobj -s -sd | FileCheck %s
@------------------------------------------------------------------------------- @-------------------------------------------------------------------------------
@ Assembly without frame pointer elimination @ Assembly without frame pointer elimination
@------------------------------------------------------------------------------- @-------------------------------------------------------------------------------
.syntax unified .syntax unified
.section .TEST1 .section .TEST1
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test/MC/ARM/eh-directive-section-comdat.s

@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \ @ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -mattr=+vfp2 -filetype=obj -o - \
@ RUN: | llvm-readobj -s -sd -sr -t | FileCheck %s @ RUN: | llvm-readobj -s -sd -sr -t | FileCheck %s
@ Check the .group section for the function in comdat section. @ Check the .group section for the function in comdat section.
@ In C++, the instantiation of the template will come with linkonce (or @ In C++, the instantiation of the template will come with linkonce (or
@ linkonce_odr) linkage, so that the linker can remove the duplicated @ linkonce_odr) linkage, so that the linker can remove the duplicated
@ instantiation. When the exception handling is enabled on those function, @ instantiation. When the exception handling is enabled on those function,
@ we have to group the corresponding .ARM.extab and .ARM.exidx with the @ we have to group the corresponding .ARM.extab and .ARM.exidx with the
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test/MC/ARM/eh-directive-vsave.s

@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \ @ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -mattr=+vfp2 -filetype=obj -o - \
@ RUN: | llvm-readobj -s -sd -sr | FileCheck %s @ RUN: | llvm-readobj -s -sd -sr | FileCheck %s
@ Check the .vsave directive @ Check the .vsave directive
@ The .vsave directive records the VFP registers which are pushed to the @ The .vsave directive records the VFP registers which are pushed to the
@ stack. There are two different opcodes: @ stack. There are two different opcodes:
@ @
@ 0xC800: pop d[(16+x+y):(16+x)] @ d[16+x+y]-d[16+x] must be consecutive @ 0xC800: pop d[(16+x+y):(16+x)] @ d[16+x+y]-d[16+x] must be consecutive
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test/MC/ARM/single-precision-fp.s

@ RUN: not llvm-mc < %s -triple thumbv8-unknown-unknown -show-encoding -mattr=+fp-only-sp,-neon 2> %t > %t2 @ RUN: not llvm-mc < %s -triple thumbv8-unknown-unknown -show-encoding -mattr=+fp-armv8,+fp-only-sp,-neon 2> %t > %t2
@ RUN: FileCheck %s < %t --check-prefix=CHECK-ERRORS @ RUN: FileCheck %s < %t --check-prefix=CHECK-ERRORS
@ RUN: FileCheck %s < %t2 @ RUN: FileCheck %s < %t2
vadd.f64 d0, d1, d2 vadd.f64 d0, d1, d2
vsub.f64 d2, d3, d4 vsub.f64 d2, d3, d4
vdiv.f64 d4, d5, d6 vdiv.f64 d4, d5, d6
vmul.f64 d6, d7, d8 vmul.f64 d6, d7, d8
vnmul.f64 d8, d9, d10 vnmul.f64 d8, d9, d10
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test/MC/ARM/vmov-vmvn-byte-replicate.s

@ PR18921, "vmov" part. @ PR18921, "vmov" part.
@ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s @ RUN: llvm-mc -triple=armv7-linux-gnueabi -mattr=+neon -show-encoding < %s | FileCheck %s
.text .text
@ CHECK: vmov.i8 d2, #0xff @ encoding: [0x1f,0x2e,0x87,0xf3] @ CHECK: vmov.i8 d2, #0xff @ encoding: [0x1f,0x2e,0x87,0xf3]
@ CHECK: vmov.i8 q2, #0xff @ encoding: [0x5f,0x4e,0x87,0xf3] @ CHECK: vmov.i8 q2, #0xff @ encoding: [0x5f,0x4e,0x87,0xf3]
@ CHECK: vmov.i8 d2, #0xab @ encoding: [0x1b,0x2e,0x82,0xf3] @ CHECK: vmov.i8 d2, #0xab @ encoding: [0x1b,0x2e,0x82,0xf3]
@ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3] @ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3]
@ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3] @ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3]
@ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3] @ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3]
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test/MC/Disassembler/ARM/armv8.1a.txt

# RUN: llvm-mc -triple armv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V81a # RUN: llvm-mc -triple armv8 -mattr=+v8.1a,+neon --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V81a
# RUN: not llvm-mc -triple armv8 -mattr=+v8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8 # RUN: not llvm-mc -triple armv8 -mattr=+v8,+neon --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8
[0x54,0x0b,0x12,0xf3] [0x54,0x0b,0x12,0xf3]
[0x12,0x0b,0x21,0xf3] [0x12,0x0b,0x21,0xf3]
[0x54,0x0c,0x12,0xf3] [0x54,0x0c,0x12,0xf3]
[0x12,0x0c,0x21,0xf3] [0x12,0x0c,0x21,0xf3]
# CHECK-V81a: vqrdmlah.s16 q0, q1, q2 # CHECK-V81a: vqrdmlah.s16 q0, q1, q2
# CHECK-V81a: vqrdmlah.s32 d0, d1, d2 # CHECK-V81a: vqrdmlah.s32 d0, d1, d2
# CHECK-V81a: vqrdmlsh.s16 q0, q1, q2 # CHECK-V81a: vqrdmlsh.s16 q0, q1, q2
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test/MC/Disassembler/ARM/crc32-thumb.txt

# RUN: llvm-mc --disassemble %s -triple=thumbv8 2>&1 | FileCheck %s # RUN: llvm-mc --disassemble %s -triple=thumbv8 -mattr=+crc 2>&1 | FileCheck %s
# CHECK: crc32b r0, r1, r2 # CHECK: crc32b r0, r1, r2
# CHECK: crc32h r0, r1, r2 # CHECK: crc32h r0, r1, r2
# CHECK: crc32w r0, r1, r2 # CHECK: crc32w r0, r1, r2
# CHECK: crc32cb r0, r1, r2 # CHECK: crc32cb r0, r1, r2
# CHECK: crc32ch r0, r1, r2 # CHECK: crc32ch r0, r1, r2
# CHECK: crc32cw r0, r1, r2 # CHECK: crc32cw r0, r1, r2
0xc1 0xfa 0x82 0xf0 0xc1 0xfa 0x82 0xf0
0xc1 0xfa 0x92 0xf0 0xc1 0xfa 0x92 0xf0
0xc1 0xfa 0xa2 0xf0 0xc1 0xfa 0xa2 0xf0
0xd1 0xfa 0x82 0xf0 0xd1 0xfa 0x82 0xf0
0xd1 0xfa 0x92 0xf0 0xd1 0xfa 0x92 0xf0
0xd1 0xfa 0xa2 0xf0 0xd1 0xfa 0xa2 0xf0

test/MC/Disassembler/ARM/crc32.txt

# RUN: llvm-mc --disassemble %s -triple=armv8 2>&1 | FileCheck %s # RUN: llvm-mc --disassemble %s -triple=armv8 -mattr=+crc 2>&1 | FileCheck %s
# CHECK: crc32b r0, r1, r2 # CHECK: crc32b r0, r1, r2
# CHECK: crc32h r0, r1, r2 # CHECK: crc32h r0, r1, r2
# CHECK: crc32w r0, r1, r2 # CHECK: crc32w r0, r1, r2
# CHECK: crc32cb r0, r1, r2 # CHECK: crc32cb r0, r1, r2
# CHECK: crc32ch r0, r1, r2 # CHECK: crc32ch r0, r1, r2
# CHECK: crc32cw r0, r1, r2 # CHECK: crc32cw r0, r1, r2
0x42 0x00 0x01 0xe1 0x42 0x00 0x01 0xe1
0x42 0x00 0x21 0xe1 0x42 0x00 0x21 0xe1
0x42 0x00 0x41 0xe1 0x42 0x00 0x41 0xe1
0x42 0x02 0x01 0xe1 0x42 0x02 0x01 0xe1
0x42 0x02 0x21 0xe1 0x42 0x02 0x21 0xe1
0x42 0x02 0x41 0xe1 0x42 0x02 0x41 0xe1

test/MC/Disassembler/ARM/invalid-FSTMX-arm.txt

# RUN: llvm-mc --disassemble %s -triple=armv7 2>&1 | FileCheck %s -check-prefix=CHECK-WARN # RUN: llvm-mc --disassemble %s -triple=armv7 -mattr=+vfp2 2>&1 | FileCheck %s -check-prefix=CHECK-WARN
# RUN: llvm-mc --disassemble %s -triple=armv7 2>&1 | FileCheck %s # RUN: llvm-mc --disassemble %s -triple=armv7 -mattr=+vfp2 2>&1 | FileCheck %s
# offset=1 # offset=1
# CHECK-WARN: potentially undefined # CHECK-WARN: potentially undefined
# CHECK-WARN: 0x01 0xdb 0x84 0xec # CHECK-WARN: 0x01 0xdb 0x84 0xec
# CHECK: fstmiax r4, {d13} # CHECK: fstmiax r4, {d13}
0x01 0xdb 0x84 0xec 0x01 0xdb 0x84 0xec

test/MC/Disassembler/ARM/neont-VLD-reencoding.txt

# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple thumbv7 -mattr=+neon -show-encoding -disassemble < %s | FileCheck %s
0xa0 0xf9 0x00 0x00 0xa0 0xf9 0x00 0x00
0xa0 0xf9 0x20 0x00 0xa0 0xf9 0x20 0x00
0xa0 0xf9 0x40 0x00 0xa0 0xf9 0x40 0x00
0xa0 0xf9 0x60 0x00 0xa0 0xf9 0x60 0x00
0xa0 0xf9 0x80 0x00 0xa0 0xf9 0x80 0x00
0xa0 0xf9 0xa0 0x00 0xa0 0xf9 0xa0 0x00
0xa0 0xf9 0xc0 0x00 0xa0 0xf9 0xc0 0x00
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test/MC/Disassembler/ARM/neont-VST-reencoding.txt

# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple thumbv7 -mattr=+neon -show-encoding -disassemble < %s | FileCheck %s
0x80 0xf9 0x00 0x00 0x80 0xf9 0x00 0x00
0x81 0xf9 0x21 0x10 0x81 0xf9 0x21 0x10
0x81 0xf9 0x42 0x10 0x81 0xf9 0x42 0x10
0x81 0xf9 0x61 0x20 0x81 0xf9 0x61 0x20
0x82 0xf9 0x82 0x20 0x82 0xf9 0x82 0x20
0x82 0xf9 0xa1 0x10 0x82 0xf9 0xa1 0x10
0x82 0xf9 0xc2 0x20 0x82 0xf9 0xc2 0x20
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test/MC/Disassembler/ARM/thumb-v8.1a.txt

# RUN: llvm-mc -triple thumbv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V81a # RUN: llvm-mc -triple thumbv8 -mattr=+v8.1a,+neon --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V81a
# RUN: not llvm-mc -triple thumbv8 -mattr=+v8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8 # RUN: not llvm-mc -triple thumbv8 -mattr=+v8,+neon --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8
[0x11,0xff,0x12,0x0b] [0x11,0xff,0x12,0x0b]
# CHECK-V81a: vqrdmlah.s16 d0, d1, d2 # CHECK-V81a: vqrdmlah.s16 d0, d1, d2
# CHECK-V8: warning: invalid instruction encoding # CHECK-V8: warning: invalid instruction encoding
# CHECK-V8: [0x11,0xff,0x12,0x0b] # CHECK-V8: [0x11,0xff,0x12,0x0b]
# CHECK-V8: ^ # CHECK-V8: ^
[0x21,0xff,0x12,0x0b] [0x21,0xff,0x12,0x0b]
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test/Transforms/LoopVectorize/ARM/interleaved_cost.ll

; RUN: opt -S -debug-only=loop-vectorize -loop-vectorize -instcombine -enable-interleaved-mem-accesses=true < %s 2>&1 | FileCheck %s ; RUN: opt -mattr=+neon -S -debug-only=loop-vectorize -loop-vectorize -instcombine -enable-interleaved-mem-accesses=true < %s 2>&1 | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
target triple = "armv8--linux-gnueabihf" target triple = "armv8--linux-gnueabihf"
@AB = common global [1024 x i8] zeroinitializer, align 4 @AB = common global [1024 x i8] zeroinitializer, align 4
@CD = common global [1024 x i8] zeroinitializer, align 4 @CD = common global [1024 x i8] zeroinitializer, align 4
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