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Differential D115796

[mlir][LLVMIR] Add `llvm.umin` and `llvm.umax` intrinsics
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Authored by zero9178 on Dec 15 2021, 4:14 AM.

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Reviewers
ftynse
mehdi_amini
wsmoses
rriddle
Commits
rG1d10bddfa336: [mlir][LLVMIR] Add `llvm.umin` and `llvm.umax` intrinsics
Summary

Ops for the signed counterparts "llvm.smin" and "llvm.smax" already exist. This patch adds the unsigned versions as well.

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Event Timeline

zero9178 created this revision.Dec 15 2021, 4:14 AM
Herald added subscribers: sdasgup3, wenzhicui, wrengr and 18 others. · View Herald TranscriptDec 15 2021, 4:14 AM
zero9178 requested review of this revision.Dec 15 2021, 4:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 15 2021, 4:14 AM
Herald added subscribers: stephenneuendorffer, nicolasvasilache. · View Herald Transcript
Harbormaster completed remote builds in B139412: Diff 394524.Dec 15 2021, 4:39 AM
ftynse accepted this revision.Dec 15 2021, 4:47 AM
This revision is now accepted and ready to land.Dec 15 2021, 4:47 AM
Closed by commit rG1d10bddfa336: [mlir][LLVMIR] Add `llvm.umin` and `llvm.umax` intrinsics (authored by zero9178). · Explain WhyDec 15 2021, 4:54 AM
This revision was automatically updated to reflect the committed changes.
zero9178 added a commit: rG1d10bddfa336: [mlir][LLVMIR] Add `llvm.umin` and `llvm.umax` intrinsics.

Revision Contents

PathSize
mlir/
include/
mlir/
Dialect/
LLVMIR/
2 lines
test/
Target/
LLVMIR/
18 lines

Diff 394524

mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td

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def LLVM_CountTrailingZerosOp : LLVM_CountZerosIntrinsicOp<"cttz">; def LLVM_CountTrailingZerosOp : LLVM_CountZerosIntrinsicOp<"cttz">;
def LLVM_CtPopOp : LLVM_UnaryIntrinsicOp<"ctpop">; def LLVM_CtPopOp : LLVM_UnaryIntrinsicOp<"ctpop">;
def LLVM_MaxNumOp : LLVM_BinarySameArgsIntrinsicOp<"maxnum">; def LLVM_MaxNumOp : LLVM_BinarySameArgsIntrinsicOp<"maxnum">;
def LLVM_MinNumOp : LLVM_BinarySameArgsIntrinsicOp<"minnum">; def LLVM_MinNumOp : LLVM_BinarySameArgsIntrinsicOp<"minnum">;
def LLVM_MaximumOp : LLVM_BinarySameArgsIntrinsicOp<"maximum">; def LLVM_MaximumOp : LLVM_BinarySameArgsIntrinsicOp<"maximum">;
def LLVM_MinimumOp : LLVM_BinarySameArgsIntrinsicOp<"minimum">; def LLVM_MinimumOp : LLVM_BinarySameArgsIntrinsicOp<"minimum">;
def LLVM_SMaxOp : LLVM_BinarySameArgsIntrinsicOp<"smax">; def LLVM_SMaxOp : LLVM_BinarySameArgsIntrinsicOp<"smax">;
def LLVM_SMinOp : LLVM_BinarySameArgsIntrinsicOp<"smin">; def LLVM_SMinOp : LLVM_BinarySameArgsIntrinsicOp<"smin">;
def LLVM_UMaxOp : LLVM_BinarySameArgsIntrinsicOp<"umax">;
def LLVM_UMinOp : LLVM_BinarySameArgsIntrinsicOp<"umin">;
def LLVM_MemcpyOp : LLVM_ZeroResultIntrOp<"memcpy", [0, 1, 2]> { def LLVM_MemcpyOp : LLVM_ZeroResultIntrOp<"memcpy", [0, 1, 2]> {
let arguments = (ins LLVM_Type:$dst, LLVM_Type:$src, LLVM_Type:$len, let arguments = (ins LLVM_Type:$dst, LLVM_Type:$src, LLVM_Type:$len,
LLVM_Type:$isVolatile); LLVM_Type:$isVolatile);
} }
def LLVM_MemcpyInlineOp : LLVM_ZeroResultIntrOp<"memcpy.inline", [0, 1, 2]> { def LLVM_MemcpyInlineOp : LLVM_ZeroResultIntrOp<"memcpy.inline", [0, 1, 2]> {
let arguments = (ins LLVM_Type:$dst, LLVM_Type:$src, LLVM_Type:$len, let arguments = (ins LLVM_Type:$dst, LLVM_Type:$src, LLVM_Type:$len,
LLVM_Type:$isVolatile); LLVM_Type:$isVolatile);
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mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir

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llvm.func @smin_test(%arg0: i32, %arg1: i32, %arg2: vector<8xi32>, %arg3: vector<8xi32>) { llvm.func @smin_test(%arg0: i32, %arg1: i32, %arg2: vector<8xi32>, %arg3: vector<8xi32>) {
// CHECK: call i32 @llvm.smin.i32 // CHECK: call i32 @llvm.smin.i32
"llvm.intr.smin"(%arg0, %arg1) : (i32, i32) -> i32 "llvm.intr.smin"(%arg0, %arg1) : (i32, i32) -> i32
// CHECK: call <8 x i32> @llvm.smin.v8i32 // CHECK: call <8 x i32> @llvm.smin.v8i32
"llvm.intr.smin"(%arg2, %arg3) : (vector<8xi32>, vector<8xi32>) -> vector<8xi32> "llvm.intr.smin"(%arg2, %arg3) : (vector<8xi32>, vector<8xi32>) -> vector<8xi32>
llvm.return llvm.return
} }
// CHECK-LABEL: @umax_test
llvm.func @umax_test(%arg0: i32, %arg1: i32, %arg2: vector<8xi32>, %arg3: vector<8xi32>) {
// CHECK: call i32 @llvm.umax.i32
"llvm.intr.umax"(%arg0, %arg1) : (i32, i32) -> i32
// CHECK: call <8 x i32> @llvm.umax.v8i32
"llvm.intr.umax"(%arg2, %arg3) : (vector<8xi32>, vector<8xi32>) -> vector<8xi32>
llvm.return
}
// CHECK-LABEL: @umin_test
llvm.func @umin_test(%arg0: i32, %arg1: i32, %arg2: vector<8xi32>, %arg3: vector<8xi32>) {
// CHECK: call i32 @llvm.umin.i32
"llvm.intr.umin"(%arg0, %arg1) : (i32, i32) -> i32
// CHECK: call <8 x i32> @llvm.umin.v8i32
"llvm.intr.umin"(%arg2, %arg3) : (vector<8xi32>, vector<8xi32>) -> vector<8xi32>
llvm.return
}
// CHECK-LABEL: @vector_reductions // CHECK-LABEL: @vector_reductions
llvm.func @vector_reductions(%arg0: f32, %arg1: vector<8xf32>, %arg2: vector<8xi32>) { llvm.func @vector_reductions(%arg0: f32, %arg1: vector<8xf32>, %arg2: vector<8xi32>) {
// CHECK: call i32 @llvm.vector.reduce.add.v8i32 // CHECK: call i32 @llvm.vector.reduce.add.v8i32
"llvm.intr.vector.reduce.add"(%arg2) : (vector<8xi32>) -> i32 "llvm.intr.vector.reduce.add"(%arg2) : (vector<8xi32>) -> i32
// CHECK: call i32 @llvm.vector.reduce.and.v8i32 // CHECK: call i32 @llvm.vector.reduce.and.v8i32
"llvm.intr.vector.reduce.and"(%arg2) : (vector<8xi32>) -> i32 "llvm.intr.vector.reduce.and"(%arg2) : (vector<8xi32>) -> i32
// CHECK: call float @llvm.vector.reduce.fmax.v8f32 // CHECK: call float @llvm.vector.reduce.fmax.v8f32
"llvm.intr.vector.reduce.fmax"(%arg1) : (vector<8xf32>) -> f32 "llvm.intr.vector.reduce.fmax"(%arg1) : (vector<8xf32>) -> f32
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