[MachineVerifier] Undef subreg operands do not require subranges

[foad]

Summary

D112556 added verification that the live interval for a subreg operand
must have subranges. This patch fixes a corner case, where if all subreg
operands for a particular register are undef uses then no subranges
are required. This matches how LiveIntervalCalc would build the live
intervals in the first place, since an undef use is not considered
to read the register.

Before this patch, CodeGen/AMDGPU/no-remat-indirect-mov.mir would fail
with -early-live-intervals:

1. After Live Interval Analysis

...

• • Bad machine code: Live interval for subreg operand has no subranges ***
• function: index_vgpr_waterfall_loop
• basic block: %bb.1 (0x6a9a968) [352B;496B)
• instruction: 432B %24:vgpr_32 = V_MOV_B32_e32 undef %18.sub0:vreg_512, implicit $exec, implicit %18:vreg_512, implicit $m0
• operand 1: undef %18.sub0:vreg_512

[arsenm]

llvm/lib/CodeGen/MachineVerifier.cpp

2232–2233

undef subreg defs do read the register (i.e. see the below readsReg check)

[foad]

Only ignore undef uses, not undef defs.

[foad]

llvm/lib/CodeGen/MachineVerifier.cpp

2232–2233

They don't read it but they do write it, so we should still require subranges. Fixed now.

llvm/lib/CodeGen/MachineVerifier.cpp

void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
   const MachineInstr *MI = MO->getParent();
   const Register Reg = MO->getReg();
   const unsigned SubRegIdx = MO->getSubReg();
 
   const LiveInterval *LI = nullptr;
   if (LiveInts && Reg.isVirtual()) {
     if (LiveInts->hasInterval(Reg)) {
       LI = &LiveInts->getInterval(Reg);
-      if (SubRegIdx != 0 && !LI->empty() && !LI->hasSubRanges() &&
-          MRI->shouldTrackSubRegLiveness(Reg))
+      if (SubRegIdx != 0 && (MO->isDef() || !MO->isUndef()) && !LI->empty() &&
+          !LI->hasSubRanges() && MRI->shouldTrackSubRegLiveness(Reg))
         report("Live interval for subreg operand has no subranges", MO, MONum);
     } else {
       report("Virtual register has no live interval", MO, MONum);
     }
   }
 
   // Both use and def operands can read a register.
   if (MO->readsReg()) {

llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900  -start-after=phi-node-elimination -stop-before=greedy -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900  -start-after=phi-node-elimination -stop-before=greedy -early-live-intervals -o - %s | FileCheck -check-prefix=GFX9 %s
 
 # Make sure that the V_MOV_B32 isn't rematerialized out of the loop. This was also breaking RenameIndependentSubregisters which missed the use of all subregisters.
 
 ---
 name: index_vgpr_waterfall_loop
 tracksRegLiveness: true
 liveins:
   - { reg: '$vgpr0', virtual-reg: '%0' }