[M68k] Adopt the new VarLenCodeEmitterGen for arithmetic instructions

[myhsu]

Summary

Following up D115128 , this patch refactors all the existing M68k arithmetic instructions to use the new VarLenCodeEmitterGen infrastructure.

This patch is tested by the existing MC test cases.

Note that one of the codegen tests needed to be updated because the ordering of two equivalent instructions were switched.

[myhsu]

Update according to the latest changes in D115128.

[myhsu]

Removed unused template arguments

[RKSimon]

llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp

91

Can this be replaced with (and add an assert message):

assert(Op.isValid() && (Op.isReg() || (Op.isImm()) && "Unsupported operand type");

[myhsu]

• Fixed minor issues in M68kMCCodeEmitter.cpp
• Temporarily disable all disassembler tests. Since our current disassembler actually relies on code-beads.

llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp

91

I prefer to use llvm_unreachable at the final else branch.

[ricky26]

LGTM

llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp

95–99

Is there any reason we can't do this? (Does it perform any worse against APInt?)

Very minor but it reads slightly better to me.

[myhsu]

Addressed feedbacks and some formatting.

llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp

95–99

Does it perform any worse against APInt?

nah I don't think so.

[RKSimon]

llvm/lib/Target/M68k/M68kInstrArithmetic.td

71

It seems a shame to lose descriptions on the encoding like the above.

[myhsu]

Adding back comments regarding instruction formats.

llvm/lib/Target/M68k/M68kInstrArithmetic.td

71

right, I shouldn't remove them.

[RKSimon]

llvm/test/MC/Disassembler/M68k/instructions.txt

4

it seems a bad move to lose test coverage during transition - could we at least split the test file so only the arithmetic instructions are affected?

[myhsu]

llvm/test/MC/Disassembler/M68k/instructions.txt

4

Indeed, let me separate this file by instruction categories, then rebase this patch on top of it.

[myhsu]

Only XFAIL arithmetic disassembler tests rather than all the test cases.

[RKSimon]

LGTM cheers

llvm/lib/Target/M68k/CMakeLists.txt

 add_llvm_component_group(M68k)
 
 set(LLVM_TARGET_DEFINITIONS M68k.td)
 
 tablegen(LLVM M68kGenGlobalISel.inc       -gen-global-isel)
 tablegen(LLVM M68kGenRegisterInfo.inc     -gen-register-info)
 tablegen(LLVM M68kGenRegisterBank.inc     -gen-register-bank)
 tablegen(LLVM M68kGenInstrInfo.inc        -gen-instr-info)
 tablegen(LLVM M68kGenSubtargetInfo.inc    -gen-subtarget)
 tablegen(LLVM M68kGenMCCodeBeads.inc      -gen-code-beads)
+tablegen(LLVM M68kGenMCCodeEmitter.inc    -gen-emitter)
 tablegen(LLVM M68kGenMCPseudoLowering.inc -gen-pseudo-lowering)
 tablegen(LLVM M68kGenDAGISel.inc          -gen-dag-isel)
 tablegen(LLVM M68kGenCallingConv.inc      -gen-callingconv)
 tablegen(LLVM M68kGenAsmWriter.inc        -gen-asm-writer)
 tablegen(LLVM M68kGenAsmMatcher.inc       -gen-asm-matcher)
 
 add_public_tablegen_target(M68kCommonTableGen)
 

llvm/lib/Target/M68k/M68kInstrArithmetic.td

 ///   [ ] - was not touched at all
 ///   [!] - requires extarnal stuff implemented
 ///   [~] - functional implementation
 ///   [X] - complete implementation
 ///
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
-// Encoding
+// OPMODE Encoding
 //===----------------------------------------------------------------------===//
+class MxOpModeEncoding<bits<3> encoding> {
+ bits<3> Value = encoding;
+}
 
-/// Encoding for Normal forms
-/// ----------------------------------------------------
-///  F  E  D  C | B  A  9 | 8  7  6 | 5  4  3 | 2  1  0
-/// ----------------------------------------------------
-///             |         |         | EFFECTIVE ADDRESS
-///  x  x  x  x |   REG   | OP MODE |   MODE  |   REG
-/// ----------------------------------------------------
-class MxArithEncoding<MxBead4Bits CMD, MxEncOpMode OPMODE, MxBead REG,
-                      MxEncEA EA, MxEncExt EXT>
-    : MxEncoding<EA.Reg, EA.DA, EA.Mode, OPMODE.B0, OPMODE.B1, OPMODE.B2, REG,
-                 CMD,EXT.Imm, EXT.B8, EXT.Scale, EXT.WL, EXT.DAReg>;
-
-/// Encoding for Extended forms
-/// ------------------------------------------------------
-///  F  E  D  C | B  A  9 | 8 | 7  6 | 5  4 | 3 | 2  1  0
-/// ------------------------------------------------------
-///  x  x  x  x |  REG Rx | 1 | SIZE | 0  0 | M |  REG Ry
-/// ------------------------------------------------------
-/// Rx - destination
-/// Ry - source
-/// M  - address mode switch
-class MxArithXEncoding<MxBead4Bits CMD, MxEncSize SIZE, MxBead1Bit MODE,
-                       MxBeadDReg SRC, MxBeadDReg DST>
-    : MxEncoding<SRC, MODE, MxBead2Bits<0b00>, SIZE, MxBead1Bit<0b1>, DST, CMD>;
+// op EA, Dn
+def MxOpMode8_d_EA  : MxOpModeEncoding<0b000>;
+def MxOpMode16_d_EA : MxOpModeEncoding<0b001>;
+def MxOpMode32_d_EA : MxOpModeEncoding<0b010>;
+
+// op Dn, EA
+def MxOpMode8_EA_d  : MxOpModeEncoding<0b100>;
+def MxOpMode16_EA_d : MxOpModeEncoding<0b101>;
+def MxOpMode32_EA_d : MxOpModeEncoding<0b110>;
+
+// op EA, An
+def MxOpMode16_a_EA : MxOpModeEncoding<0b011>;
+def MxOpMode32_a_EA : MxOpModeEncoding<0b111>;
 
-/// Encoding for Immediate forms
-/// ---------------------------------------------------
-///  F  E  D  C  B  A  9  8 | 7  6 | 5  4  3 | 2  1  0
-/// ---------------------------------------------------
-///                         |      | EFFECTIVE ADDRESS
-///  x  x  x  x  x  x  x  x | SIZE |   MODE  |   REG
-/// ---------------------------------------------------
-///     16-BIT WORD DATA    |     8-BIT BYTE DATA
-/// ---------------------------------------------------
-///                 32-BIT LONG DATA
-/// ---------------------------------------------------
-/// NOTE It is used to store an immediate to memory, imm-to-reg are handled with
-/// normal version
-class MxArithImmEncoding<MxBead4Bits CMD, MxEncSize SIZE,
-                         MxEncEA DST_EA, MxEncExt DST_EXT, MxEncExt SRC_EXT>
-    : MxEncoding<DST_EA.Reg, DST_EA.DA, DST_EA.Mode, SIZE, CMD, MxBead4Bits<0>,
-                 // Source
-                 SRC_EXT.Imm, SRC_EXT.B8, SRC_EXT.Scale,
-                 SRC_EXT.WL, SRC_EXT.DAReg,
-                 // Destination
-                 DST_EXT.Imm, DST_EXT.B8, DST_EXT.Scale,
-                 DST_EXT.WL, DST_EXT.DAReg>;
 
+//===----------------------------------------------------------------------===//
+// Encoding
+//===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // Add/Sub
 //===----------------------------------------------------------------------===//
 
 let Defs = [CCR] in {
 let Constraints = "$src = $dst" in {
 
 // $reg, $ccr <- $reg op $reg
-class MxBiArOp_RFRR_xEA<string MN, SDNode NODE, MxType DST_TYPE, MxType SRC_TYPE,
-                        bits<4> CMD, MxBead REG>
+class MxBiArOp_R_RR_xEA<string MN, SDNode NODE, MxType DST_TYPE, MxType SRC_TYPE,
+                        bits<4> CMD>
     : MxInst<(outs DST_TYPE.ROp:$dst), (ins DST_TYPE.ROp:$src, SRC_TYPE.ROp:$opd),
              MN#"."#DST_TYPE.Prefix#"\t$opd, $dst",
-             [(set DST_TYPE.VT:$dst, CCR, (NODE DST_TYPE.VT:$src, SRC_TYPE.VT:$opd))],
-             MxArithEncoding<MxBead4Bits<CMD>,
-                             !cast<MxEncOpMode>("MxOpMode"#DST_TYPE.Size#DST_TYPE.RLet#"EA"),
-                             REG,
-                             !cast<MxEncEA>("MxEncEA"#SRC_TYPE.RLet#"_2"),
-                             MxExtEmpty>>;
+             [(set DST_TYPE.VT:$dst, CCR, (NODE DST_TYPE.VT:$src, SRC_TYPE.VT:$opd))]> {
+  let Inst = (descend
+    CMD, (operand "$dst", 3),
+    !cast<MxOpModeEncoding>("MxOpMode"#DST_TYPE.Size#"_"#DST_TYPE.RLet#"_EA").Value,
+    (descend /*MODE without last bit*/0b00,
+             /*REGISTER prefixed with D/A bit*/(operand "$opd", 4))
+  );
+}
 
 /// This Op is similar to the one above except it uses reversed opmode, some
 /// commands(e.g. eor) do not support dEA or rEA modes and require EAd for
 /// register only operations.
 /// NOTE when using dd commands it is irrelevant which opmode to use(as it seems)
 /// but some opcodes support address register and some do not which creates this
 /// mess.
-class MxBiArOp_RFRR_EAd<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
+class MxBiArOp_R_RR_EAd<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd),
              MN#"."#TYPE.Prefix#"\t$opd, $dst",
-             [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))],
-             MxArithEncoding<MxBead4Bits<CMD>,
-                             !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"EAd"),
-                             MxBeadDReg<2>, MxEncEAd_0, MxExtEmpty>>;
+             [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))]> {
+  let Inst = (descend
+    CMD, (operand "$opd", 3),
+    !cast<MxOpModeEncoding>("MxOpMode"#TYPE.Size#"_EA_"#TYPE.RLet).Value,
+    /*Destination can only be a data register*/
+    /*MODE*/0b000,
+    /*REGISTER*/(operand "$dst", 3));
+}
 
 // $reg <- $reg op $imm
-class MxBiArOp_RFRI_xEA<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
+class MxBiArOp_R_RI_xEA<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.IOp:$opd),
              MN#"."#TYPE.Prefix#"\t$opd, $dst",
-             [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))],
-             MxArithEncoding<MxBead4Bits<CMD>,
-                             !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
-                             MxBeadDReg<0>, MxEncEAi,
-                             !cast<MxEncExt>("MxExtI"#TYPE.Size#"_2")>>;
+             [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))]> {
+  let Inst = (ascend
+    (descend CMD, (operand "$dst", 3),
+             !cast<MxOpModeEncoding>("MxOpMode"#TYPE.Size#"_"#TYPE.RLet#"_EA").Value,
+             MxEncAddrMode_i<"opd", TYPE.Size>.EA),
+    MxEncAddrMode_i<"opd", TYPE.Size>.Supplement
+  );
+}
 
 // Again, there are two ways to write an immediate to Dn register either dEA
 // opmode or using *I encoding, and again some instrucitons also support address
 // registers some do not.
-class MxBiArOp_RFRI<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
+class MxBiArOp_R_RI<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.IOp:$opd),
              MN#"i."#TYPE.Prefix#"\t$opd, $dst",
-             [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))],
-             MxArithImmEncoding<MxBead4Bits<CMD>, !cast<MxEncSize>("MxEncSize"#TYPE.Size),
-                                !cast<MxEncEA>("MxEncEA"#TYPE.RLet#"_0"), MxExtEmpty,
-                                !cast<MxEncExt>("MxExtI"#TYPE.Size#"_2")>>;
+             [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))]> {
+  let Inst = (ascend
+    (descend 0b0000, CMD,
+             !cast<MxNewEncSize>("MxNewEncSize"#TYPE.Size).Value,
+             // The destination cannot be address register, so it's always
+             // the MODE for data register direct mode.
+             /*MODE*/0b000,
+             /*REGISTER*/(operand "$dst", 3)),
+    // Source (i.e. immediate value) encoding
+    MxEncAddrMode_i<"opd", TYPE.Size>.Supplement
+  );
+}
 
 let mayLoad = 1 in
-class MxBiArOp_RFRM<string MN, SDNode NODE, MxType TYPE, MxOperand OPD, ComplexPattern PAT,
-                    bits<4> CMD, MxEncEA EA, MxEncExt EXT>
+class MxBiArOp_R_RM<string MN, SDNode NODE, MxType TYPE, MxOperand OPD, ComplexPattern PAT,
+                    bits<4> CMD, MxEncMemOp SRC_ENC>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, OPD:$opd),
              MN#"."#TYPE.Prefix#"\t$opd, $dst",
-             [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, (TYPE.Load PAT:$opd)))],
-             MxArithEncoding<MxBead4Bits<CMD>,
-                             !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
-                             MxBeadDReg<0>, EA, EXT>>;
-
+             [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, (TYPE.Load PAT:$opd)))]> {
+  let Inst = (ascend
+    (descend CMD, (operand "$dst", 3),
+             !cast<MxOpModeEncoding>("MxOpMode"#TYPE.Size#"_"#TYPE.RLet#"_EA").Value,
+             SRC_ENC.EA),
+    SRC_ENC.Supplement
+  );
+}
 } // Constraints
 
 let mayLoad = 1, mayStore = 1 in {
 
 // FIXME MxBiArOp_FMR/FMI cannot consume CCR from MxAdd/MxSub which leads for
 // MxAdd to survive the match and subsequent mismatch.
-class MxBiArOp_FMR<string MN, SDNode NODE, MxType TYPE,
-                   MxOperand MEMOpd, ComplexPattern MEMPat,
-                   bits<4> CMD, MxEncEA EA, MxEncExt EXT>
+class MxBiArOp_MR<string MN, MxType TYPE,
+                  MxOperand MEMOpd, bits<4> CMD, MxEncMemOp DST_ENC>
     : MxInst<(outs), (ins MEMOpd:$dst, TYPE.ROp:$opd),
-             MN#"."#TYPE.Prefix#"\t$opd, $dst",
-             [],
-             MxArithEncoding<MxBead4Bits<CMD>,
-                             !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"EA"#TYPE.RLet),
-                             MxBeadDReg<1>, EA, EXT>>;
-
-class MxBiArOp_FMI<string MN, SDNode NODE, MxType TYPE,
-                   MxOperand MEMOpd, ComplexPattern MEMPat,
-                   bits<4> CMD, MxEncEA MEMEA, MxEncExt MEMExt>
+             MN#"."#TYPE.Prefix#"\t$opd, $dst", []> {
+  let Inst = (ascend
+    (descend CMD, (operand "$opd", 3),
+             !cast<MxOpModeEncoding>("MxOpMode"#TYPE.Size#"_EA_"#TYPE.RLet).Value,
+             DST_ENC.EA),
+    DST_ENC.Supplement
+  );
+}
+
+class MxBiArOp_MI<string MN, MxType TYPE,
+                  MxOperand MEMOpd, bits<4> CMD, MxEncMemOp DST_ENC>
     : MxInst<(outs), (ins MEMOpd:$dst, TYPE.IOp:$opd),
-             MN#"."#TYPE.Prefix#"\t$opd, $dst",
-             [],
-             MxArithImmEncoding<MxBead4Bits<CMD>,
-                                !cast<MxEncSize>("MxEncSize"#TYPE.Size),
-                                MEMEA, MEMExt,
-                                !cast<MxEncExt>("MxExtI"#TYPE.Size#"_1")>>;
+             MN#"."#TYPE.Prefix#"\t$opd, $dst", []> {
+  let Inst = (ascend
+    (descend 0b0000, CMD,
+             !cast<MxNewEncSize>("MxNewEncSize"#TYPE.Size).Value,
+             DST_ENC.EA),
+    // Source (i.e. immediate value) encoding
+    MxEncAddrMode_i<"opd", TYPE.Size>.Supplement,
+    // Destination encoding
+    DST_ENC.Supplement
+  );
+}
 } // mayLoad, mayStore
 } // Defs = [CCR]
 
 multiclass MxBiArOp_DF<string MN, SDNode NODE, bit isComm,
                        bits<4> CMD, bits<4> CMDI> {
 
+  foreach SZ = [8, 16, 32] in {
     // op $mem, $reg
-  def NAME#"8dk"  : MxBiArOp_RFRM<MN, NODE, MxType8d,  MxType8.KOp,  MxType8.KPat,
-                                  CMD, MxEncEAk, MxExtBrief_2>;
-  def NAME#"16dk" : MxBiArOp_RFRM<MN, NODE, MxType16d, MxType16.KOp, MxType16.KPat,
-                                  CMD, MxEncEAk, MxExtBrief_2>;
-  def NAME#"32dk" : MxBiArOp_RFRM<MN, NODE, MxType32d, MxType32.KOp, MxType32.KPat,
-                                  CMD, MxEncEAk, MxExtBrief_2>;
-
-  def NAME#"8dq"  : MxBiArOp_RFRM<MN, NODE, MxType8d,  MxType8.QOp,  MxType8.QPat,
-                                  CMD, MxEncEAq, MxExtI16_2>;
-  def NAME#"16dq" : MxBiArOp_RFRM<MN, NODE, MxType16d, MxType16.QOp, MxType16.QPat,
-                                  CMD, MxEncEAq, MxExtI16_2>;
-  def NAME#"32dq" : MxBiArOp_RFRM<MN, NODE, MxType32d, MxType32.QOp, MxType32.QPat,
-                                  CMD, MxEncEAq, MxExtI16_2>;
-
-  def NAME#"8dp"  : MxBiArOp_RFRM<MN, NODE, MxType8d,  MxType8.POp,  MxType8.PPat,
-                                  CMD, MxEncEAp_2, MxExtI16_2>;
-  def NAME#"16dp" : MxBiArOp_RFRM<MN, NODE, MxType16d, MxType16.POp, MxType16.PPat,
-                                  CMD, MxEncEAp_2, MxExtI16_2>;
-  def NAME#"32dp" : MxBiArOp_RFRM<MN, NODE, MxType32d, MxType32.POp, MxType32.PPat,
-                                  CMD, MxEncEAp_2, MxExtI16_2>;
-
-  def NAME#"8df"  : MxBiArOp_RFRM<MN, NODE, MxType8d,  MxType8.FOp,  MxType8.FPat,
-                                  CMD, MxEncEAf_2, MxExtBrief_2>;
-  def NAME#"16df" : MxBiArOp_RFRM<MN, NODE, MxType16d, MxType16.FOp, MxType16.FPat,
-                                  CMD, MxEncEAf_2, MxExtBrief_2>;
-  def NAME#"32df" : MxBiArOp_RFRM<MN, NODE, MxType32d, MxType32.FOp, MxType32.FPat,
-                                  CMD, MxEncEAf_2, MxExtBrief_2>;
-
-  def NAME#"8dj"  : MxBiArOp_RFRM<MN, NODE, MxType8d,  MxType8.JOp,  MxType8.JPat,
-                                  CMD, MxEncEAj_2, MxExtEmpty>;
-  def NAME#"16dj" : MxBiArOp_RFRM<MN, NODE, MxType16d, MxType16.JOp, MxType16.JPat,
-                                  CMD, MxEncEAj_2, MxExtEmpty>;
-  def NAME#"32dj" : MxBiArOp_RFRM<MN, NODE, MxType32d, MxType32.JOp, MxType32.JPat,
-                                  CMD, MxEncEAj_2, MxExtEmpty>;
-
+    def NAME#SZ#"dk"  : MxBiArOp_R_RM<MN, NODE,
+                                      !cast<MxType>("MxType"#SZ#"d"),
+                                      !cast<MxType>("MxType"#SZ).KOp,
+                                      !cast<MxType>("MxType"#SZ).KPat,
+                                      CMD, MxEncAddrMode_k<"opd">>;
+
+    def NAME#SZ#"dq"  : MxBiArOp_R_RM<MN, NODE,
+                                      !cast<MxType>("MxType"#SZ#"d"),
+                                      !cast<MxType>("MxType"#SZ).QOp,
+                                      !cast<MxType>("MxType"#SZ).QPat,
+                                      CMD, MxEncAddrMode_q<"opd">>;
+
+    def NAME#SZ#"dp"  : MxBiArOp_R_RM<MN, NODE,
+                                      !cast<MxType>("MxType"#SZ#"d"),
+                                      !cast<MxType>("MxType"#SZ).POp,
+                                      !cast<MxType>("MxType"#SZ).PPat,
+                                      CMD, MxEncAddrMode_p<"opd">>;
+
+    def NAME#SZ#"df"  : MxBiArOp_R_RM<MN, NODE,
+                                      !cast<MxType>("MxType"#SZ#"d"),
+                                      !cast<MxType>("MxType"#SZ).FOp,
+                                      !cast<MxType>("MxType"#SZ).FPat,
+                                      CMD, MxEncAddrMode_f<"opd">>;
+
+    def NAME#SZ#"dj"  : MxBiArOp_R_RM<MN, NODE,
+                                      !cast<MxType>("MxType"#SZ#"d"),
+                                      !cast<MxType>("MxType"#SZ).JOp,
+                                      !cast<MxType>("MxType"#SZ).JPat,
+                                      CMD, MxEncAddrMode_j<"opd">>;
     // op $imm, $reg
-  def NAME#"8di"  : MxBiArOp_RFRI_xEA<MN, NODE, MxType8d,  CMD>;
-  def NAME#"16di" : MxBiArOp_RFRI_xEA<MN, NODE, MxType16d, CMD>;
-  def NAME#"32di" : MxBiArOp_RFRI_xEA<MN, NODE, MxType32d, CMD>;
-
+    def NAME#SZ#"di"  : MxBiArOp_R_RI_xEA<MN, NODE,
+                                          !cast<MxType>("MxType"#SZ#"d"),
+                                          CMD>;
     // op $reg, $mem
-  def NAME#"8pd"  : MxBiArOp_FMR<MN, NODE, MxType8d,  MxType8.POp,  MxType8.PPat,
-                                 CMD, MxEncEAp_0, MxExtI16_0>;
-  def NAME#"16pd" : MxBiArOp_FMR<MN, NODE, MxType16d, MxType16.POp, MxType16.PPat,
-                                 CMD, MxEncEAp_0, MxExtI16_0>;
-  def NAME#"32pd" : MxBiArOp_FMR<MN, NODE, MxType32d, MxType32.POp, MxType32.PPat,
-                                 CMD, MxEncEAp_0, MxExtI16_0>;
-
-  def NAME#"8fd"  : MxBiArOp_FMR<MN, NODE, MxType8d,  MxType8.FOp,  MxType8.FPat,
-                                 CMD, MxEncEAf_0, MxExtBrief_0>;
-  def NAME#"16fd" : MxBiArOp_FMR<MN, NODE, MxType16d, MxType16.FOp, MxType16.FPat,
-                                 CMD, MxEncEAf_0, MxExtBrief_0>;
-  def NAME#"32fd" : MxBiArOp_FMR<MN, NODE, MxType32d, MxType32.FOp, MxType32.FPat,
-                                 CMD, MxEncEAf_0, MxExtBrief_0>;
-
-  def NAME#"8jd"  : MxBiArOp_FMR<MN, NODE, MxType8d,  MxType8.JOp,  MxType8.JPat,
-                                 CMD, MxEncEAj_0, MxExtEmpty>;
-  def NAME#"16jd" : MxBiArOp_FMR<MN, NODE, MxType16d, MxType16.JOp, MxType16.JPat,
-                                 CMD, MxEncEAj_0, MxExtEmpty>;
-  def NAME#"32jd" : MxBiArOp_FMR<MN, NODE, MxType32d, MxType32.JOp, MxType32.JPat,
-                                 CMD, MxEncEAj_0, MxExtEmpty>;
-
+    def NAME#SZ#"pd"  : MxBiArOp_MR<MN,
+                                    !cast<MxType>("MxType"#SZ#"d"),
+                                    !cast<MxType>("MxType"#SZ).POp,
+                                    CMD, MxEncAddrMode_p<"dst">>;
+
+    def NAME#SZ#"fd"  : MxBiArOp_MR<MN,
+                                    !cast<MxType>("MxType"#SZ#"d"),
+                                    !cast<MxType>("MxType"#SZ).FOp,
+                                    CMD, MxEncAddrMode_f<"dst">>;
+
+    def NAME#SZ#"jd"  : MxBiArOp_MR<MN,
+                                    !cast<MxType>("MxType"#SZ#"d"),
+                                    !cast<MxType>("MxType"#SZ).JOp,
+                                    CMD, MxEncAddrMode_j<"dst">>;
     // op $imm, $mem
-  def NAME#"8pi"  : MxBiArOp_FMI<MN, NODE, MxType8,  MxType8.POp,  MxType8.PPat,
-                                 CMDI, MxEncEAp_0, MxExtI16_0>;
-  def NAME#"16pi" : MxBiArOp_FMI<MN, NODE, MxType16, MxType16.POp, MxType16.PPat,
-                                 CMDI, MxEncEAp_0, MxExtI16_0>;
-  def NAME#"32pi" : MxBiArOp_FMI<MN, NODE, MxType32, MxType32.POp, MxType32.PPat,
-                                 CMDI, MxEncEAp_0, MxExtI16_0>;
-
-  def NAME#"8fi"  : MxBiArOp_FMI<MN, NODE, MxType8,  MxType8.FOp,  MxType8.FPat,
-                                 CMDI, MxEncEAf_0, MxExtBrief_0>;
-  def NAME#"16fi" : MxBiArOp_FMI<MN, NODE, MxType16, MxType16.FOp, MxType16.FPat,
-                                 CMDI, MxEncEAf_0, MxExtBrief_0>;
-  def NAME#"32fi" : MxBiArOp_FMI<MN, NODE, MxType32, MxType32.FOp, MxType32.FPat,
-                                 CMDI, MxEncEAf_0, MxExtBrief_0>;
-
-  def NAME#"8ji"  : MxBiArOp_FMI<MN, NODE, MxType8,  MxType8.JOp,  MxType8.JPat,
-                                 CMDI, MxEncEAj_0, MxExtEmpty>;
-  def NAME#"16ji" : MxBiArOp_FMI<MN, NODE, MxType16, MxType16.JOp, MxType16.JPat,
-                                 CMDI, MxEncEAj_0, MxExtEmpty>;
-  def NAME#"32ji" : MxBiArOp_FMI<MN, NODE, MxType32, MxType32.JOp, MxType32.JPat,
-                                 CMDI, MxEncEAj_0, MxExtEmpty>;
-
-  def NAME#"16dr" : MxBiArOp_RFRR_xEA<MN, NODE, MxType16d, MxType16r,
-                                      CMD, MxBeadDReg<0>>;
-  def NAME#"32dr" : MxBiArOp_RFRR_xEA<MN, NODE, MxType32d, MxType32r,
-                                      CMD, MxBeadDReg<0>>;
-
-  let isCommutable = isComm in {
-
-    def NAME#"8dd"  : MxBiArOp_RFRR_xEA<MN, NODE, MxType8d, MxType8d,
-                                        CMD, MxBeadDReg<0>>;
-    def NAME#"16dd" : MxBiArOp_RFRR_xEA<MN, NODE, MxType16d, MxType16d,
-                                        CMD, MxBeadDReg<0>>;
-    def NAME#"32dd" : MxBiArOp_RFRR_xEA<MN, NODE, MxType32d, MxType32d,
-                                        CMD, MxBeadDReg<0>>;
-
-  } // isComm
+    def NAME#SZ#"pi"  : MxBiArOp_MI<MN,
+                                    !cast<MxType>("MxType"#SZ),
+                                    !cast<MxType>("MxType"#SZ).POp,
+                                    CMDI, MxEncAddrMode_p<"dst">>;
+
+    def NAME#SZ#"fi"  : MxBiArOp_MI<MN,
+                                    !cast<MxType>("MxType"#SZ),
+                                    !cast<MxType>("MxType"#SZ).FOp,
+                                    CMDI, MxEncAddrMode_f<"dst">>;
+
+    def NAME#SZ#"ji"  : MxBiArOp_MI<MN,
+                                    !cast<MxType>("MxType"#SZ),
+                                    !cast<MxType>("MxType"#SZ).JOp,
+                                    CMDI, MxEncAddrMode_j<"dst">>;
+    // op $reg, $reg
+    let isCommutable = isComm in
+    def NAME#SZ#"dd" : MxBiArOp_R_RR_xEA<MN, NODE,
+                                         !cast<MxType>("MxType"#SZ#"d"),
+                                         !cast<MxType>("MxType"#SZ#"d"),
+                                         CMD>;
+  } // foreach SZ
+
+  foreach SZ = [16, 32] in
+  def NAME#SZ#"dr" : MxBiArOp_R_RR_xEA<MN, NODE,
+                                       !cast<MxType>("MxType"#SZ#"d"),
+                                       !cast<MxType>("MxType"#SZ#"r"),
+                                       CMD>;
 
 } // MxBiArOp_DF
 
 
 // These special snowflakes allowed to match address registers but since *A
 // operations do not produce CCR we should not match them against Mx nodes that
 // produce it.
 let Pattern = [(null_frag)] in
-multiclass MxBiArOp_AF<string MN, SDNode NODE, bit isComm,
-                       bits<4> CMD, bits<4> CMDI> {
+multiclass MxBiArOp_AF<string MN, SDNode NODE, bits<4> CMD> {
 
-  def NAME#"32ak" : MxBiArOp_RFRM<MN, NODE, MxType32a, MxType32.KOp, MxType32.KPat,
-                                  CMD, MxEncEAk, MxExtBrief_2>;
-  def NAME#"32aq" : MxBiArOp_RFRM<MN, NODE, MxType32a, MxType32.QOp, MxType32.QPat,
-                                  CMD, MxEncEAq, MxExtI16_2>;
-  def NAME#"32af" : MxBiArOp_RFRM<MN, NODE, MxType32a, MxType32.FOp, MxType32.FPat,
-                                  CMD, MxEncEAf_2, MxExtBrief_2>;
-  def NAME#"32ap" : MxBiArOp_RFRM<MN, NODE, MxType32a, MxType32.POp, MxType32.PPat,
-                                  CMD, MxEncEAp_2, MxExtI16_2>;
-  def NAME#"32aj" : MxBiArOp_RFRM<MN, NODE, MxType32a, MxType32.JOp, MxType32.JPat,
-                                  CMD, MxEncEAj_2, MxExtEmpty>;
-  def NAME#"32ai" : MxBiArOp_RFRI_xEA<MN, NODE, MxType32a, CMD>;
+  def NAME#"32ak" : MxBiArOp_R_RM<MN, NODE, MxType32a, MxType32.KOp, MxType32.KPat,
+                                  CMD, MxEncAddrMode_k<"opd">>;
+  def NAME#"32aq" : MxBiArOp_R_RM<MN, NODE, MxType32a, MxType32.QOp, MxType32.QPat,
+                                  CMD, MxEncAddrMode_q<"opd">>;
+  def NAME#"32af" : MxBiArOp_R_RM<MN, NODE, MxType32a, MxType32.FOp, MxType32.FPat,
+                                  CMD, MxEncAddrMode_f<"opd">>;
+  def NAME#"32ap" : MxBiArOp_R_RM<MN, NODE, MxType32a, MxType32.POp, MxType32.PPat,
+                                  CMD, MxEncAddrMode_p<"opd">>;
+  def NAME#"32aj" : MxBiArOp_R_RM<MN, NODE, MxType32a, MxType32.JOp, MxType32.JPat,
+                                  CMD, MxEncAddrMode_j<"opd">>;
+  def NAME#"32ai" : MxBiArOp_R_RI_xEA<MN, NODE, MxType32a, CMD>;
 
-  def NAME#"32ar" : MxBiArOp_RFRR_xEA<MN, NODE, MxType32a, MxType32r,
-                                      CMD, MxBeadReg<0>>;
+  def NAME#"32ar" : MxBiArOp_R_RR_xEA<MN, NODE, MxType32a, MxType32r, CMD>;
 
 } // MxBiArOp_AF
 
 // NOTE These naturally produce CCR
 
 defm ADD : MxBiArOp_DF<"add",  MxAdd, 1, 0xD, 0x6>;
-defm ADD : MxBiArOp_AF<"adda", MxAdd, 1, 0xD, 0x6>;
+defm ADD : MxBiArOp_AF<"adda", MxAdd, 0xD>;
 defm SUB : MxBiArOp_DF<"sub",  MxSub, 0, 0x9, 0x4>;
-defm SUB : MxBiArOp_AF<"suba", MxSub, 0, 0x9, 0x4>;
+defm SUB : MxBiArOp_AF<"suba", MxSub, 0x9>;
 
 
 let Uses = [CCR], Defs = [CCR] in {
 let Constraints = "$src = $dst" in {
 
 // $reg, ccr <- $reg op $reg op ccr
-class MxBiArOp_RFRRF<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
+class MxBiArOp_R_RRX<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd),
              MN#"."#TYPE.Prefix#"\t$opd, $dst",
-             [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd, CCR))],
-             MxArithXEncoding<MxBead4Bits<CMD>,
-                              !cast<MxEncSize>("MxEncSize"#TYPE.Size),
-                              MxBead1Bit<0>, MxBeadDReg<2>, MxBeadDReg<0>>>;
-
+             [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd, CCR))]> {
+  let Inst = (descend CMD,
+    // Destination register
+    (operand "$dst", 3),
+    0b1,
+    // SIZE
+    !cond(!eq(TYPE.Size, 8): 0b00,
+          !eq(TYPE.Size, 16): 0b01,
+          !eq(TYPE.Size, 32): 0b10),
+    0b00, /*R/M*/0b0,
+    // Source register
+    (operand "$opd", 3)
+  );
+}
 } // Constraints
 } // Uses, Defs
 
 multiclass MxBiArOp_RFF<string MN, SDNode NODE, bit isComm, bits<4> CMD> {
 
 let isCommutable = isComm in {
-
-  def NAME#"8dd"  : MxBiArOp_RFRRF<MN, NODE, MxType8d,  CMD>;
-  def NAME#"16dd" : MxBiArOp_RFRRF<MN, NODE, MxType16d, CMD>;
-  def NAME#"32dd" : MxBiArOp_RFRRF<MN, NODE, MxType32d, CMD>;
-
+  foreach SZ = [8, 16, 32] in
+  def NAME#SZ#"dd"  : MxBiArOp_R_RRX<MN, NODE, !cast<MxType>("MxType"#SZ#"d"), CMD>;
 } // isComm
 
 } // MxBiArOp_RFF
 
 // NOTE These consume and produce CCR
 defm ADDX : MxBiArOp_RFF<"addx", MxAddX, 1, 0xD>;
 defm SUBX : MxBiArOp_RFF<"subx", MxSubX, 0, 0x9>;
 
 
 //===----------------------------------------------------------------------===//
 // And/Xor/Or
 //===----------------------------------------------------------------------===//
 
 defm AND : MxBiArOp_DF<"and", MxAnd, 1, 0xC, 0x2>;
 defm OR  : MxBiArOp_DF<"or",  MxOr,  1, 0x8, 0x0>;
 
 multiclass MxBiArOp_DF_EAd<string MN, SDNode NODE, bits<4> CMD, bits<4> CMDI> {
-
-  let isCommutable = 1 in {
-
-  def NAME#"8dd"  : MxBiArOp_RFRR_EAd<MN, NODE, MxType8d,  CMD>;
-  def NAME#"16dd" : MxBiArOp_RFRR_EAd<MN, NODE, MxType16d, CMD>;
-  def NAME#"32dd" : MxBiArOp_RFRR_EAd<MN, NODE, MxType32d, CMD>;
-
-  } // isCommutable = 1
-
-  def NAME#"8di"  : MxBiArOp_RFRI<MN, NODE,  MxType8d, CMDI>;
-  def NAME#"16di" : MxBiArOp_RFRI<MN, NODE, MxType16d, CMDI>;
-  def NAME#"32di" : MxBiArOp_RFRI<MN, NODE, MxType32d, CMDI>;
-
+  foreach SZ = [8, 16, 32] in {
+    let isCommutable = 1 in
+    def NAME#SZ#"dd"  : MxBiArOp_R_RR_EAd<MN, NODE,
+                                          !cast<MxType>("MxType"#SZ#"d"),
+                                          CMD>;
+
+    def NAME#SZ#"di"  : MxBiArOp_R_RI<MN, NODE,
+                                      !cast<MxType>("MxType"#SZ#"d"),
+                                      CMDI>;
+  } // foreach SZ
 } // MxBiArOp_DF_EAd
 
 defm XOR : MxBiArOp_DF_EAd<"eor", MxXor, 0xB, 0xA>;
 
 
 //===----------------------------------------------------------------------===//
 // CMP
 //===----------------------------------------------------------------------===//
 
 let Defs = [CCR] in {
-class MxCmp_RR<MxType LHS_TYPE, MxType RHS_TYPE = LHS_TYPE,
-               MxBead REG = MxBeadDReg<1>>
+class MxCmp_RR<MxType LHS_TYPE, MxType RHS_TYPE = LHS_TYPE>
     : MxInst<(outs), (ins LHS_TYPE.ROp:$lhs, RHS_TYPE.ROp:$rhs),
              "cmp."#RHS_TYPE.Prefix#"\t$lhs, $rhs",
-             [(set CCR, (MxCmp LHS_TYPE.VT:$lhs, RHS_TYPE.VT:$rhs))],
-             MxArithEncoding<MxBead4Bits<0xB>,
-                             !cast<MxEncOpMode>("MxOpMode"#RHS_TYPE.Size#RHS_TYPE.RLet#"EA"),
-                             REG,
-                             !cast<MxEncEA>("MxEncEA"#LHS_TYPE.RLet#"_0"),
-                             MxExtEmpty>>;
+             [(set CCR, (MxCmp LHS_TYPE.VT:$lhs, RHS_TYPE.VT:$rhs))]> {
+  let Inst = (descend 0b1011,
+    // REGISTER
+    (operand "$rhs", 3),
+    // OPMODE
+    !cast<MxOpModeEncoding>("MxOpMode"#RHS_TYPE.Size#"_"#RHS_TYPE.RLet#"_EA").Value,
+    // MODE without last bit
+    0b00,
+    // REGISTER prefixed by D/A bit
+    (operand "$lhs", 4)
+  );
+}
 
 class MxCmp_RI<MxType TYPE>
     : MxInst<(outs), (ins TYPE.IOp:$imm, TYPE.ROp:$reg),
              "cmpi."#TYPE.Prefix#"\t$imm, $reg",
-             [(set CCR, (MxCmp TYPE.IPat:$imm, TYPE.VT:$reg))],
-             MxArithImmEncoding<MxBead4Bits<0xC>,
-                                !cast<MxEncSize>("MxEncSize"#TYPE.Size),
-                                MxEncEAd_1, MxExtEmpty,
-                                !cast<MxEncExt>("MxExtI"#TYPE.Size#"_0")>>;
+             [(set CCR, (MxCmp TYPE.IPat:$imm, TYPE.VT:$reg))]> {
+  let Inst = (ascend
+    (descend 0b00001100,
+             !cast<MxNewEncSize>("MxNewEncSize"#TYPE.Size).Value,
+             // The destination cannot be address register, so it's always
+             // the MODE for data register direct mode.
+             /*MODE*/0b000,
+             /*REGISTER*/(operand "$reg", 3)),
+    // Source (i.e. immediate value) encoding
+    MxEncAddrMode_i<"imm", TYPE.Size>.Supplement
+  );
+}
 
 let mayLoad = 1 in {
 
 class MxCmp_MI<MxType TYPE, MxOperand MEMOpd, ComplexPattern MEMPat,
-               MxEncEA EA, MxEncExt EXT>
+               MxEncMemOp MEM_ENC>
     : MxInst<(outs), (ins TYPE.IOp:$imm, MEMOpd:$mem),
              "cmpi."#TYPE.Prefix#"\t$imm, $mem",
-             [(set CCR, (MxCmp TYPE.IPat:$imm, (load MEMPat:$mem)))],
-             MxArithImmEncoding<MxBead4Bits<0xC>,
-                                !cast<MxEncSize>("MxEncSize"#TYPE.Size),
-                                EA, EXT,
-                                !cast<MxEncExt>("MxExtI"#TYPE.Size#"_0")>>;
+             [(set CCR, (MxCmp TYPE.IPat:$imm, (load MEMPat:$mem)))]> {
+  let Inst = (ascend
+    (descend 0b00001100,
+             !cast<MxNewEncSize>("MxNewEncSize"#TYPE.Size).Value,
+             MEM_ENC.EA),
+    // Source (i.e. immediate value) encoding
+    MxEncAddrMode_i<"imm", TYPE.Size>.Supplement,
+    // Destination (i.e. memory operand) encoding
+    MEM_ENC.Supplement
+  );
+}
 
+// FIXME: What about abs.W?
 class MxCmp_BI<MxType TYPE>
     : MxInst<(outs), (ins TYPE.IOp:$imm, MxAL32:$abs),
              "cmpi."#TYPE.Prefix#"\t$imm, $abs",
              [(set CCR, (MxCmp TYPE.IPat:$imm,
-                               (load (i32 (MxWrapper tglobaladdr:$abs)))))],
-             MxArithImmEncoding<MxBead4Bits<0xC>,
-                                !cast<MxEncSize>("MxEncSize"#TYPE.Size),
-                                MxEncEAb, MxExtI32_1,
-                                !cast<MxEncExt>("MxExtI"#TYPE.Size#"_0")>>;
+                               (load (i32 (MxWrapper tglobaladdr:$abs)))))]> {
+  defvar AbsEncoding = MxEncAddrMode_abs<"abs", true>;
+  let Inst = (ascend
+    (descend 0b00001100,
+             !cast<MxNewEncSize>("MxNewEncSize"#TYPE.Size).Value,
+             AbsEncoding.EA),
+    // Source (i.e. immediate value) encoding
+    MxEncAddrMode_i<"imm", TYPE.Size>.Supplement,
+    // Destination (i.e. memory operand) encoding
+    AbsEncoding.Supplement
+  );
+}
 
 class MxCmp_RM<MxType TYPE, MxOperand MEMOpd, ComplexPattern MEMPat,
-               MxEncEA EA, MxEncExt EXT>
+               MxEncMemOp MEM_ENC>
     : MxInst<(outs), (ins TYPE.ROp:$reg, MEMOpd:$mem),
              "cmp."#TYPE.Prefix#"\t$mem, $reg",
-             [(set CCR, (MxCmp (load MEMPat:$mem), TYPE.ROp:$reg))],
-             MxArithEncoding<MxBead4Bits<0xB>,
-                             !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"dEA"),
-                             MxBeadDReg<0>, EA, EXT>>;
+             [(set CCR, (MxCmp (load MEMPat:$mem), TYPE.ROp:$reg))]> {
+  let Inst = (ascend
+    (descend 0b1011,
+      // REGISTER
+      (operand "$reg", 3),
+      // OPMODE
+      !cast<MxOpModeEncoding>("MxOpMode"#TYPE.Size#"_d_EA").Value,
+      MEM_ENC.EA),
+    MEM_ENC.Supplement
+  );
+}
 } // let mayLoad = 1
 
 } // let Defs = [CCR]
 
 multiclass MMxCmp_RM<MxType TYPE> {
-  def NAME#TYPE.KOp.Letter : MxCmp_RM<TYPE, TYPE.KOp, TYPE.KPat, MxEncEAk,
-                                      MxExtBrief_1>;
-  def NAME#TYPE.QOp.Letter : MxCmp_RM<TYPE, TYPE.QOp, TYPE.QPat, MxEncEAq,
-                                      MxExtI16_1>;
-  def NAME#TYPE.POp.Letter : MxCmp_RM<TYPE, TYPE.POp, TYPE.PPat, MxEncEAp_1,
-                                      MxExtI16_1>;
-  def NAME#TYPE.FOp.Letter : MxCmp_RM<TYPE, TYPE.FOp, TYPE.FPat, MxEncEAf_1,
-                                      MxExtBrief_1>;
-  def NAME#TYPE.JOp.Letter : MxCmp_RM<TYPE, TYPE.JOp, TYPE.JPat, MxEncEAj_1,
-                                      MxExtEmpty>;
+  def NAME#TYPE.KOp.Letter : MxCmp_RM<TYPE, TYPE.KOp, TYPE.KPat, MxEncAddrMode_k<"mem">>;
+  def NAME#TYPE.QOp.Letter : MxCmp_RM<TYPE, TYPE.QOp, TYPE.QPat, MxEncAddrMode_q<"mem">>;
+  def NAME#TYPE.POp.Letter : MxCmp_RM<TYPE, TYPE.POp, TYPE.PPat, MxEncAddrMode_p<"mem">>;
+  def NAME#TYPE.FOp.Letter : MxCmp_RM<TYPE, TYPE.FOp, TYPE.FPat, MxEncAddrMode_f<"mem">>;
+  def NAME#TYPE.JOp.Letter : MxCmp_RM<TYPE, TYPE.JOp, TYPE.JPat, MxEncAddrMode_j<"mem">>;
 }
 
 multiclass MMxCmp_MI<MxType TYPE> {
-  def NAME#TYPE.KOp.Letter#"i" : MxCmp_MI<TYPE, TYPE.KOp, TYPE.KPat, MxEncEAk,
-                                          MxExtBrief_1>;
-  def NAME#TYPE.QOp.Letter#"i" : MxCmp_MI<TYPE, TYPE.QOp, TYPE.QPat, MxEncEAq,
-                                          MxExtI16_1>;
-  def NAME#TYPE.POp.Letter#"i" : MxCmp_MI<TYPE, TYPE.POp, TYPE.PPat, MxEncEAp_1,
-                                          MxExtI16_1>;
-  def NAME#TYPE.FOp.Letter#"i" : MxCmp_MI<TYPE, TYPE.FOp, TYPE.FPat, MxEncEAf_1,
-                                          MxExtBrief_1>;
-  def NAME#TYPE.JOp.Letter#"i" : MxCmp_MI<TYPE, TYPE.JOp, TYPE.JPat, MxEncEAj_1,
-                                          MxExtEmpty>;
+  def NAME#TYPE.KOp.Letter#"i" : MxCmp_MI<TYPE, TYPE.KOp, TYPE.KPat,
+                                          MxEncAddrMode_k<"mem">>;
+  def NAME#TYPE.QOp.Letter#"i" : MxCmp_MI<TYPE, TYPE.QOp, TYPE.QPat,
+                                          MxEncAddrMode_q<"mem">>;
+  def NAME#TYPE.POp.Letter#"i" : MxCmp_MI<TYPE, TYPE.POp, TYPE.PPat,
+                                          MxEncAddrMode_p<"mem">>;
+  def NAME#TYPE.FOp.Letter#"i" : MxCmp_MI<TYPE, TYPE.FOp, TYPE.FPat,
+                                          MxEncAddrMode_f<"mem">>;
+  def NAME#TYPE.JOp.Letter#"i" : MxCmp_MI<TYPE, TYPE.JOp, TYPE.JPat,
+                                          MxEncAddrMode_j<"mem">>;
 }
 
 foreach S = [8, 16, 32] in {
   def CMP#S#di : MxCmp_RI<!cast<MxType>("MxType"#S#"d")>;
   def CMP#S#bi : MxCmp_BI<!cast<MxType>("MxType"#S#"d")>;
 } // foreach
 
 def CMP8dd : MxCmp_RR<MxType8d>;

 defm CMP16 : MMxCmp_MI<MxType16d>;
 defm CMP32 : MMxCmp_MI<MxType32d>;
 
 
 //===----------------------------------------------------------------------===//
 // EXT
 //===----------------------------------------------------------------------===//
 
-def MxExtOpmode_wb : MxBead3Bits<0b010>;
-def MxExtOpmode_lw : MxBead3Bits<0b011>;
-def MxExtOpmode_lb : MxBead3Bits<0b111>;
-
 /// ---------------------------------------------------
 ///  F  E  D  C  B  A  9 | 8  7  6 | 5  4  3 | 2  1  0
 /// ---------------------------------------------------
 ///  0  1  0  0  1  0  0 |  OPMODE | 0  0  0 |   REG
 /// ---------------------------------------------------
-class MxExtEncoding<MxBead3Bits OPMODE>
-    : MxEncoding<MxBeadDReg<0>, MxBead3Bits<0b000>, OPMODE,
-                 MxBead3Bits<0b100>, MxBead4Bits<0b0100>>;
-
 let Defs = [CCR] in
 let Constraints = "$src = $dst" in
 class MxExt<MxType TO, MxType FROM>
     : MxInst<(outs TO.ROp:$dst), (ins TO.ROp:$src),
-             "ext."#TO.Prefix#"\t$src", [],
-             MxExtEncoding<!cast<MxBead3Bits>("MxExtOpmode_"#TO.Prefix#FROM.Prefix)>>;
+             "ext."#TO.Prefix#"\t$src", []> {
+  let Inst = (descend 0b0100100,
+    // OPMODE
+    !cond(
+      // byte -> word
+      !and(!eq(FROM.Size, 8), !eq(TO.Size, 16)): 0b010,
+      // word -> long
+      !and(!eq(FROM.Size, 16), !eq(TO.Size, 32)): 0b011,
+      // byte -> long
+      !and(!eq(FROM.Size, 8), !eq(TO.Size, 32)): 0b111
+    ),
+    0b000,
+    // REGISTER
+    (operand "$src", 3)
+  );
+}
 
 def EXT16 : MxExt<MxType16d, MxType8d>;
 def EXT32 : MxExt<MxType32d, MxType16d>;
 
 def : Pat<(sext_inreg i16:$src, i8),  (EXT16 $src)>;
 def : Pat<(sext_inreg i32:$src, i16), (EXT32 $src)>;
 def : Pat<(sext_inreg i32:$src, i8),
           (EXT32 (MOVXd32d16 (EXT16 (EXTRACT_SUBREG $src, MxSubRegIndex16Lo))))>;
 
 
 //===----------------------------------------------------------------------===//
 // DIV/MUL
 //===----------------------------------------------------------------------===//
 
-def MxSDiMuOpmode : MxBead3Bits<0b111>;
-def MxUDiMuOpmode : MxBead3Bits<0b011>;
-
 /// Word operation:
 /// ----------------------------------------------------
 ///  F  E  D  C | B  A  9 | 8  7  6 | 5  4  3 | 2  1  0
 /// ----------------------------------------------------
 ///             |         |         | EFFECTIVE ADDRESS
 ///  x  x  x  x |   REG   | OP MODE |   MODE  |   REG
 /// ----------------------------------------------------
-class MxDiMuEncoding<MxBead4Bits CMD, MxBead3Bits OPMODE, MxEncEA EA, MxEncExt EXT>
-    : MxEncoding<EA.Reg, EA.DA, EA.Mode, OPMODE, MxBeadDReg<0>, CMD,
-                 EXT.Imm, EXT.B8, EXT.Scale, EXT.WL, EXT.DAReg>;
-
 let Defs = [CCR] in {
 let Constraints = "$src = $dst" in {
-// $reg <- $reg op $reg
-class MxDiMuOp_DD<string MN, bits<4> CMD, MxBead3Bits OPMODE,
+// $dreg <- $dreg op $dreg
+class MxDiMuOp_DD<string MN, bits<4> CMD, bit SIGNED = false,
                   MxOperand DST, MxOperand OPD>
-    : MxInst<(outs DST:$dst), (ins DST:$src, OPD:$opd), MN#"\t$opd, $dst", [],
-             MxDiMuEncoding<MxBead4Bits<CMD>, OPMODE, MxEncEAd_2, MxExtEmpty>>;
+    : MxInst<(outs DST:$dst), (ins DST:$src, OPD:$opd), MN#"\t$opd, $dst", []> {
+  let Inst = (descend CMD,
+    // REGISTER
+    (operand "$dst", 3),
+    !if(SIGNED, 0b111, 0b011),
+    /*MODE*/0b000, /*REGISTER*/(operand "$opd", 3)
+  );
+}
 
 // $reg <- $reg op $imm
-class MxDiMuOp_DI<string MN, bits<4> CMD, MxBead3Bits OPMODE,
+class MxDiMuOp_DI<string MN, bits<4> CMD, bit SIGNED = false,
                   MxOperand DST, MxOperand OPD>
-    : MxInst<(outs DST:$dst), (ins DST:$src, OPD:$opd), MN#"\t$opd, $dst", [],
-             MxDiMuEncoding<MxBead4Bits<CMD>, OPMODE, MxEncEAi, MxExtI16_2>>;
+    : MxInst<(outs DST:$dst), (ins DST:$src, OPD:$opd), MN#"\t$opd, $dst", []> {
+  // FIXME: Support immediates with different widths.
+  defvar ImmEnc = MxEncAddrMode_i<"opd", 16>;
+  let Inst = (ascend
+    (descend CMD,
+      // REGISTER
+      (operand "$dst", 3),
+      !if(SIGNED, 0b111, 0b011), ImmEnc.EA),
+    ImmEnc.Supplement
+  );
+}
 } // let Constraints
 } // Defs = [CCR]
 
 multiclass MxDiMuOp<string MN, bits<4> CMD, bit isComm = 0> {
-
   let isCommutable = isComm in {
-    def "S"#NAME#"d32d16" : MxDiMuOp_DD<MN#"s", CMD, MxSDiMuOpmode, MxDRD32,
-                                        MxDRD16>;
-    def "U"#NAME#"d32d16" : MxDiMuOp_DD<MN#"u", CMD, MxUDiMuOpmode, MxDRD32,
-                                        MxDRD16>;
+    def "S"#NAME#"d32d16" : MxDiMuOp_DD<MN#"s", CMD, /*SIGNED*/true, MxDRD32, MxDRD16>;
+    def "U"#NAME#"d32d16" : MxDiMuOp_DD<MN#"u", CMD, /*SIGNED*/false, MxDRD32, MxDRD16>;
   }
 
-  def "S"#NAME#"d32i16" : MxDiMuOp_DI<MN#"s", CMD, MxSDiMuOpmode, MxDRD32,
-                                      Mxi16imm>;
-  def "U"#NAME#"d32i16" : MxDiMuOp_DI<MN#"u", CMD, MxUDiMuOpmode, MxDRD32,
-                                      Mxi16imm>;
-
+  def "S"#NAME#"d32i16" : MxDiMuOp_DI<MN#"s", CMD, /*SIGNED*/true, MxDRD32, Mxi16imm>;
+  def "U"#NAME#"d32i16" : MxDiMuOp_DI<MN#"u", CMD, /*SIGNED*/false, MxDRD32, Mxi16imm>;
 }
 
 defm DIV : MxDiMuOp<"div", 0x8>;
 
 // This is used to cast immediates to 16-bits for operations which don't
 // support smaller immediate sizes.
 def as_i16imm : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);

 //===----------------------------------------------------------------------===//
 
 /// ------------+------------+------+---------+---------
 ///  F  E  D  C | B  A  9  8 | 7  6 | 5  4  3 | 2  1  0
 /// ------------+------------+------+-------------------
 ///             |            |      | EFFECTIVE ADDRESS
 ///  0  1  0  0 | x  x  x  x | SIZE |   MODE  |   REG
 /// ------------+------------+------+---------+---------
-class MxNEGEncoding<MxBead4Bits CMD, MxEncSize SIZE, MxEncEA EA, MxEncExt EXT>
-    : MxEncoding<EA.Reg, EA.DA, EA.Mode, SIZE, CMD, MxBead4Bits<0b0100>,
-                 EXT.Imm, EXT.B8, EXT.Scale, EXT.WL, EXT.DAReg>;
-
 let Defs = [CCR] in {
 let Constraints = "$src = $dst" in {
 
 class MxNeg_D<MxType TYPE>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src),
              "neg."#TYPE.Prefix#"\t$dst",
-             [(set TYPE.VT:$dst, (ineg TYPE.VT:$src))],
-             MxNEGEncoding<MxBead4Bits<0x4>,
-                           !cast<MxEncSize>("MxEncSize"#TYPE.Size),
-                           MxEncEAd_0, MxExtEmpty>>;
+             [(set TYPE.VT:$dst, (ineg TYPE.VT:$src))]> {
+  let Inst = (descend 0b01000100,
+    /*SIZE*/!cast<MxNewEncSize>("MxNewEncSize"#TYPE.Size).Value,
+    //MODE without last bit
+    0b00,
+    //REGISTER prefixed by D/A bit
+    (operand "$dst", 4)
+  );
+}
 
 let Uses = [CCR] in {
 class MxNegX_D<MxType TYPE>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src),
              "negx."#TYPE.Prefix#"\t$dst",
-             [(set TYPE.VT:$dst, (MxSubX 0, TYPE.VT:$src, CCR))],
-             MxNEGEncoding<MxBead4Bits<0x0>,
-                           !cast<MxEncSize>("MxEncSize"#TYPE.Size),
-                           MxEncEAd_0, MxExtEmpty>>;
+             [(set TYPE.VT:$dst, (MxSubX 0, TYPE.VT:$src, CCR))]> {
+  let Inst = (descend 0b01000000,
+    /*SIZE*/!cast<MxNewEncSize>("MxNewEncSize"#TYPE.Size).Value,
+    //MODE without last bit
+    0b00,
+    //REGISTER prefixed by D/A bit
+    (operand "$dst", 4)
+  );
+}
 }
 
 } // let Constraints
 } // let Defs = [CCR]
 
 foreach S = [8, 16, 32] in {
   def NEG#S#d  : MxNeg_D<!cast<MxType>("MxType"#S#"d")>;
   def NEGX#S#d : MxNegX_D<!cast<MxType>("MxType"#S#"d")>;

llvm/lib/Target/M68k/M68kInstrFormats.td

 /// the register and we have to encode those separately using MxBeadDA<opN>
 ///
 class MxEncEA<MxBead reg, MxBead mode, MxBead da = MxBeadIgnore> {
   MxBead Reg = reg;
   MxBead Mode = mode;
   MxBead DA = da;
 }
 
+class MxEncMemOp {
+  dag EA = (ascend);
+  dag Supplement = (ascend);
+}
+
 // FIXME: Is there a way to factorize the addressing mode suffix (i.e.
 // 'r', 'd', 'a' etc.) and use something like multiclass to replace?
 def MxEncEAr_0: MxEncEA<MxBeadDAReg<0>, MxBead2Bits<0b00>>;
 def MxEncEAd_0: MxEncEA<MxBeadDReg<0>, MxBead2Bits<0b00>, MxBead1Bit<0>>;
 def MxEncEAa_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b00>, MxBead1Bit<1>>;
 def MxEncEAj_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b01>, MxBead1Bit<0>>;
 def MxEncEAo_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b01>, MxBead1Bit<1>>;
 def MxEncEAe_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b10>, MxBead1Bit<0>>;

 def MxEncEAp_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b10>, MxBead1Bit<1>>;
 def MxEncEAf_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b11>, MxBead1Bit<0>>;
 
 def MxEncEAb : MxEncEA<MxBead3Bits<0b001>, MxBead2Bits<0b11>, MxBead1Bit<1>>;
 def MxEncEAq : MxEncEA<MxBead3Bits<0b010>, MxBead2Bits<0b11>, MxBead1Bit<1>>;
 def MxEncEAk : MxEncEA<MxBead3Bits<0b011>, MxBead2Bits<0b11>, MxBead1Bit<1>>;
 def MxEncEAi : MxEncEA<MxBead3Bits<0b100>, MxBead2Bits<0b11>, MxBead1Bit<1>>;
 
+class MxEncBriefExt<string reg_opnd, string disp_opnd,
+                    bit size_w_l = false, int scale = 1> {
+  dag Value = (descend
+    // D/A + REGISTER
+    (operand "$"#reg_opnd, 4),
+    // W/L
+    size_w_l,
+    // SCALE
+    !cond(
+      !eq(scale, 1) : 0b00,
+      !eq(scale, 2) : 0b01,
+      !eq(scale, 4) : 0b10,
+      !eq(scale, 8) : 0b11
+    ),
+    0b0,
+    // Displacement
+    (operand "$"#disp_opnd, 8)
+  );
+}
+
+class MxEncAddrMode_k<string opnd_name> : MxEncMemOp {
+  let EA = (descend /*MODE*/0b111,
+                     /*REGISTER*/0b011);
+
+  let Supplement = MxEncBriefExt<opnd_name#".index", opnd_name#".disp",
+                                 /*W/L*/true>.Value;
+}
+
+class MxEncAddrMode_q<string opnd_name> : MxEncMemOp {
+  let EA = (descend /*MODE*/0b111,
+                     /*REGISTER*/0b010);
+
+  // 16-bit Displacement
+  let Supplement = (operand "$"#opnd_name, 16);
+}
+
+class MxEncAddrMode_p<string opnd_name> : MxEncMemOp {
+  let EA = (descend /*MODE*/0b101,
+                     /*REGISTER*/(operand "$"#opnd_name#".reg", 3));
+
+  // 16-bit Displacement
+  let Supplement = (operand "$"#opnd_name#".disp", 16);
+}
+
+class MxEncAddrMode_f<string opnd_name> : MxEncMemOp {
+  let EA = (descend /*MODE*/0b110,
+                     /*REGISTER*/(operand "$"#opnd_name#".reg", 3));
+
+  let Supplement = MxEncBriefExt<opnd_name#".index", opnd_name#".disp",
+                                 /*W/L*/true>.Value;
+}
+
+class MxEncAddrMode_j<string reg_opnd> : MxEncMemOp {
+  let EA = (descend /*MODE*/0b010,
+                     /*REGISTER*/(operand "$"#reg_opnd, 3));
+}
+
+class MxEncAddrMode_i<string opnd_name, int size> : MxEncMemOp {
+  let EA = (descend /*MODE*/0b111,
+                     /*REGISTER*/0b100);
+
+  // Immediate
+  let Supplement =
+    !cond(
+      !eq(size, 8)  : (descend 0b00000000, (operand "$"#opnd_name, 8)),
+      !eq(size, 16) : (operand "$"#opnd_name, 16),
+      !eq(size, 32) : (ascend (slice "$"#opnd_name, 31, 16),
+                              (slice "$"#opnd_name, 15, 0))
+    );
+}
+
+// abs.W -> size_w_l = false
+// abs.L -> size_w_l = true
+class MxEncAddrMode_abs<string opnd_name, bit size_w_l = false> : MxEncMemOp {
+  let EA = (descend /*MODE*/0b111,
+                     /*REGISTER*/0b00, size_w_l);
+
+  // Absolute address
+  let Supplement = !if(size_w_l,
+    // abs.L
+    (ascend (slice "$"#opnd_name, 31, 16),
+            (slice "$"#opnd_name, 15, 0)),
+    // abs.W
+    (operand "$"#opnd_name, 16)
+  );
+}
+
 // Allows you to specify each bit of opcode
 class MxEncOpMode<MxBead b0, MxBead b1 = MxBeadIgnore, MxBead b2 = MxBeadIgnore> {
   MxBead B0 = b0;
   MxBead B1 = b1;
   MxBead B2 = b2;
 }
 
 // op EA, Dn
def MxExtBrief_4 : MxEncExt<MxBead8Disp<4>, MxBead1Bit<0b0>,
                             MxBeadDAReg<4, 1>>;
 
 class MxEncSize<bits<2> value> : MxBead2Bits<value>;
 def MxEncSize8  : MxEncSize<0b00>;
 def MxEncSize16 : MxEncSize<0b01>;
 def MxEncSize32 : MxEncSize<0b10>;
 def MxEncSize64 : MxEncSize<0b11>;
 
+// TODO: Remove "New" in the name after the codebead-based
+// representation is deprecated.
+class MxNewEncSize<bits<2> value> {
+  bits<2> Value = value;
+}
+def MxNewEncSize8  : MxNewEncSize<0b00>;
+def MxNewEncSize16 : MxNewEncSize<0b01>;
+def MxNewEncSize32 : MxNewEncSize<0b10>;
+def MxNewEncSize64 : MxNewEncSize<0b11>;
+
 // M68k INSTRUCTION. Most instructions specify the location of an operand by
 // using the effective address field in the operation word. The effective address
 // is composed of two 3-bit fields: the mode field and the register field. The
 // value in the mode field selects the different address modes. The register
 // field contains the number of a register.  The effective address field may
 // require additional information to fully specify the operand. This additional
 // information, called the effective address extension, is contained in the
 // following word or words and is considered part of the instruction. The
class MxInst<dag outs, dag ins,
   let OutOperandList = outs;
   let InOperandList  = ins;
   let AsmString      = asmStr;
   let Pattern        = pattern;
   let Itinerary      = itin;
 
   // Byte stream
   field bits<192> Beads = beads.Value;
+  dag Inst = (ascend);
 
   // Number of bytes
   let Size = 0;
 
   let UseLogicalOperandMappings = 1;
 }
 
 // M68k PSEUDO INSTRUCTION
 class MxPseudo<dag outs, dag ins, list<dag> pattern = []>
     : MxInst<outs, ins, "; error: this should not be emitted", pattern> {
   let isPseudo = 1;
 }

llvm/lib/Target/M68k/M68kInstrInfo.td

 def MxARIPD32_TC  : MxMemOp<(ops AR32_TC), MxSize32, "e", "printARIPD32Mem", MxARIPD>;
 
 // ADDRESS REGISTER INDIRECT WITH DISPLACEMENT. This addressing mode requires one
 // word of extension. The address of the operand is the sum of the address in
 // the address register and the sign-extended 16-bit displacement integer in the
 // extension word. The reference is classified as a data reference with the
 // exception of the jump and jump-to-subroutine instructions.
 def MxARID        : MxOpClass<"ARID">;
-def MxARID8       : MxMemOp<(ops i16imm, AR32), MxSize8,  "p", "printARID8Mem", MxARID>;
-def MxARID16      : MxMemOp<(ops i16imm, AR32), MxSize16, "p", "printARID16Mem", MxARID>;
-def MxARID32      : MxMemOp<(ops i16imm, AR32), MxSize32, "p", "printARID32Mem", MxARID>;
-
-def MxARID8_TC    : MxMemOp<(ops i16imm, AR32_TC), MxSize8,  "p", "printARID8Mem", MxARID>;
-def MxARID16_TC   : MxMemOp<(ops i16imm, AR32_TC), MxSize16, "p", "printARID16Mem", MxARID>;
-def MxARID32_TC   : MxMemOp<(ops i16imm, AR32_TC), MxSize32, "p", "printARID32Mem", MxARID>;
+def MxARID8       : MxMemOp<(ops i16imm:$disp, AR32:$reg), MxSize8,  "p", "printARID8Mem", MxARID>;
+def MxARID16      : MxMemOp<(ops i16imm:$disp, AR32:$reg), MxSize16, "p", "printARID16Mem", MxARID>;
+def MxARID32      : MxMemOp<(ops i16imm:$disp, AR32:$reg), MxSize32, "p", "printARID32Mem", MxARID>;
+
+def MxARID8_TC    : MxMemOp<(ops i16imm:$disp, AR32_TC:$reg), MxSize8,  "p", "printARID8Mem", MxARID>;
+def MxARID16_TC   : MxMemOp<(ops i16imm:$disp, AR32_TC:$reg), MxSize16, "p", "printARID16Mem", MxARID>;
+def MxARID32_TC   : MxMemOp<(ops i16imm:$disp, AR32_TC:$reg), MxSize32, "p", "printARID32Mem", MxARID>;
 
 // ADDRESS REGISTER INDIRECT WITH INDEX. This addressing mode requires one word
 // of extension. The address of the operand is the sum of the address in the
 // address register, the signextended displacement integer in the low order eight
 // bits of the extension word, and the contents of the index register.
 // The reference is classified as a data reference with the exception of the
 // jump and jump-to-subroutine instructions
 def MxARII       : MxOpClass<"ARII">;
-def MxARII8      : MxMemOp<(ops i8imm, AR32, XR32), MxSize8,  "f", "printARII8Mem", MxARII>;
-def MxARII16     : MxMemOp<(ops i8imm, AR32, XR32), MxSize16, "f", "printARII16Mem", MxARII>;
-def MxARII32     : MxMemOp<(ops i8imm, AR32, XR32), MxSize32, "f", "printARII32Mem", MxARII>;
-
-def MxARII8_TC   : MxMemOp<(ops i8imm, AR32_TC, XR32_TC), MxSize8,  "f", "printARII8Mem", MxARII>;
-def MxARII16_TC  : MxMemOp<(ops i8imm, AR32_TC, XR32_TC), MxSize16, "f", "printARII16Mem", MxARII>;
-def MxARII32_TC  : MxMemOp<(ops i8imm, AR32_TC, XR32_TC), MxSize32, "f", "printARII32Mem", MxARII>;
+def MxARII8      : MxMemOp<(ops i8imm:$disp, AR32:$reg, XR32:$index),
+                           MxSize8,  "f", "printARII8Mem", MxARII>;
+def MxARII16     : MxMemOp<(ops i8imm:$disp, AR32:$reg, XR32:$index),
+                           MxSize16, "f", "printARII16Mem", MxARII>;
+def MxARII32     : MxMemOp<(ops i8imm:$disp, AR32:$reg, XR32:$index),
+                           MxSize32, "f", "printARII32Mem", MxARII>;
+
+def MxARII8_TC   : MxMemOp<(ops i8imm:$disp, AR32_TC:$reg, XR32_TC:$index),
+                           MxSize8,  "f", "printARII8Mem", MxARII>;
+def MxARII16_TC  : MxMemOp<(ops i8imm:$disp, AR32_TC:$reg, XR32_TC:$index),
+                           MxSize16, "f", "printARII16Mem", MxARII>;
+def MxARII32_TC  : MxMemOp<(ops i8imm:$disp, AR32_TC:$reg, XR32_TC:$index),
+                           MxSize32, "f", "printARII32Mem", MxARII>;
 
 // ABSOLUTE SHORT ADDRESS. This addressing mode requires one word of extension.
 // The address of the operand is the extension word. The 16-bit address is sign
 // extended before it is used.  The reference is classified as a data reference
 // with the exception of the jump and jump-tosubroutine instructions.
 def MxAddr     : MxOpClass<"Addr">;
 let RenderMethod = "addAddrOperands" in {
   // This hierarchy ensures Addr8 will always be parsed

 def MxPCD32    : MxMemOp<(ops i16imm), MxSize32, "q", "printPCD32Mem", MxPCD>;
 
 // PROGRAM COUNTER WITH INDEX. This addressing mode requires one word of
 // extension. The address is the sum of the address in the program counter, the
 // sign-extended displacement integer in the lower eight bits of the extension
 // word, and the contents of the index register.  The value in the program
 // counter is the address of the extension word. This reference is classified as
 // a program reference.
-def MxPCI8   : MxMemOp<(ops i8imm, XR32), MxSize8,  "k", "printPCI8Mem", MxPCI>;
-def MxPCI16  : MxMemOp<(ops i8imm, XR32), MxSize16, "k", "printPCI16Mem", MxPCI>;
-def MxPCI32  : MxMemOp<(ops i8imm, XR32), MxSize32, "k", "printPCI32Mem", MxPCI>;
+def MxPCI8   : MxMemOp<(ops i8imm:$disp, XR32:$index), MxSize8,  "k", "printPCI8Mem", MxPCI>;
+def MxPCI16  : MxMemOp<(ops i8imm:$disp, XR32:$index), MxSize16, "k", "printPCI16Mem", MxPCI>;
+def MxPCI32  : MxMemOp<(ops i8imm:$disp, XR32:$index), MxSize32, "k", "printPCI32Mem", MxPCI>;
 } // OPERAND_PCREL
 
 def MxImm : AsmOperandClass {
   let Name = "MxImm";
   let PredicateMethod = "isImm";
   let RenderMethod = "addImmOperands";
   let ParserMethod = "parseImm";
 }

llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp

 
 namespace {
 class M68kMCCodeEmitter : public MCCodeEmitter {
   M68kMCCodeEmitter(const M68kMCCodeEmitter &) = delete;
   void operator=(const M68kMCCodeEmitter &) = delete;
   const MCInstrInfo &MCII;
   MCContext &Ctx;
 
+  void getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
+                             APInt &Inst, APInt &Scratch,
+                             const MCSubtargetInfo &STI) const;
+
+  void getMachineOpValue(const MCInst &MI, const MCOperand &Op,
+                         APInt &Value,
+                         SmallVectorImpl<MCFixup> &Fixups,
+                         const MCSubtargetInfo &STI) const;
+
 public:
   M68kMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
       : MCII(mcii), Ctx(ctx) {}
 
   ~M68kMCCodeEmitter() override {}
 
   // TableGen'erated function
   const uint8_t *getGenInstrBeads(const MCInst &MI) const {
public:
 
   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const override;
 };
 
 } // end anonymous namespace
 
+#include "M68kGenMCCodeEmitter.inc"
+
+void M68kMCCodeEmitter::getMachineOpValue(const MCInst &MI,
+                                          const MCOperand &Op,
+                                          APInt &Value,
+                                          SmallVectorImpl<MCFixup> &Fixups,
+                                          const MCSubtargetInfo &STI) const {
+  // Register
+  if (Op.isReg()) {
+    unsigned RegNum = Op.getReg();
+    const auto *RI = Ctx.getRegisterInfo();
+    uint32_t Val = RI->getEncodingValue(RegNum);
+    // Setup the D/A bit
+    if (M68kII::isAddressRegister(RegNum))
+      Val |= 0b1000;
+    Value |= Val;
+  } else if (Op.isImm()) {
+    // Immediate
+    Value |= static_cast<uint64_t>(Op.getImm());
+  } else {
+    llvm_unreachable("Unsupported operand type");
+  }
+}
+
 unsigned M68kMCCodeEmitter::encodeBits(unsigned ThisByte, uint8_t Bead,
                                        const MCInst &MI,
                                        const MCInstrDesc &Desc,
                                        uint64_t &Buffer, unsigned Offset,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        const MCSubtargetInfo &STI) const {
   unsigned Num = 0;
   switch (Bead & 0xF) {
void M68kMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                           SmallVectorImpl<MCFixup> &Fixups,
                                           const MCSubtargetInfo &STI) const {
   unsigned Opcode = MI.getOpcode();
   const MCInstrDesc &Desc = MCII.get(Opcode);
 
   LLVM_DEBUG(dbgs() << "EncodeInstruction: " << MCII.getName(Opcode) << "("
                     << Opcode << ")\n");
 
+  // Try using the new method first.
+  APInt EncodedInst(16, 0U);
+  APInt Scratch(16, 0U);
+  getBinaryCodeForInstr(MI, Fixups, EncodedInst, Scratch, STI);
+  if (EncodedInst.getBitWidth()) {
+    LLVM_DEBUG(dbgs() << "Instruction " << MCII.getName(Opcode) << "("
+                      << Opcode << ") is using the new code emitter\n");
+    ArrayRef<uint64_t> Data(EncodedInst.getRawData(),
+                            EncodedInst.getNumWords());
+    int64_t InstSize = EncodedInst.getBitWidth();
+    for (uint64_t Word : Data) {
+      for (int i = 0; i < 4 && InstSize > 0; ++i, InstSize -= 16) {
+        support::endian::write<uint16_t>(OS, static_cast<uint16_t>(Word),
+                                         support::big);
+        Word >>= 16;
+      }
+    }
+    return;
+  }
+
   const uint8_t *Beads = getGenInstrBeads(MI);
   if (!Beads || !*Beads) {
     llvm_unreachable("*** Instruction does not have Beads defined");
   }
 
   uint64_t Buffer = 0;
   unsigned Offset = 0;
   unsigned ThisByte = 0;

llvm/test/CodeGen/M68k/Control/cmp.ll

 ; CHECK-NEXT:    movem.l %d2, (0,%sp) ; 8-byte Folded Spill
 ; CHECK-NEXT:    move.l #16777215, %d0
 ; CHECK-NEXT:    and.l (8,%sp), %d0
 ; CHECK-NEXT:    sne %d1
 ; CHECK-NEXT:    and.l #255, %d1
 ; CHECK-NEXT:    move.l (16,%sp), %a0
 ; CHECK-NEXT:    move.b (15,%sp), %d2
 ; CHECK-NEXT:    and.l #255, %d2
-; CHECK-NEXT:    add.l %d2, %d1
+; CHECK-NEXT:    add.l %d1, %d2
 ; CHECK-NEXT:    sne (%a0)
 ; CHECK-NEXT:    cmpi.l #0, %d0
 ; CHECK-NEXT:    lea (d,%pc), %a0
 ; CHECK-NEXT:    sne (%a0)
 ; CHECK-NEXT:    movem.l (0,%sp), %d2 ; 8-byte Folded Reload
 ; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
   %bf.shl = shl i32 %bf.load, 8

llvm/test/MC/Disassembler/M68k/instructions.txt

 # RUN: llvm-mc -disassemble -triple m68k %s | FileCheck %s
+# Disable all disassembler tests until the migration to the new code emitter
+# is finished.
+# XFAIL: *
 
 # CHECK: move.l %a1, %a0
 0x20 0x49
 # CHECK: adda.l %a0, %a1
 0xd3 0xc8
 # CHECK: sub.w %d3, %d1
 0x92 0x43
 # CHECK: cmp.w %d1, %d0