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Differential D114792

[AMDGPU] Test for in-order waitcnt insertion for bvh instructions
ClosedPublic

Authored by dstuttard on Nov 30 2021, 5:54 AM.

Details

Reviewers
foad
rampitec
Commits
rG17a3385c3538: [AMDGPU] Test for in-order waitcnt insertion for bvh instructions
Summary

In-order bvh instructions don't require a waitcnt as order is
guaranteed.

However, waitcnt IS required for other image instruction types vs
bvh.

Pre-commit test for new functionality.

Diff Detail

Event Timeline

dstuttard created this revision.Nov 30 2021, 5:54 AM
Herald added subscribers: kerbowa, t-tye, tpr and 4 others. · View Herald TranscriptNov 30 2021, 5:54 AM
dstuttard requested review of this revision.Nov 30 2021, 5:54 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 30 2021, 5:54 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
dstuttard added reviewers: foad, rampitec.Nov 30 2021, 5:58 AM

Pre-commit test

dstuttard updated this revision to Diff 390677.Nov 30 2021, 6:03 AM

Updating with link to change for which this is a pre-commit

(https://reviews.llvm.org/D114794)

foad added inline comments.Nov 30 2021, 6:05 AM
llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir
4

I think the canonical YAML format is to have --- before each function and ... after it, like this:

---
function goes here
...
8

It looks like these checks are (or could be?) autogenerated, but there's no "autogenerated by" comment on line 1.

foad added a child revision: D114794: [AMDGPU] Add support for in-order bvh in waitcnt pass.Nov 30 2021, 6:06 AM
dstuttard added inline comments.Nov 30 2021, 6:08 AM
llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir
4

Ok

8

They weren't autogenerated - but that's a good point, there's no reason why not. I'll update it.

dstuttard updated this revision to Diff 390684.Nov 30 2021, 6:22 AM

Updating test in light of review suggestions

foad accepted this revision.Nov 30 2021, 6:26 AM

LGTM. Maybe wait a little in case people in other time zones have comments.

This revision is now accepted and ready to land.Nov 30 2021, 6:26 AM
Harbormaster completed remote builds in B136678: Diff 390684.Nov 30 2021, 7:03 AM
Closed by commit rG17a3385c3538: [AMDGPU] Test for in-order waitcnt insertion for bvh instructions (authored by dstuttard). · Explain WhyDec 2 2021, 6:26 AM
This revision was automatically updated to reflect the committed changes.
dstuttard added a commit: rG17a3385c3538: [AMDGPU] Test for in-order waitcnt insertion for bvh instructions.

Revision Contents

PathSize
llvm/
test/
CodeGen/
AMDGPU/
55 lines

Diff 390677

llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir

  • This file was added.
# RUN: llc -march=amdgcn -mcpu=gfx1030 -run-pass=si-insert-waitcnts -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
...
name: waitcnt-check-inorder
foadUnsubmitted
Not Done
ReplyInline Actions

I think the canonical YAML format is to have --- before each function and ... after it, like this:

---
function goes here
...
foad: I think the canonical YAML format is to have `---` before each function and `...` after it…
dstuttardAuthorUnsubmitted
Done
ReplyInline Actions

Ok

dstuttard: Ok
body: |
bb.0:
; GCN-LABEL: name: waitcnt-check-inorder
; GCN: $vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_BVH_INTERSECT_RAY_sa_gfx10 killed $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19
foadUnsubmitted
Not Done
ReplyInline Actions

It looks like these checks are (or could be?) autogenerated, but there's no "autogenerated by" comment on line 1.

foad: It looks like these checks are (or could be?) autogenerated, but there's no "autogenerated by"…
dstuttardAuthorUnsubmitted
Done
ReplyInline Actions

They weren't autogenerated - but that's a good point, there's no reason why not. I'll update it.

dstuttard: They weren't autogenerated - but that's a good point, there's no reason why not. I'll update it.
; GCN-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_BVH_INTERSECT_RAY_sa_gfx10 killed $vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35
$vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_BVH_INTERSECT_RAY_sa_gfx10 killed $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19, renamable $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec :: (dereferenceable load (s128) from custom "ImageResource")
$vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_BVH_INTERSECT_RAY_sa_gfx10 killed $vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec :: (dereferenceable load (s128) from custom "ImageResource")
S_ENDPGM 0
...
name: waitcnt-check-vs-vmem
body: |
bb.0:
; GCN-LABEL: name: waitcnt-check-vs-vmem
; GCN: $vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_BVH_INTERSECT_RAY_sa_gfx10 killed $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19
; GCN-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr16, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
$vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_BVH_INTERSECT_RAY_sa_gfx10 killed $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19, renamable $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec :: (dereferenceable load (s128) from custom "ImageResource")
$vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr16, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0
...
name: waitcnt-check-vs-mimg-samp
body: |
bb.0:
; GCN-LABEL: name: waitcnt-check-vs-mimg-samp
; GCN: $vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_BVH_INTERSECT_RAY_sa_gfx10 killed $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19
; GCN-NEXT: S_WAITCNT 16240
; GCN-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_SAMPLE_V4_V2 $vgpr20_vgpr21
$vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_BVH_INTERSECT_RAY_sa_gfx10 killed $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec :: (dereferenceable load (s128) from custom "ImageResource")
$vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_SAMPLE_V4_V2 $vgpr20_vgpr21, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)
S_ENDPGM 0
...
name: waitcnt-check-vs-vmem-reverse
body: |
bb.0:
; GCN-LABEL: name: waitcnt-check-vs-vmem-reverse
; GCN: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr20, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
; GCN-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_BVH_INTERSECT_RAY_sa_gfx10 killed $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19
$vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr20, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
$vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_BVH_INTERSECT_RAY_sa_gfx10 killed $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec :: (dereferenceable load (s128) from custom "ImageResource")
S_ENDPGM 0
...
name: waitcnt-check-vs-mimg-samp-reverse
body: |
bb.0:
; GCN-LABEL: name: waitcnt-check-vs-mimg-samp-reverse
; GCN: $vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_SAMPLE_V4_V2 $vgpr16_vgpr17
; GCN-NEXT: S_WAITCNT 16240
; GCN-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_BVH_INTERSECT_RAY_sa_gfx10 killed $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19
$vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_SAMPLE_V4_V2 $vgpr16_vgpr17, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)
$vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_BVH_INTERSECT_RAY_sa_gfx10 killed $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec :: (dereferenceable load (s128) from custom "ImageResource")
S_ENDPGM 0
...