Big-endian version of vpermxor

[tislam]

Summary

A big-endian version of vpermxor, named vpermxor_be, is added to LLVM and Clang. vpermxor_be can be called directly on both the little-endian and the big-endian platforms.

[nemanjai]

Please also add a test for this builtin to the front end test clang/test/CodeGen/builtins-ppc-crypto.c

llvm/lib/Target/PowerPC/PPCInstrVSX.td

2500

Although it would be redundant, it is not invalid to use this builtin/intrinsic in BE compilations. As such, please move this to a block that has only the
[HasVSX, HasP8Altivec] predicates as the desired code is the same for LE/BE.

llvm/test/CodeGen/PowerPC/crypto_bifs_be.ll

10

Please clean up this test case a bit:

• Run opt --passes="default<O2>" on it to clean up the unnecessary code
• Remove the attributes
• The 755 permissions on the test case are unusual
• Produce the CHECK's automatically using $LLVM_SRC/utils/update_llc_test_checks.py
• Add a BE invocation (either the P8 or the P9 can just use the powerpc64-unknown-linux-gnu triple)

[tislam]

• Added test for vpermxor_be in clang/test/CodeGen/builtins-ppc-crypto.c.
• Placed vpermxor_be under [HasVSX, HasP8Altivec] in llvm/lib/Target/PowerPC/PPCInstrVSX.td.
• Updated test llvm/test/CodeGen/PowerPC/crypto_bifs_be.ll.

[nemanjai]

LGTM.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

2506

Nit: the v16i8 should be aligned with the v16i8 above.

llvm/test/CodeGen/PowerPC/crypto_bifs_be.ll

9

There isn't really any difference in how we handle this on P9 so this run line is probably superfluous. Feel free to get rid of it when pushing this upstream.

[tislam]

• The P9 RUN step on big-endian platform is removed from the lit test.
• Fixed formatting in llvm/lib/Target/PowerPC/PPCInstrVSX.td

clang/include/clang/Basic/BuiltinsPPC.def

 
 BUILTIN(__builtin_altivec_vgbbd, "V16UcV16Uc", "")
 BUILTIN(__builtin_altivec_vbpermq, "V2ULLiV16UcV16Uc", "")
 BUILTIN(__builtin_altivec_vbpermd, "V2ULLiV2ULLiV16Uc", "")
 
 // P8 Crypto built-ins.
 BUILTIN(__builtin_altivec_crypto_vsbox, "V2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_crypto_vpermxor, "V16UcV16UcV16UcV16Uc", "")
+BUILTIN(__builtin_altivec_crypto_vpermxor_be, "V16UcV16UcV16UcV16Uc", "")
 BUILTIN(__builtin_altivec_crypto_vshasigmaw, "V4UiV4UiIiIi", "")
 BUILTIN(__builtin_altivec_crypto_vshasigmad, "V2ULLiV2ULLiIiIi", "")
 BUILTIN(__builtin_altivec_crypto_vcipher, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_crypto_vcipherlast, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_crypto_vncipher, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_crypto_vncipherlast, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_crypto_vpmsumb, "V16UcV16UcV16Uc", "")
 BUILTIN(__builtin_altivec_crypto_vpmsumh, "V8UsV8UsV8Us", "")

clang/test/CodeGen/builtins-ppc-crypto.c

 // CHECK-LABEL: test_vpermxoruc
 vector unsigned char test_vpermxoruc(vector unsigned char a,
                                      vector unsigned char b,
                                      vector unsigned char c) {
   return vec_permxor(a, b, c);
 // CHECK: @llvm.ppc.altivec.crypto.vpermxor
 }
 
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vpermxorb_be
+vector unsigned char test_vpermxorb_be(vector unsigned char a,
+                                       vector unsigned char b,
+                                       vector unsigned char c) {
+  return __builtin_altivec_crypto_vpermxor_be(a, b, c);
+// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be
+}
+
+// CHECK-LABEL: define{{.*}} <8 x i16> @test_vpermxorh_be
+vector unsigned short test_vpermxorh_be(vector unsigned short a,
+                                        vector unsigned short b,
+                                        vector unsigned short c) {
+  return __builtin_altivec_crypto_vpermxor_be(a, b, c);
+// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be
+}
+
+// CHECK-LABEL: define{{.*}} <4 x i32> @test_vpermxorw_be
+vector unsigned int test_vpermxorw_be(vector unsigned int a,
+                                      vector unsigned int b,
+                                      vector unsigned int c) {
+  return __builtin_altivec_crypto_vpermxor_be(a, b, c);
+// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be
+}
+
+// CHECK-LABEL: define{{.*}} <2 x i64> @test_vpermxord_be
+vector unsigned long long test_vpermxord_be(vector unsigned long long a,
+                                            vector unsigned long long b,
+                                            vector unsigned long long c) {
+  return __builtin_altivec_crypto_vpermxor_be(a, b, c);
+// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be
+}
+
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vpermxorbc_be
+vector bool char test_vpermxorbc_be(vector bool char a,
+                                    vector bool char b,
+                                    vector bool char c) {
+  return  __builtin_altivec_crypto_vpermxor_be(a, b, c);
+// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be
+}
+
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vpermxorsc_be
+vector signed char test_vpermxorsc_be(vector signed char a,
+                                      vector signed char b,
+                                      vector signed char c) {
+  return  __builtin_altivec_crypto_vpermxor_be(a, b, c);
+// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be
+}
+
+// CHECK-LABEL: define{{.*}} <16 x i8> @test_vpermxoruc_be
+vector unsigned char test_vpermxoruc_be(vector unsigned char a,
+                                        vector unsigned char b,
+                                        vector unsigned char c) {
+  return  __builtin_altivec_crypto_vpermxor_be(a, b, c);
+// CHECK: @llvm.ppc.altivec.crypto.vpermxor.be
+}
+
 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vcipher
 vector unsigned long long test_vcipher(void)
 {
   vector unsigned long long a = D_INIT1
   vector unsigned long long b = D_INIT2
   return __builtin_altivec_crypto_vcipher(a, b);
 // CHECK: @llvm.ppc.altivec.crypto.vcipher
 }

llvm/include/llvm/IR/IntrinsicsPowerPC.td

 let TargetPrefix = "ppc" in {  // All PPC intrinsics start with "llvm.ppc.".
   def int_ppc_altivec_crypto_vsbox :
               GCCBuiltin<"__builtin_altivec_crypto_vsbox">,
               Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty], [IntrNoMem]>;
   def int_ppc_altivec_crypto_vpermxor :
               GCCBuiltin<"__builtin_altivec_crypto_vpermxor">,
               Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
                          llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
+  def int_ppc_altivec_crypto_vpermxor_be :
+              GCCBuiltin<"__builtin_altivec_crypto_vpermxor_be">,
+              Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
+                         llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
 
 def int_ppc_altivec_crypto_vshasigmad :
             GCCBuiltin<"__builtin_altivec_crypto_vshasigmad">,
             Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,
                        llvm_i32_ty, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
 def int_ppc_altivec_crypto_vshasigmaw :
             GCCBuiltin<"__builtin_altivec_crypto_vshasigmaw">,
             Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,

llvm/lib/Target/PowerPC/PPCInstrVSX.td

 // [HasVSX, HasOnlySwappingMemOps]
 // [HasVSX, HasOnlySwappingMemOps, IsBigEndian]
 // [HasVSX, HasP8Vector]
 // [HasVSX, HasP8Vector, IsBigEndian]
 // [HasVSX, HasP8Vector, IsBigEndian, IsPPC64]
 // [HasVSX, HasP8Vector, IsLittleEndian]
 // [HasVSX, HasP8Vector, NoP9Vector, IsBigEndian, IsPPC64]
 // [HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian]
+// [HasVSX, HasP8Altivec]
 // [HasVSX, HasDirectMove]
 // [HasVSX, HasDirectMove, IsBigEndian]
 // [HasVSX, HasDirectMove, IsLittleEndian]
 // [HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian, IsPPC64]
 // [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64]
 // [HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian]
 // [HasVSX, HasDirectMove, NoP9Vector, IsLittleEndian]
 // [HasVSX, HasP9Vector]

 
 // These Altivec patterns are here because we need a VSX instruction to match
 // the intrinsic (but only for little endian system).
 let Predicates = [HasVSX, IsLittleEndian, HasP8Altivec] in
   def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor v16i8:$a,
                                                     v16i8:$b, v16i8:$c)),
             (v16i8 (VPERMXOR $a, $b, (XXLNOR (COPY_TO_REGCLASS $c, VSRC),
                                              (COPY_TO_REGCLASS $c, VSRC))))>;
 let Predicates = [HasVSX, IsBigEndian, HasP8Altivec] in
   def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor v16i8:$a,
                                                     v16i8:$b, v16i8:$c)),
             (v16i8 (VPERMXOR $a, $b, $c))>;
+let Predicates = [HasVSX, HasP8Altivec] in
+  def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor_be v16i8:$a,
+                                                       v16i8:$b, v16i8:$c)),
+            (v16i8 (VPERMXOR $a, $b, $c))>;
 
 let AddedComplexity = 400 in {
 // Valid for any VSX subtarget, regardless of endianness.
 let Predicates = [HasVSX] in {
 def : Pat<(v4i32 (vnot v4i32:$A)),
           (v4i32 (XXLNOR $A, $A))>;
 def : Pat<(v4i32 (or (and (vnot v4i32:$C), v4i32:$A),
                      (and v4i32:$B, v4i32:$C))),

llvm/test/CodeGen/PowerPC/crypto_bifs_be.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefixes=CHECK-LE-P8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefixes=CHECK-P9
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefixes=CHECK-BE-P8
+
+define <16 x i8> @test_vpermxorb() local_unnamed_addr {
+; CHECK-LE-P8-LABEL: test_vpermxorb:
+; CHECK-LE-P8:       # %bb.0: # %entry
+; CHECK-LE-P8-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
+; CHECK-LE-P8-NEXT:    addis 4, 2, .LCPI0_1@toc@ha
+; CHECK-LE-P8-NEXT:    addi 3, 3, .LCPI0_0@toc@l
+; CHECK-LE-P8-NEXT:    lvx 2, 0, 3
+; CHECK-LE-P8-NEXT:    addi 3, 4, .LCPI0_1@toc@l
+; CHECK-LE-P8-NEXT:    lvx 3, 0, 3
+; CHECK-LE-P8-NEXT:    vpermxor 2, 3, 2, 2
+; CHECK-LE-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: test_vpermxorb:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
+; CHECK-P9-NEXT:    addi 3, 3, .LCPI0_0@toc@l
+; CHECK-P9-NEXT:    lxv 34, 0(3)
+; CHECK-P9-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
+; CHECK-P9-NEXT:    addi 3, 3, .LCPI0_1@toc@l
+; CHECK-P9-NEXT:    lxv 35, 0(3)
+; CHECK-P9-NEXT:    vpermxor 2, 3, 2, 2
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-BE-P8-LABEL: test_vpermxorb:
+; CHECK-BE-P8:       # %bb.0: # %entry
+; CHECK-BE-P8-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
+; CHECK-BE-P8-NEXT:    addis 4, 2, .LCPI0_1@toc@ha
+; CHECK-BE-P8-NEXT:    addi 3, 3, .LCPI0_0@toc@l
+; CHECK-BE-P8-NEXT:    addi 4, 4, .LCPI0_1@toc@l
+; CHECK-BE-P8-NEXT:    lxvw4x 34, 0, 3
+; CHECK-BE-P8-NEXT:    lxvw4x 35, 0, 4
+; CHECK-BE-P8-NEXT:    vpermxor 2, 3, 2, 2
+; CHECK-BE-P8-NEXT:    blr
+entry:
+  %0 = tail call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor.be(<16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8> <i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 112>, <16 x i8> <i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 112>)
+  ret <16 x i8> %0
+}
+
+declare <16 x i8> @llvm.ppc.altivec.crypto.vpermxor.be(<16 x i8>, <16 x i8>, <16 x i8>)
+
+define <8 x i16> @test_vpermxorh() local_unnamed_addr {
+; CHECK-LE-P8-LABEL: test_vpermxorh:
+; CHECK-LE-P8:       # %bb.0: # %entry
+; CHECK-LE-P8-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
+; CHECK-LE-P8-NEXT:    addis 4, 2, .LCPI1_1@toc@ha
+; CHECK-LE-P8-NEXT:    addi 3, 3, .LCPI1_0@toc@l
+; CHECK-LE-P8-NEXT:    lvx 2, 0, 3
+; CHECK-LE-P8-NEXT:    addi 3, 4, .LCPI1_1@toc@l
+; CHECK-LE-P8-NEXT:    lvx 3, 0, 3
+; CHECK-LE-P8-NEXT:    vpermxor 2, 3, 2, 2
+; CHECK-LE-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: test_vpermxorh:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
+; CHECK-P9-NEXT:    addi 3, 3, .LCPI1_0@toc@l
+; CHECK-P9-NEXT:    lxv 34, 0(3)
+; CHECK-P9-NEXT:    addis 3, 2, .LCPI1_1@toc@ha
+; CHECK-P9-NEXT:    addi 3, 3, .LCPI1_1@toc@l
+; CHECK-P9-NEXT:    lxv 35, 0(3)
+; CHECK-P9-NEXT:    vpermxor 2, 3, 2, 2
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-BE-P8-LABEL: test_vpermxorh:
+; CHECK-BE-P8:       # %bb.0: # %entry
+; CHECK-BE-P8-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
+; CHECK-BE-P8-NEXT:    addis 4, 2, .LCPI1_1@toc@ha
+; CHECK-BE-P8-NEXT:    addi 3, 3, .LCPI1_0@toc@l
+; CHECK-BE-P8-NEXT:    addi 4, 4, .LCPI1_1@toc@l
+; CHECK-BE-P8-NEXT:    lxvw4x 34, 0, 3
+; CHECK-BE-P8-NEXT:    lxvw4x 35, 0, 4
+; CHECK-BE-P8-NEXT:    vpermxor 2, 3, 2, 2
+; CHECK-BE-P8-NEXT:    blr
+entry:
+  %0 = tail call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor.be(<16 x i8> <i8 2, i8 1, i8 4, i8 3, i8 6, i8 5, i8 8, i8 7, i8 10, i8 9, i8 12, i8 11, i8 14, i8 13, i8 16, i8 15>, <16 x i8> <i8 114, i8 113, i8 116, i8 115, i8 118, i8 117, i8 120, i8 119, i8 122, i8 121, i8 124, i8 123, i8 126, i8 125, i8 112, i8 127>, <16 x i8> <i8 114, i8 113, i8 116, i8 115, i8 118, i8 117, i8 120, i8 119, i8 122, i8 121, i8 124, i8 123, i8 126, i8 125, i8 112, i8 127>)
+  %1 = bitcast <16 x i8> %0 to <8 x i16>
+  ret <8 x i16> %1
+}
+
+define <4 x i32> @test_vpermxorw() local_unnamed_addr {
+; CHECK-LE-P8-LABEL: test_vpermxorw:
+; CHECK-LE-P8:       # %bb.0: # %entry
+; CHECK-LE-P8-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
+; CHECK-LE-P8-NEXT:    addis 4, 2, .LCPI2_1@toc@ha
+; CHECK-LE-P8-NEXT:    addi 3, 3, .LCPI2_0@toc@l
+; CHECK-LE-P8-NEXT:    lvx 2, 0, 3
+; CHECK-LE-P8-NEXT:    addi 3, 4, .LCPI2_1@toc@l
+; CHECK-LE-P8-NEXT:    lvx 3, 0, 3
+; CHECK-LE-P8-NEXT:    vpermxor 2, 3, 2, 2
+; CHECK-LE-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: test_vpermxorw:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
+; CHECK-P9-NEXT:    addi 3, 3, .LCPI2_0@toc@l
+; CHECK-P9-NEXT:    lxv 34, 0(3)
+; CHECK-P9-NEXT:    addis 3, 2, .LCPI2_1@toc@ha
+; CHECK-P9-NEXT:    addi 3, 3, .LCPI2_1@toc@l
+; CHECK-P9-NEXT:    lxv 35, 0(3)
+; CHECK-P9-NEXT:    vpermxor 2, 3, 2, 2
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-BE-P8-LABEL: test_vpermxorw:
+; CHECK-BE-P8:       # %bb.0: # %entry
+; CHECK-BE-P8-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
+; CHECK-BE-P8-NEXT:    addis 4, 2, .LCPI2_1@toc@ha
+; CHECK-BE-P8-NEXT:    addi 3, 3, .LCPI2_0@toc@l
+; CHECK-BE-P8-NEXT:    addi 4, 4, .LCPI2_1@toc@l
+; CHECK-BE-P8-NEXT:    lxvw4x 34, 0, 3
+; CHECK-BE-P8-NEXT:    lxvw4x 35, 0, 4
+; CHECK-BE-P8-NEXT:    vpermxor 2, 3, 2, 2
+; CHECK-BE-P8-NEXT:    blr
+entry:
+  %0 = tail call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor.be(<16 x i8> <i8 4, i8 3, i8 2, i8 1, i8 8, i8 7, i8 6, i8 5, i8 12, i8 11, i8 10, i8 9, i8 16, i8 15, i8 14, i8 13>, <16 x i8> <i8 116, i8 115, i8 114, i8 113, i8 120, i8 119, i8 118, i8 117, i8 124, i8 123, i8 122, i8 121, i8 112, i8 127, i8 126, i8 125>, <16 x i8> <i8 116, i8 115, i8 114, i8 113, i8 120, i8 119, i8 118, i8 117, i8 124, i8 123, i8 122, i8 121, i8 112, i8 127, i8 126, i8 125>)
+  %1 = bitcast <16 x i8> %0 to <4 x i32>
+  ret <4 x i32> %1
+}
+
+define <2 x i64> @test_vpermxord() local_unnamed_addr {
+; CHECK-LE-P8-LABEL: test_vpermxord:
+; CHECK-LE-P8:       # %bb.0: # %entry
+; CHECK-LE-P8-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
+; CHECK-LE-P8-NEXT:    addis 4, 2, .LCPI3_1@toc@ha
+; CHECK-LE-P8-NEXT:    addi 3, 3, .LCPI3_0@toc@l
+; CHECK-LE-P8-NEXT:    lvx 2, 0, 3
+; CHECK-LE-P8-NEXT:    addi 3, 4, .LCPI3_1@toc@l
+; CHECK-LE-P8-NEXT:    lvx 3, 0, 3
+; CHECK-LE-P8-NEXT:    vpermxor 2, 3, 2, 2
+; CHECK-LE-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: test_vpermxord:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
+; CHECK-P9-NEXT:    addi 3, 3, .LCPI3_0@toc@l
+; CHECK-P9-NEXT:    lxv 34, 0(3)
+; CHECK-P9-NEXT:    addis 3, 2, .LCPI3_1@toc@ha
+; CHECK-P9-NEXT:    addi 3, 3, .LCPI3_1@toc@l
+; CHECK-P9-NEXT:    lxv 35, 0(3)
+; CHECK-P9-NEXT:    vpermxor 2, 3, 2, 2
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-BE-P8-LABEL: test_vpermxord:
+; CHECK-BE-P8:       # %bb.0: # %entry
+; CHECK-BE-P8-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
+; CHECK-BE-P8-NEXT:    addis 4, 2, .LCPI3_1@toc@ha
+; CHECK-BE-P8-NEXT:    addi 3, 3, .LCPI3_0@toc@l
+; CHECK-BE-P8-NEXT:    addi 4, 4, .LCPI3_1@toc@l
+; CHECK-BE-P8-NEXT:    lxvw4x 34, 0, 3
+; CHECK-BE-P8-NEXT:    lxvw4x 35, 0, 4
+; CHECK-BE-P8-NEXT:    vpermxor 2, 3, 2, 2
+; CHECK-BE-P8-NEXT:    blr
+entry:
+  %0 = tail call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor.be(<16 x i8> <i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9>, <16 x i8> <i8 120, i8 119, i8 118, i8 117, i8 116, i8 115, i8 114, i8 113, i8 112, i8 127, i8 126, i8 125, i8 124, i8 123, i8 122, i8 121>, <16 x i8> <i8 120, i8 119, i8 118, i8 117, i8 116, i8 115, i8 114, i8 113, i8 112, i8 127, i8 126, i8 125, i8 124, i8 123, i8 122, i8 121>)
+  %1 = bitcast <16 x i8> %0 to <2 x i64>
+  ret <2 x i64> %1
+}
+