This is an archive of the discontinued LLVM Phabricator instance.

Differential D114499

[GlobalISel] Fold or of shifts to funnel shifts.
ClosedPublic

Authored by abinavpp on Nov 23 2021, 9:04 PM.

Details

Reviewers
aemerson
arsenm
foad
paquette
Commits
rG4af45f10cccb: [GlobalISel] Fold or of shifts to funnel shift.
Summary

This change folds a basic funnel shift idiom:

  • (or (shl x, amt), (lshr y, sub(bw, amt))) -> fshl(x, y, amt)
  • (or (shl x, sub(bw, amt)), (lshr y, amt)) -> fshr(x, y, amt)

This also helps in folding to rotate shift if x and y are equal since we
already have a funnel shift to rotate combine.

Diff Detail

Event Timeline

abinavpp created this revision.Nov 23 2021, 9:04 PM
Herald added subscribers: kerbowa, hiraditya, rovka and 2 others. · View Herald TranscriptNov 23 2021, 9:04 PM
abinavpp requested review of this revision.Nov 23 2021, 9:04 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 23 2021, 9:04 PM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
abinavpp added a comment.Nov 23 2021, 9:08 PM

Verification: https://alive2.llvm.org/ce/z/5UeARb, https://alive2.llvm.org/ce/z/YPorGw

Harbormaster completed remote builds in B135775: Diff 389385.Nov 23 2021, 9:49 PM
foad added a comment.Nov 24 2021, 7:31 AM

(or (shl x, amt), (lshr y, sub(bw, amt)) -> fshl(x, y)
(or (shl x, sub(bw, amt), (lshr y, amt)) -> fshr(x, y)

Funnel shifts take three arguments "x, y, amt".

foad added inline comments.Nov 24 2021, 7:39 AM
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
3881

Missing right paren after sub(bw, amt).

3889

Missing right paren after sub(bw, amt).

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
18

Huh? The funnel shift amount should surely be %amt not %bw.

abinavpp added inline comments.Nov 24 2021, 6:24 PM
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
18

D'oh!

abinavpp updated this revision to Diff 389636.Nov 24 2021, 6:36 PM

Addressed review comments.

abinavpp edited the summary of this revision. (Show Details)Nov 24 2021, 6:41 PM
abinavpp marked 3 inline comments as done.
Harbormaster completed remote builds in B135956: Diff 389636.Nov 24 2021, 7:20 PM
foad accepted this revision.Nov 25 2021, 1:15 AM

LGTM. But why doesn't it already work on vectors? And would it be worth adding support for constant shift amounts like (or (shl x, 20), (lshr x, 12))?

This revision is now accepted and ready to land.Nov 25 2021, 1:15 AM
abinavpp added a comment.Nov 26 2021, 3:30 AM
In D114499#3153099, @foad wrote:

But why doesn't it already work on vectors?

We're not matching the constant splat here. D114625 should fix this, if I haven't missed anything.

In D114499#3153099, @foad wrote:

And would it be worth adding support for constant shift amounts like (or (shl x, 20), (lshr x, 12))?

Yes, we need to extend the pattern match.

Closed by commit rG4af45f10cccb: [GlobalISel] Fold or of shifts to funnel shift. (authored by abinavpp). · Explain WhyNov 26 2021, 4:04 AM
This revision was automatically updated to reflect the committed changes.
abinavpp added a commit: rG4af45f10cccb: [GlobalISel] Fold or of shifts to funnel shift..
abinavpp added a comment.Jan 3 2022, 2:39 AM
In D114499#3153099, @foad wrote:

And would it be worth adding support for constant shift amounts like (or (shl x, 20), (lshr x, 12))?

Yes, we need to extend the pattern match.

D116529

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
1 line
Target/
GlobalISel/
10 lines
lib/
CodeGen/
GlobalISel/
45 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
142 lines
131 lines

Diff 389989

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

Show First 20 Lines • Show All 558 Lines • ▼ Show 20 Linespublic:
/// Use a function which takes in a MachineIRBuilder to perform a combine. /// Use a function which takes in a MachineIRBuilder to perform a combine.
/// By default, it erases the instruction \p MI from the function. /// By default, it erases the instruction \p MI from the function.
void applyBuildFn(MachineInstr &MI, BuildFnTy &MatchInfo); void applyBuildFn(MachineInstr &MI, BuildFnTy &MatchInfo);
/// Use a function which takes in a MachineIRBuilder to perform a combine. /// Use a function which takes in a MachineIRBuilder to perform a combine.
/// This variant does not erase \p MI after calling the build function. /// This variant does not erase \p MI after calling the build function.
void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo); void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo);
bool matchOrShiftToFunnelShift(MachineInstr &MI, BuildFnTy &MatchInfo);
bool matchFunnelShiftToRotate(MachineInstr &MI); bool matchFunnelShiftToRotate(MachineInstr &MI);
void applyFunnelShiftToRotate(MachineInstr &MI); void applyFunnelShiftToRotate(MachineInstr &MI);
bool matchRotateOutOfRange(MachineInstr &MI); bool matchRotateOutOfRange(MachineInstr &MI);
void applyRotateOutOfRange(MachineInstr &MI); void applyRotateOutOfRange(MachineInstr &MI);
/// \returns true if a G_ICMP instruction \p MI can be replaced with a true /// \returns true if a G_ICMP instruction \p MI can be replaced with a true
/// or false constant based off of KnownBits information. /// or false constant based off of KnownBits information.
bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo); bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo);
▲ Show 20 Lines • Show All 125 Lines • Show Last 20 Lines

llvm/include/llvm/Target/GlobalISel/Combine.td

Show First 20 Lines • Show All 639 Lines • ▼ Show 20 Linesdef extract_all_elts_from_build_vector : GICombineRule<
(match (wip_match_opcode G_BUILD_VECTOR):$root, (match (wip_match_opcode G_BUILD_VECTOR):$root,
[{ return Helper.matchExtractAllEltsFromBuildVector(*${root}, ${matchinfo}); }]), [{ return Helper.matchExtractAllEltsFromBuildVector(*${root}, ${matchinfo}); }]),
(apply [{ Helper.applyExtractAllEltsFromBuildVector(*${root}, ${matchinfo}); }])>; (apply [{ Helper.applyExtractAllEltsFromBuildVector(*${root}, ${matchinfo}); }])>;
def extract_vec_elt_combines : GICombineGroup<[ def extract_vec_elt_combines : GICombineGroup<[
extract_vec_elt_build_vec, extract_vec_elt_build_vec,
extract_all_elts_from_build_vector]>; extract_all_elts_from_build_vector]>;
def funnel_shift_from_or_shift : GICombineRule<
(defs root:$root, build_fn_matchinfo:$info),
(match (wip_match_opcode G_OR):$root,
[{ return Helper.matchOrShiftToFunnelShift(*${root}, ${info}); }]),
(apply [{ Helper.applyBuildFn(*${root}, ${info}); }])
>;
def funnel_shift_to_rotate : GICombineRule< def funnel_shift_to_rotate : GICombineRule<
(defs root:$root), (defs root:$root),
(match (wip_match_opcode G_FSHL, G_FSHR):$root, (match (wip_match_opcode G_FSHL, G_FSHR):$root,
[{ return Helper.matchFunnelShiftToRotate(*${root}); }]), [{ return Helper.matchFunnelShiftToRotate(*${root}); }]),
(apply [{ Helper.applyFunnelShiftToRotate(*${root}); }]) (apply [{ Helper.applyFunnelShiftToRotate(*${root}); }])
>; >;
def rotate_out_of_range : GICombineRule< def rotate_out_of_range : GICombineRule<
Show All 22 Linesdef and_or_disjoint_mask : GICombineRule<
(apply [{ Helper.applyBuildFnNoErase(*${root}, ${info}); }])>; (apply [{ Helper.applyBuildFnNoErase(*${root}, ${info}); }])>;
def bitfield_extract_from_and : GICombineRule< def bitfield_extract_from_and : GICombineRule<
(defs root:$root, build_fn_matchinfo:$info), (defs root:$root, build_fn_matchinfo:$info),
(match (wip_match_opcode G_AND):$root, (match (wip_match_opcode G_AND):$root,
[{ return Helper.matchBitfieldExtractFromAnd(*${root}, ${info}); }]), [{ return Helper.matchBitfieldExtractFromAnd(*${root}, ${info}); }]),
(apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>; (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
def funnel_shift_combines : GICombineGroup<[funnel_shift_to_rotate]>; def funnel_shift_combines : GICombineGroup<[funnel_shift_from_or_shift,
funnel_shift_to_rotate]>;
def bitfield_extract_from_sext_inreg : GICombineRule< def bitfield_extract_from_sext_inreg : GICombineRule<
(defs root:$root, build_fn_matchinfo:$info), (defs root:$root, build_fn_matchinfo:$info),
(match (wip_match_opcode G_SEXT_INREG):$root, (match (wip_match_opcode G_SEXT_INREG):$root,
[{ return Helper.matchBitfieldExtractFromSExtInReg(*${root}, ${info}); }]), [{ return Helper.matchBitfieldExtractFromSExtInReg(*${root}, ${info}); }]),
(apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>; (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
def bitfield_extract_from_shr : GICombineRule< def bitfield_extract_from_shr : GICombineRule<
▲ Show 20 Lines • Show All 115 Lines • Show Last 20 Lines

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Show First 20 Lines • Show All 3,860 Lines • ▼ Show 20 Lines
} }
void CombinerHelper::applyBuildFnNoErase( void CombinerHelper::applyBuildFnNoErase(
MachineInstr &MI, std::function<void(MachineIRBuilder &)> &MatchInfo) { MachineInstr &MI, std::function<void(MachineIRBuilder &)> &MatchInfo) {
Builder.setInstrAndDebugLoc(MI); Builder.setInstrAndDebugLoc(MI);
MatchInfo(Builder); MatchInfo(Builder);
} }
bool CombinerHelper::matchOrShiftToFunnelShift(MachineInstr &MI,
BuildFnTy &MatchInfo) {
assert(MI.getOpcode() == TargetOpcode::G_OR);
Register Dst = MI.getOperand(0).getReg();
LLT Ty = MRI.getType(Dst);
unsigned BitWidth = Ty.getScalarSizeInBits();
Register ShlSrc, ShlAmt, LShrSrc, LShrAmt;
unsigned FshOpc = 0;
// TODO: Handle vector types.
// Match (or (shl x, amt), (lshr y, sub(bw, amt))).
foadUnsubmitted
Done
ReplyInline Actions

Missing right paren after sub(bw, amt).

foad: Missing right paren after `sub(bw, amt)`.
if (mi_match(Dst, MRI,
// m_GOr() handles the commuted version as well.
m_GOr(m_GShl(m_Reg(ShlSrc), m_Reg(ShlAmt)),
m_GLShr(m_Reg(LShrSrc), m_GSub(m_SpecificICst(BitWidth),
m_Reg(LShrAmt)))))) {
FshOpc = TargetOpcode::G_FSHL;
// Match (or (shl x, sub(bw, amt)), (lshr y, amt)).
foadUnsubmitted
Done
ReplyInline Actions

Missing right paren after sub(bw, amt).

foad: Missing right paren after `sub(bw, amt)`.
} else if (mi_match(
Dst, MRI,
m_GOr(m_GLShr(m_Reg(LShrSrc), m_Reg(LShrAmt)),
m_GShl(m_Reg(ShlSrc), m_GSub(m_SpecificICst(BitWidth),
m_Reg(ShlAmt)))))) {
FshOpc = TargetOpcode::G_FSHR;
} else {
return false;
}
if (ShlAmt != LShrAmt)
return false;
LLT AmtTy = MRI.getType(ShlAmt);
if (!isLegalOrBeforeLegalizer({FshOpc, {Ty, AmtTy}}))
return false;
MatchInfo = [=](MachineIRBuilder &B) {
B.buildInstr(FshOpc, {Dst}, {ShlSrc, LShrSrc, ShlAmt});
};
return true;
}
/// Match an FSHL or FSHR that can be combined to a ROTR or ROTL rotate. /// Match an FSHL or FSHR that can be combined to a ROTR or ROTL rotate.
bool CombinerHelper::matchFunnelShiftToRotate(MachineInstr &MI) { bool CombinerHelper::matchFunnelShiftToRotate(MachineInstr &MI) {
unsigned Opc = MI.getOpcode(); unsigned Opc = MI.getOpcode();
assert(Opc == TargetOpcode::G_FSHL || Opc == TargetOpcode::G_FSHR); assert(Opc == TargetOpcode::G_FSHL || Opc == TargetOpcode::G_FSHR);
Register X = MI.getOperand(1).getReg(); Register X = MI.getOperand(1).getReg();
Register Y = MI.getOperand(2).getReg(); Register Y = MI.getOperand(2).getReg();
if (X != Y) if (X != Y)
return false; return false;
▲ Show 20 Lines • Show All 893 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
---
name: fshl_i32
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK-LABEL: name: fshl_i32
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
; CHECK-NEXT: %b:_(s32) = COPY $vgpr1
; CHECK-NEXT: %amt:_(s32) = COPY $vgpr2
; CHECK-NEXT: %or:_(s32) = G_FSHL %a, %b, %amt(s32)
; CHECK-NEXT: $vgpr3 = COPY %or(s32)
foadUnsubmitted
Done
ReplyInline Actions

Huh? The funnel shift amount should surely be %amt not %bw.

foad: Huh? The funnel shift amount should surely be %amt not %bw.
abinavppAuthorUnsubmitted
Done
ReplyInline Actions

D'oh!

abinavpp: D'oh!
%a:_(s32) = COPY $vgpr0
%b:_(s32) = COPY $vgpr1
%amt:_(s32) = COPY $vgpr2
%bw:_(s32) = G_CONSTANT i32 32
%shl:_(s32) = G_SHL %a:_, %amt:_(s32)
%sub:_(s32) = G_SUB %bw:_, %amt:_
%lshr:_(s32) = G_LSHR %b:_, %sub:_(s32)
%or:_(s32) = G_OR %shl:_, %lshr:_
$vgpr3 = COPY %or
...
---
name: fshl_commute_i32
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK-LABEL: name: fshl_commute_i32
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
; CHECK-NEXT: %b:_(s32) = COPY $vgpr1
; CHECK-NEXT: %amt:_(s32) = COPY $vgpr2
; CHECK-NEXT: %or:_(s32) = G_FSHL %a, %b, %amt(s32)
; CHECK-NEXT: $vgpr3 = COPY %or(s32)
%a:_(s32) = COPY $vgpr0
%b:_(s32) = COPY $vgpr1
%amt:_(s32) = COPY $vgpr2
%bw:_(s32) = G_CONSTANT i32 32
%shl:_(s32) = G_SHL %a:_, %amt:_(s32)
%sub:_(s32) = G_SUB %bw:_, %amt:_
%lshr:_(s32) = G_LSHR %b:_, %sub:_(s32)
%or:_(s32) = G_OR %lshr:_, %shl:_
$vgpr3 = COPY %or
...
---
name: fshr_i32
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK-LABEL: name: fshr_i32
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
; CHECK-NEXT: %b:_(s32) = COPY $vgpr1
; CHECK-NEXT: %amt:_(s32) = COPY $vgpr2
; CHECK-NEXT: %or:_(s32) = G_FSHR %a, %b, %amt(s32)
; CHECK-NEXT: $vgpr3 = COPY %or(s32)
%a:_(s32) = COPY $vgpr0
%b:_(s32) = COPY $vgpr1
%amt:_(s32) = COPY $vgpr2
%bw:_(s32) = G_CONSTANT i32 32
%lshr:_(s32) = G_LSHR %b:_, %amt:_(s32)
%sub:_(s32) = G_SUB %bw:_, %amt:_
%shl:_(s32) = G_SHL %a:_, %sub:_(s32)
%or:_(s32) = G_OR %shl:_, %lshr:_
$vgpr3 = COPY %or
...
---
name: fshl_i32_bad_const
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK-LABEL: name: fshl_i32_bad_const
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
; CHECK-NEXT: %b:_(s32) = COPY $vgpr1
; CHECK-NEXT: %amt:_(s32) = COPY $vgpr2
; CHECK-NEXT: %bw:_(s32) = G_CONSTANT i32 31
; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt(s32)
; CHECK-NEXT: %sub:_(s32) = G_SUB %bw, %amt
; CHECK-NEXT: %lshr:_(s32) = G_LSHR %b, %sub(s32)
; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr
; CHECK-NEXT: $vgpr3 = COPY %or(s32)
%a:_(s32) = COPY $vgpr0
%b:_(s32) = COPY $vgpr1
%amt:_(s32) = COPY $vgpr2
%bw:_(s32) = G_CONSTANT i32 31
%shl:_(s32) = G_SHL %a:_, %amt:_(s32)
%sub:_(s32) = G_SUB %bw:_, %amt:_
%lshr:_(s32) = G_LSHR %b:_, %sub:_(s32)
%or:_(s32) = G_OR %shl:_, %lshr:_
$vgpr3 = COPY %or
...
---
name: fshl_i32_bad_amt_reg
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
; CHECK-LABEL: name: fshl_i32_bad_amt_reg
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
; CHECK-NEXT: %b:_(s32) = COPY $vgpr1
; CHECK-NEXT: %amt:_(s32) = COPY $vgpr2
; CHECK-NEXT: %amt1:_(s32) = COPY $vgpr3
; CHECK-NEXT: %bw:_(s32) = G_CONSTANT i32 32
; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt(s32)
; CHECK-NEXT: %sub:_(s32) = G_SUB %bw, %amt1
; CHECK-NEXT: %lshr:_(s32) = G_LSHR %b, %sub(s32)
; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr
; CHECK-NEXT: $vgpr4 = COPY %or(s32)
%a:_(s32) = COPY $vgpr0
%b:_(s32) = COPY $vgpr1
%amt:_(s32) = COPY $vgpr2
%amt1:_(s32) = COPY $vgpr3
%bw:_(s32) = G_CONSTANT i32 32
%shl:_(s32) = G_SHL %a:_, %amt:_(s32)
%sub:_(s32) = G_SUB %bw:_, %amt1:_
%lshr:_(s32) = G_LSHR %b:_, %sub:_(s32)
%or:_(s32) = G_OR %shl:_, %lshr:_
$vgpr4 = COPY %or
...

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
---
name: rotl_i32
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: rotl_i32
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
; CHECK-NEXT: %or:_(s32) = G_ROTL %a, %amt(s32)
; CHECK-NEXT: $vgpr2 = COPY %or(s32)
%a:_(s32) = COPY $vgpr0
%amt:_(s32) = COPY $vgpr1
%bw:_(s32) = G_CONSTANT i32 32
%shl:_(s32) = G_SHL %a:_, %amt:_(s32)
%sub:_(s32) = G_SUB %bw:_, %amt:_
%lshr:_(s32) = G_LSHR %a:_, %sub:_(s32)
%or:_(s32) = G_OR %shl:_, %lshr:_
$vgpr2 = COPY %or
...
---
name: rotl_commute_i32
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: rotl_commute_i32
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
; CHECK-NEXT: %or:_(s32) = G_ROTL %a, %amt(s32)
; CHECK-NEXT: $vgpr2 = COPY %or(s32)
%a:_(s32) = COPY $vgpr0
%amt:_(s32) = COPY $vgpr1
%bw:_(s32) = G_CONSTANT i32 32
%shl:_(s32) = G_SHL %a:_, %amt:_(s32)
%sub:_(s32) = G_SUB %bw:_, %amt:_
%lshr:_(s32) = G_LSHR %a:_, %sub:_(s32)
%or:_(s32) = G_OR %lshr:_, %shl:_
$vgpr2 = COPY %or
...
---
name: rotr_i32
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: rotr_i32
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
; CHECK-NEXT: %or:_(s32) = G_ROTR %a, %amt(s32)
; CHECK-NEXT: $vgpr2 = COPY %or(s32)
%a:_(s32) = COPY $vgpr0
%amt:_(s32) = COPY $vgpr1
%bw:_(s32) = G_CONSTANT i32 32
%lshr:_(s32) = G_LSHR %a:_, %amt:_(s32)
%sub:_(s32) = G_SUB %bw:_, %amt:_
%shl:_(s32) = G_SHL %a:_, %sub:_(s32)
%or:_(s32) = G_OR %shl:_, %lshr:_
$vgpr2 = COPY %or
...
---
name: rotl_i32_bad_const
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: rotl_i32_bad_const
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
; CHECK-NEXT: %bw:_(s32) = G_CONSTANT i32 31
; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt(s32)
; CHECK-NEXT: %sub:_(s32) = G_SUB %bw, %amt
; CHECK-NEXT: %lshr:_(s32) = G_LSHR %a, %sub(s32)
; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr
; CHECK-NEXT: $vgpr2 = COPY %or(s32)
%a:_(s32) = COPY $vgpr0
%amt:_(s32) = COPY $vgpr1
%bw:_(s32) = G_CONSTANT i32 31
%shl:_(s32) = G_SHL %a:_, %amt:_(s32)
%sub:_(s32) = G_SUB %bw:_, %amt:_
%lshr:_(s32) = G_LSHR %a:_, %sub:_(s32)
%or:_(s32) = G_OR %shl:_, %lshr:_
$vgpr2 = COPY %or
...
---
name: rotl_i32_bad_amt_reg
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK-LABEL: name: rotl_i32_bad_amt_reg
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
; CHECK-NEXT: %amt1:_(s32) = COPY $vgpr2
; CHECK-NEXT: %bw:_(s32) = G_CONSTANT i32 32
; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt(s32)
; CHECK-NEXT: %sub:_(s32) = G_SUB %bw, %amt1
; CHECK-NEXT: %lshr:_(s32) = G_LSHR %a, %sub(s32)
; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr
; CHECK-NEXT: $vgpr3 = COPY %or(s32)
%a:_(s32) = COPY $vgpr0
%amt:_(s32) = COPY $vgpr1
%amt1:_(s32) = COPY $vgpr2
%bw:_(s32) = G_CONSTANT i32 32
%shl:_(s32) = G_SHL %a:_, %amt:_(s32)
%sub:_(s32) = G_SUB %bw:_, %amt1:_
%lshr:_(s32) = G_LSHR %a:_, %sub:_(s32)
%or:_(s32) = G_OR %shl:_, %lshr:_
$vgpr3 = COPY %or
...