[AMDGPU] Fold more inline constant operands by commuting instructions

[foad]

Summary

SIFoldOperands::foldInstOperand folds an immediate value into any number
of inline immediates uses, but it was missing uses that could be inline
if the instruction was commuted. The test diffs mostly show cases where
the immediate value 0 can be folded into more than one commuted v_addc
instruction.

Unfortunately this adds more duplication between
isInlineConstantIfFolded and tryAddToFoldList, but there was already
duplication of the mac/mad handling.

[arsenm]

A dedicated test (maybe MIR) would be nice

[foad]

Add a MIR test.

[foad]

llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir

18 ↗

(On Diff #388498)

It occurs to me now that SIFoldOperands would probably have succeeded here if these were using the e64 form of the instruction. But there are obviously real world cases where it sees the e32 form, otherwise none of the .ll tests would have been improved by this patch.

Is it worth abandoning this patch and pursuing why we are selecting e32 instructions in the first place?

[arsenm]

llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir

18 ↗

(On Diff #388498)

I don't know about abandoning, but it should be looked into. We're mostly consistent in picking the e64 forms upfront

[foad]

This is obsoleted by D114643 which removed isInlineConstantIfFolded. I committed the new test case from this patch in 01c53d7d80eada4db2c63df28bfbeeb0e2f8cad7 to verify that this is no longer required.

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

 // instruction types are replaced during operand folding.
 static bool isInlineConstantIfFolded(const SIInstrInfo *TII,
                                      const MachineInstr &UseMI,
                                      unsigned OpNo,
                                      const MachineOperand &OpToFold) {
   if (TII->isInlineConstant(UseMI, OpNo, OpToFold))
     return true;
 
+  unsigned CommuteIdx0 = TargetInstrInfo::CommuteAnyOperandIndex;
+  unsigned CommuteIdx1 = TargetInstrInfo::CommuteAnyOperandIndex;
+  if (TII->findCommutedOpIndices(UseMI, CommuteIdx0, CommuteIdx1) &&
+      (OpNo == CommuteIdx0 || OpNo == CommuteIdx1)) {
+    unsigned OtherOpNo = OpNo == CommuteIdx0 ? CommuteIdx1 : CommuteIdx0;
+    if (TII->isInlineConstant(UseMI, OtherOpNo, OpToFold))
+      return true;
+  }
+
   unsigned Opc = UseMI.getOpcode();
   unsigned NewOpc = macToMad(Opc);
   if (NewOpc != AMDGPU::INSTRUCTION_LIST_END) {
     // Special case for mac. Since this is replaced with mad when folded into
     // src2, we need to check the legality for the final instruction.
     int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
     if (static_cast<int>(OpNo) == Src2Idx) {
       const MCInstrDesc &MadDesc = TII->get(NewOpc);

llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll

 ; GFX6-LABEL: udiv_i64_oddk_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f176a73
 ; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX6-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX6-NEXT:    s_movk_i32 s4, 0xfee0
 ; GFX6-NEXT:    s_mov_b32 s5, 0x68958c89
-; GFX6-NEXT:    v_mov_b32_e32 v7, 0
+; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GFX6-NEXT:    s_movk_i32 s8, 0x11f
+; GFX6-NEXT:    s_mov_b32 s9, 0x976a7377
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s4
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s5
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s5
-; GFX6-NEXT:    s_mov_b32 s9, 0x976a7377
+; GFX6-NEXT:    v_mul_lo_u32 v5, v0, s5
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s5
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
+; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v4, v0, v5
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
-; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v5
+; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v5
 ; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s4
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s5
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s5
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s4, s0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s5
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
 ; GFX6-NEXT:    s_mov_b32 s5, s1
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v4, s2, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v5, s3, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s3, v0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s8
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s9
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s9
 ; GFX6-NEXT:    v_mov_b32_e32 v5, s8
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s9

 ; GFX9-LABEL: udiv_i64_oddk_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f176a73
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX9-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_movk_i32 s2, 0xfee0
 ; GFX9-NEXT:    s_mov_b32 s3, 0x68958c89
-; GFX9-NEXT:    v_mov_b32_e32 v6, 0
+; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s2
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v1, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s3
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s2
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s3
 ; GFX9-NEXT:    s_movk_i32 s2, 0x11f
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
 ; GFX9-NEXT:    s_mov_b32 s3, 0x976a7377
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v4, v5, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v5, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
+; GFX9-NEXT:    v_mov_b32_e32 v6, s2
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v5, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s2
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s3
-; GFX9-NEXT:    v_mov_b32_e32 v5, s2
+; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s3
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
 ; GFX9-NEXT:    v_sub_u32_e32 v4, s7, v2
 ; GFX9-NEXT:    v_sub_co_u32_e32 v3, vcc, s6, v3
-; GFX9-NEXT:    v_subb_co_u32_e64 v4, s[0:1], v4, v5, vcc
-; GFX9-NEXT:    v_subrev_co_u32_e64 v5, s[0:1], s3, v3
+; GFX9-NEXT:    v_subb_co_u32_e64 v4, s[0:1], v4, v6, vcc
+; GFX9-NEXT:    v_subrev_co_u32_e64 v6, s[0:1], s3, v3
 ; GFX9-NEXT:    v_subbrev_co_u32_e64 v4, s[0:1], 0, v4, s[0:1]
 ; GFX9-NEXT:    s_movk_i32 s3, 0x11e
 ; GFX9-NEXT:    v_cmp_lt_u32_e64 s[0:1], s3, v4
 ; GFX9-NEXT:    s_mov_b32 s6, 0x976a7376
 ; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
-; GFX9-NEXT:    v_cmp_lt_u32_e64 s[0:1], s6, v5
-; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
+; GFX9-NEXT:    v_cmp_lt_u32_e64 s[0:1], s6, v6
+; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
 ; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s2, v4
-; GFX9-NEXT:    v_cndmask_b32_e64 v4, v7, v5, s[0:1]
+; GFX9-NEXT:    v_cndmask_b32_e64 v4, v7, v6, s[0:1]
 ; GFX9-NEXT:    v_mov_b32_e32 v7, s7
 ; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v7, v2, vcc
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s3, v2
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
 ; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v3
 ; GFX9-NEXT:    v_cndmask_b32_e64 v4, 1, 2, s[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v2
 ; GFX9-NEXT:    v_add_co_u32_e64 v4, s[0:1], v0, v4
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v5, s[0:1], 0, v1, s[0:1]
+; GFX9-NEXT:    v_addc_co_u32_e64 v6, s[0:1], 0, v1, s[0:1]
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX9-NEXT:    global_store_dwordx2 v6, v[0:1], s[4:5]
+; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
+; GFX9-NEXT:    global_store_dwordx2 v5, v[0:1], s[4:5]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX90A-LABEL: udiv_i64_oddk_denom:
 ; GFX90A:       ; %bb.0:
 ; GFX90A-NEXT:    v_mov_b32_e32 v0, 0x4f176a73
 ; GFX90A-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX90A-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
 ; GFX90A-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX90A-NEXT:    s_movk_i32 s2, 0xfee0
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_mov_b32 s0, 0x68958c89
 ; GFX90A-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX90A-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX90A-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX90A-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX90A-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX90A-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX90A-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX90A-NEXT:    s_mov_b32 s3, 0x976a7377
+; GFX90A-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v0, s2
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, s0
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX90A-NEXT:    v_mul_lo_u32 v4, v1, s0
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v3, v4
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v0, s0
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, v0, v3
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v0, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v1, v6
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v1, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v4, v0, s2
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, v0, s0
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, s0
 ; GFX90A-NEXT:    v_add_u32_e32 v4, v5, v4
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v0, s0
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, v0, v3
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v0, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v1, v6
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v1, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_mul_lo_u32 v4, s6, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s6, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, s6, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, s7, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v0, s7, v0
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v4, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s7, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v6, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX90A-NEXT:    s_movk_i32 s2, 0x11f
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v0, s2
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, s3
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX90A-NEXT:    v_mul_lo_u32 v4, v1, s3

 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: udiv_v2i64_mixed_pow2k_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x457ff000
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX6-NEXT:    s_movk_i32 s6, 0xf001
-; GFX6-NEXT:    v_mov_b32_e32 v7, 0
 ; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_lshr_b64 s[8:9], s[0:1], 12
 ; GFX6-NEXT:    s_movk_i32 s0, 0xfff
 ; GFX6-NEXT:    v_mul_hi_u32 v2, v0, s6
-; GFX6-NEXT:    v_mul_lo_u32 v3, v1, s6
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s6
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s6
+; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s6
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v4
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
-; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
+; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX6-NEXT:    v_mul_hi_u32 v2, v0, s6
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v1, s6
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s6
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v4
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
 ; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
 ; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v4, s2, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v5, s3, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s3, v0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s0
 ; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 2, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v8, v0, s0
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v0

 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udiv_v2i64_mixed_pow2k_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x457ff000
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_movk_i32 s2, 0xf001
-; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX9-NEXT:    s_movk_i32 s8, 0xfff
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT:    s_movk_i32 s8, 0xfff
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s2
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s2
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s2
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
-; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v3
+; GFX9-NEXT:    v_mul_hi_u32 v5, v0, v3
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v3
+; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v3, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s2
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s2
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s2
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_lshr_b64 s[2:3], s[4:5], 12
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v5, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v6, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GFX9-NEXT:    s_movk_i32 s4, 0xffe
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
-; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
+; GFX9-NEXT:    v_mul_hi_u32 v5, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s8
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s8
-; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s8
+; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s8
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s7
-; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, s6, v4
+; GFX9-NEXT:    v_sub_co_u32_e32 v5, vcc, s6, v5
 ; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v3, v2, vcc
-; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s8, v4
+; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s8, v5
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s4, v3
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v6
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, -1, v3, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, 1, 2, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v0, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s4, v4
-; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
+; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s4, v5
+; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
-; GFX9-NEXT:    v_cndmask_b32_e32 v2, -1, v4, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, -1, v5, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v3, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, v1, v6, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
-; GFX9-NEXT:    global_store_dwordx4 v5, v[0:3], s[0:1]
+; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX90A-LABEL: udiv_v2i64_mixed_pow2k_denom:
 ; GFX90A:       ; %bb.0:
 ; GFX90A-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX90A-NEXT:    v_madak_f32 v0, 0, v0, 0x457ff000
 ; GFX90A-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24

 ; GFX90A-NEXT:    v_mul_hi_u32 v3, v0, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v1, v6
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, v0, s4
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, v1, s4
 ; GFX90A-NEXT:    v_sub_u32_e32 v3, v3, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v0, s4
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, v0, v2
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v0, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, v0, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v1, v6
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, s6, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s6, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v2, s6, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, s7, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v0, s7, v0
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v3, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s7, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v0, vcc, v2, v6, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v2, vcc, v5, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX90A-NEXT:    s_movk_i32 s4, 0xfff
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, v1, s4
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, v0, s4
 ; GFX90A-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v0, s4

 ; GFX6-LABEL: urem_i64_oddk_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f1761f8
 ; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX6-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX6-NEXT:    s_movk_i32 s2, 0xfee0
 ; GFX6-NEXT:    s_mov_b32 s3, 0x689e0837
-; GFX6-NEXT:    v_mov_b32_e32 v7, 0
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s12, 0x9761f7c9
-; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s2
-; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s3
-; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s3
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s8, s4
 ; GFX6-NEXT:    s_movk_i32 s4, 0x11f
+; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s2
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s3
+; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s3
+; GFX6-NEXT:    v_mul_lo_u32 v5, v0, s3
+; GFX6-NEXT:    s_mov_b32 s12, 0x9761f7c9
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s3
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
+; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v4, v0, v5
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
-; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v5
+; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v5
 ; GFX6-NEXT:    s_mov_b32 s9, s5
 ; GFX6-NEXT:    s_movk_i32 s5, 0x11e
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s2
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s3
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s3
 ; GFX6-NEXT:    s_mov_b32 s11, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s10, -1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s3
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v4, s6, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v5, s7, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s7, v0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s4
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s12
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s12
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s12
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1

 ; GFX9-LABEL: urem_i64_oddk_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f1761f8
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX9-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_movk_i32 s2, 0xfee0
 ; GFX9-NEXT:    s_mov_b32 s3, 0x689e0837
-; GFX9-NEXT:    v_mov_b32_e32 v6, 0
+; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX9-NEXT:    s_movk_i32 s8, 0x11f
+; GFX9-NEXT:    s_mov_b32 s9, 0x9761f7c9
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s2
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v1, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s3
-; GFX9-NEXT:    s_mov_b32 s9, 0x9761f7c9
+; GFX9-NEXT:    s_mov_b32 s10, 0x9761f7c8
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    s_mov_b32 s10, 0x9761f7c8
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s2
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s3
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v4, v5, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v5, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v5, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s8
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s9
 ; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s9
 ; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s9
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
 ; GFX9-NEXT:    v_sub_u32_e32 v2, s7, v1
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s8
 ; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, s6, v0
 ; GFX9-NEXT:    v_subb_co_u32_e64 v2, s[0:1], v2, v3, vcc
-; GFX9-NEXT:    v_subrev_co_u32_e64 v4, s[0:1], s9, v0
-; GFX9-NEXT:    v_subbrev_co_u32_e64 v5, s[2:3], 0, v2, s[0:1]
+; GFX9-NEXT:    v_subrev_co_u32_e64 v5, s[0:1], s9, v0
+; GFX9-NEXT:    v_subbrev_co_u32_e64 v6, s[2:3], 0, v2, s[0:1]
 ; GFX9-NEXT:    s_movk_i32 s6, 0x11e
-; GFX9-NEXT:    v_cmp_lt_u32_e64 s[2:3], s6, v5
+; GFX9-NEXT:    v_cmp_lt_u32_e64 s[2:3], s6, v6
 ; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
-; GFX9-NEXT:    v_cmp_lt_u32_e64 s[2:3], s10, v4
+; GFX9-NEXT:    v_cmp_lt_u32_e64 s[2:3], s10, v5
 ; GFX9-NEXT:    v_subb_co_u32_e64 v2, s[0:1], v2, v3, s[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
-; GFX9-NEXT:    v_cmp_eq_u32_e64 s[2:3], s8, v5
-; GFX9-NEXT:    v_subrev_co_u32_e64 v3, s[0:1], s9, v4
+; GFX9-NEXT:    v_cmp_eq_u32_e64 s[2:3], s8, v6
+; GFX9-NEXT:    v_subrev_co_u32_e64 v3, s[0:1], s9, v5
 ; GFX9-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[2:3]
 ; GFX9-NEXT:    v_subbrev_co_u32_e64 v2, s[0:1], 0, v2, s[0:1]
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v7
-; GFX9-NEXT:    v_cndmask_b32_e64 v3, v4, v3, s[0:1]
-; GFX9-NEXT:    v_mov_b32_e32 v4, s7
-; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v4, v1, vcc
+; GFX9-NEXT:    v_cndmask_b32_e64 v3, v5, v3, s[0:1]
+; GFX9-NEXT:    v_mov_b32_e32 v5, s7
+; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v5, v1, vcc
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v1
-; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s10, v0
-; GFX9-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s10, v0
+; GFX9-NEXT:    v_cndmask_b32_e64 v2, v6, v2, s[0:1]
+; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v1
-; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
+; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX9-NEXT:    global_store_dwordx2 v6, v[0:1], s[4:5]
+; GFX9-NEXT:    global_store_dwordx2 v4, v[0:1], s[4:5]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX90A-LABEL: urem_i64_oddk_denom:
 ; GFX90A:       ; %bb.0:
 ; GFX90A-NEXT:    v_mov_b32_e32 v0, 0x4f1761f8
 ; GFX90A-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX90A-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
 ; GFX90A-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX90A-NEXT:    s_movk_i32 s2, 0xfee0
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_mov_b32 s0, 0x689e0837
 ; GFX90A-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX90A-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX90A-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX90A-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX90A-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX90A-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX90A-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX90A-NEXT:    s_movk_i32 s8, 0x11f
+; GFX90A-NEXT:    s_mov_b32 s9, 0x9761f7c9
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v0, s2
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, s0
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX90A-NEXT:    v_mul_lo_u32 v4, v1, s0
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v3, v4
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v0, s0
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, v0, v3
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v0, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v1, v6
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v1, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v4, v0, s2
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, v0, s0
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, s0
 ; GFX90A-NEXT:    v_add_u32_e32 v4, v5, v4
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v0, s0
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, v0, v3
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v0, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v1, v6
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v1, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_mul_lo_u32 v4, s6, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s6, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, s6, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, s7, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v0, s7, v0
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v4, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s7, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v6, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
-; GFX90A-NEXT:    s_mov_b32 s9, 0x9761f7c9
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v0, s8
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, s9
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX90A-NEXT:    v_mul_lo_u32 v1, v1, s9
 ; GFX90A-NEXT:    v_add_u32_e32 v1, v3, v1
 ; GFX90A-NEXT:    v_mul_lo_u32 v0, v0, s9
 ; GFX90A-NEXT:    v_sub_u32_e32 v3, s7, v1

 ; GFX90A-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v1
 ; GFX90A-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; GFX90A-NEXT:    v_cmp_lt_u32_e32 vcc, s10, v0
 ; GFX90A-NEXT:    v_cndmask_b32_e64 v3, v6, v3, s[0:1]
 ; GFX90A-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
 ; GFX90A-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v1
 ; GFX90A-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
 ; GFX90A-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GFX90A-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX90A-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
 ; GFX90A-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
 ; GFX90A-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
 ; GFX90A-NEXT:    s_endpgm
   %r = urem i64 %x, 1235195393993
   store i64 %r, i64 addrspace(1)* %out
   ret void
 }

 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: sdiv_i64_oddk_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX6-NEXT:    s_mov_b32 s5, 0xffed2705
-; GFX6-NEXT:    v_mov_b32_e32 v7, 0
 ; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
 ; GFX6-NEXT:    s_add_u32 s2, s2, s8
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s5
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s5
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s5
 ; GFX6-NEXT:    s_mov_b32 s9, s8
 ; GFX6-NEXT:    s_addc_u32 s3, s3, s8
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
-; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
 ; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GFX6-NEXT:    s_xor_b64 s[2:3], s[2:3], s[8:9]
 ; GFX6-NEXT:    s_mov_b32 s4, s0
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s5
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s5
 ; GFX6-NEXT:    s_mov_b32 s0, 0x12d8fb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s5
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v3
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v5, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v4, s2, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v5, s3, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s3, v0
 ; GFX6-NEXT:    s_mov_b32 s5, s1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s0
 ; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 2, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v8, v0, s0
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v0

 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: sdiv_i64_oddk_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_mov_b32 s4, 0xffed2705
-; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s4
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s4
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s4
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s4
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s4
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s4
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
 ; GFX9-NEXT:    s_add_u32 s2, s2, s4
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
-; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v4
+; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v7, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v5, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    s_mov_b32 s5, s4
 ; GFX9-NEXT:    s_addc_u32 s3, s3, s4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    s_xor_b64 s[2:3], s[2:3], s[4:5]
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s2, v1
-; GFX9-NEXT:    v_mul_hi_u32 v6, s3, v1
+; GFX9-NEXT:    v_mul_hi_u32 v5, s3, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s3, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s3, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s3, v0
 ; GFX9-NEXT:    s_mov_b32 s5, 0x12d8fb
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s5
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s5
-; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s5
+; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s5
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s3
-; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, s2, v4
+; GFX9-NEXT:    v_sub_co_u32_e32 v5, vcc, s2, v5
 ; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v3, v2, vcc
-; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s5, v4
+; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s5, v5
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
 ; GFX9-NEXT:    s_mov_b32 s2, 0x12d8fa
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s2, v3
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v6
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, -1, v3, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, 1, 2, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v0, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s2, v4
-; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
+; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s2, v5
+; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
-; GFX9-NEXT:    v_cndmask_b32_e32 v2, -1, v4, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, -1, v5, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
 ; GFX9-NEXT:    v_xor_b32_e32 v1, s4, v1
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s4
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s4, v0
 ; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
-; GFX9-NEXT:    global_store_dwordx2 v5, v[0:1], s[0:1]
+; GFX9-NEXT:    global_store_dwordx2 v4, v[0:1], s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX90A-LABEL: sdiv_i64_oddk_denom:
 ; GFX90A:       ; %bb.0:
 ; GFX90A-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX90A-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
 ; GFX90A-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX90A-NEXT:    s_mov_b32 s4, 0xffed2705
-; GFX90A-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX90A-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX90A-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX90A-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX90A-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX90A-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX90A-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX90A-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX90A-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, s4
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, s4
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX90A-NEXT:    v_sub_u32_e32 v3, v3, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v0, s4
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, v0, v3
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v0, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v1, v6
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v1, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, s4
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, s4
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX90A-NEXT:    v_sub_u32_e32 v3, v3, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, v0, s4
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, v1, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v7, v1, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v9, v0, v3
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, v0, v5
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v0, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v9
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v1, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v6, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    s_ashr_i32 s4, s3, 31
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX90A-NEXT:    s_add_u32 s2, s2, s4
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
 ; GFX90A-NEXT:    s_mov_b32 s5, s4
 ; GFX90A-NEXT:    s_addc_u32 s3, s3, s4
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
 ; GFX90A-NEXT:    s_xor_b64 s[2:3], s[2:3], s[4:5]
 ; GFX90A-NEXT:    v_mul_lo_u32 v4, s2, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s2, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, s2, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, s3, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v0, s3, v0
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v4, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s3, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v6, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v1, s3, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    s_mov_b32 s5, 0x12d8fb
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, s5
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, s5
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX90A-NEXT:    v_mul_lo_u32 v4, v0, s5

 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
 ; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GFX6-NEXT:    s_xor_b64 s[2:3], s[2:3], s[12:13]
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GFX6-NEXT:    v_mov_b32_e32 v4, 0
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
-; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, s5, v0
 ; GFX6-NEXT:    s_mov_b32 s5, s1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v0
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v3
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v3
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
-; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v6, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v5, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
-; GFX6-NEXT:    v_mul_hi_u32 v5, s2, v1
-; GFX6-NEXT:    v_mul_hi_u32 v6, s3, v1
+; GFX6-NEXT:    v_mul_hi_u32 v4, s2, v1
+; GFX6-NEXT:    v_mul_hi_u32 v5, s3, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s3, v0
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s3, v0
 ; GFX6-NEXT:    s_mov_b32 s4, s0
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v6, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s10, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s10, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v4, s11, v0
 ; GFX6-NEXT:    v_mov_b32_e32 v5, s11
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, s10, v0

 ; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: sdiv_i64_pow2_shl_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x34
 ; GFX9-NEXT:    s_mov_b64 s[2:3], 0x1000
-; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_lshl_b64 s[4:5], s[2:3], s4
 ; GFX9-NEXT:    s_ashr_i32 s2, s5, 31
 ; GFX9-NEXT:    s_add_u32 s4, s4, s2
 ; GFX9-NEXT:    s_mov_b32 s3, s2
 ; GFX9-NEXT:    s_addc_u32 s5, s5, s2
 ; GFX9-NEXT:    s_xor_b64 s[8:9], s[4:5], s[2:3]
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
 ; GFX9-NEXT:    s_sub_u32 s10, 0, s8
 ; GFX9-NEXT:    s_subb_u32 s4, 0, s9
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s10, v0
-; GFX9-NEXT:    v_mul_lo_u32 v6, s4, v0
-; GFX9-NEXT:    v_mul_lo_u32 v5, s10, v0
-; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
-; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
-; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v5
-; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
-; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s10, v0
+; GFX9-NEXT:    v_mul_lo_u32 v2, s10, v1
+; GFX9-NEXT:    v_mul_hi_u32 v3, s10, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v5, s4, v0
-; GFX9-NEXT:    v_mul_lo_u32 v6, s10, v0
+; GFX9-NEXT:    v_mul_lo_u32 v4, s10, v0
+; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v4
+; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, s10, v1
+; GFX9-NEXT:    v_mul_hi_u32 v3, s10, v0
+; GFX9-NEXT:    v_mul_lo_u32 v4, s4, v0
+; GFX9-NEXT:    v_mul_lo_u32 v5, s10, v0
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
-; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
-; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v6
-; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v6
-; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
-; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v5
+; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v5
+; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
+; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v5, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s10, s7, 31
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX9-NEXT:    s_add_u32 s0, s6, s10
-; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    s_mov_b32 s11, s10
 ; GFX9-NEXT:    s_addc_u32 s1, s7, s10
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
-; GFX9-NEXT:    v_mul_lo_u32 v3, s6, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v0
-; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
-; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
+; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
+; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
+; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
+; GFX9-NEXT:    v_mul_hi_u32 v5, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v2, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, s8, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s8, v0
-; GFX9-NEXT:    v_mul_lo_u32 v5, s9, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v6, s9
-; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
-; GFX9-NEXT:    v_mul_lo_u32 v4, s8, v0
-; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
-; GFX9-NEXT:    v_sub_u32_e32 v5, s7, v3
-; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, s6, v4
-; GFX9-NEXT:    v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc
-; GFX9-NEXT:    v_subrev_co_u32_e64 v6, s[0:1], s8, v4
-; GFX9-NEXT:    v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1]
-; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v5
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, s8, v1
+; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
+; GFX9-NEXT:    v_mul_lo_u32 v4, s9, v0
+; GFX9-NEXT:    v_mov_b32_e32 v5, 0
+; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT:    v_mul_lo_u32 v3, s8, v0
+; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT:    v_sub_u32_e32 v4, s7, v2
+; GFX9-NEXT:    v_sub_co_u32_e32 v3, vcc, s6, v3
+; GFX9-NEXT:    v_subb_co_u32_e64 v4, s[0:1], v4, v6, vcc
+; GFX9-NEXT:    v_subrev_co_u32_e64 v6, s[0:1], s8, v3
+; GFX9-NEXT:    v_subbrev_co_u32_e64 v4, s[0:1], 0, v4, s[0:1]
+; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v4
 ; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
 ; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v6
 ; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
-; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v5
-; GFX9-NEXT:    v_cndmask_b32_e64 v5, v7, v6, s[0:1]
+; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v4
+; GFX9-NEXT:    v_cndmask_b32_e64 v4, v7, v6, s[0:1]
 ; GFX9-NEXT:    v_mov_b32_e32 v7, s7
-; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v7, v3, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
-; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
+; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v7, v2, vcc
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
+; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
 ; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v4
-; GFX9-NEXT:    v_cndmask_b32_e64 v5, 1, 2, s[0:1]
-; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v3
-; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], v0, v5
-; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v4, vcc
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
+; GFX9-NEXT:    v_cndmask_b32_e64 v4, 1, 2, s[0:1]
+; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v2
+; GFX9-NEXT:    v_add_co_u32_e64 v4, s[0:1], v0, v4
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v6, s[0:1], 0, v1, s[0:1]
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
-; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
 ; GFX9-NEXT:    s_xor_b64 s[0:1], s[10:11], s[2:3]
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v0, s0, v0
 ; GFX9-NEXT:    v_xor_b32_e32 v1, s1, v1
-; GFX9-NEXT:    v_mov_b32_e32 v3, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s0, v0
-; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
+; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
+; GFX9-NEXT:    global_store_dwordx2 v5, v[0:1], s[4:5]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX90A-LABEL: sdiv_i64_pow2_shl_denom:
 ; GFX90A:       ; %bb.0:
 ; GFX90A-NEXT:    s_load_dword s4, s[0:1], 0x34
 ; GFX90A-NEXT:    s_mov_b64 s[2:3], 0x1000
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)

 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v1, v6
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v1, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, s0, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, s0, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX90A-NEXT:    v_mul_lo_u32 v4, s1, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v3, v4
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, s0, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, v1, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v7, v1, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v9, v0, v3
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, v0, v5
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v0, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v9
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v1, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v6, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX90A-NEXT:    s_add_u32 s0, s6, s10
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
 ; GFX90A-NEXT:    s_addc_u32 s1, s7, s10
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
 ; GFX90A-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
 ; GFX90A-NEXT:    v_mul_lo_u32 v4, s6, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s6, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, s6, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, s7, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v0, s7, v0
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v4, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s7, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v6, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, s8, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, s8, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX90A-NEXT:    v_mul_lo_u32 v4, s9, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v3, v4

 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
 ; GFX6-NEXT:    s_ashr_i32 s10, s3, 31
 ; GFX6-NEXT:    s_add_u32 s0, s2, s10
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
-; GFX6-NEXT:    v_mov_b32_e32 v4, 0
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s6
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s6
 ; GFX6-NEXT:    s_mov_b32 s11, s10
 ; GFX6-NEXT:    s_addc_u32 s1, s3, s10
 ; GFX6-NEXT:    s_xor_b64 s[0:1], s[0:1], s[10:11]
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s6
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
-; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v3
+; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v3
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
-; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v6, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v5, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v0
-; GFX6-NEXT:    v_mul_hi_u32 v5, s0, v1
-; GFX6-NEXT:    v_mul_hi_u32 v6, s1, v1
+; GFX6-NEXT:    v_mul_hi_u32 v4, s0, v1
+; GFX6-NEXT:    v_mul_hi_u32 v5, s1, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s1, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s1, v0
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, s1, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
 ; GFX6-NEXT:    s_movk_i32 s2, 0xfff
 ; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v6, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s2
 ; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s2
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 2, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v8, v0, s2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v0

 ;
 ; GFX9-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x457ff000
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0, v1
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_movk_i32 s8, 0xf001
-; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s2, s5, 31
 ; GFX9-NEXT:    s_lshr_b32 s2, s2, 20
-; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s8
-; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s8
-; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s8
+; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s8
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s8
+; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s8
 ; GFX9-NEXT:    s_add_u32 s2, s4, s2
 ; GFX9-NEXT:    s_addc_u32 s3, s5, 0
-; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
+; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v5, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v6, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v5
-; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v4
+; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GFX9-NEXT:    s_ashr_i64 s[2:3], s[2:3], 12
 ; GFX9-NEXT:    s_ashr_i32 s4, s7, 31
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s8
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s8
-; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s8
+; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s8
 ; GFX9-NEXT:    s_add_u32 s6, s6, s4
 ; GFX9-NEXT:    s_mov_b32 s5, s4
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
-; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v5
-; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
+; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v4
+; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v6, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v5, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v5, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    s_addc_u32 s7, s7, s4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    s_xor_b64 s[6:7], s[6:7], s[4:5]
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
-; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
-; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
+; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
+; GFX9-NEXT:    v_mul_hi_u32 v5, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
 ; GFX9-NEXT:    s_movk_i32 s5, 0xfff
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v5
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s5
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s5
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s5
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s7
 ; GFX9-NEXT:    v_sub_co_u32_e32 v5, vcc, s6, v5
 ; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v3, v2, vcc
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s5, v5
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
 ; GFX9-NEXT:    s_movk_i32 s5, 0xffe
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s5, v3

 ; GFX90A-NEXT:    v_mul_hi_u32 v3, v0, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v1, v6
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, v1, s4
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, v0, s4
 ; GFX90A-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX90A-NEXT:    v_sub_u32_e32 v2, v2, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, v0, s4
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, v1, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v7, v1, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v9, v0, v2
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, v0, v5
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v0, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v9
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, v1, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v6, vcc
 ; GFX90A-NEXT:    s_addc_u32 s1, s5, 0
-; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX90A-NEXT:    s_ashr_i64 s[0:1], s[0:1], 12
 ; GFX90A-NEXT:    v_add_co_u32_e32 v2, vcc, v5, v2
 ; GFX90A-NEXT:    s_ashr_i32 s4, s7, 31
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    s_add_u32 s6, s6, s4
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX90A-NEXT:    s_mov_b32 s5, s4
 ; GFX90A-NEXT:    s_addc_u32 s7, s7, s4
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX90A-NEXT:    s_xor_b64 s[6:7], s[6:7], s[4:5]
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, s6, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s6, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v2, s6, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, s7, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v0, s7, v0
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v3, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s7, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v0, vcc, v2, v6, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v2, vcc, v5, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX90A-NEXT:    s_movk_i32 s5, 0xfff
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, v1, s5
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, v0, s5
 ; GFX90A-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v0, s5

 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
 ; GFX6-NEXT:    v_mul_f32_e32 v0, s19, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, s20, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, s21, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v0
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_ashr_i32 s14, s1, 31
 ; GFX6-NEXT:    s_add_u32 s0, s0, s14
-; GFX6-NEXT:    v_mul_lo_u32 v0, s6, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v2
-; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v2
-; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
+; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v0
 ; GFX6-NEXT:    s_mov_b32 s15, s14
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v0, v4
-; GFX6-NEXT:    v_mul_lo_u32 v0, v2, v3
-; GFX6-NEXT:    v_mul_hi_u32 v4, v2, v5
-; GFX6-NEXT:    v_mul_hi_u32 v6, v2, v3
-; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v3
-; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v4, v0
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v4, v0, v5
+; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v6, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v5
 ; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v5
 ; GFX6-NEXT:    s_addc_u32 s1, s1, s14
 ; GFX6-NEXT:    s_xor_b64 s[16:17], s[0:1], s[14:15]
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v5, vcc
-; GFX6-NEXT:    v_mov_b32_e32 v0, 0
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v0, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, s6, v1
-; GFX6-NEXT:    v_mul_hi_u32 v4, s6, v2
-; GFX6-NEXT:    v_mul_lo_u32 v5, s7, v2
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
 ; GFX6-NEXT:    s_xor_b64 s[14:15], s[14:15], s[12:13]
 ; GFX6-NEXT:    s_ashr_i32 s12, s9, 31
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_mul_lo_u32 v4, s6, v2
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v3
-; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v4
-; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v4
-; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_mul_lo_u32 v3, s6, v0
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v3
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v5, v0, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, s16, v1
-; GFX6-NEXT:    v_mul_hi_u32 v4, s16, v2
-; GFX6-NEXT:    v_mul_hi_u32 v5, s16, v1
-; GFX6-NEXT:    v_mul_hi_u32 v6, s17, v1
+; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v2, s16, v1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s16, v0
+; GFX6-NEXT:    v_mul_hi_u32 v4, s16, v1
+; GFX6-NEXT:    v_mul_hi_u32 v5, s17, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s17, v1
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s17, v2
-; GFX6-NEXT:    v_mul_hi_u32 v2, s17, v2
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, s17, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s17, v0
 ; GFX6-NEXT:    s_add_u32 s8, s8, s12
 ; GFX6-NEXT:    s_mov_b32 s13, s12
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v4, v2, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v0, vcc
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, s10, v2
-; GFX6-NEXT:    v_mul_hi_u32 v4, s10, v1
-; GFX6-NEXT:    v_mul_lo_u32 v5, s11, v1
-; GFX6-NEXT:    v_mov_b32_e32 v6, s11
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v2, s10, v1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s10, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, s11, v0
+; GFX6-NEXT:    v_mov_b32_e32 v5, s11
 ; GFX6-NEXT:    s_addc_u32 s9, s9, s12
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_mul_lo_u32 v4, s10, v1
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s17, v3
-; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s16, v4
-; GFX6-NEXT:    v_subb_u32_e64 v5, s[0:1], v5, v6, vcc
-; GFX6-NEXT:    v_subrev_i32_e64 v6, s[0:1], s10, v4
-; GFX6-NEXT:    v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v5
-; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v6
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_mul_lo_u32 v3, s10, v0
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s17, v2
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s16, v3
+; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
+; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s10, v3
+; GFX6-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v5
-; GFX6-NEXT:    v_cndmask_b32_e64 v5, v7, v6, s[0:1]
-; GFX6-NEXT:    v_add_i32_e64 v6, s[0:1], 2, v1
-; GFX6-NEXT:    v_addc_u32_e64 v7, s[0:1], 0, v2, s[0:1]
-; GFX6-NEXT:    v_add_i32_e64 v8, s[0:1], 1, v1
-; GFX6-NEXT:    v_addc_u32_e64 v9, s[0:1], 0, v2, s[0:1]
-; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v5
+; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v4
+; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
+; GFX6-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
+; GFX6-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
+; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
+; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
+; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
 ; GFX6-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]
-; GFX6-NEXT:    v_cndmask_b32_e64 v5, v9, v7, s[0:1]
-; GFX6-NEXT:    v_mov_b32_e32 v7, s17
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v9, s8
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v10, s9
-; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v7, v3, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
-; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v4
-; GFX6-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v3
-; GFX6-NEXT:    v_mac_f32_e32 v9, s18, v10
-; GFX6-NEXT:    v_cndmask_b32_e32 v3, v7, v4, vcc
-; GFX6-NEXT:    v_rcp_f32_e32 v4, v9
-; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
-; GFX6-NEXT:    v_cndmask_b32_e64 v3, v8, v6, s[0:1]
-; GFX6-NEXT:    v_mul_f32_e32 v4, s19, v4
-; GFX6-NEXT:    v_mul_f32_e32 v5, s20, v4
-; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX6-NEXT:    v_mac_f32_e32 v4, s21, v5
+; GFX6-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
+; GFX6-NEXT:    v_mov_b32_e32 v6, s17
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v8, s8
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v9, s9
+; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v2
+; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
+; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v2
+; GFX6-NEXT:    v_mac_f32_e32 v8, s18, v9
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
+; GFX6-NEXT:    v_rcp_f32_e32 v3, v8
+; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX6-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
+; GFX6-NEXT:    v_mul_f32_e32 v3, s19, v3
+; GFX6-NEXT:    v_mul_f32_e32 v4, s20, v3
+; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
+; GFX6-NEXT:    v_mac_f32_e32 v3, s21, v4
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GFX6-NEXT:    s_sub_u32 s0, 0, s8
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v4
-; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v5
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v2, s0, v3
+; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
 ; GFX6-NEXT:    s_subb_u32 s1, 0, s9
-; GFX6-NEXT:    v_mul_lo_u32 v7, s1, v4
+; GFX6-NEXT:    v_mul_lo_u32 v6, s1, v3
 ; GFX6-NEXT:    s_ashr_i32 s10, s3, 31
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v4
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
-; GFX6-NEXT:    v_mul_lo_u32 v7, v4, v3
-; GFX6-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GFX6-NEXT:    v_mul_hi_u32 v9, v4, v3
-; GFX6-NEXT:    v_mul_hi_u32 v10, v5, v3
-; GFX6-NEXT:    v_mul_lo_u32 v3, v5, v3
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v9, v5, v6
-; GFX6-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v3
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
+; GFX6-NEXT:    v_mul_lo_u32 v6, v3, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v3, v5
+; GFX6-NEXT:    v_mul_hi_u32 v8, v3, v2
+; GFX6-NEXT:    v_mul_hi_u32 v9, v4, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, v4, v2
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v8, v4, v5
+; GFX6-NEXT:    v_mul_hi_u32 v5, v4, v5
 ; GFX6-NEXT:    s_mov_b32 s11, s10
-; GFX6-NEXT:    v_xor_b32_e32 v1, s14, v1
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v8, v6, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v10, v0, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v5, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v6, s0, v3
-; GFX6-NEXT:    v_mul_lo_u32 v7, s1, v3
-; GFX6-NEXT:    v_xor_b32_e32 v2, s15, v2
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v3
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GFX6-NEXT:    v_mul_lo_u32 v9, v3, v5
-; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v6
-; GFX6-NEXT:    v_mul_hi_u32 v11, v3, v5
-; GFX6-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GFX6-NEXT:    v_mul_lo_u32 v6, v4, v6
-; GFX6-NEXT:    v_mul_hi_u32 v7, v4, v5
-; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, v4, v5
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
-; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v10, v8, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v7, v0, vcc
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
+; GFX6-NEXT:    v_xor_b32_e32 v0, s14, v0
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v9, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v5, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, s0, v3
+; GFX6-NEXT:    v_mul_hi_u32 v5, s0, v2
+; GFX6-NEXT:    v_mul_lo_u32 v6, s1, v2
+; GFX6-NEXT:    v_xor_b32_e32 v1, s15, v1
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v2
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GFX6-NEXT:    v_mul_lo_u32 v8, v2, v4
+; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v5
+; GFX6-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GFX6-NEXT:    v_mul_hi_u32 v7, v3, v5
+; GFX6-NEXT:    v_mul_lo_u32 v5, v3, v5
+; GFX6-NEXT:    v_mul_hi_u32 v6, v3, v4
+; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, v3, v4
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v9, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GFX6-NEXT:    s_add_u32 s0, s2, s10
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GFX6-NEXT:    s_addc_u32 s1, s3, s10
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
 ; GFX6-NEXT:    s_xor_b64 s[2:3], s[0:1], s[10:11]
-; GFX6-NEXT:    v_mul_lo_u32 v5, s2, v4
-; GFX6-NEXT:    v_mul_hi_u32 v6, s2, v3
-; GFX6-NEXT:    v_mul_hi_u32 v8, s2, v4
-; GFX6-NEXT:    v_mul_hi_u32 v9, s3, v4
-; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v4
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v8, s3, v3
-; GFX6-NEXT:    v_mul_hi_u32 v3, s3, v3
-; GFX6-NEXT:    v_mov_b32_e32 v7, s15
-; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v3, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v9, v0, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v0, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s8, v4
-; GFX6-NEXT:    v_mul_hi_u32 v6, s8, v3
-; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s14, v1
-; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v2, v7, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s9, v3
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT:    v_mul_lo_u32 v4, s2, v3
+; GFX6-NEXT:    v_mul_hi_u32 v5, s2, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, s2, v3
+; GFX6-NEXT:    v_mul_hi_u32 v8, s3, v3
+; GFX6-NEXT:    v_mul_lo_u32 v3, s3, v3
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v7, s3, v2
+; GFX6-NEXT:    v_mul_hi_u32 v2, s3, v2
+; GFX6-NEXT:    v_mov_b32_e32 v6, s15
+; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v2, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v8, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, s8, v3
+; GFX6-NEXT:    v_mul_hi_u32 v5, s8, v2
+; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s14, v0
+; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v6, s9, v2
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT:    v_mul_lo_u32 v5, s8, v2
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, s3, v4
 ; GFX6-NEXT:    v_mov_b32_e32 v7, s9
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GFX6-NEXT:    v_mul_lo_u32 v5, s8, v3
-; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, s3, v2
 ; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s2, v5
 ; GFX6-NEXT:    v_subb_u32_e64 v6, s[0:1], v6, v7, vcc
 ; GFX6-NEXT:    v_subrev_i32_e64 v7, s[0:1], s8, v5
 ; GFX6-NEXT:    v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]
 ; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v6
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[0:1]
 ; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v7
 ; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v6
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[0:1]
-; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 2, v3
-; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v4, s[0:1]
-; GFX6-NEXT:    v_add_i32_e64 v9, s[0:1], 1, v3
-; GFX6-NEXT:    v_addc_u32_e64 v10, s[0:1], 0, v4, s[0:1]
+; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 2, v2
+; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v3, s[0:1]
+; GFX6-NEXT:    v_add_i32_e64 v9, s[0:1], 1, v2
+; GFX6-NEXT:    v_addc_u32_e64 v10, s[0:1], 0, v3, s[0:1]
 ; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, v10, v8, s[0:1]
 ; GFX6-NEXT:    v_mov_b32_e32 v8, s3
-; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v8, v2, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
+; GFX6-NEXT:    v_subb_u32_e32 v4, vcc, v8, v4, vcc
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v5
 ; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v2
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v8, v5, vcc
-; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v4
+; GFX6-NEXT:    v_cndmask_b32_e32 v4, v8, v5, vcc
+; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v4, v9, v7, s[0:1]
-; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX6-NEXT:    s_xor_b64 s[0:1], s[10:11], s[12:13]
-; GFX6-NEXT:    v_xor_b32_e32 v3, s0, v3
-; GFX6-NEXT:    v_xor_b32_e32 v4, s1, v2
-; GFX6-NEXT:    v_mov_b32_e32 v5, s1
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s0, v3
-; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v4, v5, vcc
+; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX6-NEXT:    v_xor_b32_e32 v2, s0, v2
+; GFX6-NEXT:    v_xor_b32_e32 v3, s1, v3
+; GFX6-NEXT:    v_mov_b32_e32 v4, s1
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s0, v2
+; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
 ; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: sdiv_v2i64_pow2_shl_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x44
 ; GFX9-NEXT:    s_mov_b64 s[2:3], 0x1000
 ; GFX9-NEXT:    s_mov_b32 s16, 0x4f800000

 ; GFX9-NEXT:    v_mac_f32_e32 v0, s16, v1
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; GFX9-NEXT:    v_mul_f32_e32 v0, s17, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, s18, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, s19, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v0
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s14, s5, 31
 ; GFX9-NEXT:    s_mov_b32 s15, s14
-; GFX9-NEXT:    v_mul_lo_u32 v0, s2, v1
-; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v2
-; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v2
-; GFX9-NEXT:    v_mul_lo_u32 v4, s2, v2
-; GFX9-NEXT:    v_add_u32_e32 v0, v3, v0
-; GFX9-NEXT:    v_add_u32_e32 v5, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v4
-; GFX9-NEXT:    v_mul_lo_u32 v6, v2, v5
-; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v5
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v5
-; GFX9-NEXT:    v_mov_b32_e32 v0, 0
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v1
+; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v0
+; GFX9-NEXT:    v_mul_lo_u32 v4, s2, v0
+; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v2
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v0, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, s2, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s2, v2
-; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v2
-; GFX9-NEXT:    v_mul_lo_u32 v6, s2, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v1
+; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GFX9-NEXT:    v_mul_lo_u32 v4, s3, v0
+; GFX9-NEXT:    v_mul_lo_u32 v5, s2, v0
 ; GFX9-NEXT:    s_add_u32 s2, s4, s14
-; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
-; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
-; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v3
-; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v6
-; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v6
-; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
-; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v5
+; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v5
+; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
+; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v5, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v0, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    s_addc_u32 s3, s5, s14
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], s[2:3], s[14:15]
-; GFX9-NEXT:    v_mul_lo_u32 v3, s4, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s4, v2
-; GFX9-NEXT:    v_mul_hi_u32 v5, s4, v1
-; GFX9-NEXT:    v_mul_hi_u32 v6, s5, v1
+; GFX9-NEXT:    v_mul_lo_u32 v2, s4, v1
+; GFX9-NEXT:    v_mul_hi_u32 v3, s4, v0
+; GFX9-NEXT:    v_mul_hi_u32 v4, s4, v1
+; GFX9-NEXT:    v_mul_hi_u32 v5, s5, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s5, v1
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v5, s5, v2
-; GFX9-NEXT:    v_mul_hi_u32 v2, s5, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v4, s5, v0
+; GFX9-NEXT:    v_mul_hi_u32 v0, s5, v0
+; GFX9-NEXT:    v_mov_b32_e32 v6, s11
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v4, v2, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v0, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v2, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v3, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v0, v1
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s10, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v5, s11, v1
-; GFX9-NEXT:    v_mov_b32_e32 v6, s11
+; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s10, v1
 ; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
 ; GFX9-NEXT:    v_sub_u32_e32 v5, s5, v3
 ; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, s4, v4
 ; GFX9-NEXT:    v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc
 ; GFX9-NEXT:    v_subrev_co_u32_e64 v6, s[0:1], s10, v4
 ; GFX9-NEXT:    v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1]

 ; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v4, v6
 ; GFX9-NEXT:    v_mul_hi_u32 v6, v4, v6
 ; GFX9-NEXT:    v_xor_b32_e32 v1, s0, v1
 ; GFX9-NEXT:    v_xor_b32_e32 v2, s1, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v9
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v8, v6, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v0, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v10, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v6, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v5, s10, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v6, s10, v3
 ; GFX9-NEXT:    v_mul_lo_u32 v7, s11, v3
 ; GFX9-NEXT:    v_mul_lo_u32 v8, s10, v3
 ; GFX9-NEXT:    s_ashr_i32 s10, s7, 31
 ; GFX9-NEXT:    v_add_u32_e32 v5, v6, v5
 ; GFX9-NEXT:    v_add_u32_e32 v5, v5, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v3, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v3, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v7, v4, v8
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v4, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v6, v4, v5
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
 ; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v4, v5
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v7, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v6, v0, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
 ; GFX9-NEXT:    s_add_u32 s6, s6, s10
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
 ; GFX9-NEXT:    s_mov_b32 s11, s10
 ; GFX9-NEXT:    s_addc_u32 s7, s7, s10
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v6, vcc
 ; GFX9-NEXT:    s_xor_b64 s[6:7], s[6:7], s[10:11]
 ; GFX9-NEXT:    v_mul_lo_u32 v5, s6, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v6, s6, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v8, s6, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v9, s7, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v4
 ; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v8, s7, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s7, v3
 ; GFX9-NEXT:    v_mov_b32_e32 v7, s1
 ; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v0, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v9, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v5, s8, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v6, s8, v3
 ; GFX9-NEXT:    v_mul_lo_u32 v8, s9, v3
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v1, vcc, s0, v1
 ; GFX9-NEXT:    v_add_u32_e32 v5, v6, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v6, s8, v3

 ; GFX90A-NEXT:    v_cvt_f32_u32_e32 v1, s13
 ; GFX90A-NEXT:    s_mov_b32 s19, 0xcf800000
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; GFX90A-NEXT:    s_sub_u32 s0, 0, s12
 ; GFX90A-NEXT:    v_mac_f32_e32 v0, s16, v1
 ; GFX90A-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX90A-NEXT:    s_subb_u32 s1, 0, s13
-; GFX90A-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    s_ashr_i32 s14, s5, 31
+; GFX90A-NEXT:    s_mov_b32 s15, s14
 ; GFX90A-NEXT:    v_mul_f32_e32 v0, s17, v0
 ; GFX90A-NEXT:    v_mul_f32_e32 v1, s18, v0
 ; GFX90A-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX90A-NEXT:    v_mac_f32_e32 v0, s19, v1
 ; GFX90A-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX90A-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX90A-NEXT:    s_mov_b32 s15, s14
+; GFX90A-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, s0, v1
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, s1, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v3, v5
 ; GFX90A-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, s0, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, v0, v2
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v0, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, v0, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v1, v6
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, s0, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, s1, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v2, v2, v3
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, s0, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, v1, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v7, v1, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v9, v0, v2
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, v0, v5
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v0, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v9
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, v1, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v6, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v2, vcc, v5, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    s_add_u32 s0, s4, s14
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX90A-NEXT:    s_addc_u32 s1, s5, s14
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX90A-NEXT:    s_xor_b64 s[4:5], s[0:1], s[14:15]
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, s4, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s4, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v2, s4, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, s5, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v0, s5, v0
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v3, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s5, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v0, vcc, v2, v6, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v2, vcc, v5, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v1, s5, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, s12, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, s12, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, s13, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v2, v2, v3

 ; GFX90A-NEXT:    v_mul_hi_u32 v6, v2, v5
 ; GFX90A-NEXT:    v_add_co_u32_e32 v7, vcc, v9, v7
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v10, v3, v8
 ; GFX90A-NEXT:    v_mul_lo_u32 v8, v3, v8
 ; GFX90A-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v8
 ; GFX90A-NEXT:    v_mul_hi_u32 v9, v3, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v6, vcc, v6, v10, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v7, vcc, v9, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, v3, v5
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v6, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, s0, v3
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, s0, v2
 ; GFX90A-NEXT:    v_add_u32_e32 v5, v6, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, s1, v2
 ; GFX90A-NEXT:    v_add_u32_e32 v5, v5, v6
 ; GFX90A-NEXT:    v_mul_lo_u32 v7, s0, v2
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v3, v7
 ; GFX90A-NEXT:    v_mul_lo_u32 v9, v3, v7
 ; GFX90A-NEXT:    v_mul_lo_u32 v11, v2, v5
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v2, v7
 ; GFX90A-NEXT:    v_mul_hi_u32 v10, v2, v5
 ; GFX90A-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v11
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v10, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v9
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, v3, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v6, vcc, v6, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, v3, v5
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX90A-NEXT:    s_ashr_i32 s10, s7, 31
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
 ; GFX90A-NEXT:    s_add_u32 s0, s6, s10
 ; GFX90A-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v5
 ; GFX90A-NEXT:    s_mov_b32 s11, s10
 ; GFX90A-NEXT:    s_addc_u32 s1, s7, s10
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v6, vcc
 ; GFX90A-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, s6, v3
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, s6, v2
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s6, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, s7, v2
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, s7, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v2, vcc, v6, v2
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, s7, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v2, vcc, v5, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, s7, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, s8, v3
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, s8, v2
 ; GFX90A-NEXT:    v_add_u32_e32 v5, v6, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, s9, v2
 ; GFX90A-NEXT:    v_add_u32_e32 v5, v5, v6

 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: srem_i64_oddk_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX6-NEXT:    s_mov_b32 s4, 0xffed2705
-; GFX6-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
 ; GFX6-NEXT:    s_add_u32 s2, s2, s8
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s4
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s4
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s4
 ; GFX6-NEXT:    s_mov_b32 s9, s8
 ; GFX6-NEXT:    s_addc_u32 s3, s3, s8
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
-; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
 ; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GFX6-NEXT:    s_xor_b64 s[2:3], s[2:3], s[8:9]
 ; GFX6-NEXT:    s_mov_b32 s5, s1
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s4
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s4
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s4
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
-; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v3
+; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v3
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v6, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v4, s2, v1
-; GFX6-NEXT:    v_mul_hi_u32 v6, s3, v1
+; GFX6-NEXT:    v_mul_hi_u32 v5, s3, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s3, v0
 ; GFX6-NEXT:    s_mov_b32 s4, s0
 ; GFX6-NEXT:    s_mov_b32 s0, 0x12d8fb
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v6, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s0
 ; GFX6-NEXT:    v_mul_hi_u32 v2, v0, s0
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s0
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GFX6-NEXT:    v_mov_b32_e32 v2, s3
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0

 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: srem_i64_oddk_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_mov_b32 s4, 0xffed2705
-; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s4
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s4
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s4
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s4
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s4
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s4
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
 ; GFX9-NEXT:    s_add_u32 s2, s2, s4
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
-; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v4
+; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v7, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v5, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    s_mov_b32 s5, s4
 ; GFX9-NEXT:    s_addc_u32 s3, s3, s4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    s_xor_b64 s[2:3], s[2:3], s[4:5]
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s2, v1
-; GFX9-NEXT:    v_mul_hi_u32 v6, s3, v1
+; GFX9-NEXT:    v_mul_hi_u32 v5, s3, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s3, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s3, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s3, v0
 ; GFX9-NEXT:    s_mov_b32 s5, 0x12d8fb
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s5
 ; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s5
 ; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s5
+; GFX9-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s3
 ; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, s2, v0
 ; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v2, v1, vcc
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s5, v0
-; GFX9-NEXT:    v_subbrev_co_u32_e32 v3, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_subrev_co_u32_e32 v4, vcc, s5, v2
-; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v3, vcc
+; GFX9-NEXT:    v_subbrev_co_u32_e32 v4, vcc, 0, v1, vcc
+; GFX9-NEXT:    v_subrev_co_u32_e32 v5, vcc, s5, v2
+; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v4, vcc
 ; GFX9-NEXT:    s_mov_b32 s2, 0x12d8fa
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s2, v2
 ; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
+; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v4
 ; GFX9-NEXT:    v_cndmask_b32_e32 v7, -1, v7, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s2, v0
-; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
+; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX9-NEXT:    v_cndmask_b32_e32 v4, -1, v4, vcc
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX9-NEXT:    v_cndmask_b32_e32 v5, -1, v5, vcc
+; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0
 ; GFX9-NEXT:    v_xor_b32_e32 v1, s4, v1
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s4
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s4, v0
 ; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
-; GFX9-NEXT:    global_store_dwordx2 v5, v[0:1], s[0:1]
+; GFX9-NEXT:    global_store_dwordx2 v3, v[0:1], s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX90A-LABEL: srem_i64_oddk_denom:
 ; GFX90A:       ; %bb.0:
 ; GFX90A-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX90A-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
 ; GFX90A-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX90A-NEXT:    s_mov_b32 s4, 0xffed2705
-; GFX90A-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX90A-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX90A-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX90A-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX90A-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX90A-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX90A-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX90A-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX90A-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, s4
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, s4
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX90A-NEXT:    v_sub_u32_e32 v3, v3, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v0, s4
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, v0, v3
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v0, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v1, v6
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v1, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, s4
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, s4
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX90A-NEXT:    v_sub_u32_e32 v3, v3, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, v0, s4
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, v1, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v7, v1, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v9, v0, v3
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, v0, v5
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v0, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v9
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v1, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v6, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    s_ashr_i32 s4, s3, 31
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX90A-NEXT:    s_add_u32 s2, s2, s4
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
 ; GFX90A-NEXT:    s_mov_b32 s5, s4
 ; GFX90A-NEXT:    s_addc_u32 s3, s3, s4
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
 ; GFX90A-NEXT:    s_xor_b64 s[2:3], s[2:3], s[4:5]
 ; GFX90A-NEXT:    v_mul_lo_u32 v4, s2, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s2, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, s2, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, s3, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v0, s3, v0
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v4, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s3, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v6, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v1, s3, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    s_mov_b32 s5, 0x12d8fb
 ; GFX90A-NEXT:    v_mul_lo_u32 v1, v1, s5
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, v0, s5
 ; GFX90A-NEXT:    v_mul_lo_u32 v0, v0, s5
 ; GFX90A-NEXT:    v_add_u32_e32 v1, v3, v1

 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
 ; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GFX6-NEXT:    s_xor_b64 s[12:13], s[2:3], s[10:11]
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GFX6-NEXT:    v_mov_b32_e32 v4, 0
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
-; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, s5, v0
 ; GFX6-NEXT:    s_mov_b32 s5, s1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v0
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v3
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v3
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
-; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v6, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v5, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s12, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s12, v0
-; GFX6-NEXT:    v_mul_hi_u32 v5, s12, v1
-; GFX6-NEXT:    v_mul_hi_u32 v6, s13, v1
+; GFX6-NEXT:    v_mul_hi_u32 v4, s12, v1
+; GFX6-NEXT:    v_mul_hi_u32 v5, s13, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s13, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s13, v0
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, s13, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s13, v0
 ; GFX6-NEXT:    s_mov_b32 s4, s0
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v6, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s8, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v2, s8, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v3, s9, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v0, s8, v0
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3

 ; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: srem_i64_pow2_shl_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x34
 ; GFX9-NEXT:    s_mov_b64 s[2:3], 0x1000
-; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
 ; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
 ; GFX9-NEXT:    s_add_u32 s2, s2, s4
 ; GFX9-NEXT:    s_mov_b32 s5, s4
 ; GFX9-NEXT:    s_addc_u32 s3, s3, s4
 ; GFX9-NEXT:    s_xor_b64 s[8:9], s[2:3], s[4:5]
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
 ; GFX9-NEXT:    s_sub_u32 s2, 0, s8
 ; GFX9-NEXT:    s_subb_u32 s3, 0, s9
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s10, s7, 31
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    s_add_u32 s0, s6, s10
 ; GFX9-NEXT:    s_mov_b32 s11, s10
-; GFX9-NEXT:    v_mul_lo_u32 v3, s2, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s2, v0
-; GFX9-NEXT:    v_mul_lo_u32 v6, s3, v0
-; GFX9-NEXT:    v_mul_lo_u32 v5, s2, v0
-; GFX9-NEXT:    s_addc_u32 s1, s7, s10
-; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
-; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
-; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v5
-; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
-; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, s2, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s2, v0
+; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v1
+; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v0
-; GFX9-NEXT:    v_mul_lo_u32 v6, s2, v0
+; GFX9-NEXT:    v_mul_lo_u32 v4, s2, v0
+; GFX9-NEXT:    s_addc_u32 s1, s7, s10
+; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v4
+; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v1
+; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GFX9-NEXT:    v_mul_lo_u32 v4, s3, v0
+; GFX9-NEXT:    v_mul_lo_u32 v5, s2, v0
 ; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
-; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
-; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
-; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v6
-; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v6
-; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
-; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v5
+; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v5
+; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
+; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v5, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, s6, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v0
-; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
-; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
+; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
+; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
+; GFX9-NEXT:    v_mul_hi_u32 v5, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v2, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s8, v1
-; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
-; GFX9-NEXT:    v_mul_lo_u32 v4, s9, v0
+; GFX9-NEXT:    v_mul_hi_u32 v2, s8, v0
+; GFX9-NEXT:    v_mul_lo_u32 v3, s9, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v0, s8, v0
-; GFX9-NEXT:    v_add_u32_e32 v1, v3, v1
-; GFX9-NEXT:    v_add_u32_e32 v1, v1, v4
-; GFX9-NEXT:    v_sub_u32_e32 v3, s7, v1
-; GFX9-NEXT:    v_mov_b32_e32 v4, s9
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
+; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
+; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT:    v_sub_u32_e32 v2, s7, v1
+; GFX9-NEXT:    v_mov_b32_e32 v3, s9
 ; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, s6, v0
-; GFX9-NEXT:    v_subb_co_u32_e64 v3, s[0:1], v3, v4, vcc
+; GFX9-NEXT:    v_subb_co_u32_e64 v2, s[0:1], v2, v3, vcc
 ; GFX9-NEXT:    v_subrev_co_u32_e64 v5, s[0:1], s8, v0
-; GFX9-NEXT:    v_subbrev_co_u32_e64 v6, s[2:3], 0, v3, s[0:1]
+; GFX9-NEXT:    v_subbrev_co_u32_e64 v6, s[2:3], 0, v2, s[0:1]
 ; GFX9-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v6
 ; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
 ; GFX9-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v5
-; GFX9-NEXT:    v_subb_co_u32_e64 v3, s[0:1], v3, v4, s[0:1]
+; GFX9-NEXT:    v_subb_co_u32_e64 v2, s[0:1], v2, v3, s[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
 ; GFX9-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v6
-; GFX9-NEXT:    v_subrev_co_u32_e64 v4, s[0:1], s8, v5
+; GFX9-NEXT:    v_subrev_co_u32_e64 v3, s[0:1], s8, v5
 ; GFX9-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[2:3]
-; GFX9-NEXT:    v_subbrev_co_u32_e64 v3, s[0:1], 0, v3, s[0:1]
+; GFX9-NEXT:    v_subbrev_co_u32_e64 v2, s[0:1], 0, v2, s[0:1]
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v7
-; GFX9-NEXT:    v_cndmask_b32_e64 v4, v5, v4, s[0:1]
+; GFX9-NEXT:    v_cndmask_b32_e64 v3, v5, v3, s[0:1]
 ; GFX9-NEXT:    v_mov_b32_e32 v5, s7
 ; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v5, v1, vcc
 ; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
 ; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
-; GFX9-NEXT:    v_cndmask_b32_e64 v3, v6, v3, s[0:1]
+; GFX9-NEXT:    v_cndmask_b32_e64 v2, v6, v2, s[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
 ; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
-; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v0, s10, v0
 ; GFX9-NEXT:    v_xor_b32_e32 v1, s10, v1
-; GFX9-NEXT:    v_mov_b32_e32 v3, s10
+; GFX9-NEXT:    v_mov_b32_e32 v2, s10
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s10, v0
-; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
+; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
+; GFX9-NEXT:    global_store_dwordx2 v4, v[0:1], s[4:5]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX90A-LABEL: srem_i64_pow2_shl_denom:
 ; GFX90A:       ; %bb.0:
 ; GFX90A-NEXT:    s_load_dword s4, s[0:1], 0x34
 ; GFX90A-NEXT:    s_mov_b64 s[2:3], 0x1000
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)

 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v0, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v1, v6
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v1, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, s0, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, s0, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX90A-NEXT:    v_mul_lo_u32 v4, s1, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v3, v4
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, s0, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, v1, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v7, v1, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v9, v0, v3
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, v0, v5
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v0, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v9
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
 ; GFX90A-NEXT:    v_mul_hi_u32 v4, v1, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v6, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX90A-NEXT:    s_add_u32 s0, s6, s10
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
 ; GFX90A-NEXT:    s_addc_u32 s1, s7, s10
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
 ; GFX90A-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
 ; GFX90A-NEXT:    v_mul_lo_u32 v4, s6, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s6, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, s6, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, s7, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v0, s7, v0
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v4, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s7, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v6, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v2, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v1, s8, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, s8, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v1, v3, v1
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, s9, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v1, v1, v3

 ; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    v_mul_f32_e32 v0, s19, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, s20, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, s21, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v0
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_ashr_i32 s12, s9, 31
 ; GFX6-NEXT:    s_add_u32 s0, s8, s12
-; GFX6-NEXT:    v_mul_lo_u32 v0, s2, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v2
-; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v2
-; GFX6-NEXT:    v_mul_lo_u32 v5, s2, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
+; GFX6-NEXT:    v_mul_lo_u32 v5, s2, v0
 ; GFX6-NEXT:    s_mov_b32 s13, s12
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v0, v4
-; GFX6-NEXT:    v_mul_lo_u32 v0, v2, v3
-; GFX6-NEXT:    v_mul_hi_u32 v4, v2, v5
-; GFX6-NEXT:    v_mul_hi_u32 v6, v2, v3
-; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v3
-; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v4, v0
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v4, v0, v5
+; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v6, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v5
 ; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v5
 ; GFX6-NEXT:    s_addc_u32 s1, s9, s12
 ; GFX6-NEXT:    s_xor_b64 s[8:9], s[0:1], s[12:13]
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v5, vcc
-; GFX6-NEXT:    v_mov_b32_e32 v0, 0
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v0, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
-; GFX6-NEXT:    v_mul_hi_u32 v4, s2, v2
-; GFX6-NEXT:    v_mul_lo_u32 v5, s3, v2
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_mul_lo_u32 v4, s2, v2
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v3
-; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v4
-; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v4
-; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v0
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v3
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v5, v0, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, s8, v1
-; GFX6-NEXT:    v_mul_hi_u32 v4, s8, v2
-; GFX6-NEXT:    v_mul_hi_u32 v5, s8, v1
-; GFX6-NEXT:    v_mul_hi_u32 v6, s9, v1
+; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v2, s8, v1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s8, v0
+; GFX6-NEXT:    v_mul_hi_u32 v4, s8, v1
+; GFX6-NEXT:    v_mul_hi_u32 v5, s9, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s9, v1
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s9, v2
-; GFX6-NEXT:    v_mul_hi_u32 v2, s9, v2
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v4, v2, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v0, vcc
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s16, v2
-; GFX6-NEXT:    v_mul_hi_u32 v3, s16, v1
-; GFX6-NEXT:    v_mul_lo_u32 v4, s17, v1
-; GFX6-NEXT:    v_mul_lo_u32 v1, s16, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, s9, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s9, v0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s9, v2
-; GFX6-NEXT:    v_mov_b32_e32 v4, s17
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s8, v1
-; GFX6-NEXT:    v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
-; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s16, v1
-; GFX6-NEXT:    v_subbrev_u32_e64 v6, s[2:3], 0, v3, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s17, v6
+; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v1, s16, v1
+; GFX6-NEXT:    v_mul_hi_u32 v2, s16, v0
+; GFX6-NEXT:    v_mul_lo_u32 v3, s17, v0
+; GFX6-NEXT:    v_mul_lo_u32 v0, s16, v0
+; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s9, v1
+; GFX6-NEXT:    v_mov_b32_e32 v3, s17
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s8, v0
+; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
+; GFX6-NEXT:    v_subrev_i32_e64 v4, s[0:1], s16, v0
+; GFX6-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s17, v5
+; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s16, v4
+; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s16, v5
-; GFX6-NEXT:    v_subb_u32_e64 v3, s[0:1], v3, v4, s[0:1]
-; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s17, v6
-; GFX6-NEXT:    v_subrev_i32_e64 v4, s[0:1], s16, v5
-; GFX6-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[2:3]
-; GFX6-NEXT:    v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s17, v5
+; GFX6-NEXT:    v_subrev_i32_e64 v3, s[0:1], s16, v4
+; GFX6-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
+; GFX6-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
 ; GFX6-NEXT:    s_ashr_i32 s2, s15, 31
-; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v7
+; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
 ; GFX6-NEXT:    s_add_u32 s8, s14, s2
-; GFX6-NEXT:    v_cndmask_b32_e64 v3, v6, v3, s[0:1]
-; GFX6-NEXT:    v_mov_b32_e32 v6, s9
+; GFX6-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
+; GFX6-NEXT:    v_mov_b32_e32 v5, s9
 ; GFX6-NEXT:    s_mov_b32 s3, s2
 ; GFX6-NEXT:    s_addc_u32 s9, s15, s2
 ; GFX6-NEXT:    s_xor_b64 s[8:9], s[8:9], s[2:3]
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, s8
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v8, s9
-; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s17, v2
-; GFX6-NEXT:    v_mac_f32_e32 v7, s18, v8
-; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s16, v1
-; GFX6-NEXT:    v_rcp_f32_e32 v7, v7
-; GFX6-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s17, v2
-; GFX6-NEXT:    v_cndmask_b32_e32 v6, v6, v9, vcc
-; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX6-NEXT:    v_cndmask_b32_e64 v3, v5, v4, s[0:1]
-; GFX6-NEXT:    v_mul_f32_e32 v4, s19, v7
-; GFX6-NEXT:    v_mul_f32_e32 v5, s20, v4
-; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX6-NEXT:    v_mac_f32_e32 v4, s21, v5
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s8
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, s9
+; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s17, v1
+; GFX6-NEXT:    v_mac_f32_e32 v6, s18, v7
+; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s16, v0
+; GFX6-NEXT:    v_rcp_f32_e32 v6, v6
+; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s17, v1
+; GFX6-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
+; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
+; GFX6-NEXT:    v_mul_f32_e32 v3, s19, v6
+; GFX6-NEXT:    v_mul_f32_e32 v4, s20, v3
+; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
+; GFX6-NEXT:    v_mac_f32_e32 v3, s21, v4
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GFX6-NEXT:    s_sub_u32 s0, 0, s8
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v4
-; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v5
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v2, s0, v3
+; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
 ; GFX6-NEXT:    s_subb_u32 s1, 0, s9
-; GFX6-NEXT:    v_mul_lo_u32 v7, s1, v4
+; GFX6-NEXT:    v_mul_lo_u32 v6, s1, v3
 ; GFX6-NEXT:    s_ashr_i32 s14, s11, 31
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v4
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
-; GFX6-NEXT:    v_mul_lo_u32 v7, v4, v3
-; GFX6-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GFX6-NEXT:    v_mul_hi_u32 v9, v4, v3
-; GFX6-NEXT:    v_mul_hi_u32 v10, v5, v3
-; GFX6-NEXT:    v_mul_lo_u32 v3, v5, v3
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v9, v5, v6
-; GFX6-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v3
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
+; GFX6-NEXT:    v_mul_lo_u32 v6, v3, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v3, v5
+; GFX6-NEXT:    v_mul_hi_u32 v8, v3, v2
+; GFX6-NEXT:    v_mul_hi_u32 v9, v4, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, v4, v2
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v8, v4, v5
+; GFX6-NEXT:    v_mul_hi_u32 v5, v4, v5
 ; GFX6-NEXT:    s_mov_b32 s15, s14
+; GFX6-NEXT:    v_xor_b32_e32 v0, s12, v0
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v9, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v5, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, s0, v3
+; GFX6-NEXT:    v_mul_hi_u32 v5, s0, v2
+; GFX6-NEXT:    v_mul_lo_u32 v6, s1, v2
 ; GFX6-NEXT:    v_xor_b32_e32 v1, s12, v1
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v8, v6, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v10, v0, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v5, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v6, s0, v3
-; GFX6-NEXT:    v_mul_lo_u32 v7, s1, v3
-; GFX6-NEXT:    v_xor_b32_e32 v2, s12, v2
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v3
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GFX6-NEXT:    v_mul_lo_u32 v9, v3, v5
-; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v6
-; GFX6-NEXT:    v_mul_hi_u32 v11, v3, v5
-; GFX6-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GFX6-NEXT:    v_mul_lo_u32 v6, v4, v6
-; GFX6-NEXT:    v_mul_hi_u32 v7, v4, v5
-; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, v4, v5
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
-; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v10, v8, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v7, v0, vcc
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v2
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GFX6-NEXT:    v_mul_lo_u32 v8, v2, v4
+; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v5
+; GFX6-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GFX6-NEXT:    v_mul_hi_u32 v7, v3, v5
+; GFX6-NEXT:    v_mul_lo_u32 v5, v3, v5
+; GFX6-NEXT:    v_mul_hi_u32 v6, v3, v4
+; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, v3, v4
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v9, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GFX6-NEXT:    s_add_u32 s0, s10, s14
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GFX6-NEXT:    s_addc_u32 s1, s11, s14
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
 ; GFX6-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
-; GFX6-NEXT:    v_mul_lo_u32 v5, s10, v4
-; GFX6-NEXT:    v_mul_hi_u32 v6, s10, v3
-; GFX6-NEXT:    v_mul_hi_u32 v8, s10, v4
-; GFX6-NEXT:    v_mul_hi_u32 v9, s11, v4
-; GFX6-NEXT:    v_mul_lo_u32 v4, s11, v4
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v8, s11, v3
-; GFX6-NEXT:    v_mul_hi_u32 v3, s11, v3
-; GFX6-NEXT:    v_mov_b32_e32 v7, s12
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v3, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v9, v0, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
-; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v0, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v4, s8, v0
-; GFX6-NEXT:    v_mul_hi_u32 v5, s8, v3
-; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s12, v1
-; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v2, v7, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s9, v3
-; GFX6-NEXT:    v_mul_lo_u32 v3, s8, v3
+; GFX6-NEXT:    v_mul_lo_u32 v4, s10, v3
+; GFX6-NEXT:    v_mul_hi_u32 v5, s10, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, s10, v3
+; GFX6-NEXT:    v_mul_hi_u32 v8, s11, v3
+; GFX6-NEXT:    v_mul_lo_u32 v3, s11, v3
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
-; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s11, v2
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v7, s11, v2
+; GFX6-NEXT:    v_mul_hi_u32 v2, s11, v2
+; GFX6-NEXT:    v_mov_b32_e32 v6, s12
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v2, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v8, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v3, s8, v3
+; GFX6-NEXT:    v_mul_hi_u32 v4, s8, v2
+; GFX6-NEXT:    v_mul_lo_u32 v5, s9, v2
+; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s12, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, s8, v2
+; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s11, v3
 ; GFX6-NEXT:    v_mov_b32_e32 v5, s9
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s10, v3
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s10, v2
 ; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
-; GFX6-NEXT:    v_subrev_i32_e64 v6, s[0:1], s8, v3
+; GFX6-NEXT:    v_subrev_i32_e64 v6, s[0:1], s8, v2
 ; GFX6-NEXT:    v_subbrev_u32_e64 v7, s[2:3], 0, v4, s[0:1]
 ; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v7
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
 ; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v6
 ; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[2:3]
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v7
 ; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s8, v6
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[2:3]
 ; GFX6-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
 ; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v8
 ; GFX6-NEXT:    v_cndmask_b32_e64 v4, v7, v4, s[0:1]
 ; GFX6-NEXT:    v_mov_b32_e32 v7, s11
-; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v7, v2, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
+; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v7, v3, vcc
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
 ; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v2
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v3
 ; GFX6-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
 ; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT:    v_xor_b32_e32 v2, s14, v2
 ; GFX6-NEXT:    v_xor_b32_e32 v3, s14, v3
-; GFX6-NEXT:    v_xor_b32_e32 v4, s14, v2
-; GFX6-NEXT:    v_mov_b32_e32 v5, s14
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s14, v3
-; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v4, v5, vcc
+; GFX6-NEXT:    v_mov_b32_e32 v4, s14
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s14, v2
+; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
 ; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: srem_v2i64_pow2_shl_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x44
 ; GFX9-NEXT:    s_mov_b64 s[2:3], 0x1000
 ; GFX9-NEXT:    s_mov_b32 s16, 0x4f800000

 ; GFX9-NEXT:    v_mac_f32_e32 v0, s16, v1
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; GFX9-NEXT:    v_mul_f32_e32 v0, s17, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, s18, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, s19, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v0
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s8, s5, 31
 ; GFX9-NEXT:    s_mov_b32 s9, s8
-; GFX9-NEXT:    v_mul_lo_u32 v0, s2, v1
-; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v2
-; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v2
-; GFX9-NEXT:    v_mul_lo_u32 v4, s2, v2
-; GFX9-NEXT:    v_add_u32_e32 v0, v3, v0
-; GFX9-NEXT:    v_add_u32_e32 v5, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v4
-; GFX9-NEXT:    v_mul_lo_u32 v6, v2, v5
-; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v5
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v5
-; GFX9-NEXT:    v_mov_b32_e32 v0, 0
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v1
+; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v0
+; GFX9-NEXT:    v_mul_lo_u32 v4, s2, v0
+; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v2
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v0, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, s2, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s2, v2
-; GFX9-NEXT:    v_mul_lo_u32 v5, s3, v2
-; GFX9-NEXT:    v_mul_lo_u32 v6, s2, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v1
+; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GFX9-NEXT:    v_mul_lo_u32 v4, s3, v0
+; GFX9-NEXT:    v_mul_lo_u32 v5, s2, v0
 ; GFX9-NEXT:    s_add_u32 s2, s4, s8
-; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
-; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
-; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v3
-; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v6
-; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v6
-; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
-; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v5
+; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v5
+; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
+; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v5, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v0, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    s_addc_u32 s3, s5, s8
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX9-NEXT:    s_xor_b64 s[14:15], s[2:3], s[8:9]
-; GFX9-NEXT:    v_mul_lo_u32 v3, s14, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s14, v2
-; GFX9-NEXT:    v_mul_hi_u32 v5, s14, v1
-; GFX9-NEXT:    v_mul_hi_u32 v6, s15, v1
+; GFX9-NEXT:    v_mul_lo_u32 v2, s14, v1
+; GFX9-NEXT:    v_mul_hi_u32 v3, s14, v0
+; GFX9-NEXT:    v_mul_hi_u32 v4, s14, v1
+; GFX9-NEXT:    v_mul_hi_u32 v5, s15, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s15, v1
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v5, s15, v2
-; GFX9-NEXT:    v_mul_hi_u32 v2, s15, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v4, s15, v0
+; GFX9-NEXT:    v_mul_hi_u32 v0, s15, v0
 ; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v4, v2, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v0, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v2, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v3, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v2, s12, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v0, v1
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v2, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, s12, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s12, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s13, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s12, v1
+; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
 ; GFX9-NEXT:    v_sub_u32_e32 v3, s15, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v4, s13
 ; GFX9-NEXT:    v_sub_co_u32_e32 v1, vcc, s14, v1
 ; GFX9-NEXT:    v_subb_co_u32_e64 v3, s[0:1], v3, v4, vcc
 ; GFX9-NEXT:    v_subrev_co_u32_e64 v5, s[0:1], s12, v1
 ; GFX9-NEXT:    v_subbrev_co_u32_e64 v6, s[2:3], 0, v3, s[0:1]

 ; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v5, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v5, v3
 ; GFX9-NEXT:    s_ashr_i32 s12, s7, 31
 ; GFX9-NEXT:    s_mov_b32 s13, s12
 ; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v9
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v8, v3, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v0, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v10, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v6, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v5, s0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v6, s0, v3
 ; GFX9-NEXT:    v_mul_lo_u32 v7, s1, v3
 ; GFX9-NEXT:    v_mul_lo_u32 v8, s0, v3
 ; GFX9-NEXT:    s_add_u32 s0, s6, s12
 ; GFX9-NEXT:    v_add_u32_e32 v5, v6, v5
 ; GFX9-NEXT:    v_add_u32_e32 v5, v5, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v3, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v3, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v7, v4, v8
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v4, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v6, v4, v5
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
 ; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v4, v5
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v7, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v6, v0, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
 ; GFX9-NEXT:    s_addc_u32 s1, s7, s12
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v6, vcc
 ; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[12:13]
 ; GFX9-NEXT:    v_mul_lo_u32 v5, s6, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v6, s6, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v8, s6, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v9, s7, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v4
 ; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v8, s7, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s7, v3
 ; GFX9-NEXT:    v_xor_b32_e32 v1, s8, v1
 ; GFX9-NEXT:    v_xor_b32_e32 v2, s8, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v0, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v9, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s10, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v5, s10, v3
 ; GFX9-NEXT:    v_mul_lo_u32 v6, s11, v3
 ; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v3
 ; GFX9-NEXT:    v_mov_b32_e32 v7, s8
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v1, vcc, s8, v1

 ; GFX90A-NEXT:    v_cvt_f32_u32_e32 v1, s13
 ; GFX90A-NEXT:    s_mov_b32 s19, 0xcf800000
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; GFX90A-NEXT:    s_sub_u32 s0, 0, s12
 ; GFX90A-NEXT:    v_mac_f32_e32 v0, s16, v1
 ; GFX90A-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX90A-NEXT:    s_subb_u32 s1, 0, s13
-; GFX90A-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    s_ashr_i32 s14, s5, 31
+; GFX90A-NEXT:    s_mov_b32 s15, s14
 ; GFX90A-NEXT:    v_mul_f32_e32 v0, s17, v0
 ; GFX90A-NEXT:    v_mul_f32_e32 v1, s18, v0
 ; GFX90A-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX90A-NEXT:    v_mac_f32_e32 v0, s19, v1
 ; GFX90A-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX90A-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX90A-NEXT:    s_mov_b32 s15, s14
+; GFX90A-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, s0, v1
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, s1, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v3, v5
 ; GFX90A-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, s0, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, v0, v2
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v0, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, v0, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v1, v6
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, s0, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, s1, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v2, v2, v3
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, s0, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, v1, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v7, v1, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v9, v0, v2
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, v0, v5
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v0, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v9
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
 ; GFX90A-NEXT:    v_mul_hi_u32 v3, v1, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v6, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v2, vcc, v5, v2
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX90A-NEXT:    s_add_u32 s0, s4, s14
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX90A-NEXT:    s_addc_u32 s1, s5, s14
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; GFX90A-NEXT:    s_xor_b64 s[4:5], s[0:1], s[14:15]
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, s4, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s4, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v2, s4, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, s5, v0
 ; GFX90A-NEXT:    v_mul_lo_u32 v0, s5, v0
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v3, v0
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s5, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v0, vcc, v2, v6, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v2, vcc, v5, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v1, s5, v1
 ; GFX90A-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v1, s12, v1
 ; GFX90A-NEXT:    v_mul_hi_u32 v2, s12, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v1, v2, v1
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, s13, v0
 ; GFX90A-NEXT:    v_add_u32_e32 v1, v1, v2

 ; GFX90A-NEXT:    v_mul_hi_u32 v6, v2, v5
 ; GFX90A-NEXT:    v_add_co_u32_e32 v7, vcc, v9, v7
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v10, v3, v8
 ; GFX90A-NEXT:    v_mul_lo_u32 v8, v3, v8
 ; GFX90A-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v8
 ; GFX90A-NEXT:    v_mul_hi_u32 v9, v3, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v6, vcc, v6, v10, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v7, vcc, v9, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, v3, v5
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v6, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, s0, v3
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, s0, v2
 ; GFX90A-NEXT:    v_add_u32_e32 v5, v6, v5
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, s1, v2
 ; GFX90A-NEXT:    v_add_u32_e32 v5, v5, v6
 ; GFX90A-NEXT:    v_mul_lo_u32 v7, s0, v2
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, v3, v7
 ; GFX90A-NEXT:    v_mul_lo_u32 v9, v3, v7
 ; GFX90A-NEXT:    v_mul_lo_u32 v11, v2, v5
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, v2, v7
 ; GFX90A-NEXT:    v_mul_hi_u32 v10, v2, v5
 ; GFX90A-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v11
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v10, vcc
 ; GFX90A-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v9
 ; GFX90A-NEXT:    v_mul_hi_u32 v6, v3, v5
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v6, vcc, v6, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, v3, v5
 ; GFX90A-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
 ; GFX90A-NEXT:    s_ashr_i32 s10, s7, 31
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
 ; GFX90A-NEXT:    s_add_u32 s0, s6, s10
 ; GFX90A-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v5
 ; GFX90A-NEXT:    s_mov_b32 s11, s10
 ; GFX90A-NEXT:    s_addc_u32 s1, s7, s10
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v6, vcc
 ; GFX90A-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
 ; GFX90A-NEXT:    v_mul_lo_u32 v6, s6, v3
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, s6, v2
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s6, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_mul_hi_u32 v8, s7, v2
 ; GFX90A-NEXT:    v_mul_lo_u32 v2, s7, v2
 ; GFX90A-NEXT:    v_add_co_u32_e32 v2, vcc, v6, v2
 ; GFX90A-NEXT:    v_mul_hi_u32 v7, s7, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v2, vcc, v5, v8, vcc
-; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
+; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, s7, v3
 ; GFX90A-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
 ; GFX90A-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
 ; GFX90A-NEXT:    v_mul_lo_u32 v3, s4, v3
 ; GFX90A-NEXT:    v_mul_hi_u32 v5, s4, v2
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v5, v3
 ; GFX90A-NEXT:    v_mul_lo_u32 v5, s5, v2
 ; GFX90A-NEXT:    v_add_u32_e32 v3, v3, v5

llvm/test/CodeGen/AMDGPU/bypass-div.ll

 ; GFX9-NEXT:    v_xor_b32_e32 v3, v3, v4
 ; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v2
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, v3
 ; GFX9-NEXT:    v_sub_co_u32_e32 v7, vcc, 0, v2
 ; GFX9-NEXT:    v_subb_co_u32_e32 v8, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v6
 ; GFX9-NEXT:    v_rcp_f32_e32 v5, v5
-; GFX9-NEXT:    v_mov_b32_e32 v14, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
 ; GFX9-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
 ; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
 ; GFX9-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v6
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v7, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v8, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v7, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v12, v7, v5
 ; GFX9-NEXT:    v_add3_u32 v9, v10, v11, v9
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v5, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v12
 ; GFX9-NEXT:    v_mul_hi_u32 v13, v5, v9
-; GFX9-NEXT:    v_mul_hi_u32 v15, v6, v9
+; GFX9-NEXT:    v_mul_hi_u32 v14, v6, v9
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v6, v9
 ; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
 ; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v13, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v13, v6, v12
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v6, v12
 ; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v13
 ; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v11, v12, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v15, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v14, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
 ; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v9
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v6, v10, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v7, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v8, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v7, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v5
 ; GFX9-NEXT:    v_add3_u32 v8, v10, v9, v8
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v5, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v5, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v13, v5, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v6, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v6, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v6, v8
 ; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v12, v11
 ; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, 0, v13, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v8
 ; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v11, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v12, v10, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v9, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v6, v8, vcc
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v7
 ; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v0, v6
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v7, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v1, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v1, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v10
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v5, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v11, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v3, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v6
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v2, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v2, v5
 ; GFX9-NEXT:    v_add3_u32 v8, v10, v9, v8
 ; GFX9-NEXT:    v_sub_u32_e32 v9, v1, v8

 ; GFX9-NEXT:    s_cbranch_execz BB1_2
 ; GFX9-NEXT:  ; %bb.1:
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v2
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
 ; GFX9-NEXT:    v_sub_co_u32_e32 v6, vcc, 0, v2
 ; GFX9-NEXT:    v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
-; GFX9-NEXT:    v_mov_b32_e32 v12, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GFX9-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
 ; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v7, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v6, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v4
 ; GFX9-NEXT:    v_add3_u32 v8, v10, v8, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v11
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v13, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v14, v5, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_mul_lo_u32 v12, v5, v11
+; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v10
 ; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v13, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v13, v5, v11
-; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v13
+; GFX9-NEXT:    v_mul_hi_u32 v13, v5, v8
+; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v12
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v14, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v13, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v5, v9, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v6, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v6, v4
 ; GFX9-NEXT:    v_add3_u32 v7, v9, v8, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v6
-; GFX9-NEXT:    v_mul_hi_u32 v13, v4, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v5, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v5, v6
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v5, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v13, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v5, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v10, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v11, v9, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v8, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v5, v7, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v9, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v9, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v3, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v4
 ; GFX9-NEXT:    v_add3_u32 v6, v8, v7, v6
 ; GFX9-NEXT:    v_sub_u32_e32 v7, v1, v6

 ; GFX9-NEXT:    v_xor_b32_e32 v3, v3, v4
 ; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v2
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
 ; GFX9-NEXT:    v_sub_co_u32_e32 v6, vcc, 0, v2
 ; GFX9-NEXT:    v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
-; GFX9-NEXT:    v_mov_b32_e32 v13, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GFX9-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
 ; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v6, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v7, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v6, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v4
 ; GFX9-NEXT:    v_add3_u32 v8, v9, v10, v8
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v4, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v4, v11
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v14, v5, v8
+; GFX9-NEXT:    v_mul_hi_u32 v13, v5, v8
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
 ; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v12, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v12, v5, v11
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v12
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v14, v13, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v13, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v5, v9, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v6, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v6, v4
 ; GFX9-NEXT:    v_add3_u32 v7, v9, v8, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v6
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v5, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v5, v6
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v5, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
 ; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v5, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v10, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v11, v9, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v8, v13, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v5, v7, vcc
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v6
 ; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v5
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v6, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v6
 ; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v1, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
 ; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v9
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v13, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v10, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v3, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v2, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v2, v4
 ; GFX9-NEXT:    v_add3_u32 v5, v8, v5, v7
 ; GFX9-NEXT:    v_sub_u32_e32 v7, v1, v5

 ; GFX9-NEXT:    s_cbranch_execz BB3_2
 ; GFX9-NEXT:  ; %bb.1:
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v2
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
 ; GFX9-NEXT:    v_sub_co_u32_e32 v6, vcc, 0, v2
 ; GFX9-NEXT:    v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
-; GFX9-NEXT:    v_mov_b32_e32 v12, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GFX9-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
 ; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v7, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v6, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v4
 ; GFX9-NEXT:    v_add3_u32 v8, v10, v8, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v11
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v13, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v14, v5, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_mul_lo_u32 v12, v5, v11
+; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v10
 ; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v13, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v13, v5, v11
-; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v13
+; GFX9-NEXT:    v_mul_hi_u32 v13, v5, v8
+; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v12
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v14, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v13, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v5, v9, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v6, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v6, v4
 ; GFX9-NEXT:    v_add3_u32 v7, v9, v8, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v6
-; GFX9-NEXT:    v_mul_hi_u32 v13, v4, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v5, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v5, v6
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v5, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v13, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v5, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v10, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v11, v9, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v8, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v5, v7, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v9, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v9, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v3, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v2, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v2, v4
 ; GFX9-NEXT:    v_add3_u32 v5, v7, v5, v6
 ; GFX9-NEXT:    v_sub_u32_e32 v6, v1, v5

 ; GFX9-NEXT:    v_xor_b32_e32 v3, v3, v4
 ; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v4
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v2
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, v3
 ; GFX9-NEXT:    v_sub_co_u32_e32 v7, vcc, 0, v2
 ; GFX9-NEXT:    v_subb_co_u32_e32 v8, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v6
 ; GFX9-NEXT:    v_rcp_f32_e32 v5, v5
-; GFX9-NEXT:    v_mov_b32_e32 v14, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
 ; GFX9-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
 ; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
 ; GFX9-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v6
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v7, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v8, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v7, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v12, v7, v5
 ; GFX9-NEXT:    v_add3_u32 v9, v10, v11, v9
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v5, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v12
 ; GFX9-NEXT:    v_mul_hi_u32 v13, v5, v9
-; GFX9-NEXT:    v_mul_hi_u32 v15, v6, v9
+; GFX9-NEXT:    v_mul_hi_u32 v14, v6, v9
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v6, v9
 ; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
 ; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v13, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v13, v6, v12
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v6, v12
 ; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v13
 ; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v11, v12, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v15, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v14, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
 ; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v9
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v6, v10, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v7, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v8, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v7, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v5
 ; GFX9-NEXT:    v_add3_u32 v8, v10, v9, v8
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v5, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v5, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v13, v5, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v6, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v6, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v6, v8
 ; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v12, v11
 ; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, 0, v13, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v8
 ; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v11, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v12, v10, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v9, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v6, v8, vcc
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v7
 ; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v0, v6
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v7, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v1, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v1, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v10
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v5, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v11, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v3, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v6
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v2, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v2, v5
 ; GFX9-NEXT:    v_add3_u32 v8, v10, v9, v8
 ; GFX9-NEXT:    v_sub_u32_e32 v9, v1, v8

 ; GFX9-NEXT:    s_cbranch_execz BB9_2
 ; GFX9-NEXT:  ; %bb.1:
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v2
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
 ; GFX9-NEXT:    v_sub_co_u32_e32 v6, vcc, 0, v2
 ; GFX9-NEXT:    v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
-; GFX9-NEXT:    v_mov_b32_e32 v12, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GFX9-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
 ; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v7, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v6, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v4
 ; GFX9-NEXT:    v_add3_u32 v8, v10, v8, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v11
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v13, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v14, v5, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_mul_lo_u32 v12, v5, v11
+; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v10
 ; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v13, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v13, v5, v11
-; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v13
+; GFX9-NEXT:    v_mul_hi_u32 v13, v5, v8
+; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v12
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v14, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v13, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v5, v9, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v6, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v6, v4
 ; GFX9-NEXT:    v_add3_u32 v7, v9, v8, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v6
-; GFX9-NEXT:    v_mul_hi_u32 v13, v4, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v5, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v5, v6
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v5, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v13, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v5, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v10, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v11, v9, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v8, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v5, v7, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v7, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v9, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v9, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v5
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v3, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v4
 ; GFX9-NEXT:    v_add3_u32 v6, v8, v7, v6
 ; GFX9-NEXT:    v_sub_u32_e32 v7, v1, v6

llvm/test/CodeGen/AMDGPU/flat-scratch.ll

bb:
   ret void
 }
 
 define void @store_load_vindex_foo(i32 %idx) {
 ; GFX9-LABEL: store_load_vindex_foo:
 ; GFX9:       ; %bb.0: ; %bb
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s32
-; GFX9-NEXT:    v_mov_b32_e32 v3, 15
 ; GFX9-NEXT:    v_lshl_add_u32 v2, v0, 2, v1
-; GFX9-NEXT:    v_and_b32_e32 v0, v0, v3
+; GFX9-NEXT:    v_mov_b32_e32 v3, 15
+; GFX9-NEXT:    v_and_b32_e32 v0, 15, v0
 ; GFX9-NEXT:    scratch_store_dword v2, v3, off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    v_lshl_add_u32 v0, v0, 2, v1
 ; GFX9-NEXT:    scratch_load_dword v0, v0, off glc
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: store_load_vindex_foo:
 ; GFX10:       ; %bb.0: ; %bb
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_mov_b32_e32 v1, 15
-; GFX10-NEXT:    v_mov_b32_e32 v2, s32
-; GFX10-NEXT:    v_and_b32_e32 v3, v0, v1
-; GFX10-NEXT:    v_lshl_add_u32 v0, v0, 2, v2
-; GFX10-NEXT:    v_lshl_add_u32 v2, v3, 2, v2
-; GFX10-NEXT:    scratch_store_dword v0, v1, off
+; GFX10-NEXT:    v_mov_b32_e32 v1, s32
+; GFX10-NEXT:    v_and_b32_e32 v2, 15, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, 15
+; GFX10-NEXT:    v_lshl_add_u32 v0, v0, 2, v1
+; GFX10-NEXT:    v_lshl_add_u32 v1, v2, 2, v1
+; GFX10-NEXT:    scratch_store_dword v0, v3, off
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    scratch_load_dword v0, v2, off glc dlc
+; GFX10-NEXT:    scratch_load_dword v0, v1, off glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-PAL-LABEL: store_load_vindex_foo:
 ; GFX9-PAL:       ; %bb.0: ; %bb
 ; GFX9-PAL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-PAL-NEXT:    v_mov_b32_e32 v1, s32
-; GFX9-PAL-NEXT:    v_mov_b32_e32 v3, 15
 ; GFX9-PAL-NEXT:    v_lshl_add_u32 v2, v0, 2, v1
-; GFX9-PAL-NEXT:    v_and_b32_e32 v0, v0, v3
+; GFX9-PAL-NEXT:    v_mov_b32_e32 v3, 15
+; GFX9-PAL-NEXT:    v_and_b32_e32 v0, 15, v0
 ; GFX9-PAL-NEXT:    scratch_store_dword v2, v3, off
 ; GFX9-PAL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-PAL-NEXT:    v_lshl_add_u32 v0, v0, 2, v1
 ; GFX9-PAL-NEXT:    scratch_load_dword v0, v0, off glc
 ; GFX9-PAL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-PAL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-PAL-LABEL: store_load_vindex_foo:
 ; GFX10-PAL:       ; %bb.0: ; %bb
 ; GFX10-PAL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-PAL-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-PAL-NEXT:    v_mov_b32_e32 v1, 15
-; GFX10-PAL-NEXT:    v_mov_b32_e32 v2, s32
-; GFX10-PAL-NEXT:    v_and_b32_e32 v3, v0, v1
-; GFX10-PAL-NEXT:    v_lshl_add_u32 v0, v0, 2, v2
-; GFX10-PAL-NEXT:    v_lshl_add_u32 v2, v3, 2, v2
-; GFX10-PAL-NEXT:    scratch_store_dword v0, v1, off
+; GFX10-PAL-NEXT:    v_mov_b32_e32 v1, s32
+; GFX10-PAL-NEXT:    v_and_b32_e32 v2, 15, v0
+; GFX10-PAL-NEXT:    v_mov_b32_e32 v3, 15
+; GFX10-PAL-NEXT:    v_lshl_add_u32 v0, v0, 2, v1
+; GFX10-PAL-NEXT:    v_lshl_add_u32 v1, v2, 2, v1
+; GFX10-PAL-NEXT:    scratch_store_dword v0, v3, off
 ; GFX10-PAL-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-PAL-NEXT:    scratch_load_dword v0, v2, off glc dlc
+; GFX10-PAL-NEXT:    scratch_load_dword v0, v1, off glc dlc
 ; GFX10-PAL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-PAL-NEXT:    s_setpc_b64 s[30:31]
 bb:
   %i = alloca [32 x float], align 4, addrspace(5)
   %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
   %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
   %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
   store volatile i32 15, i32 addrspace(5)* %i8, align 4

 define void @store_load_vindex_small_offset_foo(i32 %idx) {
 ; GFX9-LABEL: store_load_vindex_small_offset_foo:
 ; GFX9:       ; %bb.0: ; %bb
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    scratch_load_dword v1, off, s32 glc
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_add_i32 vcc_hi, s32, 0x100
 ; GFX9-NEXT:    v_mov_b32_e32 v1, vcc_hi
-; GFX9-NEXT:    v_mov_b32_e32 v3, 15
 ; GFX9-NEXT:    v_lshl_add_u32 v2, v0, 2, v1
-; GFX9-NEXT:    v_and_b32_e32 v0, v0, v3
+; GFX9-NEXT:    v_mov_b32_e32 v3, 15
+; GFX9-NEXT:    v_and_b32_e32 v0, 15, v0
 ; GFX9-NEXT:    scratch_store_dword v2, v3, off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    v_lshl_add_u32 v0, v0, 2, v1
 ; GFX9-NEXT:    scratch_load_dword v0, v0, off glc
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: store_load_vindex_small_offset_foo:
 ; GFX10:       ; %bb.0: ; %bb
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_mov_b32_e32 v1, 15
 ; GFX10-NEXT:    s_add_i32 vcc_lo, s32, 0x100
-; GFX10-NEXT:    v_mov_b32_e32 v2, vcc_lo
-; GFX10-NEXT:    v_and_b32_e32 v3, v0, v1
-; GFX10-NEXT:    v_lshl_add_u32 v0, v0, 2, v2
-; GFX10-NEXT:    v_lshl_add_u32 v2, v3, 2, v2
-; GFX10-NEXT:    scratch_load_dword v3, off, s32 glc dlc
+; GFX10-NEXT:    v_and_b32_e32 v2, 15, v0
+; GFX10-NEXT:    v_mov_b32_e32 v1, vcc_lo
+; GFX10-NEXT:    v_mov_b32_e32 v3, 15
+; GFX10-NEXT:    v_lshl_add_u32 v0, v0, 2, v1
+; GFX10-NEXT:    v_lshl_add_u32 v1, v2, 2, v1
+; GFX10-NEXT:    scratch_load_dword v2, off, s32 glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    scratch_store_dword v0, v1, off
+; GFX10-NEXT:    scratch_store_dword v0, v3, off
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    scratch_load_dword v0, v2, off glc dlc
+; GFX10-NEXT:    scratch_load_dword v0, v1, off glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-PAL-LABEL: store_load_vindex_small_offset_foo:
 ; GFX9-PAL:       ; %bb.0: ; %bb
 ; GFX9-PAL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-PAL-NEXT:    scratch_load_dword v1, off, s32 glc
 ; GFX9-PAL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-PAL-NEXT:    s_add_i32 vcc_hi, s32, 0x100
 ; GFX9-PAL-NEXT:    v_mov_b32_e32 v1, vcc_hi
-; GFX9-PAL-NEXT:    v_mov_b32_e32 v3, 15
 ; GFX9-PAL-NEXT:    v_lshl_add_u32 v2, v0, 2, v1
-; GFX9-PAL-NEXT:    v_and_b32_e32 v0, v0, v3
+; GFX9-PAL-NEXT:    v_mov_b32_e32 v3, 15
+; GFX9-PAL-NEXT:    v_and_b32_e32 v0, 15, v0
 ; GFX9-PAL-NEXT:    scratch_store_dword v2, v3, off
 ; GFX9-PAL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-PAL-NEXT:    v_lshl_add_u32 v0, v0, 2, v1
 ; GFX9-PAL-NEXT:    scratch_load_dword v0, v0, off glc
 ; GFX9-PAL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-PAL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-PAL-LABEL: store_load_vindex_small_offset_foo:
 ; GFX10-PAL:       ; %bb.0: ; %bb
 ; GFX10-PAL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-PAL-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-PAL-NEXT:    v_mov_b32_e32 v1, 15
 ; GFX10-PAL-NEXT:    s_add_i32 vcc_lo, s32, 0x100
-; GFX10-PAL-NEXT:    v_mov_b32_e32 v2, vcc_lo
-; GFX10-PAL-NEXT:    v_and_b32_e32 v3, v0, v1
-; GFX10-PAL-NEXT:    v_lshl_add_u32 v0, v0, 2, v2
-; GFX10-PAL-NEXT:    v_lshl_add_u32 v2, v3, 2, v2
-; GFX10-PAL-NEXT:    scratch_load_dword v3, off, s32 glc dlc
+; GFX10-PAL-NEXT:    v_and_b32_e32 v2, 15, v0
+; GFX10-PAL-NEXT:    v_mov_b32_e32 v1, vcc_lo
+; GFX10-PAL-NEXT:    v_mov_b32_e32 v3, 15
+; GFX10-PAL-NEXT:    v_lshl_add_u32 v0, v0, 2, v1
+; GFX10-PAL-NEXT:    v_lshl_add_u32 v1, v2, 2, v1
+; GFX10-PAL-NEXT:    scratch_load_dword v2, off, s32 glc dlc
 ; GFX10-PAL-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-PAL-NEXT:    scratch_store_dword v0, v1, off
+; GFX10-PAL-NEXT:    scratch_store_dword v0, v3, off
 ; GFX10-PAL-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-PAL-NEXT:    scratch_load_dword v0, v2, off glc dlc
+; GFX10-PAL-NEXT:    scratch_load_dword v0, v1, off glc dlc
 ; GFX10-PAL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-PAL-NEXT:    s_setpc_b64 s[30:31]
 bb:
   %padding = alloca [64 x i32], align 4, addrspace(5)
   %i = alloca [32 x float], align 4, addrspace(5)
   %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef
   %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
   %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*

 define void @store_load_vindex_large_offset_foo(i32 %idx) {
 ; GFX9-LABEL: store_load_vindex_large_offset_foo:
 ; GFX9:       ; %bb.0: ; %bb
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    scratch_load_dword v1, off, s32 glc
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_add_i32 vcc_hi, s32, 0x4000
 ; GFX9-NEXT:    v_mov_b32_e32 v1, vcc_hi
-; GFX9-NEXT:    v_mov_b32_e32 v3, 15
 ; GFX9-NEXT:    v_lshl_add_u32 v2, v0, 2, v1
-; GFX9-NEXT:    v_and_b32_e32 v0, v0, v3
+; GFX9-NEXT:    v_mov_b32_e32 v3, 15
+; GFX9-NEXT:    v_and_b32_e32 v0, 15, v0
 ; GFX9-NEXT:    scratch_store_dword v2, v3, off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    v_lshl_add_u32 v0, v0, 2, v1
 ; GFX9-NEXT:    scratch_load_dword v0, v0, off glc
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: store_load_vindex_large_offset_foo:
 ; GFX10:       ; %bb.0: ; %bb
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_mov_b32_e32 v1, 15
 ; GFX10-NEXT:    s_add_i32 vcc_lo, s32, 0x4000
-; GFX10-NEXT:    v_mov_b32_e32 v2, vcc_lo
-; GFX10-NEXT:    v_and_b32_e32 v3, v0, v1
-; GFX10-NEXT:    v_lshl_add_u32 v0, v0, 2, v2
-; GFX10-NEXT:    v_lshl_add_u32 v2, v3, 2, v2
-; GFX10-NEXT:    scratch_load_dword v3, off, s32 glc dlc
+; GFX10-NEXT:    v_and_b32_e32 v2, 15, v0
+; GFX10-NEXT:    v_mov_b32_e32 v1, vcc_lo
+; GFX10-NEXT:    v_mov_b32_e32 v3, 15
+; GFX10-NEXT:    v_lshl_add_u32 v0, v0, 2, v1
+; GFX10-NEXT:    v_lshl_add_u32 v1, v2, 2, v1
+; GFX10-NEXT:    scratch_load_dword v2, off, s32 glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    scratch_store_dword v0, v1, off
+; GFX10-NEXT:    scratch_store_dword v0, v3, off
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    scratch_load_dword v0, v2, off glc dlc
+; GFX10-NEXT:    scratch_load_dword v0, v1, off glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-PAL-LABEL: store_load_vindex_large_offset_foo:
 ; GFX9-PAL:       ; %bb.0: ; %bb
 ; GFX9-PAL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-PAL-NEXT:    scratch_load_dword v1, off, s32 glc
 ; GFX9-PAL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-PAL-NEXT:    s_add_i32 vcc_hi, s32, 0x4000
 ; GFX9-PAL-NEXT:    v_mov_b32_e32 v1, vcc_hi
-; GFX9-PAL-NEXT:    v_mov_b32_e32 v3, 15
 ; GFX9-PAL-NEXT:    v_lshl_add_u32 v2, v0, 2, v1
-; GFX9-PAL-NEXT:    v_and_b32_e32 v0, v0, v3
+; GFX9-PAL-NEXT:    v_mov_b32_e32 v3, 15
+; GFX9-PAL-NEXT:    v_and_b32_e32 v0, 15, v0
 ; GFX9-PAL-NEXT:    scratch_store_dword v2, v3, off
 ; GFX9-PAL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-PAL-NEXT:    v_lshl_add_u32 v0, v0, 2, v1
 ; GFX9-PAL-NEXT:    scratch_load_dword v0, v0, off glc
 ; GFX9-PAL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-PAL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-PAL-LABEL: store_load_vindex_large_offset_foo:
 ; GFX10-PAL:       ; %bb.0: ; %bb
 ; GFX10-PAL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-PAL-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-PAL-NEXT:    v_mov_b32_e32 v1, 15
 ; GFX10-PAL-NEXT:    s_add_i32 vcc_lo, s32, 0x4000
-; GFX10-PAL-NEXT:    v_mov_b32_e32 v2, vcc_lo
-; GFX10-PAL-NEXT:    v_and_b32_e32 v3, v0, v1
-; GFX10-PAL-NEXT:    v_lshl_add_u32 v0, v0, 2, v2
-; GFX10-PAL-NEXT:    v_lshl_add_u32 v2, v3, 2, v2
-; GFX10-PAL-NEXT:    scratch_load_dword v3, off, s32 glc dlc
+; GFX10-PAL-NEXT:    v_and_b32_e32 v2, 15, v0
+; GFX10-PAL-NEXT:    v_mov_b32_e32 v1, vcc_lo
+; GFX10-PAL-NEXT:    v_mov_b32_e32 v3, 15
+; GFX10-PAL-NEXT:    v_lshl_add_u32 v0, v0, 2, v1
+; GFX10-PAL-NEXT:    v_lshl_add_u32 v1, v2, 2, v1
+; GFX10-PAL-NEXT:    scratch_load_dword v2, off, s32 glc dlc
 ; GFX10-PAL-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-PAL-NEXT:    scratch_store_dword v0, v1, off
+; GFX10-PAL-NEXT:    scratch_store_dword v0, v3, off
 ; GFX10-PAL-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-PAL-NEXT:    scratch_load_dword v0, v2, off glc dlc
+; GFX10-PAL-NEXT:    scratch_load_dword v0, v1, off glc dlc
 ; GFX10-PAL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-PAL-NEXT:    s_setpc_b64 s[30:31]
 bb:
   %padding = alloca [4096 x i32], align 4, addrspace(5)
   %i = alloca [32 x float], align 4, addrspace(5)
   %pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef
   %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
   %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*

llvm/test/CodeGen/AMDGPU/sdiv64.ll

 ; GCN-NEXT:    s_xor_b64 s[10:11], s[2:3], s[8:9]
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s10
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s11
 ; GCN-NEXT:    s_sub_u32 s4, 0, s10
 ; GCN-NEXT:    s_subb_u32 s5, 0, s11
 ; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
-; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    s_ashr_i32 s12, s3, 31
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v1, v1
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
+; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GCN-NEXT:    s_add_u32 s2, s2, s12
 ; GCN-NEXT:    s_mov_b32 s13, s12
-; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
-; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v2, s4, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v5, s5, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
 ; GCN-NEXT:    s_addc_u32 s3, s3, s12
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
+; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
+; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
+; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
-; GCN-NEXT:    v_mul_hi_u32 v8, v2, v3
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v5, s5, v0
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v8, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s4, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s5, v0
 ; GCN-NEXT:    s_xor_b64 s[2:3], s[2:3], s[12:13]
 ; GCN-NEXT:    s_mov_b32 s5, s1
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s2, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
-; GCN-NEXT:    v_mul_hi_u32 v5, s2, v2
-; GCN-NEXT:    v_mul_hi_u32 v6, s3, v2
-; GCN-NEXT:    v_mul_lo_u32 v2, s3, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_mul_lo_u32 v3, s4, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
+; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GCN-NEXT:    v_mul_hi_u32 v4, s2, v1
+; GCN-NEXT:    v_mul_hi_u32 v5, s3, v1
+; GCN-NEXT:    v_mul_lo_u32 v1, s3, v1
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
 ; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
 ; GCN-NEXT:    s_mov_b32 s4, s0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
 ; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
 ; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
 ; GCN-NEXT:    v_mov_b32_e32 v5, s11
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GCN-NEXT:    v_mul_lo_u32 v3, s10, v0
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s3, v2

 ; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
 ; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v2
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v6, v3
 ; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v2
 ; GCN-NEXT:    v_subb_u32_e32 v8, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v6
 ; GCN-NEXT:    v_rcp_f32_e32 v5, v5
-; GCN-NEXT:    v_mov_b32_e32 v14, 0
 ; GCN-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
 ; GCN-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
 ; GCN-NEXT:    v_trunc_f32_e32 v6, v6
 ; GCN-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v6, v6
 ; GCN-NEXT:    v_mul_hi_u32 v9, v7, v5
 ; GCN-NEXT:    v_mul_lo_u32 v10, v7, v6
 ; GCN-NEXT:    v_mul_lo_u32 v11, v8, v5
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
 ; GCN-NEXT:    v_mul_lo_u32 v10, v7, v5
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
 ; GCN-NEXT:    v_mul_lo_u32 v11, v5, v9
 ; GCN-NEXT:    v_mul_hi_u32 v12, v5, v10
 ; GCN-NEXT:    v_mul_hi_u32 v13, v5, v9
-; GCN-NEXT:    v_mul_hi_u32 v15, v6, v9
+; GCN-NEXT:    v_mul_hi_u32 v14, v6, v9
 ; GCN-NEXT:    v_mul_lo_u32 v9, v6, v9
 ; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; GCN-NEXT:    v_addc_u32_e32 v12, vcc, 0, v13, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v13, v6, v10
 ; GCN-NEXT:    v_mul_hi_u32 v10, v6, v10
 ; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
 ; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v12, v10, vcc
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v15, v14, vcc
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v14, vcc
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v10, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v9, v7, v6
 ; GCN-NEXT:    v_mul_hi_u32 v10, v7, v5
 ; GCN-NEXT:    v_mul_lo_u32 v8, v8, v5
 ; GCN-NEXT:    v_mul_lo_u32 v7, v7, v5
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_mul_lo_u32 v11, v5, v8
 ; GCN-NEXT:    v_mul_hi_u32 v12, v5, v7
 ; GCN-NEXT:    v_mul_hi_u32 v13, v5, v8
 ; GCN-NEXT:    v_mul_hi_u32 v10, v6, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, v6, v7
 ; GCN-NEXT:    v_mul_hi_u32 v9, v6, v8
 ; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; GCN-NEXT:    v_addc_u32_e32 v12, vcc, 0, v13, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v8, v6, v8
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v10, vcc
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v9, v14, vcc
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v8, vcc
 ; GCN-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
 ; GCN-NEXT:    v_xor_b32_e32 v0, v0, v7
 ; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
 ; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
 ; GCN-NEXT:    v_mul_hi_u32 v10, v0, v6
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
 ; GCN-NEXT:    v_xor_b32_e32 v1, v1, v7
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v10, v1, v5
 ; GCN-NEXT:    v_mul_hi_u32 v5, v1, v5
 ; GCN-NEXT:    v_mul_hi_u32 v11, v1, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v11, v14, vcc
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v11, vcc
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
 ; GCN-NEXT:    v_mul_hi_u32 v9, v2, v5
 ; GCN-NEXT:    v_mul_lo_u32 v10, v3, v5
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10

 ; GCN-NEXT:    s_addc_u32 s3, s3, s8
 ; GCN-NEXT:    s_xor_b64 s[2:3], s[2:3], s[8:9]
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
 ; GCN-NEXT:    s_sub_u32 s4, 0, s2
 ; GCN-NEXT:    s_subb_u32 s5, 0, s3
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
-; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v1, v1
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
+; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
-; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
-; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v2, s4, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s4, v0
 ; GCN-NEXT:    v_mul_lo_u32 v5, s5, v0
-; GCN-NEXT:    s_mov_b32 s5, s1
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v5, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
+; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v6, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v8, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s4, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s5, v0
+; GCN-NEXT:    s_mov_b32 s5, s1
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_mul_lo_u32 v3, s4, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
+; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
 ; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
 ; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
 ; GCN-NEXT:    v_mov_b32_e32 v4, s3
 ; GCN-NEXT:    s_mov_b32 s4, s0
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s3, v0

 ; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
 ; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v0
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v1
 ; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v0
 ; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
 ; GCN-NEXT:    v_rcp_f32_e32 v3, v3
-; GCN-NEXT:    v_mov_b32_e32 v12, 0
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
 ; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
 ; GCN-NEXT:    v_trunc_f32_e32 v4, v4
 ; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
 ; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
 ; GCN-NEXT:    v_mul_lo_u32 v9, v3, v7
 ; GCN-NEXT:    v_mul_hi_u32 v10, v3, v8
 ; GCN-NEXT:    v_mul_hi_u32 v11, v3, v7
-; GCN-NEXT:    v_mul_hi_u32 v13, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
 ; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v8, vcc
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v12, vcc
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v8, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v7, v5, v4
 ; GCN-NEXT:    v_mul_hi_u32 v8, v5, v3
 ; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
 ; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_mul_lo_u32 v9, v3, v6
 ; GCN-NEXT:    v_mul_hi_u32 v10, v3, v5
 ; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
 ; GCN-NEXT:    v_mul_hi_u32 v8, v4, v5
 ; GCN-NEXT:    v_mul_lo_u32 v5, v4, v5
 ; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v4, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v8, vcc
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v4, 24
 ; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
 ; GCN-NEXT:    v_mul_hi_u32 v4, v4, 24
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5

 ; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
 ; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v0
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v1
 ; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v0
 ; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
 ; GCN-NEXT:    v_rcp_f32_e32 v3, v3
-; GCN-NEXT:    v_mov_b32_e32 v12, 0
 ; GCN-NEXT:    s_mov_b32 s4, 0x8000
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
 ; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
 ; GCN-NEXT:    v_trunc_f32_e32 v4, v4
 ; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
 ; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
 ; GCN-NEXT:    v_mul_lo_u32 v9, v3, v7
 ; GCN-NEXT:    v_mul_hi_u32 v10, v3, v8
 ; GCN-NEXT:    v_mul_hi_u32 v11, v3, v7
-; GCN-NEXT:    v_mul_hi_u32 v13, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
 ; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v8, vcc
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v12, vcc
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v8, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v7, v5, v4
 ; GCN-NEXT:    v_mul_hi_u32 v8, v5, v3
 ; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
 ; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_mul_lo_u32 v9, v3, v6
 ; GCN-NEXT:    v_mul_hi_u32 v10, v3, v5
 ; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
 ; GCN-NEXT:    v_mul_hi_u32 v8, v4, v5
 ; GCN-NEXT:    v_mul_lo_u32 v5, v4, v5
 ; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v4, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v8, vcc
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
 ; GCN-NEXT:    v_lshrrev_b32_e32 v5, 17, v4
 ; GCN-NEXT:    v_lshlrev_b32_e32 v4, 15, v4
 ; GCN-NEXT:    v_lshrrev_b32_e32 v3, 17, v3
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4

llvm/test/CodeGen/AMDGPU/srem64.ll

 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
 ; GCN-NEXT:    s_sub_u32 s0, 0, s12
 ; GCN-NEXT:    s_subb_u32 s1, 0, s13
 ; GCN-NEXT:    s_mov_b32 s4, s8
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
-; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    s_mov_b32 s5, s9
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v1, v1
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
+; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
-; GCN-NEXT:    v_mul_lo_u32 v6, s1, v0
-; GCN-NEXT:    v_mul_lo_u32 v5, s0, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
+; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s10, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s10, v0
-; GCN-NEXT:    v_mul_hi_u32 v5, s10, v2
-; GCN-NEXT:    v_mul_hi_u32 v6, s11, v2
-; GCN-NEXT:    v_mul_lo_u32 v2, s11, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v5, s11, v0
-; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
+; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v6, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v8, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s1, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_mul_lo_u32 v3, s0, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
+; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
+; GCN-NEXT:    v_mul_hi_u32 v4, s10, v1
+; GCN-NEXT:    v_mul_hi_u32 v5, s11, v1
+; GCN-NEXT:    v_mul_lo_u32 v1, s11, v1
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
+; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
 ; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
 ; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
 ; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
 ; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
 ; GCN-NEXT:    v_mov_b32_e32 v3, s13

 ; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
 ; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
 ; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
 ; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; GCN-NEXT:    v_rcp_f32_e32 v4, v4
-; GCN-NEXT:    v_mov_b32_e32 v13, 0
 ; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v5, v5
 ; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
 ; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
 ; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
 ; GCN-NEXT:    v_mul_lo_u32 v10, v4, v8
 ; GCN-NEXT:    v_mul_hi_u32 v11, v4, v9
 ; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v14, v5, v8
+; GCN-NEXT:    v_mul_hi_u32 v13, v5, v8
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
 ; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
 ; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
 ; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v13, vcc
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v13, vcc
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v9, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
 ; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GCN-NEXT:    v_mul_lo_u32 v10, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v11, v4, v6
 ; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v9, v5, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v5, v6
 ; GCN-NEXT:    v_mul_hi_u32 v8, v5, v7
 ; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v7, v5, v7
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v8, v13, vcc
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
 ; GCN-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
 ; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
 ; GCN-NEXT:    v_mul_lo_u32 v7, v0, v5
 ; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
 ; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v9, v1, v4
 ; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GCN-NEXT:    v_mul_hi_u32 v10, v1, v5
 ; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v10, v13, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v10, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
 ; GCN-NEXT:    v_mul_hi_u32 v7, v2, v4
 ; GCN-NEXT:    v_mul_lo_u32 v8, v3, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
; GCN-IR-NEXT:    s_endpgm
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 ; 33 known sign bits
 define amdgpu_kernel void @s_test_srem33_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_srem33_64:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GCN-NEXT:    v_mov_b32_e32 v6, 0
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    s_mov_b32 s11, 0xf000
+; GCN-NEXT:    s_mov_b32 s10, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_ashr_i64 s[2:3], s[10:11], 31
-; GCN-NEXT:    s_ashr_i64 s[4:5], s[0:1], 31
+; GCN-NEXT:    s_ashr_i64 s[2:3], s[6:7], 31
+; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 31
 ; GCN-NEXT:    s_ashr_i32 s0, s1, 31
-; GCN-NEXT:    s_add_u32 s4, s4, s0
+; GCN-NEXT:    s_add_u32 s8, s8, s0
 ; GCN-NEXT:    s_mov_b32 s1, s0
-; GCN-NEXT:    s_addc_u32 s5, s5, s0
-; GCN-NEXT:    s_xor_b64 s[12:13], s[4:5], s[0:1]
+; GCN-NEXT:    s_addc_u32 s9, s9, s0
+; GCN-NEXT:    s_xor_b64 s[12:13], s[8:9], s[0:1]
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
 ; GCN-NEXT:    s_sub_u32 s0, 0, s12
 ; GCN-NEXT:    s_subb_u32 s1, 0, s13
-; GCN-NEXT:    s_ashr_i32 s10, s11, 31
+; GCN-NEXT:    s_ashr_i32 s6, s7, 31
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
-; GCN-NEXT:    s_mov_b32 s11, s10
-; GCN-NEXT:    s_mov_b32 s4, s8
-; GCN-NEXT:    s_mov_b32 s5, s9
+; GCN-NEXT:    s_mov_b32 s7, s6
+; GCN-NEXT:    s_mov_b32 s8, s4
+; GCN-NEXT:    s_mov_b32 s9, s5
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GCN-NEXT:    v_trunc_f32_e32 v1, v1
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
 ; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
 ; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
 ; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GCN-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
-; GCN-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
+; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
 ; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
 ; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GCN-NEXT:    v_mul_lo_u32 v4, s1, v0
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GCN-NEXT:    v_mul_lo_u32 v3, s0, v0
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
-; GCN-NEXT:    v_mul_lo_u32 v7, v0, v2
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v9, v0, v2
+; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v8, v0, v2
 ; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
 ; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v5, vcc
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GCN-NEXT:    s_add_u32 s0, s2, s10
+; GCN-NEXT:    s_add_u32 s0, s2, s6
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT:    s_addc_u32 s1, s3, s10
+; GCN-NEXT:    s_addc_u32 s1, s3, s6
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GCN-NEXT:    s_xor_b64 s[14:15], s[0:1], s[10:11]
+; GCN-NEXT:    s_xor_b64 s[14:15], s[0:1], s[6:7]
 ; GCN-NEXT:    v_mul_lo_u32 v2, s14, v1
 ; GCN-NEXT:    v_mul_hi_u32 v3, s14, v0
 ; GCN-NEXT:    v_mul_hi_u32 v4, s14, v1
 ; GCN-NEXT:    v_mul_hi_u32 v5, s15, v1
 ; GCN-NEXT:    v_mul_lo_u32 v1, s15, v1
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, s15, v0
 ; GCN-NEXT:    v_mul_hi_u32 v0, s15, v0
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v6, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
 ; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
 ; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
 ; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3

 ; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
 ; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT:    v_xor_b32_e32 v0, s10, v0
-; GCN-NEXT:    v_xor_b32_e32 v1, s10, v1
-; GCN-NEXT:    v_mov_b32_e32 v2, s10
-; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s10, v0
+; GCN-NEXT:    v_xor_b32_e32 v0, s6, v0
+; GCN-NEXT:    v_xor_b32_e32 v1, s6, v1
+; GCN-NEXT:    v_mov_b32_e32 v2, s6
+; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s6, v0
 ; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_srem33_64:
 ; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
 ; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[6:7], 31

 ; GCN-NEXT:    s_xor_b64 s[8:9], s[2:3], s[4:5]
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
 ; GCN-NEXT:    s_sub_u32 s2, 0, s8
 ; GCN-NEXT:    s_subb_u32 s3, 0, s9
 ; GCN-NEXT:    s_mov_b32 s4, s0
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
-; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    s_mov_b32 s5, s1
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v1, v1
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
+; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_lo_u32 v3, s2, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v6, s3, v0
-; GCN-NEXT:    v_mul_lo_u32 v5, s2, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
-; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s2, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
+; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
 ; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-NEXT:    v_mul_lo_u32 v4, s2, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v5, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
+; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v6, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v8, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_mul_lo_u32 v3, s2, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
+; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
 ; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
 ; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
 ; GCN-NEXT:    v_mov_b32_e32 v3, s9
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s9, v0
 ; GCN-NEXT:    v_mul_hi_u32 v2, s8, v0

 ; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
 ; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
 ; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
 ; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
 ; GCN-NEXT:    v_rcp_f32_e32 v2, v2
-; GCN-NEXT:    v_mov_b32_e32 v11, 0
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v3, v3
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
 ; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
 ; GCN-NEXT:    v_mul_hi_u32 v9, v2, v7
 ; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
 ; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v11, vcc
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v11, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
 ; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
 ; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
 ; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
 ; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
 ; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
 ; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
 ; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v11, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
 ; GCN-NEXT:    v_mul_hi_u32 v2, v2, 24
 ; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4

 ; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
 ; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
 ; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
 ; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
 ; GCN-NEXT:    v_rcp_f32_e32 v2, v2
-; GCN-NEXT:    v_mov_b32_e32 v11, 0
 ; GCN-NEXT:    s_mov_b32 s4, 0x8000
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v3, v3
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
 ; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
 ; GCN-NEXT:    v_mul_hi_u32 v9, v2, v7
 ; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
 ; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v11, vcc
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v11, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
 ; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
 ; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
 ; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
 ; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
 ; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
 ; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
 ; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v11, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
 ; GCN-NEXT:    v_lshrrev_b32_e32 v4, 17, v3
 ; GCN-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
 ; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3

llvm/test/CodeGen/AMDGPU/stack-realign.ll

 }
 
 ; GCN-LABEL: {{^}}needs_align16_stack_align4:
 ; GCN: s_add_i32 [[SCRATCH_REG:s[0-9]+]], s32, 0x3c0{{$}}
 ; GCN: s_and_b32 s33, [[SCRATCH_REG]], 0xfffffc00
 
 ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
 ; GCN: v_or_b32_e32 v{{[0-9]+}}, 12
-; GCN: s_addk_i32 s32, 0x2800{{$}}
 ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
+; GCN: s_addk_i32 s32, 0x2800{{$}}
 ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
 ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
 
 ; GCN: s_addk_i32 s32, 0xd800
 
 ; GCN: ; ScratchSize: 160
 define void @needs_align16_stack_align4(i32 %idx) #2 {
   %alloca.align16 = alloca [8 x <4 x i32>], align 16, addrspace(5)
   %gep0 = getelementptr inbounds [8 x <4 x i32>], [8 x <4 x i32>] addrspace(5)* %alloca.align16, i32 0, i32 %idx
   store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %gep0, align 16
   ret void
 }
 
 ; GCN-LABEL: {{^}}needs_align32:
 ; GCN: s_add_i32 [[SCRATCH_REG:s[0-9]+]], s32, 0x7c0{{$}}
 ; GCN: s_and_b32 s33, [[SCRATCH_REG]], 0xfffff800
 
 ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
 ; GCN: v_or_b32_e32 v{{[0-9]+}}, 12
-; GCN: s_addk_i32 s32, 0x3000{{$}}
 ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
+; GCN: s_addk_i32 s32, 0x3000{{$}}
 ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
 ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
 
 ; GCN: s_addk_i32 s32, 0xd000
 
 ; GCN: ; ScratchSize: 192
 define void @needs_align32(i32 %idx) #0 {
   %alloca.align16 = alloca [8 x <4 x i32>], align 32, addrspace(5)

llvm/test/CodeGen/AMDGPU/udiv.ll

 define i64 @v_test_udiv64_mulhi_fold(i64 %arg) {
 ; SI-LABEL: v_test_udiv64_mulhi_fold:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; SI-NEXT:    v_madak_f32 v2, 0, v2, 0x47c35000
 ; SI-NEXT:    v_rcp_f32_e32 v2, v2
 ; SI-NEXT:    s_mov_b32 s4, 0xfffe7960
-; SI-NEXT:    v_mov_b32_e32 v9, 0
 ; SI-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
 ; SI-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
 ; SI-NEXT:    v_trunc_f32_e32 v3, v3
 ; SI-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; SI-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; SI-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; SI-NEXT:    v_mul_hi_u32 v4, v2, s4
 ; SI-NEXT:    v_mul_lo_u32 v5, v3, s4
 ; SI-NEXT:    v_mul_lo_u32 v6, v2, s4
 ; SI-NEXT:    v_subrev_i32_e32 v4, vcc, v2, v4
 ; SI-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; SI-NEXT:    v_mul_lo_u32 v5, v2, v4
-; SI-NEXT:    v_mul_hi_u32 v7, v2, v6
+; SI-NEXT:    v_mul_hi_u32 v5, v2, v6
+; SI-NEXT:    v_mul_lo_u32 v7, v2, v4
 ; SI-NEXT:    v_mul_hi_u32 v8, v2, v4
-; SI-NEXT:    v_mul_hi_u32 v10, v3, v4
+; SI-NEXT:    v_mul_hi_u32 v9, v3, v4
 ; SI-NEXT:    v_mul_lo_u32 v4, v3, v4
-; SI-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; SI-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
 ; SI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; SI-NEXT:    v_mul_lo_u32 v8, v3, v6
 ; SI-NEXT:    v_mul_hi_u32 v6, v3, v6
 ; SI-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
 ; SI-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; SI-NEXT:    v_addc_u32_e32 v6, vcc, v10, v9, vcc
+; SI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v9, vcc
 ; SI-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; SI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; SI-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; SI-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
 ; SI-NEXT:    v_mul_hi_u32 v4, v2, s4
 ; SI-NEXT:    v_mul_lo_u32 v5, v3, s4
 ; SI-NEXT:    v_mul_lo_u32 v6, v2, s4
 ; SI-NEXT:    s_mov_b32 s4, 0x186a0
 ; SI-NEXT:    v_subrev_i32_e32 v4, vcc, v2, v4
 ; SI-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; SI-NEXT:    v_mul_lo_u32 v5, v2, v4
 ; SI-NEXT:    v_mul_hi_u32 v7, v2, v6
 ; SI-NEXT:    v_mul_hi_u32 v8, v2, v4
-; SI-NEXT:    v_mul_hi_u32 v10, v3, v4
+; SI-NEXT:    v_mul_hi_u32 v9, v3, v4
 ; SI-NEXT:    v_mul_lo_u32 v4, v3, v4
 ; SI-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
 ; SI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; SI-NEXT:    v_mul_lo_u32 v8, v3, v6
 ; SI-NEXT:    v_mul_hi_u32 v6, v3, v6
 ; SI-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
 ; SI-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; SI-NEXT:    v_addc_u32_e32 v6, vcc, v10, v9, vcc
+; SI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v9, vcc
 ; SI-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; SI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; SI-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; SI-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
 ; SI-NEXT:    v_mul_lo_u32 v4, v0, v3
 ; SI-NEXT:    v_mul_hi_u32 v5, v0, v2
 ; SI-NEXT:    v_mul_hi_u32 v6, v0, v3
 ; SI-NEXT:    v_mul_hi_u32 v7, v1, v3
 ; SI-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; SI-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; SI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; SI-NEXT:    v_mul_lo_u32 v6, v1, v2
 ; SI-NEXT:    v_mul_hi_u32 v2, v1, v2
 ; SI-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; SI-NEXT:    v_addc_u32_e32 v2, vcc, v5, v2, vcc
-; SI-NEXT:    v_addc_u32_e32 v4, vcc, v7, v9, vcc
+; SI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; SI-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; SI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; SI-NEXT:    v_mul_lo_u32 v4, v3, s4
 ; SI-NEXT:    v_mul_hi_u32 v5, v2, s4
 ; SI-NEXT:    v_mul_lo_u32 v6, v2, s4
 ; SI-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; SI-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
 ; SI-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc

 ;
 ; VI-LABEL: v_test_udiv64_mulhi_fold:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; VI-NEXT:    v_madak_f32 v2, 0, v2, 0x47c35000
 ; VI-NEXT:    v_rcp_f32_e32 v2, v2
 ; VI-NEXT:    s_mov_b32 s4, 0xfffe7960
-; VI-NEXT:    v_mov_b32_e32 v9, 0
 ; VI-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
 ; VI-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
 ; VI-NEXT:    v_trunc_f32_e32 v3, v3
 ; VI-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; VI-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; VI-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; VI-NEXT:    v_mul_hi_u32 v4, v2, s4
 ; VI-NEXT:    v_mul_lo_u32 v5, v3, s4
 ; VI-NEXT:    v_mul_lo_u32 v6, v2, s4
 ; VI-NEXT:    v_subrev_u32_e32 v4, vcc, v2, v4
 ; VI-NEXT:    v_add_u32_e32 v4, vcc, v5, v4
-; VI-NEXT:    v_mul_lo_u32 v5, v2, v4
-; VI-NEXT:    v_mul_hi_u32 v7, v2, v6
+; VI-NEXT:    v_mul_hi_u32 v5, v2, v6
+; VI-NEXT:    v_mul_lo_u32 v7, v2, v4
 ; VI-NEXT:    v_mul_hi_u32 v8, v2, v4
-; VI-NEXT:    v_mul_hi_u32 v10, v3, v4
+; VI-NEXT:    v_mul_hi_u32 v9, v3, v4
 ; VI-NEXT:    v_mul_lo_u32 v4, v3, v4
-; VI-NEXT:    v_add_u32_e32 v5, vcc, v7, v5
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v5, v7
 ; VI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; VI-NEXT:    v_mul_lo_u32 v8, v3, v6
 ; VI-NEXT:    v_mul_hi_u32 v6, v3, v6
 ; VI-NEXT:    v_add_u32_e32 v5, vcc, v5, v8
 ; VI-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; VI-NEXT:    v_addc_u32_e32 v6, vcc, v10, v9, vcc
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v9, vcc
 ; VI-NEXT:    v_add_u32_e32 v4, vcc, v5, v4
 ; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v4
 ; VI-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
 ; VI-NEXT:    v_mul_hi_u32 v4, v2, s4
 ; VI-NEXT:    v_mul_lo_u32 v5, v3, s4
 ; VI-NEXT:    v_mul_lo_u32 v6, v2, s4
 ; VI-NEXT:    s_mov_b32 s4, 0x186a0
 ; VI-NEXT:    v_subrev_u32_e32 v4, vcc, v2, v4
 ; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v5
 ; VI-NEXT:    v_mul_lo_u32 v5, v2, v4
 ; VI-NEXT:    v_mul_hi_u32 v7, v2, v6
 ; VI-NEXT:    v_mul_hi_u32 v8, v2, v4
-; VI-NEXT:    v_mul_hi_u32 v10, v3, v4
+; VI-NEXT:    v_mul_hi_u32 v9, v3, v4
 ; VI-NEXT:    v_mul_lo_u32 v4, v3, v4
 ; VI-NEXT:    v_add_u32_e32 v5, vcc, v7, v5
 ; VI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; VI-NEXT:    v_mul_lo_u32 v8, v3, v6
 ; VI-NEXT:    v_mul_hi_u32 v6, v3, v6
 ; VI-NEXT:    v_add_u32_e32 v5, vcc, v5, v8
 ; VI-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; VI-NEXT:    v_addc_u32_e32 v6, vcc, v10, v9, vcc
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v9, vcc
 ; VI-NEXT:    v_add_u32_e32 v4, vcc, v5, v4
 ; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v4
 ; VI-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
 ; VI-NEXT:    v_mul_lo_u32 v4, v0, v3
 ; VI-NEXT:    v_mul_hi_u32 v5, v0, v2
 ; VI-NEXT:    v_mul_hi_u32 v6, v0, v3
 ; VI-NEXT:    v_mul_hi_u32 v7, v1, v3
 ; VI-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; VI-NEXT:    v_add_u32_e32 v4, vcc, v5, v4
 ; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mul_lo_u32 v6, v1, v2
 ; VI-NEXT:    v_mul_hi_u32 v2, v1, v2
 ; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v6
 ; VI-NEXT:    v_addc_u32_e32 v2, vcc, v5, v2, vcc
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, v7, v9, vcc
+; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v3
 ; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; VI-NEXT:    v_mul_lo_u32 v4, v3, s4
 ; VI-NEXT:    v_mul_hi_u32 v5, v2, s4
 ; VI-NEXT:    v_mul_lo_u32 v6, v2, s4
 ; VI-NEXT:    v_add_u32_e32 v4, vcc, v5, v4
 ; VI-NEXT:    v_sub_u32_e32 v0, vcc, v0, v6
 ; VI-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc

 ;
 ; GCN-LABEL: v_test_udiv64_mulhi_fold:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; GCN-NEXT:    v_madak_f32 v2, 0, v2, 0x47c35000
 ; GCN-NEXT:    v_rcp_f32_e32 v2, v2
 ; GCN-NEXT:    s_mov_b32 s4, 0xfffe7960
-; GCN-NEXT:    v_mov_b32_e32 v9, 0
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v3, v3
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_mul_hi_u32 v4, v2, s4
 ; GCN-NEXT:    v_mul_lo_u32 v5, v3, s4
 ; GCN-NEXT:    v_mul_lo_u32 v6, v2, s4
 ; GCN-NEXT:    v_subrev_u32_e32 v4, vcc, v2, v4
 ; GCN-NEXT:    v_add_u32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_mul_lo_u32 v5, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
+; GCN-NEXT:    v_mul_hi_u32 v5, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
 ; GCN-NEXT:    v_mul_hi_u32 v8, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
+; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
-; GCN-NEXT:    v_add_u32_e32 v5, vcc, v7, v5
+; GCN-NEXT:    v_add_u32_e32 v5, vcc, v5, v7
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
 ; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
 ; GCN-NEXT:    v_add_u32_e32 v5, vcc, v5, v8
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v9, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v9, vcc
 ; GCN-NEXT:    v_add_u32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_add_u32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
 ; GCN-NEXT:    v_mul_hi_u32 v4, v2, s4
 ; GCN-NEXT:    v_mul_lo_u32 v5, v3, s4
 ; GCN-NEXT:    v_mul_lo_u32 v6, v2, s4
 ; GCN-NEXT:    s_mov_b32 s4, 0x186a0
 ; GCN-NEXT:    v_subrev_u32_e32 v4, vcc, v2, v4
 ; GCN-NEXT:    v_add_u32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_mul_lo_u32 v5, v2, v4
 ; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
 ; GCN-NEXT:    v_mul_hi_u32 v8, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
+; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
 ; GCN-NEXT:    v_add_u32_e32 v5, vcc, v7, v5
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
 ; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
 ; GCN-NEXT:    v_add_u32_e32 v5, vcc, v5, v8
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v9, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v9, vcc
 ; GCN-NEXT:    v_add_u32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_add_u32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v0, v3
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v2
 ; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
 ; GCN-NEXT:    v_mul_hi_u32 v7, v1, v3
 ; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GCN-NEXT:    v_add_u32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v1, v2
 ; GCN-NEXT:    v_mul_hi_u32 v2, v1, v2
 ; GCN-NEXT:    v_add_u32_e32 v4, vcc, v4, v6
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v2, vcc
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v9, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; GCN-NEXT:    v_add_u32_e32 v2, vcc, v2, v3
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, s4
 ; GCN-NEXT:    v_mul_hi_u32 v5, v2, s4
 ; GCN-NEXT:    v_mul_lo_u32 v6, v2, s4
 ; GCN-NEXT:    v_add_u32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_sub_u32_e32 v0, vcc, v0, v6
 ; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc

llvm/test/CodeGen/AMDGPU/udiv64.ll

 ; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
 ; GCN-NEXT:    s_sub_u32 s4, 0, s8
 ; GCN-NEXT:    s_subb_u32 s5, 0, s9
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
-; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v1, v1
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
+; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
-; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v2, s4, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s4, v0
 ; GCN-NEXT:    v_mul_lo_u32 v5, s5, v0
-; GCN-NEXT:    s_mov_b32 s5, s1
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s2, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
-; GCN-NEXT:    v_mul_hi_u32 v5, s2, v2
-; GCN-NEXT:    v_mul_hi_u32 v6, s3, v2
-; GCN-NEXT:    v_mul_lo_u32 v2, s3, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
-; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
-; GCN-NEXT:    s_mov_b32 s4, s0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
+; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v6, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v8, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s4, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s5, v0
+; GCN-NEXT:    s_mov_b32 s5, s1
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_mul_lo_u32 v3, s4, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
+; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GCN-NEXT:    v_mul_hi_u32 v4, s2, v1
+; GCN-NEXT:    v_mul_hi_u32 v5, s3, v1
+; GCN-NEXT:    v_mul_lo_u32 v1, s3, v1
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
+; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
+; GCN-NEXT:    s_mov_b32 s4, s0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v2, s8, v1
 ; GCN-NEXT:    v_mul_hi_u32 v3, s8, v0
 ; GCN-NEXT:    v_mul_lo_u32 v4, s9, v0
 ; GCN-NEXT:    v_mov_b32_e32 v5, s9
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GCN-NEXT:    v_mul_lo_u32 v3, s8, v0
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s3, v2

 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
 ; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
 ; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; GCN-NEXT:    v_rcp_f32_e32 v4, v4
-; GCN-NEXT:    v_mov_b32_e32 v13, 0
 ; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v5, v5
 ; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
 ; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
 ; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
 ; GCN-NEXT:    v_mul_lo_u32 v10, v4, v8
 ; GCN-NEXT:    v_mul_hi_u32 v11, v4, v9
 ; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v14, v5, v8
+; GCN-NEXT:    v_mul_hi_u32 v13, v5, v8
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
 ; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
 ; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
 ; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v13, vcc
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v13, vcc
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v9, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
 ; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GCN-NEXT:    v_mul_lo_u32 v10, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v11, v4, v6
 ; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v9, v5, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v5, v6
 ; GCN-NEXT:    v_mul_hi_u32 v8, v5, v7
 ; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v7, v5, v7
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v8, v13, vcc
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v0, v5
 ; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v8, v0, v5
 ; GCN-NEXT:    v_mul_hi_u32 v9, v1, v5
 ; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v8, v1, v4
 ; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v4, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v13, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v9, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v2, v5
 ; GCN-NEXT:    v_mul_hi_u32 v7, v2, v4
 ; GCN-NEXT:    v_mul_lo_u32 v8, v3, v4
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8

 ; GCN-NEXT:    s_and_b32 s2, s2, s7
 ; GCN-NEXT:    s_and_b32 s3, s3, s6
 ; GCN-NEXT:    v_mov_b32_e32 v0, s2
 ; GCN-NEXT:    v_alignbit_b32 v0, s3, v0, 24
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
 ; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GCN-NEXT:    s_load_dword s8, s[0:1], 0xb
 ; GCN-NEXT:    s_load_dword s0, s[0:1], 0xc
-; GCN-NEXT:    v_mov_b32_e32 v8, 0
 ; GCN-NEXT:    v_mac_f32_e32 v1, 0x4f800000, v2
 ; GCN-NEXT:    v_rcp_f32_e32 v1, v1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_and_b32 s6, s0, s6
+; GCN-NEXT:    s_and_b32 s9, s0, s6
 ; GCN-NEXT:    s_and_b32 s8, s8, s7
 ; GCN-NEXT:    s_lshr_b64 s[0:1], s[2:3], 24
 ; GCN-NEXT:    v_mul_f32_e32 v1, 0x5f7ffffc, v1
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v1
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_mac_f32_e32 v1, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    s_sub_u32 s0, 0, s0
 ; GCN-NEXT:    s_subb_u32 s1, 0, s1
 ; GCN-NEXT:    v_mul_hi_u32 v3, s0, v1
 ; GCN-NEXT:    v_mul_lo_u32 v4, s0, v2
 ; GCN-NEXT:    v_mul_lo_u32 v5, s1, v1
 ; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, s0, v1
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GCN-NEXT:    v_mul_lo_u32 v5, v1, v3
 ; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
 ; GCN-NEXT:    v_mul_hi_u32 v7, v1, v3
-; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v3
 ; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
 ; GCN-NEXT:    v_mul_hi_u32 v4, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v4, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
 ; GCN-NEXT:    v_mul_hi_u32 v4, s0, v1
 ; GCN-NEXT:    v_mul_lo_u32 v5, s1, v1
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-NEXT:    v_mul_lo_u32 v4, s0, v1
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
 ; GCN-NEXT:    v_mul_lo_u32 v7, v1, v3
-; GCN-NEXT:    v_mul_hi_u32 v9, v1, v4
-; GCN-NEXT:    v_mul_hi_u32 v10, v1, v3
+; GCN-NEXT:    v_mul_hi_u32 v8, v1, v4
+; GCN-NEXT:    v_mul_hi_u32 v9, v1, v3
 ; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
 ; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
 ; GCN-NEXT:    v_mov_b32_e32 v3, s8
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
-; GCN-NEXT:    v_alignbit_b32 v3, s6, v3, 24
+; GCN-NEXT:    v_alignbit_b32 v3, s9, v3, 24
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, v2
 ; GCN-NEXT:    v_mul_hi_u32 v1, v3, v1
 ; GCN-NEXT:    v_mul_hi_u32 v2, v3, v2
-; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_mov_b32_e32 v5, 0
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, 0, v1
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, 0, v1
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
 ; GCN-NEXT:    v_mul_hi_u32 v7, v0, v1
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, 2, v1
 ; GCN-NEXT:    v_mul_lo_u32 v10, v0, v1
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v2, vcc
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, 1, v1

 ; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
 ; GCN-NEXT:    s_sub_u32 s4, 0, s2
 ; GCN-NEXT:    s_subb_u32 s5, 0, s3
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
-; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v1, v1
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
+; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
-; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
-; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v2, s4, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s4, v0
 ; GCN-NEXT:    v_mul_lo_u32 v5, s5, v0
-; GCN-NEXT:    s_mov_b32 s5, s1
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v5, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
+; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v6, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v8, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s4, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s5, v0
+; GCN-NEXT:    s_mov_b32 s5, s1
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_mul_lo_u32 v3, s4, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
+; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
 ; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
 ; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
 ; GCN-NEXT:    v_mov_b32_e32 v4, s3
 ; GCN-NEXT:    s_mov_b32 s4, s0
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s3, v0

 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
 ; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
 ; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
 ; GCN-NEXT:    v_rcp_f32_e32 v2, v2
-; GCN-NEXT:    v_mov_b32_e32 v11, 0
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v3, v3
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
 ; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
 ; GCN-NEXT:    v_mul_lo_u32 v9, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GCN-NEXT:    v_mul_lo_u32 v7, v2, v6
 ; GCN-NEXT:    v_mul_hi_u32 v8, v2, v9
 ; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v10, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v10, v3, v9
 ; GCN-NEXT:    v_mul_hi_u32 v9, v3, v9
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v11, vcc
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v11, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
 ; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
 ; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
 ; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
 ; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
 ; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
 ; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
 ; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v11, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v3, v5, vcc
 ; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
 ; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
 ; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3

 
 define amdgpu_kernel void @s_test_udiv_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
 ; GCN-LABEL: s_test_udiv_k_den_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    s_movk_i32 s4, 0xffe8
-; GCN-NEXT:    v_mov_b32_e32 v7, 0
 ; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GCN-NEXT:    v_trunc_f32_e32 v1, v1
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    s_mov_b32 s5, s1
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    v_mul_hi_u32 v2, v0, s4
-; GCN-NEXT:    v_mul_lo_u32 v3, v1, s4
-; GCN-NEXT:    v_mul_lo_u32 v4, v0, s4
 ; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_mul_hi_u32 v2, v0, s4
+; GCN-NEXT:    v_mul_lo_u32 v4, v1, s4
+; GCN-NEXT:    v_mul_lo_u32 v3, v0, s4
 ; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_mul_lo_u32 v3, v0, v2
-; GCN-NEXT:    v_mul_hi_u32 v5, v0, v4
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, v0, v3
+; GCN-NEXT:    v_mul_lo_u32 v4, v0, v2
 ; GCN-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
-; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
+; GCN-NEXT:    v_mul_lo_u32 v6, v1, v3
+; GCN-NEXT:    v_mul_hi_u32 v3, v1, v3
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GCN-NEXT:    v_mul_hi_u32 v2, v0, s4
 ; GCN-NEXT:    v_mul_lo_u32 v3, v1, s4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v0, s4
 ; GCN-NEXT:    s_mov_b32 s4, s0
 ; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; GCN-NEXT:    v_mul_lo_u32 v3, v0, v2
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
 ; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
 ; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
 ; GCN-NEXT:    v_mul_hi_u32 v4, s2, v1
 ; GCN-NEXT:    v_mul_hi_u32 v5, s3, v1
 ; GCN-NEXT:    v_mul_lo_u32 v1, s3, v1
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
 ; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v1, 24
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, 24
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, 2, v0
 ; GCN-NEXT:    v_mul_lo_u32 v8, v0, 24
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, 1, v0

 define i64 @v_test_udiv_k_den_i64(i64 %x) {
 ; GCN-LABEL: v_test_udiv_k_den_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; GCN-NEXT:    v_madak_f32 v2, 0, v2, 0x41c00000
 ; GCN-NEXT:    v_rcp_f32_e32 v2, v2
 ; GCN-NEXT:    s_movk_i32 s4, 0xffe8
-; GCN-NEXT:    v_mov_b32_e32 v9, 0
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v3, v3
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_mul_hi_u32 v4, v2, s4
 ; GCN-NEXT:    v_mul_lo_u32 v5, v3, s4
 ; GCN-NEXT:    v_mul_lo_u32 v6, v2, s4
 ; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_mul_lo_u32 v5, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
+; GCN-NEXT:    v_mul_hi_u32 v5, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
 ; GCN-NEXT:    v_mul_hi_u32 v8, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
+; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
 ; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v9, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v9, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
 ; GCN-NEXT:    v_mul_hi_u32 v4, v2, s4
 ; GCN-NEXT:    v_mul_lo_u32 v5, v3, s4
 ; GCN-NEXT:    v_mul_lo_u32 v6, v2, s4
 ; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_mul_lo_u32 v5, v2, v4
 ; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
 ; GCN-NEXT:    v_mul_hi_u32 v8, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
+; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
 ; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v9, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v9, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v0, v3
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v2
 ; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
 ; GCN-NEXT:    v_mul_hi_u32 v7, v1, v3
 ; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v1, v2
 ; GCN-NEXT:    v_mul_hi_u32 v2, v1, v2
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v2, vcc
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v9, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
 ; GCN-NEXT:    v_mul_hi_u32 v5, v2, 24
 ; GCN-NEXT:    v_mul_lo_u32 v6, v2, 24
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
 ; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc

llvm/test/CodeGen/AMDGPU/urem64.ll

 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
 ; GCN-NEXT:    s_sub_u32 s0, 0, s12
 ; GCN-NEXT:    s_subb_u32 s1, 0, s13
 ; GCN-NEXT:    s_mov_b32 s4, s8
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
-; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    s_mov_b32 s5, s9
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v1, v1
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
+; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
-; GCN-NEXT:    v_mul_lo_u32 v6, s1, v0
-; GCN-NEXT:    v_mul_lo_u32 v5, s0, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
+; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s10, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s10, v0
-; GCN-NEXT:    v_mul_hi_u32 v5, s10, v2
-; GCN-NEXT:    v_mul_hi_u32 v6, s11, v2
-; GCN-NEXT:    v_mul_lo_u32 v2, s11, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v5, s11, v0
-; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
+; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v6, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v8, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s1, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_mul_lo_u32 v3, s0, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
+; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
+; GCN-NEXT:    v_mul_hi_u32 v4, s10, v1
+; GCN-NEXT:    v_mul_hi_u32 v5, s11, v1
+; GCN-NEXT:    v_mul_lo_u32 v1, s11, v1
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
+; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
 ; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
 ; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
 ; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
 ; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
 ; GCN-NEXT:    v_mov_b32_e32 v3, s13

 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
 ; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
 ; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; GCN-NEXT:    v_rcp_f32_e32 v4, v4
-; GCN-NEXT:    v_mov_b32_e32 v13, 0
 ; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v5, v5
 ; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
 ; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
 ; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
 ; GCN-NEXT:    v_mul_lo_u32 v10, v4, v8
 ; GCN-NEXT:    v_mul_hi_u32 v11, v4, v9
 ; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v14, v5, v8
+; GCN-NEXT:    v_mul_hi_u32 v13, v5, v8
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
 ; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
 ; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
 ; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v13, vcc
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v13, vcc
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v9, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
 ; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GCN-NEXT:    v_mul_lo_u32 v10, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v11, v4, v6
 ; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v9, v5, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v5, v6
 ; GCN-NEXT:    v_mul_hi_u32 v8, v5, v7
 ; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v7, v5, v7
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v8, v13, vcc
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v0, v5
 ; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v8, v0, v5
 ; GCN-NEXT:    v_mul_hi_u32 v9, v1, v5
 ; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v8, v1, v4
 ; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v4, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v13, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v9, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
 ; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
 ; GCN-NEXT:    v_mul_lo_u32 v7, v3, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7

 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s6
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s7
 ; GCN-NEXT:    s_sub_u32 s0, 0, s6
 ; GCN-NEXT:    s_subb_u32 s1, 0, s7
 ; GCN-NEXT:    s_mov_b32 s8, s4
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
-; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    s_mov_b32 s9, s5
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v1, v1
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
+; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
-; GCN-NEXT:    v_mul_lo_u32 v6, s1, v0
-; GCN-NEXT:    v_mul_lo_u32 v5, s0, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
-; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
+; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v5, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
+; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v6, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v8, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s1, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_mul_lo_u32 v3, s0, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
+; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
 ; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
 ; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
 ; GCN-NEXT:    v_mov_b32_e32 v3, s7
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s7, v0
 ; GCN-NEXT:    v_mul_hi_u32 v2, s6, v0

 
 define amdgpu_kernel void @s_test_urem_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
 ; GCN-LABEL: s_test_urem_k_den_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    s_movk_i32 s4, 0xffe8
-; GCN-NEXT:    v_mov_b32_e32 v2, 0
 ; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GCN-NEXT:    v_trunc_f32_e32 v1, v1
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    s_mov_b32 s5, s1
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    v_mul_hi_u32 v3, v0, s4
-; GCN-NEXT:    v_mul_lo_u32 v5, v1, s4
-; GCN-NEXT:    v_mul_lo_u32 v4, v0, s4
 ; GCN-NEXT:    s_mov_b32 s6, -1
-; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, v0, v3
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, v0, v4
-; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v1, v3
-; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
-; GCN-NEXT:    v_mul_lo_u32 v7, v1, v4
-; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v4, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v2, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
-; GCN-NEXT:    v_mul_hi_u32 v3, v0, s4
+; GCN-NEXT:    v_mul_hi_u32 v2, v0, s4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v1, s4
-; GCN-NEXT:    v_mul_lo_u32 v5, v0, s4
+; GCN-NEXT:    v_mul_lo_u32 v3, v0, s4
+; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, v0, v3
+; GCN-NEXT:    v_mul_lo_u32 v4, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v1, v2
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
+; GCN-NEXT:    v_mul_lo_u32 v6, v1, v3
+; GCN-NEXT:    v_mul_hi_u32 v3, v1, v3
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT:    v_mul_hi_u32 v2, v0, s4
+; GCN-NEXT:    v_mul_lo_u32 v3, v1, s4
+; GCN-NEXT:    v_mul_lo_u32 v4, v0, s4
 ; GCN-NEXT:    s_mov_b32 s4, s0
-; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, v0, v3
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, v0, v5
-; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v1, v3
-; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
-; GCN-NEXT:    v_mul_lo_u32 v7, v1, v5
-; GCN-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v2, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s2, v1
-; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
-; GCN-NEXT:    v_mul_hi_u32 v5, s2, v1
-; GCN-NEXT:    v_mul_hi_u32 v6, s3, v1
+; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
+; GCN-NEXT:    v_mul_lo_u32 v3, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, v0, v4
+; GCN-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, v1, v2
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
+; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
+; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GCN-NEXT:    v_mul_hi_u32 v4, s2, v1
+; GCN-NEXT:    v_mul_hi_u32 v5, s3, v1
 ; GCN-NEXT:    v_mul_lo_u32 v1, s3, v1
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
 ; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v6, v2, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, v1, 24
 ; GCN-NEXT:    v_mul_hi_u32 v2, v0, 24
 ; GCN-NEXT:    v_mul_lo_u32 v0, v0, 24
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GCN-NEXT:    v_mov_b32_e32 v2, s3
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0

 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
 ; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
 ; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
 ; GCN-NEXT:    v_rcp_f32_e32 v2, v2
-; GCN-NEXT:    v_mov_b32_e32 v11, 0
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v3, v3
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
 ; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
 ; GCN-NEXT:    v_mul_lo_u32 v9, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GCN-NEXT:    v_mul_lo_u32 v7, v2, v6
 ; GCN-NEXT:    v_mul_hi_u32 v8, v2, v9
 ; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v10, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v10, v3, v9
 ; GCN-NEXT:    v_mul_hi_u32 v9, v3, v9
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v11, vcc
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v11, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
 ; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
 ; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
 ; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
 ; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
 ; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
 ; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
 ; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v11, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v3, v5, vcc
 ; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
 ; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
 ; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
 ; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2