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[mlir][vector] Insert/extract element can accept index
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Authored by Mogball on Nov 17 2021, 9:57 PM.

Details

Summary

vector::InsertElementOp and vector::ExtractElementOp have had their position
operand changed to accept AnySignlessIntegerOrIndex for better operability with
operations that use index, such as affine loops.

LLVM's extractelement and insertelement can also accept i64, so lowering
directly to these operations without explicitly inserting casts is allowed. SPIRV's
equivalent ops can also accept i64.

Diff Detail

Event Timeline

Mogball created this revision.Nov 17 2021, 9:57 PM
Mogball requested review of this revision.Nov 17 2021, 9:57 PM

Thanks for the improvement @Mogball and thanks @krzysz00 for diagnosing the problem !

This revision is now accepted and ready to land.Nov 17 2021, 11:44 PM
jpienaar accepted this revision.Nov 18 2021, 6:21 AM
jpienaar added a subscriber: jpienaar.

Nice!

This revision was automatically updated to reflect the committed changes.