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Differential D114076

[AMDGPU] Update GFX10 memory model to account for MALL
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Authored by critson on Nov 17 2021, 4:12 AM.

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Reviewers
t-tye
foad
rampitec
Commits
rG6d28dffb6bf4: [AMDGPU] Update GFX10 memory model to account for MALL
Summary

Document memory attached last level (MALL) cache added in GFX10.3.

Diff Detail

Event Timeline

critson created this revision.Nov 17 2021, 4:12 AM
Herald added subscribers: kerbowa, tpr, dstuttard and 4 others. · View Herald TranscriptNov 17 2021, 4:12 AM
critson requested review of this revision.Nov 17 2021, 4:12 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 17 2021, 4:12 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Harbormaster completed remote builds in B134709: Diff 387896.Nov 17 2021, 4:59 AM
t-tye accepted this revision.Nov 17 2021, 9:55 AM

LGTM

This revision is now accepted and ready to land.Nov 17 2021, 9:55 AM
Closed by commit rG6d28dffb6bf4: [AMDGPU] Update GFX10 memory model to account for MALL (authored by critson). · Explain WhyNov 17 2021, 4:30 PM
This revision was automatically updated to reflect the committed changes.
critson added a commit: rG6d28dffb6bf4: [AMDGPU] Update GFX10 memory model to account for MALL.

Revision Contents

PathSize
llvm/
docs/
7 lines

Diff 387896

llvm/docs/AMDGPUUsage.rst

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 367 Lines • ▼ Show 20 Lines ``gfx90c`` ``amdgcn`` APU - xnack - Absolute - *pal-amdpal* - Ryzen 7 4700G
- Ryzen Pro 4000G - Ryzen Pro 4000G
- Ryzen 7 Pro 4700G - Ryzen 7 Pro 4700G
- Ryzen 7 Pro 4750GE - Ryzen 7 Pro 4750GE
- Ryzen 5 Pro 4650G - Ryzen 5 Pro 4650G
- Ryzen 5 Pro 4650GE - Ryzen 5 Pro 4650GE
- Ryzen 3 Pro 4350G - Ryzen 3 Pro 4350G
- Ryzen 3 Pro 4350GE - Ryzen 3 Pro 4350GE
**GCN GFX10 (RDNA 1)** [AMD-GCN-GFX10-RDNA1]_ **GCN GFX10.1 (RDNA 1)** [AMD-GCN-GFX10-RDNA1]_
----------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------
``gfx1010`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon RX 5700 ``gfx1010`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon RX 5700
- wavefrontsize64 flat - *pal-amdhsa* - Radeon RX 5700 XT - wavefrontsize64 flat - *pal-amdhsa* - Radeon RX 5700 XT
- xnack scratch - *pal-amdpal* - Radeon Pro 5600 XT - xnack scratch - *pal-amdpal* - Radeon Pro 5600 XT
- Radeon Pro 5600M - Radeon Pro 5600M
``gfx1011`` ``amdgcn`` dGPU - cumode - *rocm-amdhsa* - Radeon Pro V520 ``gfx1011`` ``amdgcn`` dGPU - cumode - *rocm-amdhsa* - Radeon Pro V520
- wavefrontsize64 - Absolute - *pal-amdhsa* - wavefrontsize64 - Absolute - *pal-amdhsa*
- xnack flat - *pal-amdpal* - xnack flat - *pal-amdpal*
scratch scratch
``gfx1012`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon RX 5500 ``gfx1012`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon RX 5500
- wavefrontsize64 flat - *pal-amdhsa* - Radeon RX 5500 XT - wavefrontsize64 flat - *pal-amdhsa* - Radeon RX 5500 XT
- xnack scratch - *pal-amdpal* - xnack scratch - *pal-amdpal*
``gfx1013`` ``amdgcn`` APU - cumode - Absolute - *rocm-amdhsa* *TBA* ``gfx1013`` ``amdgcn`` APU - cumode - Absolute - *rocm-amdhsa* *TBA*
- wavefrontsize64 flat - *pal-amdhsa* - wavefrontsize64 flat - *pal-amdhsa*
- xnack scratch - *pal-amdpal* .. TODO:: - xnack scratch - *pal-amdpal* .. TODO::
Add product Add product
names. names.
**GCN GFX10 (RDNA 2)** [AMD-GCN-GFX10-RDNA2]_ **GCN GFX10.3 (RDNA 2)** [AMD-GCN-GFX10-RDNA2]_
----------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------
``gfx1030`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon RX 6800 ``gfx1030`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon RX 6800
- wavefrontsize64 flat - *pal-amdhsa* - Radeon RX 6800 XT - wavefrontsize64 flat - *pal-amdhsa* - Radeon RX 6800 XT
scratch - *pal-amdpal* - Radeon RX 6900 XT scratch - *pal-amdpal* - Radeon RX 6900 XT
``gfx1031`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon RX 6700 XT ``gfx1031`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* - Radeon RX 6700 XT
- wavefrontsize64 flat - *pal-amdhsa* - wavefrontsize64 flat - *pal-amdhsa*
scratch - *pal-amdpal* scratch - *pal-amdpal*
``gfx1032`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* *TBA* ``gfx1032`` ``amdgcn`` dGPU - cumode - Absolute - *rocm-amdhsa* *TBA*
▲ Show 20 Lines • Show All 8,161 Lines • ▼ Show 20 Lines* Each L1 quadrant of a single SA accesses a different L2 channel. Each L1
work-groups (which may be executing on different SAs) of an agent can be work-groups (which may be executing on different SAs) of an agent can be
reordered relative to each other. A ``s_waitcnt vmcnt(0) & vscnt(0)`` is reordered relative to each other. A ``s_waitcnt vmcnt(0) & vscnt(0)`` is
required to ensure synchronization between vector memory operations of required to ensure synchronization between vector memory operations of
different SAs. It ensures a previous vector memory operation has completed different SAs. It ensures a previous vector memory operation has completed
before executing a subsequent vector memory and so can be used to meet the before executing a subsequent vector memory and so can be used to meet the
requirements of acquire, release and sequential consistency. requirements of acquire, release and sequential consistency.
* The L2 cache can be kept coherent with other agents on some targets, or ranges * The L2 cache can be kept coherent with other agents on some targets, or ranges
of virtual addresses can be set up to bypass it to ensure system coherence. of virtual addresses can be set up to bypass it to ensure system coherence.
* On GFX10.3 a memory attached last level (MALL) cache exists for GPU memory.
The MALL cache is fully coherent with GPU memory and has no impact on system
coherence. All agents (GPU and CPU) access GPU memory through the MALL cache.
Scalar memory operations are only used to access memory that is proven to not Scalar memory operations are only used to access memory that is proven to not
change during the execution of the kernel dispatch. This includes constant change during the execution of the kernel dispatch. This includes constant
address space and global address space for program scope ``const`` variables. address space and global address space for program scope ``const`` variables.
Therefore, the kernel machine code does not have to maintain the scalar cache to Therefore, the kernel machine code does not have to maintain the scalar cache to
ensure it is coherent with the vector caches. The scalar and vector caches are ensure it is coherent with the vector caches. The scalar and vector caches are
invalidated between kernel dispatches by CP since constant address space data invalidated between kernel dispatches by CP since constant address space data
may change between kernel dispatch executions. See may change between kernel dispatch executions. See
▲ Show 20 Lines • Show All 3,808 Lines • Show Last 20 Lines