[PowerPC] Support of ppc_fp128 in lowering of llvm.is_fpclass

[sepavloff]

Summary

PowerPC supports ppc_fp128, which is not an IEEE floating point
type. The generic lowering of llvm.is_fpclass could not handle it
properly. This change extends the generic lowering code to
support ppc_fp128.

The change was tested on emulator using runtime tests from
https://reviews.llvm.org/D112933 and the patch for clang
https://reviews.llvm.org/D112932.

[qiucf]

llvm/test/CodeGen/PowerPC/ppc-is_fpclass.ll

3

Can you please add test case for fp128 type (under -mcpu=power9)?

And seems we don't need ppc- prefix in filename.

[sepavloff]

Updated patch

• In the test file name the prefix ppc- is dropped,
• The test now is compiled for POWER9
• The revision is retitled.

[qiucf]

Thanks

[sepavloff]

Thanks!

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

 
 SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
                                          unsigned Check, SDNodeFlags Flags,
                                          const SDLoc &DL,
                                          SelectionDAG &DAG) const {
   EVT OperandVT = Op.getValueType();
   assert(OperandVT.isFloatingPoint());
 
+  // PPC double double is a pair of doubles, of which the higher part determines
+  // the value class.
+  if (OperandVT == MVT::ppcf128) {
+    Op = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::f64, Op,
+                     DAG.getConstant(1, DL, MVT::i32));
+    OperandVT = MVT::f64;
+  }
+
   APInt InvertMask = APInt::getAllOnesValue(ResultVT.getScalarSizeInBits());
   SDValue InvertMaskV = DAG.getConstant(InvertMask, DL, ResultVT);
 
   bool IsInverted = false;
   if (unsigned InvertedCheck = checkInvertedFPClass(Check)) {
     IsInverted = true;
     Check = InvertedCheck;
   }

llvm/test/CodeGen/PowerPC/ppc-is_fpclass.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpcle-unknown-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s
+
+
+define i1 @isnan_float(float %x) nounwind {
+; CHECK-LABEL: isnan_float:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    fcmpu 0, 1, 1
+; CHECK-NEXT:    li 4, 1
+; CHECK-NEXT:    bc 12, 3, .LBB0_1
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB0_1:
+; CHECK-NEXT:    addi 3, 4, 0
+; CHECK-NEXT:    blr
+  %1 = call i1 @llvm.is.fpclass.f32(float %x, metadata !"nan")
+  ret i1 %1
+}
+
+define i1 @isnan_double(double %x) nounwind {
+; CHECK-LABEL: isnan_double:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    fcmpu 0, 1, 1
+; CHECK-NEXT:    li 4, 1
+; CHECK-NEXT:    bc 12, 3, .LBB1_1
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB1_1:
+; CHECK-NEXT:    addi 3, 4, 0
+; CHECK-NEXT:    blr
+  %1 = call i1 @llvm.is.fpclass.f64(double %x, metadata !"nan")
+  ret i1 %1
+}
+
+define i1 @isnan_ldouble(ppc_fp128 %x) nounwind {
+; CHECK-LABEL: isnan_ldouble:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    fcmpu 0, 1, 1
+; CHECK-NEXT:    li 4, 1
+; CHECK-NEXT:    bc 12, 3, .LBB2_1
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB2_1:
+; CHECK-NEXT:    addi 3, 4, 0
+; CHECK-NEXT:    blr
+  %1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, metadata !"nan")
+  ret i1 %1
+}
+
+define i1 @isnan_float_strictfp(float %x) strictfp nounwind {
+; CHECK-LABEL: isnan_float_strictfp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    stfs 1, 12(1)
+; CHECK-NEXT:    lis 3, 32640
+; CHECK-NEXT:    lwz 4, 12(1)
+; CHECK-NEXT:    clrlwi 4, 4, 1
+; CHECK-NEXT:    cmpw 4, 3
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    li 4, 1
+; CHECK-NEXT:    bc 12, 1, .LBB3_1
+; CHECK-NEXT:    b .LBB3_2
+; CHECK-NEXT:  .LBB3_1:
+; CHECK-NEXT:    addi 3, 4, 0
+; CHECK-NEXT:  .LBB3_2:
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  %1 = call i1 @llvm.is.fpclass.f32(float %x, metadata !"nan")
+  ret i1 %1
+}
+
+define i1 @isnan_double_strictfp(double %x) strictfp nounwind {
+; CHECK-LABEL: isnan_double_strictfp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    stfd 1, 8(1)
+; CHECK-NEXT:    lis 3, 32752
+; CHECK-NEXT:    lwz 4, 12(1)
+; CHECK-NEXT:    lwz 5, 8(1)
+; CHECK-NEXT:    clrlwi 4, 4, 1
+; CHECK-NEXT:    cmpw 4, 3
+; CHECK-NEXT:    xoris 3, 4, 32752
+; CHECK-NEXT:    cmplwi 1, 3, 0
+; CHECK-NEXT:    crandc 20, 1, 6
+; CHECK-NEXT:    cmpwi 5, 0
+; CHECK-NEXT:    crandc 21, 6, 2
+; CHECK-NEXT:    crnor 20, 21, 20
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    bc 12, 20, .LBB4_1
+; CHECK-NEXT:    b .LBB4_2
+; CHECK-NEXT:  .LBB4_1:
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB4_2:
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  %1 = call i1 @llvm.is.fpclass.f64(double %x, metadata !"nan")
+  ret i1 %1
+}
+
+define i1 @isnan_ldouble_strictfp(ppc_fp128 %x) strictfp nounwind {
+; CHECK-LABEL: isnan_ldouble_strictfp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    stfd 1, 8(1)
+; CHECK-NEXT:    lis 3, 32752
+; CHECK-NEXT:    lwz 4, 12(1)
+; CHECK-NEXT:    lwz 5, 8(1)
+; CHECK-NEXT:    clrlwi 4, 4, 1
+; CHECK-NEXT:    cmpw 4, 3
+; CHECK-NEXT:    xoris 3, 4, 32752
+; CHECK-NEXT:    cmplwi 1, 3, 0
+; CHECK-NEXT:    crandc 20, 1, 6
+; CHECK-NEXT:    cmpwi 5, 0
+; CHECK-NEXT:    crandc 21, 6, 2
+; CHECK-NEXT:    crnor 20, 21, 20
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    bc 12, 20, .LBB5_1
+; CHECK-NEXT:    b .LBB5_2
+; CHECK-NEXT:  .LBB5_1:
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB5_2:
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  %1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, metadata !"nan")
+  ret i1 %1
+}
+
+define i1 @isinf_float(float %x) nounwind {
+; CHECK-LABEL: isinf_float:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    stfs 1, 12(1)
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    lwz 4, 12(1)
+; CHECK-NEXT:    clrlwi 4, 4, 1
+; CHECK-NEXT:    xoris 4, 4, 32640
+; CHECK-NEXT:    cmplwi 4, 0
+; CHECK-NEXT:    li 4, 1
+; CHECK-NEXT:    bc 12, 2, .LBB6_1
+; CHECK-NEXT:    b .LBB6_2
+; CHECK-NEXT:  .LBB6_1:
+; CHECK-NEXT:    addi 3, 4, 0
+; CHECK-NEXT:  .LBB6_2:
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  %1 = call i1 @llvm.is.fpclass.f32(float %x, metadata !"inf")
+  ret i1 %1
+}
+
+define i1 @isinf_ldouble(ppc_fp128 %x) nounwind {
+; CHECK-LABEL: isinf_ldouble:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    stfd 1, 8(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    lwz 4, 8(1)
+; CHECK-NEXT:    clrlwi 3, 3, 1
+; CHECK-NEXT:    xoris 3, 3, 32752
+; CHECK-NEXT:    or 3, 4, 3
+; CHECK-NEXT:    cntlzw 3, 3
+; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  %1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, metadata !"inf")
+  ret i1 %1
+}
+
+define i1 @isfinite_float(float %x) nounwind {
+; CHECK-LABEL: isfinite_float:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    stfs 1, 12(1)
+; CHECK-NEXT:    lis 3, 32640
+; CHECK-NEXT:    lwz 4, 12(1)
+; CHECK-NEXT:    clrlwi 4, 4, 1
+; CHECK-NEXT:    cmpw 4, 3
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    li 4, 1
+; CHECK-NEXT:    bc 12, 0, .LBB8_1
+; CHECK-NEXT:    b .LBB8_2
+; CHECK-NEXT:  .LBB8_1:
+; CHECK-NEXT:    addi 3, 4, 0
+; CHECK-NEXT:  .LBB8_2:
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  %1 = call i1 @llvm.is.fpclass.f32(float %x, metadata !"finite")
+  ret i1 %1
+}
+
+define i1 @isnormal_float(float %x) nounwind {
+; CHECK-LABEL: isnormal_float:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    stfs 1, 12(1)
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    lwz 4, 12(1)
+; CHECK-NEXT:    clrlwi 4, 4, 1
+; CHECK-NEXT:    addis 4, 4, -128
+; CHECK-NEXT:    srwi 4, 4, 24
+; CHECK-NEXT:    cmplwi 4, 127
+; CHECK-NEXT:    li 4, 1
+; CHECK-NEXT:    bc 12, 0, .LBB9_1
+; CHECK-NEXT:    b .LBB9_2
+; CHECK-NEXT:  .LBB9_1:
+; CHECK-NEXT:    addi 3, 4, 0
+; CHECK-NEXT:  .LBB9_2:
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  %1 = call i1 @llvm.is.fpclass.f32(float %x, metadata !"normal")
+  ret i1 %1
+}
+
+define i1 @issubnormal_float(float %x) nounwind {
+; CHECK-LABEL: issubnormal_float:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    stfs 1, 12(1)
+; CHECK-NEXT:    lis 3, 127
+; CHECK-NEXT:    lwz 4, 12(1)
+; CHECK-NEXT:    ori 3, 3, 65535
+; CHECK-NEXT:    clrlwi 4, 4, 1
+; CHECK-NEXT:    addi 4, 4, -1
+; CHECK-NEXT:    cmplw 4, 3
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    li 4, 1
+; CHECK-NEXT:    bc 12, 0, .LBB10_1
+; CHECK-NEXT:    b .LBB10_2
+; CHECK-NEXT:  .LBB10_1:
+; CHECK-NEXT:    addi 3, 4, 0
+; CHECK-NEXT:  .LBB10_2:
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  %1 = call i1 @llvm.is.fpclass.f32(float %x, metadata !"subnormal")
+  ret i1 %1
+}
+
+define i1 @iszero_float(float %x) nounwind {
+; CHECK-LABEL: iszero_float:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lis 3, .LCPI11_0@ha
+; CHECK-NEXT:    lfs 0, .LCPI11_0@l(3)
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    li 4, 1
+; CHECK-NEXT:    fcmpu 0, 1, 0
+; CHECK-NEXT:    bc 12, 2, .LBB11_1
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB11_1:
+; CHECK-NEXT:    addi 3, 4, 0
+; CHECK-NEXT:    blr
+  %1 = call i1 @llvm.is.fpclass.f32(float %x, metadata !"zero")
+  ret i1 %1
+}
+
+declare i1 @llvm.is.fpclass.f32(float, metadata)
+declare i1 @llvm.is.fpclass.f64(double, metadata)
+declare i1 @llvm.is.fpclass.ppcf128(ppc_fp128, metadata)