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Differential D112201

[CortexA55][SchedModels] Complete Cortex-A55 scheduler model
Needs ReviewPublic

Authored by kpdev42 on Oct 20 2021, 11:51 PM.

Details

Reviewers
dmgreen
NickGuy
andreadb
sjarus
Summary

Depends on D114642, D116361

Diff Detail

Event Timeline

kpdev42 created this revision.Oct 20 2021, 11:51 PM
Herald added subscribers: gbedwell, hiraditya. · View Herald TranscriptOct 20 2021, 11:51 PM
kpdev42 requested review of this revision.Oct 20 2021, 11:51 PM
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Harbormaster completed remote builds in B129878: Diff 381151.Oct 21 2021, 4:22 AM
asl added a subscriber: asl.Oct 27 2021, 1:37 AM
kpdev42 added a comment.Oct 27 2021, 4:58 AM

Ping

dmgreen added a comment.Oct 28 2021, 12:52 AM

OK. Do you have any performance results that suggest this is an improvement?

kpdev42 updated this revision to Diff 390056.Nov 26 2021, 7:31 AM
kpdev42 edited the summary of this revision. (Show Details)
kpdev42 added a parent revision: D114642: [AArch64][SchedModels] Handle virtual registers in FP/NEON predicates.

I’ve attached test results for LLVM test suite (MultiSource and MicroBenchmarks suites) which show difference between complete and incomplete Cortex-A55 scheduler model.
I’d also mention that we’ve got small (~1%) improvements in GeekBench SGEMM and AES-XTS tests.

Harbormaster completed remote builds in B136237: Diff 390056.Nov 26 2021, 7:32 AM
dmgreen added a comment.Dec 17 2021, 1:23 AM
In D112201#3155985, @kpdev42 wrote:

I’ve attached test results for LLVM test suite (MultiSource and MicroBenchmarks suites) which show difference between complete and incomplete Cortex-A55 scheduler model.
I’d also mention that we’ve got small (~1%) improvements in GeekBench SGEMM and AES-XTS tests.

OK Thanks. I presume this is run on a Cortex-A55? And the noise is low enough to make them meaningful?

We wrote a few different updates to the CortexA55 schedule prior to making it the default under cpu=generic. We had already written patches a lot like this (not this exactly - the neon part of this patch. This patch is trying to do too much at once and needs to be split up). The problem is that the A55 is notoriously difficult to schedule for and a lot of the patches we tried ended up making the performance worse, not better. We run a set of some benchmarks on an RTL simulator to get deterministic results. They are perhaps not the best benchmarks, but are very accurate, and this patch shows the same results where things don't look better.

(We also had a few other reasons for keeping the higher latencies, like the A510 sometimes having higher latencies but higher throughputs, and this schedule being used for cpu=generic allows it to produce better code in more cases. Plus it effecting many test now that it is the default. I was at least hoping to give it some times before we changed everything again.)

I think there is values to having more accurate scheduling, even if the performance results we have are not perfect. I would suggest trying to split this patch up a bit though, to make sure we can check that the parts are correct. At least the LDP and NEON parts are logically separate.

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-neon-instructions.s
1064

Why has this file been rewritten?

kpdev42 edited the summary of this revision. (Show Details)Dec 28 2021, 10:31 PM
kpdev42 added a parent revision: D116361: [SchedModels][CortexA55] Fix scheduling of FP loads.
kpdev42 added a comment.Dec 28 2021, 10:37 PM
In D112201#3199365, @dmgreen wrote:

OK Thanks. I presume this is run on a Cortex-A55? And the noise is low enough to make them meaningful?

We've run all the tests on Odroid-C4 board (4 A55 cores) with locked frequencies for each core. LLVM test suite was compiled with complete and incomplete model and run 10 times. We also repeated such test few times to ensure result is meaningful

kpdev42 mentioned this in D117003: [SchedModels][CortexA55] Add ASIMD integer instructioins.Jan 11 2022, 3:04 AM
kpdev42 mentioned this in rG37fa99eda0f5: [SchedModels][CortexA55] Add ASIMD integer instructions.Feb 17 2022, 2:43 AM
kpdev42 updated this revision to Diff 410445.Feb 21 2022, 9:31 PM

An update for Cortex-A55 model. It contains ASIMD fp, misc, crypto and crc instructions.

Herald added a reviewer: sjarus. · View Herald TranscriptFeb 21 2022, 9:31 PM
Herald added subscribers: armkevincheng, eric-k256. · View Herald Transcript
Harbormaster completed remote builds in B150805: Diff 410445.Feb 21 2022, 9:31 PM
kpdev42 added a comment.Nov 9 2022, 1:44 AM

ping

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Diff 410445

llvm/lib/Target/AArch64/AArch64SchedA55.td

Show All 18 Linesdef CortexA55Model : SchedMachineModel {
let MicroOpBufferSize = 0; // The Cortex-A55 is an in-order processor let MicroOpBufferSize = 0; // The Cortex-A55 is an in-order processor
let IssueWidth = 2; // It dual-issues under most circumstances let IssueWidth = 2; // It dual-issues under most circumstances
let LoadLatency = 4; // Cycles for loads to access the cache. The let LoadLatency = 4; // Cycles for loads to access the cache. The
// optimisation guide shows that most loads have // optimisation guide shows that most loads have
// a latency of 3, but some have a latency of 4 // a latency of 3, but some have a latency of 4
// or 5. Setting it 4 looked to be good trade-off. // or 5. Setting it 4 looked to be good trade-off.
let MispredictPenalty = 8; // A branch direction mispredict. let MispredictPenalty = 8; // A branch direction mispredict.
let PostRAScheduler = 1; // Enable PostRA scheduler pass. let PostRAScheduler = 1; // Enable PostRA scheduler pass.
let CompleteModel = 0; // Covers instructions applicable to Cortex-A55. let CompleteModel = 1; // Covers instructions applicable to Cortex-A55.
list<Predicate> UnsupportedFeatures = [HasSVE]; list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F);
// FIXME: Remove when all errors have been fixed. // FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0; let FullInstRWOverlapCheck = 0;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available. // Define each kind of processor resource and number available.
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
// NEON // NEON
class CortexA55WriteVd<int n, ProcResourceKind res> : SchedWriteRes<[res]> { class CortexA55WriteVd<int n, ProcResourceKind res> : SchedWriteRes<[res]> {
let Latency = n; let Latency = n;
} }
class CortexA55WriteVq<int n, ProcResourceKind res> : SchedWriteRes<[res, res]> { class CortexA55WriteVq<int n, ProcResourceKind res> : SchedWriteRes<[res, res]> {
let Latency = n; let Latency = n;
let BeginGroup = 1; let BeginGroup = 1;
} }
class CortexA55WriteVqDual<int n, ProcResourceKind res> : SchedWriteRes<[res, res]> {
let Latency = n;
}
class CortexA55WriteVqL<int n, ProcResourceKind res> : SchedWriteRes<[res, res, res, res]> { class CortexA55WriteVqL<int n, ProcResourceKind res> : SchedWriteRes<[res, res, res, res]> {
let Latency = n; let Latency = n;
let BeginGroup = 1; let BeginGroup = 1;
} }
// Used for tbl/tbx
class CortexA55WriteVqTab<int n, int rc, ProcResourceKind res> : SchedWriteRes<[res, res]> {
let Latency = n;
let BeginGroup = 1;
let ResourceCycles = [rc, rc];
}
def CortexA55WriteDotScVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>; def CortexA55WriteDotScVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>;
def CortexA55WriteDotVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>; def CortexA55WriteDotVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>;
def CortexA55WriteDotVd_4 : CortexA55WriteVd<4, CortexA55UnitFPALU>; def CortexA55WriteDotVd_4 : CortexA55WriteVd<4, CortexA55UnitFPALU>;
def CortexA55WriteMlaLVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>; def CortexA55WriteMlaLVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>;
def CortexA55WriteMlaIxVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>; def CortexA55WriteMlaIxVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>;
def CortexA55WriteMlaVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>; def CortexA55WriteMlaVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>;
def CortexA55WriteMlaVd_4 : CortexA55WriteVd<4, CortexA55UnitFPALU>; def CortexA55WriteMlaVd_4 : CortexA55WriteVd<4, CortexA55UnitFPALU>;
def CortexA55WriteAluVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>; def CortexA55WriteAluVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>;
def CortexA55WriteAluVd_3 : CortexA55WriteVd<3, CortexA55UnitFPALU>; def CortexA55WriteAluVd_3 : CortexA55WriteVd<3, CortexA55UnitFPALU>;
def CortexA55WriteAluVq_3 : CortexA55WriteVq<3, CortexA55UnitFPALU>; def CortexA55WriteAluVq_3 : CortexA55WriteVq<3, CortexA55UnitFPALU>;
def CortexA55WriteAluVd_2 : CortexA55WriteVd<2, CortexA55UnitFPALU>; def CortexA55WriteAluVd_2 : CortexA55WriteVd<2, CortexA55UnitFPALU>;
def CortexA55WriteAluVq_2 : CortexA55WriteVq<2, CortexA55UnitFPALU>; def CortexA55WriteAluVq_2 : CortexA55WriteVq<2, CortexA55UnitFPALU>;
def CortexA55WriteAluVd_1 : CortexA55WriteVd<1, CortexA55UnitFPALU>; def CortexA55WriteAluVd_1 : CortexA55WriteVd<1, CortexA55UnitFPALU>;
def CortexA55WriteAluVq_1 : CortexA55WriteVq<1, CortexA55UnitFPALU>; def CortexA55WriteAluVq_1 : CortexA55WriteVq<1, CortexA55UnitFPALU>;
def CortexA55WriteAluVqL_4 : CortexA55WriteVqL<4, CortexA55UnitFPALU>; def CortexA55WriteAluVqL_4 : CortexA55WriteVqL<4, CortexA55UnitFPALU>;
def CortexA55WriteAluTab_2_1 : CortexA55WriteVqTab<2, 1, CortexA55UnitFPALU>;
def CortexA55WriteAluTab_3_2 : CortexA55WriteVqTab<3, 2, CortexA55UnitFPALU>;
def CortexA55WriteAluTab_4_3 : CortexA55WriteVqTab<4, 3, CortexA55UnitFPALU>;
def CortexA55WriteAluTab_5_4 : CortexA55WriteVqTab<5, 4, CortexA55UnitFPALU>;
def CortexA55WriteAluTab_6_5 : CortexA55WriteVqTab<6, 5, CortexA55UnitFPALU>;
// According to A55 optimization guide AESIMC/AESMC can be dual-issued.
def CortexA55WriteAesMixCol : CortexA55WriteVqDual<2, CortexA55UnitFPALU>;
def CortexA55WriteAesEnc : CortexA55WriteVq<2, CortexA55UnitFPALU>;
def CortexA55WriteAesDec : CortexA55WriteVq<2, CortexA55UnitFPALU>;
def : SchedAlias<WriteVd, CortexA55WriteVd<4, CortexA55UnitFPALU>>; def : SchedAlias<WriteVd, CortexA55WriteVd<4, CortexA55UnitFPALU>>;
def : SchedAlias<WriteVq, CortexA55WriteVq<4, CortexA55UnitFPALU>>; def : SchedAlias<WriteVq, CortexA55WriteVq<4, CortexA55UnitFPALU>>;
// FP ALU specific new schedwrite definitions // FP ALU specific new schedwrite definitions
def CortexA55WriteFPALU_F2 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 2;} def CortexA55WriteFPALU_F2 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 2;}
def CortexA55WriteFPALU_F3 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 3;} def CortexA55WriteFPALU_F3 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 3;}
def CortexA55WriteFPALU_F4 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 4;} def CortexA55WriteFPALU_F4 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 4;}
def CortexA55WriteFPALU_F5 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 5;} def CortexA55WriteFPALU_F5 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 5;}
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Linesdef : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
WriteIM32,WriteIM64]>; WriteIM32,WriteIM64]>;
// NEON ALU/MAC forwarding paths // NEON ALU/MAC forwarding paths
def CortexA55ReadMla : SchedReadAdvance<3, [CortexA55WriteMlaVd_4, CortexA55WriteMlaVq_4]>; def CortexA55ReadMla : SchedReadAdvance<3, [CortexA55WriteMlaVd_4, CortexA55WriteMlaVq_4]>;
def CortexA55ReadMlaIx : SchedReadAdvance<3, [CortexA55WriteMlaIxVq_4]>; def CortexA55ReadMlaIx : SchedReadAdvance<3, [CortexA55WriteMlaIxVq_4]>;
def CortexA55ReadMlaL : SchedReadAdvance<3, [CortexA55WriteMlaLVq_4]>; def CortexA55ReadMlaL : SchedReadAdvance<3, [CortexA55WriteMlaLVq_4]>;
def CortexA55ReadDot : SchedReadAdvance<3, [CortexA55WriteDotVd_4, CortexA55WriteDotVq_4]>; def CortexA55ReadDot : SchedReadAdvance<3, [CortexA55WriteDotVd_4, CortexA55WriteDotVq_4]>;
def CortexA55ReadDotSc : SchedReadAdvance<3, [CortexA55WriteDotScVq_4]>; def CortexA55ReadDotSc : SchedReadAdvance<3, [CortexA55WriteDotScVq_4]>;
def CortexA55ReadAesMC : SchedReadAdvance<1, [CortexA55WriteAesEnc]>;
def CortexA55ReadAesIMC : SchedReadAdvance<1, [CortexA55WriteAesDec]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Subtarget-specific InstRWs. // Subtarget-specific InstRWs.
//--- //---
// Miscellaneous // Miscellaneous
//--- //---
def : InstRW<[CortexA55WriteVLD1SI,CortexA55WriteLDP1], (instregex "LDPS?Wi")>; def : InstRW<[CortexA55WriteVLD1SI,CortexA55WriteLDP1], (instregex "LDPS?Wi")>;
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Linesdef : InstRW<[CortexA55WriteAluVq_3], (instregex "[SU]RSHRv(16i8|2i64|4i32|8i16)",
"RSHRNv(16i8|4i32|8i16)")>; "RSHRNv(16i8|4i32|8i16)")>;
// ASIMD shift by register // ASIMD shift by register
def : InstRW<[CortexA55WriteAluVd_2], (instregex "[SU]SHLv(1i64|2i32|4i16|8i8)")>; def : InstRW<[CortexA55WriteAluVd_2], (instregex "[SU]SHLv(1i64|2i32|4i16|8i8)")>;
def : InstRW<[CortexA55WriteAluVq_2], (instregex "[SU]SHLv(2i64|4i32|8i16|16i8)")>; def : InstRW<[CortexA55WriteAluVq_2], (instregex "[SU]SHLv(2i64|4i32|8i16|16i8)")>;
// ASIMD shift by register #2 // ASIMD shift by register #2
def : InstRW<[CortexA55WriteAluVd_3], (instregex "[SU]RSHLv(1i64|2i32|4i16|8i8)")>; def : InstRW<[CortexA55WriteAluVd_3], (instregex "[SU]RSHLv(1i64|2i32|4i16|8i8)")>;
def : InstRW<[CortexA55WriteAluVq_3], (instregex "[SU]RSHLv(2i64|4i32|8i16|16i8)")>; def : InstRW<[CortexA55WriteAluVq_3], (instregex "[SU]RSHLv(2i64|4i32|8i16|16i8)")>;
// 4.16. Advanced SIMD floating-point instructions
// ASIMD FP compare
def : InstRW<[CortexA55WriteAluVd_2], (instregex "FAC(GT|GE)(16|32|64|v2f32|v4f16)",
"FCM(EQ|GT|GE)(16|32|64|v1i|v2i32|v4i16|v2f32|v4f16)", "FCM(LE|LT)(v1i|v2i32|v4i16)")>;
// , "FCM(LE|LT)(v2i64|v4i32|v8i16"
def : InstRW<[CortexA55WriteAluVq_2], (instregex "FAC(GT|GE)(v2f64|v4f32|v8f16)",
"FCM(EQ|GT|GE)(v2i64|v4i32|v2f64|v4f32|v8)", "FCM(LE|LT)(v2i64|v4i32|v8i16)")>;
// ASIMD FP divide, H-form
def : InstRW<[CortexA55WriteFDivHP], (instrs FDIVv4f16, FDIVv8f16)>;
// ASIMD FP divide, S-form
def : InstRW<[CortexA55WriteFDivSP], (instrs FDIVv2f32, FDIVv4f32)>;
// ASIMD FP divide, D-form
def : InstRW<[CortexA55WriteFDivDP], (instrs FDIVv2f64)>;
// ASIMD FP max/min, reduce
def : InstRW<[CortexA55WriteAluVq_4], (instregex "FMAX(NM)?Vv", "FMIN(NM)?Vv")>;
// ASIMD FP multiply, by element
def : InstRW<[CortexA55WriteAluVq_4], (instregex "FMULX?v[1248]i")>;
// 4.17. Advanced SIMD miscellaneous instructions
// ASIMD bit reverse / ASIMD bitwise insert
def : InstRW<[CortexA55WriteAluVd_2], (instregex "R?BITv8", "BIFv8", "BSLv8")>;
def : InstRW<[CortexA55WriteAluVq_2], (instregex "R?BITv16", "BIFv16", "BSLv16")>;
// ASIMD count
def : InstRW<[CortexA55WriteAluVd_2], (instregex "CLZv(2i32|4i16|8i8)", "CNTv8")>;
def : InstRW<[CortexA55WriteAluVq_2], (instregex "CLZv(4i32|8i16|16i8)", "CNTv16")>;
// ASIMD count #2
def : InstRW<[CortexA55WriteAluVd_3], (instregex "CLSv(2i32|4i16|8i8)")>;
def : InstRW<[CortexA55WriteAluVq_3], (instregex "CLSv(4i32|8i16|16i8)")>;
// ASIMD extract
def : InstRW<[CortexA55WriteAluVd_2], (instrs EXTv8i8)>;
def : InstRW<[CortexA55WriteAluVq_2], (instrs EXTv16i8)>;
// ASIMD extract narrow
//def : InstRW<[CortexA55WriteAluVd_1], (instregex "XTNv(2i32|4i16|8i8)")>;
//def : InstRW<[CortexA55WriteAluVq_1], (instregex "XTNv(4i32|8i16|16i8)")>;
// ASIMD extract narrow, saturating
// Cortex A55 optimization guide says all sqxtn/uqxtn instructions have
// throughput 2
def : InstRW<[CortexA55WriteAluVd_2], (instregex "[SU]QXTNv", "SQXTUNv")>;
// ASIMD insert, element to element
def : InstRW<[CortexA55WriteAluVd_2], (instregex "INSvi(8|16|32|64)lane$")>;
// ASIMD move, integer immed
def : InstRW<[CortexA55WriteAluVd_1], (instregex "MOVI(D|v2i|v2s|v8b|v4i16)")>;
def : InstRW<[CortexA55WriteAluVq_1], (instregex "MOVIv(2d|4s|8i|16b|4i32)")>;
// ASIMD move, FP immed
def : InstRW<[CortexA55WriteAluVd_1], (instregex "FMOVv")>;
// ASIMD reverse
def : InstRW<[CortexA55WriteAluVd_2], (instregex "REV16v8i8", "REV32v(4i16|8i8)",
"REV64v(2i32|4i16|8i8)")>;
def : InstRW<[CortexA55WriteAluVq_2], (instregex "REV16v16i8", "REV32v(8i16|16i8)",
"REV64v(4i32|8i16|16i8)")>;
// ASIMD table lookup (TBL, 1 reg)
def : InstRW<[CortexA55WriteAluTab_2_1], (instrs TBLv8i8One, TBLv16i8One)>;
// ASIMD table lookup (TBL, 2 regs)
def : InstRW<[CortexA55WriteAluTab_3_2], (instrs TBLv8i8Two, TBLv16i8Two)>;
// ASIMD table lookup (TBL, 3 regs)
def : InstRW<[CortexA55WriteAluTab_4_3], (instrs TBLv8i8Three, TBLv16i8Three)>;
// ASIMD table lookup (TBL, 4 regs)
def : InstRW<[CortexA55WriteAluTab_5_4], (instrs TBLv8i8Four, TBLv16i8Four)>;
// ASIMD table lookup (TBX, 1 reg)
def : InstRW<[CortexA55WriteAluTab_3_2], (instrs TBXv8i8One, TBXv16i8One)>;
// ASIMD table lookup (TBX, 2 regs)
def : InstRW<[CortexA55WriteAluTab_4_3], (instrs TBXv8i8Two, TBXv16i8Two)>;
// ASIMD table lookup (TBX, 3 regs)
def : InstRW<[CortexA55WriteAluTab_5_4], (instrs TBXv8i8Three, TBXv16i8Three)>;
// ASIMD table lookup (TBX, 4 regs)
def : InstRW<[CortexA55WriteAluTab_6_5], (instrs TBXv8i8Four, TBXv16i8Four)>;
// ASIMD transfer, element to gen reg
// FIXME: AArch64 instruction definition has WriteVq for SMOV/UMOV, while
// A55 optimization guide says throughput is 2
def : InstRW<[CortexA55WriteAluVd_2], (instregex "[SU]MOVv")>;
// ASIMD transfer, gen reg to element
// FIXME: AArch64 instruction definition has WriteVq for INS.*gpr, while
// A55 optimization guide says throughput is 2
def : InstRW<[CortexA55WriteAluVd_2], (instregex "INSvi(8|16|32|64)gpr$")>;
// ASIMD transpose, 64-bit (.2D)
def : InstRW<[CortexA55WriteAluVq_2], (instrs TRN1v2i32, TRN2v2i32)>;
// ASIMD transpose, other
def : InstRW<[CortexA55WriteAluVd_2], (instregex "TRN[12]v(4i16|8i8)$")>;
def : InstRW<[CortexA55WriteAluVq_2], (instregex "TRN[12]v(2i64|4i32|8i16|16i8)$")>;
// ASIMD unzip/zip
def : InstRW<[CortexA55WriteAluVd_2], (instregex "(ZIP|UZP)[12]v(2i32|4i16|8i8)")>;
def : InstRW<[CortexA55WriteAluVq_2], (instregex "(ZIP|UZP)[12]v(2i64|4i32|8i16|16i8)")>;
// 4.20. Cryptographic Extension
// Crypto AES ops
def : InstRW<[CortexA55WriteAesEnc], (instrs AESErr)>;
def : InstRW<[CortexA55WriteAesDec], (instrs AESDrr)>;
// Crypto AES ops #2
def : InstRW<[CortexA55WriteAesMixCol, CortexA55ReadAesIMC], (instrs AESIMCrr, AESIMCrrTied)>;
def : InstRW<[CortexA55WriteAesMixCol, CortexA55ReadAesMC], (instrs AESMCrr, AESMCrrTied)>;
// Crypto polynomial (64x64) multiply long
def : InstRW<[CortexA55WriteAluVq_2], (instrs PMULLv1i64, PMULLv2i64)>;
// Crypto SHA1 xor ops
def : InstRW<[CortexA55WriteAluVq_2], (instrs SHA1SU0rrr)>;
// Crypto SHA1 schedule acceleration ops
def : InstRW<[CortexA55WriteAluVq_2], (instrs SHA1Hrr, SHA1SU1rr)>;
// Crypto SHA1 hash acceleration ops
def : InstRW<[CortexA55WriteAluVq_4], (instregex "SHA1[CMP]rrr$")>;
// Crypto SHA256 schedule acceleration ops
def : InstRW<[CortexA55WriteAluVq_3], (instrs SHA256SU0rr)>;
// Crypto SHA256 schedule acceleration ops
def : InstRW<[CortexA55WriteAluVq_4], (instrs SHA256SU1rrr)>;
// Crypto SHA256 hash acceleration ops
def : InstRW<[CortexA55WriteAluVq_4], (instregex "SHA256H2?rrr$")>;
// 4.21. CRC
// CRC checksum ops
def : InstRW<[CortexA55WriteAluVd_2], (instregex "CRC32C?[BHX]rr$")>;
// CRC checksum ops #2
def : InstRW<[CortexA55WriteAluVd_1], (instrs CRC32CWrr, CRC32Wrr)>;
} }

llvm/test/Analysis/CostModel/AArch64/shuffle-select.ll

; RUN: opt < %s -mtriple=aarch64--linux-gnu -passes='print<cost-model>' 2>&1 -disable-output | FileCheck %s --check-prefix=COST ; RUN: opt < %s -mtriple=aarch64--linux-gnu -passes='print<cost-model>' 2>&1 -disable-output | FileCheck %s --check-prefix=COST
; RUN: llc < %s -mtriple=aarch64--linux-gnu | FileCheck %s --check-prefix=CODE ; RUN: llc < %s -mtriple=aarch64--linux-gnu | FileCheck %s --check-prefix=CODE
; COST-LABEL: sel.v8i8 ; COST-LABEL: sel.v8i8
; COST: Found an estimated cost of 42 for instruction: %tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15> ; COST: Found an estimated cost of 42 for instruction: %tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
; CODE-LABEL: sel.v8i8 ; CODE-LABEL: sel.v8i8
; CODE: tbl v0.8b, { v0.16b }, v1.8b ; CODE: tbl v0.8b, { v0.16b }, v2.8b
define <8 x i8> @sel.v8i8(<8 x i8> %v0, <8 x i8> %v1) { define <8 x i8> @sel.v8i8(<8 x i8> %v0, <8 x i8> %v1) {
%tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15> %tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
ret <8 x i8> %tmp0 ret <8 x i8> %tmp0
} }
; COST-LABEL: sel.v16i8 ; COST-LABEL: sel.v16i8
; COST: Found an estimated cost of 90 for instruction: %tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31> ; COST: Found an estimated cost of 90 for instruction: %tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
; CODE-LABEL: sel.v16i8 ; CODE-LABEL: sel.v16i8
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llvm/test/Analysis/CostModel/AArch64/vector-select.ll

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; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %cmp.1 = icmp sle <3 x i64> %a, %b ; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %cmp.1 = icmp sle <3 x i64> %a, %b
; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s.1 = select <3 x i1> %cmp.1, <3 x i64> %a, <3 x i64> %c ; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s.1 = select <3 x i1> %cmp.1, <3 x i64> %a, <3 x i64> %c
; CODE-LABEL: v3i64_select_sle ; CODE-LABEL: v3i64_select_sle
; CODE: bb.0 ; CODE: bb.0
; CODE: mov ; CODE: mov
; CODE: mov ; CODE: mov
; CODE: mov ; CODE: mov
; CODE: ldr
; CODE: cmge ; CODE: cmge
; CODE: cmge ; CODE: cmge
; CODE: ldr
; CODE: bif ; CODE: bif
; CODE: bif ; CODE: bif
; CODE: ext ; CODE: ext
; CODE: ret ; CODE: ret
define <3 x i64> @v3i64_select_sle(<3 x i64> %a, <3 x i64> %b, <3 x i64> %c) { define <3 x i64> @v3i64_select_sle(<3 x i64> %a, <3 x i64> %b, <3 x i64> %c) {
%cmp.1 = icmp sle <3 x i64> %a, %b %cmp.1 = icmp sle <3 x i64> %a, %b
%s.1 = select <3 x i1> %cmp.1, <3 x i64> %a, <3 x i64> %c %s.1 = select <3 x i1> %cmp.1, <3 x i64> %a, <3 x i64> %c
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llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll

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; SDAG-NEXT: uzp2 v0.8h, v0.8h, v3.8h ; SDAG-NEXT: uzp2 v0.8h, v0.8h, v3.8h
; SDAG-NEXT: add v0.8h, v0.8h, v1.8h ; SDAG-NEXT: add v0.8h, v0.8h, v1.8h
; SDAG-NEXT: ushl v0.8h, v0.8h, v2.8h ; SDAG-NEXT: ushl v0.8h, v0.8h, v2.8h
; SDAG-NEXT: ret ; SDAG-NEXT: ret
; ;
; GISEL-LABEL: combine_vec_udiv_nonuniform: ; GISEL-LABEL: combine_vec_udiv_nonuniform:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: adrp x8, .LCPI1_4 ; GISEL-NEXT: adrp x8, .LCPI1_4
; GISEL-NEXT: adrp x9, .LCPI1_0 ; GISEL-NEXT: adrp x9, .LCPI1_5
; GISEL-NEXT: adrp x10, .LCPI1_0
; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI1_4] ; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI1_4]
; GISEL-NEXT: adrp x8, .LCPI1_3 ; GISEL-NEXT: adrp x8, .LCPI1_3
; GISEL-NEXT: ldr q5, [x9, :lo12:.LCPI1_0] ; GISEL-NEXT: ldr q5, [x10, :lo12:.LCPI1_0]
; GISEL-NEXT: neg v1.8h, v1.8h ; GISEL-NEXT: neg v1.8h, v1.8h
; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI1_3] ; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI1_3]
; GISEL-NEXT: adrp x8, .LCPI1_2 ; GISEL-NEXT: adrp x8, .LCPI1_2
; GISEL-NEXT: ushl v1.8h, v0.8h, v1.8h ; GISEL-NEXT: ushl v1.8h, v0.8h, v1.8h
; GISEL-NEXT: umull2 v3.4s, v1.8h, v2.8h ; GISEL-NEXT: umull2 v3.4s, v1.8h, v2.8h
; GISEL-NEXT: umull v1.4s, v1.4h, v2.4h ; GISEL-NEXT: umull v1.4s, v1.4h, v2.4h
; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI1_2] ; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI1_2]
; GISEL-NEXT: adrp x8, .LCPI1_5 ; GISEL-NEXT: adrp x8, .LCPI1_1
; GISEL-NEXT: uzp2 v1.8h, v1.8h, v3.8h ; GISEL-NEXT: uzp2 v1.8h, v1.8h, v3.8h
; GISEL-NEXT: ldr q6, [x8, :lo12:.LCPI1_1]
; GISEL-NEXT: sub v3.8h, v0.8h, v1.8h ; GISEL-NEXT: sub v3.8h, v0.8h, v1.8h
; GISEL-NEXT: umull2 v4.4s, v3.8h, v2.8h ; GISEL-NEXT: umull2 v4.4s, v3.8h, v2.8h
; GISEL-NEXT: umull v2.4s, v3.4h, v2.4h ; GISEL-NEXT: umull v2.4s, v3.4h, v2.4h
; GISEL-NEXT: ldr q3, [x8, :lo12:.LCPI1_5] ; GISEL-NEXT: ldr q3, [x9, :lo12:.LCPI1_5]
; GISEL-NEXT: adrp x8, .LCPI1_1
; GISEL-NEXT: cmeq v3.8h, v3.8h, v5.8h ; GISEL-NEXT: cmeq v3.8h, v3.8h, v5.8h
; GISEL-NEXT: uzp2 v2.8h, v2.8h, v4.8h ; GISEL-NEXT: uzp2 v2.8h, v2.8h, v4.8h
; GISEL-NEXT: ldr q4, [x8, :lo12:.LCPI1_1]
; GISEL-NEXT: shl v3.8h, v3.8h, #15 ; GISEL-NEXT: shl v3.8h, v3.8h, #15
; GISEL-NEXT: add v1.8h, v2.8h, v1.8h ; GISEL-NEXT: add v1.8h, v2.8h, v1.8h
; GISEL-NEXT: neg v2.8h, v4.8h ; GISEL-NEXT: neg v2.8h, v6.8h
; GISEL-NEXT: ushl v1.8h, v1.8h, v2.8h ; GISEL-NEXT: ushl v1.8h, v1.8h, v2.8h
; GISEL-NEXT: sshr v2.8h, v3.8h, #15 ; GISEL-NEXT: sshr v2.8h, v3.8h, #15
; GISEL-NEXT: bif v0.16b, v1.16b, v2.16b ; GISEL-NEXT: bif v0.16b, v1.16b, v2.16b
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%1 = udiv <8 x i16> %x, <i16 23, i16 34, i16 -23, i16 56, i16 128, i16 -1, i16 -256, i16 -32768> %1 = udiv <8 x i16> %x, <i16 23, i16 34, i16 -23, i16 56, i16 128, i16 -1, i16 -256, i16 -32768>
ret <8 x i16> %1 ret <8 x i16> %1
} }
define <8 x i16> @combine_vec_udiv_nonuniform2(<8 x i16> %x) { define <8 x i16> @combine_vec_udiv_nonuniform2(<8 x i16> %x) {
; SDAG-LABEL: combine_vec_udiv_nonuniform2: ; SDAG-LABEL: combine_vec_udiv_nonuniform2:
; SDAG: // %bb.0: ; SDAG: // %bb.0:
; SDAG-NEXT: adrp x8, .LCPI2_0 ; SDAG-NEXT: adrp x8, .LCPI2_0
; SDAG-NEXT: adrp x9, .LCPI2_1 ; SDAG-NEXT: adrp x9, .LCPI2_1
; SDAG-NEXT: ldr q1, [x8, :lo12:.LCPI2_0] ; SDAG-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]
; SDAG-NEXT: adrp x8, .LCPI2_2 ; SDAG-NEXT: adrp x8, .LCPI2_2
; SDAG-NEXT: ldr q2, [x9, :lo12:.LCPI2_1] ; SDAG-NEXT: ldr q2, [x9, :lo12:.LCPI2_1]
; SDAG-NEXT: ushl v0.8h, v0.8h, v1.8h ; SDAG-NEXT: ushl v0.8h, v0.8h, v1.8h
; SDAG-NEXT: umull2 v1.4s, v0.8h, v2.8h ; SDAG-NEXT: umull2 v1.4s, v0.8h, v2.8h
; SDAG-NEXT: umull v0.4s, v0.4h, v2.4h ; SDAG-NEXT: umull v0.4s, v0.4h, v2.4h
; SDAG-NEXT: ldr q2, [x8, :lo12:.LCPI2_2]
; SDAG-NEXT: uzp2 v0.8h, v0.8h, v1.8h ; SDAG-NEXT: uzp2 v0.8h, v0.8h, v1.8h
; SDAG-NEXT: ldr q1, [x8, :lo12:.LCPI2_2] ; SDAG-NEXT: ushl v0.8h, v0.8h, v2.8h
; SDAG-NEXT: ushl v0.8h, v0.8h, v1.8h
; SDAG-NEXT: ret ; SDAG-NEXT: ret
; ;
; GISEL-LABEL: combine_vec_udiv_nonuniform2: ; GISEL-LABEL: combine_vec_udiv_nonuniform2:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: adrp x8, .LCPI2_3 ; GISEL-NEXT: adrp x8, .LCPI2_3
; GISEL-NEXT: adrp x9, .LCPI2_4 ; GISEL-NEXT: adrp x9, .LCPI2_4
; GISEL-NEXT: adrp x10, .LCPI2_0
; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI2_3] ; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI2_3]
; GISEL-NEXT: adrp x8, .LCPI2_2 ; GISEL-NEXT: adrp x8, .LCPI2_2
; GISEL-NEXT: ldr q4, [x10, :lo12:.LCPI2_0] ; GISEL-NEXT: ldr q2, [x9, :lo12:.LCPI2_4]
; GISEL-NEXT: adrp x9, .LCPI2_0
; GISEL-NEXT: neg v1.8h, v1.8h ; GISEL-NEXT: neg v1.8h, v1.8h
; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI2_2] ; GISEL-NEXT: ldr q3, [x8, :lo12:.LCPI2_2]
; GISEL-NEXT: adrp x8, .LCPI2_1 ; GISEL-NEXT: adrp x8, .LCPI2_1
; GISEL-NEXT: ldr q4, [x9, :lo12:.LCPI2_0]
; GISEL-NEXT: ushl v1.8h, v0.8h, v1.8h ; GISEL-NEXT: ushl v1.8h, v0.8h, v1.8h
; GISEL-NEXT: umull2 v3.4s, v1.8h, v2.8h ; GISEL-NEXT: umull2 v5.4s, v1.8h, v3.8h
; GISEL-NEXT: ldr q5, [x8, :lo12:.LCPI2_1] ; GISEL-NEXT: umull v1.4s, v1.4h, v3.4h
; GISEL-NEXT: umull v1.4s, v1.4h, v2.4h ; GISEL-NEXT: ldr q3, [x8, :lo12:.LCPI2_1]
; GISEL-NEXT: ldr q2, [x9, :lo12:.LCPI2_4]
; GISEL-NEXT: cmeq v2.8h, v2.8h, v4.8h ; GISEL-NEXT: cmeq v2.8h, v2.8h, v4.8h
; GISEL-NEXT: uzp2 v1.8h, v1.8h, v3.8h ; GISEL-NEXT: neg v3.8h, v3.8h
; GISEL-NEXT: neg v3.8h, v5.8h
; GISEL-NEXT: shl v2.8h, v2.8h, #15 ; GISEL-NEXT: shl v2.8h, v2.8h, #15
; GISEL-NEXT: ushl v1.8h, v1.8h, v3.8h ; GISEL-NEXT: uzp2 v1.8h, v1.8h, v5.8h
; GISEL-NEXT: sshr v2.8h, v2.8h, #15 ; GISEL-NEXT: sshr v2.8h, v2.8h, #15
; GISEL-NEXT: ushl v1.8h, v1.8h, v3.8h
; GISEL-NEXT: bif v0.16b, v1.16b, v2.16b ; GISEL-NEXT: bif v0.16b, v1.16b, v2.16b
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%1 = udiv <8 x i16> %x, <i16 -34, i16 35, i16 36, i16 -37, i16 38, i16 -39, i16 40, i16 -41> %1 = udiv <8 x i16> %x, <i16 -34, i16 35, i16 36, i16 -37, i16 38, i16 -39, i16 40, i16 -41>
ret <8 x i16> %1 ret <8 x i16> %1
} }
define <8 x i16> @combine_vec_udiv_nonuniform3(<8 x i16> %x) { define <8 x i16> @combine_vec_udiv_nonuniform3(<8 x i16> %x) {
; SDAG-LABEL: combine_vec_udiv_nonuniform3: ; SDAG-LABEL: combine_vec_udiv_nonuniform3:
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; SDAG-NEXT: ret ; SDAG-NEXT: ret
; ;
; GISEL-LABEL: combine_vec_udiv_nonuniform3: ; GISEL-LABEL: combine_vec_udiv_nonuniform3:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: adrp x8, .LCPI3_2 ; GISEL-NEXT: adrp x8, .LCPI3_2
; GISEL-NEXT: adrp x9, .LCPI3_0 ; GISEL-NEXT: adrp x9, .LCPI3_0
; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI3_2] ; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI3_2]
; GISEL-NEXT: adrp x8, .LCPI3_3 ; GISEL-NEXT: adrp x8, .LCPI3_3
; GISEL-NEXT: ldr q3, [x9, :lo12:.LCPI3_0] ; GISEL-NEXT: ldr q4, [x9, :lo12:.LCPI3_0]
; GISEL-NEXT: umull2 v2.4s, v0.8h, v1.8h ; GISEL-NEXT: umull2 v2.4s, v0.8h, v1.8h
; GISEL-NEXT: ldr q3, [x8, :lo12:.LCPI3_3]
; GISEL-NEXT: umull v1.4s, v0.4h, v1.4h ; GISEL-NEXT: umull v1.4s, v0.4h, v1.4h
; GISEL-NEXT: uzp2 v1.8h, v1.8h, v2.8h
; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI3_3]
; GISEL-NEXT: adrp x8, .LCPI3_1 ; GISEL-NEXT: adrp x8, .LCPI3_1
; GISEL-NEXT: cmeq v2.8h, v2.8h, v3.8h ; GISEL-NEXT: cmeq v3.8h, v3.8h, v4.8h
; GISEL-NEXT: sub v4.8h, v0.8h, v1.8h ; GISEL-NEXT: ldr q4, [x8, :lo12:.LCPI3_1]
; GISEL-NEXT: ldr q3, [x8, :lo12:.LCPI3_1] ; GISEL-NEXT: uzp2 v1.8h, v1.8h, v2.8h
; GISEL-NEXT: shl v2.8h, v2.8h, #15 ; GISEL-NEXT: shl v3.8h, v3.8h, #15
; GISEL-NEXT: usra v1.8h, v4.8h, #1 ; GISEL-NEXT: sub v2.8h, v0.8h, v1.8h
; GISEL-NEXT: neg v3.8h, v3.8h ; GISEL-NEXT: usra v1.8h, v2.8h, #1
; GISEL-NEXT: sshr v2.8h, v2.8h, #15 ; GISEL-NEXT: neg v2.8h, v4.8h
; GISEL-NEXT: ushl v1.8h, v1.8h, v3.8h ; GISEL-NEXT: ushl v1.8h, v1.8h, v2.8h
; GISEL-NEXT: sshr v2.8h, v3.8h, #15
; GISEL-NEXT: bif v0.16b, v1.16b, v2.16b ; GISEL-NEXT: bif v0.16b, v1.16b, v2.16b
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%1 = udiv <8 x i16> %x, <i16 7, i16 23, i16 25, i16 27, i16 31, i16 47, i16 63, i16 127> %1 = udiv <8 x i16> %x, <i16 7, i16 23, i16 25, i16 27, i16 31, i16 47, i16 63, i16 127>
ret <8 x i16> %1 ret <8 x i16> %1
} }
define <16 x i8> @combine_vec_udiv_nonuniform4(<16 x i8> %x) { define <16 x i8> @combine_vec_udiv_nonuniform4(<16 x i8> %x) {
; SDAG-LABEL: combine_vec_udiv_nonuniform4: ; SDAG-LABEL: combine_vec_udiv_nonuniform4:
; SDAG: // %bb.0: ; SDAG: // %bb.0:
; SDAG-NEXT: adrp x8, .LCPI4_0 ; SDAG-NEXT: adrp x8, .LCPI4_0
; SDAG-NEXT: adrp x9, .LCPI4_2 ; SDAG-NEXT: adrp x9, .LCPI4_2
; SDAG-NEXT: ldr q1, [x8, :lo12:.LCPI4_0] ; SDAG-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]
; SDAG-NEXT: adrp x8, .LCPI4_1 ; SDAG-NEXT: adrp x8, .LCPI4_1
; SDAG-NEXT: ldr q3, [x9, :lo12:.LCPI4_2]
; SDAG-NEXT: umull2 v2.8h, v0.16b, v1.16b ; SDAG-NEXT: umull2 v2.8h, v0.16b, v1.16b
; SDAG-NEXT: ldr q3, [x8, :lo12:.LCPI4_1]
; SDAG-NEXT: umull v1.8h, v0.8b, v1.8b ; SDAG-NEXT: umull v1.8h, v0.8b, v1.8b
; SDAG-NEXT: uzp2 v1.16b, v1.16b, v2.16b
; SDAG-NEXT: ldr q2, [x8, :lo12:.LCPI4_1]
; SDAG-NEXT: adrp x8, .LCPI4_3 ; SDAG-NEXT: adrp x8, .LCPI4_3
; SDAG-NEXT: ushl v1.16b, v1.16b, v2.16b ; SDAG-NEXT: uzp2 v1.16b, v1.16b, v2.16b
; SDAG-NEXT: ldr q2, [x8, :lo12:.LCPI4_3] ; SDAG-NEXT: ldr q2, [x9, :lo12:.LCPI4_2]
; SDAG-NEXT: and v1.16b, v1.16b, v3.16b ; SDAG-NEXT: ushl v1.16b, v1.16b, v3.16b
; SDAG-NEXT: and v0.16b, v0.16b, v2.16b ; SDAG-NEXT: ldr q3, [x8, :lo12:.LCPI4_3]
; SDAG-NEXT: and v1.16b, v1.16b, v2.16b
; SDAG-NEXT: and v0.16b, v0.16b, v3.16b
; SDAG-NEXT: orr v0.16b, v0.16b, v1.16b ; SDAG-NEXT: orr v0.16b, v0.16b, v1.16b
; SDAG-NEXT: ret ; SDAG-NEXT: ret
; ;
; GISEL-LABEL: combine_vec_udiv_nonuniform4: ; GISEL-LABEL: combine_vec_udiv_nonuniform4:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: adrp x8, .LCPI4_2 ; GISEL-NEXT: adrp x8, .LCPI4_2
; GISEL-NEXT: adrp x9, .LCPI4_0 ; GISEL-NEXT: adrp x9, .LCPI4_3
; GISEL-NEXT: adrp x10, .LCPI4_0
; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI4_2] ; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI4_2]
; GISEL-NEXT: adrp x8, .LCPI4_3
; GISEL-NEXT: ldr q4, [x9, :lo12:.LCPI4_0]
; GISEL-NEXT: umull2 v2.8h, v0.16b, v1.16b
; GISEL-NEXT: ldr q3, [x8, :lo12:.LCPI4_3]
; GISEL-NEXT: umull v1.8h, v0.8b, v1.8b
; GISEL-NEXT: adrp x8, .LCPI4_1 ; GISEL-NEXT: adrp x8, .LCPI4_1
; GISEL-NEXT: cmeq v3.16b, v3.16b, v4.16b ; GISEL-NEXT: ldr q2, [x9, :lo12:.LCPI4_3]
; GISEL-NEXT: uzp2 v1.16b, v1.16b, v2.16b ; GISEL-NEXT: ldr q3, [x10, :lo12:.LCPI4_0]
; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI4_1] ; GISEL-NEXT: umull2 v4.8h, v0.16b, v1.16b
; GISEL-NEXT: shl v3.16b, v3.16b, #7 ; GISEL-NEXT: umull v1.8h, v0.8b, v1.8b
; GISEL-NEXT: neg v2.16b, v2.16b ; GISEL-NEXT: cmeq v2.16b, v2.16b, v3.16b
; GISEL-NEXT: ushl v1.16b, v1.16b, v2.16b ; GISEL-NEXT: ldr q3, [x8, :lo12:.LCPI4_1]
; GISEL-NEXT: sshr v2.16b, v3.16b, #7 ; GISEL-NEXT: shl v2.16b, v2.16b, #7
; GISEL-NEXT: uzp2 v1.16b, v1.16b, v4.16b
; GISEL-NEXT: neg v3.16b, v3.16b
; GISEL-NEXT: sshr v2.16b, v2.16b, #7
; GISEL-NEXT: ushl v1.16b, v1.16b, v3.16b
; GISEL-NEXT: bif v0.16b, v1.16b, v2.16b ; GISEL-NEXT: bif v0.16b, v1.16b, v2.16b
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%div = udiv <16 x i8> %x, <i8 -64, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> %div = udiv <16 x i8> %x, <i8 -64, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %div ret <16 x i8> %div
} }
define <8 x i16> @pr38477(<8 x i16> %a0) { define <8 x i16> @pr38477(<8 x i16> %a0) {
; SDAG-LABEL: pr38477: ; SDAG-LABEL: pr38477:
Show All 20 Lines
; SDAG-NEXT: and v0.16b, v0.16b, v2.16b ; SDAG-NEXT: and v0.16b, v0.16b, v2.16b
; SDAG-NEXT: and v1.16b, v1.16b, v4.16b ; SDAG-NEXT: and v1.16b, v1.16b, v4.16b
; SDAG-NEXT: orr v0.16b, v0.16b, v1.16b ; SDAG-NEXT: orr v0.16b, v0.16b, v1.16b
; SDAG-NEXT: ret ; SDAG-NEXT: ret
; ;
; GISEL-LABEL: pr38477: ; GISEL-LABEL: pr38477:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: adrp x8, .LCPI5_3 ; GISEL-NEXT: adrp x8, .LCPI5_3
; GISEL-NEXT: adrp x9, .LCPI5_0 ; GISEL-NEXT: adrp x9, .LCPI5_4
; GISEL-NEXT: adrp x10, .LCPI5_0
; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI5_3] ; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI5_3]
; GISEL-NEXT: adrp x8, .LCPI5_2 ; GISEL-NEXT: adrp x8, .LCPI5_2
; GISEL-NEXT: ldr q5, [x9, :lo12:.LCPI5_0] ; GISEL-NEXT: ldr q5, [x10, :lo12:.LCPI5_0]
; GISEL-NEXT: umull2 v2.4s, v0.8h, v1.8h ; GISEL-NEXT: umull2 v2.4s, v0.8h, v1.8h
; GISEL-NEXT: umull v1.4s, v0.4h, v1.4h ; GISEL-NEXT: umull v1.4s, v0.4h, v1.4h
; GISEL-NEXT: uzp2 v1.8h, v1.8h, v2.8h ; GISEL-NEXT: uzp2 v1.8h, v1.8h, v2.8h
; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI5_2] ; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI5_2]
; GISEL-NEXT: adrp x8, .LCPI5_4 ; GISEL-NEXT: adrp x8, .LCPI5_1
; GISEL-NEXT: sub v3.8h, v0.8h, v1.8h ; GISEL-NEXT: sub v3.8h, v0.8h, v1.8h
; GISEL-NEXT: umull2 v4.4s, v3.8h, v2.8h ; GISEL-NEXT: umull2 v4.4s, v3.8h, v2.8h
; GISEL-NEXT: ldr q6, [x8, :lo12:.LCPI5_1]
; GISEL-NEXT: umull v2.4s, v3.4h, v2.4h ; GISEL-NEXT: umull v2.4s, v3.4h, v2.4h
; GISEL-NEXT: ldr q3, [x8, :lo12:.LCPI5_4] ; GISEL-NEXT: ldr q3, [x9, :lo12:.LCPI5_4]
; GISEL-NEXT: adrp x8, .LCPI5_1
; GISEL-NEXT: cmeq v3.8h, v3.8h, v5.8h ; GISEL-NEXT: cmeq v3.8h, v3.8h, v5.8h
; GISEL-NEXT: uzp2 v2.8h, v2.8h, v4.8h ; GISEL-NEXT: uzp2 v2.8h, v2.8h, v4.8h
; GISEL-NEXT: ldr q4, [x8, :lo12:.LCPI5_1]
; GISEL-NEXT: shl v3.8h, v3.8h, #15 ; GISEL-NEXT: shl v3.8h, v3.8h, #15
; GISEL-NEXT: add v1.8h, v2.8h, v1.8h ; GISEL-NEXT: add v1.8h, v2.8h, v1.8h
; GISEL-NEXT: neg v2.8h, v4.8h ; GISEL-NEXT: neg v2.8h, v6.8h
; GISEL-NEXT: ushl v1.8h, v1.8h, v2.8h ; GISEL-NEXT: ushl v1.8h, v1.8h, v2.8h
; GISEL-NEXT: sshr v2.8h, v3.8h, #15 ; GISEL-NEXT: sshr v2.8h, v3.8h, #15
; GISEL-NEXT: bif v0.16b, v1.16b, v2.16b ; GISEL-NEXT: bif v0.16b, v1.16b, v2.16b
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%1 = udiv <8 x i16> %a0, <i16 1, i16 119, i16 73, i16 -111, i16 -3, i16 118, i16 32, i16 31> %1 = udiv <8 x i16> %a0, <i16 1, i16 119, i16 73, i16 -111, i16 -3, i16 118, i16 32, i16 31>
ret <8 x i16> %1 ret <8 x i16> %1
} }

llvm/test/CodeGen/AArch64/aarch64-avoid-illegal-extract-subvector.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -o -| FileCheck %s ; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -o -| FileCheck %s
define <2 x i64> @test1(<4 x i32> %x) #0 { define <2 x i64> @test1(<4 x i32> %x) #0 {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: mov w9, v0.s[2] ; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: mov w8, v0.s[2]
; CHECK-NEXT: mov v0.d[1], x9 ; CHECK-NEXT: mov v1.d[1], x8
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%i1 = extractelement <4 x i32> %x, i32 1 %i1 = extractelement <4 x i32> %x, i32 1
%zi1 = zext i32 %i1 to i64 %zi1 = zext i32 %i1 to i64
%i2 = extractelement <4 x i32> %x, i32 2 %i2 = extractelement <4 x i32> %x, i32 2
%zi2 = zext i32 %i2 to i64 %zi2 = zext i32 %i2 to i64
%v1 = insertelement <2 x i64> undef, i64 %zi1, i32 0 %v1 = insertelement <2 x i64> undef, i64 %zi1, i32 0
%v2 = insertelement <2 x i64> %v1, i64 %zi2, i32 1 %v2 = insertelement <2 x i64> %v1, i64 %zi2, i32 1
ret <2 x i64> %v2 ret <2 x i64> %v2
} }
define <4 x i64> @test2(<4 x i32> %0) { define <4 x i64> @test2(<4 x i32> %0) {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, .LCPI1_0 ; CHECK-NEXT: adrp x8, .LCPI1_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: mov w9, v0.s[2]
; CHECK-NEXT: fmov d1, x8 ; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: mov v1.d[1], x9 ; CHECK-NEXT: mov w8, v0.s[2]
; CHECK-NEXT: mov v1.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%1 = add <4 x i32> %0, <i32 -4, i32 -8, i32 -12, i32 -16> %1 = add <4 x i32> %0, <i32 -4, i32 -8, i32 -12, i32 -16>
%2 = extractelement <4 x i32> %1, i32 1 %2 = extractelement <4 x i32> %1, i32 1
%zext1 = zext i32 %2 to i64 %zext1 = zext i32 %2 to i64
%3 = extractelement <4 x i32> %1, i32 2 %3 = extractelement <4 x i32> %1, i32 2
%zext2 = zext i32 %3 to i64 %zext2 = zext i32 %3 to i64
%4 = insertelement <4 x i64> undef, i64 %zext1, i32 2 %4 = insertelement <4 x i64> undef, i64 %zext1, i32 2
%5 = insertelement <4 x i64> %4, i64 %zext2, i32 3 %5 = insertelement <4 x i64> %4, i64 %zext2, i32 3
ret <4 x i64> %5 ret <4 x i64> %5
} }

llvm/test/CodeGen/AArch64/aarch64-be-bv.ll

Show First 20 Lines • Show All 161 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
store <8 x i16> %rv, <8 x i16>* @vec_v8i16 store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void ret void
} }
define dso_local void @fmov_modimm_t11() nounwind { define dso_local void @fmov_modimm_t11() nounwind {
; CHECK-LABEL: fmov_modimm_t11: ; CHECK-LABEL: fmov_modimm_t11:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, vec_v8i16 ; CHECK-NEXT: adrp x8, vec_v8i16
; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
; CHECK-NEXT: fmov v1.4s, #3.00000000 ; CHECK-NEXT: fmov v1.4s, #3.00000000
; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
; CHECK-NEXT: ld1 { v0.8h }, [x8] ; CHECK-NEXT: ld1 { v0.8h }, [x8]
; CHECK-NEXT: add v0.8h, v0.8h, v1.8h ; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
; CHECK-NEXT: st1 { v0.8h }, [x8] ; CHECK-NEXT: st1 { v0.8h }, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16 %in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448> %rv = add <8 x i16> %in, <i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16 store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void ret void
} }
define dso_local void @fmov_modimm_t12() nounwind { define dso_local void @fmov_modimm_t12() nounwind {
; CHECK-LABEL: fmov_modimm_t12: ; CHECK-LABEL: fmov_modimm_t12:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, vec_v8i16 ; CHECK-NEXT: adrp x8, vec_v8i16
; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
; CHECK-NEXT: fmov v1.2d, #0.17968750 ; CHECK-NEXT: fmov v1.2d, #0.17968750
; CHECK-NEXT: add x8, x8, :lo12:vec_v8i16
; CHECK-NEXT: ld1 { v0.8h }, [x8] ; CHECK-NEXT: ld1 { v0.8h }, [x8]
; CHECK-NEXT: add v0.8h, v0.8h, v1.8h ; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
; CHECK-NEXT: st1 { v0.8h }, [x8] ; CHECK-NEXT: st1 { v0.8h }, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%in = load <8 x i16>, <8 x i16>* @vec_v8i16 %in = load <8 x i16>, <8 x i16>* @vec_v8i16
%rv = add <8 x i16> %in, <i16 0, i16 0, i16 0, i16 16327, i16 0, i16 0, i16 0, i16 16327> %rv = add <8 x i16> %in, <i16 0, i16 0, i16 0, i16 16327, i16 0, i16 0, i16 0, i16 16327>
store <8 x i16> %rv, <8 x i16>* @vec_v8i16 store <8 x i16> %rv, <8 x i16>* @vec_v8i16
ret void ret void
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llvm/test/CodeGen/AArch64/aarch64-smull.ll

Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%tmp5 = mul <8 x i16> %tmp3, %tmp4 %tmp5 = mul <8 x i16> %tmp3, %tmp4
%and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %and ret <8 x i16> %and
} }
define <4 x i32> @amull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <4 x i32> @amull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: amull_v4i16_v4i32: ; CHECK-LABEL: amull_v4i16_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d1, [x0] ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d2, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: movi v0.2d, #0x00ffff0000ffff ; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-NEXT: smull v1.4s, v1.4h, v2.4h ; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v0.16b, v1.16b, v0.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <4 x i16>, <4 x i16>* %A %tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B %tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = zext <4 x i16> %tmp1 to <4 x i32> %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
%tmp4 = zext <4 x i16> %tmp2 to <4 x i32> %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
%tmp5 = mul <4 x i32> %tmp3, %tmp4 %tmp5 = mul <4 x i32> %tmp3, %tmp4
%and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535> %and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %and ret <4 x i32> %and
} }
define <2 x i64> @amull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x i64> @amull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-LABEL: amull_v2i32_v2i64: ; CHECK-LABEL: amull_v2i32_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d1, [x0] ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d2, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: movi v0.2d, #0x000000ffffffff ; CHECK-NEXT: smull v0.2d, v0.2s, v1.2s
; CHECK-NEXT: smull v1.2d, v1.2s, v2.2s ; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
; CHECK-NEXT: and v0.16b, v1.16b, v0.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <2 x i32>, <2 x i32>* %A %tmp1 = load <2 x i32>, <2 x i32>* %A
%tmp2 = load <2 x i32>, <2 x i32>* %B %tmp2 = load <2 x i32>, <2 x i32>* %B
%tmp3 = zext <2 x i32> %tmp1 to <2 x i64> %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
%tmp4 = zext <2 x i32> %tmp2 to <2 x i64> %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
%tmp5 = mul <2 x i64> %tmp3, %tmp4 %tmp5 = mul <2 x i64> %tmp3, %tmp4
%and = and <2 x i64> %tmp5, <i64 4294967295, i64 4294967295> %and = and <2 x i64> %tmp5, <i64 4294967295, i64 4294967295>
ret <2 x i64> %and ret <2 x i64> %and
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%tmp7 = add <8 x i16> %tmp1, %tmp6 %tmp7 = add <8 x i16> %tmp1, %tmp6
%and = and <8 x i16> %tmp7, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <8 x i16> %tmp7, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %and ret <8 x i16> %and
} }
define <4 x i32> @amlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { define <4 x i32> @amlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
; CHECK-LABEL: amlal_v4i16_v4i32: ; CHECK-LABEL: amlal_v4i16_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d0, [x1]
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: ldr q1, [x0]
; CHECK-NEXT: ldr d3, [x2] ; CHECK-NEXT: ldr d2, [x2]
; CHECK-NEXT: smlal v1.4s, v0.4h, v2.4h
; CHECK-NEXT: movi v0.2d, #0x00ffff0000ffff ; CHECK-NEXT: movi v0.2d, #0x00ffff0000ffff
; CHECK-NEXT: smlal v2.4s, v1.4h, v3.4h ; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
; CHECK-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <4 x i32>, <4 x i32>* %A %tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B %tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = load <4 x i16>, <4 x i16>* %C %tmp3 = load <4 x i16>, <4 x i16>* %C
%tmp4 = zext <4 x i16> %tmp2 to <4 x i32> %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
%tmp5 = zext <4 x i16> %tmp3 to <4 x i32> %tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
%tmp6 = mul <4 x i32> %tmp4, %tmp5 %tmp6 = mul <4 x i32> %tmp4, %tmp5
%tmp7 = add <4 x i32> %tmp1, %tmp6 %tmp7 = add <4 x i32> %tmp1, %tmp6
%and = and <4 x i32> %tmp7, <i32 65535, i32 65535, i32 65535, i32 65535> %and = and <4 x i32> %tmp7, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %and ret <4 x i32> %and
} }
define <2 x i64> @amlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { define <2 x i64> @amlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
; CHECK-LABEL: amlal_v2i32_v2i64: ; CHECK-LABEL: amlal_v2i32_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d0, [x1]
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: ldr q1, [x0]
; CHECK-NEXT: ldr d3, [x2] ; CHECK-NEXT: ldr d2, [x2]
; CHECK-NEXT: smlal v1.2d, v0.2s, v2.2s
; CHECK-NEXT: movi v0.2d, #0x000000ffffffff ; CHECK-NEXT: movi v0.2d, #0x000000ffffffff
; CHECK-NEXT: smlal v2.2d, v1.2s, v3.2s ; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
; CHECK-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <2 x i64>, <2 x i64>* %A %tmp1 = load <2 x i64>, <2 x i64>* %A
%tmp2 = load <2 x i32>, <2 x i32>* %B %tmp2 = load <2 x i32>, <2 x i32>* %B
%tmp3 = load <2 x i32>, <2 x i32>* %C %tmp3 = load <2 x i32>, <2 x i32>* %C
%tmp4 = zext <2 x i32> %tmp2 to <2 x i64> %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
%tmp5 = zext <2 x i32> %tmp3 to <2 x i64> %tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
%tmp6 = mul <2 x i64> %tmp4, %tmp5 %tmp6 = mul <2 x i64> %tmp4, %tmp5
%tmp7 = add <2 x i64> %tmp1, %tmp6 %tmp7 = add <2 x i64> %tmp1, %tmp6
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%tmp7 = sub <8 x i16> %tmp1, %tmp6 %tmp7 = sub <8 x i16> %tmp1, %tmp6
%and = and <8 x i16> %tmp7, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <8 x i16> %tmp7, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %and ret <8 x i16> %and
} }
define <4 x i32> @amlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { define <4 x i32> @amlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
; CHECK-LABEL: amlsl_v4i16_v4i32: ; CHECK-LABEL: amlsl_v4i16_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d0, [x1]
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: ldr q1, [x0]
; CHECK-NEXT: ldr d3, [x2] ; CHECK-NEXT: ldr d2, [x2]
; CHECK-NEXT: smlsl v1.4s, v0.4h, v2.4h
; CHECK-NEXT: movi v0.2d, #0x00ffff0000ffff ; CHECK-NEXT: movi v0.2d, #0x00ffff0000ffff
; CHECK-NEXT: smlsl v2.4s, v1.4h, v3.4h ; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
; CHECK-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <4 x i32>, <4 x i32>* %A %tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B %tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = load <4 x i16>, <4 x i16>* %C %tmp3 = load <4 x i16>, <4 x i16>* %C
%tmp4 = zext <4 x i16> %tmp2 to <4 x i32> %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
%tmp5 = zext <4 x i16> %tmp3 to <4 x i32> %tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
%tmp6 = mul <4 x i32> %tmp4, %tmp5 %tmp6 = mul <4 x i32> %tmp4, %tmp5
%tmp7 = sub <4 x i32> %tmp1, %tmp6 %tmp7 = sub <4 x i32> %tmp1, %tmp6
%and = and <4 x i32> %tmp7, <i32 65535, i32 65535, i32 65535, i32 65535> %and = and <4 x i32> %tmp7, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %and ret <4 x i32> %and
} }
define <2 x i64> @amlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { define <2 x i64> @amlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
; CHECK-LABEL: amlsl_v2i32_v2i64: ; CHECK-LABEL: amlsl_v2i32_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d0, [x1]
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: ldr q1, [x0]
; CHECK-NEXT: ldr d3, [x2] ; CHECK-NEXT: ldr d2, [x2]
; CHECK-NEXT: smlsl v1.2d, v0.2s, v2.2s
; CHECK-NEXT: movi v0.2d, #0x000000ffffffff ; CHECK-NEXT: movi v0.2d, #0x000000ffffffff
; CHECK-NEXT: smlsl v2.2d, v1.2s, v3.2s ; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
; CHECK-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <2 x i64>, <2 x i64>* %A %tmp1 = load <2 x i64>, <2 x i64>* %A
%tmp2 = load <2 x i32>, <2 x i32>* %B %tmp2 = load <2 x i32>, <2 x i32>* %B
%tmp3 = load <2 x i32>, <2 x i32>* %C %tmp3 = load <2 x i32>, <2 x i32>* %C
%tmp4 = zext <2 x i32> %tmp2 to <2 x i64> %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
%tmp5 = zext <2 x i32> %tmp3 to <2 x i64> %tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
%tmp6 = mul <2 x i64> %tmp4, %tmp5 %tmp6 = mul <2 x i64> %tmp4, %tmp5
%tmp7 = sub <2 x i64> %tmp1, %tmp6 %tmp7 = sub <2 x i64> %tmp1, %tmp6
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%and = and <8 x i16> %tmp4, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <8 x i16> %tmp4, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %and ret <8 x i16> %and
} }
define <4 x i32> @amull_extvec_v4i16_v4i32(<4 x i16> %arg) nounwind { define <4 x i32> @amull_extvec_v4i16_v4i32(<4 x i16> %arg) nounwind {
; CHECK-LABEL: amull_extvec_v4i16_v4i32: ; CHECK-LABEL: amull_extvec_v4i16_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1234 ; CHECK-NEXT: mov w8, #1234
; CHECK-NEXT: dup v1.4h, w8
; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff ; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
; CHECK-NEXT: dup v2.4h, w8
; CHECK-NEXT: smull v0.4s, v0.4h, v2.4h
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = zext <4 x i16> %arg to <4 x i32> %tmp3 = zext <4 x i16> %arg to <4 x i32>
%tmp4 = mul <4 x i32> %tmp3, <i32 1234, i32 1234, i32 1234, i32 1234> %tmp4 = mul <4 x i32> %tmp3, <i32 1234, i32 1234, i32 1234, i32 1234>
%and = and <4 x i32> %tmp4, <i32 65535, i32 65535, i32 65535, i32 65535> %and = and <4 x i32> %tmp4, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %and ret <4 x i32> %and
} }
define <2 x i64> @amull_extvec_v2i32_v2i64(<2 x i32> %arg) nounwind { define <2 x i64> @amull_extvec_v2i32_v2i64(<2 x i32> %arg) nounwind {
; CHECK-LABEL: amull_extvec_v2i32_v2i64: ; CHECK-LABEL: amull_extvec_v2i32_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1234 ; CHECK-NEXT: mov w8, #1234
; CHECK-NEXT: dup v1.2s, w8
; CHECK-NEXT: smull v0.2d, v0.2s, v1.2s
; CHECK-NEXT: movi v1.2d, #0x000000ffffffff ; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
; CHECK-NEXT: dup v2.2s, w8
; CHECK-NEXT: smull v0.2d, v0.2s, v2.2s
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = zext <2 x i32> %arg to <2 x i64> %tmp3 = zext <2 x i32> %arg to <2 x i64>
%tmp4 = mul <2 x i64> %tmp3, <i64 1234, i64 1234> %tmp4 = mul <2 x i64> %tmp3, <i64 1234, i64 1234>
%and = and <2 x i64> %tmp4, <i64 4294967295, i64 4294967295> %and = and <2 x i64> %tmp4, <i64 4294967295, i64 4294967295>
ret <2 x i64> %and ret <2 x i64> %and
} }
▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%mul = mul <16 x i16> %arg1_ext, %arg2_ext %mul = mul <16 x i16> %arg1_ext, %arg2_ext
%and = and <16 x i16> %mul, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <16 x i16> %mul, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <16 x i16> %and ret <16 x i16> %and
} }
define <8 x i32> @amull2_i16(<8 x i16> %arg1, <8 x i16> %arg2) { define <8 x i32> @amull2_i16(<8 x i16> %arg1, <8 x i16> %arg2) {
; CHECK-LABEL: amull2_i16: ; CHECK-LABEL: amull2_i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
; CHECK-NEXT: smull2 v3.4s, v0.8h, v1.8h ; CHECK-NEXT: smull2 v3.4s, v0.8h, v1.8h
; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h ; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v1.16b, v3.16b, v2.16b ; CHECK-NEXT: and v1.16b, v3.16b, v2.16b
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%arg1_ext = zext <8 x i16> %arg1 to <8 x i32> %arg1_ext = zext <8 x i16> %arg1 to <8 x i32>
%arg2_ext = zext <8 x i16> %arg2 to <8 x i32> %arg2_ext = zext <8 x i16> %arg2 to <8 x i32>
%mul = mul <8 x i32> %arg1_ext, %arg2_ext %mul = mul <8 x i32> %arg1_ext, %arg2_ext
%and = and <8 x i32> %mul, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535> %and = and <8 x i32> %mul, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
ret <8 x i32> %and ret <8 x i32> %and
} }
define <4 x i64> @amull2_i32(<4 x i32> %arg1, <4 x i32> %arg2) { define <4 x i64> @amull2_i32(<4 x i32> %arg1, <4 x i32> %arg2) {
; CHECK-LABEL: amull2_i32: ; CHECK-LABEL: amull2_i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.2d, #0x000000ffffffff
; CHECK-NEXT: smull2 v3.2d, v0.4s, v1.4s ; CHECK-NEXT: smull2 v3.2d, v0.4s, v1.4s
; CHECK-NEXT: smull v0.2d, v0.2s, v1.2s ; CHECK-NEXT: smull v0.2d, v0.2s, v1.2s
; CHECK-NEXT: movi v2.2d, #0x000000ffffffff
; CHECK-NEXT: and v1.16b, v3.16b, v2.16b ; CHECK-NEXT: and v1.16b, v3.16b, v2.16b
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%arg1_ext = zext <4 x i32> %arg1 to <4 x i64> %arg1_ext = zext <4 x i32> %arg1 to <4 x i64>
%arg2_ext = zext <4 x i32> %arg2 to <4 x i64> %arg2_ext = zext <4 x i32> %arg2 to <4 x i64>
%mul = mul <4 x i64> %arg1_ext, %arg2_ext %mul = mul <4 x i64> %arg1_ext, %arg2_ext
%and = and <4 x i64> %mul, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> %and = and <4 x i64> %mul, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
ret <4 x i64> %and ret <4 x i64> %and
} }

llvm/test/CodeGen/AArch64/aarch64-wide-mul.ll

Show First 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
define <16 x i64> @mla_i64(<16 x i8> %a, <16 x i8> %b, <16 x i64> %c) { define <16 x i64> @mla_i64(<16 x i8> %a, <16 x i8> %b, <16 x i64> %c) {
; CHECK-LABEL: mla_i64: ; CHECK-LABEL: mla_i64:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ushll v18.8h, v0.8b, #0 ; CHECK-NEXT: ushll v18.8h, v0.8b, #0
; CHECK-NEXT: ushll2 v0.8h, v0.16b, #0 ; CHECK-NEXT: ushll2 v0.8h, v0.16b, #0
; CHECK-NEXT: ushll v25.8h, v1.8b, #0 ; CHECK-NEXT: ushll v25.8h, v1.8b, #0
; CHECK-NEXT: ushll2 v1.8h, v1.16b, #0 ; CHECK-NEXT: ushll2 v1.8h, v1.16b, #0
; CHECK-NEXT: mov v16.16b, v7.16b
; CHECK-NEXT: mov v17.16b, v6.16b
; CHECK-NEXT: ldp q6, q7, [sp]
; CHECK-NEXT: ushll v19.4s, v18.4h, #0 ; CHECK-NEXT: ushll v19.4s, v18.4h, #0
; CHECK-NEXT: ushll v20.4s, v0.4h, #0 ; CHECK-NEXT: ushll v20.4s, v0.4h, #0
; CHECK-NEXT: ushll2 v18.4s, v18.8h, #0 ; CHECK-NEXT: ushll2 v18.4s, v18.8h, #0
; CHECK-NEXT: ushll v26.4s, v25.4h, #0 ; CHECK-NEXT: ushll v26.4s, v25.4h, #0
; CHECK-NEXT: ushll v27.4s, v1.4h, #0 ; CHECK-NEXT: ushll v27.4s, v1.4h, #0
; CHECK-NEXT: ushll2 v25.4s, v25.8h, #0 ; CHECK-NEXT: ushll2 v25.4s, v25.8h, #0
; CHECK-NEXT: mov v16.16b, v7.16b
; CHECK-NEXT: mov v17.16b, v6.16b
; CHECK-NEXT: ldp q6, q7, [sp]
; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0 ; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0
; CHECK-NEXT: ushll2 v1.4s, v1.8h, #0 ; CHECK-NEXT: ushll2 v1.4s, v1.8h, #0
; CHECK-NEXT: ext v21.16b, v19.16b, v19.16b, #8 ; CHECK-NEXT: ext v21.16b, v19.16b, v19.16b, #8
; CHECK-NEXT: ext v22.16b, v20.16b, v20.16b, #8 ; CHECK-NEXT: ext v22.16b, v20.16b, v20.16b, #8
; CHECK-NEXT: ext v23.16b, v18.16b, v18.16b, #8 ; CHECK-NEXT: ext v23.16b, v18.16b, v18.16b, #8
; CHECK-NEXT: ext v28.16b, v26.16b, v26.16b, #8 ; CHECK-NEXT: ext v28.16b, v26.16b, v26.16b, #8
; CHECK-NEXT: ext v29.16b, v27.16b, v27.16b, #8 ; CHECK-NEXT: ext v29.16b, v27.16b, v27.16b, #8
; CHECK-NEXT: ext v30.16b, v25.16b, v25.16b, #8 ; CHECK-NEXT: ext v30.16b, v25.16b, v25.16b, #8
Show All 24 Lines

llvm/test/CodeGen/AArch64/active_lane_mask.ll

Show First 20 Lines • Show All 436 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <8 x i1> %active.lane.mask ret <8 x i1> %active.lane.mask
} }
define <4 x i1> @lane_mask_v4i1_i8(i8 %index, i8 %TC) { define <4 x i1> @lane_mask_v4i1_i8(i8 %index, i8 %TC) {
; CHECK-LABEL: lane_mask_v4i1_i8: ; CHECK-LABEL: lane_mask_v4i1_i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI25_0 ; CHECK-NEXT: adrp x8, .LCPI25_0
; CHECK-NEXT: dup v0.4h, w0 ; CHECK-NEXT: dup v0.4h, w0
; CHECK-NEXT: movi d2, #0xff00ff00ff00ff ; CHECK-NEXT: dup v2.4h, w1
; CHECK-NEXT: dup v3.4h, w1
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI25_0] ; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI25_0]
; CHECK-NEXT: bic v0.4h, #255, lsl #8 ; CHECK-NEXT: bic v0.4h, #255, lsl #8
; CHECK-NEXT: bic v3.4h, #255, lsl #8 ; CHECK-NEXT: bic v2.4h, #255, lsl #8
; CHECK-NEXT: add v0.4h, v0.4h, v1.4h ; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
; CHECK-NEXT: umin v0.4h, v0.4h, v2.4h ; CHECK-NEXT: movi d1, #0xff00ff00ff00ff
; CHECK-NEXT: cmhi v0.4h, v3.4h, v0.4h ; CHECK-NEXT: umin v0.4h, v0.4h, v1.4h
; CHECK-NEXT: cmhi v0.4h, v2.4h, v0.4h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i8(i8 %index, i8 %TC) %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i8(i8 %index, i8 %TC)
ret <4 x i1> %active.lane.mask ret <4 x i1> %active.lane.mask
} }
define <2 x i1> @lane_mask_v2i1_i8(i8 %index, i8 %TC) { define <2 x i1> @lane_mask_v2i1_i8(i8 %index, i8 %TC) {
; CHECK-LABEL: lane_mask_v2i1_i8: ; CHECK-LABEL: lane_mask_v2i1_i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI26_0 ; CHECK-NEXT: adrp x8, .LCPI26_0
; CHECK-NEXT: movi d0, #0x0000ff000000ff ; CHECK-NEXT: dup v0.2s, w0
; CHECK-NEXT: dup v1.2s, w0 ; CHECK-NEXT: movi d2, #0x0000ff000000ff
; CHECK-NEXT: dup v3.2s, w1 ; CHECK-NEXT: dup v3.2s, w1
; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI26_0] ; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI26_0]
; CHECK-NEXT: and v1.8b, v1.8b, v0.8b ; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
; CHECK-NEXT: add v1.2s, v1.2s, v2.2s ; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
; CHECK-NEXT: umin v1.2s, v1.2s, v0.2s ; CHECK-NEXT: and v1.8b, v3.8b, v2.8b
; CHECK-NEXT: and v0.8b, v3.8b, v0.8b ; CHECK-NEXT: umin v0.2s, v0.2s, v2.2s
; CHECK-NEXT: cmhi v0.2s, v0.2s, v1.2s ; CHECK-NEXT: cmhi v0.2s, v1.2s, v0.2s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i8(i8 %index, i8 %TC) %active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i8(i8 %index, i8 %TC)
ret <2 x i1> %active.lane.mask ret <2 x i1> %active.lane.mask
} }
declare <vscale x 32 x i1> @llvm.get.active.lane.mask.nxv32i1.i32(i32, i32) declare <vscale x 32 x i1> @llvm.get.active.lane.mask.nxv32i1.i32(i32, i32)
declare <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32, i32) declare <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32, i32)
Show All 31 Lines

llvm/test/CodeGen/AArch64/addsub-constant-folding.ll

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; CHECK-NEXT: sub sp, sp, #32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: movi v0.4s, #10
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #10
; CHECK-NEXT: add v0.4s, v1.4s, v0.4s ; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
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; CHECK-NEXT: sub sp, sp, #32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: movi v0.4s, #6
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #6
; CHECK-NEXT: add v0.4s, v1.4s, v0.4s ; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
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; CHECK-NEXT: sub sp, sp, #32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: movi v0.4s, #10
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #10
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
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; CHECK-NEXT: sub sp, sp, #32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: movi v0.4s, #2
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #2
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
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; CHECK-NEXT: sub sp, sp, #32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: movi v0.4s, #10
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #10
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
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; CHECK-NEXT: sub sp, sp, #32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: movi v0.4s, #6
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #6
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
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; CHECK-NEXT: sub sp, sp, #32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: movi v0.4s, #2
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #2
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
Show All 12 Lines

llvm/test/CodeGen/AArch64/arm64-dup.ll

Show First 20 Lines • Show All 440 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5> %r = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
ret <4 x float> %r ret <4 x float> %r
} }
define void @disguised_dup(<4 x float> %x, <4 x float>* %p1, <4 x float>* %p2) { define void @disguised_dup(<4 x float> %x, <4 x float>* %p1, <4 x float>* %p2) {
; CHECK-LABEL: disguised_dup: ; CHECK-LABEL: disguised_dup:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext.16b v1, v0, v0, #12 ; CHECK-NEXT: dup.4s v1, v0[0]
; CHECK-NEXT: dup.4s v0, v0[0] ; CHECK-NEXT: ext.16b v0, v0, v0, #12
; CHECK-NEXT: ext.16b v1, v1, v0, #8 ; CHECK-NEXT: ext.16b v0, v0, v1, #8
; CHECK-NEXT: str q1, [x0] ; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: str q1, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuf = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 0, i32 0> %shuf = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 0, i32 0>
%dup = shufflevector <4 x float> %shuf, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 2, i32 3> %dup = shufflevector <4 x float> %shuf, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 2, i32 3>
store <4 x float> %shuf, <4 x float>* %p1, align 8 store <4 x float> %shuf, <4 x float>* %p1, align 8
store <4 x float> %dup, <4 x float>* %p2, align 8 store <4 x float> %dup, <4 x float>* %p2, align 8
ret void ret void
} }

llvm/test/CodeGen/AArch64/arm64-fcopysign.ll

Show All 30 Linesentry:
%0 = tail call double @copysign(double %x, double %y) nounwind readnone %0 = tail call double @copysign(double %x, double %y) nounwind readnone
ret double %0 ret double %0
} }
; rdar://9545768 ; rdar://9545768
define double @test3(double %a, float %b, float %c) nounwind { define double @test3(double %a, float %b, float %c) nounwind {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: movi.2d v3, #0xffffffffffffffff
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: fadd s1, s1, s2 ; CHECK-NEXT: fadd s1, s1, s2
; CHECK-NEXT: fneg.2d v2, v3 ; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: movi.2d v3, #0xffffffffffffffff
; CHECK-NEXT: fneg.2d v3, v3
; CHECK-NEXT: fcvt d1, s1 ; CHECK-NEXT: fcvt d1, s1
; CHECK-NEXT: bif.16b v0, v1, v2 ; CHECK-NEXT: bif.16b v0, v1, v3
; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = fadd float %b, %c %tmp1 = fadd float %b, %c
%tmp2 = fpext float %tmp1 to double %tmp2 = fpext float %tmp1 to double
%tmp = tail call double @copysign( double %a, double %tmp2 ) nounwind readnone %tmp = tail call double @copysign( double %a, double %tmp2 ) nounwind readnone
ret double %tmp ret double %tmp
} }
Show All 23 Lines

llvm/test/CodeGen/AArch64/arm64-memset-inline.ll

Show First 20 Lines • Show All 179 Lines • ▼ Show 20 Lines
define void @bzero_32_stack() { define void @bzero_32_stack() {
; CHECK-LABEL: bzero_32_stack: ; CHECK-LABEL: bzero_32_stack:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov x0, sp ; CHECK-NEXT: mov x0, sp
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: stp q0, q0, [sp] ; CHECK-NEXT: stp q0, q0, [sp]
; CHECK-NEXT: bl something ; CHECK-NEXT: bl something
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%buf = alloca [32 x i8], align 1 %buf = alloca [32 x i8], align 1
%cast = bitcast [32 x i8]* %buf to i8* %cast = bitcast [32 x i8]* %buf to i8*
call void @llvm.memset.p0i8.i32(i8* %cast, i8 0, i32 32, i1 false) call void @llvm.memset.p0i8.i32(i8* %cast, i8 0, i32 32, i1 false)
call void @something(i8* %cast) call void @something(i8* %cast)
ret void ret void
} }
define void @bzero_40_stack() { define void @bzero_40_stack() {
; CHECK-LABEL: bzero_40_stack: ; CHECK-LABEL: bzero_40_stack:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #64 ; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: str x30, [sp, #48] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #48] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov x0, sp ; CHECK-NEXT: mov x0, sp
; CHECK-NEXT: str xzr, [sp, #32] ; CHECK-NEXT: str xzr, [sp, #32]
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: stp q0, q0, [sp] ; CHECK-NEXT: stp q0, q0, [sp]
; CHECK-NEXT: bl something ; CHECK-NEXT: bl something
; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #64 ; CHECK-NEXT: add sp, sp, #64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%buf = alloca [40 x i8], align 1 %buf = alloca [40 x i8], align 1
%cast = bitcast [40 x i8]* %buf to i8* %cast = bitcast [40 x i8]* %buf to i8*
call void @llvm.memset.p0i8.i32(i8* %cast, i8 0, i32 40, i1 false) call void @llvm.memset.p0i8.i32(i8* %cast, i8 0, i32 40, i1 false)
call void @something(i8* %cast) call void @something(i8* %cast)
ret void ret void
} }
define void @bzero_64_stack() { define void @bzero_64_stack() {
; CHECK-LABEL: bzero_64_stack: ; CHECK-LABEL: bzero_64_stack:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #80 ; CHECK-NEXT: sub sp, sp, #80
; CHECK-NEXT: str x30, [sp, #64] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #64] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 80 ; CHECK-NEXT: .cfi_def_cfa_offset 80
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov x0, sp ; CHECK-NEXT: mov x0, sp
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: stp q0, q0, [sp, #32] ; CHECK-NEXT: stp q0, q0, [sp, #32]
; CHECK-NEXT: stp q0, q0, [sp] ; CHECK-NEXT: stp q0, q0, [sp]
; CHECK-NEXT: bl something ; CHECK-NEXT: bl something
; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #80 ; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%buf = alloca [64 x i8], align 1 %buf = alloca [64 x i8], align 1
%cast = bitcast [64 x i8]* %buf to i8* %cast = bitcast [64 x i8]* %buf to i8*
call void @llvm.memset.p0i8.i32(i8* %cast, i8 0, i32 64, i1 false) call void @llvm.memset.p0i8.i32(i8* %cast, i8 0, i32 64, i1 false)
call void @something(i8* %cast) call void @something(i8* %cast)
ret void ret void
} }
define void @bzero_72_stack() { define void @bzero_72_stack() {
; CHECK-LABEL: bzero_72_stack: ; CHECK-LABEL: bzero_72_stack:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #96 ; CHECK-NEXT: sub sp, sp, #96
; CHECK-NEXT: str x30, [sp, #80] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #80] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 96 ; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov x0, sp ; CHECK-NEXT: mov x0, sp
; CHECK-NEXT: str xzr, [sp, #64] ; CHECK-NEXT: str xzr, [sp, #64]
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: stp q0, q0, [sp, #32] ; CHECK-NEXT: stp q0, q0, [sp, #32]
; CHECK-NEXT: stp q0, q0, [sp] ; CHECK-NEXT: stp q0, q0, [sp]
; CHECK-NEXT: bl something ; CHECK-NEXT: bl something
; CHECK-NEXT: ldr x30, [sp, #80] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #80] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #96 ; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%buf = alloca [72 x i8], align 1 %buf = alloca [72 x i8], align 1
%cast = bitcast [72 x i8]* %buf to i8* %cast = bitcast [72 x i8]* %buf to i8*
call void @llvm.memset.p0i8.i32(i8* %cast, i8 0, i32 72, i1 false) call void @llvm.memset.p0i8.i32(i8* %cast, i8 0, i32 72, i1 false)
call void @something(i8* %cast) call void @something(i8* %cast)
ret void ret void
} }
define void @bzero_128_stack() { define void @bzero_128_stack() {
; CHECK-LABEL: bzero_128_stack: ; CHECK-LABEL: bzero_128_stack:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #144 ; CHECK-NEXT: sub sp, sp, #144
; CHECK-NEXT: str x30, [sp, #128] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #128] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 144 ; CHECK-NEXT: .cfi_def_cfa_offset 144
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov x0, sp ; CHECK-NEXT: mov x0, sp
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: stp q0, q0, [sp, #96] ; CHECK-NEXT: stp q0, q0, [sp, #96]
; CHECK-NEXT: stp q0, q0, [sp, #64] ; CHECK-NEXT: stp q0, q0, [sp, #64]
; CHECK-NEXT: stp q0, q0, [sp, #32] ; CHECK-NEXT: stp q0, q0, [sp, #32]
; CHECK-NEXT: stp q0, q0, [sp] ; CHECK-NEXT: stp q0, q0, [sp]
; CHECK-NEXT: bl something ; CHECK-NEXT: bl something
; CHECK-NEXT: ldr x30, [sp, #128] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #128] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #144 ; CHECK-NEXT: add sp, sp, #144
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%buf = alloca [128 x i8], align 1 %buf = alloca [128 x i8], align 1
%cast = bitcast [128 x i8]* %buf to i8* %cast = bitcast [128 x i8]* %buf to i8*
call void @llvm.memset.p0i8.i32(i8* %cast, i8 0, i32 128, i1 false) call void @llvm.memset.p0i8.i32(i8* %cast, i8 0, i32 128, i1 false)
call void @something(i8* %cast) call void @something(i8* %cast)
ret void ret void
} }
define void @bzero_256_stack() { define void @bzero_256_stack() {
; CHECK-LABEL: bzero_256_stack: ; CHECK-LABEL: bzero_256_stack:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #272 ; CHECK-NEXT: sub sp, sp, #272
; CHECK-NEXT: stp x29, x30, [sp, #256] // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #256] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 272 ; CHECK-NEXT: .cfi_def_cfa_offset 272
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov x0, sp ; CHECK-NEXT: mov x0, sp
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: stp q0, q0, [sp, #224] ; CHECK-NEXT: stp q0, q0, [sp, #224]
; CHECK-NEXT: stp q0, q0, [sp, #192] ; CHECK-NEXT: stp q0, q0, [sp, #192]
; CHECK-NEXT: stp q0, q0, [sp, #160] ; CHECK-NEXT: stp q0, q0, [sp, #160]
; CHECK-NEXT: stp q0, q0, [sp, #128] ; CHECK-NEXT: stp q0, q0, [sp, #128]
; CHECK-NEXT: stp q0, q0, [sp, #96] ; CHECK-NEXT: stp q0, q0, [sp, #96]
; CHECK-NEXT: stp q0, q0, [sp, #64] ; CHECK-NEXT: stp q0, q0, [sp, #64]
; CHECK-NEXT: stp q0, q0, [sp, #32] ; CHECK-NEXT: stp q0, q0, [sp, #32]
; CHECK-NEXT: stp q0, q0, [sp] ; CHECK-NEXT: stp q0, q0, [sp]
▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines
define void @memset_32_stack() { define void @memset_32_stack() {
; CHECK-LABEL: memset_32_stack: ; CHECK-LABEL: memset_32_stack:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v0.16b, #170
; CHECK-NEXT: mov x0, sp ; CHECK-NEXT: mov x0, sp
; CHECK-NEXT: movi v0.16b, #170
; CHECK-NEXT: stp q0, q0, [sp] ; CHECK-NEXT: stp q0, q0, [sp]
; CHECK-NEXT: bl something ; CHECK-NEXT: bl something
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%buf = alloca [32 x i8], align 1 %buf = alloca [32 x i8], align 1
%cast = bitcast [32 x i8]* %buf to i8* %cast = bitcast [32 x i8]* %buf to i8*
call void @llvm.memset.p0i8.i32(i8* %cast, i8 -86, i32 32, i1 false) call void @llvm.memset.p0i8.i32(i8* %cast, i8 -86, i32 32, i1 false)
call void @something(i8* %cast) call void @something(i8* %cast)
ret void ret void
} }
define void @memset_40_stack() { define void @memset_40_stack() {
; CHECK-LABEL: memset_40_stack: ; CHECK-LABEL: memset_40_stack:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #64 ; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: str x30, [sp, #48] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #48] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v0.16b, #170
; CHECK-NEXT: mov x8, #-6148914691236517206 ; CHECK-NEXT: mov x8, #-6148914691236517206
; CHECK-NEXT: mov x0, sp ; CHECK-NEXT: mov x0, sp
; CHECK-NEXT: str x8, [sp, #32] ; CHECK-NEXT: movi v0.16b, #170
; CHECK-NEXT: stp q0, q0, [sp] ; CHECK-NEXT: stp q0, q0, [sp]
; CHECK-NEXT: str x8, [sp, #32]
; CHECK-NEXT: bl something ; CHECK-NEXT: bl something
; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #64 ; CHECK-NEXT: add sp, sp, #64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%buf = alloca [40 x i8], align 1 %buf = alloca [40 x i8], align 1
%cast = bitcast [40 x i8]* %buf to i8* %cast = bitcast [40 x i8]* %buf to i8*
call void @llvm.memset.p0i8.i32(i8* %cast, i8 -86, i32 40, i1 false) call void @llvm.memset.p0i8.i32(i8* %cast, i8 -86, i32 40, i1 false)
call void @something(i8* %cast) call void @something(i8* %cast)
ret void ret void
} }
define void @memset_64_stack() { define void @memset_64_stack() {
; CHECK-LABEL: memset_64_stack: ; CHECK-LABEL: memset_64_stack:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #80 ; CHECK-NEXT: sub sp, sp, #80
; CHECK-NEXT: str x30, [sp, #64] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #64] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 80 ; CHECK-NEXT: .cfi_def_cfa_offset 80
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v0.16b, #170
; CHECK-NEXT: mov x0, sp ; CHECK-NEXT: mov x0, sp
; CHECK-NEXT: movi v0.16b, #170
; CHECK-NEXT: stp q0, q0, [sp, #32] ; CHECK-NEXT: stp q0, q0, [sp, #32]
; CHECK-NEXT: stp q0, q0, [sp] ; CHECK-NEXT: stp q0, q0, [sp]
; CHECK-NEXT: bl something ; CHECK-NEXT: bl something
; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #80 ; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%buf = alloca [64 x i8], align 1 %buf = alloca [64 x i8], align 1
%cast = bitcast [64 x i8]* %buf to i8* %cast = bitcast [64 x i8]* %buf to i8*
call void @llvm.memset.p0i8.i32(i8* %cast, i8 -86, i32 64, i1 false) call void @llvm.memset.p0i8.i32(i8* %cast, i8 -86, i32 64, i1 false)
call void @something(i8* %cast) call void @something(i8* %cast)
ret void ret void
} }
define void @memset_72_stack() { define void @memset_72_stack() {
; CHECK-LABEL: memset_72_stack: ; CHECK-LABEL: memset_72_stack:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #96 ; CHECK-NEXT: sub sp, sp, #96
; CHECK-NEXT: str x30, [sp, #80] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #80] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 96 ; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v0.16b, #170
; CHECK-NEXT: mov x8, #-6148914691236517206 ; CHECK-NEXT: mov x8, #-6148914691236517206
; CHECK-NEXT: mov x0, sp ; CHECK-NEXT: mov x0, sp
; CHECK-NEXT: str x8, [sp, #64] ; CHECK-NEXT: movi v0.16b, #170
; CHECK-NEXT: stp q0, q0, [sp, #32] ; CHECK-NEXT: stp q0, q0, [sp, #32]
; CHECK-NEXT: str x8, [sp, #64]
; CHECK-NEXT: stp q0, q0, [sp] ; CHECK-NEXT: stp q0, q0, [sp]
; CHECK-NEXT: bl something ; CHECK-NEXT: bl something
; CHECK-NEXT: ldr x30, [sp, #80] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #80] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #96 ; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%buf = alloca [72 x i8], align 1 %buf = alloca [72 x i8], align 1
%cast = bitcast [72 x i8]* %buf to i8* %cast = bitcast [72 x i8]* %buf to i8*
call void @llvm.memset.p0i8.i32(i8* %cast, i8 -86, i32 72, i1 false) call void @llvm.memset.p0i8.i32(i8* %cast, i8 -86, i32 72, i1 false)
call void @something(i8* %cast) call void @something(i8* %cast)
ret void ret void
} }
define void @memset_128_stack() { define void @memset_128_stack() {
; CHECK-LABEL: memset_128_stack: ; CHECK-LABEL: memset_128_stack:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #144 ; CHECK-NEXT: sub sp, sp, #144
; CHECK-NEXT: str x30, [sp, #128] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #128] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 144 ; CHECK-NEXT: .cfi_def_cfa_offset 144
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v0.16b, #170
; CHECK-NEXT: mov x0, sp ; CHECK-NEXT: mov x0, sp
; CHECK-NEXT: movi v0.16b, #170
; CHECK-NEXT: stp q0, q0, [sp, #96] ; CHECK-NEXT: stp q0, q0, [sp, #96]
; CHECK-NEXT: stp q0, q0, [sp, #64] ; CHECK-NEXT: stp q0, q0, [sp, #64]
; CHECK-NEXT: stp q0, q0, [sp, #32] ; CHECK-NEXT: stp q0, q0, [sp, #32]
; CHECK-NEXT: stp q0, q0, [sp] ; CHECK-NEXT: stp q0, q0, [sp]
; CHECK-NEXT: bl something ; CHECK-NEXT: bl something
; CHECK-NEXT: ldr x30, [sp, #128] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #128] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #144 ; CHECK-NEXT: add sp, sp, #144
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%buf = alloca [128 x i8], align 1 %buf = alloca [128 x i8], align 1
%cast = bitcast [128 x i8]* %buf to i8* %cast = bitcast [128 x i8]* %buf to i8*
call void @llvm.memset.p0i8.i32(i8* %cast, i8 -86, i32 128, i1 false) call void @llvm.memset.p0i8.i32(i8* %cast, i8 -86, i32 128, i1 false)
call void @something(i8* %cast) call void @something(i8* %cast)
ret void ret void
} }
define void @memset_256_stack() { define void @memset_256_stack() {
; CHECK-LABEL: memset_256_stack: ; CHECK-LABEL: memset_256_stack:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #272 ; CHECK-NEXT: sub sp, sp, #272
; CHECK-NEXT: stp x29, x30, [sp, #256] // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #256] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 272 ; CHECK-NEXT: .cfi_def_cfa_offset 272
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: movi v0.16b, #170
; CHECK-NEXT: mov x0, sp ; CHECK-NEXT: mov x0, sp
; CHECK-NEXT: movi v0.16b, #170
; CHECK-NEXT: stp q0, q0, [sp, #224] ; CHECK-NEXT: stp q0, q0, [sp, #224]
; CHECK-NEXT: stp q0, q0, [sp, #192] ; CHECK-NEXT: stp q0, q0, [sp, #192]
; CHECK-NEXT: stp q0, q0, [sp, #160] ; CHECK-NEXT: stp q0, q0, [sp, #160]
; CHECK-NEXT: stp q0, q0, [sp, #128] ; CHECK-NEXT: stp q0, q0, [sp, #128]
; CHECK-NEXT: stp q0, q0, [sp, #96] ; CHECK-NEXT: stp q0, q0, [sp, #96]
; CHECK-NEXT: stp q0, q0, [sp, #64] ; CHECK-NEXT: stp q0, q0, [sp, #64]
; CHECK-NEXT: stp q0, q0, [sp, #32] ; CHECK-NEXT: stp q0, q0, [sp, #32]
; CHECK-NEXT: stp q0, q0, [sp] ; CHECK-NEXT: stp q0, q0, [sp]
Show All 14 Lines

llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll

Show First 20 Lines • Show All 111 Lines • ▼ Show 20 Linesentry:
%add.i = add <8 x i16> %vmovl.i.i, %vmovl.i2.i %add.i = add <8 x i16> %vmovl.i.i, %vmovl.i2.i
%and = and <8 x i16> %add.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <8 x i16> %add.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %and ret <8 x i16> %and
} }
define <4 x i32> @test_vaddl_a16(<4 x i16> %a, <4 x i16> %b) { define <4 x i32> @test_vaddl_a16(<4 x i16> %a, <4 x i16> %b) {
; CHECK-LABEL: test_vaddl_a16: ; CHECK-LABEL: test_vaddl_a16:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h ; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vmovl.i.i = zext <4 x i16> %a to <4 x i32> %vmovl.i.i = zext <4 x i16> %a to <4 x i32>
%vmovl.i2.i = zext <4 x i16> %b to <4 x i32> %vmovl.i2.i = zext <4 x i16> %b to <4 x i32>
%add.i = add <4 x i32> %vmovl.i.i, %vmovl.i2.i %add.i = add <4 x i32> %vmovl.i.i, %vmovl.i2.i
%and = and <4 x i32> %add.i, <i32 65535, i32 65535, i32 65535, i32 65535> %and = and <4 x i32> %add.i, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %and ret <4 x i32> %and
} }
define <2 x i64> @test_vaddl_a32(<2 x i32> %a, <2 x i32> %b) { define <2 x i64> @test_vaddl_a32(<2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: test_vaddl_a32: ; CHECK-LABEL: test_vaddl_a32:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v2.2d, #0x000000ffffffff
; CHECK-NEXT: uaddl v0.2d, v0.2s, v1.2s ; CHECK-NEXT: uaddl v0.2d, v0.2s, v1.2s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vmovl.i.i = zext <2 x i32> %a to <2 x i64> %vmovl.i.i = zext <2 x i32> %a to <2 x i64>
%vmovl.i2.i = zext <2 x i32> %b to <2 x i64> %vmovl.i2.i = zext <2 x i32> %b to <2 x i64>
%add.i = add <2 x i64> %vmovl.i.i, %vmovl.i2.i %add.i = add <2 x i64> %vmovl.i.i, %vmovl.i2.i
%and = and <2 x i64> %add.i, <i64 4294967295, i64 4294967295> %and = and <2 x i64> %add.i, <i64 4294967295, i64 4294967295>
ret <2 x i64> %and ret <2 x i64> %and
} }
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Linesentry:
%add.i = add <8 x i16> %0, %1 %add.i = add <8 x i16> %0, %1
%and = and <8 x i16> %add.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <8 x i16> %add.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %and ret <8 x i16> %and
} }
define <4 x i32> @test_vaddl_high_a16(<8 x i16> %a, <8 x i16> %b) { define <4 x i32> @test_vaddl_high_a16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vaddl_high_a16: ; CHECK-LABEL: test_vaddl_high_a16:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
; CHECK-NEXT: uaddl2 v0.4s, v0.8h, v1.8h ; CHECK-NEXT: uaddl2 v0.4s, v0.8h, v1.8h
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shuffle.i.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %shuffle.i.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32> %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>
%shuffle.i.i2.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %shuffle.i.i2.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%1 = zext <4 x i16> %shuffle.i.i2.i to <4 x i32> %1 = zext <4 x i16> %shuffle.i.i2.i to <4 x i32>
%add.i = add <4 x i32> %0, %1 %add.i = add <4 x i32> %0, %1
%and = and <4 x i32> %add.i, <i32 65535, i32 65535, i32 65535, i32 65535> %and = and <4 x i32> %add.i, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %and ret <4 x i32> %and
} }
define <2 x i64> @test_vaddl_high_a32(<4 x i32> %a, <4 x i32> %b) { define <2 x i64> @test_vaddl_high_a32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vaddl_high_a32: ; CHECK-LABEL: test_vaddl_high_a32:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v2.2d, #0x000000ffffffff
; CHECK-NEXT: uaddl2 v0.2d, v0.4s, v1.4s ; CHECK-NEXT: uaddl2 v0.2d, v0.4s, v1.4s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shuffle.i.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %shuffle.i.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64> %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>
%shuffle.i.i2.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %shuffle.i.i2.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%1 = zext <2 x i32> %shuffle.i.i2.i to <2 x i64> %1 = zext <2 x i32> %shuffle.i.i2.i to <2 x i64>
%add.i = add <2 x i64> %0, %1 %add.i = add <2 x i64> %0, %1
%and = and <2 x i64> %add.i, <i64 4294967295, i64 4294967295> %and = and <2 x i64> %add.i, <i64 4294967295, i64 4294967295>
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Linesentry:
%add.i = add <8 x i16> %vmovl.i.i, %a %add.i = add <8 x i16> %vmovl.i.i, %a
%and = and <8 x i16> %add.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <8 x i16> %add.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %and ret <8 x i16> %and
} }
define <4 x i32> @test_vaddw_a16(<4 x i32> %a, <4 x i16> %b) { define <4 x i32> @test_vaddw_a16(<4 x i32> %a, <4 x i16> %b) {
; CHECK-LABEL: test_vaddw_a16: ; CHECK-LABEL: test_vaddw_a16:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
; CHECK-NEXT: uaddw v0.4s, v0.4s, v1.4h ; CHECK-NEXT: uaddw v0.4s, v0.4s, v1.4h
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vmovl.i.i = zext <4 x i16> %b to <4 x i32> %vmovl.i.i = zext <4 x i16> %b to <4 x i32>
%add.i = add <4 x i32> %vmovl.i.i, %a %add.i = add <4 x i32> %vmovl.i.i, %a
%and = and <4 x i32> %add.i, <i32 65535, i32 65535, i32 65535, i32 65535> %and = and <4 x i32> %add.i, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %and ret <4 x i32> %and
} }
define <2 x i64> @test_vaddw_a32(<2 x i64> %a, <2 x i32> %b) { define <2 x i64> @test_vaddw_a32(<2 x i64> %a, <2 x i32> %b) {
; CHECK-LABEL: test_vaddw_a32: ; CHECK-LABEL: test_vaddw_a32:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v2.2d, #0x000000ffffffff
; CHECK-NEXT: uaddw v0.2d, v0.2d, v1.2s ; CHECK-NEXT: uaddw v0.2d, v0.2d, v1.2s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vmovl.i.i = zext <2 x i32> %b to <2 x i64> %vmovl.i.i = zext <2 x i32> %b to <2 x i64>
%add.i = add <2 x i64> %vmovl.i.i, %a %add.i = add <2 x i64> %vmovl.i.i, %a
%and = and <2 x i64> %add.i, <i64 4294967295, i64 4294967295> %and = and <2 x i64> %add.i, <i64 4294967295, i64 4294967295>
ret <2 x i64> %and ret <2 x i64> %and
} }
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%add.i = add <8 x i16> %0, %a %add.i = add <8 x i16> %0, %a
%and = and <8 x i16> %add.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <8 x i16> %add.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %and ret <8 x i16> %and
} }
define <4 x i32> @test_vaddw_high_a16(<4 x i32> %a, <8 x i16> %b) { define <4 x i32> @test_vaddw_high_a16(<4 x i32> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vaddw_high_a16: ; CHECK-LABEL: test_vaddw_high_a16:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
; CHECK-NEXT: uaddw2 v0.4s, v0.4s, v1.8h ; CHECK-NEXT: uaddw2 v0.4s, v0.4s, v1.8h
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shuffle.i.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %shuffle.i.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32> %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>
%add.i = add <4 x i32> %0, %a %add.i = add <4 x i32> %0, %a
%and = and <4 x i32> %add.i, <i32 65535, i32 65535, i32 65535, i32 65535> %and = and <4 x i32> %add.i, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %and ret <4 x i32> %and
} }
define <2 x i64> @test_vaddw_high_a32(<2 x i64> %a, <4 x i32> %b) { define <2 x i64> @test_vaddw_high_a32(<2 x i64> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vaddw_high_a32: ; CHECK-LABEL: test_vaddw_high_a32:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v2.2d, #0x000000ffffffff
; CHECK-NEXT: uaddw2 v0.2d, v0.2d, v1.4s ; CHECK-NEXT: uaddw2 v0.2d, v0.2d, v1.4s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shuffle.i.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %shuffle.i.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64> %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>
%add.i = add <2 x i64> %0, %a %add.i = add <2 x i64> %0, %a
%and = and <2 x i64> %add.i, <i64 4294967295, i64 4294967295> %and = and <2 x i64> %add.i, <i64 4294967295, i64 4294967295>
ret <2 x i64> %and ret <2 x i64> %and
} }
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%sub.i = sub <8 x i16> %vmovl.i.i, %vmovl.i2.i %sub.i = sub <8 x i16> %vmovl.i.i, %vmovl.i2.i
%and = and <8 x i16> %sub.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <8 x i16> %sub.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %and ret <8 x i16> %and
} }
define <4 x i32> @test_vsubl_a16(<4 x i16> %a, <4 x i16> %b) { define <4 x i32> @test_vsubl_a16(<4 x i16> %a, <4 x i16> %b) {
; CHECK-LABEL: test_vsubl_a16: ; CHECK-LABEL: test_vsubl_a16:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
; CHECK-NEXT: usubl v0.4s, v0.4h, v1.4h ; CHECK-NEXT: usubl v0.4s, v0.4h, v1.4h
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vmovl.i.i = zext <4 x i16> %a to <4 x i32> %vmovl.i.i = zext <4 x i16> %a to <4 x i32>
%vmovl.i2.i = zext <4 x i16> %b to <4 x i32> %vmovl.i2.i = zext <4 x i16> %b to <4 x i32>
%sub.i = sub <4 x i32> %vmovl.i.i, %vmovl.i2.i %sub.i = sub <4 x i32> %vmovl.i.i, %vmovl.i2.i
%and = and <4 x i32> %sub.i, <i32 65535, i32 65535, i32 65535, i32 65535> %and = and <4 x i32> %sub.i, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %and ret <4 x i32> %and
} }
define <2 x i64> @test_vsubl_a32(<2 x i32> %a, <2 x i32> %b) { define <2 x i64> @test_vsubl_a32(<2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: test_vsubl_a32: ; CHECK-LABEL: test_vsubl_a32:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v2.2d, #0x000000ffffffff
; CHECK-NEXT: usubl v0.2d, v0.2s, v1.2s ; CHECK-NEXT: usubl v0.2d, v0.2s, v1.2s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vmovl.i.i = zext <2 x i32> %a to <2 x i64> %vmovl.i.i = zext <2 x i32> %a to <2 x i64>
%vmovl.i2.i = zext <2 x i32> %b to <2 x i64> %vmovl.i2.i = zext <2 x i32> %b to <2 x i64>
%sub.i = sub <2 x i64> %vmovl.i.i, %vmovl.i2.i %sub.i = sub <2 x i64> %vmovl.i.i, %vmovl.i2.i
%and = and <2 x i64> %sub.i, <i64 4294967295, i64 4294967295> %and = and <2 x i64> %sub.i, <i64 4294967295, i64 4294967295>
ret <2 x i64> %and ret <2 x i64> %and
} }
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%sub.i = sub <8 x i16> %0, %1 %sub.i = sub <8 x i16> %0, %1
%and = and <8 x i16> %sub.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <8 x i16> %sub.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %and ret <8 x i16> %and
} }
define <4 x i32> @test_vsubl_high_a16(<8 x i16> %a, <8 x i16> %b) { define <4 x i32> @test_vsubl_high_a16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vsubl_high_a16: ; CHECK-LABEL: test_vsubl_high_a16:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
; CHECK-NEXT: usubl2 v0.4s, v0.8h, v1.8h ; CHECK-NEXT: usubl2 v0.4s, v0.8h, v1.8h
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shuffle.i.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %shuffle.i.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32> %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>
%shuffle.i.i2.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %shuffle.i.i2.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%1 = zext <4 x i16> %shuffle.i.i2.i to <4 x i32> %1 = zext <4 x i16> %shuffle.i.i2.i to <4 x i32>
%sub.i = sub <4 x i32> %0, %1 %sub.i = sub <4 x i32> %0, %1
%and = and <4 x i32> %sub.i, <i32 65535, i32 65535, i32 65535, i32 65535> %and = and <4 x i32> %sub.i, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %and ret <4 x i32> %and
} }
define <2 x i64> @test_vsubl_high_a32(<4 x i32> %a, <4 x i32> %b) { define <2 x i64> @test_vsubl_high_a32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vsubl_high_a32: ; CHECK-LABEL: test_vsubl_high_a32:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v2.2d, #0x000000ffffffff
; CHECK-NEXT: usubl2 v0.2d, v0.4s, v1.4s ; CHECK-NEXT: usubl2 v0.2d, v0.4s, v1.4s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shuffle.i.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %shuffle.i.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64> %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>
%shuffle.i.i2.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %shuffle.i.i2.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%1 = zext <2 x i32> %shuffle.i.i2.i to <2 x i64> %1 = zext <2 x i32> %shuffle.i.i2.i to <2 x i64>
%sub.i = sub <2 x i64> %0, %1 %sub.i = sub <2 x i64> %0, %1
%and = and <2 x i64> %sub.i, <i64 4294967295, i64 4294967295> %and = and <2 x i64> %sub.i, <i64 4294967295, i64 4294967295>
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%sub.i = sub <8 x i16> %a, %vmovl.i.i %sub.i = sub <8 x i16> %a, %vmovl.i.i
%and = and <8 x i16> %sub.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <8 x i16> %sub.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %and ret <8 x i16> %and
} }
define <4 x i32> @test_vsubw_a16(<4 x i32> %a, <4 x i16> %b) { define <4 x i32> @test_vsubw_a16(<4 x i32> %a, <4 x i16> %b) {
; CHECK-LABEL: test_vsubw_a16: ; CHECK-LABEL: test_vsubw_a16:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
; CHECK-NEXT: usubw v0.4s, v0.4s, v1.4h ; CHECK-NEXT: usubw v0.4s, v0.4s, v1.4h
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vmovl.i.i = zext <4 x i16> %b to <4 x i32> %vmovl.i.i = zext <4 x i16> %b to <4 x i32>
%sub.i = sub <4 x i32> %a, %vmovl.i.i %sub.i = sub <4 x i32> %a, %vmovl.i.i
%and = and <4 x i32> %sub.i, <i32 65535, i32 65535, i32 65535, i32 65535> %and = and <4 x i32> %sub.i, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %and ret <4 x i32> %and
} }
define <2 x i64> @test_vsubw_a32(<2 x i64> %a, <2 x i32> %b) { define <2 x i64> @test_vsubw_a32(<2 x i64> %a, <2 x i32> %b) {
; CHECK-LABEL: test_vsubw_a32: ; CHECK-LABEL: test_vsubw_a32:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v2.2d, #0x000000ffffffff
; CHECK-NEXT: usubw v0.2d, v0.2d, v1.2s ; CHECK-NEXT: usubw v0.2d, v0.2d, v1.2s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vmovl.i.i = zext <2 x i32> %b to <2 x i64> %vmovl.i.i = zext <2 x i32> %b to <2 x i64>
%sub.i = sub <2 x i64> %a, %vmovl.i.i %sub.i = sub <2 x i64> %a, %vmovl.i.i
%and = and <2 x i64> %sub.i, <i64 4294967295, i64 4294967295> %and = and <2 x i64> %sub.i, <i64 4294967295, i64 4294967295>
ret <2 x i64> %and ret <2 x i64> %and
} }
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%sub.i = sub <8 x i16> %a, %0 %sub.i = sub <8 x i16> %a, %0
%and = and <8 x i16> %sub.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <8 x i16> %sub.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %and ret <8 x i16> %and
} }
define <4 x i32> @test_vsubw_high_a16(<4 x i32> %a, <8 x i16> %b) { define <4 x i32> @test_vsubw_high_a16(<4 x i32> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vsubw_high_a16: ; CHECK-LABEL: test_vsubw_high_a16:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
; CHECK-NEXT: usubw2 v0.4s, v0.4s, v1.8h ; CHECK-NEXT: usubw2 v0.4s, v0.4s, v1.8h
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shuffle.i.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %shuffle.i.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32> %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>
%sub.i = sub <4 x i32> %a, %0 %sub.i = sub <4 x i32> %a, %0
%and = and <4 x i32> %sub.i, <i32 65535, i32 65535, i32 65535, i32 65535> %and = and <4 x i32> %sub.i, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %and ret <4 x i32> %and
} }
define <2 x i64> @test_vsubw_high_a32(<2 x i64> %a, <4 x i32> %b) { define <2 x i64> @test_vsubw_high_a32(<2 x i64> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vsubw_high_a32: ; CHECK-LABEL: test_vsubw_high_a32:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v2.2d, #0x000000ffffffff
; CHECK-NEXT: usubw2 v0.2d, v0.2d, v1.4s ; CHECK-NEXT: usubw2 v0.2d, v0.2d, v1.4s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shuffle.i.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %shuffle.i.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64> %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>
%sub.i = sub <2 x i64> %a, %0 %sub.i = sub <2 x i64> %a, %0
%and = and <2 x i64> %sub.i, <i64 4294967295, i64 4294967295> %and = and <2 x i64> %sub.i, <i64 4294967295, i64 4294967295>
ret <2 x i64> %and ret <2 x i64> %and
} }
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} }
define i128 @test_vmull_p64(i64 %a, i64 %b) #4 { define i128 @test_vmull_p64(i64 %a, i64 %b) #4 {
; CHECK-LABEL: test_vmull_p64: ; CHECK-LABEL: test_vmull_p64:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov d0, x0 ; CHECK-NEXT: fmov d0, x0
; CHECK-NEXT: fmov d1, x1 ; CHECK-NEXT: fmov d1, x1
; CHECK-NEXT: pmull v0.1q, v0.1d, v1.1d ; CHECK-NEXT: pmull v0.1q, v0.1d, v1.1d
; CHECK-NEXT: mov x1, v0.d[1]
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: mov x1, v0.d[1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vmull2.i = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %a, i64 %b) %vmull2.i = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %a, i64 %b)
%vmull3.i = bitcast <16 x i8> %vmull2.i to i128 %vmull3.i = bitcast <16 x i8> %vmull2.i to i128
ret i128 %vmull3.i ret i128 %vmull3.i
} }
define i128 @test_vmull_high_p64(<2 x i64> %a, <2 x i64> %b) #4 { define i128 @test_vmull_high_p64(<2 x i64> %a, <2 x i64> %b) #4 {
; CHECK-LABEL: test_vmull_high_p64: ; CHECK-LABEL: test_vmull_high_p64:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: pmull2 v0.1q, v0.2d, v1.2d ; CHECK-NEXT: pmull2 v0.1q, v0.2d, v1.2d
; CHECK-NEXT: mov x1, v0.d[1]
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: mov x1, v0.d[1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = extractelement <2 x i64> %a, i32 1 %0 = extractelement <2 x i64> %a, i32 1
%1 = extractelement <2 x i64> %b, i32 1 %1 = extractelement <2 x i64> %b, i32 1
%vmull2.i.i = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %0, i64 %1) #1 %vmull2.i.i = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %0, i64 %1) #1
%vmull3.i.i = bitcast <16 x i8> %vmull2.i.i to i128 %vmull3.i.i = bitcast <16 x i8> %vmull2.i.i to i128
ret i128 %vmull3.i.i ret i128 %vmull3.i.i
} }

llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll

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%abd = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) %abd = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %abd ret <2 x i32> %abd
} }
define <2 x i32> @test_sabd_v2i32_const() { define <2 x i32> @test_sabd_v2i32_const() {
; CHECK-LABEL: test_sabd_v2i32_const: ; CHECK-LABEL: test_sabd_v2i32_const:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI19_0 ; CHECK-NEXT: adrp x8, .LCPI19_0
; CHECK-NEXT: movi d0, #0x00ffffffff0000 ; CHECK-NEXT: movi d1, #0x00ffffffff0000
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI19_0] ; CHECK-NEXT: ldr d0, [x8, :lo12:.LCPI19_0]
; CHECK-NEXT: sabd v0.2s, v1.2s, v0.2s ; CHECK-NEXT: sabd v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32( %1 = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(
<2 x i32> <i32 -2147483648, i32 2147450880>, <2 x i32> <i32 -2147483648, i32 2147450880>,
<2 x i32> <i32 -65536, i32 65535>) <2 x i32> <i32 -65536, i32 65535>)
ret <2 x i32> %1 ret <2 x i32> %1
} }
define <2 x i32> @test_saba_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { define <2 x i32> @test_saba_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = mul <1 x i64> %A, %B; %tmp3 = mul <1 x i64> %A, %B;
ret <1 x i64> %tmp3 ret <1 x i64> %tmp3
} }
define <2 x i64> @mul2xi64(<2 x i64> %A, <2 x i64> %B) { define <2 x i64> @mul2xi64(<2 x i64> %A, <2 x i64> %B) {
; CHECK-LABEL: mul2xi64: ; CHECK-LABEL: mul2xi64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fmov x9, d1 ; CHECK-NEXT: fmov x8, d1
; CHECK-NEXT: fmov x10, d0 ; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: mov x8, v1.d[1] ; CHECK-NEXT: mov x10, v0.d[1]
; CHECK-NEXT: mov x11, v0.d[1] ; CHECK-NEXT: mul x8, x9, x8
; CHECK-NEXT: mov x9, v1.d[1]
; CHECK-NEXT: mul x9, x10, x9 ; CHECK-NEXT: mul x9, x10, x9
; CHECK-NEXT: mul x8, x11, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: mov v0.d[1], x9
; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = mul <2 x i64> %A, %B; %tmp3 = mul <2 x i64> %A, %B;
ret <2 x i64> %tmp3 ret <2 x i64> %tmp3
} }
define <2 x float> @mul2xfloat(<2 x float> %A, <2 x float> %B) { define <2 x float> @mul2xfloat(<2 x float> %A, <2 x float> %B) {
; CHECK-LABEL: mul2xfloat: ; CHECK-LABEL: mul2xfloat:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
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; CHECK-LABEL: sdiv8x8: ; CHECK-LABEL: sdiv8x8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 ; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: smov w8, v1.b[1] ; CHECK-NEXT: smov w8, v1.b[1]
; CHECK-NEXT: smov w9, v0.b[1] ; CHECK-NEXT: smov w9, v0.b[1]
; CHECK-NEXT: smov w10, v0.b[0] ; CHECK-NEXT: smov w10, v0.b[0]
; CHECK-NEXT: smov w11, v0.b[2] ; CHECK-NEXT: smov w11, v0.b[2]
; CHECK-NEXT: smov w12, v0.b[3]
; CHECK-NEXT: smov w13, v0.b[4]
; CHECK-NEXT: sdiv w8, w9, w8 ; CHECK-NEXT: sdiv w8, w9, w8
; CHECK-NEXT: smov w9, v1.b[0] ; CHECK-NEXT: smov w9, v1.b[0]
; CHECK-NEXT: smov w12, v0.b[3]
; CHECK-NEXT: smov w13, v0.b[4]
; CHECK-NEXT: smov w14, v0.b[5]
; CHECK-NEXT: smov w15, v0.b[6]
; CHECK-NEXT: sdiv w9, w10, w9 ; CHECK-NEXT: sdiv w9, w10, w9
; CHECK-NEXT: smov w10, v1.b[2] ; CHECK-NEXT: smov w10, v1.b[2]
; CHECK-NEXT: sdiv w10, w11, w10 ; CHECK-NEXT: sdiv w10, w11, w10
; CHECK-NEXT: smov w11, v1.b[3] ; CHECK-NEXT: smov w11, v1.b[3]
; CHECK-NEXT: fmov s2, w9 ; CHECK-NEXT: fmov s2, w9
; CHECK-NEXT: smov w9, v1.b[5]
; CHECK-NEXT: mov v2.b[1], w8 ; CHECK-NEXT: mov v2.b[1], w8
; CHECK-NEXT: smov w8, v1.b[7]
; CHECK-NEXT: sdiv w11, w12, w11 ; CHECK-NEXT: sdiv w11, w12, w11
; CHECK-NEXT: smov w12, v1.b[4] ; CHECK-NEXT: smov w12, v1.b[4]
; CHECK-NEXT: mov v2.b[2], w10 ; CHECK-NEXT: mov v2.b[2], w10
; CHECK-NEXT: smov w10, v0.b[6] ; CHECK-NEXT: smov w10, v0.b[7]
; CHECK-NEXT: sdiv w12, w13, w12 ; CHECK-NEXT: sdiv w12, w13, w12
; CHECK-NEXT: smov w13, v0.b[5] ; CHECK-NEXT: smov w13, v1.b[5]
; CHECK-NEXT: mov v2.b[3], w11 ; CHECK-NEXT: mov v2.b[3], w11
; CHECK-NEXT: smov w11, v0.b[7] ; CHECK-NEXT: sdiv w13, w14, w13
; CHECK-NEXT: sdiv w8, w13, w9 ; CHECK-NEXT: smov w14, v1.b[6]
; CHECK-NEXT: smov w9, v1.b[6]
; CHECK-NEXT: mov v2.b[4], w12 ; CHECK-NEXT: mov v2.b[4], w12
; CHECK-NEXT: sdiv w9, w10, w9 ; CHECK-NEXT: sdiv w9, w15, w14
; CHECK-NEXT: smov w10, v1.b[7] ; CHECK-NEXT: mov v2.b[5], w13
; CHECK-NEXT: mov v2.b[5], w8 ; CHECK-NEXT: sdiv w8, w10, w8
; CHECK-NEXT: sdiv w8, w11, w10
; CHECK-NEXT: mov v2.b[6], w9 ; CHECK-NEXT: mov v2.b[6], w9
; CHECK-NEXT: mov v2.b[7], w8 ; CHECK-NEXT: mov v2.b[7], w8
; CHECK-NEXT: fmov d0, d2 ; CHECK-NEXT: fmov d0, d2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = sdiv <8 x i8> %A, %B; %tmp3 = sdiv <8 x i8> %A, %B;
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
} }
define <16 x i8> @sdiv16x8(<16 x i8> %A, <16 x i8> %B) { define <16 x i8> @sdiv16x8(<16 x i8> %A, <16 x i8> %B) {
; CHECK-LABEL: sdiv16x8: ; CHECK-LABEL: sdiv16x8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: smov w8, v1.b[1] ; CHECK-NEXT: smov w8, v1.b[1]
; CHECK-NEXT: smov w9, v0.b[1] ; CHECK-NEXT: smov w9, v0.b[1]
; CHECK-NEXT: smov w10, v0.b[0] ; CHECK-NEXT: smov w10, v0.b[0]
; CHECK-NEXT: smov w11, v0.b[2] ; CHECK-NEXT: smov w11, v0.b[2]
; CHECK-NEXT: sdiv w8, w9, w8
; CHECK-NEXT: smov w9, v1.b[0]
; CHECK-NEXT: smov w12, v0.b[3] ; CHECK-NEXT: smov w12, v0.b[3]
; CHECK-NEXT: smov w13, v0.b[4] ; CHECK-NEXT: smov w13, v0.b[4]
; CHECK-NEXT: smov w14, v0.b[5] ; CHECK-NEXT: smov w14, v0.b[5]
; CHECK-NEXT: smov w15, v0.b[6] ; CHECK-NEXT: smov w15, v0.b[6]
; CHECK-NEXT: sdiv w8, w9, w8
; CHECK-NEXT: smov w9, v1.b[0]
; CHECK-NEXT: smov w16, v0.b[7] ; CHECK-NEXT: smov w16, v0.b[7]
; CHECK-NEXT: smov w17, v0.b[8] ; CHECK-NEXT: smov w17, v0.b[8]
; CHECK-NEXT: smov w18, v0.b[9]
; CHECK-NEXT: smov w0, v0.b[10]
; CHECK-NEXT: smov w1, v0.b[11]
; CHECK-NEXT: smov w2, v0.b[12]
; CHECK-NEXT: sdiv w9, w10, w9 ; CHECK-NEXT: sdiv w9, w10, w9
; CHECK-NEXT: smov w10, v1.b[2] ; CHECK-NEXT: smov w10, v1.b[2]
; CHECK-NEXT: sdiv w10, w11, w10 ; CHECK-NEXT: sdiv w10, w11, w10
; CHECK-NEXT: smov w11, v1.b[3] ; CHECK-NEXT: smov w11, v1.b[3]
; CHECK-NEXT: fmov s2, w9 ; CHECK-NEXT: fmov s2, w9
; CHECK-NEXT: smov w9, v1.b[9]
; CHECK-NEXT: mov v2.b[1], w8 ; CHECK-NEXT: mov v2.b[1], w8
; CHECK-NEXT: smov w8, v1.b[13]
; CHECK-NEXT: sdiv w11, w12, w11 ; CHECK-NEXT: sdiv w11, w12, w11
; CHECK-NEXT: smov w12, v1.b[4] ; CHECK-NEXT: smov w12, v1.b[4]
; CHECK-NEXT: mov v2.b[2], w10 ; CHECK-NEXT: mov v2.b[2], w10
; CHECK-NEXT: smov w10, v0.b[10] ; CHECK-NEXT: smov w10, v0.b[13]
; CHECK-NEXT: sdiv w12, w13, w12 ; CHECK-NEXT: sdiv w12, w13, w12
; CHECK-NEXT: smov w13, v1.b[5] ; CHECK-NEXT: smov w13, v1.b[5]
; CHECK-NEXT: mov v2.b[3], w11 ; CHECK-NEXT: mov v2.b[3], w11
; CHECK-NEXT: smov w11, v0.b[11] ; CHECK-NEXT: smov w11, v0.b[14]
; CHECK-NEXT: sdiv w13, w14, w13 ; CHECK-NEXT: sdiv w13, w14, w13
; CHECK-NEXT: smov w14, v1.b[6] ; CHECK-NEXT: smov w14, v1.b[6]
; CHECK-NEXT: mov v2.b[4], w12 ; CHECK-NEXT: mov v2.b[4], w12
; CHECK-NEXT: smov w12, v0.b[12] ; CHECK-NEXT: smov w12, v0.b[15]
; CHECK-NEXT: sdiv w14, w15, w14 ; CHECK-NEXT: sdiv w14, w15, w14
; CHECK-NEXT: smov w15, v1.b[7] ; CHECK-NEXT: smov w15, v1.b[7]
; CHECK-NEXT: mov v2.b[5], w13 ; CHECK-NEXT: mov v2.b[5], w13
; CHECK-NEXT: smov w13, v0.b[13]
; CHECK-NEXT: sdiv w15, w16, w15 ; CHECK-NEXT: sdiv w15, w16, w15
; CHECK-NEXT: smov w16, v1.b[8] ; CHECK-NEXT: smov w16, v1.b[8]
; CHECK-NEXT: mov v2.b[6], w14 ; CHECK-NEXT: mov v2.b[6], w14
; CHECK-NEXT: sdiv w16, w17, w16 ; CHECK-NEXT: sdiv w16, w17, w16
; CHECK-NEXT: smov w17, v0.b[9] ; CHECK-NEXT: smov w17, v1.b[9]
; CHECK-NEXT: mov v2.b[7], w15 ; CHECK-NEXT: mov v2.b[7], w15
; CHECK-NEXT: sdiv w8, w17, w9 ; CHECK-NEXT: sdiv w17, w18, w17
; CHECK-NEXT: smov w9, v1.b[10] ; CHECK-NEXT: smov w18, v1.b[10]
; CHECK-NEXT: mov v2.b[8], w16 ; CHECK-NEXT: mov v2.b[8], w16
; CHECK-NEXT: sdiv w9, w10, w9 ; CHECK-NEXT: sdiv w18, w0, w18
; CHECK-NEXT: smov w10, v1.b[11] ; CHECK-NEXT: smov w0, v1.b[11]
; CHECK-NEXT: mov v2.b[9], w8 ; CHECK-NEXT: mov v2.b[9], w17
; CHECK-NEXT: sdiv w0, w1, w0
; CHECK-NEXT: smov w1, v1.b[12]
; CHECK-NEXT: mov v2.b[10], w18
; CHECK-NEXT: sdiv w9, w2, w1
; CHECK-NEXT: mov v2.b[11], w0
; CHECK-NEXT: sdiv w8, w10, w8
; CHECK-NEXT: smov w10, v1.b[14]
; CHECK-NEXT: mov v2.b[12], w9
; CHECK-NEXT: sdiv w10, w11, w10 ; CHECK-NEXT: sdiv w10, w11, w10
; CHECK-NEXT: smov w11, v1.b[12] ; CHECK-NEXT: smov w11, v1.b[15]
; CHECK-NEXT: mov v2.b[10], w9
; CHECK-NEXT: smov w9, v1.b[14]
; CHECK-NEXT: sdiv w11, w12, w11
; CHECK-NEXT: smov w12, v1.b[13]
; CHECK-NEXT: mov v2.b[11], w10
; CHECK-NEXT: smov w10, v1.b[15]
; CHECK-NEXT: sdiv w8, w13, w12
; CHECK-NEXT: smov w12, v0.b[14]
; CHECK-NEXT: mov v2.b[12], w11
; CHECK-NEXT: smov w11, v0.b[15]
; CHECK-NEXT: sdiv w9, w12, w9
; CHECK-NEXT: mov v2.b[13], w8 ; CHECK-NEXT: mov v2.b[13], w8
; CHECK-NEXT: sdiv w8, w11, w10 ; CHECK-NEXT: sdiv w11, w12, w11
; CHECK-NEXT: mov v2.b[14], w9 ; CHECK-NEXT: mov v2.b[14], w10
; CHECK-NEXT: mov v2.b[15], w8 ; CHECK-NEXT: mov v2.b[15], w11
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = sdiv <16 x i8> %A, %B; %tmp3 = sdiv <16 x i8> %A, %B;
ret <16 x i8> %tmp3 ret <16 x i8> %tmp3
} }
define <1 x i16> @sdiv1x16(<1 x i16> %A, <1 x i16> %B) { define <1 x i16> @sdiv1x16(<1 x i16> %A, <1 x i16> %B) {
; CHECK-LABEL: sdiv1x16: ; CHECK-LABEL: sdiv1x16:
Show All 13 Lines
; CHECK-LABEL: sdiv4x16: ; CHECK-LABEL: sdiv4x16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 ; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: smov w8, v1.h[1] ; CHECK-NEXT: smov w8, v1.h[1]
; CHECK-NEXT: smov w9, v0.h[1] ; CHECK-NEXT: smov w9, v0.h[1]
; CHECK-NEXT: smov w10, v0.h[0] ; CHECK-NEXT: smov w10, v0.h[0]
; CHECK-NEXT: smov w11, v0.h[2] ; CHECK-NEXT: smov w11, v0.h[2]
; CHECK-NEXT: smov w12, v0.h[3]
; CHECK-NEXT: sdiv w8, w9, w8 ; CHECK-NEXT: sdiv w8, w9, w8
; CHECK-NEXT: smov w9, v1.h[0] ; CHECK-NEXT: smov w9, v1.h[0]
; CHECK-NEXT: smov w12, v0.h[3]
; CHECK-NEXT: sdiv w9, w10, w9 ; CHECK-NEXT: sdiv w9, w10, w9
; CHECK-NEXT: smov w10, v1.h[2] ; CHECK-NEXT: smov w10, v1.h[2]
; CHECK-NEXT: sdiv w10, w11, w10 ; CHECK-NEXT: sdiv w10, w11, w10
; CHECK-NEXT: smov w11, v1.h[3] ; CHECK-NEXT: smov w11, v1.h[3]
; CHECK-NEXT: fmov s0, w9 ; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: mov v0.h[1], w8 ; CHECK-NEXT: mov v0.h[1], w8
; CHECK-NEXT: sdiv w8, w12, w11 ; CHECK-NEXT: sdiv w11, w12, w11
; CHECK-NEXT: mov v0.h[2], w10 ; CHECK-NEXT: mov v0.h[2], w10
; CHECK-NEXT: mov v0.h[3], w8 ; CHECK-NEXT: mov v0.h[3], w11
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = sdiv <4 x i16> %A, %B; %tmp3 = sdiv <4 x i16> %A, %B;
ret <4 x i16> %tmp3 ret <4 x i16> %tmp3
} }
define <8 x i16> @sdiv8x16(<8 x i16> %A, <8 x i16> %B) { define <8 x i16> @sdiv8x16(<8 x i16> %A, <8 x i16> %B) {
; CHECK-LABEL: sdiv8x16: ; CHECK-LABEL: sdiv8x16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: smov w8, v1.h[1] ; CHECK-NEXT: smov w8, v1.h[1]
; CHECK-NEXT: smov w9, v0.h[1] ; CHECK-NEXT: smov w9, v0.h[1]
; CHECK-NEXT: smov w10, v0.h[0] ; CHECK-NEXT: smov w10, v0.h[0]
; CHECK-NEXT: smov w11, v0.h[2] ; CHECK-NEXT: smov w11, v0.h[2]
; CHECK-NEXT: smov w12, v0.h[3]
; CHECK-NEXT: smov w13, v0.h[4]
; CHECK-NEXT: sdiv w8, w9, w8 ; CHECK-NEXT: sdiv w8, w9, w8
; CHECK-NEXT: smov w9, v1.h[0] ; CHECK-NEXT: smov w9, v1.h[0]
; CHECK-NEXT: smov w12, v0.h[3]
; CHECK-NEXT: smov w13, v0.h[4]
; CHECK-NEXT: smov w14, v0.h[5]
; CHECK-NEXT: smov w15, v0.h[6]
; CHECK-NEXT: sdiv w9, w10, w9 ; CHECK-NEXT: sdiv w9, w10, w9
; CHECK-NEXT: smov w10, v1.h[2] ; CHECK-NEXT: smov w10, v1.h[2]
; CHECK-NEXT: sdiv w10, w11, w10 ; CHECK-NEXT: sdiv w10, w11, w10
; CHECK-NEXT: smov w11, v1.h[3] ; CHECK-NEXT: smov w11, v1.h[3]
; CHECK-NEXT: fmov s2, w9 ; CHECK-NEXT: fmov s2, w9
; CHECK-NEXT: smov w9, v1.h[5]
; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: mov v2.h[1], w8
; CHECK-NEXT: smov w8, v1.h[7]
; CHECK-NEXT: sdiv w11, w12, w11 ; CHECK-NEXT: sdiv w11, w12, w11
; CHECK-NEXT: smov w12, v1.h[4] ; CHECK-NEXT: smov w12, v1.h[4]
; CHECK-NEXT: mov v2.h[2], w10 ; CHECK-NEXT: mov v2.h[2], w10
; CHECK-NEXT: smov w10, v0.h[6] ; CHECK-NEXT: smov w10, v0.h[7]
; CHECK-NEXT: sdiv w12, w13, w12 ; CHECK-NEXT: sdiv w12, w13, w12
; CHECK-NEXT: smov w13, v0.h[5] ; CHECK-NEXT: smov w13, v1.h[5]
; CHECK-NEXT: mov v2.h[3], w11 ; CHECK-NEXT: mov v2.h[3], w11
; CHECK-NEXT: smov w11, v0.h[7] ; CHECK-NEXT: sdiv w13, w14, w13
; CHECK-NEXT: sdiv w8, w13, w9 ; CHECK-NEXT: smov w14, v1.h[6]
; CHECK-NEXT: smov w9, v1.h[6]
; CHECK-NEXT: mov v2.h[4], w12 ; CHECK-NEXT: mov v2.h[4], w12
; CHECK-NEXT: sdiv w9, w10, w9 ; CHECK-NEXT: sdiv w9, w15, w14
; CHECK-NEXT: smov w10, v1.h[7] ; CHECK-NEXT: mov v2.h[5], w13
; CHECK-NEXT: mov v2.h[5], w8 ; CHECK-NEXT: sdiv w8, w10, w8
; CHECK-NEXT: sdiv w8, w11, w10
; CHECK-NEXT: mov v2.h[6], w9 ; CHECK-NEXT: mov v2.h[6], w9
; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: mov v2.h[7], w8
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = sdiv <8 x i16> %A, %B; %tmp3 = sdiv <8 x i16> %A, %B;
ret <8 x i16> %tmp3 ret <8 x i16> %tmp3
} }
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define <4 x i32> @sdiv4x32(<4 x i32> %A, <4 x i32> %B) { define <4 x i32> @sdiv4x32(<4 x i32> %A, <4 x i32> %B) {
; CHECK-LABEL: sdiv4x32: ; CHECK-LABEL: sdiv4x32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, v1.s[1] ; CHECK-NEXT: mov w8, v1.s[1]
; CHECK-NEXT: mov w9, v0.s[1] ; CHECK-NEXT: mov w9, v0.s[1]
; CHECK-NEXT: fmov w10, s0 ; CHECK-NEXT: fmov w10, s0
; CHECK-NEXT: mov w11, v0.s[2] ; CHECK-NEXT: mov w11, v0.s[2]
; CHECK-NEXT: mov w12, v0.s[3]
; CHECK-NEXT: sdiv w8, w9, w8 ; CHECK-NEXT: sdiv w8, w9, w8
; CHECK-NEXT: fmov w9, s1 ; CHECK-NEXT: fmov w9, s1
; CHECK-NEXT: mov w12, v0.s[3]
; CHECK-NEXT: sdiv w9, w10, w9 ; CHECK-NEXT: sdiv w9, w10, w9
; CHECK-NEXT: mov w10, v1.s[2] ; CHECK-NEXT: mov w10, v1.s[2]
; CHECK-NEXT: sdiv w10, w11, w10 ; CHECK-NEXT: sdiv w10, w11, w10
; CHECK-NEXT: mov w11, v1.s[3] ; CHECK-NEXT: mov w11, v1.s[3]
; CHECK-NEXT: fmov s0, w9 ; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: mov v0.s[1], w8 ; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: sdiv w8, w12, w11 ; CHECK-NEXT: sdiv w11, w12, w11
; CHECK-NEXT: mov v0.s[2], w10 ; CHECK-NEXT: mov v0.s[2], w10
; CHECK-NEXT: mov v0.s[3], w8 ; CHECK-NEXT: mov v0.s[3], w11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = sdiv <4 x i32> %A, %B; %tmp3 = sdiv <4 x i32> %A, %B;
ret <4 x i32> %tmp3 ret <4 x i32> %tmp3
} }
define <1 x i64> @sdiv1x64(<1 x i64> %A, <1 x i64> %B) { define <1 x i64> @sdiv1x64(<1 x i64> %A, <1 x i64> %B) {
; CHECK-LABEL: sdiv1x64: ; CHECK-LABEL: sdiv1x64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
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; CHECK-LABEL: udiv8x8: ; CHECK-LABEL: udiv8x8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 ; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v1.b[1] ; CHECK-NEXT: umov w8, v1.b[1]
; CHECK-NEXT: umov w9, v0.b[1] ; CHECK-NEXT: umov w9, v0.b[1]
; CHECK-NEXT: umov w10, v0.b[0] ; CHECK-NEXT: umov w10, v0.b[0]
; CHECK-NEXT: umov w11, v0.b[2] ; CHECK-NEXT: umov w11, v0.b[2]
; CHECK-NEXT: umov w12, v0.b[3]
; CHECK-NEXT: umov w13, v0.b[4]
; CHECK-NEXT: udiv w8, w9, w8 ; CHECK-NEXT: udiv w8, w9, w8
; CHECK-NEXT: umov w9, v1.b[0] ; CHECK-NEXT: umov w9, v1.b[0]
; CHECK-NEXT: umov w12, v0.b[3]
; CHECK-NEXT: umov w13, v0.b[4]
; CHECK-NEXT: umov w14, v0.b[5]
; CHECK-NEXT: umov w15, v0.b[6]
; CHECK-NEXT: udiv w9, w10, w9 ; CHECK-NEXT: udiv w9, w10, w9
; CHECK-NEXT: umov w10, v1.b[2] ; CHECK-NEXT: umov w10, v1.b[2]
; CHECK-NEXT: udiv w10, w11, w10 ; CHECK-NEXT: udiv w10, w11, w10
; CHECK-NEXT: umov w11, v1.b[3] ; CHECK-NEXT: umov w11, v1.b[3]
; CHECK-NEXT: fmov s2, w9 ; CHECK-NEXT: fmov s2, w9
; CHECK-NEXT: umov w9, v1.b[5]
; CHECK-NEXT: mov v2.b[1], w8 ; CHECK-NEXT: mov v2.b[1], w8
; CHECK-NEXT: umov w8, v1.b[7]
; CHECK-NEXT: udiv w11, w12, w11 ; CHECK-NEXT: udiv w11, w12, w11
; CHECK-NEXT: umov w12, v1.b[4] ; CHECK-NEXT: umov w12, v1.b[4]
; CHECK-NEXT: mov v2.b[2], w10 ; CHECK-NEXT: mov v2.b[2], w10
; CHECK-NEXT: umov w10, v0.b[6] ; CHECK-NEXT: umov w10, v0.b[7]
; CHECK-NEXT: udiv w12, w13, w12 ; CHECK-NEXT: udiv w12, w13, w12
; CHECK-NEXT: umov w13, v0.b[5] ; CHECK-NEXT: umov w13, v1.b[5]
; CHECK-NEXT: mov v2.b[3], w11 ; CHECK-NEXT: mov v2.b[3], w11
; CHECK-NEXT: umov w11, v0.b[7] ; CHECK-NEXT: udiv w13, w14, w13
; CHECK-NEXT: udiv w8, w13, w9 ; CHECK-NEXT: umov w14, v1.b[6]
; CHECK-NEXT: umov w9, v1.b[6]
; CHECK-NEXT: mov v2.b[4], w12 ; CHECK-NEXT: mov v2.b[4], w12
; CHECK-NEXT: udiv w9, w10, w9 ; CHECK-NEXT: udiv w9, w15, w14
; CHECK-NEXT: umov w10, v1.b[7] ; CHECK-NEXT: mov v2.b[5], w13
; CHECK-NEXT: mov v2.b[5], w8 ; CHECK-NEXT: udiv w8, w10, w8
; CHECK-NEXT: udiv w8, w11, w10
; CHECK-NEXT: mov v2.b[6], w9 ; CHECK-NEXT: mov v2.b[6], w9
; CHECK-NEXT: mov v2.b[7], w8 ; CHECK-NEXT: mov v2.b[7], w8
; CHECK-NEXT: fmov d0, d2 ; CHECK-NEXT: fmov d0, d2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = udiv <8 x i8> %A, %B; %tmp3 = udiv <8 x i8> %A, %B;
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
} }
define <16 x i8> @udiv16x8(<16 x i8> %A, <16 x i8> %B) { define <16 x i8> @udiv16x8(<16 x i8> %A, <16 x i8> %B) {
; CHECK-LABEL: udiv16x8: ; CHECK-LABEL: udiv16x8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v1.b[1] ; CHECK-NEXT: umov w8, v1.b[1]
; CHECK-NEXT: umov w9, v0.b[1] ; CHECK-NEXT: umov w9, v0.b[1]
; CHECK-NEXT: umov w10, v0.b[0] ; CHECK-NEXT: umov w10, v0.b[0]
; CHECK-NEXT: umov w11, v0.b[2] ; CHECK-NEXT: umov w11, v0.b[2]
; CHECK-NEXT: udiv w8, w9, w8
; CHECK-NEXT: umov w9, v1.b[0]
; CHECK-NEXT: umov w12, v0.b[3] ; CHECK-NEXT: umov w12, v0.b[3]
; CHECK-NEXT: umov w13, v0.b[4] ; CHECK-NEXT: umov w13, v0.b[4]
; CHECK-NEXT: umov w14, v0.b[5] ; CHECK-NEXT: umov w14, v0.b[5]
; CHECK-NEXT: umov w15, v0.b[6] ; CHECK-NEXT: umov w15, v0.b[6]
; CHECK-NEXT: udiv w8, w9, w8
; CHECK-NEXT: umov w9, v1.b[0]
; CHECK-NEXT: umov w16, v0.b[7] ; CHECK-NEXT: umov w16, v0.b[7]
; CHECK-NEXT: umov w17, v0.b[8] ; CHECK-NEXT: umov w17, v0.b[8]
; CHECK-NEXT: umov w18, v0.b[9]
; CHECK-NEXT: umov w0, v0.b[10]
; CHECK-NEXT: umov w1, v0.b[11]
; CHECK-NEXT: umov w2, v0.b[12]
; CHECK-NEXT: udiv w9, w10, w9 ; CHECK-NEXT: udiv w9, w10, w9
; CHECK-NEXT: umov w10, v1.b[2] ; CHECK-NEXT: umov w10, v1.b[2]
; CHECK-NEXT: udiv w10, w11, w10 ; CHECK-NEXT: udiv w10, w11, w10
; CHECK-NEXT: umov w11, v1.b[3] ; CHECK-NEXT: umov w11, v1.b[3]
; CHECK-NEXT: fmov s2, w9 ; CHECK-NEXT: fmov s2, w9
; CHECK-NEXT: umov w9, v1.b[9]
; CHECK-NEXT: mov v2.b[1], w8 ; CHECK-NEXT: mov v2.b[1], w8
; CHECK-NEXT: umov w8, v1.b[13]
; CHECK-NEXT: udiv w11, w12, w11 ; CHECK-NEXT: udiv w11, w12, w11
; CHECK-NEXT: umov w12, v1.b[4] ; CHECK-NEXT: umov w12, v1.b[4]
; CHECK-NEXT: mov v2.b[2], w10 ; CHECK-NEXT: mov v2.b[2], w10
; CHECK-NEXT: umov w10, v0.b[10] ; CHECK-NEXT: umov w10, v0.b[13]
; CHECK-NEXT: udiv w12, w13, w12 ; CHECK-NEXT: udiv w12, w13, w12
; CHECK-NEXT: umov w13, v1.b[5] ; CHECK-NEXT: umov w13, v1.b[5]
; CHECK-NEXT: mov v2.b[3], w11 ; CHECK-NEXT: mov v2.b[3], w11
; CHECK-NEXT: umov w11, v0.b[11] ; CHECK-NEXT: umov w11, v0.b[14]
; CHECK-NEXT: udiv w13, w14, w13 ; CHECK-NEXT: udiv w13, w14, w13
; CHECK-NEXT: umov w14, v1.b[6] ; CHECK-NEXT: umov w14, v1.b[6]
; CHECK-NEXT: mov v2.b[4], w12 ; CHECK-NEXT: mov v2.b[4], w12
; CHECK-NEXT: umov w12, v0.b[12] ; CHECK-NEXT: umov w12, v0.b[15]
; CHECK-NEXT: udiv w14, w15, w14 ; CHECK-NEXT: udiv w14, w15, w14
; CHECK-NEXT: umov w15, v1.b[7] ; CHECK-NEXT: umov w15, v1.b[7]
; CHECK-NEXT: mov v2.b[5], w13 ; CHECK-NEXT: mov v2.b[5], w13
; CHECK-NEXT: umov w13, v0.b[13]
; CHECK-NEXT: udiv w15, w16, w15 ; CHECK-NEXT: udiv w15, w16, w15
; CHECK-NEXT: umov w16, v1.b[8] ; CHECK-NEXT: umov w16, v1.b[8]
; CHECK-NEXT: mov v2.b[6], w14 ; CHECK-NEXT: mov v2.b[6], w14
; CHECK-NEXT: udiv w16, w17, w16 ; CHECK-NEXT: udiv w16, w17, w16
; CHECK-NEXT: umov w17, v0.b[9] ; CHECK-NEXT: umov w17, v1.b[9]
; CHECK-NEXT: mov v2.b[7], w15 ; CHECK-NEXT: mov v2.b[7], w15
; CHECK-NEXT: udiv w8, w17, w9 ; CHECK-NEXT: udiv w17, w18, w17
; CHECK-NEXT: umov w9, v1.b[10] ; CHECK-NEXT: umov w18, v1.b[10]
; CHECK-NEXT: mov v2.b[8], w16 ; CHECK-NEXT: mov v2.b[8], w16
; CHECK-NEXT: udiv w9, w10, w9 ; CHECK-NEXT: udiv w18, w0, w18
; CHECK-NEXT: umov w10, v1.b[11] ; CHECK-NEXT: umov w0, v1.b[11]
; CHECK-NEXT: mov v2.b[9], w8 ; CHECK-NEXT: mov v2.b[9], w17
; CHECK-NEXT: udiv w0, w1, w0
; CHECK-NEXT: umov w1, v1.b[12]
; CHECK-NEXT: mov v2.b[10], w18
; CHECK-NEXT: udiv w9, w2, w1
; CHECK-NEXT: mov v2.b[11], w0
; CHECK-NEXT: udiv w8, w10, w8
; CHECK-NEXT: umov w10, v1.b[14]
; CHECK-NEXT: mov v2.b[12], w9
; CHECK-NEXT: udiv w10, w11, w10 ; CHECK-NEXT: udiv w10, w11, w10
; CHECK-NEXT: umov w11, v1.b[12] ; CHECK-NEXT: umov w11, v1.b[15]
; CHECK-NEXT: mov v2.b[10], w9
; CHECK-NEXT: umov w9, v1.b[14]
; CHECK-NEXT: udiv w11, w12, w11
; CHECK-NEXT: umov w12, v1.b[13]
; CHECK-NEXT: mov v2.b[11], w10
; CHECK-NEXT: umov w10, v1.b[15]
; CHECK-NEXT: udiv w8, w13, w12
; CHECK-NEXT: umov w12, v0.b[14]
; CHECK-NEXT: mov v2.b[12], w11
; CHECK-NEXT: umov w11, v0.b[15]
; CHECK-NEXT: udiv w9, w12, w9
; CHECK-NEXT: mov v2.b[13], w8 ; CHECK-NEXT: mov v2.b[13], w8
; CHECK-NEXT: udiv w8, w11, w10 ; CHECK-NEXT: udiv w11, w12, w11
; CHECK-NEXT: mov v2.b[14], w9 ; CHECK-NEXT: mov v2.b[14], w10
; CHECK-NEXT: mov v2.b[15], w8 ; CHECK-NEXT: mov v2.b[15], w11
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = udiv <16 x i8> %A, %B; %tmp3 = udiv <16 x i8> %A, %B;
ret <16 x i8> %tmp3 ret <16 x i8> %tmp3
} }
define <1 x i16> @udiv1x16(<1 x i16> %A, <1 x i16> %B) { define <1 x i16> @udiv1x16(<1 x i16> %A, <1 x i16> %B) {
; CHECK-LABEL: udiv1x16: ; CHECK-LABEL: udiv1x16:
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; CHECK-LABEL: udiv4x16: ; CHECK-LABEL: udiv4x16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 ; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v1.h[1] ; CHECK-NEXT: umov w8, v1.h[1]
; CHECK-NEXT: umov w9, v0.h[1] ; CHECK-NEXT: umov w9, v0.h[1]
; CHECK-NEXT: umov w10, v0.h[0] ; CHECK-NEXT: umov w10, v0.h[0]
; CHECK-NEXT: umov w11, v0.h[2] ; CHECK-NEXT: umov w11, v0.h[2]
; CHECK-NEXT: umov w12, v0.h[3]
; CHECK-NEXT: udiv w8, w9, w8 ; CHECK-NEXT: udiv w8, w9, w8
; CHECK-NEXT: umov w9, v1.h[0] ; CHECK-NEXT: umov w9, v1.h[0]
; CHECK-NEXT: umov w12, v0.h[3]
; CHECK-NEXT: udiv w9, w10, w9 ; CHECK-NEXT: udiv w9, w10, w9
; CHECK-NEXT: umov w10, v1.h[2] ; CHECK-NEXT: umov w10, v1.h[2]
; CHECK-NEXT: udiv w10, w11, w10 ; CHECK-NEXT: udiv w10, w11, w10
; CHECK-NEXT: umov w11, v1.h[3] ; CHECK-NEXT: umov w11, v1.h[3]
; CHECK-NEXT: fmov s0, w9 ; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: mov v0.h[1], w8 ; CHECK-NEXT: mov v0.h[1], w8
; CHECK-NEXT: udiv w8, w12, w11 ; CHECK-NEXT: udiv w11, w12, w11
; CHECK-NEXT: mov v0.h[2], w10 ; CHECK-NEXT: mov v0.h[2], w10
; CHECK-NEXT: mov v0.h[3], w8 ; CHECK-NEXT: mov v0.h[3], w11
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = udiv <4 x i16> %A, %B; %tmp3 = udiv <4 x i16> %A, %B;
ret <4 x i16> %tmp3 ret <4 x i16> %tmp3
} }
define <8 x i16> @udiv8x16(<8 x i16> %A, <8 x i16> %B) { define <8 x i16> @udiv8x16(<8 x i16> %A, <8 x i16> %B) {
; CHECK-LABEL: udiv8x16: ; CHECK-LABEL: udiv8x16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v1.h[1] ; CHECK-NEXT: umov w8, v1.h[1]
; CHECK-NEXT: umov w9, v0.h[1] ; CHECK-NEXT: umov w9, v0.h[1]
; CHECK-NEXT: umov w10, v0.h[0] ; CHECK-NEXT: umov w10, v0.h[0]
; CHECK-NEXT: umov w11, v0.h[2] ; CHECK-NEXT: umov w11, v0.h[2]
; CHECK-NEXT: umov w12, v0.h[3]
; CHECK-NEXT: umov w13, v0.h[4]
; CHECK-NEXT: udiv w8, w9, w8 ; CHECK-NEXT: udiv w8, w9, w8
; CHECK-NEXT: umov w9, v1.h[0] ; CHECK-NEXT: umov w9, v1.h[0]
; CHECK-NEXT: umov w12, v0.h[3]
; CHECK-NEXT: umov w13, v0.h[4]
; CHECK-NEXT: umov w14, v0.h[5]
; CHECK-NEXT: umov w15, v0.h[6]
; CHECK-NEXT: udiv w9, w10, w9 ; CHECK-NEXT: udiv w9, w10, w9
; CHECK-NEXT: umov w10, v1.h[2] ; CHECK-NEXT: umov w10, v1.h[2]
; CHECK-NEXT: udiv w10, w11, w10 ; CHECK-NEXT: udiv w10, w11, w10
; CHECK-NEXT: umov w11, v1.h[3] ; CHECK-NEXT: umov w11, v1.h[3]
; CHECK-NEXT: fmov s2, w9 ; CHECK-NEXT: fmov s2, w9
; CHECK-NEXT: umov w9, v1.h[5]
; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: mov v2.h[1], w8
; CHECK-NEXT: umov w8, v1.h[7]
; CHECK-NEXT: udiv w11, w12, w11 ; CHECK-NEXT: udiv w11, w12, w11
; CHECK-NEXT: umov w12, v1.h[4] ; CHECK-NEXT: umov w12, v1.h[4]
; CHECK-NEXT: mov v2.h[2], w10 ; CHECK-NEXT: mov v2.h[2], w10
; CHECK-NEXT: umov w10, v0.h[6] ; CHECK-NEXT: umov w10, v0.h[7]
; CHECK-NEXT: udiv w12, w13, w12 ; CHECK-NEXT: udiv w12, w13, w12
; CHECK-NEXT: umov w13, v0.h[5] ; CHECK-NEXT: umov w13, v1.h[5]
; CHECK-NEXT: mov v2.h[3], w11 ; CHECK-NEXT: mov v2.h[3], w11
; CHECK-NEXT: umov w11, v0.h[7] ; CHECK-NEXT: udiv w13, w14, w13
; CHECK-NEXT: udiv w8, w13, w9 ; CHECK-NEXT: umov w14, v1.h[6]
; CHECK-NEXT: umov w9, v1.h[6]
; CHECK-NEXT: mov v2.h[4], w12 ; CHECK-NEXT: mov v2.h[4], w12
; CHECK-NEXT: udiv w9, w10, w9 ; CHECK-NEXT: udiv w9, w15, w14
; CHECK-NEXT: umov w10, v1.h[7] ; CHECK-NEXT: mov v2.h[5], w13
; CHECK-NEXT: mov v2.h[5], w8 ; CHECK-NEXT: udiv w8, w10, w8
; CHECK-NEXT: udiv w8, w11, w10
; CHECK-NEXT: mov v2.h[6], w9 ; CHECK-NEXT: mov v2.h[6], w9
; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: mov v2.h[7], w8
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = udiv <8 x i16> %A, %B; %tmp3 = udiv <8 x i16> %A, %B;
ret <8 x i16> %tmp3 ret <8 x i16> %tmp3
} }
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define <4 x i32> @udiv4x32(<4 x i32> %A, <4 x i32> %B) { define <4 x i32> @udiv4x32(<4 x i32> %A, <4 x i32> %B) {
; CHECK-LABEL: udiv4x32: ; CHECK-LABEL: udiv4x32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, v1.s[1] ; CHECK-NEXT: mov w8, v1.s[1]
; CHECK-NEXT: mov w9, v0.s[1] ; CHECK-NEXT: mov w9, v0.s[1]
; CHECK-NEXT: fmov w10, s0 ; CHECK-NEXT: fmov w10, s0
; CHECK-NEXT: mov w11, v0.s[2] ; CHECK-NEXT: mov w11, v0.s[2]
; CHECK-NEXT: mov w12, v0.s[3]
; CHECK-NEXT: udiv w8, w9, w8 ; CHECK-NEXT: udiv w8, w9, w8
; CHECK-NEXT: fmov w9, s1 ; CHECK-NEXT: fmov w9, s1
; CHECK-NEXT: mov w12, v0.s[3]
; CHECK-NEXT: udiv w9, w10, w9 ; CHECK-NEXT: udiv w9, w10, w9
; CHECK-NEXT: mov w10, v1.s[2] ; CHECK-NEXT: mov w10, v1.s[2]
; CHECK-NEXT: udiv w10, w11, w10 ; CHECK-NEXT: udiv w10, w11, w10
; CHECK-NEXT: mov w11, v1.s[3] ; CHECK-NEXT: mov w11, v1.s[3]
; CHECK-NEXT: fmov s0, w9 ; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: mov v0.s[1], w8 ; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: udiv w8, w12, w11 ; CHECK-NEXT: udiv w11, w12, w11
; CHECK-NEXT: mov v0.s[2], w10 ; CHECK-NEXT: mov v0.s[2], w10
; CHECK-NEXT: mov v0.s[3], w8 ; CHECK-NEXT: mov v0.s[3], w11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = udiv <4 x i32> %A, %B; %tmp3 = udiv <4 x i32> %A, %B;
ret <4 x i32> %tmp3 ret <4 x i32> %tmp3
} }
define <1 x i64> @udiv1x64(<1 x i64> %A, <1 x i64> %B) { define <1 x i64> @udiv1x64(<1 x i64> %A, <1 x i64> %B) {
; CHECK-LABEL: udiv1x64: ; CHECK-LABEL: udiv1x64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = srem <1 x i8> %A, %B; %tmp3 = srem <1 x i8> %A, %B;
ret <1 x i8> %tmp3 ret <1 x i8> %tmp3
} }
define <8 x i8> @srem8x8(<8 x i8> %A, <8 x i8> %B) { define <8 x i8> @srem8x8(<8 x i8> %A, <8 x i8> %B) {
; CHECK-LABEL: srem8x8: ; CHECK-LABEL: srem8x8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x19, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -16
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 ; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: smov w11, v1.b[0] ; CHECK-NEXT: smov w11, v1.b[0]
; CHECK-NEXT: smov w12, v0.b[0] ; CHECK-NEXT: smov w12, v0.b[0]
; CHECK-NEXT: smov w8, v1.b[1] ; CHECK-NEXT: smov w8, v1.b[1]
; CHECK-NEXT: smov w9, v0.b[1] ; CHECK-NEXT: smov w9, v0.b[1]
; CHECK-NEXT: sdiv w13, w12, w11
; CHECK-NEXT: smov w14, v1.b[2] ; CHECK-NEXT: smov w14, v1.b[2]
; CHECK-NEXT: smov w15, v0.b[2] ; CHECK-NEXT: smov w15, v0.b[2]
; CHECK-NEXT: smov w17, v1.b[3] ; CHECK-NEXT: smov w17, v1.b[3]
; CHECK-NEXT: smov w18, v0.b[3] ; CHECK-NEXT: smov w18, v0.b[3]
; CHECK-NEXT: sdiv w13, w12, w11
; CHECK-NEXT: smov w1, v1.b[4] ; CHECK-NEXT: smov w1, v1.b[4]
; CHECK-NEXT: smov w2, v0.b[4] ; CHECK-NEXT: smov w2, v0.b[4]
; CHECK-NEXT: smov w4, v1.b[5]
; CHECK-NEXT: smov w5, v0.b[5]
; CHECK-NEXT: smov w7, v1.b[6]
; CHECK-NEXT: smov w19, v0.b[6]
; CHECK-NEXT: msub w11, w13, w11, w12 ; CHECK-NEXT: msub w11, w13, w11, w12
; CHECK-NEXT: smov w12, v1.b[5]
; CHECK-NEXT: sdiv w10, w9, w8 ; CHECK-NEXT: sdiv w10, w9, w8
; CHECK-NEXT: smov w13, v0.b[5]
; CHECK-NEXT: fmov s2, w11 ; CHECK-NEXT: fmov s2, w11
; CHECK-NEXT: smov w11, v0.b[6] ; CHECK-NEXT: smov w11, v0.b[7]
; CHECK-NEXT: msub w8, w10, w8, w9 ; CHECK-NEXT: msub w8, w10, w8, w9
; CHECK-NEXT: smov w10, v1.b[6] ; CHECK-NEXT: smov w10, v1.b[7]
; CHECK-NEXT: sdiv w16, w15, w14 ; CHECK-NEXT: sdiv w16, w15, w14
; CHECK-NEXT: mov v2.b[1], w8 ; CHECK-NEXT: mov v2.b[1], w8
; CHECK-NEXT: msub w8, w16, w14, w15 ; CHECK-NEXT: msub w9, w16, w14, w15
; CHECK-NEXT: smov w15, v1.b[7]
; CHECK-NEXT: sdiv w0, w18, w17 ; CHECK-NEXT: sdiv w0, w18, w17
; CHECK-NEXT: smov w16, v0.b[7] ; CHECK-NEXT: mov v2.b[2], w9
; CHECK-NEXT: mov v2.b[2], w8 ; CHECK-NEXT: msub w13, w0, w17, w18
; CHECK-NEXT: msub w14, w0, w17, w18
; CHECK-NEXT: sdiv w3, w2, w1 ; CHECK-NEXT: sdiv w3, w2, w1
; CHECK-NEXT: mov v2.b[3], w14 ; CHECK-NEXT: mov v2.b[3], w13
; CHECK-NEXT: msub w14, w3, w1, w2 ; CHECK-NEXT: msub w14, w3, w1, w2
; CHECK-NEXT: sdiv w9, w13, w12 ; CHECK-NEXT: sdiv w6, w5, w4
; CHECK-NEXT: mov v2.b[4], w14 ; CHECK-NEXT: mov v2.b[4], w14
; CHECK-NEXT: msub w9, w9, w12, w13 ; CHECK-NEXT: msub w9, w6, w4, w5
; CHECK-NEXT: sdiv w8, w11, w10 ; CHECK-NEXT: sdiv w12, w19, w7
; CHECK-NEXT: mov v2.b[5], w9 ; CHECK-NEXT: mov v2.b[5], w9
; CHECK-NEXT: msub w12, w12, w7, w19
; CHECK-NEXT: sdiv w8, w11, w10
; CHECK-NEXT: mov v2.b[6], w12
; CHECK-NEXT: msub w8, w8, w10, w11 ; CHECK-NEXT: msub w8, w8, w10, w11
; CHECK-NEXT: sdiv w12, w16, w15
; CHECK-NEXT: mov v2.b[6], w8
; CHECK-NEXT: msub w8, w12, w15, w16
; CHECK-NEXT: mov v2.b[7], w8 ; CHECK-NEXT: mov v2.b[7], w8
; CHECK-NEXT: fmov d0, d2 ; CHECK-NEXT: fmov d0, d2
; CHECK-NEXT: ldr x19, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = srem <8 x i8> %A, %B; %tmp3 = srem <8 x i8> %A, %B;
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
} }
define <16 x i8> @srem16x8(<16 x i8> %A, <16 x i8> %B) { define <16 x i8> @srem16x8(<16 x i8> %A, <16 x i8> %B) {
; CHECK-LABEL: srem16x8: ; CHECK-LABEL: srem16x8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: stp x26, x25, [sp, #-64]! // 16-byte Folded Spill ; CHECK-NEXT: sub sp, sp, #128
; CHECK-NEXT: stp x24, x23, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: stp x28, x27, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: stp x26, x25, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: stp x24, x23, [sp, #80] // 16-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #96] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 128
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w21, -24 ; CHECK-NEXT: .cfi_offset w21, -24
; CHECK-NEXT: .cfi_offset w22, -32 ; CHECK-NEXT: .cfi_offset w22, -32
; CHECK-NEXT: .cfi_offset w23, -40 ; CHECK-NEXT: .cfi_offset w23, -40
; CHECK-NEXT: .cfi_offset w24, -48 ; CHECK-NEXT: .cfi_offset w24, -48
; CHECK-NEXT: .cfi_offset w25, -56 ; CHECK-NEXT: .cfi_offset w25, -56
; CHECK-NEXT: .cfi_offset w26, -64 ; CHECK-NEXT: .cfi_offset w26, -64
; CHECK-NEXT: smov w11, v1.b[0] ; CHECK-NEXT: .cfi_offset w27, -72
; CHECK-NEXT: smov w12, v0.b[0] ; CHECK-NEXT: .cfi_offset w28, -80
; CHECK-NEXT: .cfi_offset w30, -88
; CHECK-NEXT: .cfi_offset w29, -96
; CHECK-NEXT: smov w8, v1.b[1] ; CHECK-NEXT: smov w8, v1.b[1]
; CHECK-NEXT: smov w9, v0.b[1] ; CHECK-NEXT: smov w6, v0.b[1]
; CHECK-NEXT: smov w14, v1.b[2] ; CHECK-NEXT: smov w16, v1.b[2]
; CHECK-NEXT: smov w15, v0.b[2] ; CHECK-NEXT: smov w15, v0.b[2]
; CHECK-NEXT: str w8, [sp, #24] // 4-byte Folded Spill
; CHECK-NEXT: sdiv w8, w6, w8
; CHECK-NEXT: smov w17, v1.b[3] ; CHECK-NEXT: smov w17, v1.b[3]
; CHECK-NEXT: smov w18, v0.b[3] ; CHECK-NEXT: smov w18, v0.b[3]
; CHECK-NEXT: sdiv w13, w12, w11 ; CHECK-NEXT: smov w3, v1.b[0]
; CHECK-NEXT: smov w0, v0.b[0]
; CHECK-NEXT: smov w1, v1.b[4] ; CHECK-NEXT: smov w1, v1.b[4]
; CHECK-NEXT: smov w2, v0.b[4] ; CHECK-NEXT: smov w2, v0.b[4]
; CHECK-NEXT: smov w4, v1.b[5] ; CHECK-NEXT: smov w4, v1.b[5]
; CHECK-NEXT: smov w5, v0.b[5] ; CHECK-NEXT: smov w5, v0.b[5]
; CHECK-NEXT: smov w7, v1.b[6] ; CHECK-NEXT: smov w7, v1.b[6]
; CHECK-NEXT: smov w19, v0.b[6] ; CHECK-NEXT: smov w19, v0.b[6]
; CHECK-NEXT: smov w21, v1.b[7] ; CHECK-NEXT: smov w21, v1.b[7]
; CHECK-NEXT: smov w22, v0.b[7] ; CHECK-NEXT: smov w22, v0.b[7]
; CHECK-NEXT: smov w24, v1.b[8] ; CHECK-NEXT: smov w24, v1.b[8]
; CHECK-NEXT: smov w25, v0.b[8] ; CHECK-NEXT: smov w25, v0.b[8]
; CHECK-NEXT: msub w11, w13, w11, w12 ; CHECK-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; CHECK-NEXT: smov w12, v1.b[9] ; CHECK-NEXT: sdiv w9, w15, w16
; CHECK-NEXT: sdiv w10, w9, w8 ; CHECK-NEXT: smov w27, v1.b[9]
; CHECK-NEXT: smov w13, v0.b[9] ; CHECK-NEXT: smov w28, v0.b[9]
; CHECK-NEXT: fmov s2, w11 ; CHECK-NEXT: smov w30, v1.b[10]
; CHECK-NEXT: smov w11, v0.b[10] ; CHECK-NEXT: smov w12, v0.b[10]
; CHECK-NEXT: msub w8, w10, w8, w9 ; CHECK-NEXT: smov w11, v1.b[11]
; CHECK-NEXT: smov w10, v1.b[10] ; CHECK-NEXT: smov w10, v0.b[11]
; CHECK-NEXT: sdiv w16, w15, w14 ; CHECK-NEXT: sdiv w8, w18, w17
; CHECK-NEXT: mov v2.b[1], w8 ; CHECK-NEXT: sdiv w20, w0, w3
; CHECK-NEXT: msub w8, w16, w14, w15 ; CHECK-NEXT: stp w8, w9, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: smov w15, v1.b[11] ; CHECK-NEXT: msub w0, w20, w3, w0
; CHECK-NEXT: sdiv w0, w18, w17 ; CHECK-NEXT: sdiv w9, w2, w1
; CHECK-NEXT: smov w16, v0.b[11] ; CHECK-NEXT: ldp w23, w20, [sp, #24] // 8-byte Folded Reload
; CHECK-NEXT: mov v2.b[2], w8 ; CHECK-NEXT: fmov s2, w0
; CHECK-NEXT: msub w14, w0, w17, w18 ; CHECK-NEXT: msub w6, w20, w23, w6
; CHECK-NEXT: smov w18, v1.b[12] ; CHECK-NEXT: ldp w20, w0, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: sdiv w3, w2, w1 ; CHECK-NEXT: sdiv w8, w5, w4
; CHECK-NEXT: smov w0, v0.b[12] ; CHECK-NEXT: mov v2.b[1], w6
; CHECK-NEXT: mov v2.b[3], w14 ; CHECK-NEXT: msub w15, w0, w16, w15
; CHECK-NEXT: msub w14, w3, w1, w2 ; CHECK-NEXT: smov w16, v1.b[13]
; CHECK-NEXT: smov w2, v1.b[13] ; CHECK-NEXT: msub w17, w20, w17, w18
; CHECK-NEXT: sdiv w6, w5, w4 ; CHECK-NEXT: smov w0, v0.b[13]
; CHECK-NEXT: smov w3, v0.b[13] ; CHECK-NEXT: mov v2.b[2], w15
; CHECK-NEXT: mov v2.b[4], w14 ; CHECK-NEXT: stp w8, w9, [sp, #8] // 8-byte Folded Spill
; CHECK-NEXT: msub w17, w6, w4, w5 ; CHECK-NEXT: sdiv w9, w19, w7
; CHECK-NEXT: sdiv w20, w19, w7 ; CHECK-NEXT: ldr w6, [sp, #12] // 4-byte Folded Reload
; CHECK-NEXT: mov v2.b[5], w17 ; CHECK-NEXT: mov v2.b[3], w17
; CHECK-NEXT: msub w17, w20, w7, w19 ; CHECK-NEXT: ldr w15, [sp, #8] // 4-byte Folded Reload
; CHECK-NEXT: sdiv w23, w22, w21 ; CHECK-NEXT: msub w1, w6, w1, w2
; CHECK-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: smov w2, v0.b[14]
; CHECK-NEXT: mov v2.b[6], w17 ; CHECK-NEXT: msub w15, w15, w4, w5
; CHECK-NEXT: msub w1, w23, w21, w22 ; CHECK-NEXT: sdiv w8, w22, w21
; CHECK-NEXT: mov v2.b[4], w1
; CHECK-NEXT: smov w1, v1.b[14]
; CHECK-NEXT: mov v2.b[5], w15
; CHECK-NEXT: stp w8, w9, [sp] // 8-byte Folded Spill
; CHECK-NEXT: sdiv w26, w25, w24 ; CHECK-NEXT: sdiv w26, w25, w24
; CHECK-NEXT: ldp x22, x21, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldp w4, w17, [sp] // 8-byte Folded Reload
; CHECK-NEXT: mov v2.b[7], w1 ; CHECK-NEXT: smov w9, v1.b[12]
; CHECK-NEXT: msub w1, w26, w24, w25 ; CHECK-NEXT: smov w8, v0.b[12]
; CHECK-NEXT: sdiv w9, w13, w12 ; CHECK-NEXT: msub w17, w17, w7, w19
; CHECK-NEXT: ldp x24, x23, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: msub w4, w4, w21, w22
; CHECK-NEXT: mov v2.b[8], w1 ; CHECK-NEXT: msub w5, w26, w24, w25
; CHECK-NEXT: msub w9, w9, w12, w13 ; CHECK-NEXT: sdiv w29, w28, w27
; CHECK-NEXT: smov w13, v1.b[15] ; CHECK-NEXT: mov v2.b[6], w17
; CHECK-NEXT: sdiv w8, w11, w10 ; CHECK-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
; CHECK-NEXT: mov v2.b[9], w9 ; CHECK-NEXT: mov v2.b[7], w4
; CHECK-NEXT: smov w9, v1.b[14] ; CHECK-NEXT: smov w4, v0.b[15]
; CHECK-NEXT: msub w8, w8, w10, w11 ; CHECK-NEXT: ldp x22, x21, [sp, #96] // 16-byte Folded Reload
; CHECK-NEXT: smov w10, v0.b[14] ; CHECK-NEXT: mov v2.b[8], w5
; CHECK-NEXT: sdiv w14, w16, w15 ; CHECK-NEXT: ldp x24, x23, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: mov v2.b[10], w8 ; CHECK-NEXT: msub w17, w29, w27, w28
; CHECK-NEXT: msub w11, w14, w15, w16 ; CHECK-NEXT: sdiv w14, w12, w30
; CHECK-NEXT: smov w14, v0.b[15] ; CHECK-NEXT: ldp x26, x25, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: sdiv w17, w0, w18 ; CHECK-NEXT: mov v2.b[9], w17
; CHECK-NEXT: mov v2.b[11], w11 ; CHECK-NEXT: ldp x28, x27, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: msub w11, w17, w18, w0 ; CHECK-NEXT: msub w12, w14, w30, w12
; CHECK-NEXT: sdiv w12, w3, w2 ; CHECK-NEXT: smov w14, v1.b[15]
; CHECK-NEXT: mov v2.b[12], w11 ; CHECK-NEXT: sdiv w13, w10, w11
; CHECK-NEXT: msub w12, w12, w2, w3 ; CHECK-NEXT: ldp x29, x30, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: sdiv w8, w10, w9 ; CHECK-NEXT: mov v2.b[10], w12
; CHECK-NEXT: mov v2.b[13], w12 ; CHECK-NEXT: msub w10, w13, w11, w10
; CHECK-NEXT: msub w8, w8, w9, w10 ; CHECK-NEXT: sdiv w3, w8, w9
; CHECK-NEXT: sdiv w11, w14, w13 ; CHECK-NEXT: mov v2.b[11], w10
; CHECK-NEXT: mov v2.b[14], w8 ; CHECK-NEXT: msub w8, w3, w9, w8
; CHECK-NEXT: msub w8, w11, w13, w14 ; CHECK-NEXT: sdiv w18, w0, w16
; CHECK-NEXT: mov v2.b[12], w8
; CHECK-NEXT: msub w9, w18, w16, w0
; CHECK-NEXT: sdiv w15, w2, w1
; CHECK-NEXT: mov v2.b[13], w9
; CHECK-NEXT: msub w10, w15, w1, w2
; CHECK-NEXT: sdiv w11, w4, w14
; CHECK-NEXT: mov v2.b[14], w10
; CHECK-NEXT: msub w8, w11, w14, w4
; CHECK-NEXT: mov v2.b[15], w8 ; CHECK-NEXT: mov v2.b[15], w8
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ldp x26, x25, [sp], #64 // 16-byte Folded Reload ; CHECK-NEXT: add sp, sp, #128
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = srem <16 x i8> %A, %B; %tmp3 = srem <16 x i8> %A, %B;
ret <16 x i8> %tmp3 ret <16 x i8> %tmp3
} }
define <1 x i16> @srem1x16(<1 x i16> %A, <1 x i16> %B) { define <1 x i16> @srem1x16(<1 x i16> %A, <1 x i16> %B) {
; CHECK-LABEL: srem1x16: ; CHECK-LABEL: srem1x16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
Show All 13 Lines
; CHECK-LABEL: srem4x16: ; CHECK-LABEL: srem4x16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 ; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: smov w11, v1.h[0] ; CHECK-NEXT: smov w11, v1.h[0]
; CHECK-NEXT: smov w12, v0.h[0] ; CHECK-NEXT: smov w12, v0.h[0]
; CHECK-NEXT: smov w8, v1.h[1] ; CHECK-NEXT: smov w8, v1.h[1]
; CHECK-NEXT: smov w9, v0.h[1] ; CHECK-NEXT: smov w9, v0.h[1]
; CHECK-NEXT: sdiv w13, w12, w11
; CHECK-NEXT: smov w14, v1.h[2] ; CHECK-NEXT: smov w14, v1.h[2]
; CHECK-NEXT: smov w15, v0.h[2] ; CHECK-NEXT: smov w15, v0.h[2]
; CHECK-NEXT: sdiv w13, w12, w11 ; CHECK-NEXT: smov w17, v1.h[3]
; CHECK-NEXT: smov w18, v0.h[3]
; CHECK-NEXT: msub w11, w13, w11, w12 ; CHECK-NEXT: msub w11, w13, w11, w12
; CHECK-NEXT: smov w12, v1.h[3]
; CHECK-NEXT: sdiv w10, w9, w8 ; CHECK-NEXT: sdiv w10, w9, w8
; CHECK-NEXT: smov w13, v0.h[3]
; CHECK-NEXT: fmov s0, w11 ; CHECK-NEXT: fmov s0, w11
; CHECK-NEXT: msub w8, w10, w8, w9 ; CHECK-NEXT: msub w8, w10, w8, w9
; CHECK-NEXT: sdiv w16, w15, w14 ; CHECK-NEXT: sdiv w16, w15, w14
; CHECK-NEXT: mov v0.h[1], w8 ; CHECK-NEXT: mov v0.h[1], w8
; CHECK-NEXT: msub w10, w16, w14, w15 ; CHECK-NEXT: msub w9, w16, w14, w15
; CHECK-NEXT: sdiv w9, w13, w12 ; CHECK-NEXT: sdiv w12, w18, w17
; CHECK-NEXT: mov v0.h[2], w10 ; CHECK-NEXT: mov v0.h[2], w9
; CHECK-NEXT: msub w8, w9, w12, w13 ; CHECK-NEXT: msub w8, w12, w17, w18
; CHECK-NEXT: mov v0.h[3], w8 ; CHECK-NEXT: mov v0.h[3], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = srem <4 x i16> %A, %B; %tmp3 = srem <4 x i16> %A, %B;
ret <4 x i16> %tmp3 ret <4 x i16> %tmp3
} }
define <8 x i16> @srem8x16(<8 x i16> %A, <8 x i16> %B) { define <8 x i16> @srem8x16(<8 x i16> %A, <8 x i16> %B) {
; CHECK-LABEL: srem8x16: ; CHECK-LABEL: srem8x16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x19, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -16
; CHECK-NEXT: smov w11, v1.h[0] ; CHECK-NEXT: smov w11, v1.h[0]
; CHECK-NEXT: smov w12, v0.h[0] ; CHECK-NEXT: smov w12, v0.h[0]
; CHECK-NEXT: smov w8, v1.h[1] ; CHECK-NEXT: smov w8, v1.h[1]
; CHECK-NEXT: smov w9, v0.h[1] ; CHECK-NEXT: smov w9, v0.h[1]
; CHECK-NEXT: sdiv w13, w12, w11
; CHECK-NEXT: smov w14, v1.h[2] ; CHECK-NEXT: smov w14, v1.h[2]
; CHECK-NEXT: smov w15, v0.h[2] ; CHECK-NEXT: smov w15, v0.h[2]
; CHECK-NEXT: smov w17, v1.h[3] ; CHECK-NEXT: smov w17, v1.h[3]
; CHECK-NEXT: smov w18, v0.h[3] ; CHECK-NEXT: smov w18, v0.h[3]
; CHECK-NEXT: sdiv w13, w12, w11
; CHECK-NEXT: smov w1, v1.h[4] ; CHECK-NEXT: smov w1, v1.h[4]
; CHECK-NEXT: smov w2, v0.h[4] ; CHECK-NEXT: smov w2, v0.h[4]
; CHECK-NEXT: smov w4, v1.h[5]
; CHECK-NEXT: smov w5, v0.h[5]
; CHECK-NEXT: smov w7, v1.h[6]
; CHECK-NEXT: smov w19, v0.h[6]
; CHECK-NEXT: msub w11, w13, w11, w12 ; CHECK-NEXT: msub w11, w13, w11, w12
; CHECK-NEXT: smov w12, v1.h[5]
; CHECK-NEXT: sdiv w10, w9, w8 ; CHECK-NEXT: sdiv w10, w9, w8
; CHECK-NEXT: smov w13, v0.h[5]
; CHECK-NEXT: fmov s2, w11 ; CHECK-NEXT: fmov s2, w11
; CHECK-NEXT: smov w11, v0.h[6] ; CHECK-NEXT: smov w11, v0.h[7]
; CHECK-NEXT: msub w8, w10, w8, w9 ; CHECK-NEXT: msub w8, w10, w8, w9
; CHECK-NEXT: smov w10, v1.h[6] ; CHECK-NEXT: smov w10, v1.h[7]
; CHECK-NEXT: sdiv w16, w15, w14 ; CHECK-NEXT: sdiv w16, w15, w14
; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: mov v2.h[1], w8
; CHECK-NEXT: msub w8, w16, w14, w15 ; CHECK-NEXT: msub w9, w16, w14, w15
; CHECK-NEXT: smov w15, v1.h[7]
; CHECK-NEXT: sdiv w0, w18, w17 ; CHECK-NEXT: sdiv w0, w18, w17
; CHECK-NEXT: smov w16, v0.h[7] ; CHECK-NEXT: mov v2.h[2], w9
; CHECK-NEXT: mov v2.h[2], w8 ; CHECK-NEXT: msub w13, w0, w17, w18
; CHECK-NEXT: msub w14, w0, w17, w18
; CHECK-NEXT: sdiv w3, w2, w1 ; CHECK-NEXT: sdiv w3, w2, w1
; CHECK-NEXT: mov v2.h[3], w14 ; CHECK-NEXT: mov v2.h[3], w13
; CHECK-NEXT: msub w14, w3, w1, w2 ; CHECK-NEXT: msub w14, w3, w1, w2
; CHECK-NEXT: sdiv w9, w13, w12 ; CHECK-NEXT: sdiv w6, w5, w4
; CHECK-NEXT: mov v2.h[4], w14 ; CHECK-NEXT: mov v2.h[4], w14
; CHECK-NEXT: msub w9, w9, w12, w13 ; CHECK-NEXT: msub w9, w6, w4, w5
; CHECK-NEXT: sdiv w8, w11, w10 ; CHECK-NEXT: sdiv w12, w19, w7
; CHECK-NEXT: mov v2.h[5], w9 ; CHECK-NEXT: mov v2.h[5], w9
; CHECK-NEXT: msub w12, w12, w7, w19
; CHECK-NEXT: sdiv w8, w11, w10
; CHECK-NEXT: mov v2.h[6], w12
; CHECK-NEXT: msub w8, w8, w10, w11 ; CHECK-NEXT: msub w8, w8, w10, w11
; CHECK-NEXT: sdiv w12, w16, w15
; CHECK-NEXT: mov v2.h[6], w8
; CHECK-NEXT: msub w8, w12, w15, w16
; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: mov v2.h[7], w8
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ldr x19, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = srem <8 x i16> %A, %B; %tmp3 = srem <8 x i16> %A, %B;
ret <8 x i16> %tmp3 ret <8 x i16> %tmp3
} }
define <1 x i32> @srem1x32(<1 x i32> %A, <1 x i32> %B) { define <1 x i32> @srem1x32(<1 x i32> %A, <1 x i32> %B) {
; CHECK-LABEL: srem1x32: ; CHECK-LABEL: srem1x32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
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; CHECK-NEXT: mov w17, v1.s[3] ; CHECK-NEXT: mov w17, v1.s[3]
; CHECK-NEXT: mov w18, v0.s[3] ; CHECK-NEXT: mov w18, v0.s[3]
; CHECK-NEXT: msub w11, w13, w11, w12 ; CHECK-NEXT: msub w11, w13, w11, w12
; CHECK-NEXT: sdiv w10, w9, w8 ; CHECK-NEXT: sdiv w10, w9, w8
; CHECK-NEXT: fmov s0, w11 ; CHECK-NEXT: fmov s0, w11
; CHECK-NEXT: msub w8, w10, w8, w9 ; CHECK-NEXT: msub w8, w10, w8, w9
; CHECK-NEXT: sdiv w16, w15, w14 ; CHECK-NEXT: sdiv w16, w15, w14
; CHECK-NEXT: mov v0.s[1], w8 ; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: msub w10, w16, w14, w15 ; CHECK-NEXT: msub w9, w16, w14, w15
; CHECK-NEXT: sdiv w9, w18, w17 ; CHECK-NEXT: sdiv w12, w18, w17
; CHECK-NEXT: mov v0.s[2], w10 ; CHECK-NEXT: mov v0.s[2], w9
; CHECK-NEXT: msub w8, w9, w17, w18 ; CHECK-NEXT: msub w8, w12, w17, w18
; CHECK-NEXT: mov v0.s[3], w8 ; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = srem <4 x i32> %A, %B; %tmp3 = srem <4 x i32> %A, %B;
ret <4 x i32> %tmp3 ret <4 x i32> %tmp3
} }
define <1 x i64> @srem1x64(<1 x i64> %A, <1 x i64> %B) { define <1 x i64> @srem1x64(<1 x i64> %A, <1 x i64> %B) {
; CHECK-LABEL: srem1x64: ; CHECK-LABEL: srem1x64:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = urem <1 x i8> %A, %B; %tmp3 = urem <1 x i8> %A, %B;
ret <1 x i8> %tmp3 ret <1 x i8> %tmp3
} }
define <8 x i8> @urem8x8(<8 x i8> %A, <8 x i8> %B) { define <8 x i8> @urem8x8(<8 x i8> %A, <8 x i8> %B) {
; CHECK-LABEL: urem8x8: ; CHECK-LABEL: urem8x8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x19, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -16
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 ; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w11, v1.b[0] ; CHECK-NEXT: umov w11, v1.b[0]
; CHECK-NEXT: umov w12, v0.b[0] ; CHECK-NEXT: umov w12, v0.b[0]
; CHECK-NEXT: umov w8, v1.b[1] ; CHECK-NEXT: umov w8, v1.b[1]
; CHECK-NEXT: umov w9, v0.b[1] ; CHECK-NEXT: umov w9, v0.b[1]
; CHECK-NEXT: udiv w13, w12, w11
; CHECK-NEXT: umov w14, v1.b[2] ; CHECK-NEXT: umov w14, v1.b[2]
; CHECK-NEXT: umov w15, v0.b[2] ; CHECK-NEXT: umov w15, v0.b[2]
; CHECK-NEXT: umov w17, v1.b[3] ; CHECK-NEXT: umov w17, v1.b[3]
; CHECK-NEXT: umov w18, v0.b[3] ; CHECK-NEXT: umov w18, v0.b[3]
; CHECK-NEXT: udiv w13, w12, w11
; CHECK-NEXT: umov w1, v1.b[4] ; CHECK-NEXT: umov w1, v1.b[4]
; CHECK-NEXT: umov w2, v0.b[4] ; CHECK-NEXT: umov w2, v0.b[4]
; CHECK-NEXT: umov w4, v1.b[5]
; CHECK-NEXT: umov w5, v0.b[5]
; CHECK-NEXT: umov w7, v1.b[6]
; CHECK-NEXT: umov w19, v0.b[6]
; CHECK-NEXT: msub w11, w13, w11, w12 ; CHECK-NEXT: msub w11, w13, w11, w12
; CHECK-NEXT: umov w12, v1.b[5]
; CHECK-NEXT: udiv w10, w9, w8 ; CHECK-NEXT: udiv w10, w9, w8
; CHECK-NEXT: umov w13, v0.b[5]
; CHECK-NEXT: fmov s2, w11 ; CHECK-NEXT: fmov s2, w11
; CHECK-NEXT: umov w11, v0.b[6] ; CHECK-NEXT: umov w11, v0.b[7]
; CHECK-NEXT: msub w8, w10, w8, w9 ; CHECK-NEXT: msub w8, w10, w8, w9
; CHECK-NEXT: umov w10, v1.b[6] ; CHECK-NEXT: umov w10, v1.b[7]
; CHECK-NEXT: udiv w16, w15, w14 ; CHECK-NEXT: udiv w16, w15, w14
; CHECK-NEXT: mov v2.b[1], w8 ; CHECK-NEXT: mov v2.b[1], w8
; CHECK-NEXT: msub w8, w16, w14, w15 ; CHECK-NEXT: msub w9, w16, w14, w15
; CHECK-NEXT: umov w15, v1.b[7]
; CHECK-NEXT: udiv w0, w18, w17 ; CHECK-NEXT: udiv w0, w18, w17
; CHECK-NEXT: umov w16, v0.b[7] ; CHECK-NEXT: mov v2.b[2], w9
; CHECK-NEXT: mov v2.b[2], w8 ; CHECK-NEXT: msub w13, w0, w17, w18
; CHECK-NEXT: msub w14, w0, w17, w18
; CHECK-NEXT: udiv w3, w2, w1 ; CHECK-NEXT: udiv w3, w2, w1
; CHECK-NEXT: mov v2.b[3], w14 ; CHECK-NEXT: mov v2.b[3], w13
; CHECK-NEXT: msub w14, w3, w1, w2 ; CHECK-NEXT: msub w14, w3, w1, w2
; CHECK-NEXT: udiv w9, w13, w12 ; CHECK-NEXT: udiv w6, w5, w4
; CHECK-NEXT: mov v2.b[4], w14 ; CHECK-NEXT: mov v2.b[4], w14
; CHECK-NEXT: msub w9, w9, w12, w13 ; CHECK-NEXT: msub w9, w6, w4, w5
; CHECK-NEXT: udiv w8, w11, w10 ; CHECK-NEXT: udiv w12, w19, w7
; CHECK-NEXT: mov v2.b[5], w9 ; CHECK-NEXT: mov v2.b[5], w9
; CHECK-NEXT: msub w12, w12, w7, w19
; CHECK-NEXT: udiv w8, w11, w10
; CHECK-NEXT: mov v2.b[6], w12
; CHECK-NEXT: msub w8, w8, w10, w11 ; CHECK-NEXT: msub w8, w8, w10, w11
; CHECK-NEXT: udiv w12, w16, w15
; CHECK-NEXT: mov v2.b[6], w8
; CHECK-NEXT: msub w8, w12, w15, w16
; CHECK-NEXT: mov v2.b[7], w8 ; CHECK-NEXT: mov v2.b[7], w8
; CHECK-NEXT: fmov d0, d2 ; CHECK-NEXT: fmov d0, d2
; CHECK-NEXT: ldr x19, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = urem <8 x i8> %A, %B; %tmp3 = urem <8 x i8> %A, %B;
ret <8 x i8> %tmp3 ret <8 x i8> %tmp3
} }
define <16 x i8> @urem16x8(<16 x i8> %A, <16 x i8> %B) { define <16 x i8> @urem16x8(<16 x i8> %A, <16 x i8> %B) {
; CHECK-LABEL: urem16x8: ; CHECK-LABEL: urem16x8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: stp x26, x25, [sp, #-64]! // 16-byte Folded Spill ; CHECK-NEXT: sub sp, sp, #128
; CHECK-NEXT: stp x24, x23, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: stp x28, x27, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: stp x26, x25, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: stp x24, x23, [sp, #80] // 16-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #96] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 128
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w21, -24 ; CHECK-NEXT: .cfi_offset w21, -24
; CHECK-NEXT: .cfi_offset w22, -32 ; CHECK-NEXT: .cfi_offset w22, -32
; CHECK-NEXT: .cfi_offset w23, -40 ; CHECK-NEXT: .cfi_offset w23, -40
; CHECK-NEXT: .cfi_offset w24, -48 ; CHECK-NEXT: .cfi_offset w24, -48
; CHECK-NEXT: .cfi_offset w25, -56 ; CHECK-NEXT: .cfi_offset w25, -56
; CHECK-NEXT: .cfi_offset w26, -64 ; CHECK-NEXT: .cfi_offset w26, -64
; CHECK-NEXT: umov w11, v1.b[0] ; CHECK-NEXT: .cfi_offset w27, -72
; CHECK-NEXT: umov w12, v0.b[0] ; CHECK-NEXT: .cfi_offset w28, -80
; CHECK-NEXT: .cfi_offset w30, -88
; CHECK-NEXT: .cfi_offset w29, -96
; CHECK-NEXT: umov w8, v1.b[1] ; CHECK-NEXT: umov w8, v1.b[1]
; CHECK-NEXT: umov w9, v0.b[1] ; CHECK-NEXT: umov w6, v0.b[1]
; CHECK-NEXT: umov w14, v1.b[2] ; CHECK-NEXT: umov w16, v1.b[2]
; CHECK-NEXT: umov w15, v0.b[2] ; CHECK-NEXT: umov w15, v0.b[2]
; CHECK-NEXT: str w8, [sp, #24] // 4-byte Folded Spill
; CHECK-NEXT: udiv w8, w6, w8
; CHECK-NEXT: umov w17, v1.b[3] ; CHECK-NEXT: umov w17, v1.b[3]
; CHECK-NEXT: umov w18, v0.b[3] ; CHECK-NEXT: umov w18, v0.b[3]
; CHECK-NEXT: udiv w13, w12, w11 ; CHECK-NEXT: umov w3, v1.b[0]
; CHECK-NEXT: umov w0, v0.b[0]
; CHECK-NEXT: umov w1, v1.b[4] ; CHECK-NEXT: umov w1, v1.b[4]
; CHECK-NEXT: umov w2, v0.b[4] ; CHECK-NEXT: umov w2, v0.b[4]
; CHECK-NEXT: umov w4, v1.b[5] ; CHECK-NEXT: umov w4, v1.b[5]
; CHECK-NEXT: umov w5, v0.b[5] ; CHECK-NEXT: umov w5, v0.b[5]
; CHECK-NEXT: umov w7, v1.b[6] ; CHECK-NEXT: umov w7, v1.b[6]
; CHECK-NEXT: umov w19, v0.b[6] ; CHECK-NEXT: umov w19, v0.b[6]
; CHECK-NEXT: umov w21, v1.b[7] ; CHECK-NEXT: umov w21, v1.b[7]
; CHECK-NEXT: umov w22, v0.b[7] ; CHECK-NEXT: umov w22, v0.b[7]
; CHECK-NEXT: umov w24, v1.b[8] ; CHECK-NEXT: umov w24, v1.b[8]
; CHECK-NEXT: umov w25, v0.b[8] ; CHECK-NEXT: umov w25, v0.b[8]
; CHECK-NEXT: msub w11, w13, w11, w12 ; CHECK-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; CHECK-NEXT: umov w12, v1.b[9] ; CHECK-NEXT: udiv w9, w15, w16
; CHECK-NEXT: udiv w10, w9, w8 ; CHECK-NEXT: umov w27, v1.b[9]
; CHECK-NEXT: umov w13, v0.b[9] ; CHECK-NEXT: umov w28, v0.b[9]
; CHECK-NEXT: fmov s2, w11 ; CHECK-NEXT: umov w30, v1.b[10]
; CHECK-NEXT: umov w11, v0.b[10] ; CHECK-NEXT: umov w12, v0.b[10]
; CHECK-NEXT: msub w8, w10, w8, w9 ; CHECK-NEXT: umov w11, v1.b[11]
; CHECK-NEXT: umov w10, v1.b[10] ; CHECK-NEXT: umov w10, v0.b[11]
; CHECK-NEXT: udiv w16, w15, w14 ; CHECK-NEXT: udiv w8, w18, w17
; CHECK-NEXT: mov v2.b[1], w8 ; CHECK-NEXT: udiv w20, w0, w3
; CHECK-NEXT: msub w8, w16, w14, w15 ; CHECK-NEXT: stp w8, w9, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: umov w15, v1.b[11] ; CHECK-NEXT: msub w0, w20, w3, w0
; CHECK-NEXT: udiv w0, w18, w17 ; CHECK-NEXT: udiv w9, w2, w1
; CHECK-NEXT: umov w16, v0.b[11] ; CHECK-NEXT: ldp w23, w20, [sp, #24] // 8-byte Folded Reload
; CHECK-NEXT: mov v2.b[2], w8 ; CHECK-NEXT: fmov s2, w0
; CHECK-NEXT: msub w14, w0, w17, w18 ; CHECK-NEXT: msub w6, w20, w23, w6
; CHECK-NEXT: umov w18, v1.b[12] ; CHECK-NEXT: ldp w20, w0, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: udiv w3, w2, w1 ; CHECK-NEXT: udiv w8, w5, w4
; CHECK-NEXT: umov w0, v0.b[12] ; CHECK-NEXT: mov v2.b[1], w6
; CHECK-NEXT: mov v2.b[3], w14 ; CHECK-NEXT: msub w15, w0, w16, w15
; CHECK-NEXT: msub w14, w3, w1, w2 ; CHECK-NEXT: umov w16, v1.b[13]
; CHECK-NEXT: umov w2, v1.b[13] ; CHECK-NEXT: msub w17, w20, w17, w18
; CHECK-NEXT: udiv w6, w5, w4 ; CHECK-NEXT: umov w0, v0.b[13]
; CHECK-NEXT: umov w3, v0.b[13] ; CHECK-NEXT: mov v2.b[2], w15
; CHECK-NEXT: mov v2.b[4], w14 ; CHECK-NEXT: stp w8, w9, [sp, #8] // 8-byte Folded Spill
; CHECK-NEXT: msub w17, w6, w4, w5 ; CHECK-NEXT: udiv w9, w19, w7
; CHECK-NEXT: udiv w20, w19, w7 ; CHECK-NEXT: ldr w6, [sp, #12] // 4-byte Folded Reload
; CHECK-NEXT: mov v2.b[5], w17 ; CHECK-NEXT: mov v2.b[3], w17
; CHECK-NEXT: msub w17, w20, w7, w19 ; CHECK-NEXT: ldr w15, [sp, #8] // 4-byte Folded Reload
; CHECK-NEXT: udiv w23, w22, w21 ; CHECK-NEXT: msub w1, w6, w1, w2
; CHECK-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: umov w2, v0.b[14]
; CHECK-NEXT: mov v2.b[6], w17 ; CHECK-NEXT: msub w15, w15, w4, w5
; CHECK-NEXT: msub w1, w23, w21, w22 ; CHECK-NEXT: udiv w8, w22, w21
; CHECK-NEXT: mov v2.b[4], w1
; CHECK-NEXT: umov w1, v1.b[14]
; CHECK-NEXT: mov v2.b[5], w15
; CHECK-NEXT: stp w8, w9, [sp] // 8-byte Folded Spill
; CHECK-NEXT: udiv w26, w25, w24 ; CHECK-NEXT: udiv w26, w25, w24
; CHECK-NEXT: ldp x22, x21, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldp w4, w17, [sp] // 8-byte Folded Reload
; CHECK-NEXT: mov v2.b[7], w1 ; CHECK-NEXT: umov w9, v1.b[12]
; CHECK-NEXT: msub w1, w26, w24, w25 ; CHECK-NEXT: umov w8, v0.b[12]
; CHECK-NEXT: udiv w9, w13, w12 ; CHECK-NEXT: msub w17, w17, w7, w19
; CHECK-NEXT: ldp x24, x23, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: msub w4, w4, w21, w22
; CHECK-NEXT: mov v2.b[8], w1 ; CHECK-NEXT: msub w5, w26, w24, w25
; CHECK-NEXT: msub w9, w9, w12, w13 ; CHECK-NEXT: udiv w29, w28, w27
; CHECK-NEXT: umov w13, v1.b[15] ; CHECK-NEXT: mov v2.b[6], w17
; CHECK-NEXT: udiv w8, w11, w10 ; CHECK-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
; CHECK-NEXT: mov v2.b[9], w9 ; CHECK-NEXT: mov v2.b[7], w4
; CHECK-NEXT: umov w9, v1.b[14] ; CHECK-NEXT: umov w4, v0.b[15]
; CHECK-NEXT: msub w8, w8, w10, w11 ; CHECK-NEXT: ldp x22, x21, [sp, #96] // 16-byte Folded Reload
; CHECK-NEXT: umov w10, v0.b[14] ; CHECK-NEXT: mov v2.b[8], w5
; CHECK-NEXT: udiv w14, w16, w15 ; CHECK-NEXT: ldp x24, x23, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: mov v2.b[10], w8 ; CHECK-NEXT: msub w17, w29, w27, w28
; CHECK-NEXT: msub w11, w14, w15, w16 ; CHECK-NEXT: udiv w14, w12, w30
; CHECK-NEXT: umov w14, v0.b[15] ; CHECK-NEXT: ldp x26, x25, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: udiv w17, w0, w18 ; CHECK-NEXT: mov v2.b[9], w17
; CHECK-NEXT: mov v2.b[11], w11 ; CHECK-NEXT: ldp x28, x27, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: msub w11, w17, w18, w0 ; CHECK-NEXT: msub w12, w14, w30, w12
; CHECK-NEXT: udiv w12, w3, w2 ; CHECK-NEXT: umov w14, v1.b[15]
; CHECK-NEXT: mov v2.b[12], w11 ; CHECK-NEXT: udiv w13, w10, w11
; CHECK-NEXT: msub w12, w12, w2, w3 ; CHECK-NEXT: ldp x29, x30, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: udiv w8, w10, w9 ; CHECK-NEXT: mov v2.b[10], w12
; CHECK-NEXT: mov v2.b[13], w12 ; CHECK-NEXT: msub w10, w13, w11, w10
; CHECK-NEXT: msub w8, w8, w9, w10 ; CHECK-NEXT: udiv w3, w8, w9
; CHECK-NEXT: udiv w11, w14, w13 ; CHECK-NEXT: mov v2.b[11], w10
; CHECK-NEXT: mov v2.b[14], w8 ; CHECK-NEXT: msub w8, w3, w9, w8
; CHECK-NEXT: msub w8, w11, w13, w14 ; CHECK-NEXT: udiv w18, w0, w16
; CHECK-NEXT: mov v2.b[12], w8
; CHECK-NEXT: msub w9, w18, w16, w0
; CHECK-NEXT: udiv w15, w2, w1
; CHECK-NEXT: mov v2.b[13], w9
; CHECK-NEXT: msub w10, w15, w1, w2
; CHECK-NEXT: udiv w11, w4, w14
; CHECK-NEXT: mov v2.b[14], w10
; CHECK-NEXT: msub w8, w11, w14, w4
; CHECK-NEXT: mov v2.b[15], w8 ; CHECK-NEXT: mov v2.b[15], w8
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ldp x26, x25, [sp], #64 // 16-byte Folded Reload ; CHECK-NEXT: add sp, sp, #128
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = urem <16 x i8> %A, %B; %tmp3 = urem <16 x i8> %A, %B;
ret <16 x i8> %tmp3 ret <16 x i8> %tmp3
} }
define <1 x i16> @urem1x16(<1 x i16> %A, <1 x i16> %B) { define <1 x i16> @urem1x16(<1 x i16> %A, <1 x i16> %B) {
; CHECK-LABEL: urem1x16: ; CHECK-LABEL: urem1x16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
Show All 13 Lines
; CHECK-LABEL: urem4x16: ; CHECK-LABEL: urem4x16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 ; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w11, v1.h[0] ; CHECK-NEXT: umov w11, v1.h[0]
; CHECK-NEXT: umov w12, v0.h[0] ; CHECK-NEXT: umov w12, v0.h[0]
; CHECK-NEXT: umov w8, v1.h[1] ; CHECK-NEXT: umov w8, v1.h[1]
; CHECK-NEXT: umov w9, v0.h[1] ; CHECK-NEXT: umov w9, v0.h[1]
; CHECK-NEXT: udiv w13, w12, w11
; CHECK-NEXT: umov w14, v1.h[2] ; CHECK-NEXT: umov w14, v1.h[2]
; CHECK-NEXT: umov w15, v0.h[2] ; CHECK-NEXT: umov w15, v0.h[2]
; CHECK-NEXT: udiv w13, w12, w11 ; CHECK-NEXT: umov w17, v1.h[3]
; CHECK-NEXT: umov w18, v0.h[3]
; CHECK-NEXT: msub w11, w13, w11, w12 ; CHECK-NEXT: msub w11, w13, w11, w12
; CHECK-NEXT: umov w12, v1.h[3]
; CHECK-NEXT: udiv w10, w9, w8 ; CHECK-NEXT: udiv w10, w9, w8
; CHECK-NEXT: umov w13, v0.h[3]
; CHECK-NEXT: fmov s0, w11 ; CHECK-NEXT: fmov s0, w11
; CHECK-NEXT: msub w8, w10, w8, w9 ; CHECK-NEXT: msub w8, w10, w8, w9
; CHECK-NEXT: udiv w16, w15, w14 ; CHECK-NEXT: udiv w16, w15, w14
; CHECK-NEXT: mov v0.h[1], w8 ; CHECK-NEXT: mov v0.h[1], w8
; CHECK-NEXT: msub w10, w16, w14, w15 ; CHECK-NEXT: msub w9, w16, w14, w15
; CHECK-NEXT: udiv w9, w13, w12 ; CHECK-NEXT: udiv w12, w18, w17
; CHECK-NEXT: mov v0.h[2], w10 ; CHECK-NEXT: mov v0.h[2], w9
; CHECK-NEXT: msub w8, w9, w12, w13 ; CHECK-NEXT: msub w8, w12, w17, w18
; CHECK-NEXT: mov v0.h[3], w8 ; CHECK-NEXT: mov v0.h[3], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = urem <4 x i16> %A, %B; %tmp3 = urem <4 x i16> %A, %B;
ret <4 x i16> %tmp3 ret <4 x i16> %tmp3
} }
define <8 x i16> @urem8x16(<8 x i16> %A, <8 x i16> %B) { define <8 x i16> @urem8x16(<8 x i16> %A, <8 x i16> %B) {
; CHECK-LABEL: urem8x16: ; CHECK-LABEL: urem8x16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x19, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -16
; CHECK-NEXT: umov w11, v1.h[0] ; CHECK-NEXT: umov w11, v1.h[0]
; CHECK-NEXT: umov w12, v0.h[0] ; CHECK-NEXT: umov w12, v0.h[0]
; CHECK-NEXT: umov w8, v1.h[1] ; CHECK-NEXT: umov w8, v1.h[1]
; CHECK-NEXT: umov w9, v0.h[1] ; CHECK-NEXT: umov w9, v0.h[1]
; CHECK-NEXT: udiv w13, w12, w11
; CHECK-NEXT: umov w14, v1.h[2] ; CHECK-NEXT: umov w14, v1.h[2]
; CHECK-NEXT: umov w15, v0.h[2] ; CHECK-NEXT: umov w15, v0.h[2]
; CHECK-NEXT: umov w17, v1.h[3] ; CHECK-NEXT: umov w17, v1.h[3]
; CHECK-NEXT: umov w18, v0.h[3] ; CHECK-NEXT: umov w18, v0.h[3]
; CHECK-NEXT: udiv w13, w12, w11
; CHECK-NEXT: umov w1, v1.h[4] ; CHECK-NEXT: umov w1, v1.h[4]
; CHECK-NEXT: umov w2, v0.h[4] ; CHECK-NEXT: umov w2, v0.h[4]
; CHECK-NEXT: umov w4, v1.h[5]
; CHECK-NEXT: umov w5, v0.h[5]
; CHECK-NEXT: umov w7, v1.h[6]
; CHECK-NEXT: umov w19, v0.h[6]
; CHECK-NEXT: msub w11, w13, w11, w12 ; CHECK-NEXT: msub w11, w13, w11, w12
; CHECK-NEXT: umov w12, v1.h[5]
; CHECK-NEXT: udiv w10, w9, w8 ; CHECK-NEXT: udiv w10, w9, w8
; CHECK-NEXT: umov w13, v0.h[5]
; CHECK-NEXT: fmov s2, w11 ; CHECK-NEXT: fmov s2, w11
; CHECK-NEXT: umov w11, v0.h[6] ; CHECK-NEXT: umov w11, v0.h[7]
; CHECK-NEXT: msub w8, w10, w8, w9 ; CHECK-NEXT: msub w8, w10, w8, w9
; CHECK-NEXT: umov w10, v1.h[6] ; CHECK-NEXT: umov w10, v1.h[7]
; CHECK-NEXT: udiv w16, w15, w14 ; CHECK-NEXT: udiv w16, w15, w14
; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: mov v2.h[1], w8
; CHECK-NEXT: msub w8, w16, w14, w15 ; CHECK-NEXT: msub w9, w16, w14, w15
; CHECK-NEXT: umov w15, v1.h[7]
; CHECK-NEXT: udiv w0, w18, w17 ; CHECK-NEXT: udiv w0, w18, w17
; CHECK-NEXT: umov w16, v0.h[7] ; CHECK-NEXT: mov v2.h[2], w9
; CHECK-NEXT: mov v2.h[2], w8 ; CHECK-NEXT: msub w13, w0, w17, w18
; CHECK-NEXT: msub w14, w0, w17, w18
; CHECK-NEXT: udiv w3, w2, w1 ; CHECK-NEXT: udiv w3, w2, w1
; CHECK-NEXT: mov v2.h[3], w14 ; CHECK-NEXT: mov v2.h[3], w13
; CHECK-NEXT: msub w14, w3, w1, w2 ; CHECK-NEXT: msub w14, w3, w1, w2
; CHECK-NEXT: udiv w9, w13, w12 ; CHECK-NEXT: udiv w6, w5, w4
; CHECK-NEXT: mov v2.h[4], w14 ; CHECK-NEXT: mov v2.h[4], w14
; CHECK-NEXT: msub w9, w9, w12, w13 ; CHECK-NEXT: msub w9, w6, w4, w5
; CHECK-NEXT: udiv w8, w11, w10 ; CHECK-NEXT: udiv w12, w19, w7
; CHECK-NEXT: mov v2.h[5], w9 ; CHECK-NEXT: mov v2.h[5], w9
; CHECK-NEXT: msub w12, w12, w7, w19
; CHECK-NEXT: udiv w8, w11, w10
; CHECK-NEXT: mov v2.h[6], w12
; CHECK-NEXT: msub w8, w8, w10, w11 ; CHECK-NEXT: msub w8, w8, w10, w11
; CHECK-NEXT: udiv w12, w16, w15
; CHECK-NEXT: mov v2.h[6], w8
; CHECK-NEXT: msub w8, w12, w15, w16
; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: mov v2.h[7], w8
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ldr x19, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = urem <8 x i16> %A, %B; %tmp3 = urem <8 x i16> %A, %B;
ret <8 x i16> %tmp3 ret <8 x i16> %tmp3
} }
define <1 x i32> @urem1x32(<1 x i32> %A, <1 x i32> %B) { define <1 x i32> @urem1x32(<1 x i32> %A, <1 x i32> %B) {
; CHECK-LABEL: urem1x32: ; CHECK-LABEL: urem1x32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
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; CHECK-NEXT: mov w17, v1.s[3] ; CHECK-NEXT: mov w17, v1.s[3]
; CHECK-NEXT: mov w18, v0.s[3] ; CHECK-NEXT: mov w18, v0.s[3]
; CHECK-NEXT: msub w11, w13, w11, w12 ; CHECK-NEXT: msub w11, w13, w11, w12
; CHECK-NEXT: udiv w10, w9, w8 ; CHECK-NEXT: udiv w10, w9, w8
; CHECK-NEXT: fmov s0, w11 ; CHECK-NEXT: fmov s0, w11
; CHECK-NEXT: msub w8, w10, w8, w9 ; CHECK-NEXT: msub w8, w10, w8, w9
; CHECK-NEXT: udiv w16, w15, w14 ; CHECK-NEXT: udiv w16, w15, w14
; CHECK-NEXT: mov v0.s[1], w8 ; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: msub w10, w16, w14, w15 ; CHECK-NEXT: msub w9, w16, w14, w15
; CHECK-NEXT: udiv w9, w18, w17 ; CHECK-NEXT: udiv w12, w18, w17
; CHECK-NEXT: mov v0.s[2], w10 ; CHECK-NEXT: mov v0.s[2], w9
; CHECK-NEXT: msub w8, w9, w17, w18 ; CHECK-NEXT: msub w8, w12, w17, w18
; CHECK-NEXT: mov v0.s[3], w8 ; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = urem <4 x i32> %A, %B; %tmp3 = urem <4 x i32> %A, %B;
ret <4 x i32> %tmp3 ret <4 x i32> %tmp3
} }
define <1 x i64> @urem1x64(<1 x i64> %A, <1 x i64> %B) { define <1 x i64> @urem1x64(<1 x i64> %A, <1 x i64> %B) {
; CHECK-LABEL: urem1x64: ; CHECK-LABEL: urem1x64:
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llvm/test/CodeGen/AArch64/arm64-nvcast.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm64-apple-ios -aarch64-enable-collect-loh=false | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios -aarch64-enable-collect-loh=false | FileCheck %s
define void @test(float * %p1, i32 %v1) { define void @test(float * %p1, i32 %v1) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1 ; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: and x8, x1, #0x3 ; CHECK-NEXT: and x8, x1, #0x3
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: fmov.2d v0, #2.00000000 ; CHECK-NEXT: fmov.2d v0, #2.00000000
; CHECK-NEXT: bfi x9, x8, #2, #2
; CHECK-NEXT: str q0, [sp] ; CHECK-NEXT: str q0, [sp]
; CHECK-NEXT: bfi x9, x8, #2, #2
; CHECK-NEXT: ldr s0, [x9] ; CHECK-NEXT: ldr s0, [x9]
; CHECK-NEXT: str s0, [x0] ; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%v2 = extractelement <3 x float> <float 0.000000e+00, float 2.000000e+00, float 0.000000e+00>, i32 %v1 %v2 = extractelement <3 x float> <float 0.000000e+00, float 2.000000e+00, float 0.000000e+00>, i32 %v1
store float %v2, float* %p1, align 4 store float %v2, float* %p1, align 4
ret void ret void
} }
define void @test2(float * %p1, i32 %v1) { define void @test2(float * %p1, i32 %v1) {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1 ; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: and x8, x1, #0x3 ; CHECK-NEXT: and x8, x1, #0x3
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: movi.16b v0, #63 ; CHECK-NEXT: movi.16b v0, #63
; CHECK-NEXT: bfi x9, x8, #2, #2
; CHECK-NEXT: str q0, [sp] ; CHECK-NEXT: str q0, [sp]
; CHECK-NEXT: bfi x9, x8, #2, #2
; CHECK-NEXT: ldr s0, [x9] ; CHECK-NEXT: ldr s0, [x9]
; CHECK-NEXT: str s0, [x0] ; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%v2 = extractelement <3 x float> <float 0.7470588088035583, float 0.7470588088035583, float 0.7470588088035583>, i32 %v1 %v2 = extractelement <3 x float> <float 0.7470588088035583, float 0.7470588088035583, float 0.7470588088035583>, i32 %v1
store float %v2, float* %p1, align 4 store float %v2, float* %p1, align 4
ret void ret void
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llvm/test/CodeGen/AArch64/arm64-promote-const-complex-initializers.ll

Show All 11 Lines
; CHECK-NEXT: lCPI0_0: ; CHECK-NEXT: lCPI0_0:
; CHECK-NEXT: .quad 0 ; 0x0 ; CHECK-NEXT: .quad 0 ; 0x0
; CHECK-NEXT: .quad 4575657221408423936 ; 0x3f80000000000000 ; CHECK-NEXT: .quad 4575657221408423936 ; 0x3f80000000000000
; CHECK-NEXT: .section __TEXT,__text,regular,pure_instructions ; CHECK-NEXT: .section __TEXT,__text,regular,pure_instructions
; CHECK-NEXT: .globl _test1 ; CHECK-NEXT: .globl _test1
; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .p2align 2
; CHECK-NEXT: _test1: ; @test1 ; CHECK-NEXT: _test1: ; @test1
; CHECK-NEXT: .cfi_startproc ; CHECK-NEXT: .cfi_startproc
; CHECK-NEXT: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh0: ; CHECK-NEXT: Lloh0:
; CHECK-NEXT: adrp x8, lCPI0_0@PAGE ; CHECK-NEXT: adrp x8, lCPI0_0@PAGE
; CHECK-NEXT: Lloh1: ; CHECK-NEXT: Lloh1:
; CHECK-NEXT: ldr q0, [x8, lCPI0_0@PAGEOFF] ; CHECK-NEXT: ldr q0, [x8, lCPI0_0@PAGEOFF]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1
ret [1 x <4 x float>] [<4 x float> bitcast (<1 x i128> <i128 84405977732342157929391748327801880576> to <4 x float>)] ret [1 x <4 x float>] [<4 x float> bitcast (<1 x i128> <i128 84405977732342157929391748327801880576> to <4 x float>)]
} }
define [1 x <4 x float>] @test2() { define [1 x <4 x float>] @test2() {
; CHECK-LABEL: .p2align 4 ; -- Begin function test2 ; CHECK-LABEL: .p2align 4 ; -- Begin function test2
; CHECK-NEXT: lCPI1_0: ; CHECK-NEXT: lCPI1_0:
; CHECK-NEXT: .long 0x00000000 ; float 0 ; CHECK-NEXT: .long 0x00000000 ; float 0
; CHECK-NEXT: .long 0x00000000 ; float 0 ; CHECK-NEXT: .long 0x00000000 ; float 0
; CHECK-NEXT: .long 0x00000000 ; float 0 ; CHECK-NEXT: .long 0x00000000 ; float 0
; CHECK-NEXT: .long 0x3f800000 ; float 1 ; CHECK-NEXT: .long 0x3f800000 ; float 1
; CHECK-NEXT: .section __TEXT,__text,regular,pure_instructions ; CHECK-NEXT: .section __TEXT,__text,regular,pure_instructions
; CHECK-NEXT: .globl _test2 ; CHECK-NEXT: .globl _test2
; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .p2align 2
; CHECK-NEXT: _test2: ; @test2 ; CHECK-NEXT: _test2: ; @test2
; CHECK-NEXT: .cfi_startproc ; CHECK-NEXT: .cfi_startproc
; CHECK-NEXT: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh2: ; CHECK-NEXT: Lloh2:
; CHECK-NEXT: adrp x8, lCPI1_0@PAGE ; CHECK-NEXT: adrp x8, lCPI1_0@PAGE
; CHECK-NEXT: Lloh3: ; CHECK-NEXT: Lloh3:
; CHECK-NEXT: ldr q1, [x8, lCPI1_0@PAGEOFF] ; CHECK-NEXT: ldr q1, [x8, lCPI1_0@PAGEOFF]
; CHECK-NEXT: mov s2, v1[1] ; CHECK-NEXT: mov s0, v1[1]
; CHECK-NEXT: mov s2, v1[2]
; CHECK-NEXT: fneg s3, s0
; CHECK-NEXT: fneg s0, s1 ; CHECK-NEXT: fneg s0, s1
; CHECK-NEXT: mov s3, v1[2]
; CHECK-NEXT: mov s1, v1[3] ; CHECK-NEXT: mov s1, v1[3]
; CHECK-NEXT: fneg s2, s2 ; CHECK-NEXT: fneg s2, s2
; CHECK-NEXT: mov.s v0[1], v3[0]
; CHECK-NEXT: fneg s1, s1 ; CHECK-NEXT: fneg s1, s1
; CHECK-NEXT: mov.s v0[1], v2[0]
; CHECK-NEXT: fneg s2, s3
; CHECK-NEXT: mov.s v0[2], v2[0] ; CHECK-NEXT: mov.s v0[2], v2[0]
; CHECK-NEXT: mov.s v0[3], v1[0] ; CHECK-NEXT: mov.s v0[3], v1[0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh2, Lloh3
; ;
ret [1 x <4 x float>] [<4 x float> ret [1 x <4 x float>] [<4 x float>
<float fneg (float extractelement (<4 x float> bitcast (<1 x i128> <i128 84405977732342157929391748327801880576> to <4 x float>), i32 0)), <float fneg (float extractelement (<4 x float> bitcast (<1 x i128> <i128 84405977732342157929391748327801880576> to <4 x float>), i32 0)),
float fneg (float extractelement (<4 x float> bitcast (<1 x i128> <i128 84405977732342157929391748327801880576> to <4 x float>), i32 1)), float fneg (float extractelement (<4 x float> bitcast (<1 x i128> <i128 84405977732342157929391748327801880576> to <4 x float>), i32 1)),
float fneg (float extractelement (<4 x float> bitcast (<1 x i128> <i128 84405977732342157929391748327801880576> to <4 x float>), i32 2)), float fneg (float extractelement (<4 x float> bitcast (<1 x i128> <i128 84405977732342157929391748327801880576> to <4 x float>), i32 2)),
float fneg (float extractelement (<4 x float> bitcast (<1 x i128> <i128 84405977732342157929391748327801880576> to <4 x float>), i32 3))>] float fneg (float extractelement (<4 x float> bitcast (<1 x i128> <i128 84405977732342157929391748327801880576> to <4 x float>), i32 3))>]
} }

llvm/test/CodeGen/AArch64/arm64-setcc-int-to-fp-combine.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
define <4 x float> @foo(<4 x float> %val, <4 x float> %test) nounwind { define <4 x float> @foo(<4 x float> %val, <4 x float> %test) nounwind {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: fmov.4s v2, #1.00000000
; CHECK-NEXT: fcmeq.4s v0, v0, v1 ; CHECK-NEXT: fcmeq.4s v0, v0, v1
; CHECK-NEXT: and.16b v0, v0, v2 ; CHECK-NEXT: fmov.4s v1, #1.00000000
; CHECK-NEXT: and.16b v0, v0, v1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%cmp = fcmp oeq <4 x float> %val, %test %cmp = fcmp oeq <4 x float> %val, %test
%ext = zext <4 x i1> %cmp to <4 x i32> %ext = zext <4 x i1> %cmp to <4 x i32>
%result = sitofp <4 x i32> %ext to <4 x float> %result = sitofp <4 x i32> %ext to <4 x float>
ret <4 x float> %result ret <4 x float> %result
} }
; Make sure the operation doesn't try to get folded when the sizes don't match, ; Make sure the operation doesn't try to get folded when the sizes don't match,
; as that ends up crashing later when trying to form a bitcast operation for ; as that ends up crashing later when trying to form a bitcast operation for
; the folded nodes. ; the folded nodes.
define void @foo1(<4 x float> %val, <4 x float> %test, <4 x double>* %p) nounwind { define void @foo1(<4 x float> %val, <4 x float> %test, <4 x double>* %p) nounwind {
; CHECK-LABEL: foo1: ; CHECK-LABEL: foo1:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: movi.4s v2, #1
; CHECK-NEXT: fcmeq.4s v0, v0, v1 ; CHECK-NEXT: fcmeq.4s v0, v0, v1
; CHECK-NEXT: movi.4s v2, #1
; CHECK-NEXT: and.16b v0, v0, v2 ; CHECK-NEXT: and.16b v0, v0, v2
; CHECK-NEXT: ushll2.2d v1, v0, #0 ; CHECK-NEXT: ushll2.2d v1, v0, #0
; CHECK-NEXT: ushll.2d v0, v0, #0 ; CHECK-NEXT: ushll.2d v0, v0, #0
; CHECK-NEXT: scvtf.2d v1, v1 ; CHECK-NEXT: scvtf.2d v1, v1
; CHECK-NEXT: scvtf.2d v0, v0 ; CHECK-NEXT: scvtf.2d v0, v0
; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%cmp = fcmp oeq <4 x float> %val, %test %cmp = fcmp oeq <4 x float> %val, %test
%ext = zext <4 x i1> %cmp to <4 x i32> %ext = zext <4 x i1> %cmp to <4 x i32>
%result = sitofp <4 x i32> %ext to <4 x double> %result = sitofp <4 x i32> %ext to <4 x double>
store <4 x double> %result, <4 x double>* %p store <4 x double> %result, <4 x double>* %p
ret void ret void
} }
; Fold explicit AND operations when the constant isn't a splat of a single ; Fold explicit AND operations when the constant isn't a splat of a single
; scalar value like what the zext creates. ; scalar value like what the zext creates.
define <4 x float> @foo2(<4 x float> %val, <4 x float> %test) nounwind { define <4 x float> @foo2(<4 x float> %val, <4 x float> %test) nounwind {
; CHECK-LABEL: foo2: ; CHECK-LABEL: foo2:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh0: ; CHECK-NEXT: Lloh0:
; CHECK-NEXT: adrp x8, lCPI2_0@PAGE ; CHECK-NEXT: adrp x8, lCPI2_0@PAGE
; CHECK-NEXT: fcmeq.4s v0, v0, v1 ; CHECK-NEXT: fcmeq.4s v0, v0, v1
; CHECK-NEXT: Lloh1: ; CHECK-NEXT: Lloh1:
; CHECK-NEXT: ldr q1, [x8, lCPI2_0@PAGEOFF] ; CHECK-NEXT: ldr q2, [x8, lCPI2_0@PAGEOFF]
; CHECK-NEXT: and.16b v0, v0, v1 ; CHECK-NEXT: and.16b v0, v0, v2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1 ; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1
%cmp = fcmp oeq <4 x float> %val, %test %cmp = fcmp oeq <4 x float> %val, %test
%ext = zext <4 x i1> %cmp to <4 x i32> %ext = zext <4 x i1> %cmp to <4 x i32>
%and = and <4 x i32> %ext, <i32 255, i32 256, i32 257, i32 258> %and = and <4 x i32> %ext, <i32 255, i32 256, i32 257, i32 258>
%result = sitofp <4 x i32> %and to <4 x float> %result = sitofp <4 x i32> %and to <4 x float>
ret <4 x float> %result ret <4 x float> %result
} }

llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll

Show First 20 Lines • Show All 219 Lines • ▼ Show 20 Lines
; Extends of vectors of i1. ; Extends of vectors of i1.
define <32 x i8> @zext_v32i1(<32 x i1> %arg) { define <32 x i8> @zext_v32i1(<32 x i1> %arg) {
; CHECK-LABEL: zext_v32i1: ; CHECK-LABEL: zext_v32i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [sp, #64] ; CHECK-NEXT: ldr w8, [sp, #64]
; CHECK-NEXT: fmov s0, w0 ; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: ldr w9, [sp] ; CHECK-NEXT: ldr w9, [sp, #72]
; CHECK-NEXT: ldr w10, [sp, #8] ; CHECK-NEXT: ldr w10, [sp]
; CHECK-NEXT: fmov s1, w8 ; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: ldr w8, [sp, #72] ; CHECK-NEXT: ldr w8, [sp, #80]
; CHECK-NEXT: mov.b v0[1], w1 ; CHECK-NEXT: mov.b v0[1], w1
; CHECK-NEXT: ldr w11, [sp, #8]
; CHECK-NEXT: movi.16b v2, #1 ; CHECK-NEXT: movi.16b v2, #1
; CHECK-NEXT: mov.b v1[1], w8 ; CHECK-NEXT: mov.b v1[1], w9
; CHECK-NEXT: ldr w8, [sp, #80] ; CHECK-NEXT: ldr w9, [sp, #88]
; CHECK-NEXT: mov.b v0[2], w2 ; CHECK-NEXT: mov.b v0[2], w2
; CHECK-NEXT: mov.b v1[2], w8 ; CHECK-NEXT: mov.b v1[2], w8
; CHECK-NEXT: ldr w8, [sp, #88]
; CHECK-NEXT: mov.b v0[3], w3
; CHECK-NEXT: mov.b v1[3], w8
; CHECK-NEXT: ldr w8, [sp, #96] ; CHECK-NEXT: ldr w8, [sp, #96]
; CHECK-NEXT: mov.b v0[3], w3
; CHECK-NEXT: mov.b v1[3], w9
; CHECK-NEXT: ldr w9, [sp, #104]
; CHECK-NEXT: mov.b v0[4], w4 ; CHECK-NEXT: mov.b v0[4], w4
; CHECK-NEXT: mov.b v1[4], w8 ; CHECK-NEXT: mov.b v1[4], w8
; CHECK-NEXT: ldr w8, [sp, #104]
; CHECK-NEXT: mov.b v0[5], w5
; CHECK-NEXT: mov.b v1[5], w8
; CHECK-NEXT: ldr w8, [sp, #112] ; CHECK-NEXT: ldr w8, [sp, #112]
; CHECK-NEXT: mov.b v0[5], w5
; CHECK-NEXT: mov.b v1[5], w9
; CHECK-NEXT: ldr w9, [sp, #120]
; CHECK-NEXT: mov.b v0[6], w6 ; CHECK-NEXT: mov.b v0[6], w6
; CHECK-NEXT: mov.b v1[6], w8 ; CHECK-NEXT: mov.b v1[6], w8
; CHECK-NEXT: ldr w8, [sp, #120]
; CHECK-NEXT: mov.b v0[7], w7
; CHECK-NEXT: mov.b v1[7], w8
; CHECK-NEXT: ldr w8, [sp, #128] ; CHECK-NEXT: ldr w8, [sp, #128]
; CHECK-NEXT: mov.b v0[8], w9 ; CHECK-NEXT: mov.b v0[7], w7
; CHECK-NEXT: ldr w9, [sp, #16] ; CHECK-NEXT: mov.b v1[7], w9
; CHECK-NEXT: ldr w9, [sp, #136]
; CHECK-NEXT: mov.b v0[8], w10
; CHECK-NEXT: ldr w10, [sp, #16]
; CHECK-NEXT: mov.b v1[8], w8 ; CHECK-NEXT: mov.b v1[8], w8
; CHECK-NEXT: ldr w8, [sp, #136]
; CHECK-NEXT: mov.b v0[9], w10
; CHECK-NEXT: ldr w10, [sp, #24]
; CHECK-NEXT: mov.b v1[9], w8
; CHECK-NEXT: ldr w8, [sp, #144] ; CHECK-NEXT: ldr w8, [sp, #144]
; CHECK-NEXT: mov.b v0[10], w9 ; CHECK-NEXT: mov.b v0[9], w11
; CHECK-NEXT: ldr w9, [sp, #32] ; CHECK-NEXT: ldr w11, [sp, #24]
; CHECK-NEXT: mov.b v1[9], w9
; CHECK-NEXT: ldr w9, [sp, #152]
; CHECK-NEXT: mov.b v0[10], w10
; CHECK-NEXT: ldr w10, [sp, #32]
; CHECK-NEXT: mov.b v1[10], w8 ; CHECK-NEXT: mov.b v1[10], w8
; CHECK-NEXT: ldr w8, [sp, #152]
; CHECK-NEXT: mov.b v0[11], w10
; CHECK-NEXT: ldr w10, [sp, #40]
; CHECK-NEXT: mov.b v1[11], w8
; CHECK-NEXT: ldr w8, [sp, #160] ; CHECK-NEXT: ldr w8, [sp, #160]
; CHECK-NEXT: mov.b v0[12], w9 ; CHECK-NEXT: mov.b v0[11], w11
; CHECK-NEXT: ldr w9, [sp, #48] ; CHECK-NEXT: ldr w11, [sp, #40]
; CHECK-NEXT: mov.b v1[11], w9
; CHECK-NEXT: ldr w9, [sp, #168]
; CHECK-NEXT: mov.b v0[12], w10
; CHECK-NEXT: ldr w10, [sp, #48]
; CHECK-NEXT: mov.b v1[12], w8 ; CHECK-NEXT: mov.b v1[12], w8
; CHECK-NEXT: ldr w8, [sp, #168]
; CHECK-NEXT: mov.b v0[13], w10
; CHECK-NEXT: ldr w10, [sp, #56]
; CHECK-NEXT: mov.b v1[13], w8
; CHECK-NEXT: ldr w8, [sp, #176] ; CHECK-NEXT: ldr w8, [sp, #176]
; CHECK-NEXT: mov.b v0[14], w9 ; CHECK-NEXT: mov.b v0[13], w11
; CHECK-NEXT: ldr w11, [sp, #56]
; CHECK-NEXT: mov.b v1[13], w9
; CHECK-NEXT: ldr w9, [sp, #184]
; CHECK-NEXT: mov.b v0[14], w10
; CHECK-NEXT: mov.b v1[14], w8 ; CHECK-NEXT: mov.b v1[14], w8
; CHECK-NEXT: ldr w8, [sp, #184] ; CHECK-NEXT: mov.b v0[15], w11
; CHECK-NEXT: mov.b v0[15], w10 ; CHECK-NEXT: mov.b v1[15], w9
; CHECK-NEXT: mov.b v1[15], w8
; CHECK-NEXT: and.16b v0, v0, v2 ; CHECK-NEXT: and.16b v0, v0, v2
; CHECK-NEXT: and.16b v1, v1, v2 ; CHECK-NEXT: and.16b v1, v1, v2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = zext <32 x i1> %arg to <32 x i8> %res = zext <32 x i1> %arg to <32 x i8>
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @sext_v32i1(<32 x i1> %arg) { define <32 x i8> @sext_v32i1(<32 x i1> %arg) {
; CHECK-LABEL: sext_v32i1: ; CHECK-LABEL: sext_v32i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [sp, #64] ; CHECK-NEXT: ldr w8, [sp, #64]
; CHECK-NEXT: fmov s0, w0 ; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: ldr w9, [sp] ; CHECK-NEXT: ldr w9, [sp, #80]
; CHECK-NEXT: ldr w10, [sp, #8] ; CHECK-NEXT: ldr w10, [sp]
; CHECK-NEXT: fmov s1, w8 ; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: ldr w8, [sp, #72] ; CHECK-NEXT: ldr w8, [sp, #72]
; CHECK-NEXT: mov.b v0[1], w1 ; CHECK-NEXT: mov.b v0[1], w1
; CHECK-NEXT: ldr w11, [sp, #8]
; CHECK-NEXT: mov.b v1[1], w8 ; CHECK-NEXT: mov.b v1[1], w8
; CHECK-NEXT: ldr w8, [sp, #80]
; CHECK-NEXT: mov.b v0[2], w2
; CHECK-NEXT: mov.b v1[2], w8
; CHECK-NEXT: ldr w8, [sp, #88] ; CHECK-NEXT: ldr w8, [sp, #88]
; CHECK-NEXT: mov.b v0[2], w2
; CHECK-NEXT: mov.b v1[2], w9
; CHECK-NEXT: ldr w9, [sp, #96]
; CHECK-NEXT: mov.b v0[3], w3 ; CHECK-NEXT: mov.b v0[3], w3
; CHECK-NEXT: mov.b v1[3], w8 ; CHECK-NEXT: mov.b v1[3], w8
; CHECK-NEXT: ldr w8, [sp, #96]
; CHECK-NEXT: mov.b v0[4], w4
; CHECK-NEXT: mov.b v1[4], w8
; CHECK-NEXT: ldr w8, [sp, #104] ; CHECK-NEXT: ldr w8, [sp, #104]
; CHECK-NEXT: mov.b v0[4], w4
; CHECK-NEXT: mov.b v1[4], w9
; CHECK-NEXT: ldr w9, [sp, #112]
; CHECK-NEXT: mov.b v0[5], w5 ; CHECK-NEXT: mov.b v0[5], w5
; CHECK-NEXT: mov.b v1[5], w8 ; CHECK-NEXT: mov.b v1[5], w8
; CHECK-NEXT: ldr w8, [sp, #112]
; CHECK-NEXT: mov.b v0[6], w6
; CHECK-NEXT: mov.b v1[6], w8
; CHECK-NEXT: ldr w8, [sp, #120] ; CHECK-NEXT: ldr w8, [sp, #120]
; CHECK-NEXT: mov.b v0[6], w6
; CHECK-NEXT: mov.b v1[6], w9
; CHECK-NEXT: ldr w9, [sp, #128]
; CHECK-NEXT: mov.b v0[7], w7 ; CHECK-NEXT: mov.b v0[7], w7
; CHECK-NEXT: mov.b v1[7], w8 ; CHECK-NEXT: mov.b v1[7], w8
; CHECK-NEXT: ldr w8, [sp, #128]
; CHECK-NEXT: mov.b v0[8], w9
; CHECK-NEXT: ldr w9, [sp, #16]
; CHECK-NEXT: mov.b v1[8], w8
; CHECK-NEXT: ldr w8, [sp, #136] ; CHECK-NEXT: ldr w8, [sp, #136]
; CHECK-NEXT: mov.b v0[9], w10 ; CHECK-NEXT: mov.b v0[8], w10
; CHECK-NEXT: ldr w10, [sp, #24] ; CHECK-NEXT: ldr w10, [sp, #16]
; CHECK-NEXT: mov.b v1[8], w9
; CHECK-NEXT: ldr w9, [sp, #144]
; CHECK-NEXT: mov.b v0[9], w11
; CHECK-NEXT: ldr w11, [sp, #24]
; CHECK-NEXT: mov.b v1[9], w8 ; CHECK-NEXT: mov.b v1[9], w8
; CHECK-NEXT: ldr w8, [sp, #144]
; CHECK-NEXT: mov.b v0[10], w9
; CHECK-NEXT: ldr w9, [sp, #32]
; CHECK-NEXT: mov.b v1[10], w8
; CHECK-NEXT: ldr w8, [sp, #152] ; CHECK-NEXT: ldr w8, [sp, #152]
; CHECK-NEXT: mov.b v0[11], w10 ; CHECK-NEXT: mov.b v0[10], w10
; CHECK-NEXT: ldr w10, [sp, #40] ; CHECK-NEXT: ldr w10, [sp, #32]
; CHECK-NEXT: mov.b v1[10], w9
; CHECK-NEXT: ldr w9, [sp, #160]
; CHECK-NEXT: mov.b v0[11], w11
; CHECK-NEXT: ldr w11, [sp, #40]
; CHECK-NEXT: mov.b v1[11], w8 ; CHECK-NEXT: mov.b v1[11], w8
; CHECK-NEXT: ldr w8, [sp, #160]
; CHECK-NEXT: mov.b v0[12], w9
; CHECK-NEXT: ldr w9, [sp, #48]
; CHECK-NEXT: mov.b v1[12], w8
; CHECK-NEXT: ldr w8, [sp, #168] ; CHECK-NEXT: ldr w8, [sp, #168]
; CHECK-NEXT: mov.b v0[13], w10 ; CHECK-NEXT: mov.b v0[12], w10
; CHECK-NEXT: ldr w10, [sp, #56] ; CHECK-NEXT: ldr w10, [sp, #48]
; CHECK-NEXT: mov.b v1[12], w9
; CHECK-NEXT: ldr w9, [sp, #176]
; CHECK-NEXT: mov.b v0[13], w11
; CHECK-NEXT: ldr w11, [sp, #56]
; CHECK-NEXT: mov.b v1[13], w8 ; CHECK-NEXT: mov.b v1[13], w8
; CHECK-NEXT: ldr w8, [sp, #176]
; CHECK-NEXT: mov.b v0[14], w9
; CHECK-NEXT: mov.b v1[14], w8
; CHECK-NEXT: ldr w8, [sp, #184] ; CHECK-NEXT: ldr w8, [sp, #184]
; CHECK-NEXT: mov.b v0[15], w10 ; CHECK-NEXT: mov.b v0[14], w10
; CHECK-NEXT: mov.b v1[14], w9
; CHECK-NEXT: mov.b v0[15], w11
; CHECK-NEXT: mov.b v1[15], w8 ; CHECK-NEXT: mov.b v1[15], w8
; CHECK-NEXT: shl.16b v0, v0, #7 ; CHECK-NEXT: shl.16b v0, v0, #7
; CHECK-NEXT: shl.16b v1, v1, #7 ; CHECK-NEXT: shl.16b v1, v1, #7
; CHECK-NEXT: cmlt.16b v0, v0, #0 ; CHECK-NEXT: cmlt.16b v0, v0, #0
; CHECK-NEXT: cmlt.16b v1, v1, #0 ; CHECK-NEXT: cmlt.16b v1, v1, #0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = sext <32 x i1> %arg to <32 x i8> %res = sext <32 x i1> %arg to <32 x i8>
ret <32 x i8> %res ret <32 x i8> %res
} }
define <64 x i8> @zext_v64i1(<64 x i1> %arg) { define <64 x i8> @zext_v64i1(<64 x i1> %arg) {
; CHECK-LABEL: zext_v64i1: ; CHECK-LABEL: zext_v64i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [sp, #320] ; CHECK-NEXT: ldr w8, [sp, #320]
; CHECK-NEXT: fmov s0, w0 ; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: ldr w9, [sp, #64] ; CHECK-NEXT: ldr w9, [sp, #192]
; CHECK-NEXT: ldr w10, [sp, #192] ; CHECK-NEXT: ldr w10, [sp, #336]
; CHECK-NEXT: fmov s3, w8 ; CHECK-NEXT: fmov s3, w8
; CHECK-NEXT: ldr w8, [sp, #328] ; CHECK-NEXT: ldr w8, [sp, #328]
; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: fmov s2, w9
; CHECK-NEXT: ldr w9, [sp, #200] ; CHECK-NEXT: ldr w9, [sp, #200]
; CHECK-NEXT: fmov s2, w10
; CHECK-NEXT: ldr w10, [sp, #336]
; CHECK-NEXT: mov.b v3[1], w8
; CHECK-NEXT: ldr w8, [sp, #72]
; CHECK-NEXT: mov.b v0[1], w1
; CHECK-NEXT: ldr w11, [sp, #352] ; CHECK-NEXT: ldr w11, [sp, #352]
; CHECK-NEXT: mov.b v2[1], w9 ; CHECK-NEXT: mov.b v0[1], w1
; CHECK-NEXT: ldr w9, [sp, #80] ; CHECK-NEXT: mov.b v3[1], w8
; CHECK-NEXT: mov.b v1[1], w8
; CHECK-NEXT: ldr w8, [sp, #344] ; CHECK-NEXT: ldr w8, [sp, #344]
; CHECK-NEXT: mov.b v2[1], w9
; CHECK-NEXT: ldr w9, [sp, #368]
; CHECK-NEXT: mov.b v3[2], w10 ; CHECK-NEXT: mov.b v3[2], w10
; CHECK-NEXT: ldr w10, [sp, #208] ; CHECK-NEXT: ldr w10, [sp, #360]
; CHECK-NEXT: mov.b v0[2], w2 ; CHECK-NEXT: mov.b v0[2], w2
; CHECK-NEXT: ldr w12, [sp, #368] ; CHECK-NEXT: ldr w12, [sp, #272]
; CHECK-NEXT: ldr w13, [sp, #384]
; CHECK-NEXT: mov.b v1[2], w9
; CHECK-NEXT: ldr w9, [sp, #360]
; CHECK-NEXT: mov.b v2[2], w10
; CHECK-NEXT: ldr w10, [sp, #88]
; CHECK-NEXT: mov.b v3[3], w8 ; CHECK-NEXT: mov.b v3[3], w8
; CHECK-NEXT: ldr w8, [sp, #216] ; CHECK-NEXT: ldr w8, [sp, #208]
; CHECK-NEXT: mov.b v0[3], w3 ; CHECK-NEXT: mov.b v0[3], w3
; CHECK-NEXT: ldr w14, [sp, #400] ; CHECK-NEXT: ldr w13, [sp, #136]
; CHECK-NEXT: mov.b v1[3], w10
; CHECK-NEXT: ldr w10, [sp, #376]
; CHECK-NEXT: mov.b v2[3], w8
; CHECK-NEXT: ldr w8, [sp, #96]
; CHECK-NEXT: mov.b v3[4], w11 ; CHECK-NEXT: mov.b v3[4], w11
; CHECK-NEXT: ldr w11, [sp, #224] ; CHECK-NEXT: ldr w11, [sp, #216]
; CHECK-NEXT: mov.b v0[4], w4 ; CHECK-NEXT: mov.b v2[2], w8
; CHECK-NEXT: ldr w15, [sp, #416] ; CHECK-NEXT: ldr w8, [sp, #376]
; CHECK-NEXT: mov.b v1[4], w8 ; CHECK-NEXT: mov.b v3[5], w10
; CHECK-NEXT: ldr w8, [sp, #392] ; CHECK-NEXT: ldr w10, [sp, #224]
; CHECK-NEXT: mov.b v2[4], w11 ; CHECK-NEXT: mov.b v2[3], w11
; CHECK-NEXT: ldr w11, [sp, #104] ; CHECK-NEXT: ldr w11, [sp, #384]
; CHECK-NEXT: mov.b v3[5], w9 ; CHECK-NEXT: mov.b v3[6], w9
; CHECK-NEXT: ldr w9, [sp, #232] ; CHECK-NEXT: ldr w9, [sp, #232]
; CHECK-NEXT: mov.b v0[5], w5 ; CHECK-NEXT: mov.b v2[4], w10
; CHECK-NEXT: ldr w16, [sp, #432] ; CHECK-NEXT: ldr w10, [sp, #392]
; CHECK-NEXT: mov.b v1[5], w11 ; CHECK-NEXT: mov.b v3[7], w8
; CHECK-NEXT: ldr w11, [sp, #408] ; CHECK-NEXT: ldr w8, [sp, #240]
; CHECK-NEXT: mov.b v2[5], w9 ; CHECK-NEXT: mov.b v2[5], w9
; CHECK-NEXT: ldr w9, [sp, #112] ; CHECK-NEXT: ldr w9, [sp, #400]
; CHECK-NEXT: mov.b v3[6], w12 ; CHECK-NEXT: mov.b v3[8], w11
; CHECK-NEXT: ldr w12, [sp, #240] ; CHECK-NEXT: ldr w11, [sp, #248]
; CHECK-NEXT: mov.b v2[6], w8
; CHECK-NEXT: ldr w8, [sp, #408]
; CHECK-NEXT: mov.b v3[9], w10
; CHECK-NEXT: ldr w10, [sp, #256]
; CHECK-NEXT: mov.b v2[7], w11
; CHECK-NEXT: ldr w11, [sp, #416]
; CHECK-NEXT: mov.b v3[10], w9
; CHECK-NEXT: ldr w9, [sp, #264]
; CHECK-NEXT: mov.b v2[8], w10
; CHECK-NEXT: ldr w10, [sp, #424]
; CHECK-NEXT: mov.b v3[11], w8
; CHECK-NEXT: ldr w8, [sp, #432]
; CHECK-NEXT: mov.b v2[9], w9
; CHECK-NEXT: ldr w9, [sp, #64]
; CHECK-NEXT: mov.b v3[12], w11
; CHECK-NEXT: mov.b v0[4], w4
; CHECK-NEXT: ldr w11, [sp, #280]
; CHECK-NEXT: mov.b v2[10], w12
; CHECK-NEXT: mov.b v3[13], w10
; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: ldr w9, [sp, #72]
; CHECK-NEXT: mov.b v0[5], w5
; CHECK-NEXT: mov.b v3[14], w8
; CHECK-NEXT: ldr w8, [sp, #80]
; CHECK-NEXT: mov.b v0[6], w6 ; CHECK-NEXT: mov.b v0[6], w6
; CHECK-NEXT: mov.b v1[6], w9 ; CHECK-NEXT: ldr w14, [sp, #144]
; CHECK-NEXT: ldr w9, [sp, #424] ; CHECK-NEXT: mov.b v1[1], w9
; CHECK-NEXT: mov.b v2[6], w12 ; CHECK-NEXT: ldr w9, [sp, #88]
; CHECK-NEXT: ldr w12, [sp, #120]
; CHECK-NEXT: mov.b v3[7], w10
; CHECK-NEXT: ldr w10, [sp, #248]
; CHECK-NEXT: mov.b v0[7], w7 ; CHECK-NEXT: mov.b v0[7], w7
; CHECK-NEXT: mov.b v1[7], w12 ; CHECK-NEXT: ldr w10, [sp, #288]
; CHECK-NEXT: ldr w12, [sp] ; CHECK-NEXT: mov.b v1[2], w8
; CHECK-NEXT: mov.b v2[7], w10 ; CHECK-NEXT: ldr w8, [sp, #96]
; CHECK-NEXT: ldr w10, [sp, #128] ; CHECK-NEXT: mov.b v2[11], w11
; CHECK-NEXT: mov.b v3[8], w13 ; CHECK-NEXT: ldr w11, [sp, #440]
; CHECK-NEXT: ldr w13, [sp, #256] ; CHECK-NEXT: mov.b v1[3], w9
; CHECK-NEXT: mov.b v0[8], w12 ; CHECK-NEXT: ldr w9, [sp, #104]
; CHECK-NEXT: ldr w12, [sp, #440] ; CHECK-NEXT: mov.b v2[12], w10
; CHECK-NEXT: mov.b v1[8], w10 ; CHECK-NEXT: ldr w10, [sp, #296]
; CHECK-NEXT: ldr w10, [sp, #8] ; CHECK-NEXT: mov.b v1[4], w8
; CHECK-NEXT: mov.b v2[8], w13 ; CHECK-NEXT: ldr w8, [sp, #112]
; CHECK-NEXT: ldr w13, [sp, #136] ; CHECK-NEXT: ldr w12, [sp, #312]
; CHECK-NEXT: mov.b v3[9], w8 ; CHECK-NEXT: mov.b v3[15], w11
; CHECK-NEXT: ldr w8, [sp, #264] ; CHECK-NEXT: mov.b v1[5], w9
; CHECK-NEXT: mov.b v0[9], w10 ; CHECK-NEXT: ldr w9, [sp, #120]
; CHECK-NEXT: ldr w10, [sp, #272] ; CHECK-NEXT: mov.b v2[13], w10
; CHECK-NEXT: ldr w10, [sp, #304]
; CHECK-NEXT: mov.b v1[6], w8
; CHECK-NEXT: ldr w8, [sp, #128]
; CHECK-NEXT: movi.16b v4, #1
; CHECK-NEXT: mov.b v1[7], w9
; CHECK-NEXT: ldr w9, [sp]
; CHECK-NEXT: mov.b v2[14], w10
; CHECK-NEXT: mov.b v1[8], w8
; CHECK-NEXT: ldr w8, [sp, #8]
; CHECK-NEXT: mov.b v0[8], w9
; CHECK-NEXT: ldr w9, [sp, #16]
; CHECK-NEXT: mov.b v1[9], w13 ; CHECK-NEXT: mov.b v1[9], w13
; CHECK-NEXT: ldr w13, [sp, #16] ; CHECK-NEXT: ldr w13, [sp, #152]
; CHECK-NEXT: mov.b v2[9], w8 ; CHECK-NEXT: mov.b v0[9], w8
; CHECK-NEXT: ldr w8, [sp, #144]
; CHECK-NEXT: mov.b v3[10], w14
; CHECK-NEXT: ldr w14, [sp, #280]
; CHECK-NEXT: mov.b v0[10], w13
; CHECK-NEXT: ldr w13, [sp, #296]
; CHECK-NEXT: mov.b v1[10], w8
; CHECK-NEXT: ldr w8, [sp, #24] ; CHECK-NEXT: ldr w8, [sp, #24]
; CHECK-NEXT: mov.b v2[10], w10 ; CHECK-NEXT: mov.b v1[10], w14
; CHECK-NEXT: ldr w10, [sp, #152] ; CHECK-NEXT: ldr w14, [sp, #160]
; CHECK-NEXT: mov.b v3[11], w11 ; CHECK-NEXT: mov.b v0[10], w9
; CHECK-NEXT: ldr w11, [sp, #288] ; CHECK-NEXT: ldr w9, [sp, #32]
; CHECK-NEXT: mov.b v1[11], w13
; CHECK-NEXT: ldr w13, [sp, #168]
; CHECK-NEXT: mov.b v0[11], w8 ; CHECK-NEXT: mov.b v0[11], w8
; CHECK-NEXT: ldr w8, [sp, #32]
; CHECK-NEXT: mov.b v1[11], w10
; CHECK-NEXT: ldr w10, [sp, #160]
; CHECK-NEXT: mov.b v2[11], w14
; CHECK-NEXT: mov.b v3[12], w15
; CHECK-NEXT: mov.b v0[12], w8
; CHECK-NEXT: ldr w8, [sp, #40] ; CHECK-NEXT: ldr w8, [sp, #40]
; CHECK-NEXT: mov.b v1[12], w10 ; CHECK-NEXT: mov.b v1[12], w14
; CHECK-NEXT: ldr w10, [sp, #168] ; CHECK-NEXT: ldr w14, [sp, #176]
; CHECK-NEXT: mov.b v2[12], w11 ; CHECK-NEXT: mov.b v0[12], w9
; CHECK-NEXT: ldr w11, [sp, #312] ; CHECK-NEXT: ldr w9, [sp, #48]
; CHECK-NEXT: mov.b v3[13], w9 ; CHECK-NEXT: mov.b v1[13], w13
; CHECK-NEXT: ldr w9, [sp, #304] ; CHECK-NEXT: ldr w13, [sp, #184]
; CHECK-NEXT: mov.b v0[13], w8 ; CHECK-NEXT: mov.b v0[13], w8
; CHECK-NEXT: ldr w8, [sp, #48]
; CHECK-NEXT: mov.b v1[13], w10
; CHECK-NEXT: ldr w10, [sp, #176]
; CHECK-NEXT: mov.b v2[13], w13
; CHECK-NEXT: mov.b v3[14], w16
; CHECK-NEXT: mov.b v0[14], w8
; CHECK-NEXT: ldr w8, [sp, #56] ; CHECK-NEXT: ldr w8, [sp, #56]
; CHECK-NEXT: mov.b v1[14], w10 ; CHECK-NEXT: mov.b v1[14], w14
; CHECK-NEXT: mov.b v2[14], w9 ; CHECK-NEXT: mov.b v2[15], w12
; CHECK-NEXT: ldr w9, [sp, #184] ; CHECK-NEXT: mov.b v0[14], w9
; CHECK-NEXT: movi.16b v4, #1 ; CHECK-NEXT: mov.b v1[15], w13
; CHECK-NEXT: mov.b v0[15], w8 ; CHECK-NEXT: mov.b v0[15], w8
; CHECK-NEXT: mov.b v1[15], w9
; CHECK-NEXT: mov.b v2[15], w11
; CHECK-NEXT: mov.b v3[15], w12
; CHECK-NEXT: and.16b v0, v0, v4
; CHECK-NEXT: and.16b v1, v1, v4 ; CHECK-NEXT: and.16b v1, v1, v4
; CHECK-NEXT: and.16b v0, v0, v4
; CHECK-NEXT: and.16b v2, v2, v4 ; CHECK-NEXT: and.16b v2, v2, v4
; CHECK-NEXT: and.16b v3, v3, v4 ; CHECK-NEXT: and.16b v3, v3, v4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = zext <64 x i1> %arg to <64 x i8> %res = zext <64 x i1> %arg to <64 x i8>
ret <64 x i8> %res ret <64 x i8> %res
} }
define <64 x i8> @sext_v64i1(<64 x i1> %arg) { define <64 x i8> @sext_v64i1(<64 x i1> %arg) {
; CHECK-LABEL: sext_v64i1: ; CHECK-LABEL: sext_v64i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [sp, #320] ; CHECK-NEXT: ldr w8, [sp, #320]
; CHECK-NEXT: fmov s3, w0 ; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: ldr w9, [sp, #64] ; CHECK-NEXT: ldr w10, [sp, #336]
; CHECK-NEXT: ldr w10, [sp, #192] ; CHECK-NEXT: ldr w9, [sp, #192]
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s2, w8
; CHECK-NEXT: ldr w8, [sp, #328] ; CHECK-NEXT: ldr w8, [sp, #328]
; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: ldr w11, [sp, #352]
; CHECK-NEXT: ldr w9, [sp, #72] ; CHECK-NEXT: mov.b v0[1], w1
; CHECK-NEXT: fmov s2, w10 ; CHECK-NEXT: fmov s3, w9
; CHECK-NEXT: ldr w10, [sp, #80] ; CHECK-NEXT: ldr w9, [sp, #200]
; CHECK-NEXT: mov.b v0[1], w8
; CHECK-NEXT: ldr w8, [sp, #200]
; CHECK-NEXT: mov.b v1[1], w9
; CHECK-NEXT: ldr w9, [sp, #336]
; CHECK-NEXT: mov.b v3[1], w1
; CHECK-NEXT: ldr w11, [sp, #88]
; CHECK-NEXT: mov.b v2[1], w8 ; CHECK-NEXT: mov.b v2[1], w8
; CHECK-NEXT: ldr w8, [sp, #344] ; CHECK-NEXT: ldr w8, [sp, #344]
; CHECK-NEXT: mov.b v0[2], w9 ; CHECK-NEXT: mov.b v0[2], w2
; CHECK-NEXT: ldr w9, [sp, #208] ; CHECK-NEXT: ldr w13, [sp, #128]
; CHECK-NEXT: mov.b v1[2], w10 ; CHECK-NEXT: mov.b v2[2], w10
; CHECK-NEXT: ldr w10, [sp, #352] ; CHECK-NEXT: ldr w10, [sp, #360]
; CHECK-NEXT: mov.b v3[2], w2 ; CHECK-NEXT: mov.b v3[1], w9
; CHECK-NEXT: ldr w12, [sp, #96] ; CHECK-NEXT: ldr w9, [sp, #368]
; CHECK-NEXT: mov.b v2[2], w9
; CHECK-NEXT: ldr w9, [sp, #360]
; CHECK-NEXT: mov.b v0[3], w8
; CHECK-NEXT: ldr w8, [sp, #216]
; CHECK-NEXT: mov.b v1[3], w11
; CHECK-NEXT: ldr w13, [sp, #104]
; CHECK-NEXT: mov.b v3[3], w3
; CHECK-NEXT: ldr w11, [sp, #368]
; CHECK-NEXT: mov.b v2[3], w8 ; CHECK-NEXT: mov.b v2[3], w8
; CHECK-NEXT: ldr w14, [sp, #112] ; CHECK-NEXT: ldr w8, [sp, #208]
; CHECK-NEXT: mov.b v0[4], w10 ; CHECK-NEXT: mov.b v0[3], w3
; CHECK-NEXT: ldr w10, [sp, #224] ; CHECK-NEXT: ldr w12, [sp, #264]
; CHECK-NEXT: mov.b v1[4], w12 ; CHECK-NEXT: mov.b v2[4], w11
; CHECK-NEXT: ldr w11, [sp, #216]
; CHECK-NEXT: mov.b v3[2], w8
; CHECK-NEXT: ldr w8, [sp, #376] ; CHECK-NEXT: ldr w8, [sp, #376]
; CHECK-NEXT: mov.b v3[4], w4 ; CHECK-NEXT: mov.b v2[5], w10
; CHECK-NEXT: ldr w15, [sp, #120] ; CHECK-NEXT: ldr w10, [sp, #224]
; CHECK-NEXT: mov.b v2[4], w10 ; CHECK-NEXT: mov.b v3[3], w11
; CHECK-NEXT: ldr w12, [sp, #384] ; CHECK-NEXT: ldr w11, [sp, #384]
; CHECK-NEXT: mov.b v0[5], w9 ; CHECK-NEXT: mov.b v2[6], w9
; CHECK-NEXT: ldr w9, [sp, #232] ; CHECK-NEXT: ldr w9, [sp, #232]
; CHECK-NEXT: mov.b v1[5], w13 ; CHECK-NEXT: mov.b v3[4], w10
; CHECK-NEXT: ldr w16, [sp, #128]
; CHECK-NEXT: mov.b v3[5], w5
; CHECK-NEXT: ldr w10, [sp, #392] ; CHECK-NEXT: ldr w10, [sp, #392]
; CHECK-NEXT: mov.b v2[5], w9
; CHECK-NEXT: ldr w13, [sp, #400]
; CHECK-NEXT: mov.b v0[6], w11
; CHECK-NEXT: ldr w11, [sp, #240]
; CHECK-NEXT: mov.b v1[6], w14
; CHECK-NEXT: ldr w9, [sp, #408]
; CHECK-NEXT: mov.b v3[6], w6
; CHECK-NEXT: ldr w14, [sp, #416]
; CHECK-NEXT: mov.b v2[6], w11
; CHECK-NEXT: ldr w11, [sp, #424]
; CHECK-NEXT: mov.b v0[7], w8
; CHECK-NEXT: ldr w8, [sp, #248]
; CHECK-NEXT: mov.b v1[7], w15
; CHECK-NEXT: ldr w15, [sp, #432]
; CHECK-NEXT: mov.b v3[7], w7
; CHECK-NEXT: mov.b v2[7], w8 ; CHECK-NEXT: mov.b v2[7], w8
; CHECK-NEXT: ldr w8, [sp] ; CHECK-NEXT: ldr w8, [sp, #240]
; CHECK-NEXT: mov.b v0[8], w12 ; CHECK-NEXT: mov.b v3[5], w9
; CHECK-NEXT: ldr w12, [sp, #256] ; CHECK-NEXT: ldr w9, [sp, #400]
; CHECK-NEXT: mov.b v1[8], w16 ; CHECK-NEXT: mov.b v2[8], w11
; CHECK-NEXT: ldr w16, [sp, #440] ; CHECK-NEXT: ldr w11, [sp, #248]
; CHECK-NEXT: mov.b v3[8], w8 ; CHECK-NEXT: mov.b v3[6], w8
; CHECK-NEXT: ldr w8, [sp, #136] ; CHECK-NEXT: ldr w8, [sp, #408]
; CHECK-NEXT: mov.b v2[8], w12
; CHECK-NEXT: ldr w12, [sp, #8]
; CHECK-NEXT: mov.b v0[9], w10
; CHECK-NEXT: ldr w10, [sp, #264]
; CHECK-NEXT: mov.b v1[9], w8
; CHECK-NEXT: ldr w8, [sp, #272]
; CHECK-NEXT: mov.b v3[9], w12
; CHECK-NEXT: ldr w12, [sp, #144]
; CHECK-NEXT: mov.b v2[9], w10 ; CHECK-NEXT: mov.b v2[9], w10
; CHECK-NEXT: ldr w10, [sp, #16] ; CHECK-NEXT: mov.b v0[4], w4
; CHECK-NEXT: mov.b v0[10], w13 ; CHECK-NEXT: mov.b v3[7], w11
; CHECK-NEXT: ldr w13, [sp, #280] ; CHECK-NEXT: ldr w11, [sp, #416]
; CHECK-NEXT: mov.b v1[10], w12 ; CHECK-NEXT: mov.b v2[10], w9
; CHECK-NEXT: ldr w12, [sp, #152] ; CHECK-NEXT: ldr w9, [sp, #424]
; CHECK-NEXT: mov.b v0[5], w5
; CHECK-NEXT: ldr w10, [sp, #256]
; CHECK-NEXT: mov.b v2[11], w8
; CHECK-NEXT: ldr w8, [sp, #432]
; CHECK-NEXT: mov.b v0[6], w6
; CHECK-NEXT: ldr w14, [sp, #136]
; CHECK-NEXT: mov.b v2[12], w11
; CHECK-NEXT: ldr w11, [sp, #64]
; CHECK-NEXT: mov.b v0[7], w7
; CHECK-NEXT: mov.b v3[8], w10
; CHECK-NEXT: mov.b v2[13], w9
; CHECK-NEXT: ldr w9, [sp, #72]
; CHECK-NEXT: fmov s1, w11
; CHECK-NEXT: ldr w10, [sp, #272]
; CHECK-NEXT: mov.b v2[14], w8
; CHECK-NEXT: ldr w8, [sp, #80]
; CHECK-NEXT: mov.b v3[9], w12
; CHECK-NEXT: ldr w12, [sp, #280]
; CHECK-NEXT: mov.b v1[1], w9
; CHECK-NEXT: ldr w9, [sp, #88]
; CHECK-NEXT: mov.b v3[10], w10 ; CHECK-NEXT: mov.b v3[10], w10
; CHECK-NEXT: ldr w10, [sp, #160] ; CHECK-NEXT: ldr w10, [sp, #288]
; CHECK-NEXT: mov.b v2[10], w8 ; CHECK-NEXT: mov.b v1[2], w8
; CHECK-NEXT: ldr w8, [sp, #24] ; CHECK-NEXT: ldr w8, [sp, #96]
; CHECK-NEXT: mov.b v0[11], w9 ; CHECK-NEXT: mov.b v3[11], w12
; CHECK-NEXT: ldr w9, [sp, #288] ; CHECK-NEXT: ldr w12, [sp, #304]
; CHECK-NEXT: mov.b v1[11], w12 ; CHECK-NEXT: mov.b v1[3], w9
; CHECK-NEXT: ldr w12, [sp, #296] ; CHECK-NEXT: ldr w9, [sp, #104]
; CHECK-NEXT: mov.b v3[11], w8 ; CHECK-NEXT: mov.b v3[12], w10
; CHECK-NEXT: ldr w10, [sp, #296]
; CHECK-NEXT: mov.b v1[4], w8
; CHECK-NEXT: ldr w8, [sp, #112]
; CHECK-NEXT: ldr w11, [sp, #440]
; CHECK-NEXT: mov.b v1[5], w9
; CHECK-NEXT: ldr w9, [sp, #120]
; CHECK-NEXT: mov.b v3[13], w10
; CHECK-NEXT: mov.b v1[6], w8
; CHECK-NEXT: ldr w8, [sp]
; CHECK-NEXT: mov.b v3[14], w12
; CHECK-NEXT: mov.b v2[15], w11
; CHECK-NEXT: mov.b v1[7], w9
; CHECK-NEXT: ldr w9, [sp, #8]
; CHECK-NEXT: mov.b v0[8], w8
; CHECK-NEXT: ldr w8, [sp, #16]
; CHECK-NEXT: mov.b v1[8], w13
; CHECK-NEXT: ldr w13, [sp, #144]
; CHECK-NEXT: mov.b v0[9], w9
; CHECK-NEXT: ldr w9, [sp, #24]
; CHECK-NEXT: mov.b v1[9], w14
; CHECK-NEXT: ldr w14, [sp, #152]
; CHECK-NEXT: mov.b v0[10], w8
; CHECK-NEXT: ldr w8, [sp, #32] ; CHECK-NEXT: ldr w8, [sp, #32]
; CHECK-NEXT: mov.b v2[11], w13 ; CHECK-NEXT: mov.b v1[10], w13
; CHECK-NEXT: mov.b v0[12], w14 ; CHECK-NEXT: ldr w13, [sp, #160]
; CHECK-NEXT: mov.b v1[12], w10 ; CHECK-NEXT: mov.b v0[11], w9
; CHECK-NEXT: ldr w10, [sp, #168] ; CHECK-NEXT: ldr w9, [sp, #40]
; CHECK-NEXT: mov.b v3[12], w8 ; CHECK-NEXT: mov.b v1[11], w14
; CHECK-NEXT: ldr w8, [sp, #40] ; CHECK-NEXT: ldr w14, [sp, #168]
; CHECK-NEXT: mov.b v2[12], w9 ; CHECK-NEXT: mov.b v0[12], w8
; CHECK-NEXT: ldr w9, [sp, #304]
; CHECK-NEXT: mov.b v0[13], w11
; CHECK-NEXT: ldr w11, [sp, #312]
; CHECK-NEXT: mov.b v1[13], w10
; CHECK-NEXT: ldr w10, [sp, #176]
; CHECK-NEXT: mov.b v3[13], w8
; CHECK-NEXT: ldr w8, [sp, #48] ; CHECK-NEXT: ldr w8, [sp, #48]
; CHECK-NEXT: mov.b v2[13], w12 ; CHECK-NEXT: mov.b v1[12], w13
; CHECK-NEXT: mov.b v0[14], w15 ; CHECK-NEXT: ldr w13, [sp, #176]
; CHECK-NEXT: mov.b v1[14], w10 ; CHECK-NEXT: mov.b v0[13], w9
; CHECK-NEXT: ldr w10, [sp, #184] ; CHECK-NEXT: ldr w9, [sp, #56]
; CHECK-NEXT: mov.b v3[14], w8 ; CHECK-NEXT: mov.b v1[13], w14
; CHECK-NEXT: ldr w8, [sp, #56] ; CHECK-NEXT: ldr w14, [sp, #184]
; CHECK-NEXT: mov.b v2[14], w9 ; CHECK-NEXT: mov.b v0[14], w8
; CHECK-NEXT: mov.b v0[15], w16 ; CHECK-NEXT: ldr w8, [sp, #312]
; CHECK-NEXT: mov.b v1[15], w10 ; CHECK-NEXT: mov.b v1[14], w13
; CHECK-NEXT: shl.16b v4, v2, #7
; CHECK-NEXT: mov.b v0[15], w9
; CHECK-NEXT: mov.b v1[15], w14
; CHECK-NEXT: mov.b v3[15], w8 ; CHECK-NEXT: mov.b v3[15], w8
; CHECK-NEXT: mov.b v2[15], w11 ; CHECK-NEXT: shl.16b v0, v0, #7
; CHECK-NEXT: shl.16b v4, v0, #7
; CHECK-NEXT: shl.16b v1, v1, #7 ; CHECK-NEXT: shl.16b v1, v1, #7
; CHECK-NEXT: shl.16b v3, v3, #7 ; CHECK-NEXT: shl.16b v3, v3, #7
; CHECK-NEXT: shl.16b v2, v2, #7 ; CHECK-NEXT: cmlt.16b v0, v0, #0
; CHECK-NEXT: cmlt.16b v0, v3, #0
; CHECK-NEXT: cmlt.16b v1, v1, #0 ; CHECK-NEXT: cmlt.16b v1, v1, #0
; CHECK-NEXT: cmlt.16b v2, v2, #0 ; CHECK-NEXT: cmlt.16b v2, v3, #0
; CHECK-NEXT: cmlt.16b v3, v4, #0 ; CHECK-NEXT: cmlt.16b v3, v4, #0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = sext <64 x i1> %arg to <64 x i8> %res = sext <64 x i1> %arg to <64 x i8>
ret <64 x i8> %res ret <64 x i8> %res
} }
define <1 x i128> @sext_v1x64(<1 x i64> %arg) { define <1 x i128> @sext_v1x64(<1 x i64> %arg) {
; X0 & X1 are the real return registers, SDAG messes with v0 too for unknown reasons. ; X0 & X1 are the real return registers, SDAG messes with v0 too for unknown reasons.
Show All 18 Lines

llvm/test/CodeGen/AArch64/arm64-vabs.ll

Show First 20 Lines • Show All 295 Lines • ▼ Show 20 Lines
; DAG: // %bb.0: ; DAG: // %bb.0:
; DAG-NEXT: uabdl.4s v0, v0, v1 ; DAG-NEXT: uabdl.4s v0, v0, v1
; DAG-NEXT: addv.4s s0, v0 ; DAG-NEXT: addv.4s s0, v0
; DAG-NEXT: fmov w0, s0 ; DAG-NEXT: fmov w0, s0
; DAG-NEXT: ret ; DAG-NEXT: ret
; ;
; GISEL-LABEL: uabdl4s_rdx_i32: ; GISEL-LABEL: uabdl4s_rdx_i32:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: movi.2d v2, #0000000000000000
; GISEL-NEXT: usubl.4s v0, v0, v1 ; GISEL-NEXT: usubl.4s v0, v0, v1
; GISEL-NEXT: movi.2d v2, #0000000000000000
; GISEL-NEXT: cmgt.4s v1, v2, v0 ; GISEL-NEXT: cmgt.4s v1, v2, v0
; GISEL-NEXT: neg.4s v2, v0 ; GISEL-NEXT: neg.4s v2, v0
; GISEL-NEXT: shl.4s v1, v1, #31 ; GISEL-NEXT: shl.4s v1, v1, #31
; GISEL-NEXT: sshr.4s v1, v1, #31 ; GISEL-NEXT: sshr.4s v1, v1, #31
; GISEL-NEXT: bit.16b v0, v2, v1 ; GISEL-NEXT: bit.16b v0, v2, v1
; GISEL-NEXT: addv.4s s0, v0 ; GISEL-NEXT: addv.4s s0, v0
; GISEL-NEXT: fmov w0, s0 ; GISEL-NEXT: fmov w0, s0
; GISEL-NEXT: ret ; GISEL-NEXT: ret
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; DAG: // %bb.0: ; DAG: // %bb.0:
; DAG-NEXT: uabdl.2d v0, v0, v1 ; DAG-NEXT: uabdl.2d v0, v0, v1
; DAG-NEXT: addp.2d d0, v0 ; DAG-NEXT: addp.2d d0, v0
; DAG-NEXT: fmov x0, d0 ; DAG-NEXT: fmov x0, d0
; DAG-NEXT: ret ; DAG-NEXT: ret
; ;
; GISEL-LABEL: uabdl2d_rdx_i64: ; GISEL-LABEL: uabdl2d_rdx_i64:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: movi.2d v2, #0000000000000000
; GISEL-NEXT: usubl.2d v0, v0, v1 ; GISEL-NEXT: usubl.2d v0, v0, v1
; GISEL-NEXT: movi.2d v2, #0000000000000000
; GISEL-NEXT: cmgt.2d v1, v2, v0 ; GISEL-NEXT: cmgt.2d v1, v2, v0
; GISEL-NEXT: neg.2d v2, v0 ; GISEL-NEXT: neg.2d v2, v0
; GISEL-NEXT: shl.2d v1, v1, #63 ; GISEL-NEXT: shl.2d v1, v1, #63
; GISEL-NEXT: sshr.2d v1, v1, #63 ; GISEL-NEXT: sshr.2d v1, v1, #63
; GISEL-NEXT: bit.16b v0, v2, v1 ; GISEL-NEXT: bit.16b v0, v2, v1
; GISEL-NEXT: addp.2d d0, v0 ; GISEL-NEXT: addp.2d d0, v0
; GISEL-NEXT: fmov x0, d0 ; GISEL-NEXT: fmov x0, d0
; GISEL-NEXT: ret ; GISEL-NEXT: ret
▲ Show 20 Lines • Show All 1,248 Lines • ▼ Show 20 Lines
; DAG-LABEL: abspattern4: ; DAG-LABEL: abspattern4:
; DAG: // %bb.0: ; DAG: // %bb.0:
; DAG-NEXT: abs.4s v0, v0 ; DAG-NEXT: abs.4s v0, v0
; DAG-NEXT: ret ; DAG-NEXT: ret
; ;
; GISEL-LABEL: abspattern4: ; GISEL-LABEL: abspattern4:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: movi.2d v1, #0000000000000000 ; GISEL-NEXT: movi.2d v1, #0000000000000000
; GISEL-NEXT: neg.4s v2, v0
; GISEL-NEXT: cmge.4s v1, v0, v1 ; GISEL-NEXT: cmge.4s v1, v0, v1
; GISEL-NEXT: neg.4s v2, v0
; GISEL-NEXT: shl.4s v1, v1, #31 ; GISEL-NEXT: shl.4s v1, v1, #31
; GISEL-NEXT: sshr.4s v1, v1, #31 ; GISEL-NEXT: sshr.4s v1, v1, #31
; GISEL-NEXT: bif.16b v0, v2, v1 ; GISEL-NEXT: bif.16b v0, v2, v1
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%tmp1neg = sub <4 x i32> zeroinitializer, %a %tmp1neg = sub <4 x i32> zeroinitializer, %a
%b = icmp sge <4 x i32> %a, zeroinitializer %b = icmp sge <4 x i32> %a, zeroinitializer
%abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg
ret <4 x i32> %abs ret <4 x i32> %abs
} }
define <8 x i16> @abspattern5(<8 x i16> %a) nounwind { define <8 x i16> @abspattern5(<8 x i16> %a) nounwind {
; DAG-LABEL: abspattern5: ; DAG-LABEL: abspattern5:
; DAG: // %bb.0: ; DAG: // %bb.0:
; DAG-NEXT: abs.8h v0, v0 ; DAG-NEXT: abs.8h v0, v0
; DAG-NEXT: ret ; DAG-NEXT: ret
; ;
; GISEL-LABEL: abspattern5: ; GISEL-LABEL: abspattern5:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: movi.2d v1, #0000000000000000 ; GISEL-NEXT: movi.2d v1, #0000000000000000
; GISEL-NEXT: neg.8h v2, v0
; GISEL-NEXT: cmgt.8h v1, v0, v1 ; GISEL-NEXT: cmgt.8h v1, v0, v1
; GISEL-NEXT: neg.8h v2, v0
; GISEL-NEXT: shl.8h v1, v1, #15 ; GISEL-NEXT: shl.8h v1, v1, #15
; GISEL-NEXT: sshr.8h v1, v1, #15 ; GISEL-NEXT: sshr.8h v1, v1, #15
; GISEL-NEXT: bif.16b v0, v2, v1 ; GISEL-NEXT: bif.16b v0, v2, v1
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%tmp1neg = sub <8 x i16> zeroinitializer, %a %tmp1neg = sub <8 x i16> zeroinitializer, %a
%b = icmp sgt <8 x i16> %a, zeroinitializer %b = icmp sgt <8 x i16> %a, zeroinitializer
%abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg %abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg
ret <8 x i16> %abs ret <8 x i16> %abs
} }
define <16 x i8> @abspattern6(<16 x i8> %a) nounwind { define <16 x i8> @abspattern6(<16 x i8> %a) nounwind {
; DAG-LABEL: abspattern6: ; DAG-LABEL: abspattern6:
; DAG: // %bb.0: ; DAG: // %bb.0:
; DAG-NEXT: abs.16b v0, v0 ; DAG-NEXT: abs.16b v0, v0
; DAG-NEXT: ret ; DAG-NEXT: ret
; ;
; GISEL-LABEL: abspattern6: ; GISEL-LABEL: abspattern6:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: movi.2d v1, #0000000000000000 ; GISEL-NEXT: movi.2d v1, #0000000000000000
; GISEL-NEXT: neg.16b v2, v0
; GISEL-NEXT: cmgt.16b v1, v1, v0 ; GISEL-NEXT: cmgt.16b v1, v1, v0
; GISEL-NEXT: neg.16b v2, v0
; GISEL-NEXT: shl.16b v1, v1, #7 ; GISEL-NEXT: shl.16b v1, v1, #7
; GISEL-NEXT: sshr.16b v1, v1, #7 ; GISEL-NEXT: sshr.16b v1, v1, #7
; GISEL-NEXT: bit.16b v0, v2, v1 ; GISEL-NEXT: bit.16b v0, v2, v1
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%tmp1neg = sub <16 x i8> zeroinitializer, %a %tmp1neg = sub <16 x i8> zeroinitializer, %a
%b = icmp slt <16 x i8> %a, zeroinitializer %b = icmp slt <16 x i8> %a, zeroinitializer
%abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a %abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a
ret <16 x i8> %abs ret <16 x i8> %abs
} }
define <2 x i64> @abspattern7(<2 x i64> %a) nounwind { define <2 x i64> @abspattern7(<2 x i64> %a) nounwind {
; DAG-LABEL: abspattern7: ; DAG-LABEL: abspattern7:
; DAG: // %bb.0: ; DAG: // %bb.0:
; DAG-NEXT: abs.2d v0, v0 ; DAG-NEXT: abs.2d v0, v0
; DAG-NEXT: ret ; DAG-NEXT: ret
; ;
; GISEL-LABEL: abspattern7: ; GISEL-LABEL: abspattern7:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: movi.2d v1, #0000000000000000 ; GISEL-NEXT: movi.2d v1, #0000000000000000
; GISEL-NEXT: neg.2d v2, v0
; GISEL-NEXT: cmge.2d v1, v1, v0 ; GISEL-NEXT: cmge.2d v1, v1, v0
; GISEL-NEXT: neg.2d v2, v0
; GISEL-NEXT: shl.2d v1, v1, #63 ; GISEL-NEXT: shl.2d v1, v1, #63
; GISEL-NEXT: sshr.2d v1, v1, #63 ; GISEL-NEXT: sshr.2d v1, v1, #63
; GISEL-NEXT: bit.16b v0, v2, v1 ; GISEL-NEXT: bit.16b v0, v2, v1
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%tmp1neg = sub <2 x i64> zeroinitializer, %a %tmp1neg = sub <2 x i64> zeroinitializer, %a
%b = icmp sle <2 x i64> %a, zeroinitializer %b = icmp sle <2 x i64> %a, zeroinitializer
%abs = select <2 x i1> %b, <2 x i64> %tmp1neg, <2 x i64> %a %abs = select <2 x i1> %b, <2 x i64> %tmp1neg, <2 x i64> %a
ret <2 x i64> %abs ret <2 x i64> %abs
} }
define <2 x i64> @uabd_i32(<2 x i32> %a, <2 x i32> %b) { define <2 x i64> @uabd_i32(<2 x i32> %a, <2 x i32> %b) {
; DAG-LABEL: uabd_i32: ; DAG-LABEL: uabd_i32:
; DAG: // %bb.0: ; DAG: // %bb.0:
; DAG-NEXT: sabdl.2d v0, v0, v1 ; DAG-NEXT: sabdl.2d v0, v0, v1
; DAG-NEXT: ret ; DAG-NEXT: ret
; ;
; GISEL-LABEL: uabd_i32: ; GISEL-LABEL: uabd_i32:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: movi.2d v2, #0000000000000000
; GISEL-NEXT: ssubl.2d v0, v0, v1 ; GISEL-NEXT: ssubl.2d v0, v0, v1
; GISEL-NEXT: movi.2d v2, #0000000000000000
; GISEL-NEXT: cmgt.2d v1, v2, v0 ; GISEL-NEXT: cmgt.2d v1, v2, v0
; GISEL-NEXT: neg.2d v2, v0 ; GISEL-NEXT: neg.2d v2, v0
; GISEL-NEXT: shl.2d v1, v1, #63 ; GISEL-NEXT: shl.2d v1, v1, #63
; GISEL-NEXT: sshr.2d v1, v1, #63 ; GISEL-NEXT: sshr.2d v1, v1, #63
; GISEL-NEXT: bit.16b v0, v2, v1 ; GISEL-NEXT: bit.16b v0, v2, v1
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%aext = sext <2 x i32> %a to <2 x i64> %aext = sext <2 x i32> %a to <2 x i64>
%bext = sext <2 x i32> %b to <2 x i64> %bext = sext <2 x i32> %b to <2 x i64>
Show All 10 Lines
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fmov x9, d0 ; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: fmov x11, d1 ; CHECK-NEXT: fmov x11, d1
; CHECK-NEXT: mov.d x8, v0[1] ; CHECK-NEXT: mov.d x8, v0[1]
; CHECK-NEXT: mov.d x10, v1[1] ; CHECK-NEXT: mov.d x10, v1[1]
; CHECK-NEXT: asr x12, x9, #63 ; CHECK-NEXT: asr x12, x9, #63
; CHECK-NEXT: asr x13, x11, #63 ; CHECK-NEXT: asr x13, x11, #63
; CHECK-NEXT: subs x9, x9, x11 ; CHECK-NEXT: subs x9, x9, x11
; CHECK-NEXT: sbcs x11, x12, x13 ; CHECK-NEXT: asr x11, x8, #63
; CHECK-NEXT: asr x12, x8, #63 ; CHECK-NEXT: sbcs x12, x12, x13
; CHECK-NEXT: asr x13, x10, #63 ; CHECK-NEXT: asr x13, x10, #63
; CHECK-NEXT: subs x8, x8, x10 ; CHECK-NEXT: subs x8, x8, x10
; CHECK-NEXT: sbcs x10, x12, x13 ; CHECK-NEXT: sbcs x10, x11, x13
; CHECK-NEXT: negs x12, x8 ; CHECK-NEXT: negs x11, x8
; CHECK-NEXT: ngcs x13, x10 ; CHECK-NEXT: ngcs x13, x10
; CHECK-NEXT: cmp x10, #0 ; CHECK-NEXT: cmp x10, #0
; CHECK-NEXT: csel x2, x12, x8, lt ; CHECK-NEXT: csel x2, x11, x8, lt
; CHECK-NEXT: csel x3, x13, x10, lt ; CHECK-NEXT: csel x3, x13, x10, lt
; CHECK-NEXT: negs x8, x9 ; CHECK-NEXT: negs x8, x9
; CHECK-NEXT: ngcs x10, x11 ; CHECK-NEXT: ngcs x10, x12
; CHECK-NEXT: cmp x11, #0 ; CHECK-NEXT: cmp x12, #0
; CHECK-NEXT: csel x8, x8, x9, lt ; CHECK-NEXT: csel x8, x8, x9, lt
; CHECK-NEXT: csel x1, x10, x11, lt ; CHECK-NEXT: csel x1, x10, x12, lt
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: mov.d v0[1], x1 ; CHECK-NEXT: mov.d v0[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%aext = sext <2 x i64> %a to <2 x i128> %aext = sext <2 x i64> %a to <2 x i128>
%bext = sext <2 x i64> %b to <2 x i128> %bext = sext <2 x i64> %b to <2 x i128>
%abdiff = sub nsw <2 x i128> %aext, %bext %abdiff = sub nsw <2 x i128> %aext, %bext
%abcmp = icmp slt <2 x i128> %abdiff, zeroinitializer %abcmp = icmp slt <2 x i128> %abdiff, zeroinitializer
%ababs = sub nsw <2 x i128> zeroinitializer, %abdiff %ababs = sub nsw <2 x i128> zeroinitializer, %abdiff
%absel = select <2 x i1> %abcmp, <2 x i128> %ababs, <2 x i128> %abdiff %absel = select <2 x i1> %abcmp, <2 x i128> %ababs, <2 x i128> %abdiff
ret <2 x i128> %absel ret <2 x i128> %absel
} }

llvm/test/CodeGen/AArch64/arm64-vhadd.ll

Show First 20 Lines • Show All 1,056 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
store <4 x i32> %result, <4 x i32>* %dest, align 16 store <4 x i32> %result, <4 x i32>* %dest, align 16
ret void ret void
} }
define <8 x i8> @andmaskv8i8(<8 x i16> %src1, <8 x i8> %src2) nounwind { define <8 x i8> @andmaskv8i8(<8 x i16> %src1, <8 x i8> %src2) nounwind {
; CHECK-LABEL: andmaskv8i8: ; CHECK-LABEL: andmaskv8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi.8b v2, #7
; CHECK-NEXT: xtn.8b v0, v0 ; CHECK-NEXT: xtn.8b v0, v0
; CHECK-NEXT: movi.8b v2, #7
; CHECK-NEXT: and.8b v0, v0, v2 ; CHECK-NEXT: and.8b v0, v0, v2
; CHECK-NEXT: uhadd.8b v0, v0, v1 ; CHECK-NEXT: uhadd.8b v0, v0, v1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%zextsrc1 = and <8 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7> %zextsrc1 = and <8 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
%zextsrc2 = zext <8 x i8> %src2 to <8 x i16> %zextsrc2 = zext <8 x i8> %src2 to <8 x i16>
%add = add <8 x i16> %zextsrc1, %zextsrc2 %add = add <8 x i16> %zextsrc1, %zextsrc2
%resulti16 = lshr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %resulti16 = lshr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
%result = trunc <8 x i16> %resulti16 to <8 x i8> %result = trunc <8 x i16> %resulti16 to <8 x i8>
ret <8 x i8> %result ret <8 x i8> %result
} }
define <16 x i8> @andmaskv16i8(<16 x i16> %src1, <16 x i8> %src2) nounwind { define <16 x i8> @andmaskv16i8(<16 x i16> %src1, <16 x i8> %src2) nounwind {
; CHECK-LABEL: andmaskv16i8: ; CHECK-LABEL: andmaskv16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi.16b v3, #7
; CHECK-NEXT: uzp1.16b v0, v0, v1 ; CHECK-NEXT: uzp1.16b v0, v0, v1
; CHECK-NEXT: and.16b v0, v0, v3 ; CHECK-NEXT: movi.16b v1, #7
; CHECK-NEXT: and.16b v0, v0, v1
; CHECK-NEXT: uhadd.16b v0, v0, v2 ; CHECK-NEXT: uhadd.16b v0, v0, v2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%zextsrc1 = and <16 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7> %zextsrc1 = and <16 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
%zextsrc2 = zext <16 x i8> %src2 to <16 x i16> %zextsrc2 = zext <16 x i8> %src2 to <16 x i16>
%add = add <16 x i16> %zextsrc1, %zextsrc2 %add = add <16 x i16> %zextsrc1, %zextsrc2
%resulti16 = lshr <16 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %resulti16 = lshr <16 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
%result = trunc <16 x i16> %resulti16 to <16 x i8> %result = trunc <16 x i16> %resulti16 to <16 x i8>
ret <16 x i8> %result ret <16 x i8> %result
} }
define <16 x i8> @andmask2v16i8(<16 x i16> %src1, <16 x i16> %src2) nounwind { define <16 x i8> @andmask2v16i8(<16 x i16> %src1, <16 x i16> %src2) nounwind {
; CHECK-LABEL: andmask2v16i8: ; CHECK-LABEL: andmask2v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi.16b v4, #3
; CHECK-NEXT: movi.16b v5, #7
; CHECK-NEXT: uzp1.16b v2, v2, v3 ; CHECK-NEXT: uzp1.16b v2, v2, v3
; CHECK-NEXT: uzp1.16b v0, v0, v1 ; CHECK-NEXT: uzp1.16b v0, v0, v1
; CHECK-NEXT: movi.16b v4, #3
; CHECK-NEXT: movi.16b v5, #7
; CHECK-NEXT: and.16b v1, v2, v4 ; CHECK-NEXT: and.16b v1, v2, v4
; CHECK-NEXT: and.16b v0, v0, v5 ; CHECK-NEXT: and.16b v0, v0, v5
; CHECK-NEXT: uhadd.16b v0, v0, v1 ; CHECK-NEXT: uhadd.16b v0, v0, v1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%zextsrc1 = and <16 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7> %zextsrc1 = and <16 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
%zextsrc2 = and <16 x i16> %src2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> %zextsrc2 = and <16 x i16> %src2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
%add = add <16 x i16> %zextsrc1, %zextsrc2 %add = add <16 x i16> %zextsrc1, %zextsrc2
%resulti16 = lshr <16 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %resulti16 = lshr <16 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
%result = trunc <16 x i16> %resulti16 to <16 x i8> %result = trunc <16 x i16> %resulti16 to <16 x i8>
ret <16 x i8> %result ret <16 x i8> %result
} }
define <8 x i8> @andmask2v8i8(<8 x i16> %src1, <8 x i16> %src2) nounwind { define <8 x i8> @andmask2v8i8(<8 x i16> %src1, <8 x i16> %src2) nounwind {
; CHECK-LABEL: andmask2v8i8: ; CHECK-LABEL: andmask2v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi.8b v2, #7
; CHECK-NEXT: xtn.8b v0, v0 ; CHECK-NEXT: xtn.8b v0, v0
; CHECK-NEXT: movi.8b v2, #7
; CHECK-NEXT: xtn.8b v1, v1 ; CHECK-NEXT: xtn.8b v1, v1
; CHECK-NEXT: and.8b v0, v0, v2 ; CHECK-NEXT: and.8b v0, v0, v2
; CHECK-NEXT: uhadd.8b v0, v0, v1 ; CHECK-NEXT: uhadd.8b v0, v0, v1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%zextsrc1 = and <8 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7> %zextsrc1 = and <8 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
%zextsrc2 = and <8 x i16> %src2, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %zextsrc2 = and <8 x i16> %src2, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
%add = add <8 x i16> %zextsrc1, %zextsrc2 %add = add <8 x i16> %zextsrc1, %zextsrc2
%resulti16 = lshr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %resulti16 = lshr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
%result = trunc <8 x i16> %resulti16 to <8 x i8> %result = trunc <8 x i16> %resulti16 to <8 x i8>
ret <8 x i8> %result ret <8 x i8> %result
} }
define <8 x i16> @andmask3v8i8(<8 x i16> %src1, <8 x i16> %src2) nounwind { define <8 x i16> @andmask3v8i8(<8 x i16> %src1, <8 x i16> %src2) nounwind {
; CHECK-LABEL: andmask3v8i8: ; CHECK-LABEL: andmask3v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi.8h v2, #7 ; CHECK-NEXT: movi.8h v2, #7
; CHECK-NEXT: bic.8h v1, #254, lsl #8
; CHECK-NEXT: and.16b v0, v0, v2 ; CHECK-NEXT: and.16b v0, v0, v2
; CHECK-NEXT: bic.8h v1, #254, lsl #8
; CHECK-NEXT: uhadd.8h v0, v0, v1 ; CHECK-NEXT: uhadd.8h v0, v0, v1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%zextsrc1 = and <8 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7> %zextsrc1 = and <8 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
%zextsrc2 = and <8 x i16> %src2, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511> %zextsrc2 = and <8 x i16> %src2, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511>
%add = add <8 x i16> %zextsrc1, %zextsrc2 %add = add <8 x i16> %zextsrc1, %zextsrc2
%resulti16 = lshr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %resulti16 = lshr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
ret <8 x i16> %resulti16 ret <8 x i16> %resulti16
} }
▲ Show 20 Lines • Show All 78 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/arm64-vmul.ll

Show First 20 Lines • Show All 982 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%tmp3 = shufflevector <4 x i32> %tmp2, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp3 = shufflevector <4 x i32> %tmp2, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
%tmp4 = mul <4 x i32> %tmp1, %tmp3 %tmp4 = mul <4 x i32> %tmp1, %tmp3
ret <4 x i32> %tmp4 ret <4 x i32> %tmp4
} }
define <2 x i64> @mul_2d(<2 x i64> %A, <2 x i64> %B) nounwind { define <2 x i64> @mul_2d(<2 x i64> %A, <2 x i64> %B) nounwind {
; CHECK-LABEL: mul_2d: ; CHECK-LABEL: mul_2d:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fmov x9, d1 ; CHECK-NEXT: fmov x8, d1
; CHECK-NEXT: fmov x10, d0 ; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: mov.d x8, v1[1] ; CHECK-NEXT: mov.d x10, v0[1]
; CHECK-NEXT: mov.d x11, v0[1] ; CHECK-NEXT: mul x8, x9, x8
; CHECK-NEXT: mov.d x9, v1[1]
; CHECK-NEXT: mul x9, x10, x9 ; CHECK-NEXT: mul x9, x10, x9
; CHECK-NEXT: mul x8, x11, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: mov.d v0[1], x9
; CHECK-NEXT: mov.d v0[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = mul <2 x i64> %A, %B %tmp1 = mul <2 x i64> %A, %B
ret <2 x i64> %tmp1 ret <2 x i64> %tmp1
} }
define <2 x float> @fmul_lane_2s(<2 x float>* %A, <2 x float>* %B) nounwind { define <2 x float> @fmul_lane_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
; CHECK-LABEL: fmul_lane_2s: ; CHECK-LABEL: fmul_lane_2s:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
▲ Show 20 Lines • Show All 1,803 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/bitcast-promote-widen.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s
; Test cases of bitcasts where one type needs to be widened and one needs to be promoted. ; Test cases of bitcasts where one type needs to be widened and one needs to be promoted.
define <2 x i16> @bitcast_v2i16_v2f16(<2 x half> %x) { define <2 x i16> @bitcast_v2i16_v2f16(<2 x half> %x) {
; CHECK-LABEL: bitcast_v2i16_v2f16: ; CHECK-LABEL: bitcast_v2i16_v2f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.h[0] ; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: umov w9, v0.h[1] ; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: mov v0.s[1], w9 ; CHECK-NEXT: mov v1.s[1], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: fmov d0, d1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = bitcast <2 x half> %x to <2 x i16> %y = bitcast <2 x half> %x to <2 x i16>
ret <2 x i16> %y ret <2 x i16> %y
} }
define <2 x half> @bitcast_v2f16_v2i16(<2 x i16> %x) { define <2 x half> @bitcast_v2f16_v2i16(<2 x i16> %x) {
; CHECK-LABEL: bitcast_v2f16_v2i16: ; CHECK-LABEL: bitcast_v2f16_v2i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: uzp1 v0.4h, v0.4h, v0.4h ; CHECK-NEXT: uzp1 v0.4h, v0.4h, v0.4h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = bitcast <2 x i16> %x to <2 x half> %y = bitcast <2 x i16> %x to <2 x half>
ret <2 x half> %y ret <2 x half> %y
} }

llvm/test/CodeGen/AArch64/build-vector-extract.ll

Show All 10 Lines; CHECK-NEXT: ret
%z = zext i32 %e to i64 %z = zext i32 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i32_zext_insert0_i64_zero(<4 x i32> %x) { define <2 x i64> @extract0_i32_zext_insert0_i64_zero(<4 x i32> %x) {
; CHECK-LABEL: extract0_i32_zext_insert0_i64_zero: ; CHECK-LABEL: extract0_i32_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: mov v1.d[0], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <4 x i32> %x, i32 0 %e = extractelement <4 x i32> %x, i32 0
%z = zext i32 %e to i64 %z = zext i32 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i32_zext_insert0_i64_undef(<4 x i32> %x) { define <2 x i64> @extract1_i32_zext_insert0_i64_undef(<4 x i32> %x) {
; CHECK-LABEL: extract1_i32_zext_insert0_i64_undef: ; CHECK-LABEL: extract1_i32_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: zip1 v0.4s, v0.4s, v0.4s ; CHECK-NEXT: zip1 v0.4s, v0.4s, v0.4s
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #12 ; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <4 x i32> %x, i32 1 %e = extractelement <4 x i32> %x, i32 1
%z = zext i32 %e to i64 %z = zext i32 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i32_zext_insert0_i64_zero(<4 x i32> %x) { define <2 x i64> @extract1_i32_zext_insert0_i64_zero(<4 x i32> %x) {
; CHECK-LABEL: extract1_i32_zext_insert0_i64_zero: ; CHECK-LABEL: extract1_i32_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: mov v1.d[0], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <4 x i32> %x, i32 1 %e = extractelement <4 x i32> %x, i32 1
%z = zext i32 %e to i64 %z = zext i32 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i32_zext_insert0_i64_undef(<4 x i32> %x) { define <2 x i64> @extract2_i32_zext_insert0_i64_undef(<4 x i32> %x) {
; CHECK-LABEL: extract2_i32_zext_insert0_i64_undef: ; CHECK-LABEL: extract2_i32_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: uzp1 v0.4s, v0.4s, v0.4s ; CHECK-NEXT: uzp1 v0.4s, v0.4s, v0.4s
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #12 ; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <4 x i32> %x, i32 2 %e = extractelement <4 x i32> %x, i32 2
%z = zext i32 %e to i64 %z = zext i32 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i32_zext_insert0_i64_zero(<4 x i32> %x) { define <2 x i64> @extract2_i32_zext_insert0_i64_zero(<4 x i32> %x) {
; CHECK-LABEL: extract2_i32_zext_insert0_i64_zero: ; CHECK-LABEL: extract2_i32_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: mov w8, v0.s[2] ; CHECK-NEXT: mov w8, v0.s[2]
; CHECK-NEXT: mov v1.d[0], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <4 x i32> %x, i32 2 %e = extractelement <4 x i32> %x, i32 2
%z = zext i32 %e to i64 %z = zext i32 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i32_zext_insert0_i64_undef(<4 x i32> %x) { define <2 x i64> @extract3_i32_zext_insert0_i64_undef(<4 x i32> %x) {
; CHECK-LABEL: extract3_i32_zext_insert0_i64_undef: ; CHECK-LABEL: extract3_i32_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000 ; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #12 ; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <4 x i32> %x, i32 3 %e = extractelement <4 x i32> %x, i32 3
%z = zext i32 %e to i64 %z = zext i32 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i32_zext_insert0_i64_zero(<4 x i32> %x) { define <2 x i64> @extract3_i32_zext_insert0_i64_zero(<4 x i32> %x) {
; CHECK-LABEL: extract3_i32_zext_insert0_i64_zero: ; CHECK-LABEL: extract3_i32_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: mov w8, v0.s[3] ; CHECK-NEXT: mov w8, v0.s[3]
; CHECK-NEXT: mov v1.d[0], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <4 x i32> %x, i32 3 %e = extractelement <4 x i32> %x, i32 3
%z = zext i32 %e to i64 %z = zext i32 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i32_zext_insert1_i64_undef(<4 x i32> %x) { define <2 x i64> @extract0_i32_zext_insert1_i64_undef(<4 x i32> %x) {
; CHECK-LABEL: extract0_i32_zext_insert1_i64_undef: ; CHECK-LABEL: extract0_i32_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000 ; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: zip1 v1.4s, v0.4s, v1.4s ; CHECK-NEXT: zip1 v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <4 x i32> %x, i32 0 %e = extractelement <4 x i32> %x, i32 0
%z = zext i32 %e to i64 %z = zext i32 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i32_zext_insert1_i64_zero(<4 x i32> %x) { define <2 x i64> @extract0_i32_zext_insert1_i64_zero(<4 x i32> %x) {
; CHECK-LABEL: extract0_i32_zext_insert1_i64_zero: ; CHECK-LABEL: extract0_i32_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: mov v1.d[1], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <4 x i32> %x, i32 0 %e = extractelement <4 x i32> %x, i32 0
%z = zext i32 %e to i64 %z = zext i32 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i32_zext_insert1_i64_undef(<4 x i32> %x) { define <2 x i64> @extract1_i32_zext_insert1_i64_undef(<4 x i32> %x) {
; CHECK-LABEL: extract1_i32_zext_insert1_i64_undef: ; CHECK-LABEL: extract1_i32_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #4 ; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <4 x i32> %x, i32 1 %e = extractelement <4 x i32> %x, i32 1
%z = zext i32 %e to i64 %z = zext i32 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i32_zext_insert1_i64_zero(<4 x i32> %x) { define <2 x i64> @extract1_i32_zext_insert1_i64_zero(<4 x i32> %x) {
; CHECK-LABEL: extract1_i32_zext_insert1_i64_zero: ; CHECK-LABEL: extract1_i32_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: mov v1.d[1], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <4 x i32> %x, i32 1 %e = extractelement <4 x i32> %x, i32 1
%z = zext i32 %e to i64 %z = zext i32 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i32_zext_insert1_i64_undef(<4 x i32> %x) { define <2 x i64> @extract2_i32_zext_insert1_i64_undef(<4 x i32> %x) {
; CHECK-LABEL: extract2_i32_zext_insert1_i64_undef: ; CHECK-LABEL: extract2_i32_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov v0.s[3], wzr ; CHECK-NEXT: mov v0.s[3], wzr
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <4 x i32> %x, i32 2 %e = extractelement <4 x i32> %x, i32 2
%z = zext i32 %e to i64 %z = zext i32 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i32_zext_insert1_i64_zero(<4 x i32> %x) { define <2 x i64> @extract2_i32_zext_insert1_i64_zero(<4 x i32> %x) {
; CHECK-LABEL: extract2_i32_zext_insert1_i64_zero: ; CHECK-LABEL: extract2_i32_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: mov w8, v0.s[2] ; CHECK-NEXT: mov w8, v0.s[2]
; CHECK-NEXT: mov v1.d[1], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <4 x i32> %x, i32 2 %e = extractelement <4 x i32> %x, i32 2
%z = zext i32 %e to i64 %z = zext i32 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i32_zext_insert1_i64_undef(<4 x i32> %x) { define <2 x i64> @extract3_i32_zext_insert1_i64_undef(<4 x i32> %x) {
; CHECK-LABEL: extract3_i32_zext_insert1_i64_undef: ; CHECK-LABEL: extract3_i32_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000 ; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #4 ; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <4 x i32> %x, i32 3 %e = extractelement <4 x i32> %x, i32 3
%z = zext i32 %e to i64 %z = zext i32 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i32_zext_insert1_i64_zero(<4 x i32> %x) { define <2 x i64> @extract3_i32_zext_insert1_i64_zero(<4 x i32> %x) {
; CHECK-LABEL: extract3_i32_zext_insert1_i64_zero: ; CHECK-LABEL: extract3_i32_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: mov w8, v0.s[3] ; CHECK-NEXT: mov w8, v0.s[3]
; CHECK-NEXT: mov v1.d[1], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <4 x i32> %x, i32 3 %e = extractelement <4 x i32> %x, i32 3
%z = zext i32 %e to i64 %z = zext i32 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i16_zext_insert0_i64_undef(<8 x i16> %x) { define <2 x i64> @extract0_i16_zext_insert0_i64_undef(<8 x i16> %x) {
; CHECK-LABEL: extract0_i16_zext_insert0_i64_undef: ; CHECK-LABEL: extract0_i16_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[0] ; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 0 %e = extractelement <8 x i16> %x, i32 0
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i16_zext_insert0_i64_zero(<8 x i16> %x) { define <2 x i64> @extract0_i16_zext_insert0_i64_zero(<8 x i16> %x) {
; CHECK-LABEL: extract0_i16_zext_insert0_i64_zero: ; CHECK-LABEL: extract0_i16_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: umov w8, v0.h[0] ; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: mov v1.d[0], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 0 %e = extractelement <8 x i16> %x, i32 0
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i16_zext_insert0_i64_undef(<8 x i16> %x) { define <2 x i64> @extract1_i16_zext_insert0_i64_undef(<8 x i16> %x) {
; CHECK-LABEL: extract1_i16_zext_insert0_i64_undef: ; CHECK-LABEL: extract1_i16_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[1] ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 1 %e = extractelement <8 x i16> %x, i32 1
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i16_zext_insert0_i64_zero(<8 x i16> %x) { define <2 x i64> @extract1_i16_zext_insert0_i64_zero(<8 x i16> %x) {
; CHECK-LABEL: extract1_i16_zext_insert0_i64_zero: ; CHECK-LABEL: extract1_i16_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: umov w8, v0.h[1] ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: mov v1.d[0], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 1 %e = extractelement <8 x i16> %x, i32 1
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i16_zext_insert0_i64_undef(<8 x i16> %x) { define <2 x i64> @extract2_i16_zext_insert0_i64_undef(<8 x i16> %x) {
; CHECK-LABEL: extract2_i16_zext_insert0_i64_undef: ; CHECK-LABEL: extract2_i16_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[2] ; CHECK-NEXT: umov w8, v0.h[2]
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 2 %e = extractelement <8 x i16> %x, i32 2
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i16_zext_insert0_i64_zero(<8 x i16> %x) { define <2 x i64> @extract2_i16_zext_insert0_i64_zero(<8 x i16> %x) {
; CHECK-LABEL: extract2_i16_zext_insert0_i64_zero: ; CHECK-LABEL: extract2_i16_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: umov w8, v0.h[2] ; CHECK-NEXT: umov w8, v0.h[2]
; CHECK-NEXT: mov v1.d[0], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 2 %e = extractelement <8 x i16> %x, i32 2
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i16_zext_insert0_i64_undef(<8 x i16> %x) { define <2 x i64> @extract3_i16_zext_insert0_i64_undef(<8 x i16> %x) {
; CHECK-LABEL: extract3_i16_zext_insert0_i64_undef: ; CHECK-LABEL: extract3_i16_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[3] ; CHECK-NEXT: umov w8, v0.h[3]
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 3 %e = extractelement <8 x i16> %x, i32 3
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i16_zext_insert0_i64_zero(<8 x i16> %x) { define <2 x i64> @extract3_i16_zext_insert0_i64_zero(<8 x i16> %x) {
; CHECK-LABEL: extract3_i16_zext_insert0_i64_zero: ; CHECK-LABEL: extract3_i16_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: umov w8, v0.h[3] ; CHECK-NEXT: umov w8, v0.h[3]
; CHECK-NEXT: mov v1.d[0], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 3 %e = extractelement <8 x i16> %x, i32 3
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i16_zext_insert1_i64_undef(<8 x i16> %x) { define <2 x i64> @extract0_i16_zext_insert1_i64_undef(<8 x i16> %x) {
; CHECK-LABEL: extract0_i16_zext_insert1_i64_undef: ; CHECK-LABEL: extract0_i16_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[0] ; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: dup v0.2d, x8 ; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 0 %e = extractelement <8 x i16> %x, i32 0
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i16_zext_insert1_i64_zero(<8 x i16> %x) { define <2 x i64> @extract0_i16_zext_insert1_i64_zero(<8 x i16> %x) {
; CHECK-LABEL: extract0_i16_zext_insert1_i64_zero: ; CHECK-LABEL: extract0_i16_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: umov w8, v0.h[0] ; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: mov v1.d[1], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 0 %e = extractelement <8 x i16> %x, i32 0
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i16_zext_insert1_i64_undef(<8 x i16> %x) { define <2 x i64> @extract1_i16_zext_insert1_i64_undef(<8 x i16> %x) {
; CHECK-LABEL: extract1_i16_zext_insert1_i64_undef: ; CHECK-LABEL: extract1_i16_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[1] ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: dup v0.2d, x8 ; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 1 %e = extractelement <8 x i16> %x, i32 1
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i16_zext_insert1_i64_zero(<8 x i16> %x) { define <2 x i64> @extract1_i16_zext_insert1_i64_zero(<8 x i16> %x) {
; CHECK-LABEL: extract1_i16_zext_insert1_i64_zero: ; CHECK-LABEL: extract1_i16_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: umov w8, v0.h[1] ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: mov v1.d[1], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 1 %e = extractelement <8 x i16> %x, i32 1
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i16_zext_insert1_i64_undef(<8 x i16> %x) { define <2 x i64> @extract2_i16_zext_insert1_i64_undef(<8 x i16> %x) {
; CHECK-LABEL: extract2_i16_zext_insert1_i64_undef: ; CHECK-LABEL: extract2_i16_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[2] ; CHECK-NEXT: umov w8, v0.h[2]
; CHECK-NEXT: dup v0.2d, x8 ; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 2 %e = extractelement <8 x i16> %x, i32 2
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i16_zext_insert1_i64_zero(<8 x i16> %x) { define <2 x i64> @extract2_i16_zext_insert1_i64_zero(<8 x i16> %x) {
; CHECK-LABEL: extract2_i16_zext_insert1_i64_zero: ; CHECK-LABEL: extract2_i16_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: umov w8, v0.h[2] ; CHECK-NEXT: umov w8, v0.h[2]
; CHECK-NEXT: mov v1.d[1], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 2 %e = extractelement <8 x i16> %x, i32 2
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i16_zext_insert1_i64_undef(<8 x i16> %x) { define <2 x i64> @extract3_i16_zext_insert1_i64_undef(<8 x i16> %x) {
; CHECK-LABEL: extract3_i16_zext_insert1_i64_undef: ; CHECK-LABEL: extract3_i16_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[3] ; CHECK-NEXT: umov w8, v0.h[3]
; CHECK-NEXT: dup v0.2d, x8 ; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 3 %e = extractelement <8 x i16> %x, i32 3
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i16_zext_insert1_i64_zero(<8 x i16> %x) { define <2 x i64> @extract3_i16_zext_insert1_i64_zero(<8 x i16> %x) {
; CHECK-LABEL: extract3_i16_zext_insert1_i64_zero: ; CHECK-LABEL: extract3_i16_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: umov w8, v0.h[3] ; CHECK-NEXT: umov w8, v0.h[3]
; CHECK-NEXT: mov v1.d[1], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 3 %e = extractelement <8 x i16> %x, i32 3
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
; i8 ; i8
define <2 x i64> @extract0_i8_zext_insert0_i64_undef(<16 x i8> %x) { define <2 x i64> @extract0_i8_zext_insert0_i64_undef(<16 x i8> %x) {
; CHECK-LABEL: extract0_i8_zext_insert0_i64_undef: ; CHECK-LABEL: extract0_i8_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[0] ; CHECK-NEXT: umov w8, v0.b[0]
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 0 %e = extractelement <16 x i8> %x, i32 0
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i8_zext_insert0_i64_zero(<16 x i8> %x) { define <2 x i64> @extract0_i8_zext_insert0_i64_zero(<16 x i8> %x) {
; CHECK-LABEL: extract0_i8_zext_insert0_i64_zero: ; CHECK-LABEL: extract0_i8_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: umov w8, v0.b[0] ; CHECK-NEXT: umov w8, v0.b[0]
; CHECK-NEXT: mov v1.d[0], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 0 %e = extractelement <16 x i8> %x, i32 0
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i8_zext_insert0_i64_undef(<16 x i8> %x) { define <2 x i64> @extract1_i8_zext_insert0_i64_undef(<16 x i8> %x) {
; CHECK-LABEL: extract1_i8_zext_insert0_i64_undef: ; CHECK-LABEL: extract1_i8_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 1 %e = extractelement <16 x i8> %x, i32 1
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i8_zext_insert0_i64_zero(<16 x i8> %x) { define <2 x i64> @extract1_i8_zext_insert0_i64_zero(<16 x i8> %x) {
; CHECK-LABEL: extract1_i8_zext_insert0_i64_zero: ; CHECK-LABEL: extract1_i8_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: mov v1.d[0], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 1 %e = extractelement <16 x i8> %x, i32 1
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i8_zext_insert0_i64_undef(<16 x i8> %x) { define <2 x i64> @extract2_i8_zext_insert0_i64_undef(<16 x i8> %x) {
; CHECK-LABEL: extract2_i8_zext_insert0_i64_undef: ; CHECK-LABEL: extract2_i8_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[2] ; CHECK-NEXT: umov w8, v0.b[2]
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 2 %e = extractelement <16 x i8> %x, i32 2
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i8_zext_insert0_i64_zero(<16 x i8> %x) { define <2 x i64> @extract2_i8_zext_insert0_i64_zero(<16 x i8> %x) {
; CHECK-LABEL: extract2_i8_zext_insert0_i64_zero: ; CHECK-LABEL: extract2_i8_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: umov w8, v0.b[2] ; CHECK-NEXT: umov w8, v0.b[2]
; CHECK-NEXT: mov v1.d[0], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 2 %e = extractelement <16 x i8> %x, i32 2
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i8_zext_insert0_i64_undef(<16 x i8> %x) { define <2 x i64> @extract3_i8_zext_insert0_i64_undef(<16 x i8> %x) {
; CHECK-LABEL: extract3_i8_zext_insert0_i64_undef: ; CHECK-LABEL: extract3_i8_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[3] ; CHECK-NEXT: umov w8, v0.b[3]
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 3 %e = extractelement <16 x i8> %x, i32 3
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i8_zext_insert0_i64_zero(<16 x i8> %x) { define <2 x i64> @extract3_i8_zext_insert0_i64_zero(<16 x i8> %x) {
; CHECK-LABEL: extract3_i8_zext_insert0_i64_zero: ; CHECK-LABEL: extract3_i8_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: umov w8, v0.b[3] ; CHECK-NEXT: umov w8, v0.b[3]
; CHECK-NEXT: mov v1.d[0], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 3 %e = extractelement <16 x i8> %x, i32 3
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i8_zext_insert1_i64_undef(<16 x i8> %x) { define <2 x i64> @extract0_i8_zext_insert1_i64_undef(<16 x i8> %x) {
; CHECK-LABEL: extract0_i8_zext_insert1_i64_undef: ; CHECK-LABEL: extract0_i8_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[0] ; CHECK-NEXT: umov w8, v0.b[0]
; CHECK-NEXT: dup v0.2d, x8 ; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 0 %e = extractelement <16 x i8> %x, i32 0
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i8_zext_insert1_i64_zero(<16 x i8> %x) { define <2 x i64> @extract0_i8_zext_insert1_i64_zero(<16 x i8> %x) {
; CHECK-LABEL: extract0_i8_zext_insert1_i64_zero: ; CHECK-LABEL: extract0_i8_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: umov w8, v0.b[0] ; CHECK-NEXT: umov w8, v0.b[0]
; CHECK-NEXT: mov v1.d[1], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 0 %e = extractelement <16 x i8> %x, i32 0
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i8_zext_insert1_i64_undef(<16 x i8> %x) { define <2 x i64> @extract1_i8_zext_insert1_i64_undef(<16 x i8> %x) {
; CHECK-LABEL: extract1_i8_zext_insert1_i64_undef: ; CHECK-LABEL: extract1_i8_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: dup v0.2d, x8 ; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 1 %e = extractelement <16 x i8> %x, i32 1
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i8_zext_insert1_i64_zero(<16 x i8> %x) { define <2 x i64> @extract1_i8_zext_insert1_i64_zero(<16 x i8> %x) {
; CHECK-LABEL: extract1_i8_zext_insert1_i64_zero: ; CHECK-LABEL: extract1_i8_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: mov v1.d[1], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 1 %e = extractelement <16 x i8> %x, i32 1
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i8_zext_insert1_i64_undef(<16 x i8> %x) { define <2 x i64> @extract2_i8_zext_insert1_i64_undef(<16 x i8> %x) {
; CHECK-LABEL: extract2_i8_zext_insert1_i64_undef: ; CHECK-LABEL: extract2_i8_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[2] ; CHECK-NEXT: umov w8, v0.b[2]
; CHECK-NEXT: dup v0.2d, x8 ; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 2 %e = extractelement <16 x i8> %x, i32 2
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i8_zext_insert1_i64_zero(<16 x i8> %x) { define <2 x i64> @extract2_i8_zext_insert1_i64_zero(<16 x i8> %x) {
; CHECK-LABEL: extract2_i8_zext_insert1_i64_zero: ; CHECK-LABEL: extract2_i8_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: umov w8, v0.b[2] ; CHECK-NEXT: umov w8, v0.b[2]
; CHECK-NEXT: mov v1.d[1], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 2 %e = extractelement <16 x i8> %x, i32 2
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i8_zext_insert1_i64_undef(<16 x i8> %x) { define <2 x i64> @extract3_i8_zext_insert1_i64_undef(<16 x i8> %x) {
; CHECK-LABEL: extract3_i8_zext_insert1_i64_undef: ; CHECK-LABEL: extract3_i8_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[3] ; CHECK-NEXT: umov w8, v0.b[3]
; CHECK-NEXT: dup v0.2d, x8 ; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 3 %e = extractelement <16 x i8> %x, i32 3
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i8_zext_insert1_i64_zero(<16 x i8> %x) { define <2 x i64> @extract3_i8_zext_insert1_i64_zero(<16 x i8> %x) {
; CHECK-LABEL: extract3_i8_zext_insert1_i64_zero: ; CHECK-LABEL: extract3_i8_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: umov w8, v0.b[3] ; CHECK-NEXT: umov w8, v0.b[3]
; CHECK-NEXT: mov v1.d[1], x8 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 3 %e = extractelement <16 x i8> %x, i32 3
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
Show All 19 Lines

llvm/test/CodeGen/AArch64/cmp-select-sign.ll

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%c = icmp ugt i64 %a, -1 %c = icmp ugt i64 %a, -1
%res = select i1 %c, i64 1, i64 -1 %res = select i1 %c, i64 1, i64 -1
ret i64 %res ret i64 %res
} }
define <7 x i8> @sign_7xi8(<7 x i8> %a) { define <7 x i8> @sign_7xi8(<7 x i8> %a) {
; CHECK-LABEL: sign_7xi8: ; CHECK-LABEL: sign_7xi8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.8b, #1
; CHECK-NEXT: cmlt v0.8b, v0.8b, #0 ; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
; CHECK-NEXT: movi v1.8b, #1
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt <7 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> %c = icmp sgt <7 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%res = select <7 x i1> %c, <7 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <7 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> %res = select <7 x i1> %c, <7 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <7 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
ret <7 x i8> %res ret <7 x i8> %res
} }
define <8 x i8> @sign_8xi8(<8 x i8> %a) { define <8 x i8> @sign_8xi8(<8 x i8> %a) {
; CHECK-LABEL: sign_8xi8: ; CHECK-LABEL: sign_8xi8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.8b, #1
; CHECK-NEXT: cmlt v0.8b, v0.8b, #0 ; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
; CHECK-NEXT: movi v1.8b, #1
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt <8 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> %c = icmp sgt <8 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%res = select <8 x i1> %c, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> %res = select <8 x i1> %c, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
ret <8 x i8> %res ret <8 x i8> %res
} }
define <16 x i8> @sign_16xi8(<16 x i8> %a) { define <16 x i8> @sign_16xi8(<16 x i8> %a) {
; CHECK-LABEL: sign_16xi8: ; CHECK-LABEL: sign_16xi8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.16b, #1
; CHECK-NEXT: cmlt v0.16b, v0.16b, #0 ; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
; CHECK-NEXT: movi v1.16b, #1
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> %c = icmp sgt <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%res = select <16 x i1> %c, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> %res = select <16 x i1> %c, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
ret <16 x i8> %res ret <16 x i8> %res
} }
define <3 x i32> @sign_3xi32(<3 x i32> %a) { define <3 x i32> @sign_3xi32(<3 x i32> %a) {
Show All 21 Lines
define <4 x i32> @sign_4xi32_multi_use(<4 x i32> %a) { define <4 x i32> @sign_4xi32_multi_use(<4 x i32> %a) {
; CHECK-LABEL: sign_4xi32_multi_use: ; CHECK-LABEL: sign_4xi32_multi_use:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT: cmgt v1.4s, v0.4s, v1.4s
; CHECK-NEXT: cmlt v2.4s, v0.4s, #0 ; CHECK-NEXT: cmlt v2.4s, v0.4s, #0
; CHECK-NEXT: xtn v0.4h, v1.4s
; CHECK-NEXT: orr v2.4s, #1 ; CHECK-NEXT: orr v2.4s, #1
; CHECK-NEXT: cmgt v1.4s, v0.4s, v1.4s
; CHECK-NEXT: str q2, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q2, [sp] // 16-byte Folded Spill
; CHECK-NEXT: xtn v0.4h, v1.4s
; CHECK-NEXT: bl use_4xi1 ; CHECK-NEXT: bl use_4xi1
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1> %c = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
%res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> %res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
call void @use_4xi1(<4 x i1> %c) call void @use_4xi1(<4 x i1> %c)
ret <4 x i32> %res ret <4 x i32> %res
} }
; Second icmp operand breaks sign pattern. ; Second icmp operand breaks sign pattern.
define <4 x i32> @not_sign_4xi32(<4 x i32> %a) { define <4 x i32> @not_sign_4xi32(<4 x i32> %a) {
; CHECK-LABEL: not_sign_4xi32: ; CHECK-LABEL: not_sign_4xi32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI16_0 ; CHECK-NEXT: adrp x8, .LCPI16_0
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s ; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s
; CHECK-NEXT: and v1.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v1.16b, v0.16b, v1.16b
; CHECK-NEXT: orn v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orn v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt <4 x i32> %a, <i32 1, i32 -1, i32 -1, i32 -1> %c = icmp sgt <4 x i32> %a, <i32 1, i32 -1, i32 -1, i32 -1>
%res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> %res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
ret <4 x i32> %res ret <4 x i32> %res
} }
; First select operand breaks sign pattern. ; First select operand breaks sign pattern.
Show All 9 Lines; CHECK-NEXT: ret
%res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 -1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> %res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 -1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
ret <4 x i32> %res ret <4 x i32> %res
} }
; Second select operand breaks sign pattern. ; Second select operand breaks sign pattern.
define <4 x i32> @not_sign_4xi32_3(<4 x i32> %a) { define <4 x i32> @not_sign_4xi32_3(<4 x i32> %a) {
; CHECK-LABEL: not_sign_4xi32_3: ; CHECK-LABEL: not_sign_4xi32_3:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT: adrp x8, .LCPI18_0 ; CHECK-NEXT: adrp x8, .LCPI18_0
; CHECK-NEXT: movi v2.4s, #1 ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI18_0]
; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s ; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s
; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI18_0]
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1> %c = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
%res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 1> %res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 1>
ret <4 x i32> %res ret <4 x i32> %res
} }
; i65 is not legal. ; i65 is not legal.
define <4 x i65> @sign_4xi65(<4 x i65> %a) { define <4 x i65> @sign_4xi65(<4 x i65> %a) {
; CHECK-LABEL: sign_4xi65: ; CHECK-LABEL: sign_4xi65:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sbfx x8, x1, #0, #1 ; CHECK-NEXT: sbfx x8, x1, #0, #1
; CHECK-NEXT: sbfx x10, x5, #0, #1 ; CHECK-NEXT: sbfx x10, x7, #0, #1
; CHECK-NEXT: orr x9, x8, #0x1 ; CHECK-NEXT: orr x9, x8, #0x1
; CHECK-NEXT: lsr x1, x8, #63 ; CHECK-NEXT: lsr x1, x8, #63
; CHECK-NEXT: sbfx x8, x7, #0, #1 ; CHECK-NEXT: sbfx x8, x5, #0, #1
; CHECK-NEXT: orr x4, x10, #0x1 ; CHECK-NEXT: orr x6, x10, #0x1
; CHECK-NEXT: lsr x5, x10, #63 ; CHECK-NEXT: orr x4, x8, #0x1
; CHECK-NEXT: orr x6, x8, #0x1 ; CHECK-NEXT: lsr x5, x8, #63
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: sbfx x9, x3, #0, #1 ; CHECK-NEXT: sbfx x9, x3, #0, #1
; CHECK-NEXT: orr x2, x9, #0x1 ; CHECK-NEXT: orr x2, x9, #0x1
; CHECK-NEXT: lsr x3, x9, #63 ; CHECK-NEXT: lsr x3, x9, #63
; CHECK-NEXT: lsr x7, x8, #63 ; CHECK-NEXT: lsr x7, x10, #63
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt <4 x i65> %a, <i65 -1, i65 -1, i65 -1, i65 -1> %c = icmp sgt <4 x i65> %a, <i65 -1, i65 -1, i65 -1, i65 -1>
%res = select <4 x i1> %c, <4 x i65> <i65 1, i65 1, i65 1, i65 1>, <4 x i65 > <i65 -1, i65 -1, i65 -1, i65 -1> %res = select <4 x i1> %c, <4 x i65> <i65 1, i65 1, i65 1, i65 1>, <4 x i65 > <i65 -1, i65 -1, i65 -1, i65 -1>
ret <4 x i65> %res ret <4 x i65> %res
} }
declare void @use_4xi1(<4 x i1>) declare void @use_4xi1(<4 x i1>)

llvm/test/CodeGen/AArch64/combine-mul.ll

Show All 22 Lines; CHECK-NEXT: ret
%b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 2> %b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 2>
%c = icmp ne <4 x i32> %b, zeroinitializer %c = icmp ne <4 x i32> %b, zeroinitializer
ret <4 x i1> %c ret <4 x i1> %c
} }
define <4 x i1> @PR48683_vec_undef(<4 x i32> %x) { define <4 x i1> @PR48683_vec_undef(<4 x i32> %x) {
; CHECK-LABEL: PR48683_vec_undef: ; CHECK-LABEL: PR48683_vec_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #2
; CHECK-NEXT: mul v0.4s, v0.4s, v0.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v0.4s
; CHECK-NEXT: movi v1.4s, #2
; CHECK-NEXT: cmtst v0.4s, v0.4s, v1.4s ; CHECK-NEXT: cmtst v0.4s, v0.4s, v1.4s
; CHECK-NEXT: xtn v0.4h, v0.4s ; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = mul <4 x i32> %x, %x %a = mul <4 x i32> %x, %x
%b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 undef> %b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 undef>
%c = icmp ne <4 x i32> %b, zeroinitializer %c = icmp ne <4 x i32> %b, zeroinitializer
ret <4 x i1> %c ret <4 x i1> %c
} }
▲ Show 20 Lines • Show All 101 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/dag-combine-trunc-build-vec.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64 < %s | FileCheck %s ; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
; This test is reduced fom https://github.com/android/ndk/issues/1207 for an ; This test is reduced fom https://github.com/android/ndk/issues/1207 for an
; issue with the following DAGCobmine operation: ; issue with the following DAGCobmine operation:
; truncate(build_vector(x,y)) -> build_vector(truncate(x),truncate(y)) ; truncate(build_vector(x,y)) -> build_vector(truncate(x),truncate(y))
; The combine should avoid creating illegal types if types have already been ; The combine should avoid creating illegal types if types have already been
; legalized. ; legalized.
define void @no_combine(i32 %p) local_unnamed_addr { define void @no_combine(i32 %p) local_unnamed_addr {
; CHECK-LABEL: no_combine: ; CHECK-LABEL: no_combine:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.4h, #4 ; CHECK-NEXT: dup v0.4s, w0
; CHECK-NEXT: dup v1.4s, w0 ; CHECK-NEXT: movi v1.4h, #4
; CHECK-NEXT: xtn v1.4h, v1.4s ; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: mov v1.d[1], v0.d[0] ; CHECK-NEXT: mov v0.d[1], v1.d[0]
; CHECK-NEXT: uzp1 v0.16b, v1.16b, v1.16b ; CHECK-NEXT: uzp1 v0.16b, v0.16b, v0.16b
; CHECK-NEXT: str q0, [x8] ; CHECK-NEXT: str q0, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; The two shufflevector operations are needed to force the DAGCombine to happen ; The two shufflevector operations are needed to force the DAGCombine to happen
; after type legalization and before operation legalization. Removing either ; after type legalization and before operation legalization. Removing either
; makes the combine to happen before type legalization and the issue no longer ; makes the combine to happen before type legalization and the issue no longer
; repros. ; repros.
%1 = insertelement <16 x i32> undef, i32 %p, i32 0 %1 = insertelement <16 x i32> undef, i32 %p, i32 0
Show All 22 Lines

llvm/test/CodeGen/AArch64/dag-numsignbits.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-unknown | FileCheck %s
; PR32273 ; PR32273
define void @signbits_vXi1(<4 x i16> %a1) { define void @signbits_vXi1(<4 x i16> %a1) {
; CHECK-LABEL: signbits_vXi1: ; CHECK-LABEL: signbits_vXi1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI0_0 ; CHECK-NEXT: adrp x8, .LCPI0_0
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: movi v2.4h, #1
; CHECK-NEXT: dup v0.4h, v0.h[0]
; CHECK-NEXT: mov w1, wzr ; CHECK-NEXT: mov w1, wzr
; CHECK-NEXT: dup v0.4h, v0.h[0]
; CHECK-NEXT: mov w2, wzr ; CHECK-NEXT: mov w2, wzr
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_0] ; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_0]
; CHECK-NEXT: adrp x8, .LCPI0_1 ; CHECK-NEXT: adrp x8, .LCPI0_1
; CHECK-NEXT: add v0.4h, v0.4h, v1.4h ; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_1] ; CHECK-NEXT: movi v1.4h, #1
; CHECK-NEXT: cmgt v0.4h, v2.4h, v0.4h ; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI0_1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b ; CHECK-NEXT: cmgt v0.4h, v1.4h, v0.4h
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
; CHECK-NEXT: shl v0.4h, v0.4h, #15 ; CHECK-NEXT: shl v0.4h, v0.4h, #15
; CHECK-NEXT: cmlt v0.4h, v0.4h, #0 ; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
; CHECK-NEXT: umov w0, v0.h[0] ; CHECK-NEXT: umov w0, v0.h[0]
; CHECK-NEXT: umov w3, v0.h[3] ; CHECK-NEXT: umov w3, v0.h[3]
; CHECK-NEXT: b foo ; CHECK-NEXT: b foo
%tmp3 = shufflevector <4 x i16> %a1, <4 x i16> undef, <4 x i32> zeroinitializer %tmp3 = shufflevector <4 x i16> %a1, <4 x i16> undef, <4 x i32> zeroinitializer
%tmp5 = add <4 x i16> %tmp3, <i16 18249, i16 6701, i16 -18744, i16 -25086> %tmp5 = add <4 x i16> %tmp3, <i16 18249, i16 6701, i16 -18744, i16 -25086>
%tmp6 = icmp slt <4 x i16> %tmp5, <i16 1, i16 1, i16 1, i16 1> %tmp6 = icmp slt <4 x i16> %tmp5, <i16 1, i16 1, i16 1, i16 1>
Show All 15 Lines

llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-signed.ll

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y, <16 x i8>* %divdst) nounwind { define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y, <16 x i8>* %divdst) nounwind {
; ALL-LABEL: vector_i128_i8: ; ALL-LABEL: vector_i128_i8:
; ALL: // %bb.0: ; ALL: // %bb.0:
; ALL-NEXT: smov w8, v1.b[1] ; ALL-NEXT: smov w8, v1.b[1]
; ALL-NEXT: smov w9, v0.b[1] ; ALL-NEXT: smov w9, v0.b[1]
; ALL-NEXT: smov w10, v0.b[0] ; ALL-NEXT: smov w10, v0.b[0]
; ALL-NEXT: smov w11, v0.b[2] ; ALL-NEXT: smov w11, v0.b[2]
; ALL-NEXT: sdiv w8, w9, w8
; ALL-NEXT: smov w9, v1.b[0]
; ALL-NEXT: smov w12, v0.b[3] ; ALL-NEXT: smov w12, v0.b[3]
; ALL-NEXT: smov w13, v0.b[4] ; ALL-NEXT: smov w13, v0.b[4]
; ALL-NEXT: smov w14, v0.b[5] ; ALL-NEXT: smov w14, v0.b[5]
; ALL-NEXT: smov w15, v0.b[6] ; ALL-NEXT: smov w15, v0.b[6]
; ALL-NEXT: sdiv w8, w9, w8
; ALL-NEXT: smov w9, v1.b[0]
; ALL-NEXT: smov w16, v0.b[7] ; ALL-NEXT: smov w16, v0.b[7]
; ALL-NEXT: smov w17, v0.b[8] ; ALL-NEXT: smov w17, v0.b[8]
; ALL-NEXT: smov w18, v0.b[9]
; ALL-NEXT: smov w1, v0.b[10]
; ALL-NEXT: smov w2, v0.b[11]
; ALL-NEXT: smov w3, v0.b[12]
; ALL-NEXT: sdiv w9, w10, w9 ; ALL-NEXT: sdiv w9, w10, w9
; ALL-NEXT: smov w10, v1.b[2] ; ALL-NEXT: smov w10, v1.b[2]
; ALL-NEXT: sdiv w10, w11, w10 ; ALL-NEXT: sdiv w10, w11, w10
; ALL-NEXT: smov w11, v1.b[3] ; ALL-NEXT: smov w11, v1.b[3]
; ALL-NEXT: fmov s2, w9 ; ALL-NEXT: fmov s2, w9
; ALL-NEXT: smov w9, v1.b[9]
; ALL-NEXT: mov v2.b[1], w8 ; ALL-NEXT: mov v2.b[1], w8
; ALL-NEXT: smov w8, v1.b[13]
; ALL-NEXT: sdiv w11, w12, w11 ; ALL-NEXT: sdiv w11, w12, w11
; ALL-NEXT: smov w12, v1.b[4] ; ALL-NEXT: smov w12, v1.b[4]
; ALL-NEXT: mov v2.b[2], w10 ; ALL-NEXT: mov v2.b[2], w10
; ALL-NEXT: smov w10, v0.b[10] ; ALL-NEXT: smov w10, v0.b[13]
; ALL-NEXT: sdiv w12, w13, w12 ; ALL-NEXT: sdiv w12, w13, w12
; ALL-NEXT: smov w13, v1.b[5] ; ALL-NEXT: smov w13, v1.b[5]
; ALL-NEXT: mov v2.b[3], w11 ; ALL-NEXT: mov v2.b[3], w11
; ALL-NEXT: smov w11, v0.b[11] ; ALL-NEXT: smov w11, v0.b[14]
; ALL-NEXT: sdiv w13, w14, w13 ; ALL-NEXT: sdiv w13, w14, w13
; ALL-NEXT: smov w14, v1.b[6] ; ALL-NEXT: smov w14, v1.b[6]
; ALL-NEXT: mov v2.b[4], w12 ; ALL-NEXT: mov v2.b[4], w12
; ALL-NEXT: smov w12, v0.b[12] ; ALL-NEXT: smov w12, v0.b[15]
; ALL-NEXT: sdiv w14, w15, w14 ; ALL-NEXT: sdiv w14, w15, w14
; ALL-NEXT: smov w15, v1.b[7] ; ALL-NEXT: smov w15, v1.b[7]
; ALL-NEXT: mov v2.b[5], w13 ; ALL-NEXT: mov v2.b[5], w13
; ALL-NEXT: smov w13, v0.b[13]
; ALL-NEXT: sdiv w15, w16, w15 ; ALL-NEXT: sdiv w15, w16, w15
; ALL-NEXT: smov w16, v1.b[8] ; ALL-NEXT: smov w16, v1.b[8]
; ALL-NEXT: mov v2.b[6], w14 ; ALL-NEXT: mov v2.b[6], w14
; ALL-NEXT: sdiv w16, w17, w16 ; ALL-NEXT: sdiv w16, w17, w16
; ALL-NEXT: smov w17, v0.b[9] ; ALL-NEXT: smov w17, v1.b[9]
; ALL-NEXT: mov v2.b[7], w15 ; ALL-NEXT: mov v2.b[7], w15
; ALL-NEXT: sdiv w8, w17, w9 ; ALL-NEXT: sdiv w17, w18, w17
; ALL-NEXT: smov w9, v1.b[10] ; ALL-NEXT: smov w18, v1.b[10]
; ALL-NEXT: mov v2.b[8], w16 ; ALL-NEXT: mov v2.b[8], w16
; ALL-NEXT: sdiv w9, w10, w9 ; ALL-NEXT: sdiv w18, w1, w18
; ALL-NEXT: smov w10, v1.b[11] ; ALL-NEXT: smov w1, v1.b[11]
; ALL-NEXT: mov v2.b[9], w8 ; ALL-NEXT: mov v2.b[9], w17
; ALL-NEXT: sdiv w1, w2, w1
; ALL-NEXT: smov w2, v1.b[12]
; ALL-NEXT: mov v2.b[10], w18
; ALL-NEXT: sdiv w9, w3, w2
; ALL-NEXT: mov v2.b[11], w1
; ALL-NEXT: sdiv w8, w10, w8
; ALL-NEXT: smov w10, v1.b[14]
; ALL-NEXT: mov v2.b[12], w9
; ALL-NEXT: sdiv w10, w11, w10 ; ALL-NEXT: sdiv w10, w11, w10
; ALL-NEXT: smov w11, v1.b[12] ; ALL-NEXT: smov w11, v1.b[15]
; ALL-NEXT: mov v2.b[10], w9
; ALL-NEXT: smov w9, v1.b[14]
; ALL-NEXT: sdiv w11, w12, w11
; ALL-NEXT: smov w12, v1.b[13]
; ALL-NEXT: mov v2.b[11], w10
; ALL-NEXT: smov w10, v1.b[15]
; ALL-NEXT: sdiv w8, w13, w12
; ALL-NEXT: smov w12, v0.b[14]
; ALL-NEXT: mov v2.b[12], w11
; ALL-NEXT: smov w11, v0.b[15]
; ALL-NEXT: sdiv w9, w12, w9
; ALL-NEXT: mov v2.b[13], w8 ; ALL-NEXT: mov v2.b[13], w8
; ALL-NEXT: sdiv w8, w11, w10 ; ALL-NEXT: sdiv w11, w12, w11
; ALL-NEXT: mov v2.b[14], w9 ; ALL-NEXT: mov v2.b[14], w10
; ALL-NEXT: mov v2.b[15], w8 ; ALL-NEXT: mov v2.b[15], w11
; ALL-NEXT: mls v0.16b, v2.16b, v1.16b ; ALL-NEXT: mls v0.16b, v2.16b, v1.16b
; ALL-NEXT: str q2, [x0] ; ALL-NEXT: str q2, [x0]
; ALL-NEXT: ret ; ALL-NEXT: ret
%div = sdiv <16 x i8> %x, %y %div = sdiv <16 x i8> %x, %y
store <16 x i8> %div, <16 x i8>* %divdst, align 16 store <16 x i8> %div, <16 x i8>* %divdst, align 16
%t1 = mul <16 x i8> %div, %y %t1 = mul <16 x i8> %div, %y
%t2 = sub <16 x i8> %x, %t1 %t2 = sub <16 x i8> %x, %t1
ret <16 x i8> %t2 ret <16 x i8> %t2
} }
define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y, <8 x i16>* %divdst) nounwind { define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y, <8 x i16>* %divdst) nounwind {
; ALL-LABEL: vector_i128_i16: ; ALL-LABEL: vector_i128_i16:
; ALL: // %bb.0: ; ALL: // %bb.0:
; ALL-NEXT: smov w8, v1.h[1] ; ALL-NEXT: smov w8, v1.h[1]
; ALL-NEXT: smov w9, v0.h[1] ; ALL-NEXT: smov w9, v0.h[1]
; ALL-NEXT: smov w10, v0.h[0] ; ALL-NEXT: smov w10, v0.h[0]
; ALL-NEXT: smov w11, v0.h[2] ; ALL-NEXT: smov w11, v0.h[2]
; ALL-NEXT: smov w12, v0.h[3]
; ALL-NEXT: smov w13, v0.h[4]
; ALL-NEXT: sdiv w8, w9, w8 ; ALL-NEXT: sdiv w8, w9, w8
; ALL-NEXT: smov w9, v1.h[0] ; ALL-NEXT: smov w9, v1.h[0]
; ALL-NEXT: smov w12, v0.h[3]
; ALL-NEXT: smov w13, v0.h[4]
; ALL-NEXT: smov w14, v0.h[5]
; ALL-NEXT: smov w15, v0.h[6]
; ALL-NEXT: sdiv w9, w10, w9 ; ALL-NEXT: sdiv w9, w10, w9
; ALL-NEXT: smov w10, v1.h[2] ; ALL-NEXT: smov w10, v1.h[2]
; ALL-NEXT: sdiv w10, w11, w10 ; ALL-NEXT: sdiv w10, w11, w10
; ALL-NEXT: smov w11, v1.h[3] ; ALL-NEXT: smov w11, v1.h[3]
; ALL-NEXT: fmov s2, w9 ; ALL-NEXT: fmov s2, w9
; ALL-NEXT: smov w9, v1.h[5]
; ALL-NEXT: mov v2.h[1], w8 ; ALL-NEXT: mov v2.h[1], w8
; ALL-NEXT: smov w8, v1.h[7]
; ALL-NEXT: sdiv w11, w12, w11 ; ALL-NEXT: sdiv w11, w12, w11
; ALL-NEXT: smov w12, v1.h[4] ; ALL-NEXT: smov w12, v1.h[4]
; ALL-NEXT: mov v2.h[2], w10 ; ALL-NEXT: mov v2.h[2], w10
; ALL-NEXT: smov w10, v0.h[6] ; ALL-NEXT: smov w10, v0.h[7]
; ALL-NEXT: sdiv w12, w13, w12 ; ALL-NEXT: sdiv w12, w13, w12
; ALL-NEXT: smov w13, v0.h[5] ; ALL-NEXT: smov w13, v1.h[5]
; ALL-NEXT: mov v2.h[3], w11 ; ALL-NEXT: mov v2.h[3], w11
; ALL-NEXT: smov w11, v0.h[7] ; ALL-NEXT: sdiv w13, w14, w13
; ALL-NEXT: sdiv w8, w13, w9 ; ALL-NEXT: smov w14, v1.h[6]
; ALL-NEXT: smov w9, v1.h[6]
; ALL-NEXT: mov v2.h[4], w12 ; ALL-NEXT: mov v2.h[4], w12
; ALL-NEXT: sdiv w9, w10, w9 ; ALL-NEXT: sdiv w9, w15, w14
; ALL-NEXT: smov w10, v1.h[7] ; ALL-NEXT: mov v2.h[5], w13
; ALL-NEXT: mov v2.h[5], w8 ; ALL-NEXT: sdiv w8, w10, w8
; ALL-NEXT: sdiv w8, w11, w10
; ALL-NEXT: mov v2.h[6], w9 ; ALL-NEXT: mov v2.h[6], w9
; ALL-NEXT: mov v2.h[7], w8 ; ALL-NEXT: mov v2.h[7], w8
; ALL-NEXT: mls v0.8h, v2.8h, v1.8h ; ALL-NEXT: mls v0.8h, v2.8h, v1.8h
; ALL-NEXT: str q2, [x0] ; ALL-NEXT: str q2, [x0]
; ALL-NEXT: ret ; ALL-NEXT: ret
%div = sdiv <8 x i16> %x, %y %div = sdiv <8 x i16> %x, %y
store <8 x i16> %div, <8 x i16>* %divdst, align 16 store <8 x i16> %div, <8 x i16>* %divdst, align 16
%t1 = mul <8 x i16> %div, %y %t1 = mul <8 x i16> %div, %y
%t2 = sub <8 x i16> %x, %t1 %t2 = sub <8 x i16> %x, %t1
ret <8 x i16> %t2 ret <8 x i16> %t2
} }
define <4 x i32> @vector_i128_i32(<4 x i32> %x, <4 x i32> %y, <4 x i32>* %divdst) nounwind { define <4 x i32> @vector_i128_i32(<4 x i32> %x, <4 x i32> %y, <4 x i32>* %divdst) nounwind {
; ALL-LABEL: vector_i128_i32: ; ALL-LABEL: vector_i128_i32:
; ALL: // %bb.0: ; ALL: // %bb.0:
; ALL-NEXT: mov w8, v1.s[1] ; ALL-NEXT: mov w8, v1.s[1]
; ALL-NEXT: mov w9, v0.s[1] ; ALL-NEXT: mov w9, v0.s[1]
; ALL-NEXT: fmov w10, s0 ; ALL-NEXT: fmov w10, s0
; ALL-NEXT: mov w11, v0.s[2] ; ALL-NEXT: mov w11, v0.s[2]
; ALL-NEXT: mov w12, v0.s[3]
; ALL-NEXT: sdiv w8, w9, w8 ; ALL-NEXT: sdiv w8, w9, w8
; ALL-NEXT: fmov w9, s1 ; ALL-NEXT: fmov w9, s1
; ALL-NEXT: mov w12, v0.s[3]
; ALL-NEXT: sdiv w9, w10, w9 ; ALL-NEXT: sdiv w9, w10, w9
; ALL-NEXT: mov w10, v1.s[2] ; ALL-NEXT: mov w10, v1.s[2]
; ALL-NEXT: sdiv w10, w11, w10 ; ALL-NEXT: sdiv w10, w11, w10
; ALL-NEXT: mov w11, v1.s[3] ; ALL-NEXT: mov w11, v1.s[3]
; ALL-NEXT: fmov s2, w9 ; ALL-NEXT: fmov s2, w9
; ALL-NEXT: mov v2.s[1], w8 ; ALL-NEXT: mov v2.s[1], w8
; ALL-NEXT: sdiv w8, w12, w11 ; ALL-NEXT: sdiv w11, w12, w11
; ALL-NEXT: mov v2.s[2], w10 ; ALL-NEXT: mov v2.s[2], w10
; ALL-NEXT: mov v2.s[3], w8 ; ALL-NEXT: mov v2.s[3], w11
; ALL-NEXT: mls v0.4s, v2.4s, v1.4s ; ALL-NEXT: mls v0.4s, v2.4s, v1.4s
; ALL-NEXT: str q2, [x0] ; ALL-NEXT: str q2, [x0]
; ALL-NEXT: ret ; ALL-NEXT: ret
%div = sdiv <4 x i32> %x, %y %div = sdiv <4 x i32> %x, %y
store <4 x i32> %div, <4 x i32>* %divdst, align 16 store <4 x i32> %div, <4 x i32>* %divdst, align 16
%t1 = mul <4 x i32> %div, %y %t1 = mul <4 x i32> %div, %y
%t2 = sub <4 x i32> %x, %t1 %t2 = sub <4 x i32> %x, %t1
ret <4 x i32> %t2 ret <4 x i32> %t2
} }
define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64>* %divdst) nounwind { define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64>* %divdst) nounwind {
; ALL-LABEL: vector_i128_i64: ; ALL-LABEL: vector_i128_i64:
; ALL: // %bb.0: ; ALL: // %bb.0:
; ALL-NEXT: fmov x8, d1 ; ALL-NEXT: fmov x8, d1
; ALL-NEXT: fmov x9, d0 ; ALL-NEXT: fmov x9, d0
; ALL-NEXT: mov x10, v1.d[1] ; ALL-NEXT: mov x10, v1.d[1]
; ALL-NEXT: mov x11, v0.d[1] ; ALL-NEXT: mov x11, v0.d[1]
; ALL-NEXT: sdiv x9, x9, x8 ; ALL-NEXT: sdiv x9, x9, x8
; ALL-NEXT: mul x8, x9, x8 ; ALL-NEXT: mul x8, x9, x8
; ALL-NEXT: sdiv x11, x11, x10 ; ALL-NEXT: sdiv x11, x11, x10
; ALL-NEXT: fmov d2, x9
; ALL-NEXT: fmov d1, x8 ; ALL-NEXT: fmov d1, x8
; ALL-NEXT: mul x10, x11, x10 ; ALL-NEXT: mul x10, x11, x10
; ALL-NEXT: mov v2.d[1], x11
; ALL-NEXT: mov v1.d[1], x10 ; ALL-NEXT: mov v1.d[1], x10
; ALL-NEXT: str q2, [x0]
; ALL-NEXT: sub v0.2d, v0.2d, v1.2d ; ALL-NEXT: sub v0.2d, v0.2d, v1.2d
; ALL-NEXT: fmov d1, x9
; ALL-NEXT: mov v1.d[1], x11
; ALL-NEXT: str q1, [x0]
; ALL-NEXT: ret ; ALL-NEXT: ret
%div = sdiv <2 x i64> %x, %y %div = sdiv <2 x i64> %x, %y
store <2 x i64> %div, <2 x i64>* %divdst, align 16 store <2 x i64> %div, <2 x i64>* %divdst, align 16
%t1 = mul <2 x i64> %div, %y %t1 = mul <2 x i64> %div, %y
%t2 = sub <2 x i64> %x, %t1 %t2 = sub <2 x i64> %x, %t1
ret <2 x i64> %t2 ret <2 x i64> %t2
} }
▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-unsigned.ll

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y, <16 x i8>* %divdst) nounwind { define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y, <16 x i8>* %divdst) nounwind {
; ALL-LABEL: vector_i128_i8: ; ALL-LABEL: vector_i128_i8:
; ALL: // %bb.0: ; ALL: // %bb.0:
; ALL-NEXT: umov w8, v1.b[1] ; ALL-NEXT: umov w8, v1.b[1]
; ALL-NEXT: umov w9, v0.b[1] ; ALL-NEXT: umov w9, v0.b[1]
; ALL-NEXT: umov w10, v0.b[0] ; ALL-NEXT: umov w10, v0.b[0]
; ALL-NEXT: umov w11, v0.b[2] ; ALL-NEXT: umov w11, v0.b[2]
; ALL-NEXT: udiv w8, w9, w8
; ALL-NEXT: umov w9, v1.b[0]
; ALL-NEXT: umov w12, v0.b[3] ; ALL-NEXT: umov w12, v0.b[3]
; ALL-NEXT: umov w13, v0.b[4] ; ALL-NEXT: umov w13, v0.b[4]
; ALL-NEXT: umov w14, v0.b[5] ; ALL-NEXT: umov w14, v0.b[5]
; ALL-NEXT: umov w15, v0.b[6] ; ALL-NEXT: umov w15, v0.b[6]
; ALL-NEXT: udiv w8, w9, w8
; ALL-NEXT: umov w9, v1.b[0]
; ALL-NEXT: umov w16, v0.b[7] ; ALL-NEXT: umov w16, v0.b[7]
; ALL-NEXT: umov w17, v0.b[8] ; ALL-NEXT: umov w17, v0.b[8]
; ALL-NEXT: umov w18, v0.b[9]
; ALL-NEXT: umov w1, v0.b[10]
; ALL-NEXT: umov w2, v0.b[11]
; ALL-NEXT: umov w3, v0.b[12]
; ALL-NEXT: udiv w9, w10, w9 ; ALL-NEXT: udiv w9, w10, w9
; ALL-NEXT: umov w10, v1.b[2] ; ALL-NEXT: umov w10, v1.b[2]
; ALL-NEXT: udiv w10, w11, w10 ; ALL-NEXT: udiv w10, w11, w10
; ALL-NEXT: umov w11, v1.b[3] ; ALL-NEXT: umov w11, v1.b[3]
; ALL-NEXT: fmov s2, w9 ; ALL-NEXT: fmov s2, w9
; ALL-NEXT: umov w9, v1.b[9]
; ALL-NEXT: mov v2.b[1], w8 ; ALL-NEXT: mov v2.b[1], w8
; ALL-NEXT: umov w8, v1.b[13]
; ALL-NEXT: udiv w11, w12, w11 ; ALL-NEXT: udiv w11, w12, w11
; ALL-NEXT: umov w12, v1.b[4] ; ALL-NEXT: umov w12, v1.b[4]
; ALL-NEXT: mov v2.b[2], w10 ; ALL-NEXT: mov v2.b[2], w10
; ALL-NEXT: umov w10, v0.b[10] ; ALL-NEXT: umov w10, v0.b[13]
; ALL-NEXT: udiv w12, w13, w12 ; ALL-NEXT: udiv w12, w13, w12
; ALL-NEXT: umov w13, v1.b[5] ; ALL-NEXT: umov w13, v1.b[5]
; ALL-NEXT: mov v2.b[3], w11 ; ALL-NEXT: mov v2.b[3], w11
; ALL-NEXT: umov w11, v0.b[11] ; ALL-NEXT: umov w11, v0.b[14]
; ALL-NEXT: udiv w13, w14, w13 ; ALL-NEXT: udiv w13, w14, w13
; ALL-NEXT: umov w14, v1.b[6] ; ALL-NEXT: umov w14, v1.b[6]
; ALL-NEXT: mov v2.b[4], w12 ; ALL-NEXT: mov v2.b[4], w12
; ALL-NEXT: umov w12, v0.b[12] ; ALL-NEXT: umov w12, v0.b[15]
; ALL-NEXT: udiv w14, w15, w14 ; ALL-NEXT: udiv w14, w15, w14
; ALL-NEXT: umov w15, v1.b[7] ; ALL-NEXT: umov w15, v1.b[7]
; ALL-NEXT: mov v2.b[5], w13 ; ALL-NEXT: mov v2.b[5], w13
; ALL-NEXT: umov w13, v0.b[13]
; ALL-NEXT: udiv w15, w16, w15 ; ALL-NEXT: udiv w15, w16, w15
; ALL-NEXT: umov w16, v1.b[8] ; ALL-NEXT: umov w16, v1.b[8]
; ALL-NEXT: mov v2.b[6], w14 ; ALL-NEXT: mov v2.b[6], w14
; ALL-NEXT: udiv w16, w17, w16 ; ALL-NEXT: udiv w16, w17, w16
; ALL-NEXT: umov w17, v0.b[9] ; ALL-NEXT: umov w17, v1.b[9]
; ALL-NEXT: mov v2.b[7], w15 ; ALL-NEXT: mov v2.b[7], w15
; ALL-NEXT: udiv w8, w17, w9 ; ALL-NEXT: udiv w17, w18, w17
; ALL-NEXT: umov w9, v1.b[10] ; ALL-NEXT: umov w18, v1.b[10]
; ALL-NEXT: mov v2.b[8], w16 ; ALL-NEXT: mov v2.b[8], w16
; ALL-NEXT: udiv w9, w10, w9 ; ALL-NEXT: udiv w18, w1, w18
; ALL-NEXT: umov w10, v1.b[11] ; ALL-NEXT: umov w1, v1.b[11]
; ALL-NEXT: mov v2.b[9], w8 ; ALL-NEXT: mov v2.b[9], w17
; ALL-NEXT: udiv w1, w2, w1
; ALL-NEXT: umov w2, v1.b[12]
; ALL-NEXT: mov v2.b[10], w18
; ALL-NEXT: udiv w9, w3, w2
; ALL-NEXT: mov v2.b[11], w1
; ALL-NEXT: udiv w8, w10, w8
; ALL-NEXT: umov w10, v1.b[14]
; ALL-NEXT: mov v2.b[12], w9
; ALL-NEXT: udiv w10, w11, w10 ; ALL-NEXT: udiv w10, w11, w10
; ALL-NEXT: umov w11, v1.b[12] ; ALL-NEXT: umov w11, v1.b[15]
; ALL-NEXT: mov v2.b[10], w9
; ALL-NEXT: umov w9, v1.b[14]
; ALL-NEXT: udiv w11, w12, w11
; ALL-NEXT: umov w12, v1.b[13]
; ALL-NEXT: mov v2.b[11], w10
; ALL-NEXT: umov w10, v1.b[15]
; ALL-NEXT: udiv w8, w13, w12
; ALL-NEXT: umov w12, v0.b[14]
; ALL-NEXT: mov v2.b[12], w11
; ALL-NEXT: umov w11, v0.b[15]
; ALL-NEXT: udiv w9, w12, w9
; ALL-NEXT: mov v2.b[13], w8 ; ALL-NEXT: mov v2.b[13], w8
; ALL-NEXT: udiv w8, w11, w10 ; ALL-NEXT: udiv w11, w12, w11
; ALL-NEXT: mov v2.b[14], w9 ; ALL-NEXT: mov v2.b[14], w10
; ALL-NEXT: mov v2.b[15], w8 ; ALL-NEXT: mov v2.b[15], w11
; ALL-NEXT: mls v0.16b, v2.16b, v1.16b ; ALL-NEXT: mls v0.16b, v2.16b, v1.16b
; ALL-NEXT: str q2, [x0] ; ALL-NEXT: str q2, [x0]
; ALL-NEXT: ret ; ALL-NEXT: ret
%div = udiv <16 x i8> %x, %y %div = udiv <16 x i8> %x, %y
store <16 x i8> %div, <16 x i8>* %divdst, align 16 store <16 x i8> %div, <16 x i8>* %divdst, align 16
%t1 = mul <16 x i8> %div, %y %t1 = mul <16 x i8> %div, %y
%t2 = sub <16 x i8> %x, %t1 %t2 = sub <16 x i8> %x, %t1
ret <16 x i8> %t2 ret <16 x i8> %t2
} }
define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y, <8 x i16>* %divdst) nounwind { define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y, <8 x i16>* %divdst) nounwind {
; ALL-LABEL: vector_i128_i16: ; ALL-LABEL: vector_i128_i16:
; ALL: // %bb.0: ; ALL: // %bb.0:
; ALL-NEXT: umov w8, v1.h[1] ; ALL-NEXT: umov w8, v1.h[1]
; ALL-NEXT: umov w9, v0.h[1] ; ALL-NEXT: umov w9, v0.h[1]
; ALL-NEXT: umov w10, v0.h[0] ; ALL-NEXT: umov w10, v0.h[0]
; ALL-NEXT: umov w11, v0.h[2] ; ALL-NEXT: umov w11, v0.h[2]
; ALL-NEXT: umov w12, v0.h[3]
; ALL-NEXT: umov w13, v0.h[4]
; ALL-NEXT: udiv w8, w9, w8 ; ALL-NEXT: udiv w8, w9, w8
; ALL-NEXT: umov w9, v1.h[0] ; ALL-NEXT: umov w9, v1.h[0]
; ALL-NEXT: umov w12, v0.h[3]
; ALL-NEXT: umov w13, v0.h[4]
; ALL-NEXT: umov w14, v0.h[5]
; ALL-NEXT: umov w15, v0.h[6]
; ALL-NEXT: udiv w9, w10, w9 ; ALL-NEXT: udiv w9, w10, w9
; ALL-NEXT: umov w10, v1.h[2] ; ALL-NEXT: umov w10, v1.h[2]
; ALL-NEXT: udiv w10, w11, w10 ; ALL-NEXT: udiv w10, w11, w10
; ALL-NEXT: umov w11, v1.h[3] ; ALL-NEXT: umov w11, v1.h[3]
; ALL-NEXT: fmov s2, w9 ; ALL-NEXT: fmov s2, w9
; ALL-NEXT: umov w9, v1.h[5]
; ALL-NEXT: mov v2.h[1], w8 ; ALL-NEXT: mov v2.h[1], w8
; ALL-NEXT: umov w8, v1.h[7]
; ALL-NEXT: udiv w11, w12, w11 ; ALL-NEXT: udiv w11, w12, w11
; ALL-NEXT: umov w12, v1.h[4] ; ALL-NEXT: umov w12, v1.h[4]
; ALL-NEXT: mov v2.h[2], w10 ; ALL-NEXT: mov v2.h[2], w10
; ALL-NEXT: umov w10, v0.h[6] ; ALL-NEXT: umov w10, v0.h[7]
; ALL-NEXT: udiv w12, w13, w12 ; ALL-NEXT: udiv w12, w13, w12
; ALL-NEXT: umov w13, v0.h[5] ; ALL-NEXT: umov w13, v1.h[5]
; ALL-NEXT: mov v2.h[3], w11 ; ALL-NEXT: mov v2.h[3], w11
; ALL-NEXT: umov w11, v0.h[7] ; ALL-NEXT: udiv w13, w14, w13
; ALL-NEXT: udiv w8, w13, w9 ; ALL-NEXT: umov w14, v1.h[6]
; ALL-NEXT: umov w9, v1.h[6]
; ALL-NEXT: mov v2.h[4], w12 ; ALL-NEXT: mov v2.h[4], w12
; ALL-NEXT: udiv w9, w10, w9 ; ALL-NEXT: udiv w9, w15, w14
; ALL-NEXT: umov w10, v1.h[7] ; ALL-NEXT: mov v2.h[5], w13
; ALL-NEXT: mov v2.h[5], w8 ; ALL-NEXT: udiv w8, w10, w8
; ALL-NEXT: udiv w8, w11, w10
; ALL-NEXT: mov v2.h[6], w9 ; ALL-NEXT: mov v2.h[6], w9
; ALL-NEXT: mov v2.h[7], w8 ; ALL-NEXT: mov v2.h[7], w8
; ALL-NEXT: mls v0.8h, v2.8h, v1.8h ; ALL-NEXT: mls v0.8h, v2.8h, v1.8h
; ALL-NEXT: str q2, [x0] ; ALL-NEXT: str q2, [x0]
; ALL-NEXT: ret ; ALL-NEXT: ret
%div = udiv <8 x i16> %x, %y %div = udiv <8 x i16> %x, %y
store <8 x i16> %div, <8 x i16>* %divdst, align 16 store <8 x i16> %div, <8 x i16>* %divdst, align 16
%t1 = mul <8 x i16> %div, %y %t1 = mul <8 x i16> %div, %y
%t2 = sub <8 x i16> %x, %t1 %t2 = sub <8 x i16> %x, %t1
ret <8 x i16> %t2 ret <8 x i16> %t2
} }
define <4 x i32> @vector_i128_i32(<4 x i32> %x, <4 x i32> %y, <4 x i32>* %divdst) nounwind { define <4 x i32> @vector_i128_i32(<4 x i32> %x, <4 x i32> %y, <4 x i32>* %divdst) nounwind {
; ALL-LABEL: vector_i128_i32: ; ALL-LABEL: vector_i128_i32:
; ALL: // %bb.0: ; ALL: // %bb.0:
; ALL-NEXT: mov w8, v1.s[1] ; ALL-NEXT: mov w8, v1.s[1]
; ALL-NEXT: mov w9, v0.s[1] ; ALL-NEXT: mov w9, v0.s[1]
; ALL-NEXT: fmov w10, s0 ; ALL-NEXT: fmov w10, s0
; ALL-NEXT: mov w11, v0.s[2] ; ALL-NEXT: mov w11, v0.s[2]
; ALL-NEXT: mov w12, v0.s[3]
; ALL-NEXT: udiv w8, w9, w8 ; ALL-NEXT: udiv w8, w9, w8
; ALL-NEXT: fmov w9, s1 ; ALL-NEXT: fmov w9, s1
; ALL-NEXT: mov w12, v0.s[3]
; ALL-NEXT: udiv w9, w10, w9 ; ALL-NEXT: udiv w9, w10, w9
; ALL-NEXT: mov w10, v1.s[2] ; ALL-NEXT: mov w10, v1.s[2]
; ALL-NEXT: udiv w10, w11, w10 ; ALL-NEXT: udiv w10, w11, w10
; ALL-NEXT: mov w11, v1.s[3] ; ALL-NEXT: mov w11, v1.s[3]
; ALL-NEXT: fmov s2, w9 ; ALL-NEXT: fmov s2, w9
; ALL-NEXT: mov v2.s[1], w8 ; ALL-NEXT: mov v2.s[1], w8
; ALL-NEXT: udiv w8, w12, w11 ; ALL-NEXT: udiv w11, w12, w11
; ALL-NEXT: mov v2.s[2], w10 ; ALL-NEXT: mov v2.s[2], w10
; ALL-NEXT: mov v2.s[3], w8 ; ALL-NEXT: mov v2.s[3], w11
; ALL-NEXT: mls v0.4s, v2.4s, v1.4s ; ALL-NEXT: mls v0.4s, v2.4s, v1.4s
; ALL-NEXT: str q2, [x0] ; ALL-NEXT: str q2, [x0]
; ALL-NEXT: ret ; ALL-NEXT: ret
%div = udiv <4 x i32> %x, %y %div = udiv <4 x i32> %x, %y
store <4 x i32> %div, <4 x i32>* %divdst, align 16 store <4 x i32> %div, <4 x i32>* %divdst, align 16
%t1 = mul <4 x i32> %div, %y %t1 = mul <4 x i32> %div, %y
%t2 = sub <4 x i32> %x, %t1 %t2 = sub <4 x i32> %x, %t1
ret <4 x i32> %t2 ret <4 x i32> %t2
} }
define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64>* %divdst) nounwind { define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y, <2 x i64>* %divdst) nounwind {
; ALL-LABEL: vector_i128_i64: ; ALL-LABEL: vector_i128_i64:
; ALL: // %bb.0: ; ALL: // %bb.0:
; ALL-NEXT: fmov x8, d1 ; ALL-NEXT: fmov x8, d1
; ALL-NEXT: fmov x9, d0 ; ALL-NEXT: fmov x9, d0
; ALL-NEXT: mov x10, v1.d[1] ; ALL-NEXT: mov x10, v1.d[1]
; ALL-NEXT: mov x11, v0.d[1] ; ALL-NEXT: mov x11, v0.d[1]
; ALL-NEXT: udiv x9, x9, x8 ; ALL-NEXT: udiv x9, x9, x8
; ALL-NEXT: mul x8, x9, x8 ; ALL-NEXT: mul x8, x9, x8
; ALL-NEXT: udiv x11, x11, x10 ; ALL-NEXT: udiv x11, x11, x10
; ALL-NEXT: fmov d2, x9
; ALL-NEXT: fmov d1, x8 ; ALL-NEXT: fmov d1, x8
; ALL-NEXT: mul x10, x11, x10 ; ALL-NEXT: mul x10, x11, x10
; ALL-NEXT: mov v2.d[1], x11
; ALL-NEXT: mov v1.d[1], x10 ; ALL-NEXT: mov v1.d[1], x10
; ALL-NEXT: str q2, [x0]
; ALL-NEXT: sub v0.2d, v0.2d, v1.2d ; ALL-NEXT: sub v0.2d, v0.2d, v1.2d
; ALL-NEXT: fmov d1, x9
; ALL-NEXT: mov v1.d[1], x11
; ALL-NEXT: str q1, [x0]
; ALL-NEXT: ret ; ALL-NEXT: ret
%div = udiv <2 x i64> %x, %y %div = udiv <2 x i64> %x, %y
store <2 x i64> %div, <2 x i64>* %divdst, align 16 store <2 x i64> %div, <2 x i64>* %divdst, align 16
%t1 = mul <2 x i64> %div, %y %t1 = mul <2 x i64> %div, %y
%t2 = sub <2 x i64> %x, %t1 %t2 = sub <2 x i64> %x, %t1
ret <2 x i64> %t2 ret <2 x i64> %t2
} }
▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/expand-vector-rot.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-linux-android | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-linux-android | FileCheck %s
declare <2 x i16> @llvm.fshl.v2i16(<2 x i16>, <2 x i16>, <2 x i16>) declare <2 x i16> @llvm.fshl.v2i16(<2 x i16>, <2 x i16>, <2 x i16>)
define <2 x i16> @rotlv2_16(<2 x i16> %vec2_16, <2 x i16> %shift) { define <2 x i16> @rotlv2_16(<2 x i16> %vec2_16, <2 x i16> %shift) {
; CHECK-LABEL: rotlv2_16: ; CHECK-LABEL: rotlv2_16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.2s, #15 ; CHECK-NEXT: neg v2.2s, v1.2s
; CHECK-NEXT: movi d3, #0x00ffff0000ffff ; CHECK-NEXT: movi v3.2s, #15
; CHECK-NEXT: neg v4.2s, v1.2s ; CHECK-NEXT: movi d4, #0x00ffff0000ffff
; CHECK-NEXT: and v4.8b, v4.8b, v2.8b ; CHECK-NEXT: and v1.8b, v1.8b, v3.8b
; CHECK-NEXT: and v3.8b, v0.8b, v3.8b ; CHECK-NEXT: and v2.8b, v2.8b, v3.8b
; CHECK-NEXT: neg v4.2s, v4.2s ; CHECK-NEXT: and v4.8b, v0.8b, v4.8b
; CHECK-NEXT: and v1.8b, v1.8b, v2.8b ; CHECK-NEXT: neg v2.2s, v2.2s
; CHECK-NEXT: ushl v0.2s, v0.2s, v1.2s ; CHECK-NEXT: ushl v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ushl v2.2s, v3.2s, v4.2s ; CHECK-NEXT: ushl v2.2s, v4.2s, v2.2s
; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b ; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %vec2_16, <2 x i16> %vec2_16, <2 x i16> %shift) %1 = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %vec2_16, <2 x i16> %vec2_16, <2 x i16> %shift)
ret <2 x i16> %1 ret <2 x i16> %1
} }

llvm/test/CodeGen/AArch64/fcvt_combine.ll

Show First 20 Lines • Show All 174 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%scale = fmul <3 x float> %in, <float 4.0, float 4.0, float 4.0> %scale = fmul <3 x float> %in, <float 4.0, float 4.0, float 4.0>
%val = fptosi <3 x float> %scale to <3 x i32> %val = fptosi <3 x float> %scale to <3 x i32>
ret <3 x i32> %val ret <3 x i32> %val
} }
define <8 x i16> @test_v8f16(<8 x half> %in) { define <8 x i16> @test_v8f16(<8 x half> %in) {
; CHECK-NO16-LABEL: test_v8f16: ; CHECK-NO16-LABEL: test_v8f16:
; CHECK-NO16: // %bb.0: ; CHECK-NO16: // %bb.0:
; CHECK-NO16-NEXT: mov h2, v0.h[4] ; CHECK-NO16-NEXT: mov h2, v0.h[1]
; CHECK-NO16-NEXT: mov h3, v0.h[5] ; CHECK-NO16-NEXT: mov h3, v0.h[4]
; CHECK-NO16-NEXT: mov h4, v0.h[1] ; CHECK-NO16-NEXT: mov h4, v0.h[5]
; CHECK-NO16-NEXT: mov h5, v0.h[2] ; CHECK-NO16-NEXT: mov h6, v0.h[2]
; CHECK-NO16-NEXT: mov h6, v0.h[6] ; CHECK-NO16-NEXT: mov h16, v0.h[6]
; CHECK-NO16-NEXT: mov h5, v0.h[3]
; CHECK-NO16-NEXT: fcvt s7, h0 ; CHECK-NO16-NEXT: fcvt s7, h0
; CHECK-NO16-NEXT: fmov s1, #4.00000000 ; CHECK-NO16-NEXT: mov h0, v0.h[7]
; CHECK-NO16-NEXT: mov h16, v0.h[3]
; CHECK-NO16-NEXT: fcvt s2, h2 ; CHECK-NO16-NEXT: fcvt s2, h2
; CHECK-NO16-NEXT: fcvt s3, h3 ; CHECK-NO16-NEXT: fcvt s3, h3
; CHECK-NO16-NEXT: fcvt s4, h4 ; CHECK-NO16-NEXT: fcvt s4, h4
; CHECK-NO16-NEXT: mov h0, v0.h[7] ; CHECK-NO16-NEXT: fmov s1, #4.00000000
; CHECK-NO16-NEXT: fcvt s5, h5
; CHECK-NO16-NEXT: fcvt s6, h6 ; CHECK-NO16-NEXT: fcvt s6, h6
; CHECK-NO16-NEXT: fmul s7, s7, s1
; CHECK-NO16-NEXT: fcvt s16, h16 ; CHECK-NO16-NEXT: fcvt s16, h16
; CHECK-NO16-NEXT: fcvt s5, h5
; CHECK-NO16-NEXT: fcvt s0, h0
; CHECK-NO16-NEXT: fmul s7, s7, s1
; CHECK-NO16-NEXT: fmul s2, s2, s1 ; CHECK-NO16-NEXT: fmul s2, s2, s1
; CHECK-NO16-NEXT: fmul s3, s3, s1 ; CHECK-NO16-NEXT: fmul s3, s3, s1
; CHECK-NO16-NEXT: fmul s4, s4, s1 ; CHECK-NO16-NEXT: fmul s4, s4, s1
; CHECK-NO16-NEXT: fcvt s0, h0
; CHECK-NO16-NEXT: fmul s5, s5, s1
; CHECK-NO16-NEXT: fmul s6, s6, s1 ; CHECK-NO16-NEXT: fmul s6, s6, s1
; CHECK-NO16-NEXT: fcvt h7, s7
; CHECK-NO16-NEXT: fmul s16, s16, s1 ; CHECK-NO16-NEXT: fmul s16, s16, s1
; CHECK-NO16-NEXT: fcvt h2, s2 ; CHECK-NO16-NEXT: fmul s5, s5, s1
; CHECK-NO16-NEXT: fcvt h3, s3
; CHECK-NO16-NEXT: fcvt h4, s4
; CHECK-NO16-NEXT: fmul s0, s0, s1 ; CHECK-NO16-NEXT: fmul s0, s0, s1
; CHECK-NO16-NEXT: fcvt h1, s5 ; CHECK-NO16-NEXT: fcvt h7, s7
; CHECK-NO16-NEXT: fcvt h5, s6 ; CHECK-NO16-NEXT: fcvt h1, s2
; CHECK-NO16-NEXT: mov v2.h[1], v3.h[0] ; CHECK-NO16-NEXT: fcvt h2, s3
; CHECK-NO16-NEXT: fcvt h3, s16 ; CHECK-NO16-NEXT: fcvt h3, s4
; CHECK-NO16-NEXT: mov v7.h[1], v4.h[0] ; CHECK-NO16-NEXT: fcvt h4, s6
; CHECK-NO16-NEXT: fcvt h6, s16
; CHECK-NO16-NEXT: fcvt h5, s5
; CHECK-NO16-NEXT: fcvt h0, s0 ; CHECK-NO16-NEXT: fcvt h0, s0
; CHECK-NO16-NEXT: mov v2.h[2], v5.h[0] ; CHECK-NO16-NEXT: mov v7.h[1], v1.h[0]
; CHECK-NO16-NEXT: mov v7.h[2], v1.h[0] ; CHECK-NO16-NEXT: mov v2.h[1], v3.h[0]
; CHECK-NO16-NEXT: mov v7.h[2], v4.h[0]
; CHECK-NO16-NEXT: mov v2.h[2], v6.h[0]
; CHECK-NO16-NEXT: mov v7.h[3], v5.h[0]
; CHECK-NO16-NEXT: mov v2.h[3], v0.h[0] ; CHECK-NO16-NEXT: mov v2.h[3], v0.h[0]
; CHECK-NO16-NEXT: mov v7.h[3], v3.h[0]
; CHECK-NO16-NEXT: fcvtl v0.4s, v2.4h
; CHECK-NO16-NEXT: fcvtl v1.4s, v7.4h ; CHECK-NO16-NEXT: fcvtl v1.4s, v7.4h
; CHECK-NO16-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NO16-NEXT: fcvtl v0.4s, v2.4h
; CHECK-NO16-NEXT: fcvtzs v1.4s, v1.4s ; CHECK-NO16-NEXT: fcvtzs v1.4s, v1.4s
; CHECK-NO16-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NO16-NEXT: uzp1 v0.8h, v1.8h, v0.8h ; CHECK-NO16-NEXT: uzp1 v0.8h, v1.8h, v0.8h
; CHECK-NO16-NEXT: ret ; CHECK-NO16-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_v8f16: ; CHECK-FP16-LABEL: test_v8f16:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h, #2 ; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h, #2
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%scale = fmul <8 x half> %in, <half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0> %scale = fmul <8 x half> %in, <half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0>
%val = fptosi <8 x half> %scale to <8 x i16> %val = fptosi <8 x half> %scale to <8 x i16>
ret <8 x i16> %val ret <8 x i16> %val
} }
define <4 x i16> @test_v4f16(<4 x half> %in) { define <4 x i16> @test_v4f16(<4 x half> %in) {
; CHECK-NO16-LABEL: test_v4f16: ; CHECK-NO16-LABEL: test_v4f16:
; CHECK-NO16: // %bb.0: ; CHECK-NO16: // %bb.0:
; CHECK-NO16-NEXT: fmov v1.4s, #4.00000000
; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h ; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NO16-NEXT: fmov v1.4s, #4.00000000
; CHECK-NO16-NEXT: fmul v0.4s, v0.4s, v1.4s ; CHECK-NO16-NEXT: fmul v0.4s, v0.4s, v1.4s
; CHECK-NO16-NEXT: fcvtn v0.4h, v0.4s ; CHECK-NO16-NEXT: fcvtn v0.4h, v0.4s
; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h ; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NO16-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NO16-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NO16-NEXT: xtn v0.4h, v0.4s ; CHECK-NO16-NEXT: xtn v0.4h, v0.4s
; CHECK-NO16-NEXT: ret ; CHECK-NO16-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_v4f16: ; CHECK-FP16-LABEL: test_v4f16:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzu v0.4h, v0.4h, #2 ; CHECK-FP16-NEXT: fcvtzu v0.4h, v0.4h, #2
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%scale = fmul <4 x half> %in, <half 4.0, half 4.0, half 4.0, half 4.0> %scale = fmul <4 x half> %in, <half 4.0, half 4.0, half 4.0, half 4.0>
%val = fptoui <4 x half> %scale to <4 x i16> %val = fptoui <4 x half> %scale to <4 x i16>
ret <4 x i16> %val ret <4 x i16> %val
} }
define <4 x i32> @test_v4f16_i32(<4 x half> %in) { define <4 x i32> @test_v4f16_i32(<4 x half> %in) {
; CHECK-NO16-LABEL: test_v4f16_i32: ; CHECK-NO16-LABEL: test_v4f16_i32:
; CHECK-NO16: // %bb.0: ; CHECK-NO16: // %bb.0:
; CHECK-NO16-NEXT: fmov v1.4s, #4.00000000
; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h ; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NO16-NEXT: fmov v1.4s, #4.00000000
; CHECK-NO16-NEXT: fmul v0.4s, v0.4s, v1.4s ; CHECK-NO16-NEXT: fmul v0.4s, v0.4s, v1.4s
; CHECK-NO16-NEXT: fcvtn v0.4h, v0.4s ; CHECK-NO16-NEXT: fcvtn v0.4h, v0.4s
; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h ; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NO16-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NO16-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NO16-NEXT: ret ; CHECK-NO16-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_v4f16_i32: ; CHECK-FP16-LABEL: test_v4f16_i32:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
▲ Show 20 Lines • Show All 200 Lines • ▼ Show 20 Lines
} }
define <8 x i16> @test_v8f16_sat(<8 x half> %in) { define <8 x i16> @test_v8f16_sat(<8 x half> %in) {
; CHECK-NO16-LABEL: test_v8f16_sat: ; CHECK-NO16-LABEL: test_v8f16_sat:
; CHECK-NO16: // %bb.0: ; CHECK-NO16: // %bb.0:
; CHECK-NO16-NEXT: mov h2, v0.h[4] ; CHECK-NO16-NEXT: mov h2, v0.h[4]
; CHECK-NO16-NEXT: mov h3, v0.h[5] ; CHECK-NO16-NEXT: mov h3, v0.h[5]
; CHECK-NO16-NEXT: mov h4, v0.h[6] ; CHECK-NO16-NEXT: mov h4, v0.h[6]
; CHECK-NO16-NEXT: fmov s1, #4.00000000
; CHECK-NO16-NEXT: mov h5, v0.h[7] ; CHECK-NO16-NEXT: mov h5, v0.h[7]
; CHECK-NO16-NEXT: fmov s1, #4.00000000
; CHECK-NO16-NEXT: mov h6, v0.h[1] ; CHECK-NO16-NEXT: mov h6, v0.h[1]
; CHECK-NO16-NEXT: mov h7, v0.h[2] ; CHECK-NO16-NEXT: mov h7, v0.h[2]
; CHECK-NO16-NEXT: fcvt s16, h0 ; CHECK-NO16-NEXT: mov h16, v0.h[3]
; CHECK-NO16-NEXT: fcvt s2, h2 ; CHECK-NO16-NEXT: fcvt s2, h2
; CHECK-NO16-NEXT: fcvt s3, h3 ; CHECK-NO16-NEXT: fcvt s3, h3
; CHECK-NO16-NEXT: fcvt s4, h4 ; CHECK-NO16-NEXT: fcvt s4, h4
; CHECK-NO16-NEXT: mov h0, v0.h[3]
; CHECK-NO16-NEXT: fcvt s5, h5 ; CHECK-NO16-NEXT: fcvt s5, h5
; CHECK-NO16-NEXT: fcvt s0, h0
; CHECK-NO16-NEXT: fcvt s6, h6 ; CHECK-NO16-NEXT: fcvt s6, h6
; CHECK-NO16-NEXT: fcvt s7, h7
; CHECK-NO16-NEXT: mov w9, #32767 ; CHECK-NO16-NEXT: mov w9, #32767
; CHECK-NO16-NEXT: mov w10, #-32768
; CHECK-NO16-NEXT: fmul s2, s2, s1 ; CHECK-NO16-NEXT: fmul s2, s2, s1
; CHECK-NO16-NEXT: fmul s3, s3, s1 ; CHECK-NO16-NEXT: fmul s3, s3, s1
; CHECK-NO16-NEXT: fmul s4, s4, s1 ; CHECK-NO16-NEXT: fmul s4, s4, s1
; CHECK-NO16-NEXT: fcvt s0, h0
; CHECK-NO16-NEXT: fmul s5, s5, s1 ; CHECK-NO16-NEXT: fmul s5, s5, s1
; CHECK-NO16-NEXT: fmul s0, s0, s1
; CHECK-NO16-NEXT: fmul s6, s6, s1 ; CHECK-NO16-NEXT: fmul s6, s6, s1
; CHECK-NO16-NEXT: mov w10, #-32768
; CHECK-NO16-NEXT: fcvt h2, s2 ; CHECK-NO16-NEXT: fcvt h2, s2
; CHECK-NO16-NEXT: fcvt h3, s3 ; CHECK-NO16-NEXT: fcvt h3, s3
; CHECK-NO16-NEXT: fmul s0, s0, s1 ; CHECK-NO16-NEXT: fcvt h4, s4
; CHECK-NO16-NEXT: fcvt h5, s5 ; CHECK-NO16-NEXT: fcvt h5, s5
; CHECK-NO16-NEXT: fcvt h6, s6
; CHECK-NO16-NEXT: mov v2.h[1], v3.h[0]
; CHECK-NO16-NEXT: fcvt h3, s4
; CHECK-NO16-NEXT: fcvt s4, h7
; CHECK-NO16-NEXT: fmul s7, s16, s1
; CHECK-NO16-NEXT: fcvt h0, s0 ; CHECK-NO16-NEXT: fcvt h0, s0
; CHECK-NO16-NEXT: mov v2.h[2], v3.h[0] ; CHECK-NO16-NEXT: mov v2.h[1], v3.h[0]
; CHECK-NO16-NEXT: fmul s3, s4, s1 ; CHECK-NO16-NEXT: fcvt s3, h16
; CHECK-NO16-NEXT: fcvt h4, s7 ; CHECK-NO16-NEXT: mov v2.h[2], v4.h[0]
; CHECK-NO16-NEXT: fmul s4, s7, s1
; CHECK-NO16-NEXT: mov v2.h[3], v5.h[0] ; CHECK-NO16-NEXT: mov v2.h[3], v5.h[0]
; CHECK-NO16-NEXT: fcvt h1, s3 ; CHECK-NO16-NEXT: fmul s1, s3, s1
; CHECK-NO16-NEXT: mov v4.h[1], v6.h[0] ; CHECK-NO16-NEXT: fcvt h3, s6
; CHECK-NO16-NEXT: fcvtl v2.4s, v2.4h ; CHECK-NO16-NEXT: fcvtl v2.4s, v2.4h
; CHECK-NO16-NEXT: mov v4.h[2], v1.h[0] ; CHECK-NO16-NEXT: fcvt h4, s4
; CHECK-NO16-NEXT: mov s1, v2.s[1] ; CHECK-NO16-NEXT: fcvt h1, s1
; CHECK-NO16-NEXT: mov v0.h[1], v3.h[0]
; CHECK-NO16-NEXT: mov s3, v2.s[1]
; CHECK-NO16-NEXT: fcvtzs w11, s2 ; CHECK-NO16-NEXT: fcvtzs w11, s2
; CHECK-NO16-NEXT: mov v4.h[3], v0.h[0] ; CHECK-NO16-NEXT: mov v0.h[2], v4.h[0]
; CHECK-NO16-NEXT: mov s0, v2.s[2] ; CHECK-NO16-NEXT: mov v0.h[3], v1.h[0]
; CHECK-NO16-NEXT: mov s1, v2.s[2]
; CHECK-NO16-NEXT: fcvtzs w8, s3
; CHECK-NO16-NEXT: mov s2, v2.s[3] ; CHECK-NO16-NEXT: mov s2, v2.s[3]
; CHECK-NO16-NEXT: fcvtzs w8, s1 ; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NO16-NEXT: fcvtl v1.4s, v4.4h
; CHECK-NO16-NEXT: fcvtzs w12, s0
; CHECK-NO16-NEXT: cmp w8, w9 ; CHECK-NO16-NEXT: cmp w8, w9
; CHECK-NO16-NEXT: fcvtzs w13, s2 ; CHECK-NO16-NEXT: fcvtzs w12, s1
; CHECK-NO16-NEXT: csel w8, w8, w9, lt ; CHECK-NO16-NEXT: csel w8, w8, w9, lt
; CHECK-NO16-NEXT: fcvtzs w13, s2
; CHECK-NO16-NEXT: cmn w8, #8, lsl #12 // =32768 ; CHECK-NO16-NEXT: cmn w8, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: mov s1, v0.s[1]
; CHECK-NO16-NEXT: csel w8, w8, w10, gt ; CHECK-NO16-NEXT: csel w8, w8, w10, gt
; CHECK-NO16-NEXT: cmp w11, w9 ; CHECK-NO16-NEXT: cmp w11, w9
; CHECK-NO16-NEXT: csel w11, w11, w9, lt ; CHECK-NO16-NEXT: csel w11, w11, w9, lt
; CHECK-NO16-NEXT: mov s0, v1.s[1] ; CHECK-NO16-NEXT: fcvtzs w15, s0
; CHECK-NO16-NEXT: cmn w11, #8, lsl #12 // =32768 ; CHECK-NO16-NEXT: cmn w11, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: fcvtzs w15, s1
; CHECK-NO16-NEXT: csel w11, w11, w10, gt ; CHECK-NO16-NEXT: csel w11, w11, w10, gt
; CHECK-NO16-NEXT: cmp w12, w9 ; CHECK-NO16-NEXT: cmp w12, w9
; CHECK-NO16-NEXT: csel w12, w12, w9, lt ; CHECK-NO16-NEXT: csel w12, w12, w9, lt
; CHECK-NO16-NEXT: fcvtzs w14, s1
; CHECK-NO16-NEXT: cmn w12, #8, lsl #12 // =32768 ; CHECK-NO16-NEXT: cmn w12, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: fcvtzs w14, s0 ; CHECK-NO16-NEXT: mov s1, v0.s[2]
; CHECK-NO16-NEXT: csel w12, w12, w10, gt ; CHECK-NO16-NEXT: csel w12, w12, w10, gt
; CHECK-NO16-NEXT: cmp w13, w9 ; CHECK-NO16-NEXT: cmp w13, w9
; CHECK-NO16-NEXT: csel w13, w13, w9, lt ; CHECK-NO16-NEXT: csel w13, w13, w9, lt
; CHECK-NO16-NEXT: mov s0, v1.s[2] ; CHECK-NO16-NEXT: mov s0, v0.s[3]
; CHECK-NO16-NEXT: cmn w13, #8, lsl #12 // =32768 ; CHECK-NO16-NEXT: cmn w13, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: fmov s2, w11
; CHECK-NO16-NEXT: csel w13, w13, w10, gt ; CHECK-NO16-NEXT: csel w13, w13, w10, gt
; CHECK-NO16-NEXT: cmp w14, w9 ; CHECK-NO16-NEXT: cmp w14, w9
; CHECK-NO16-NEXT: csel w14, w14, w9, lt ; CHECK-NO16-NEXT: csel w14, w14, w9, lt
; CHECK-NO16-NEXT: fcvtzs w16, s1
; CHECK-NO16-NEXT: cmn w14, #8, lsl #12 // =32768 ; CHECK-NO16-NEXT: cmn w14, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: fcvtzs w17, s0
; CHECK-NO16-NEXT: csel w14, w14, w10, gt ; CHECK-NO16-NEXT: csel w14, w14, w10, gt
; CHECK-NO16-NEXT: cmp w15, w9 ; CHECK-NO16-NEXT: cmp w15, w9
; CHECK-NO16-NEXT: csel w15, w15, w9, lt ; CHECK-NO16-NEXT: csel w15, w15, w9, lt
; CHECK-NO16-NEXT: fmov s0, w11
; CHECK-NO16-NEXT: cmn w15, #8, lsl #12 // =32768 ; CHECK-NO16-NEXT: cmn w15, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: csel w11, w15, w10, gt ; CHECK-NO16-NEXT: csel w15, w15, w10, gt
; CHECK-NO16-NEXT: fcvtzs w15, s0 ; CHECK-NO16-NEXT: cmp w16, w9
; CHECK-NO16-NEXT: mov s0, v1.s[3] ; CHECK-NO16-NEXT: csel w11, w16, w9, lt
; CHECK-NO16-NEXT: mov v2.s[1], w8 ; CHECK-NO16-NEXT: mov v0.s[1], w8
; CHECK-NO16-NEXT: fmov s1, w11 ; CHECK-NO16-NEXT: cmn w11, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: cmp w15, w9 ; CHECK-NO16-NEXT: fmov s1, w15
; CHECK-NO16-NEXT: csel w8, w15, w9, lt ; CHECK-NO16-NEXT: csel w11, w11, w10, gt
; CHECK-NO16-NEXT: fcvtzs w11, s0 ; CHECK-NO16-NEXT: cmp w17, w9
; CHECK-NO16-NEXT: cmn w8, #8, lsl #12 // =32768 ; CHECK-NO16-NEXT: mov v0.s[2], w12
; CHECK-NO16-NEXT: csel w8, w17, w9, lt
; CHECK-NO16-NEXT: mov v1.s[1], w14 ; CHECK-NO16-NEXT: mov v1.s[1], w14
; CHECK-NO16-NEXT: cmn w8, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: csel w8, w8, w10, gt ; CHECK-NO16-NEXT: csel w8, w8, w10, gt
; CHECK-NO16-NEXT: mov v2.s[2], w12 ; CHECK-NO16-NEXT: mov v0.s[3], w13
; CHECK-NO16-NEXT: cmp w11, w9 ; CHECK-NO16-NEXT: mov v1.s[2], w11
; CHECK-NO16-NEXT: csel w9, w11, w9, lt
; CHECK-NO16-NEXT: mov v1.s[2], w8
; CHECK-NO16-NEXT: cmn w9, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: csel w8, w9, w10, gt
; CHECK-NO16-NEXT: mov v2.s[3], w13
; CHECK-NO16-NEXT: mov v1.s[3], w8 ; CHECK-NO16-NEXT: mov v1.s[3], w8
; CHECK-NO16-NEXT: uzp1 v0.8h, v1.8h, v2.8h ; CHECK-NO16-NEXT: uzp1 v0.8h, v1.8h, v0.8h
; CHECK-NO16-NEXT: ret ; CHECK-NO16-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_v8f16_sat: ; CHECK-FP16-LABEL: test_v8f16_sat:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h, #2 ; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h, #2
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%mul.i = fmul <8 x half> %in, <half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0> %mul.i = fmul <8 x half> %in, <half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0>
%val = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %mul.i) %val = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %mul.i)
ret <8 x i16> %val ret <8 x i16> %val
} }
define <4 x i16> @test_v4f16_sat(<4 x half> %in) { define <4 x i16> @test_v4f16_sat(<4 x half> %in) {
; CHECK-NO16-LABEL: test_v4f16_sat: ; CHECK-NO16-LABEL: test_v4f16_sat:
; CHECK-NO16: // %bb.0: ; CHECK-NO16: // %bb.0:
; CHECK-NO16-NEXT: fmov v1.4s, #4.00000000
; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h ; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NO16-NEXT: fmov v1.4s, #4.00000000
; CHECK-NO16-NEXT: fmul v0.4s, v0.4s, v1.4s ; CHECK-NO16-NEXT: fmul v0.4s, v0.4s, v1.4s
; CHECK-NO16-NEXT: fcvtn v0.4h, v0.4s ; CHECK-NO16-NEXT: fcvtn v0.4h, v0.4s
; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h ; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NO16-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NO16-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NO16-NEXT: uqxtn v0.4h, v0.4s ; CHECK-NO16-NEXT: uqxtn v0.4h, v0.4s
; CHECK-NO16-NEXT: ret ; CHECK-NO16-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_v4f16_sat: ; CHECK-FP16-LABEL: test_v4f16_sat:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzu v0.4h, v0.4h, #2 ; CHECK-FP16-NEXT: fcvtzu v0.4h, v0.4h, #2
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%mul.i = fmul <4 x half> %in, <half 4.0, half 4.0, half 4.0, half 4.0> %mul.i = fmul <4 x half> %in, <half 4.0, half 4.0, half 4.0, half 4.0>
%val = call <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half> %mul.i) %val = call <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half> %mul.i)
ret <4 x i16> %val ret <4 x i16> %val
} }
define <4 x i32> @test_v4f16_i32_sat(<4 x half> %in) { define <4 x i32> @test_v4f16_i32_sat(<4 x half> %in) {
; CHECK-NO16-LABEL: test_v4f16_i32_sat: ; CHECK-NO16-LABEL: test_v4f16_i32_sat:
; CHECK-NO16: // %bb.0: ; CHECK-NO16: // %bb.0:
; CHECK-NO16-NEXT: fmov v1.4s, #4.00000000
; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h ; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NO16-NEXT: fmov v1.4s, #4.00000000
; CHECK-NO16-NEXT: fmul v0.4s, v0.4s, v1.4s ; CHECK-NO16-NEXT: fmul v0.4s, v0.4s, v1.4s
; CHECK-NO16-NEXT: fcvtn v0.4h, v0.4s ; CHECK-NO16-NEXT: fcvtn v0.4h, v0.4s
; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h ; CHECK-NO16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NO16-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NO16-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NO16-NEXT: ret ; CHECK-NO16-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_v4f16_i32_sat: ; CHECK-FP16-LABEL: test_v4f16_i32_sat:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: movi v1.4h, #68, lsl #8 ; CHECK-FP16-NEXT: movi v1.4h, #68, lsl #8
; CHECK-FP16-NEXT: fmul v0.4h, v0.4h, v1.4h ; CHECK-FP16-NEXT: fmul v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT: fcvtl v0.4s, v0.4h ; CHECK-FP16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-FP16-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-FP16-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%mul.i = fmul <4 x half> %in, <half 4.0, half 4.0, half 4.0, half 4.0> %mul.i = fmul <4 x half> %in, <half 4.0, half 4.0, half 4.0, half 4.0>
%val = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f16(<4 x half> %mul.i) %val = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f16(<4 x half> %mul.i)
ret <4 x i32> %val ret <4 x i32> %val
} }
define <4 x i32> @test_extrasat(<4 x float> %f) { define <4 x i32> @test_extrasat(<4 x float> %f) {
; CHECK-LABEL: test_extrasat: ; CHECK-LABEL: test_extrasat:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0xffffff00ffffff
; CHECK-NEXT: fcvtzu v0.4s, v0.4s, #3 ; CHECK-NEXT: fcvtzu v0.4s, v0.4s, #3
; CHECK-NEXT: movi v1.2d, #0xffffff00ffffff
; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s ; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mul.i = fmul <4 x float> %f, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00> %mul.i = fmul <4 x float> %f, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
%vcvt.i = call <4 x i24> @llvm.fptoui.sat.v4i24.v4f32(<4 x float> %mul.i) %vcvt.i = call <4 x i24> @llvm.fptoui.sat.v4i24.v4f32(<4 x float> %mul.i)
%t = zext <4 x i24> %vcvt.i to <4 x i32> %t = zext <4 x i24> %vcvt.i to <4 x i32>
ret <4 x i32> %t ret <4 x i32> %t
} }

llvm/test/CodeGen/AArch64/fdiv-combine.ll

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines; CHECK-NEXT: b foo_2d
%div1 = fdiv double %b, %D %div1 = fdiv double %b, %D
tail call void @foo_2d(double %div, double %div1) tail call void @foo_2d(double %div, double %div1)
ret void ret void
} }
define void @splat_three_fdiv_4xfloat(float %D, <4 x float> %a, <4 x float> %b, <4 x float> %c) #0 { define void @splat_three_fdiv_4xfloat(float %D, <4 x float> %a, <4 x float> %b, <4 x float> %c) #0 {
; CHECK-LABEL: splat_three_fdiv_4xfloat: ; CHECK-LABEL: splat_three_fdiv_4xfloat:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fmov v4.4s, #1.00000000
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: fmov v4.4s, #1.00000000
; CHECK-NEXT: dup v0.4s, v0.s[0] ; CHECK-NEXT: dup v0.4s, v0.s[0]
; CHECK-NEXT: fdiv v4.4s, v4.4s, v0.4s ; CHECK-NEXT: fdiv v4.4s, v4.4s, v0.4s
; CHECK-NEXT: fmul v0.4s, v1.4s, v4.4s ; CHECK-NEXT: fmul v0.4s, v1.4s, v4.4s
; CHECK-NEXT: fmul v1.4s, v2.4s, v4.4s ; CHECK-NEXT: fmul v1.4s, v2.4s, v4.4s
; CHECK-NEXT: fmul v2.4s, v3.4s, v4.4s ; CHECK-NEXT: fmul v2.4s, v3.4s, v4.4s
; CHECK-NEXT: b foo_3_4xf ; CHECK-NEXT: b foo_3_4xf
%D.ins = insertelement <4 x float> poison, float %D, i64 0 %D.ins = insertelement <4 x float> poison, float %D, i64 0
%splat = shufflevector <4 x float> %D.ins, <4 x float> poison, <4 x i32> zeroinitializer %splat = shufflevector <4 x float> %D.ins, <4 x float> poison, <4 x i32> zeroinitializer
%div = fdiv <4 x float> %a, %splat %div = fdiv <4 x float> %a, %splat
%div1 = fdiv <4 x float> %b, %splat %div1 = fdiv <4 x float> %b, %splat
%div2 = fdiv <4 x float> %c, %splat %div2 = fdiv <4 x float> %c, %splat
tail call void @foo_3_4xf(<4 x float> %div, <4 x float> %div1, <4 x float> %div2) tail call void @foo_3_4xf(<4 x float> %div, <4 x float> %div1, <4 x float> %div2)
ret void ret void
} }
define <4 x float> @splat_fdiv_v4f32(float %D, <4 x float> %a) #1 { define <4 x float> @splat_fdiv_v4f32(float %D, <4 x float> %a) #1 {
; CHECK-LABEL: splat_fdiv_v4f32: ; CHECK-LABEL: splat_fdiv_v4f32:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov v2.4s, #1.00000000
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: fmov v2.4s, #1.00000000
; CHECK-NEXT: dup v0.4s, v0.s[0] ; CHECK-NEXT: dup v0.4s, v0.s[0]
; CHECK-NEXT: fdiv v0.4s, v2.4s, v0.4s ; CHECK-NEXT: fdiv v0.4s, v2.4s, v0.4s
; CHECK-NEXT: fmul v0.4s, v1.4s, v0.4s ; CHECK-NEXT: fmul v0.4s, v1.4s, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%D.ins = insertelement <4 x float> poison, float %D, i64 0 %D.ins = insertelement <4 x float> poison, float %D, i64 0
%splat = shufflevector <4 x float> %D.ins, <4 x float> poison, <4 x i32> zeroinitializer %splat = shufflevector <4 x float> %D.ins, <4 x float> poison, <4 x i32> zeroinitializer
%div = fdiv <4 x float> %a, %splat %div = fdiv <4 x float> %a, %splat
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llvm/test/CodeGen/AArch64/fdiv_combine.ll

Show All 23 Linesentry:
%div.i = fdiv <2 x float> %vcvt.i, <float 8.0, float 8.0> %div.i = fdiv <2 x float> %vcvt.i, <float 8.0, float 8.0>
ret <2 x float> %div.i ret <2 x float> %div.i
} }
; Test which should not fold due to non-power of 2. ; Test which should not fold due to non-power of 2.
define <2 x float> @test3(<2 x i32> %in) { define <2 x float> @test3(<2 x i32> %in) {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov.2s v1, #9.00000000
; CHECK-NEXT: scvtf.2s v0, v0 ; CHECK-NEXT: scvtf.2s v0, v0
; CHECK-NEXT: fmov.2s v1, #9.00000000
; CHECK-NEXT: fdiv.2s v0, v0, v1 ; CHECK-NEXT: fdiv.2s v0, v0, v1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vcvt.i = sitofp <2 x i32> %in to <2 x float> %vcvt.i = sitofp <2 x i32> %in to <2 x float>
%div.i = fdiv <2 x float> %vcvt.i, <float 9.0, float 9.0> %div.i = fdiv <2 x float> %vcvt.i, <float 9.0, float 9.0>
ret <2 x float> %div.i ret <2 x float> %div.i
} }
; Test which should not fold due to power of 2 out of range. ; Test which should not fold due to power of 2 out of range.
define <2 x float> @test4(<2 x i32> %in) { define <2 x float> @test4(<2 x i32> %in) {
; CHECK-LABEL: test4: ; CHECK-LABEL: test4:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi.2s v1, #80, lsl #24
; CHECK-NEXT: scvtf.2s v0, v0 ; CHECK-NEXT: scvtf.2s v0, v0
; CHECK-NEXT: movi.2s v1, #80, lsl #24
; CHECK-NEXT: fdiv.2s v0, v0, v1 ; CHECK-NEXT: fdiv.2s v0, v0, v1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vcvt.i = sitofp <2 x i32> %in to <2 x float> %vcvt.i = sitofp <2 x i32> %in to <2 x float>
%div.i = fdiv <2 x float> %vcvt.i, <float 0x4200000000000000, float 0x4200000000000000> %div.i = fdiv <2 x float> %vcvt.i, <float 0x4200000000000000, float 0x4200000000000000>
ret <2 x float> %div.i ret <2 x float> %div.i
} }
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llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll

Show First 20 Lines • Show All 235 Lines • ▼ Show 20 Lines
; CHECK-NEXT: mov s3, v0.s[1] ; CHECK-NEXT: mov s3, v0.s[1]
; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: fcmp s0, s1
; CHECK-NEXT: mov s4, v1.s[2] ; CHECK-NEXT: mov s4, v1.s[2]
; CHECK-NEXT: mov s5, v0.s[2] ; CHECK-NEXT: mov s5, v0.s[2]
; CHECK-NEXT: mov s1, v1.s[3] ; CHECK-NEXT: mov s1, v1.s[3]
; CHECK-NEXT: mov s0, v0.s[3] ; CHECK-NEXT: mov s0, v0.s[3]
; CHECK-NEXT: csetm w8, eq ; CHECK-NEXT: csetm w8, eq
; CHECK-NEXT: fcmp s3, s2 ; CHECK-NEXT: fcmp s3, s2
; CHECK-NEXT: fmov s2, w8 ; CHECK-NEXT: csetm w9, eq
; CHECK-NEXT: csetm w8, eq
; CHECK-NEXT: fcmp s5, s4 ; CHECK-NEXT: fcmp s5, s4
; CHECK-NEXT: mov v2.s[1], w8 ; CHECK-NEXT: fmov s2, w8
; CHECK-NEXT: csetm w8, eq ; CHECK-NEXT: csetm w8, eq
; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: fcmp s0, s1
; CHECK-NEXT: mov v2.s[1], w9
; CHECK-NEXT: csetm w9, eq
; CHECK-NEXT: mov v2.s[2], w8 ; CHECK-NEXT: mov v2.s[2], w8
; CHECK-NEXT: csetm w8, eq ; CHECK-NEXT: mov v2.s[3], w9
; CHECK-NEXT: mov v2.s[3], w8
; CHECK-NEXT: xtn v0.4h, v2.4s ; CHECK-NEXT: xtn v0.4h, v2.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%val = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x float> %x, <4 x float> %y, metadata !"oeq", metadata !"fpexcept.strict") %val = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x float> %x, <4 x float> %y, metadata !"oeq", metadata !"fpexcept.strict")
ret <4 x i1> %val ret <4 x i1> %val
} }
define <4 x i1> @fcmps_v4f32(<4 x float> %x, <4 x float> %y) #0 { define <4 x i1> @fcmps_v4f32(<4 x float> %x, <4 x float> %y) #0 {
; CHECK-LABEL: fcmps_v4f32: ; CHECK-LABEL: fcmps_v4f32:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov s2, v1.s[1] ; CHECK-NEXT: mov s2, v1.s[1]
; CHECK-NEXT: mov s3, v0.s[1] ; CHECK-NEXT: mov s3, v0.s[1]
; CHECK-NEXT: fcmpe s0, s1 ; CHECK-NEXT: fcmpe s0, s1
; CHECK-NEXT: mov s4, v1.s[2] ; CHECK-NEXT: mov s4, v1.s[2]
; CHECK-NEXT: mov s5, v0.s[2] ; CHECK-NEXT: mov s5, v0.s[2]
; CHECK-NEXT: mov s1, v1.s[3] ; CHECK-NEXT: mov s1, v1.s[3]
; CHECK-NEXT: mov s0, v0.s[3] ; CHECK-NEXT: mov s0, v0.s[3]
; CHECK-NEXT: csetm w8, eq ; CHECK-NEXT: csetm w8, eq
; CHECK-NEXT: fcmpe s3, s2 ; CHECK-NEXT: fcmpe s3, s2
; CHECK-NEXT: fmov s2, w8 ; CHECK-NEXT: csetm w9, eq
; CHECK-NEXT: csetm w8, eq
; CHECK-NEXT: fcmpe s5, s4 ; CHECK-NEXT: fcmpe s5, s4
; CHECK-NEXT: mov v2.s[1], w8 ; CHECK-NEXT: fmov s2, w8
; CHECK-NEXT: csetm w8, eq ; CHECK-NEXT: csetm w8, eq
; CHECK-NEXT: fcmpe s0, s1 ; CHECK-NEXT: fcmpe s0, s1
; CHECK-NEXT: mov v2.s[1], w9
; CHECK-NEXT: csetm w9, eq
; CHECK-NEXT: mov v2.s[2], w8 ; CHECK-NEXT: mov v2.s[2], w8
; CHECK-NEXT: csetm w8, eq ; CHECK-NEXT: mov v2.s[3], w9
; CHECK-NEXT: mov v2.s[3], w8
; CHECK-NEXT: xtn v0.4h, v2.4s ; CHECK-NEXT: xtn v0.4h, v2.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%val = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x float> %x, <4 x float> %y, metadata !"oeq", metadata !"fpexcept.strict") %val = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x float> %x, <4 x float> %y, metadata !"oeq", metadata !"fpexcept.strict")
ret <4 x i1> %val ret <4 x i1> %val
} }
▲ Show 20 Lines • Show All 598 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT ; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT
; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16 ; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
define <8 x half> @add_h(<8 x half> %a, <8 x half> %b) { define <8 x half> @add_h(<8 x half> %a, <8 x half> %b) {
; CHECK-CVT-LABEL: add_h: ; CHECK-CVT-LABEL: add_h:
; CHECK-CVT: // %bb.0: // %entry ; CHECK-CVT: // %bb.0: // %entry
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: fcvt s4, h1
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: fcvt s5, h0
; CHECK-CVT-NEXT: mov h6, v1.h[2] ; CHECK-CVT-NEXT: mov h6, v1.h[2]
; CHECK-CVT-NEXT: mov h7, v0.h[2] ; CHECK-CVT-NEXT: mov h7, v0.h[2]
; CHECK-CVT-NEXT: mov h16, v1.h[3] ; CHECK-CVT-NEXT: mov h16, v1.h[3]
; CHECK-CVT-NEXT: mov h17, v0.h[3] ; CHECK-CVT-NEXT: mov h17, v0.h[3]
; CHECK-CVT-NEXT: mov h18, v1.h[4]
; CHECK-CVT-NEXT: mov h19, v0.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s6, h6
; CHECK-CVT-NEXT: fcvt s7, h7
; CHECK-CVT-NEXT: mov h20, v1.h[5]
; CHECK-CVT-NEXT: fadd s4, s5, s4 ; CHECK-CVT-NEXT: fadd s4, s5, s4
; CHECK-CVT-NEXT: fcvt s5, h6 ; CHECK-CVT-NEXT: mov h5, v0.h[5]
; CHECK-CVT-NEXT: fcvt s6, h7 ; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcvt s7, h16 ; CHECK-CVT-NEXT: fcvt s17, h17
; CHECK-CVT-NEXT: fcvt s16, h17 ; CHECK-CVT-NEXT: fcvt s18, h18
; CHECK-CVT-NEXT: fadd s3, s3, s2 ; CHECK-CVT-NEXT: fcvt s19, h19
; CHECK-CVT-NEXT: fadd s2, s3, s2
; CHECK-CVT-NEXT: fadd s3, s7, s6
; CHECK-CVT-NEXT: fcvt s6, h20
; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fadd s7, s17, s16
; CHECK-CVT-NEXT: mov h16, v1.h[6]
; CHECK-CVT-NEXT: fadd s17, s19, s18
; CHECK-CVT-NEXT: mov h18, v0.h[6]
; CHECK-CVT-NEXT: fcvt h19, s2
; CHECK-CVT-NEXT: fcvt h2, s4 ; CHECK-CVT-NEXT: fcvt h2, s4
; CHECK-CVT-NEXT: fadd s4, s6, s5
; CHECK-CVT-NEXT: mov h5, v1.h[4]
; CHECK-CVT-NEXT: mov h6, v0.h[4]
; CHECK-CVT-NEXT: fadd s7, s16, s7
; CHECK-CVT-NEXT: fcvt h3, s3
; CHECK-CVT-NEXT: mov h16, v0.h[5]
; CHECK-CVT-NEXT: fcvt h7, s7
; CHECK-CVT-NEXT: mov v2.h[1], v3.h[0]
; CHECK-CVT-NEXT: fcvt h3, s4
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: mov h6, v1.h[5]
; CHECK-CVT-NEXT: mov v2.h[2], v3.h[0]
; CHECK-CVT-NEXT: fadd s3, s5, s4
; CHECK-CVT-NEXT: fcvt s4, h6
; CHECK-CVT-NEXT: fcvt s5, h16
; CHECK-CVT-NEXT: mov h6, v1.h[6]
; CHECK-CVT-NEXT: mov h16, v0.h[6]
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: mov v2.h[3], v7.h[0]
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: fadd s4, s5, s6
; CHECK-CVT-NEXT: fcvt h3, s3 ; CHECK-CVT-NEXT: fcvt h3, s3
; CHECK-CVT-NEXT: fadd s4, s5, s4 ; CHECK-CVT-NEXT: fcvt s5, h16
; CHECK-CVT-NEXT: fcvt s5, h6 ; CHECK-CVT-NEXT: fcvt s6, h18
; CHECK-CVT-NEXT: fcvt s6, h16 ; CHECK-CVT-NEXT: mov v2.h[1], v19.h[0]
; CHECK-CVT-NEXT: fcvt h7, s7
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v2.h[4], v3.h[0] ; CHECK-CVT-NEXT: mov v2.h[2], v3.h[0]
; CHECK-CVT-NEXT: fcvt h3, s4 ; CHECK-CVT-NEXT: fadd s3, s6, s5
; CHECK-CVT-NEXT: fadd s4, s6, s5 ; CHECK-CVT-NEXT: fcvt h5, s17
; CHECK-CVT-NEXT: mov v2.h[3], v7.h[0]
; CHECK-CVT-NEXT: fadd s0, s0, s1 ; CHECK-CVT-NEXT: fadd s0, s0, s1
; CHECK-CVT-NEXT: mov v2.h[5], v3.h[0] ; CHECK-CVT-NEXT: fcvt h1, s4
; CHECK-CVT-NEXT: fcvt h3, s4 ; CHECK-CVT-NEXT: mov v2.h[4], v5.h[0]
; CHECK-CVT-NEXT: fcvt h3, s3
; CHECK-CVT-NEXT: mov v2.h[5], v1.h[0]
; CHECK-CVT-NEXT: fcvt h0, s0 ; CHECK-CVT-NEXT: fcvt h0, s0
; CHECK-CVT-NEXT: mov v2.h[6], v3.h[0] ; CHECK-CVT-NEXT: mov v2.h[6], v3.h[0]
; CHECK-CVT-NEXT: mov v2.h[7], v0.h[0] ; CHECK-CVT-NEXT: mov v2.h[7], v0.h[0]
; CHECK-CVT-NEXT: mov v0.16b, v2.16b ; CHECK-CVT-NEXT: mov v0.16b, v2.16b
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: add_h: ; CHECK-FP16-LABEL: add_h:
; CHECK-FP16: // %bb.0: // %entry ; CHECK-FP16: // %bb.0: // %entry
Show All 11 Lines
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: fcvt s4, h1
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: fcvt s5, h0
; CHECK-CVT-NEXT: mov h6, v1.h[2] ; CHECK-CVT-NEXT: mov h6, v1.h[2]
; CHECK-CVT-NEXT: mov h7, v0.h[2] ; CHECK-CVT-NEXT: mov h7, v0.h[2]
; CHECK-CVT-NEXT: mov h16, v1.h[3] ; CHECK-CVT-NEXT: mov h16, v1.h[3]
; CHECK-CVT-NEXT: mov h17, v0.h[3] ; CHECK-CVT-NEXT: mov h17, v0.h[3]
; CHECK-CVT-NEXT: mov h18, v1.h[4]
; CHECK-CVT-NEXT: mov h19, v0.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s6, h6
; CHECK-CVT-NEXT: fcvt s7, h7
; CHECK-CVT-NEXT: mov h20, v1.h[5]
; CHECK-CVT-NEXT: fsub s4, s5, s4 ; CHECK-CVT-NEXT: fsub s4, s5, s4
; CHECK-CVT-NEXT: fcvt s5, h6 ; CHECK-CVT-NEXT: mov h5, v0.h[5]
; CHECK-CVT-NEXT: fcvt s6, h7 ; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcvt s7, h16 ; CHECK-CVT-NEXT: fcvt s17, h17
; CHECK-CVT-NEXT: fcvt s16, h17 ; CHECK-CVT-NEXT: fcvt s18, h18
; CHECK-CVT-NEXT: fsub s3, s3, s2 ; CHECK-CVT-NEXT: fcvt s19, h19
; CHECK-CVT-NEXT: fsub s2, s3, s2
; CHECK-CVT-NEXT: fsub s3, s7, s6
; CHECK-CVT-NEXT: fcvt s6, h20
; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fsub s7, s17, s16
; CHECK-CVT-NEXT: mov h16, v1.h[6]
; CHECK-CVT-NEXT: fsub s17, s19, s18
; CHECK-CVT-NEXT: mov h18, v0.h[6]
; CHECK-CVT-NEXT: fcvt h19, s2
; CHECK-CVT-NEXT: fcvt h2, s4 ; CHECK-CVT-NEXT: fcvt h2, s4
; CHECK-CVT-NEXT: fsub s4, s6, s5
; CHECK-CVT-NEXT: mov h5, v1.h[4]
; CHECK-CVT-NEXT: mov h6, v0.h[4]
; CHECK-CVT-NEXT: fsub s7, s16, s7
; CHECK-CVT-NEXT: fcvt h3, s3
; CHECK-CVT-NEXT: mov h16, v0.h[5]
; CHECK-CVT-NEXT: fcvt h7, s7
; CHECK-CVT-NEXT: mov v2.h[1], v3.h[0]
; CHECK-CVT-NEXT: fcvt h3, s4
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: mov h6, v1.h[5]
; CHECK-CVT-NEXT: mov v2.h[2], v3.h[0]
; CHECK-CVT-NEXT: fsub s3, s5, s4
; CHECK-CVT-NEXT: fcvt s4, h6
; CHECK-CVT-NEXT: fcvt s5, h16
; CHECK-CVT-NEXT: mov h6, v1.h[6]
; CHECK-CVT-NEXT: mov h16, v0.h[6]
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: mov v2.h[3], v7.h[0]
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: fsub s4, s5, s6
; CHECK-CVT-NEXT: fcvt h3, s3 ; CHECK-CVT-NEXT: fcvt h3, s3
; CHECK-CVT-NEXT: fsub s4, s5, s4 ; CHECK-CVT-NEXT: fcvt s5, h16
; CHECK-CVT-NEXT: fcvt s5, h6 ; CHECK-CVT-NEXT: fcvt s6, h18
; CHECK-CVT-NEXT: fcvt s6, h16 ; CHECK-CVT-NEXT: mov v2.h[1], v19.h[0]
; CHECK-CVT-NEXT: fcvt h7, s7
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v2.h[4], v3.h[0] ; CHECK-CVT-NEXT: mov v2.h[2], v3.h[0]
; CHECK-CVT-NEXT: fcvt h3, s4 ; CHECK-CVT-NEXT: fsub s3, s6, s5
; CHECK-CVT-NEXT: fsub s4, s6, s5 ; CHECK-CVT-NEXT: fcvt h5, s17
; CHECK-CVT-NEXT: mov v2.h[3], v7.h[0]
; CHECK-CVT-NEXT: fsub s0, s0, s1 ; CHECK-CVT-NEXT: fsub s0, s0, s1
; CHECK-CVT-NEXT: mov v2.h[5], v3.h[0] ; CHECK-CVT-NEXT: fcvt h1, s4
; CHECK-CVT-NEXT: fcvt h3, s4 ; CHECK-CVT-NEXT: mov v2.h[4], v5.h[0]
; CHECK-CVT-NEXT: fcvt h3, s3
; CHECK-CVT-NEXT: mov v2.h[5], v1.h[0]
; CHECK-CVT-NEXT: fcvt h0, s0 ; CHECK-CVT-NEXT: fcvt h0, s0
; CHECK-CVT-NEXT: mov v2.h[6], v3.h[0] ; CHECK-CVT-NEXT: mov v2.h[6], v3.h[0]
; CHECK-CVT-NEXT: mov v2.h[7], v0.h[0] ; CHECK-CVT-NEXT: mov v2.h[7], v0.h[0]
; CHECK-CVT-NEXT: mov v0.16b, v2.16b ; CHECK-CVT-NEXT: mov v0.16b, v2.16b
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: sub_h: ; CHECK-FP16-LABEL: sub_h:
; CHECK-FP16: // %bb.0: // %entry ; CHECK-FP16: // %bb.0: // %entry
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; CHECK-CVT-LABEL: mul_h: ; CHECK-CVT-LABEL: mul_h:
; CHECK-CVT: // %bb.0: // %entry ; CHECK-CVT: // %bb.0: // %entry
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: fcvt s4, h1
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: fcvt s5, h0
; CHECK-CVT-NEXT: mov h6, v1.h[2] ; CHECK-CVT-NEXT: mov h6, v1.h[2]
; CHECK-CVT-NEXT: mov h7, v0.h[2] ; CHECK-CVT-NEXT: mov h7, v0.h[2]
; CHECK-CVT-NEXT: mov h16, v0.h[3] ; CHECK-CVT-NEXT: mov h16, v1.h[3]
; CHECK-CVT-NEXT: mov h17, v0.h[3]
; CHECK-CVT-NEXT: mov h18, v1.h[4]
; CHECK-CVT-NEXT: mov h19, v0.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fmul s4, s5, s4
; CHECK-CVT-NEXT: mov h5, v1.h[3]
; CHECK-CVT-NEXT: fcvt s6, h6 ; CHECK-CVT-NEXT: fcvt s6, h6
; CHECK-CVT-NEXT: fcvt s7, h7 ; CHECK-CVT-NEXT: fcvt s7, h7
; CHECK-CVT-NEXT: fmul s3, s3, s2 ; CHECK-CVT-NEXT: mov h20, v1.h[5]
; CHECK-CVT-NEXT: fcvt h2, s4
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: fcvt s5, h16
; CHECK-CVT-NEXT: fmul s6, s7, s6
; CHECK-CVT-NEXT: mov h7, v1.h[4]
; CHECK-CVT-NEXT: mov h16, v0.h[4]
; CHECK-CVT-NEXT: fcvt h3, s3
; CHECK-CVT-NEXT: fmul s4, s5, s4 ; CHECK-CVT-NEXT: fmul s4, s5, s4
; CHECK-CVT-NEXT: mov h5, v0.h[5] ; CHECK-CVT-NEXT: mov h5, v0.h[5]
; CHECK-CVT-NEXT: fcvt h6, s6
; CHECK-CVT-NEXT: fcvt s7, h7
; CHECK-CVT-NEXT: mov v2.h[1], v3.h[0]
; CHECK-CVT-NEXT: mov h3, v1.h[5]
; CHECK-CVT-NEXT: fcvt s16, h16 ; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcvt h4, s4 ; CHECK-CVT-NEXT: fcvt s17, h17
; CHECK-CVT-NEXT: fcvt s18, h18
; CHECK-CVT-NEXT: fcvt s19, h19
; CHECK-CVT-NEXT: fmul s2, s3, s2
; CHECK-CVT-NEXT: fmul s3, s7, s6
; CHECK-CVT-NEXT: fcvt s6, h20
; CHECK-CVT-NEXT: fcvt s5, h5 ; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fmul s7, s17, s16
; CHECK-CVT-NEXT: mov v2.h[2], v6.h[0] ; CHECK-CVT-NEXT: mov h16, v1.h[6]
; CHECK-CVT-NEXT: fmul s6, s16, s7 ; CHECK-CVT-NEXT: fmul s17, s19, s18
; CHECK-CVT-NEXT: mov h7, v1.h[6] ; CHECK-CVT-NEXT: mov h18, v0.h[6]
; CHECK-CVT-NEXT: mov h16, v0.h[6] ; CHECK-CVT-NEXT: fcvt h19, s2
; CHECK-CVT-NEXT: fcvt h2, s4
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: fmul s3, s5, s3
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: mov v2.h[3], v4.h[0] ; CHECK-CVT-NEXT: fmul s4, s5, s6
; CHECK-CVT-NEXT: fcvt h4, s6
; CHECK-CVT-NEXT: fcvt s5, h7
; CHECK-CVT-NEXT: fcvt s6, h16
; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: fcvt h3, s3 ; CHECK-CVT-NEXT: fcvt h3, s3
; CHECK-CVT-NEXT: fcvt s5, h16
; CHECK-CVT-NEXT: fcvt s6, h18
; CHECK-CVT-NEXT: mov v2.h[1], v19.h[0]
; CHECK-CVT-NEXT: fcvt h7, s7
; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v2.h[4], v4.h[0] ; CHECK-CVT-NEXT: mov v2.h[2], v3.h[0]
; CHECK-CVT-NEXT: fmul s4, s6, s5 ; CHECK-CVT-NEXT: fmul s3, s6, s5
; CHECK-CVT-NEXT: fcvt h5, s17
; CHECK-CVT-NEXT: mov v2.h[3], v7.h[0]
; CHECK-CVT-NEXT: fmul s0, s0, s1 ; CHECK-CVT-NEXT: fmul s0, s0, s1
; CHECK-CVT-NEXT: mov v2.h[5], v3.h[0] ; CHECK-CVT-NEXT: fcvt h1, s4
; CHECK-CVT-NEXT: fcvt h3, s4 ; CHECK-CVT-NEXT: mov v2.h[4], v5.h[0]
; CHECK-CVT-NEXT: fcvt h3, s3
; CHECK-CVT-NEXT: mov v2.h[5], v1.h[0]
; CHECK-CVT-NEXT: fcvt h0, s0 ; CHECK-CVT-NEXT: fcvt h0, s0
; CHECK-CVT-NEXT: mov v2.h[6], v3.h[0] ; CHECK-CVT-NEXT: mov v2.h[6], v3.h[0]
; CHECK-CVT-NEXT: mov v2.h[7], v0.h[0] ; CHECK-CVT-NEXT: mov v2.h[7], v0.h[0]
; CHECK-CVT-NEXT: mov v0.16b, v2.16b ; CHECK-CVT-NEXT: mov v0.16b, v2.16b
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: mul_h: ; CHECK-FP16-LABEL: mul_h:
; CHECK-FP16: // %bb.0: // %entry ; CHECK-FP16: // %bb.0: // %entry
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; CHECK-CVT-NEXT: fcvt s7, h7 ; CHECK-CVT-NEXT: fcvt s7, h7
; CHECK-CVT-NEXT: fcvt s16, h16 ; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcvt s17, h17 ; CHECK-CVT-NEXT: fcvt s17, h17
; CHECK-CVT-NEXT: fdiv s2, s3, s2 ; CHECK-CVT-NEXT: fdiv s2, s3, s2
; CHECK-CVT-NEXT: fcvt s3, h1 ; CHECK-CVT-NEXT: fcvt s3, h1
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: fdiv s3, s4, s3 ; CHECK-CVT-NEXT: fdiv s3, s4, s3
; CHECK-CVT-NEXT: mov h4, v1.h[2] ; CHECK-CVT-NEXT: mov h4, v1.h[2]
; CHECK-CVT-NEXT: fcvt h18, s2 ; CHECK-CVT-NEXT: fcvt h2, s2
; CHECK-CVT-NEXT: fcvt s4, h4 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fdiv s4, s5, s4 ; CHECK-CVT-NEXT: fdiv s4, s5, s4
; CHECK-CVT-NEXT: mov h5, v1.h[3] ; CHECK-CVT-NEXT: mov h5, v1.h[3]
; CHECK-CVT-NEXT: fcvt h2, s3
; CHECK-CVT-NEXT: fcvt s5, h5 ; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: mov v2.h[1], v18.h[0]
; CHECK-CVT-NEXT: fdiv s5, s6, s5 ; CHECK-CVT-NEXT: fdiv s5, s6, s5
; CHECK-CVT-NEXT: mov h6, v1.h[4] ; CHECK-CVT-NEXT: mov h6, v1.h[4]
; CHECK-CVT-NEXT: fcvt h4, s4
; CHECK-CVT-NEXT: fcvt s6, h6 ; CHECK-CVT-NEXT: fcvt s6, h6
; CHECK-CVT-NEXT: mov v2.h[2], v4.h[0]
; CHECK-CVT-NEXT: fdiv s6, s7, s6 ; CHECK-CVT-NEXT: fdiv s6, s7, s6
; CHECK-CVT-NEXT: mov h7, v1.h[5] ; CHECK-CVT-NEXT: mov h7, v1.h[5]
; CHECK-CVT-NEXT: fcvt h4, s5
; CHECK-CVT-NEXT: fcvt s7, h7 ; CHECK-CVT-NEXT: fcvt s7, h7
; CHECK-CVT-NEXT: mov v2.h[3], v4.h[0]
; CHECK-CVT-NEXT: fdiv s7, s16, s7 ; CHECK-CVT-NEXT: fdiv s7, s16, s7
; CHECK-CVT-NEXT: mov h16, v1.h[6] ; CHECK-CVT-NEXT: mov h16, v1.h[6]
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: fcvt s16, h16 ; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: fdiv s3, s17, s16 ; CHECK-CVT-NEXT: fdiv s16, s17, s16
; CHECK-CVT-NEXT: fdiv s0, s0, s1 ; CHECK-CVT-NEXT: fdiv s1, s0, s1
; CHECK-CVT-NEXT: fcvt h1, s6 ; CHECK-CVT-NEXT: fcvt h0, s3
; CHECK-CVT-NEXT: mov v2.h[4], v1.h[0] ; CHECK-CVT-NEXT: fcvt h3, s4
; CHECK-CVT-NEXT: fcvt h1, s7 ; CHECK-CVT-NEXT: mov v0.h[1], v2.h[0]
; CHECK-CVT-NEXT: mov v2.h[5], v1.h[0] ; CHECK-CVT-NEXT: fcvt h2, s5
; CHECK-CVT-NEXT: fcvt h1, s3 ; CHECK-CVT-NEXT: mov v0.h[2], v3.h[0]
; CHECK-CVT-NEXT: mov v2.h[6], v1.h[0] ; CHECK-CVT-NEXT: fcvt h3, s6
; CHECK-CVT-NEXT: fcvt h0, s0 ; CHECK-CVT-NEXT: mov v0.h[3], v2.h[0]
; CHECK-CVT-NEXT: mov v2.h[7], v0.h[0] ; CHECK-CVT-NEXT: fcvt h2, s7
; CHECK-CVT-NEXT: mov v0.16b, v2.16b ; CHECK-CVT-NEXT: mov v0.h[4], v3.h[0]
; CHECK-CVT-NEXT: fcvt h3, s16
; CHECK-CVT-NEXT: mov v0.h[5], v2.h[0]
; CHECK-CVT-NEXT: fcvt h1, s1
; CHECK-CVT-NEXT: mov v0.h[6], v3.h[0]
; CHECK-CVT-NEXT: mov v0.h[7], v1.h[0]
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: div_h: ; CHECK-FP16-LABEL: div_h:
; CHECK-FP16: // %bb.0: // %entry ; CHECK-FP16: // %bb.0: // %entry
; CHECK-FP16-NEXT: fdiv v0.8h, v0.8h, v1.8h ; CHECK-FP16-NEXT: fdiv v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
entry: entry:
%0 = fdiv <8 x half> %a, %b %0 = fdiv <8 x half> %a, %b
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define <8 x half> @d_to_h(<8 x double> %a) { define <8 x half> @d_to_h(<8 x double> %a) {
; CHECK-LABEL: d_to_h: ; CHECK-LABEL: d_to_h:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d4, v0.d[1] ; CHECK-NEXT: mov d4, v0.d[1]
; CHECK-NEXT: fcvt h0, d0 ; CHECK-NEXT: fcvt h0, d0
; CHECK-NEXT: mov d5, v1.d[1] ; CHECK-NEXT: mov d5, v1.d[1]
; CHECK-NEXT: fcvt h1, d1 ; CHECK-NEXT: fcvt h1, d1
; CHECK-NEXT: fcvt h4, d4 ; CHECK-NEXT: fcvt h4, d4
; CHECK-NEXT: fcvt h5, d5
; CHECK-NEXT: mov v0.h[1], v4.h[0] ; CHECK-NEXT: mov v0.h[1], v4.h[0]
; CHECK-NEXT: fcvt h4, d5 ; CHECK-NEXT: mov d4, v2.d[1]
; CHECK-NEXT: mov v0.h[2], v1.h[0] ; CHECK-NEXT: mov v0.h[2], v1.h[0]
; CHECK-NEXT: fcvt h1, d2 ; CHECK-NEXT: fcvt h1, d2
; CHECK-NEXT: mov d2, v2.d[1] ; CHECK-NEXT: mov v0.h[3], v5.h[0]
; CHECK-NEXT: mov v0.h[3], v4.h[0] ; CHECK-NEXT: fcvt h2, d4
; CHECK-NEXT: fcvt h2, d2 ; CHECK-NEXT: mov d4, v3.d[1]
; CHECK-NEXT: mov v0.h[4], v1.h[0] ; CHECK-NEXT: mov v0.h[4], v1.h[0]
; CHECK-NEXT: fcvt h1, d3 ; CHECK-NEXT: fcvt h1, d3
; CHECK-NEXT: mov v0.h[5], v2.h[0] ; CHECK-NEXT: mov v0.h[5], v2.h[0]
; CHECK-NEXT: mov d2, v3.d[1] ; CHECK-NEXT: fcvt h2, d4
; CHECK-NEXT: mov v0.h[6], v1.h[0] ; CHECK-NEXT: mov v0.h[6], v1.h[0]
; CHECK-NEXT: fcvt h1, d2 ; CHECK-NEXT: mov v0.h[7], v2.h[0]
; CHECK-NEXT: mov v0.h[7], v1.h[0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = fptrunc <8 x double> %a to <8 x half> %1 = fptrunc <8 x double> %a to <8 x half>
ret <8 x half> %1 ret <8 x half> %1
} }
define <8 x float> @h_to_s(<8 x half> %a) { define <8 x float> @h_to_s(<8 x half> %a) {
; CHECK-LABEL: h_to_s: ; CHECK-LABEL: h_to_s:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtl2 v1.4s, v0.8h ; CHECK-NEXT: fcvtl2 v1.4s, v0.8h
; CHECK-NEXT: fcvtl v0.4s, v0.4h ; CHECK-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = fpext <8 x half> %a to <8 x float> %1 = fpext <8 x half> %a to <8 x float>
ret <8 x float> %1 ret <8 x float> %1
} }
define <8 x double> @h_to_d(<8 x half> %a) { define <8 x double> @h_to_d(<8 x half> %a) {
; CHECK-LABEL: h_to_d: ; CHECK-LABEL: h_to_d:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: mov h1, v0.h[1] ; CHECK-NEXT: mov h3, v0.h[1]
; CHECK-NEXT: mov h3, v0.h[3] ; CHECK-NEXT: mov h4, v0.h[3]
; CHECK-NEXT: mov h4, v0.h[2] ; CHECK-NEXT: mov h5, v0.h[2]
; CHECK-NEXT: mov h6, v1.h[1]
; CHECK-NEXT: mov h7, v1.h[3]
; CHECK-NEXT: mov h16, v1.h[2]
; CHECK-NEXT: fcvt d0, h0 ; CHECK-NEXT: fcvt d0, h0
; CHECK-NEXT: mov h5, v2.h[1] ; CHECK-NEXT: fcvt d2, h1
; CHECK-NEXT: mov h6, v2.h[3]
; CHECK-NEXT: mov h7, v2.h[2]
; CHECK-NEXT: fcvt d16, h1
; CHECK-NEXT: fcvt d17, h3 ; CHECK-NEXT: fcvt d17, h3
; CHECK-NEXT: fcvt d1, h4 ; CHECK-NEXT: fcvt d4, h4
; CHECK-NEXT: fcvt d2, h2 ; CHECK-NEXT: fcvt d1, h5
; CHECK-NEXT: fcvt d4, h5
; CHECK-NEXT: fcvt d5, h6 ; CHECK-NEXT: fcvt d5, h6
; CHECK-NEXT: fcvt d3, h7 ; CHECK-NEXT: fcvt d6, h7
; CHECK-NEXT: mov v0.d[1], v16.d[0] ; CHECK-NEXT: fcvt d3, h16
; CHECK-NEXT: mov v1.d[1], v17.d[0] ; CHECK-NEXT: mov v0.d[1], v17.d[0]
; CHECK-NEXT: mov v2.d[1], v4.d[0] ; CHECK-NEXT: mov v1.d[1], v4.d[0]
; CHECK-NEXT: mov v3.d[1], v5.d[0] ; CHECK-NEXT: mov v2.d[1], v5.d[0]
; CHECK-NEXT: mov v3.d[1], v6.d[0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = fpext <8 x half> %a to <8 x double> %1 = fpext <8 x half> %a to <8 x double>
ret <8 x double> %1 ret <8 x double> %1
} }
define <8 x half> @bitcast_i_to_h(float, <8 x i16> %a) { define <8 x half> @bitcast_i_to_h(float, <8 x i16> %a) {
; CHECK-LABEL: bitcast_i_to_h: ; CHECK-LABEL: bitcast_i_to_h:
▲ Show 20 Lines • Show All 361 Lines • ▼ Show 20 Lines; CHECK-FP16-NEXT: ret
ret <8 x i16> %1 ret <8 x i16> %1
} }
define <8 x i1> @test_fcmp_une(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_une(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_une: ; CHECK-CVT-LABEL: test_fcmp_une:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: mov h4, v1.h[2]
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: mov h5, v0.h[2]
; CHECK-CVT-NEXT: mov h6, v1.h[4] ; CHECK-CVT-NEXT: fcvt s6, h1
; CHECK-CVT-NEXT: mov h7, v0.h[4] ; CHECK-CVT-NEXT: fcvt s7, h0
; CHECK-CVT-NEXT: mov h16, v1.h[5] ; CHECK-CVT-NEXT: mov h16, v1.h[5]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s6, h6 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcvt s7, h7 ; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov h2, v1.h[2] ; CHECK-CVT-NEXT: mov h2, v1.h[3]
; CHECK-CVT-NEXT: mov h3, v0.h[2] ; CHECK-CVT-NEXT: mov h3, v0.h[3]
; CHECK-CVT-NEXT: csetm w8, ne ; CHECK-CVT-NEXT: csetm w8, ne
; CHECK-CVT-NEXT: fcmp s5, s4 ; CHECK-CVT-NEXT: fcmp s7, s6
; CHECK-CVT-NEXT: mov h6, v1.h[4]
; CHECK-CVT-NEXT: mov h7, v0.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: mov h5, v0.h[3] ; CHECK-CVT-NEXT: csetm w9, ne
; CHECK-CVT-NEXT: fcmp s5, s4
; CHECK-CVT-NEXT: mov h4, v0.h[5]
; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: fcvt s6, h7
; CHECK-CVT-NEXT: fmov s7, w9
; CHECK-CVT-NEXT: csetm w9, ne ; CHECK-CVT-NEXT: csetm w9, ne
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: mov h2, v1.h[6]
; CHECK-CVT-NEXT: fcvt s3, h4 ; CHECK-CVT-NEXT: mov h3, v0.h[6]
; CHECK-CVT-NEXT: fcvt s4, h5 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: mov h5, v0.h[5] ; CHECK-CVT-NEXT: mov v7.h[1], w8
; CHECK-CVT-NEXT: mov v2.h[1], w8
; CHECK-CVT-NEXT: csetm w8, ne
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: fcvt s3, h16
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: mov h5, v1.h[6]
; CHECK-CVT-NEXT: mov v2.h[2], w8
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: csetm w8, ne ; CHECK-CVT-NEXT: csetm w8, ne
; CHECK-CVT-NEXT: fcmp s7, s6 ; CHECK-CVT-NEXT: fcmp s6, s5
; CHECK-CVT-NEXT: mov h6, v0.h[6]
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: mov v2.h[3], w8 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: csetm w8, ne ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcmp s4, s3 ; CHECK-CVT-NEXT: mov v7.h[2], w9
; CHECK-CVT-NEXT: fcvt s3, h5 ; CHECK-CVT-NEXT: csetm w9, ne
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: fcmp s4, s16
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: mov v7.h[3], w8
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v2.h[4], w8
; CHECK-CVT-NEXT: csetm w8, ne
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: mov v2.h[5], w8
; CHECK-CVT-NEXT: csetm w8, ne ; CHECK-CVT-NEXT: csetm w8, ne
; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov v7.h[4], w9
; CHECK-CVT-NEXT: csetm w9, ne
; CHECK-CVT-NEXT: fcmp s0, s1 ; CHECK-CVT-NEXT: fcmp s0, s1
; CHECK-CVT-NEXT: mov v2.h[6], w8 ; CHECK-CVT-NEXT: mov v7.h[5], w8
; CHECK-CVT-NEXT: csetm w8, ne ; CHECK-CVT-NEXT: csetm w8, ne
; CHECK-CVT-NEXT: mov v2.h[7], w8 ; CHECK-CVT-NEXT: mov v7.h[6], w9
; CHECK-CVT-NEXT: xtn v0.8b, v2.8h ; CHECK-CVT-NEXT: mov v7.h[7], w8
; CHECK-CVT-NEXT: xtn v0.8b, v7.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_fcmp_une: ; CHECK-FP16-LABEL: test_fcmp_une:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcmeq v0.8h, v0.8h, v1.8h ; CHECK-FP16-NEXT: fcmeq v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: mvn v0.16b, v0.16b ; CHECK-FP16-NEXT: mvn v0.16b, v0.16b
; CHECK-FP16-NEXT: xtn v0.8b, v0.8h ; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%1 = fcmp une <8 x half> %a, %b %1 = fcmp une <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_ueq(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_ueq(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_ueq: ; CHECK-CVT-LABEL: test_fcmp_ueq:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: fcvt s4, h1
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: fcvt s5, h0
; CHECK-CVT-NEXT: mov h6, v0.h[4] ; CHECK-CVT-NEXT: mov h6, v1.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov h2, v1.h[2] ; CHECK-CVT-NEXT: mov h2, v1.h[2]
; CHECK-CVT-NEXT: mov h3, v0.h[2] ; CHECK-CVT-NEXT: mov h3, v0.h[2]
; CHECK-CVT-NEXT: csetm w8, eq ; CHECK-CVT-NEXT: csetm w8, eq
; CHECK-CVT-NEXT: csinv w8, w8, wzr, vc ; CHECK-CVT-NEXT: csinv w8, w8, wzr, vc
; CHECK-CVT-NEXT: fcmp s5, s4 ; CHECK-CVT-NEXT: fcmp s5, s4
; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: mov h5, v0.h[3] ; CHECK-CVT-NEXT: mov h5, v0.h[3]
; CHECK-CVT-NEXT: csetm w9, eq ; CHECK-CVT-NEXT: csetm w9, eq
; CHECK-CVT-NEXT: csinv w9, w9, wzr, vc ; CHECK-CVT-NEXT: csinv w9, w9, wzr, vc
; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: fcvt s2, h5 ; CHECK-CVT-NEXT: mov h2, v0.h[4]
; CHECK-CVT-NEXT: fmov s3, w9 ; CHECK-CVT-NEXT: fcvt s3, h4
; CHECK-CVT-NEXT: mov h5, v1.h[4] ; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: csetm w9, eq ; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: mov v3.h[1], w8 ; CHECK-CVT-NEXT: csetm w10, eq
; CHECK-CVT-NEXT: csinv w8, w9, wzr, vc ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcmp s2, s4 ; CHECK-CVT-NEXT: csinv w10, w10, wzr, vc
; CHECK-CVT-NEXT: fcvt s2, h5 ; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: mov h3, v1.h[5]
; CHECK-CVT-NEXT: mov h5, v1.h[5] ; CHECK-CVT-NEXT: mov h4, v0.h[5]
; CHECK-CVT-NEXT: mov h6, v0.h[5] ; CHECK-CVT-NEXT: csetm w11, eq
; CHECK-CVT-NEXT: csetm w9, eq ; CHECK-CVT-NEXT: csinv w11, w11, wzr, vc
; CHECK-CVT-NEXT: mov v3.h[2], w8 ; CHECK-CVT-NEXT: fcmp s2, s5
; CHECK-CVT-NEXT: csinv w8, w9, wzr, vc ; CHECK-CVT-NEXT: fcvt s2, h3
; CHECK-CVT-NEXT: fcmp s4, s2 ; CHECK-CVT-NEXT: fcvt s3, h4
; CHECK-CVT-NEXT: fcvt s2, h5 ; CHECK-CVT-NEXT: mov h4, v1.h[6]
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: mov h5, v0.h[6]
; CHECK-CVT-NEXT: mov h5, v1.h[6] ; CHECK-CVT-NEXT: csetm w12, eq
; CHECK-CVT-NEXT: mov h6, v0.h[6]
; CHECK-CVT-NEXT: csetm w9, eq
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: mov v3.h[3], w8 ; CHECK-CVT-NEXT: csinv w12, w12, wzr, vc
; CHECK-CVT-NEXT: csinv w8, w9, wzr, vc
; CHECK-CVT-NEXT: fcmp s4, s2
; CHECK-CVT-NEXT: fcvt s2, h5
; CHECK-CVT-NEXT: fcvt s4, h6
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: fmov s2, w9
; CHECK-CVT-NEXT: fcvt s3, h4
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: csetm w9, eq ; CHECK-CVT-NEXT: mov v2.h[1], w8
; CHECK-CVT-NEXT: mov v3.h[4], w8
; CHECK-CVT-NEXT: csinv w8, w9, wzr, vc
; CHECK-CVT-NEXT: fcmp s4, s2
; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v3.h[5], w8
; CHECK-CVT-NEXT: csetm w8, eq ; CHECK-CVT-NEXT: csetm w8, eq
; CHECK-CVT-NEXT: csinv w8, w8, wzr, vc ; CHECK-CVT-NEXT: csinv w8, w8, wzr, vc
; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: mov v2.h[2], w10
; CHECK-CVT-NEXT: mov v2.h[3], w11
; CHECK-CVT-NEXT: csetm w9, eq
; CHECK-CVT-NEXT: csinv w9, w9, wzr, vc
; CHECK-CVT-NEXT: fcmp s0, s1 ; CHECK-CVT-NEXT: fcmp s0, s1
; CHECK-CVT-NEXT: mov v3.h[6], w8 ; CHECK-CVT-NEXT: mov v2.h[4], w12
; CHECK-CVT-NEXT: mov v2.h[5], w8
; CHECK-CVT-NEXT: csetm w8, eq ; CHECK-CVT-NEXT: csetm w8, eq
; CHECK-CVT-NEXT: csinv w8, w8, wzr, vc ; CHECK-CVT-NEXT: csinv w8, w8, wzr, vc
; CHECK-CVT-NEXT: mov v3.h[7], w8 ; CHECK-CVT-NEXT: mov v2.h[6], w9
; CHECK-CVT-NEXT: xtn v0.8b, v3.8h ; CHECK-CVT-NEXT: mov v2.h[7], w8
; CHECK-CVT-NEXT: xtn v0.8b, v2.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_fcmp_ueq: ; CHECK-FP16-LABEL: test_fcmp_ueq:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcmgt v2.8h, v0.8h, v1.8h ; CHECK-FP16-NEXT: fcmgt v2.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h ; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h
; CHECK-FP16-NEXT: orr v0.16b, v0.16b, v2.16b ; CHECK-FP16-NEXT: orr v0.16b, v0.16b, v2.16b
; CHECK-FP16-NEXT: mvn v0.16b, v0.16b ; CHECK-FP16-NEXT: mvn v0.16b, v0.16b
; CHECK-FP16-NEXT: xtn v0.8b, v0.8h ; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%1 = fcmp ueq <8 x half> %a, %b %1 = fcmp ueq <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_ugt(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_ugt(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_ugt: ; CHECK-CVT-LABEL: test_fcmp_ugt:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: mov h4, v1.h[2]
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: mov h5, v0.h[2]
; CHECK-CVT-NEXT: mov h6, v1.h[4] ; CHECK-CVT-NEXT: fcvt s6, h1
; CHECK-CVT-NEXT: mov h7, v0.h[4] ; CHECK-CVT-NEXT: fcvt s7, h0
; CHECK-CVT-NEXT: mov h16, v1.h[5] ; CHECK-CVT-NEXT: mov h16, v1.h[5]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s6, h6 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcvt s7, h7 ; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov h2, v1.h[2] ; CHECK-CVT-NEXT: mov h2, v1.h[3]
; CHECK-CVT-NEXT: mov h3, v0.h[2] ; CHECK-CVT-NEXT: mov h3, v0.h[3]
; CHECK-CVT-NEXT: csetm w8, hi ; CHECK-CVT-NEXT: csetm w8, hi
; CHECK-CVT-NEXT: fcmp s5, s4 ; CHECK-CVT-NEXT: fcmp s7, s6
; CHECK-CVT-NEXT: mov h6, v1.h[4]
; CHECK-CVT-NEXT: mov h7, v0.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: mov h5, v0.h[3] ; CHECK-CVT-NEXT: csetm w9, hi
; CHECK-CVT-NEXT: fcmp s5, s4
; CHECK-CVT-NEXT: mov h4, v0.h[5]
; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: fcvt s6, h7
; CHECK-CVT-NEXT: fmov s7, w9
; CHECK-CVT-NEXT: csetm w9, hi ; CHECK-CVT-NEXT: csetm w9, hi
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: mov h2, v1.h[6]
; CHECK-CVT-NEXT: fcvt s3, h4 ; CHECK-CVT-NEXT: mov h3, v0.h[6]
; CHECK-CVT-NEXT: fcvt s4, h5 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: mov h5, v0.h[5] ; CHECK-CVT-NEXT: mov v7.h[1], w8
; CHECK-CVT-NEXT: mov v2.h[1], w8
; CHECK-CVT-NEXT: csetm w8, hi
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: fcvt s3, h16
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: mov h5, v1.h[6]
; CHECK-CVT-NEXT: mov v2.h[2], w8
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: csetm w8, hi ; CHECK-CVT-NEXT: csetm w8, hi
; CHECK-CVT-NEXT: fcmp s7, s6 ; CHECK-CVT-NEXT: fcmp s6, s5
; CHECK-CVT-NEXT: mov h6, v0.h[6]
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: mov v2.h[3], w8 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: csetm w8, hi ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcmp s4, s3 ; CHECK-CVT-NEXT: mov v7.h[2], w9
; CHECK-CVT-NEXT: fcvt s3, h5 ; CHECK-CVT-NEXT: csetm w9, hi
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: fcmp s4, s16
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: mov v7.h[3], w8
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v2.h[4], w8
; CHECK-CVT-NEXT: csetm w8, hi
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: mov v2.h[5], w8
; CHECK-CVT-NEXT: csetm w8, hi ; CHECK-CVT-NEXT: csetm w8, hi
; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov v7.h[4], w9
; CHECK-CVT-NEXT: csetm w9, hi
; CHECK-CVT-NEXT: fcmp s0, s1 ; CHECK-CVT-NEXT: fcmp s0, s1
; CHECK-CVT-NEXT: mov v2.h[6], w8 ; CHECK-CVT-NEXT: mov v7.h[5], w8
; CHECK-CVT-NEXT: csetm w8, hi ; CHECK-CVT-NEXT: csetm w8, hi
; CHECK-CVT-NEXT: mov v2.h[7], w8 ; CHECK-CVT-NEXT: mov v7.h[6], w9
; CHECK-CVT-NEXT: xtn v0.8b, v2.8h ; CHECK-CVT-NEXT: mov v7.h[7], w8
; CHECK-CVT-NEXT: xtn v0.8b, v7.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_fcmp_ugt: ; CHECK-FP16-LABEL: test_fcmp_ugt:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcmge v0.8h, v1.8h, v0.8h ; CHECK-FP16-NEXT: fcmge v0.8h, v1.8h, v0.8h
; CHECK-FP16-NEXT: mvn v0.16b, v0.16b ; CHECK-FP16-NEXT: mvn v0.16b, v0.16b
; CHECK-FP16-NEXT: xtn v0.8b, v0.8h ; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%1 = fcmp ugt <8 x half> %a, %b %1 = fcmp ugt <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_uge(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_uge(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_uge: ; CHECK-CVT-LABEL: test_fcmp_uge:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: mov h4, v1.h[2]
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: mov h5, v0.h[2]
; CHECK-CVT-NEXT: mov h6, v1.h[4] ; CHECK-CVT-NEXT: fcvt s6, h1
; CHECK-CVT-NEXT: mov h7, v0.h[4] ; CHECK-CVT-NEXT: fcvt s7, h0
; CHECK-CVT-NEXT: mov h16, v1.h[5] ; CHECK-CVT-NEXT: mov h16, v1.h[5]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s6, h6 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcvt s7, h7 ; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov h2, v1.h[2] ; CHECK-CVT-NEXT: mov h2, v1.h[3]
; CHECK-CVT-NEXT: mov h3, v0.h[2] ; CHECK-CVT-NEXT: mov h3, v0.h[3]
; CHECK-CVT-NEXT: csetm w8, pl ; CHECK-CVT-NEXT: csetm w8, pl
; CHECK-CVT-NEXT: fcmp s5, s4 ; CHECK-CVT-NEXT: fcmp s7, s6
; CHECK-CVT-NEXT: mov h6, v1.h[4]
; CHECK-CVT-NEXT: mov h7, v0.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: mov h5, v0.h[3] ; CHECK-CVT-NEXT: csetm w9, pl
; CHECK-CVT-NEXT: fcmp s5, s4
; CHECK-CVT-NEXT: mov h4, v0.h[5]
; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: fcvt s6, h7
; CHECK-CVT-NEXT: fmov s7, w9
; CHECK-CVT-NEXT: csetm w9, pl ; CHECK-CVT-NEXT: csetm w9, pl
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: mov h2, v1.h[6]
; CHECK-CVT-NEXT: fcvt s3, h4 ; CHECK-CVT-NEXT: mov h3, v0.h[6]
; CHECK-CVT-NEXT: fcvt s4, h5 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: mov h5, v0.h[5] ; CHECK-CVT-NEXT: mov v7.h[1], w8
; CHECK-CVT-NEXT: mov v2.h[1], w8
; CHECK-CVT-NEXT: csetm w8, pl
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: fcvt s3, h16
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: mov h5, v1.h[6]
; CHECK-CVT-NEXT: mov v2.h[2], w8
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: csetm w8, pl ; CHECK-CVT-NEXT: csetm w8, pl
; CHECK-CVT-NEXT: fcmp s7, s6 ; CHECK-CVT-NEXT: fcmp s6, s5
; CHECK-CVT-NEXT: mov h6, v0.h[6]
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: mov v2.h[3], w8 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: csetm w8, pl ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcmp s4, s3 ; CHECK-CVT-NEXT: mov v7.h[2], w9
; CHECK-CVT-NEXT: fcvt s3, h5 ; CHECK-CVT-NEXT: csetm w9, pl
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: fcmp s4, s16
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: mov v7.h[3], w8
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v2.h[4], w8
; CHECK-CVT-NEXT: csetm w8, pl
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: mov v2.h[5], w8
; CHECK-CVT-NEXT: csetm w8, pl ; CHECK-CVT-NEXT: csetm w8, pl
; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov v7.h[4], w9
; CHECK-CVT-NEXT: csetm w9, pl
; CHECK-CVT-NEXT: fcmp s0, s1 ; CHECK-CVT-NEXT: fcmp s0, s1
; CHECK-CVT-NEXT: mov v2.h[6], w8 ; CHECK-CVT-NEXT: mov v7.h[5], w8
; CHECK-CVT-NEXT: csetm w8, pl ; CHECK-CVT-NEXT: csetm w8, pl
; CHECK-CVT-NEXT: mov v2.h[7], w8 ; CHECK-CVT-NEXT: mov v7.h[6], w9
; CHECK-CVT-NEXT: xtn v0.8b, v2.8h ; CHECK-CVT-NEXT: mov v7.h[7], w8
; CHECK-CVT-NEXT: xtn v0.8b, v7.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_fcmp_uge: ; CHECK-FP16-LABEL: test_fcmp_uge:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h ; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h
; CHECK-FP16-NEXT: mvn v0.16b, v0.16b ; CHECK-FP16-NEXT: mvn v0.16b, v0.16b
; CHECK-FP16-NEXT: xtn v0.8b, v0.8h ; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%1 = fcmp uge <8 x half> %a, %b %1 = fcmp uge <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_ult(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_ult(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_ult: ; CHECK-CVT-LABEL: test_fcmp_ult:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: mov h4, v1.h[2]
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: mov h5, v0.h[2]
; CHECK-CVT-NEXT: mov h6, v1.h[4] ; CHECK-CVT-NEXT: fcvt s6, h1
; CHECK-CVT-NEXT: mov h7, v0.h[4] ; CHECK-CVT-NEXT: fcvt s7, h0
; CHECK-CVT-NEXT: mov h16, v1.h[5] ; CHECK-CVT-NEXT: mov h16, v1.h[5]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s6, h6 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcvt s7, h7 ; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov h2, v1.h[2] ; CHECK-CVT-NEXT: mov h2, v1.h[3]
; CHECK-CVT-NEXT: mov h3, v0.h[2] ; CHECK-CVT-NEXT: mov h3, v0.h[3]
; CHECK-CVT-NEXT: csetm w8, lt ; CHECK-CVT-NEXT: csetm w8, lt
; CHECK-CVT-NEXT: fcmp s5, s4 ; CHECK-CVT-NEXT: fcmp s7, s6
; CHECK-CVT-NEXT: mov h6, v1.h[4]
; CHECK-CVT-NEXT: mov h7, v0.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: mov h5, v0.h[3] ; CHECK-CVT-NEXT: csetm w9, lt
; CHECK-CVT-NEXT: fcmp s5, s4
; CHECK-CVT-NEXT: mov h4, v0.h[5]
; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: fcvt s6, h7
; CHECK-CVT-NEXT: fmov s7, w9
; CHECK-CVT-NEXT: csetm w9, lt ; CHECK-CVT-NEXT: csetm w9, lt
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: mov h2, v1.h[6]
; CHECK-CVT-NEXT: fcvt s3, h4 ; CHECK-CVT-NEXT: mov h3, v0.h[6]
; CHECK-CVT-NEXT: fcvt s4, h5 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: mov h5, v0.h[5] ; CHECK-CVT-NEXT: mov v7.h[1], w8
; CHECK-CVT-NEXT: mov v2.h[1], w8
; CHECK-CVT-NEXT: csetm w8, lt
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: fcvt s3, h16
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: mov h5, v1.h[6]
; CHECK-CVT-NEXT: mov v2.h[2], w8
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: csetm w8, lt ; CHECK-CVT-NEXT: csetm w8, lt
; CHECK-CVT-NEXT: fcmp s7, s6 ; CHECK-CVT-NEXT: fcmp s6, s5
; CHECK-CVT-NEXT: mov h6, v0.h[6]
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: mov v2.h[3], w8 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: csetm w8, lt ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcmp s4, s3 ; CHECK-CVT-NEXT: mov v7.h[2], w9
; CHECK-CVT-NEXT: fcvt s3, h5 ; CHECK-CVT-NEXT: csetm w9, lt
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: fcmp s4, s16
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: mov v7.h[3], w8
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v2.h[4], w8
; CHECK-CVT-NEXT: csetm w8, lt
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: mov v2.h[5], w8
; CHECK-CVT-NEXT: csetm w8, lt ; CHECK-CVT-NEXT: csetm w8, lt
; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov v7.h[4], w9
; CHECK-CVT-NEXT: csetm w9, lt
; CHECK-CVT-NEXT: fcmp s0, s1 ; CHECK-CVT-NEXT: fcmp s0, s1
; CHECK-CVT-NEXT: mov v2.h[6], w8 ; CHECK-CVT-NEXT: mov v7.h[5], w8
; CHECK-CVT-NEXT: csetm w8, lt ; CHECK-CVT-NEXT: csetm w8, lt
; CHECK-CVT-NEXT: mov v2.h[7], w8 ; CHECK-CVT-NEXT: mov v7.h[6], w9
; CHECK-CVT-NEXT: xtn v0.8b, v2.8h ; CHECK-CVT-NEXT: mov v7.h[7], w8
; CHECK-CVT-NEXT: xtn v0.8b, v7.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_fcmp_ult: ; CHECK-FP16-LABEL: test_fcmp_ult:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcmge v0.8h, v0.8h, v1.8h ; CHECK-FP16-NEXT: fcmge v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: mvn v0.16b, v0.16b ; CHECK-FP16-NEXT: mvn v0.16b, v0.16b
; CHECK-FP16-NEXT: xtn v0.8b, v0.8h ; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%1 = fcmp ult <8 x half> %a, %b %1 = fcmp ult <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_ule(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_ule(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_ule: ; CHECK-CVT-LABEL: test_fcmp_ule:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: mov h4, v1.h[2]
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: mov h5, v0.h[2]
; CHECK-CVT-NEXT: mov h6, v1.h[4] ; CHECK-CVT-NEXT: fcvt s6, h1
; CHECK-CVT-NEXT: mov h7, v0.h[4] ; CHECK-CVT-NEXT: fcvt s7, h0
; CHECK-CVT-NEXT: mov h16, v1.h[5] ; CHECK-CVT-NEXT: mov h16, v1.h[5]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s6, h6 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcvt s7, h7 ; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov h2, v1.h[2] ; CHECK-CVT-NEXT: mov h2, v1.h[3]
; CHECK-CVT-NEXT: mov h3, v0.h[2] ; CHECK-CVT-NEXT: mov h3, v0.h[3]
; CHECK-CVT-NEXT: csetm w8, le ; CHECK-CVT-NEXT: csetm w8, le
; CHECK-CVT-NEXT: fcmp s5, s4 ; CHECK-CVT-NEXT: fcmp s7, s6
; CHECK-CVT-NEXT: mov h6, v1.h[4]
; CHECK-CVT-NEXT: mov h7, v0.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: mov h5, v0.h[3] ; CHECK-CVT-NEXT: csetm w9, le
; CHECK-CVT-NEXT: fcmp s5, s4
; CHECK-CVT-NEXT: mov h4, v0.h[5]
; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: fcvt s6, h7
; CHECK-CVT-NEXT: fmov s7, w9
; CHECK-CVT-NEXT: csetm w9, le ; CHECK-CVT-NEXT: csetm w9, le
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: mov h2, v1.h[6]
; CHECK-CVT-NEXT: fcvt s3, h4 ; CHECK-CVT-NEXT: mov h3, v0.h[6]
; CHECK-CVT-NEXT: fcvt s4, h5 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: mov h5, v0.h[5] ; CHECK-CVT-NEXT: mov v7.h[1], w8
; CHECK-CVT-NEXT: mov v2.h[1], w8
; CHECK-CVT-NEXT: csetm w8, le
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: fcvt s3, h16
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: mov h5, v1.h[6]
; CHECK-CVT-NEXT: mov v2.h[2], w8
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: csetm w8, le ; CHECK-CVT-NEXT: csetm w8, le
; CHECK-CVT-NEXT: fcmp s7, s6 ; CHECK-CVT-NEXT: fcmp s6, s5
; CHECK-CVT-NEXT: mov h6, v0.h[6]
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: mov v2.h[3], w8 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: csetm w8, le ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcmp s4, s3 ; CHECK-CVT-NEXT: mov v7.h[2], w9
; CHECK-CVT-NEXT: fcvt s3, h5 ; CHECK-CVT-NEXT: csetm w9, le
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: fcmp s4, s16
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: mov v7.h[3], w8
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v2.h[4], w8
; CHECK-CVT-NEXT: csetm w8, le
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: mov v2.h[5], w8
; CHECK-CVT-NEXT: csetm w8, le ; CHECK-CVT-NEXT: csetm w8, le
; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov v7.h[4], w9
; CHECK-CVT-NEXT: csetm w9, le
; CHECK-CVT-NEXT: fcmp s0, s1 ; CHECK-CVT-NEXT: fcmp s0, s1
; CHECK-CVT-NEXT: mov v2.h[6], w8 ; CHECK-CVT-NEXT: mov v7.h[5], w8
; CHECK-CVT-NEXT: csetm w8, le ; CHECK-CVT-NEXT: csetm w8, le
; CHECK-CVT-NEXT: mov v2.h[7], w8 ; CHECK-CVT-NEXT: mov v7.h[6], w9
; CHECK-CVT-NEXT: xtn v0.8b, v2.8h ; CHECK-CVT-NEXT: mov v7.h[7], w8
; CHECK-CVT-NEXT: xtn v0.8b, v7.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_fcmp_ule: ; CHECK-FP16-LABEL: test_fcmp_ule:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcmgt v0.8h, v0.8h, v1.8h ; CHECK-FP16-NEXT: fcmgt v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: mvn v0.16b, v0.16b ; CHECK-FP16-NEXT: mvn v0.16b, v0.16b
; CHECK-FP16-NEXT: xtn v0.8b, v0.8h ; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%1 = fcmp ule <8 x half> %a, %b %1 = fcmp ule <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_uno(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_uno(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_uno: ; CHECK-CVT-LABEL: test_fcmp_uno:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: mov h4, v1.h[2]
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: mov h5, v0.h[2]
; CHECK-CVT-NEXT: mov h6, v1.h[4] ; CHECK-CVT-NEXT: fcvt s6, h1
; CHECK-CVT-NEXT: mov h7, v0.h[4] ; CHECK-CVT-NEXT: fcvt s7, h0
; CHECK-CVT-NEXT: mov h16, v1.h[5] ; CHECK-CVT-NEXT: mov h16, v1.h[5]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s6, h6 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcvt s7, h7 ; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov h2, v1.h[2] ; CHECK-CVT-NEXT: mov h2, v1.h[3]
; CHECK-CVT-NEXT: mov h3, v0.h[2] ; CHECK-CVT-NEXT: mov h3, v0.h[3]
; CHECK-CVT-NEXT: csetm w8, vs ; CHECK-CVT-NEXT: csetm w8, vs
; CHECK-CVT-NEXT: fcmp s5, s4 ; CHECK-CVT-NEXT: fcmp s7, s6
; CHECK-CVT-NEXT: mov h6, v1.h[4]
; CHECK-CVT-NEXT: mov h7, v0.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: mov h5, v0.h[3] ; CHECK-CVT-NEXT: csetm w9, vs
; CHECK-CVT-NEXT: fcmp s5, s4
; CHECK-CVT-NEXT: mov h4, v0.h[5]
; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: fcvt s6, h7
; CHECK-CVT-NEXT: fmov s7, w9
; CHECK-CVT-NEXT: csetm w9, vs ; CHECK-CVT-NEXT: csetm w9, vs
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: mov h2, v1.h[6]
; CHECK-CVT-NEXT: fcvt s3, h4 ; CHECK-CVT-NEXT: mov h3, v0.h[6]
; CHECK-CVT-NEXT: fcvt s4, h5 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: mov h5, v0.h[5] ; CHECK-CVT-NEXT: mov v7.h[1], w8
; CHECK-CVT-NEXT: mov v2.h[1], w8
; CHECK-CVT-NEXT: csetm w8, vs
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: fcvt s3, h16
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: mov h5, v1.h[6]
; CHECK-CVT-NEXT: mov v2.h[2], w8
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: csetm w8, vs ; CHECK-CVT-NEXT: csetm w8, vs
; CHECK-CVT-NEXT: fcmp s7, s6 ; CHECK-CVT-NEXT: fcmp s6, s5
; CHECK-CVT-NEXT: mov h6, v0.h[6]
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: mov v2.h[3], w8 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: csetm w8, vs ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcmp s4, s3 ; CHECK-CVT-NEXT: mov v7.h[2], w9
; CHECK-CVT-NEXT: fcvt s3, h5 ; CHECK-CVT-NEXT: csetm w9, vs
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: fcmp s4, s16
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: mov v7.h[3], w8
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v2.h[4], w8
; CHECK-CVT-NEXT: csetm w8, vs
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: mov v2.h[5], w8
; CHECK-CVT-NEXT: csetm w8, vs ; CHECK-CVT-NEXT: csetm w8, vs
; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov v7.h[4], w9
; CHECK-CVT-NEXT: csetm w9, vs
; CHECK-CVT-NEXT: fcmp s0, s1 ; CHECK-CVT-NEXT: fcmp s0, s1
; CHECK-CVT-NEXT: mov v2.h[6], w8 ; CHECK-CVT-NEXT: mov v7.h[5], w8
; CHECK-CVT-NEXT: csetm w8, vs ; CHECK-CVT-NEXT: csetm w8, vs
; CHECK-CVT-NEXT: mov v2.h[7], w8 ; CHECK-CVT-NEXT: mov v7.h[6], w9
; CHECK-CVT-NEXT: xtn v0.8b, v2.8h ; CHECK-CVT-NEXT: mov v7.h[7], w8
; CHECK-CVT-NEXT: xtn v0.8b, v7.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_fcmp_uno: ; CHECK-FP16-LABEL: test_fcmp_uno:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcmge v2.8h, v0.8h, v1.8h ; CHECK-FP16-NEXT: fcmge v2.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h ; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h
; CHECK-FP16-NEXT: orr v0.16b, v0.16b, v2.16b ; CHECK-FP16-NEXT: orr v0.16b, v0.16b, v2.16b
; CHECK-FP16-NEXT: mvn v0.16b, v0.16b ; CHECK-FP16-NEXT: mvn v0.16b, v0.16b
; CHECK-FP16-NEXT: xtn v0.8b, v0.8h ; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%1 = fcmp uno <8 x half> %a, %b %1 = fcmp uno <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_one(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_one(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_one: ; CHECK-CVT-LABEL: test_fcmp_one:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: fcvt s4, h1
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: fcvt s5, h0
; CHECK-CVT-NEXT: mov h6, v0.h[4] ; CHECK-CVT-NEXT: mov h6, v1.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov h2, v1.h[2] ; CHECK-CVT-NEXT: mov h2, v1.h[2]
; CHECK-CVT-NEXT: mov h3, v0.h[2] ; CHECK-CVT-NEXT: mov h3, v0.h[2]
; CHECK-CVT-NEXT: csetm w8, mi ; CHECK-CVT-NEXT: csetm w8, mi
; CHECK-CVT-NEXT: csinv w8, w8, wzr, le ; CHECK-CVT-NEXT: csinv w8, w8, wzr, le
; CHECK-CVT-NEXT: fcmp s5, s4 ; CHECK-CVT-NEXT: fcmp s5, s4
; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: mov h5, v0.h[3] ; CHECK-CVT-NEXT: mov h5, v0.h[3]
; CHECK-CVT-NEXT: csetm w9, mi ; CHECK-CVT-NEXT: csetm w9, mi
; CHECK-CVT-NEXT: csinv w9, w9, wzr, le ; CHECK-CVT-NEXT: csinv w9, w9, wzr, le
; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: fcvt s2, h5 ; CHECK-CVT-NEXT: mov h2, v0.h[4]
; CHECK-CVT-NEXT: fmov s3, w9 ; CHECK-CVT-NEXT: fcvt s3, h4
; CHECK-CVT-NEXT: mov h5, v1.h[4] ; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: csetm w9, mi ; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: mov v3.h[1], w8 ; CHECK-CVT-NEXT: csetm w10, mi
; CHECK-CVT-NEXT: csinv w8, w9, wzr, le ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcmp s2, s4 ; CHECK-CVT-NEXT: csinv w10, w10, wzr, le
; CHECK-CVT-NEXT: fcvt s2, h5 ; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: mov h3, v1.h[5]
; CHECK-CVT-NEXT: mov h5, v1.h[5] ; CHECK-CVT-NEXT: mov h4, v0.h[5]
; CHECK-CVT-NEXT: mov h6, v0.h[5] ; CHECK-CVT-NEXT: csetm w11, mi
; CHECK-CVT-NEXT: csetm w9, mi ; CHECK-CVT-NEXT: csinv w11, w11, wzr, le
; CHECK-CVT-NEXT: mov v3.h[2], w8 ; CHECK-CVT-NEXT: fcmp s2, s5
; CHECK-CVT-NEXT: csinv w8, w9, wzr, le ; CHECK-CVT-NEXT: fcvt s2, h3
; CHECK-CVT-NEXT: fcmp s4, s2 ; CHECK-CVT-NEXT: fcvt s3, h4
; CHECK-CVT-NEXT: fcvt s2, h5 ; CHECK-CVT-NEXT: mov h4, v1.h[6]
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: mov h5, v0.h[6]
; CHECK-CVT-NEXT: mov h5, v1.h[6] ; CHECK-CVT-NEXT: csetm w12, mi
; CHECK-CVT-NEXT: mov h6, v0.h[6]
; CHECK-CVT-NEXT: csetm w9, mi
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: mov v3.h[3], w8 ; CHECK-CVT-NEXT: csinv w12, w12, wzr, le
; CHECK-CVT-NEXT: csinv w8, w9, wzr, le
; CHECK-CVT-NEXT: fcmp s4, s2
; CHECK-CVT-NEXT: fcvt s2, h5
; CHECK-CVT-NEXT: fcvt s4, h6
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: fmov s2, w9
; CHECK-CVT-NEXT: fcvt s3, h4
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: csetm w9, mi ; CHECK-CVT-NEXT: mov v2.h[1], w8
; CHECK-CVT-NEXT: mov v3.h[4], w8
; CHECK-CVT-NEXT: csinv w8, w9, wzr, le
; CHECK-CVT-NEXT: fcmp s4, s2
; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v3.h[5], w8
; CHECK-CVT-NEXT: csetm w8, mi ; CHECK-CVT-NEXT: csetm w8, mi
; CHECK-CVT-NEXT: csinv w8, w8, wzr, le ; CHECK-CVT-NEXT: csinv w8, w8, wzr, le
; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: mov v2.h[2], w10
; CHECK-CVT-NEXT: mov v2.h[3], w11
; CHECK-CVT-NEXT: csetm w9, mi
; CHECK-CVT-NEXT: csinv w9, w9, wzr, le
; CHECK-CVT-NEXT: fcmp s0, s1 ; CHECK-CVT-NEXT: fcmp s0, s1
; CHECK-CVT-NEXT: mov v3.h[6], w8 ; CHECK-CVT-NEXT: mov v2.h[4], w12
; CHECK-CVT-NEXT: mov v2.h[5], w8
; CHECK-CVT-NEXT: csetm w8, mi ; CHECK-CVT-NEXT: csetm w8, mi
; CHECK-CVT-NEXT: csinv w8, w8, wzr, le ; CHECK-CVT-NEXT: csinv w8, w8, wzr, le
; CHECK-CVT-NEXT: mov v3.h[7], w8 ; CHECK-CVT-NEXT: mov v2.h[6], w9
; CHECK-CVT-NEXT: xtn v0.8b, v3.8h ; CHECK-CVT-NEXT: mov v2.h[7], w8
; CHECK-CVT-NEXT: xtn v0.8b, v2.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_fcmp_one: ; CHECK-FP16-LABEL: test_fcmp_one:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcmgt v2.8h, v0.8h, v1.8h ; CHECK-FP16-NEXT: fcmgt v2.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h ; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h
; CHECK-FP16-NEXT: orr v0.16b, v0.16b, v2.16b ; CHECK-FP16-NEXT: orr v0.16b, v0.16b, v2.16b
; CHECK-FP16-NEXT: xtn v0.8b, v0.8h ; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%1 = fcmp one <8 x half> %a, %b %1 = fcmp one <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_oeq(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_oeq(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_oeq: ; CHECK-CVT-LABEL: test_fcmp_oeq:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: mov h4, v1.h[2]
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: mov h5, v0.h[2]
; CHECK-CVT-NEXT: mov h6, v1.h[4] ; CHECK-CVT-NEXT: fcvt s6, h1
; CHECK-CVT-NEXT: mov h7, v0.h[4] ; CHECK-CVT-NEXT: fcvt s7, h0
; CHECK-CVT-NEXT: mov h16, v1.h[5] ; CHECK-CVT-NEXT: mov h16, v1.h[5]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s6, h6 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcvt s7, h7 ; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov h2, v1.h[2] ; CHECK-CVT-NEXT: mov h2, v1.h[3]
; CHECK-CVT-NEXT: mov h3, v0.h[2] ; CHECK-CVT-NEXT: mov h3, v0.h[3]
; CHECK-CVT-NEXT: csetm w8, eq ; CHECK-CVT-NEXT: csetm w8, eq
; CHECK-CVT-NEXT: fcmp s5, s4 ; CHECK-CVT-NEXT: fcmp s7, s6
; CHECK-CVT-NEXT: mov h6, v1.h[4]
; CHECK-CVT-NEXT: mov h7, v0.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: mov h5, v0.h[3] ; CHECK-CVT-NEXT: csetm w9, eq
; CHECK-CVT-NEXT: fcmp s5, s4
; CHECK-CVT-NEXT: mov h4, v0.h[5]
; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: fcvt s6, h7
; CHECK-CVT-NEXT: fmov s7, w9
; CHECK-CVT-NEXT: csetm w9, eq ; CHECK-CVT-NEXT: csetm w9, eq
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: mov h2, v1.h[6]
; CHECK-CVT-NEXT: fcvt s3, h4 ; CHECK-CVT-NEXT: mov h3, v0.h[6]
; CHECK-CVT-NEXT: fcvt s4, h5 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: mov h5, v0.h[5] ; CHECK-CVT-NEXT: mov v7.h[1], w8
; CHECK-CVT-NEXT: mov v2.h[1], w8
; CHECK-CVT-NEXT: csetm w8, eq
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: fcvt s3, h16
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: mov h5, v1.h[6]
; CHECK-CVT-NEXT: mov v2.h[2], w8
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: csetm w8, eq ; CHECK-CVT-NEXT: csetm w8, eq
; CHECK-CVT-NEXT: fcmp s7, s6 ; CHECK-CVT-NEXT: fcmp s6, s5
; CHECK-CVT-NEXT: mov h6, v0.h[6]
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: mov v2.h[3], w8 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: csetm w8, eq ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcmp s4, s3 ; CHECK-CVT-NEXT: mov v7.h[2], w9
; CHECK-CVT-NEXT: fcvt s3, h5 ; CHECK-CVT-NEXT: csetm w9, eq
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: fcmp s4, s16
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: mov v7.h[3], w8
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v2.h[4], w8
; CHECK-CVT-NEXT: csetm w8, eq
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: mov v2.h[5], w8
; CHECK-CVT-NEXT: csetm w8, eq ; CHECK-CVT-NEXT: csetm w8, eq
; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov v7.h[4], w9
; CHECK-CVT-NEXT: csetm w9, eq
; CHECK-CVT-NEXT: fcmp s0, s1 ; CHECK-CVT-NEXT: fcmp s0, s1
; CHECK-CVT-NEXT: mov v2.h[6], w8 ; CHECK-CVT-NEXT: mov v7.h[5], w8
; CHECK-CVT-NEXT: csetm w8, eq ; CHECK-CVT-NEXT: csetm w8, eq
; CHECK-CVT-NEXT: mov v2.h[7], w8 ; CHECK-CVT-NEXT: mov v7.h[6], w9
; CHECK-CVT-NEXT: xtn v0.8b, v2.8h ; CHECK-CVT-NEXT: mov v7.h[7], w8
; CHECK-CVT-NEXT: xtn v0.8b, v7.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_fcmp_oeq: ; CHECK-FP16-LABEL: test_fcmp_oeq:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcmeq v0.8h, v0.8h, v1.8h ; CHECK-FP16-NEXT: fcmeq v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: xtn v0.8b, v0.8h ; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%1 = fcmp oeq <8 x half> %a, %b %1 = fcmp oeq <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_ogt(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_ogt(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_ogt: ; CHECK-CVT-LABEL: test_fcmp_ogt:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: mov h4, v1.h[2]
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: mov h5, v0.h[2]
; CHECK-CVT-NEXT: mov h6, v1.h[4] ; CHECK-CVT-NEXT: fcvt s6, h1
; CHECK-CVT-NEXT: mov h7, v0.h[4] ; CHECK-CVT-NEXT: fcvt s7, h0
; CHECK-CVT-NEXT: mov h16, v1.h[5] ; CHECK-CVT-NEXT: mov h16, v1.h[5]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s6, h6 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcvt s7, h7 ; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov h2, v1.h[2] ; CHECK-CVT-NEXT: mov h2, v1.h[3]
; CHECK-CVT-NEXT: mov h3, v0.h[2] ; CHECK-CVT-NEXT: mov h3, v0.h[3]
; CHECK-CVT-NEXT: csetm w8, gt ; CHECK-CVT-NEXT: csetm w8, gt
; CHECK-CVT-NEXT: fcmp s5, s4 ; CHECK-CVT-NEXT: fcmp s7, s6
; CHECK-CVT-NEXT: mov h6, v1.h[4]
; CHECK-CVT-NEXT: mov h7, v0.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: mov h5, v0.h[3] ; CHECK-CVT-NEXT: csetm w9, gt
; CHECK-CVT-NEXT: fcmp s5, s4
; CHECK-CVT-NEXT: mov h4, v0.h[5]
; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: fcvt s6, h7
; CHECK-CVT-NEXT: fmov s7, w9
; CHECK-CVT-NEXT: csetm w9, gt ; CHECK-CVT-NEXT: csetm w9, gt
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: mov h2, v1.h[6]
; CHECK-CVT-NEXT: fcvt s3, h4 ; CHECK-CVT-NEXT: mov h3, v0.h[6]
; CHECK-CVT-NEXT: fcvt s4, h5 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: mov h5, v0.h[5] ; CHECK-CVT-NEXT: mov v7.h[1], w8
; CHECK-CVT-NEXT: mov v2.h[1], w8
; CHECK-CVT-NEXT: csetm w8, gt
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: fcvt s3, h16
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: mov h5, v1.h[6]
; CHECK-CVT-NEXT: mov v2.h[2], w8
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: csetm w8, gt ; CHECK-CVT-NEXT: csetm w8, gt
; CHECK-CVT-NEXT: fcmp s7, s6 ; CHECK-CVT-NEXT: fcmp s6, s5
; CHECK-CVT-NEXT: mov h6, v0.h[6]
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: mov v2.h[3], w8 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: csetm w8, gt ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcmp s4, s3 ; CHECK-CVT-NEXT: mov v7.h[2], w9
; CHECK-CVT-NEXT: fcvt s3, h5 ; CHECK-CVT-NEXT: csetm w9, gt
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: fcmp s4, s16
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: mov v7.h[3], w8
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v2.h[4], w8
; CHECK-CVT-NEXT: csetm w8, gt
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: mov v2.h[5], w8
; CHECK-CVT-NEXT: csetm w8, gt ; CHECK-CVT-NEXT: csetm w8, gt
; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov v7.h[4], w9
; CHECK-CVT-NEXT: csetm w9, gt
; CHECK-CVT-NEXT: fcmp s0, s1 ; CHECK-CVT-NEXT: fcmp s0, s1
; CHECK-CVT-NEXT: mov v2.h[6], w8 ; CHECK-CVT-NEXT: mov v7.h[5], w8
; CHECK-CVT-NEXT: csetm w8, gt ; CHECK-CVT-NEXT: csetm w8, gt
; CHECK-CVT-NEXT: mov v2.h[7], w8 ; CHECK-CVT-NEXT: mov v7.h[6], w9
; CHECK-CVT-NEXT: xtn v0.8b, v2.8h ; CHECK-CVT-NEXT: mov v7.h[7], w8
; CHECK-CVT-NEXT: xtn v0.8b, v7.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_fcmp_ogt: ; CHECK-FP16-LABEL: test_fcmp_ogt:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcmgt v0.8h, v0.8h, v1.8h ; CHECK-FP16-NEXT: fcmgt v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: xtn v0.8b, v0.8h ; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%1 = fcmp ogt <8 x half> %a, %b %1 = fcmp ogt <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_oge(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_oge(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_oge: ; CHECK-CVT-LABEL: test_fcmp_oge:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: mov h4, v1.h[2]
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: mov h5, v0.h[2]
; CHECK-CVT-NEXT: mov h6, v1.h[4] ; CHECK-CVT-NEXT: fcvt s6, h1
; CHECK-CVT-NEXT: mov h7, v0.h[4] ; CHECK-CVT-NEXT: fcvt s7, h0
; CHECK-CVT-NEXT: mov h16, v1.h[5] ; CHECK-CVT-NEXT: mov h16, v1.h[5]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s6, h6 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcvt s7, h7 ; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov h2, v1.h[2] ; CHECK-CVT-NEXT: mov h2, v1.h[3]
; CHECK-CVT-NEXT: mov h3, v0.h[2] ; CHECK-CVT-NEXT: mov h3, v0.h[3]
; CHECK-CVT-NEXT: csetm w8, ge ; CHECK-CVT-NEXT: csetm w8, ge
; CHECK-CVT-NEXT: fcmp s5, s4 ; CHECK-CVT-NEXT: fcmp s7, s6
; CHECK-CVT-NEXT: mov h6, v1.h[4]
; CHECK-CVT-NEXT: mov h7, v0.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: mov h5, v0.h[3] ; CHECK-CVT-NEXT: csetm w9, ge
; CHECK-CVT-NEXT: fcmp s5, s4
; CHECK-CVT-NEXT: mov h4, v0.h[5]
; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: fcvt s6, h7
; CHECK-CVT-NEXT: fmov s7, w9
; CHECK-CVT-NEXT: csetm w9, ge ; CHECK-CVT-NEXT: csetm w9, ge
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: mov h2, v1.h[6]
; CHECK-CVT-NEXT: fcvt s3, h4 ; CHECK-CVT-NEXT: mov h3, v0.h[6]
; CHECK-CVT-NEXT: fcvt s4, h5 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: mov h5, v0.h[5] ; CHECK-CVT-NEXT: mov v7.h[1], w8
; CHECK-CVT-NEXT: mov v2.h[1], w8
; CHECK-CVT-NEXT: csetm w8, ge
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: fcvt s3, h16
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: mov h5, v1.h[6]
; CHECK-CVT-NEXT: mov v2.h[2], w8
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: csetm w8, ge ; CHECK-CVT-NEXT: csetm w8, ge
; CHECK-CVT-NEXT: fcmp s7, s6 ; CHECK-CVT-NEXT: fcmp s6, s5
; CHECK-CVT-NEXT: mov h6, v0.h[6]
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: mov v2.h[3], w8 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: csetm w8, ge ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcmp s4, s3 ; CHECK-CVT-NEXT: mov v7.h[2], w9
; CHECK-CVT-NEXT: fcvt s3, h5 ; CHECK-CVT-NEXT: csetm w9, ge
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: fcmp s4, s16
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: mov v7.h[3], w8
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v2.h[4], w8
; CHECK-CVT-NEXT: csetm w8, ge
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: mov v2.h[5], w8
; CHECK-CVT-NEXT: csetm w8, ge ; CHECK-CVT-NEXT: csetm w8, ge
; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov v7.h[4], w9
; CHECK-CVT-NEXT: csetm w9, ge
; CHECK-CVT-NEXT: fcmp s0, s1 ; CHECK-CVT-NEXT: fcmp s0, s1
; CHECK-CVT-NEXT: mov v2.h[6], w8 ; CHECK-CVT-NEXT: mov v7.h[5], w8
; CHECK-CVT-NEXT: csetm w8, ge ; CHECK-CVT-NEXT: csetm w8, ge
; CHECK-CVT-NEXT: mov v2.h[7], w8 ; CHECK-CVT-NEXT: mov v7.h[6], w9
; CHECK-CVT-NEXT: xtn v0.8b, v2.8h ; CHECK-CVT-NEXT: mov v7.h[7], w8
; CHECK-CVT-NEXT: xtn v0.8b, v7.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_fcmp_oge: ; CHECK-FP16-LABEL: test_fcmp_oge:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcmge v0.8h, v0.8h, v1.8h ; CHECK-FP16-NEXT: fcmge v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: xtn v0.8b, v0.8h ; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%1 = fcmp oge <8 x half> %a, %b %1 = fcmp oge <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_olt(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_olt(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_olt: ; CHECK-CVT-LABEL: test_fcmp_olt:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: mov h4, v1.h[2]
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: mov h5, v0.h[2]
; CHECK-CVT-NEXT: mov h6, v1.h[4] ; CHECK-CVT-NEXT: fcvt s6, h1
; CHECK-CVT-NEXT: mov h7, v0.h[4] ; CHECK-CVT-NEXT: fcvt s7, h0
; CHECK-CVT-NEXT: mov h16, v1.h[5] ; CHECK-CVT-NEXT: mov h16, v1.h[5]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s6, h6 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcvt s7, h7 ; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov h2, v1.h[2] ; CHECK-CVT-NEXT: mov h2, v1.h[3]
; CHECK-CVT-NEXT: mov h3, v0.h[2] ; CHECK-CVT-NEXT: mov h3, v0.h[3]
; CHECK-CVT-NEXT: csetm w8, mi ; CHECK-CVT-NEXT: csetm w8, mi
; CHECK-CVT-NEXT: fcmp s5, s4 ; CHECK-CVT-NEXT: fcmp s7, s6
; CHECK-CVT-NEXT: mov h6, v1.h[4]
; CHECK-CVT-NEXT: mov h7, v0.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: mov h5, v0.h[3] ; CHECK-CVT-NEXT: csetm w9, mi
; CHECK-CVT-NEXT: fcmp s5, s4
; CHECK-CVT-NEXT: mov h4, v0.h[5]
; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: fcvt s6, h7
; CHECK-CVT-NEXT: fmov s7, w9
; CHECK-CVT-NEXT: csetm w9, mi ; CHECK-CVT-NEXT: csetm w9, mi
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: mov h2, v1.h[6]
; CHECK-CVT-NEXT: fcvt s3, h4 ; CHECK-CVT-NEXT: mov h3, v0.h[6]
; CHECK-CVT-NEXT: fcvt s4, h5 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: mov h5, v0.h[5] ; CHECK-CVT-NEXT: mov v7.h[1], w8
; CHECK-CVT-NEXT: mov v2.h[1], w8
; CHECK-CVT-NEXT: csetm w8, mi
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: fcvt s3, h16
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: mov h5, v1.h[6]
; CHECK-CVT-NEXT: mov v2.h[2], w8
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: csetm w8, mi ; CHECK-CVT-NEXT: csetm w8, mi
; CHECK-CVT-NEXT: fcmp s7, s6 ; CHECK-CVT-NEXT: fcmp s6, s5
; CHECK-CVT-NEXT: mov h6, v0.h[6]
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: mov v2.h[3], w8 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: csetm w8, mi ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcmp s4, s3 ; CHECK-CVT-NEXT: mov v7.h[2], w9
; CHECK-CVT-NEXT: fcvt s3, h5 ; CHECK-CVT-NEXT: csetm w9, mi
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: fcmp s4, s16
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: mov v7.h[3], w8
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v2.h[4], w8
; CHECK-CVT-NEXT: csetm w8, mi
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: mov v2.h[5], w8
; CHECK-CVT-NEXT: csetm w8, mi ; CHECK-CVT-NEXT: csetm w8, mi
; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov v7.h[4], w9
; CHECK-CVT-NEXT: csetm w9, mi
; CHECK-CVT-NEXT: fcmp s0, s1 ; CHECK-CVT-NEXT: fcmp s0, s1
; CHECK-CVT-NEXT: mov v2.h[6], w8 ; CHECK-CVT-NEXT: mov v7.h[5], w8
; CHECK-CVT-NEXT: csetm w8, mi ; CHECK-CVT-NEXT: csetm w8, mi
; CHECK-CVT-NEXT: mov v2.h[7], w8 ; CHECK-CVT-NEXT: mov v7.h[6], w9
; CHECK-CVT-NEXT: xtn v0.8b, v2.8h ; CHECK-CVT-NEXT: mov v7.h[7], w8
; CHECK-CVT-NEXT: xtn v0.8b, v7.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_fcmp_olt: ; CHECK-FP16-LABEL: test_fcmp_olt:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h ; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h
; CHECK-FP16-NEXT: xtn v0.8b, v0.8h ; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%1 = fcmp olt <8 x half> %a, %b %1 = fcmp olt <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_ole(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_ole(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_ole: ; CHECK-CVT-LABEL: test_fcmp_ole:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: mov h4, v1.h[2]
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: mov h5, v0.h[2]
; CHECK-CVT-NEXT: mov h6, v1.h[4] ; CHECK-CVT-NEXT: fcvt s6, h1
; CHECK-CVT-NEXT: mov h7, v0.h[4] ; CHECK-CVT-NEXT: fcvt s7, h0
; CHECK-CVT-NEXT: mov h16, v1.h[5] ; CHECK-CVT-NEXT: mov h16, v1.h[5]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s6, h6 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcvt s7, h7 ; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov h2, v1.h[2] ; CHECK-CVT-NEXT: mov h2, v1.h[3]
; CHECK-CVT-NEXT: mov h3, v0.h[2] ; CHECK-CVT-NEXT: mov h3, v0.h[3]
; CHECK-CVT-NEXT: csetm w8, ls ; CHECK-CVT-NEXT: csetm w8, ls
; CHECK-CVT-NEXT: fcmp s5, s4 ; CHECK-CVT-NEXT: fcmp s7, s6
; CHECK-CVT-NEXT: mov h6, v1.h[4]
; CHECK-CVT-NEXT: mov h7, v0.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: mov h5, v0.h[3] ; CHECK-CVT-NEXT: csetm w9, ls
; CHECK-CVT-NEXT: fcmp s5, s4
; CHECK-CVT-NEXT: mov h4, v0.h[5]
; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: fcvt s6, h7
; CHECK-CVT-NEXT: fmov s7, w9
; CHECK-CVT-NEXT: csetm w9, ls ; CHECK-CVT-NEXT: csetm w9, ls
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: mov h2, v1.h[6]
; CHECK-CVT-NEXT: fcvt s3, h4 ; CHECK-CVT-NEXT: mov h3, v0.h[6]
; CHECK-CVT-NEXT: fcvt s4, h5 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: mov h5, v0.h[5] ; CHECK-CVT-NEXT: mov v7.h[1], w8
; CHECK-CVT-NEXT: mov v2.h[1], w8
; CHECK-CVT-NEXT: csetm w8, ls
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: fcvt s3, h16
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: mov h5, v1.h[6]
; CHECK-CVT-NEXT: mov v2.h[2], w8
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: csetm w8, ls ; CHECK-CVT-NEXT: csetm w8, ls
; CHECK-CVT-NEXT: fcmp s7, s6 ; CHECK-CVT-NEXT: fcmp s6, s5
; CHECK-CVT-NEXT: mov h6, v0.h[6]
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: mov v2.h[3], w8 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: csetm w8, ls ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcmp s4, s3 ; CHECK-CVT-NEXT: mov v7.h[2], w9
; CHECK-CVT-NEXT: fcvt s3, h5 ; CHECK-CVT-NEXT: csetm w9, ls
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: fcmp s4, s16
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: mov v7.h[3], w8
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v2.h[4], w8
; CHECK-CVT-NEXT: csetm w8, ls
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: mov v2.h[5], w8
; CHECK-CVT-NEXT: csetm w8, ls ; CHECK-CVT-NEXT: csetm w8, ls
; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov v7.h[4], w9
; CHECK-CVT-NEXT: csetm w9, ls
; CHECK-CVT-NEXT: fcmp s0, s1 ; CHECK-CVT-NEXT: fcmp s0, s1
; CHECK-CVT-NEXT: mov v2.h[6], w8 ; CHECK-CVT-NEXT: mov v7.h[5], w8
; CHECK-CVT-NEXT: csetm w8, ls ; CHECK-CVT-NEXT: csetm w8, ls
; CHECK-CVT-NEXT: mov v2.h[7], w8 ; CHECK-CVT-NEXT: mov v7.h[6], w9
; CHECK-CVT-NEXT: xtn v0.8b, v2.8h ; CHECK-CVT-NEXT: mov v7.h[7], w8
; CHECK-CVT-NEXT: xtn v0.8b, v7.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_fcmp_ole: ; CHECK-FP16-LABEL: test_fcmp_ole:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcmge v0.8h, v1.8h, v0.8h ; CHECK-FP16-NEXT: fcmge v0.8h, v1.8h, v0.8h
; CHECK-FP16-NEXT: xtn v0.8b, v0.8h ; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%1 = fcmp ole <8 x half> %a, %b %1 = fcmp ole <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_ord(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_ord(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_ord: ; CHECK-CVT-LABEL: test_fcmp_ord:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: mov h2, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h3, v0.h[1] ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h1 ; CHECK-CVT-NEXT: mov h4, v1.h[2]
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: mov h5, v0.h[2]
; CHECK-CVT-NEXT: mov h6, v1.h[4] ; CHECK-CVT-NEXT: fcvt s6, h1
; CHECK-CVT-NEXT: mov h7, v0.h[4] ; CHECK-CVT-NEXT: fcvt s7, h0
; CHECK-CVT-NEXT: mov h16, v1.h[5] ; CHECK-CVT-NEXT: mov h16, v1.h[5]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s6, h6 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcvt s7, h7 ; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvt s16, h16
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov h2, v1.h[2] ; CHECK-CVT-NEXT: mov h2, v1.h[3]
; CHECK-CVT-NEXT: mov h3, v0.h[2] ; CHECK-CVT-NEXT: mov h3, v0.h[3]
; CHECK-CVT-NEXT: csetm w8, vc ; CHECK-CVT-NEXT: csetm w8, vc
; CHECK-CVT-NEXT: fcmp s5, s4 ; CHECK-CVT-NEXT: fcmp s7, s6
; CHECK-CVT-NEXT: mov h6, v1.h[4]
; CHECK-CVT-NEXT: mov h7, v0.h[4]
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: mov h5, v0.h[3] ; CHECK-CVT-NEXT: csetm w9, vc
; CHECK-CVT-NEXT: fcmp s5, s4
; CHECK-CVT-NEXT: mov h4, v0.h[5]
; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: fcvt s6, h7
; CHECK-CVT-NEXT: fmov s7, w9
; CHECK-CVT-NEXT: csetm w9, vc ; CHECK-CVT-NEXT: csetm w9, vc
; CHECK-CVT-NEXT: fcmp s3, s2 ; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: mov h2, v1.h[6]
; CHECK-CVT-NEXT: fcvt s3, h4 ; CHECK-CVT-NEXT: mov h3, v0.h[6]
; CHECK-CVT-NEXT: fcvt s4, h5 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: mov h5, v0.h[5] ; CHECK-CVT-NEXT: mov v7.h[1], w8
; CHECK-CVT-NEXT: mov v2.h[1], w8
; CHECK-CVT-NEXT: csetm w8, vc
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: fcvt s3, h16
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: mov h5, v1.h[6]
; CHECK-CVT-NEXT: mov v2.h[2], w8
; CHECK-CVT-NEXT: mov h1, v1.h[7] ; CHECK-CVT-NEXT: mov h1, v1.h[7]
; CHECK-CVT-NEXT: csetm w8, vc ; CHECK-CVT-NEXT: csetm w8, vc
; CHECK-CVT-NEXT: fcmp s7, s6 ; CHECK-CVT-NEXT: fcmp s6, s5
; CHECK-CVT-NEXT: mov h6, v0.h[6]
; CHECK-CVT-NEXT: mov h0, v0.h[7] ; CHECK-CVT-NEXT: mov h0, v0.h[7]
; CHECK-CVT-NEXT: mov v2.h[3], w8 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: csetm w8, vc ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcmp s4, s3 ; CHECK-CVT-NEXT: mov v7.h[2], w9
; CHECK-CVT-NEXT: fcvt s3, h5 ; CHECK-CVT-NEXT: csetm w9, vc
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: fcmp s4, s16
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: mov v7.h[3], w8
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov v2.h[4], w8
; CHECK-CVT-NEXT: csetm w8, vc
; CHECK-CVT-NEXT: fcmp s4, s3
; CHECK-CVT-NEXT: mov v2.h[5], w8
; CHECK-CVT-NEXT: csetm w8, vc ; CHECK-CVT-NEXT: csetm w8, vc
; CHECK-CVT-NEXT: fcmp s3, s2
; CHECK-CVT-NEXT: mov v7.h[4], w9
; CHECK-CVT-NEXT: csetm w9, vc
; CHECK-CVT-NEXT: fcmp s0, s1 ; CHECK-CVT-NEXT: fcmp s0, s1
; CHECK-CVT-NEXT: mov v2.h[6], w8 ; CHECK-CVT-NEXT: mov v7.h[5], w8
; CHECK-CVT-NEXT: csetm w8, vc ; CHECK-CVT-NEXT: csetm w8, vc
; CHECK-CVT-NEXT: mov v2.h[7], w8 ; CHECK-CVT-NEXT: mov v7.h[6], w9
; CHECK-CVT-NEXT: xtn v0.8b, v2.8h ; CHECK-CVT-NEXT: mov v7.h[7], w8
; CHECK-CVT-NEXT: xtn v0.8b, v7.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_fcmp_ord: ; CHECK-FP16-LABEL: test_fcmp_ord:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcmge v2.8h, v0.8h, v1.8h ; CHECK-FP16-NEXT: fcmge v2.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h ; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h
; CHECK-FP16-NEXT: orr v0.16b, v0.16b, v2.16b ; CHECK-FP16-NEXT: orr v0.16b, v0.16b, v2.16b
; CHECK-FP16-NEXT: xtn v0.8b, v0.8h ; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%1 = fcmp ord <8 x half> %a, %b %1 = fcmp ord <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll

Show First 20 Lines • Show All 188 Lines • ▼ Show 20 Linesentry:
ret <2 x i16> %conv6 ret <2 x i16> %conv6
} }
define <2 x i16> @ustest_f64i16(<2 x double> %x) { define <2 x i16> @ustest_f64i16(<2 x double> %x) {
; CHECK-LABEL: ustest_f64i16: ; CHECK-LABEL: ustest_f64i16:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs v0.2d, v0.2d ; CHECK-NEXT: fcvtzs v0.2d, v0.2d
; CHECK-NEXT: movi d1, #0x00ffff0000ffff ; CHECK-NEXT: movi d1, #0x00ffff0000ffff
; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: xtn v0.2s, v0.2d ; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s ; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
; CHECK-NEXT: smax v0.2s, v0.2s, v2.2s ; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%conv = fptosi <2 x double> %x to <2 x i32> %conv = fptosi <2 x double> %x to <2 x i32>
%0 = icmp slt <2 x i32> %conv, <i32 65535, i32 65535> %0 = icmp slt <2 x i32> %conv, <i32 65535, i32 65535>
%spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 65535, i32 65535> %spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>
%1 = icmp sgt <2 x i32> %spec.store.select, zeroinitializer %1 = icmp sgt <2 x i32> %spec.store.select, zeroinitializer
%spec.store.select7 = select <2 x i1> %1, <2 x i32> %spec.store.select, <2 x i32> zeroinitializer %spec.store.select7 = select <2 x i1> %1, <2 x i32> %spec.store.select, <2 x i32> zeroinitializer
%conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16> %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>
▲ Show 20 Lines • Show All 643 Lines • ▼ Show 20 Linesentry:
ret <2 x i16> %conv6 ret <2 x i16> %conv6
} }
define <2 x i16> @ustest_f64i16_mm(<2 x double> %x) { define <2 x i16> @ustest_f64i16_mm(<2 x double> %x) {
; CHECK-LABEL: ustest_f64i16_mm: ; CHECK-LABEL: ustest_f64i16_mm:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs v0.2d, v0.2d ; CHECK-NEXT: fcvtzs v0.2d, v0.2d
; CHECK-NEXT: movi d1, #0x00ffff0000ffff ; CHECK-NEXT: movi d1, #0x00ffff0000ffff
; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: xtn v0.2s, v0.2d ; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s ; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
; CHECK-NEXT: smax v0.2s, v0.2s, v2.2s ; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%conv = fptosi <2 x double> %x to <2 x i32> %conv = fptosi <2 x double> %x to <2 x i32>
%spec.store.select = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>) %spec.store.select = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>)
%spec.store.select7 = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %spec.store.select, <2 x i32> zeroinitializer) %spec.store.select7 = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %spec.store.select, <2 x i32> zeroinitializer)
%conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16> %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>
ret <2 x i16> %conv6 ret <2 x i16> %conv6
} }
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llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1 ; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2 ; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3 ; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3
; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4 ; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4
; CHECK-NEXT: mov v0.s[1], v1.s[0] ; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: fcvtzs v4.4s, v4.4s ; CHECK-NEXT: fcvtzs v4.4s, v4.4s
; CHECK-NEXT: mov v0.s[2], v2.s[0] ; CHECK-NEXT: mov v0.s[2], v2.s[0]
; CHECK-NEXT: fmov w4, s4
; CHECK-NEXT: mov v0.s[3], v3.s[0] ; CHECK-NEXT: mov v0.s[3], v3.s[0]
; CHECK-NEXT: fmov w4, s4
; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: mov w1, v0.s[1] ; CHECK-NEXT: mov w1, v0.s[1]
; CHECK-NEXT: mov w2, v0.s[2] ; CHECK-NEXT: mov w2, v0.s[2]
; CHECK-NEXT: mov w3, v0.s[3] ; CHECK-NEXT: mov w3, v0.s[3]
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <5 x i32> @llvm.fptosi.sat.v5f32.v5i32(<5 x float> %f) %x = call <5 x i32> @llvm.fptosi.sat.v5f32.v5i32(<5 x float> %f)
ret <5 x i32> %x ret <5 x i32> %x
} }
define <6 x i32> @test_signed_v6f32_v6i32(<6 x float> %f) { define <6 x i32> @test_signed_v6f32_v6i32(<6 x float> %f) {
; CHECK-LABEL: test_signed_v6f32_v6i32: ; CHECK-LABEL: test_signed_v6f32_v6i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1 ; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2 ; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4 ; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4
; CHECK-NEXT: // kill: def $s5 killed $s5 def $q5 ; CHECK-NEXT: // kill: def $s5 killed $s5 def $q5
; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3 ; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3
; CHECK-NEXT: mov v0.s[1], v1.s[0] ; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: mov v4.s[1], v5.s[0] ; CHECK-NEXT: mov v4.s[1], v5.s[0]
; CHECK-NEXT: mov v0.s[2], v2.s[0] ; CHECK-NEXT: mov v0.s[2], v2.s[0]
; CHECK-NEXT: fcvtzs v1.4s, v4.4s ; CHECK-NEXT: fcvtzs v1.4s, v4.4s
; CHECK-NEXT: mov v0.s[3], v3.s[0] ; CHECK-NEXT: mov v0.s[3], v3.s[0]
; CHECK-NEXT: mov w5, v1.s[1]
; CHECK-NEXT: fmov w4, s1
; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: fmov w4, s1
; CHECK-NEXT: mov w5, v1.s[1]
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: mov w1, v0.s[1] ; CHECK-NEXT: mov w1, v0.s[1]
; CHECK-NEXT: mov w2, v0.s[2] ; CHECK-NEXT: mov w2, v0.s[2]
; CHECK-NEXT: mov w3, v0.s[3] ; CHECK-NEXT: mov w3, v0.s[3]
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <6 x i32> @llvm.fptosi.sat.v6f32.v6i32(<6 x float> %f) %x = call <6 x i32> @llvm.fptosi.sat.v6f32.v6i32(<6 x float> %f)
ret <6 x i32> %x ret <6 x i32> %x
} }
define <7 x i32> @test_signed_v7f32_v7i32(<7 x float> %f) { define <7 x i32> @test_signed_v7f32_v7i32(<7 x float> %f) {
; CHECK-LABEL: test_signed_v7f32_v7i32: ; CHECK-LABEL: test_signed_v7f32_v7i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1 ; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4 ; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4
; CHECK-NEXT: // kill: def $s5 killed $s5 def $q5 ; CHECK-NEXT: // kill: def $s5 killed $s5 def $q5
; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2 ; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
; CHECK-NEXT: // kill: def $s6 killed $s6 def $q6 ; CHECK-NEXT: // kill: def $s6 killed $s6 def $q6
; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3 ; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3
; CHECK-NEXT: mov v0.s[1], v1.s[0] ; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: mov v4.s[1], v5.s[0] ; CHECK-NEXT: mov v4.s[1], v5.s[0]
; CHECK-NEXT: mov v0.s[2], v2.s[0] ; CHECK-NEXT: mov v0.s[2], v2.s[0]
; CHECK-NEXT: mov v4.s[2], v6.s[0] ; CHECK-NEXT: mov v4.s[2], v6.s[0]
; CHECK-NEXT: mov v0.s[3], v3.s[0] ; CHECK-NEXT: mov v0.s[3], v3.s[0]
; CHECK-NEXT: fcvtzs v1.4s, v4.4s ; CHECK-NEXT: fcvtzs v1.4s, v4.4s
; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: fmov w4, s1
; CHECK-NEXT: mov w5, v1.s[1] ; CHECK-NEXT: mov w5, v1.s[1]
; CHECK-NEXT: mov w6, v1.s[2] ; CHECK-NEXT: mov w6, v1.s[2]
; CHECK-NEXT: fmov w4, s1 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: mov w1, v0.s[1] ; CHECK-NEXT: mov w1, v0.s[1]
; CHECK-NEXT: mov w2, v0.s[2] ; CHECK-NEXT: mov w2, v0.s[2]
; CHECK-NEXT: mov w3, v0.s[3] ; CHECK-NEXT: mov w3, v0.s[3]
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <7 x i32> @llvm.fptosi.sat.v7f32.v7i32(<7 x float> %f) %x = call <7 x i32> @llvm.fptosi.sat.v7f32.v7i32(<7 x float> %f)
ret <7 x i32> %x ret <7 x i32> %x
} }
define <8 x i32> @test_signed_v8f32_v8i32(<8 x float> %f) { define <8 x i32> @test_signed_v8f32_v8i32(<8 x float> %f) {
; CHECK-LABEL: test_signed_v8f32_v8i32: ; CHECK-LABEL: test_signed_v8f32_v8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
Show All 37 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptosi.sat.v2f64.v2i32(<2 x double> %f) %x = call <2 x i32> @llvm.fptosi.sat.v2f64.v2i32(<2 x double> %f)
ret <2 x i32> %x ret <2 x i32> %x
} }
define <3 x i32> @test_signed_v3f64_v3i32(<3 x double> %f) { define <3 x i32> @test_signed_v3f64_v3i32(<3 x double> %f) {
; CHECK-LABEL: test_signed_v3f64_v3i32: ; CHECK-LABEL: test_signed_v3f64_v3i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs w8, d0 ; CHECK-NEXT: fcvtzs w9, d0
; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: fcvtzs w8, d1 ; CHECK-NEXT: fcvtzs w8, d1
; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: fcvtzs w9, d2
; CHECK-NEXT: mov v0.s[1], w8 ; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: fcvtzs w8, d2
; CHECK-NEXT: mov v0.s[2], w8
; CHECK-NEXT: fcvtzs w8, d0 ; CHECK-NEXT: fcvtzs w8, d0
; CHECK-NEXT: mov v0.s[2], w9
; CHECK-NEXT: mov v0.s[3], w8 ; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <3 x i32> @llvm.fptosi.sat.v3f64.v3i32(<3 x double> %f) %x = call <3 x i32> @llvm.fptosi.sat.v3f64.v3i32(<3 x double> %f)
ret <3 x i32> %x ret <3 x i32> %x
} }
define <4 x i32> @test_signed_v4f64_v4i32(<4 x double> %f) { define <4 x i32> @test_signed_v4f64_v4i32(<4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i32: ; CHECK-LABEL: test_signed_v4f64_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d2, v0.d[1] ; CHECK-NEXT: mov d2, v0.d[1]
; CHECK-NEXT: fcvtzs w8, d0 ; CHECK-NEXT: fcvtzs w8, d0
; CHECK-NEXT: fcvtzs w9, d1
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: fcvtzs w8, d2 ; CHECK-NEXT: fcvtzs w8, d2
; CHECK-NEXT: mov d2, v1.d[1]
; CHECK-NEXT: mov v0.s[1], w8 ; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: fcvtzs w8, d1 ; CHECK-NEXT: fcvtzs w8, d2
; CHECK-NEXT: mov d1, v1.d[1] ; CHECK-NEXT: mov v0.s[2], w9
; CHECK-NEXT: mov v0.s[2], w8
; CHECK-NEXT: fcvtzs w8, d1
; CHECK-NEXT: mov v0.s[3], w8 ; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i32> @llvm.fptosi.sat.v4f64.v4i32(<4 x double> %f) %x = call <4 x i32> @llvm.fptosi.sat.v4f64.v4i32(<4 x double> %f)
ret <4 x i32> %x ret <4 x i32> %x
} }
define <5 x i32> @test_signed_v5f64_v5i32(<5 x double> %f) { define <5 x i32> @test_signed_v5f64_v5i32(<5 x double> %f) {
; CHECK-LABEL: test_signed_v5f64_v5i32: ; CHECK-LABEL: test_signed_v5f64_v5i32:
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define <5 x i32> @test_signed_v5f16_v5i32(<5 x half> %f) { define <5 x i32> @test_signed_v5f16_v5i32(<5 x half> %f) {
; CHECK-LABEL: test_signed_v5f16_v5i32: ; CHECK-LABEL: test_signed_v5f16_v5i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtl v1.4s, v0.4h ; CHECK-NEXT: fcvtl v1.4s, v0.4h
; CHECK-NEXT: fcvtl2 v0.4s, v0.8h ; CHECK-NEXT: fcvtl2 v0.4s, v0.8h
; CHECK-NEXT: fcvtzs v1.4s, v1.4s ; CHECK-NEXT: fcvtzs v1.4s, v1.4s
; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: fmov w4, s0
; CHECK-NEXT: mov w1, v1.s[1] ; CHECK-NEXT: mov w1, v1.s[1]
; CHECK-NEXT: mov w2, v1.s[2] ; CHECK-NEXT: mov w2, v1.s[2]
; CHECK-NEXT: mov w3, v1.s[3] ; CHECK-NEXT: mov w3, v1.s[3]
; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: fmov w4, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <5 x i32> @llvm.fptosi.sat.v5f16.v5i32(<5 x half> %f) %x = call <5 x i32> @llvm.fptosi.sat.v5f16.v5i32(<5 x half> %f)
ret <5 x i32> %x ret <5 x i32> %x
} }
define <6 x i32> @test_signed_v6f16_v6i32(<6 x half> %f) { define <6 x i32> @test_signed_v6f16_v6i32(<6 x half> %f) {
; CHECK-LABEL: test_signed_v6f16_v6i32: ; CHECK-LABEL: test_signed_v6f16_v6i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtl v1.4s, v0.4h ; CHECK-NEXT: fcvtl v1.4s, v0.4h
; CHECK-NEXT: fcvtl2 v0.4s, v0.8h ; CHECK-NEXT: fcvtl2 v0.4s, v0.8h
; CHECK-NEXT: fcvtzs v1.4s, v1.4s ; CHECK-NEXT: fcvtzs v1.4s, v1.4s
; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: fmov w4, s0
; CHECK-NEXT: mov w1, v1.s[1] ; CHECK-NEXT: mov w1, v1.s[1]
; CHECK-NEXT: mov w2, v1.s[2] ; CHECK-NEXT: mov w2, v1.s[2]
; CHECK-NEXT: mov w3, v1.s[3] ; CHECK-NEXT: mov w3, v1.s[3]
; CHECK-NEXT: mov w5, v0.s[1] ; CHECK-NEXT: mov w5, v0.s[1]
; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: fmov w4, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <6 x i32> @llvm.fptosi.sat.v6f16.v6i32(<6 x half> %f) %x = call <6 x i32> @llvm.fptosi.sat.v6f16.v6i32(<6 x half> %f)
ret <6 x i32> %x ret <6 x i32> %x
} }
define <7 x i32> @test_signed_v7f16_v7i32(<7 x half> %f) { define <7 x i32> @test_signed_v7f16_v7i32(<7 x half> %f) {
; CHECK-LABEL: test_signed_v7f16_v7i32: ; CHECK-LABEL: test_signed_v7f16_v7i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtl v1.4s, v0.4h ; CHECK-NEXT: fcvtl2 v1.4s, v0.8h
; CHECK-NEXT: fcvtl2 v0.4s, v0.8h ; CHECK-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NEXT: fcvtzs v1.4s, v1.4s ; CHECK-NEXT: fcvtzs v1.4s, v1.4s
; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: mov w1, v1.s[1] ; CHECK-NEXT: fmov w4, s1
; CHECK-NEXT: mov w2, v1.s[2] ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: mov w3, v1.s[3] ; CHECK-NEXT: mov w5, v1.s[1]
; CHECK-NEXT: mov w5, v0.s[1] ; CHECK-NEXT: mov w1, v0.s[1]
; CHECK-NEXT: mov w6, v0.s[2] ; CHECK-NEXT: mov w2, v0.s[2]
; CHECK-NEXT: fmov w0, s1 ; CHECK-NEXT: mov w3, v0.s[3]
; CHECK-NEXT: fmov w4, s0 ; CHECK-NEXT: mov w6, v1.s[2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <7 x i32> @llvm.fptosi.sat.v7f16.v7i32(<7 x half> %f) %x = call <7 x i32> @llvm.fptosi.sat.v7f16.v7i32(<7 x half> %f)
ret <7 x i32> %x ret <7 x i32> %x
} }
define <8 x i32> @test_signed_v8f16_v8i32(<8 x half> %f) { define <8 x i32> @test_signed_v8f16_v8i32(<8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i32: ; CHECK-LABEL: test_signed_v8f16_v8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
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declare <2 x i50> @llvm.fptosi.sat.v2f32.v2i50 (<2 x float>) declare <2 x i50> @llvm.fptosi.sat.v2f32.v2i50 (<2 x float>)
declare <2 x i64> @llvm.fptosi.sat.v2f32.v2i64 (<2 x float>) declare <2 x i64> @llvm.fptosi.sat.v2f32.v2i64 (<2 x float>)
declare <2 x i100> @llvm.fptosi.sat.v2f32.v2i100(<2 x float>) declare <2 x i100> @llvm.fptosi.sat.v2f32.v2i100(<2 x float>)
declare <2 x i128> @llvm.fptosi.sat.v2f32.v2i128(<2 x float>) declare <2 x i128> @llvm.fptosi.sat.v2f32.v2i128(<2 x float>)
define <2 x i1> @test_signed_v2f32_v2i1(<2 x float> %f) { define <2 x i1> @test_signed_v2f32_v2i1(<2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i1: ; CHECK-LABEL: test_signed_v2f32_v2i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: fcvtzs v0.2s, v0.2s ; CHECK-NEXT: fcvtzs v0.2s, v0.2s
; CHECK-NEXT: movi v2.2d, #0xffffffffffffffff ; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s ; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
; CHECK-NEXT: smax v0.2s, v0.2s, v2.2s ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i1> @llvm.fptosi.sat.v2f32.v2i1(<2 x float> %f) %x = call <2 x i1> @llvm.fptosi.sat.v2f32.v2i1(<2 x float> %f)
ret <2 x i1> %x ret <2 x i1> %x
} }
define <2 x i8> @test_signed_v2f32_v2i8(<2 x float> %f) { define <2 x i8> @test_signed_v2f32_v2i8(<2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i8: ; CHECK-LABEL: test_signed_v2f32_v2i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2s, #127
; CHECK-NEXT: fcvtzs v0.2s, v0.2s ; CHECK-NEXT: fcvtzs v0.2s, v0.2s
; CHECK-NEXT: movi v1.2s, #127
; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s ; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mvni v1.2s, #127 ; CHECK-NEXT: mvni v1.2s, #127
; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s ; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i8> @llvm.fptosi.sat.v2f32.v2i8(<2 x float> %f) %x = call <2 x i8> @llvm.fptosi.sat.v2f32.v2i8(<2 x float> %f)
ret <2 x i8> %x ret <2 x i8> %x
} }
define <2 x i13> @test_signed_v2f32_v2i13(<2 x float> %f) { define <2 x i13> @test_signed_v2f32_v2i13(<2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i13: ; CHECK-LABEL: test_signed_v2f32_v2i13:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2s, #15, msl #8
; CHECK-NEXT: fcvtzs v0.2s, v0.2s ; CHECK-NEXT: fcvtzs v0.2s, v0.2s
; CHECK-NEXT: movi v1.2s, #15, msl #8
; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s ; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mvni v1.2s, #15, msl #8 ; CHECK-NEXT: mvni v1.2s, #15, msl #8
; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s ; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i13> @llvm.fptosi.sat.v2f32.v2i13(<2 x float> %f) %x = call <2 x i13> @llvm.fptosi.sat.v2f32.v2i13(<2 x float> %f)
ret <2 x i13> %x ret <2 x i13> %x
} }
define <2 x i16> @test_signed_v2f32_v2i16(<2 x float> %f) { define <2 x i16> @test_signed_v2f32_v2i16(<2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i16: ; CHECK-LABEL: test_signed_v2f32_v2i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2s, #127, msl #8
; CHECK-NEXT: fcvtzs v0.2s, v0.2s ; CHECK-NEXT: fcvtzs v0.2s, v0.2s
; CHECK-NEXT: movi v1.2s, #127, msl #8
; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s ; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mvni v1.2s, #127, msl #8 ; CHECK-NEXT: mvni v1.2s, #127, msl #8
; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s ; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i16> @llvm.fptosi.sat.v2f32.v2i16(<2 x float> %f) %x = call <2 x i16> @llvm.fptosi.sat.v2f32.v2i16(<2 x float> %f)
ret <2 x i16> %x ret <2 x i16> %x
} }
define <2 x i19> @test_signed_v2f32_v2i19(<2 x float> %f) { define <2 x i19> @test_signed_v2f32_v2i19(<2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i19: ; CHECK-LABEL: test_signed_v2f32_v2i19:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2s, #3, msl #16
; CHECK-NEXT: fcvtzs v0.2s, v0.2s ; CHECK-NEXT: fcvtzs v0.2s, v0.2s
; CHECK-NEXT: movi v1.2s, #3, msl #16
; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s ; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mvni v1.2s, #3, msl #16 ; CHECK-NEXT: mvni v1.2s, #3, msl #16
; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s ; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i19> @llvm.fptosi.sat.v2f32.v2i19(<2 x float> %f) %x = call <2 x i19> @llvm.fptosi.sat.v2f32.v2i19(<2 x float> %f)
ret <2 x i19> %x ret <2 x i19> %x
} }
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declare <4 x i50> @llvm.fptosi.sat.v4f32.v4i50 (<4 x float>) declare <4 x i50> @llvm.fptosi.sat.v4f32.v4i50 (<4 x float>)
declare <4 x i64> @llvm.fptosi.sat.v4f32.v4i64 (<4 x float>) declare <4 x i64> @llvm.fptosi.sat.v4f32.v4i64 (<4 x float>)
declare <4 x i100> @llvm.fptosi.sat.v4f32.v4i100(<4 x float>) declare <4 x i100> @llvm.fptosi.sat.v4f32.v4i100(<4 x float>)
declare <4 x i128> @llvm.fptosi.sat.v4f32.v4i128(<4 x float>) declare <4 x i128> @llvm.fptosi.sat.v4f32.v4i128(<4 x float>)
define <4 x i1> @test_signed_v4f32_v4i1(<4 x float> %f) { define <4 x i1> @test_signed_v4f32_v4i1(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i1: ; CHECK-LABEL: test_signed_v4f32_v4i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s ; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s ; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
; CHECK-NEXT: xtn v0.4h, v0.4s ; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i1> @llvm.fptosi.sat.v4f32.v4i1(<4 x float> %f) %x = call <4 x i1> @llvm.fptosi.sat.v4f32.v4i1(<4 x float> %f)
ret <4 x i1> %x ret <4 x i1> %x
} }
define <4 x i8> @test_signed_v4f32_v4i8(<4 x float> %f) { define <4 x i8> @test_signed_v4f32_v4i8(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i8: ; CHECK-LABEL: test_signed_v4f32_v4i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #127
; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: movi v1.4s, #127
; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s ; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
; CHECK-NEXT: mvni v1.4s, #127 ; CHECK-NEXT: mvni v1.4s, #127
; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s ; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
; CHECK-NEXT: xtn v0.4h, v0.4s ; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i8> @llvm.fptosi.sat.v4f32.v4i8(<4 x float> %f) %x = call <4 x i8> @llvm.fptosi.sat.v4f32.v4i8(<4 x float> %f)
ret <4 x i8> %x ret <4 x i8> %x
} }
define <4 x i13> @test_signed_v4f32_v4i13(<4 x float> %f) { define <4 x i13> @test_signed_v4f32_v4i13(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i13: ; CHECK-LABEL: test_signed_v4f32_v4i13:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #15, msl #8
; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: movi v1.4s, #15, msl #8
; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s ; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
; CHECK-NEXT: mvni v1.4s, #15, msl #8 ; CHECK-NEXT: mvni v1.4s, #15, msl #8
; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s ; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
; CHECK-NEXT: xtn v0.4h, v0.4s ; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i13> @llvm.fptosi.sat.v4f32.v4i13(<4 x float> %f) %x = call <4 x i13> @llvm.fptosi.sat.v4f32.v4i13(<4 x float> %f)
ret <4 x i13> %x ret <4 x i13> %x
} }
define <4 x i16> @test_signed_v4f32_v4i16(<4 x float> %f) { define <4 x i16> @test_signed_v4f32_v4i16(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i16: ; CHECK-LABEL: test_signed_v4f32_v4i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: sqxtn v0.4h, v0.4s ; CHECK-NEXT: sqxtn v0.4h, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i16> @llvm.fptosi.sat.v4f32.v4i16(<4 x float> %f) %x = call <4 x i16> @llvm.fptosi.sat.v4f32.v4i16(<4 x float> %f)
ret <4 x i16> %x ret <4 x i16> %x
} }
define <4 x i19> @test_signed_v4f32_v4i19(<4 x float> %f) { define <4 x i19> @test_signed_v4f32_v4i19(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i19: ; CHECK-LABEL: test_signed_v4f32_v4i19:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #3, msl #16
; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: movi v1.4s, #3, msl #16
; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s ; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
; CHECK-NEXT: mvni v1.4s, #3, msl #16 ; CHECK-NEXT: mvni v1.4s, #3, msl #16
; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s ; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i19> @llvm.fptosi.sat.v4f32.v4i19(<4 x float> %f) %x = call <4 x i19> @llvm.fptosi.sat.v4f32.v4i19(<4 x float> %f)
ret <4 x i19> %x ret <4 x i19> %x
} }
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; CHECK-CVT-NEXT: smin v0.4s, v0.4s, v1.4s ; CHECK-CVT-NEXT: smin v0.4s, v0.4s, v1.4s
; CHECK-CVT-NEXT: movi v1.2d, #0xffffffffffffffff ; CHECK-CVT-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-CVT-NEXT: smax v0.4s, v0.4s, v1.4s ; CHECK-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
; CHECK-CVT-NEXT: xtn v0.4h, v0.4s ; CHECK-CVT-NEXT: xtn v0.4h, v0.4s
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_signed_v4f16_v4i1: ; CHECK-FP16-LABEL: test_signed_v4f16_v4i1:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: movi v1.2d, #0000000000000000
; CHECK-FP16-NEXT: fcvtzs v0.4h, v0.4h ; CHECK-FP16-NEXT: fcvtzs v0.4h, v0.4h
; CHECK-FP16-NEXT: movi v2.2d, #0xffffffffffffffff ; CHECK-FP16-NEXT: movi v1.2d, #0000000000000000
; CHECK-FP16-NEXT: smin v0.4h, v0.4h, v1.4h ; CHECK-FP16-NEXT: smin v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT: smax v0.4h, v0.4h, v2.4h ; CHECK-FP16-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-FP16-NEXT: smax v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <4 x i1> @llvm.fptosi.sat.v4f16.v4i1(<4 x half> %f) %x = call <4 x i1> @llvm.fptosi.sat.v4f16.v4i1(<4 x half> %f)
ret <4 x i1> %x ret <4 x i1> %x
} }
define <4 x i8> @test_signed_v4f16_v4i8(<4 x half> %f) { define <4 x i8> @test_signed_v4f16_v4i8(<4 x half> %f) {
; CHECK-CVT-LABEL: test_signed_v4f16_v4i8: ; CHECK-CVT-LABEL: test_signed_v4f16_v4i8:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h ; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT: movi v1.4s, #127 ; CHECK-CVT-NEXT: movi v1.4s, #127
; CHECK-CVT-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-CVT-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-CVT-NEXT: smin v0.4s, v0.4s, v1.4s ; CHECK-CVT-NEXT: smin v0.4s, v0.4s, v1.4s
; CHECK-CVT-NEXT: mvni v1.4s, #127 ; CHECK-CVT-NEXT: mvni v1.4s, #127
; CHECK-CVT-NEXT: smax v0.4s, v0.4s, v1.4s ; CHECK-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
; CHECK-CVT-NEXT: xtn v0.4h, v0.4s ; CHECK-CVT-NEXT: xtn v0.4h, v0.4s
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_signed_v4f16_v4i8: ; CHECK-FP16-LABEL: test_signed_v4f16_v4i8:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: movi v1.4h, #127
; CHECK-FP16-NEXT: fcvtzs v0.4h, v0.4h ; CHECK-FP16-NEXT: fcvtzs v0.4h, v0.4h
; CHECK-FP16-NEXT: movi v1.4h, #127
; CHECK-FP16-NEXT: smin v0.4h, v0.4h, v1.4h ; CHECK-FP16-NEXT: smin v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT: mvni v1.4h, #127 ; CHECK-FP16-NEXT: mvni v1.4h, #127
; CHECK-FP16-NEXT: smax v0.4h, v0.4h, v1.4h ; CHECK-FP16-NEXT: smax v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <4 x i8> @llvm.fptosi.sat.v4f16.v4i8(<4 x half> %f) %x = call <4 x i8> @llvm.fptosi.sat.v4f16.v4i8(<4 x half> %f)
ret <4 x i8> %x ret <4 x i8> %x
} }
define <4 x i13> @test_signed_v4f16_v4i13(<4 x half> %f) { define <4 x i13> @test_signed_v4f16_v4i13(<4 x half> %f) {
; CHECK-CVT-LABEL: test_signed_v4f16_v4i13: ; CHECK-CVT-LABEL: test_signed_v4f16_v4i13:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h ; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT: movi v1.4s, #15, msl #8 ; CHECK-CVT-NEXT: movi v1.4s, #15, msl #8
; CHECK-CVT-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-CVT-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-CVT-NEXT: smin v0.4s, v0.4s, v1.4s ; CHECK-CVT-NEXT: smin v0.4s, v0.4s, v1.4s
; CHECK-CVT-NEXT: mvni v1.4s, #15, msl #8 ; CHECK-CVT-NEXT: mvni v1.4s, #15, msl #8
; CHECK-CVT-NEXT: smax v0.4s, v0.4s, v1.4s ; CHECK-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
; CHECK-CVT-NEXT: xtn v0.4h, v0.4s ; CHECK-CVT-NEXT: xtn v0.4h, v0.4s
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_signed_v4f16_v4i13: ; CHECK-FP16-LABEL: test_signed_v4f16_v4i13:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzs v0.4h, v0.4h ; CHECK-FP16-NEXT: fcvtzs v0.4h, v0.4h
; CHECK-FP16-NEXT: mvni v1.4h, #240, lsl #8
; CHECK-FP16-NEXT: smin v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT: movi v1.4h, #240, lsl #8 ; CHECK-FP16-NEXT: movi v1.4h, #240, lsl #8
; CHECK-FP16-NEXT: mvni v2.4h, #240, lsl #8
; CHECK-FP16-NEXT: smin v0.4h, v0.4h, v2.4h
; CHECK-FP16-NEXT: smax v0.4h, v0.4h, v1.4h ; CHECK-FP16-NEXT: smax v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <4 x i13> @llvm.fptosi.sat.v4f16.v4i13(<4 x half> %f) %x = call <4 x i13> @llvm.fptosi.sat.v4f16.v4i13(<4 x half> %f)
ret <4 x i13> %x ret <4 x i13> %x
} }
define <4 x i16> @test_signed_v4f16_v4i16(<4 x half> %f) { define <4 x i16> @test_signed_v4f16_v4i16(<4 x half> %f) {
; CHECK-CVT-LABEL: test_signed_v4f16_v4i16: ; CHECK-CVT-LABEL: test_signed_v4f16_v4i16:
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; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: csel x9, xzr, x9, vs ; CHECK-NEXT: csel x9, xzr, x9, vs
; CHECK-NEXT: csel x1, xzr, x8, vs ; CHECK-NEXT: csel x1, xzr, x8, vs
; CHECK-NEXT: ldp x24, x23, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldp x24, x23, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: ldp x26, x25, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x26, x25, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #112 ; CHECK-NEXT: add sp, sp, #112
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i100> @llvm.fptosi.sat.v4f16.v4i100(<4 x half> %f) %x = call <4 x i100> @llvm.fptosi.sat.v4f16.v4i100(<4 x half> %f)
ret <4 x i100> %x ret <4 x i100> %x
} }
define <4 x i128> @test_signed_v4f16_v4i128(<4 x half> %f) { define <4 x i128> @test_signed_v4f16_v4i128(<4 x half> %f) {
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; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: csel x9, xzr, x9, vs ; CHECK-NEXT: csel x9, xzr, x9, vs
; CHECK-NEXT: csel x1, xzr, x8, vs ; CHECK-NEXT: csel x1, xzr, x8, vs
; CHECK-NEXT: ldp x24, x23, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldp x24, x23, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: ldp x26, x25, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x26, x25, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #112 ; CHECK-NEXT: add sp, sp, #112
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i128> @llvm.fptosi.sat.v4f16.v4i128(<4 x half> %f) %x = call <4 x i128> @llvm.fptosi.sat.v4f16.v4i128(<4 x half> %f)
ret <4 x i128> %x ret <4 x i128> %x
} }
; ;
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; CHECK-CVT-NEXT: cmp w10, #0 ; CHECK-CVT-NEXT: cmp w10, #0
; CHECK-CVT-NEXT: csel w10, w10, wzr, lt ; CHECK-CVT-NEXT: csel w10, w10, wzr, lt
; CHECK-CVT-NEXT: fcvtzs w12, s2 ; CHECK-CVT-NEXT: fcvtzs w12, s2
; CHECK-CVT-NEXT: cmp w10, #0 ; CHECK-CVT-NEXT: cmp w10, #0
; CHECK-CVT-NEXT: mov s0, v0.s[3] ; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: csinv w10, w10, wzr, ge ; CHECK-CVT-NEXT: csinv w10, w10, wzr, ge
; CHECK-CVT-NEXT: cmp w11, #0 ; CHECK-CVT-NEXT: cmp w11, #0
; CHECK-CVT-NEXT: csel w11, w11, wzr, lt ; CHECK-CVT-NEXT: csel w11, w11, wzr, lt
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: fcvtzs w14, s1
; CHECK-CVT-NEXT: cmp w11, #0 ; CHECK-CVT-NEXT: cmp w11, #0
; CHECK-CVT-NEXT: csinv w11, w11, wzr, ge ; CHECK-CVT-NEXT: csinv w11, w11, wzr, ge
; CHECK-CVT-NEXT: cmp w12, #0 ; CHECK-CVT-NEXT: cmp w12, #0
; CHECK-CVT-NEXT: csel w12, w12, wzr, lt ; CHECK-CVT-NEXT: csel w12, w12, wzr, lt
; CHECK-CVT-NEXT: fcvtzs w15, s0
; CHECK-CVT-NEXT: cmp w12, #0 ; CHECK-CVT-NEXT: cmp w12, #0
; CHECK-CVT-NEXT: fmov s0, w9
; CHECK-CVT-NEXT: csinv w12, w12, wzr, ge ; CHECK-CVT-NEXT: csinv w12, w12, wzr, ge
; CHECK-CVT-NEXT: cmp w13, #0 ; CHECK-CVT-NEXT: cmp w13, #0
; CHECK-CVT-NEXT: csel w13, w13, wzr, lt ; CHECK-CVT-NEXT: csel w13, w13, wzr, lt
; CHECK-CVT-NEXT: cmp w13, #0 ; CHECK-CVT-NEXT: cmp w13, #0
; CHECK-CVT-NEXT: csinv w9, w13, wzr, ge ; CHECK-CVT-NEXT: mov v0.s[1], w8
; CHECK-CVT-NEXT: fcvtzs w13, s1 ; CHECK-CVT-NEXT: csinv w13, w13, wzr, ge
; CHECK-CVT-NEXT: mov v2.s[1], w8 ; CHECK-CVT-NEXT: cmp w14, #0
; CHECK-CVT-NEXT: fmov s1, w9 ; CHECK-CVT-NEXT: csel w9, w14, wzr, lt
; CHECK-CVT-NEXT: cmp w13, #0 ; CHECK-CVT-NEXT: mov v0.s[2], w10
; CHECK-CVT-NEXT: csel w8, w13, wzr, lt ; CHECK-CVT-NEXT: cmp w9, #0
; CHECK-CVT-NEXT: fcvtzs w9, s0 ; CHECK-CVT-NEXT: fmov s1, w13
; CHECK-CVT-NEXT: cmp w8, #0 ; CHECK-CVT-NEXT: csinv w9, w9, wzr, ge
; CHECK-CVT-NEXT: cmp w15, #0
; CHECK-CVT-NEXT: mov v0.s[3], w11
; CHECK-CVT-NEXT: csel w8, w15, wzr, lt
; CHECK-CVT-NEXT: mov v1.s[1], w12 ; CHECK-CVT-NEXT: mov v1.s[1], w12
; CHECK-CVT-NEXT: cmp w8, #0
; CHECK-CVT-NEXT: csinv w8, w8, wzr, ge ; CHECK-CVT-NEXT: csinv w8, w8, wzr, ge
; CHECK-CVT-NEXT: cmp w9, #0 ; CHECK-CVT-NEXT: mov v1.s[2], w9
; CHECK-CVT-NEXT: csel w9, w9, wzr, lt
; CHECK-CVT-NEXT: mov v2.s[2], w10
; CHECK-CVT-NEXT: cmp w9, #0
; CHECK-CVT-NEXT: mov v1.s[2], w8
; CHECK-CVT-NEXT: csinv w8, w9, wzr, ge
; CHECK-CVT-NEXT: mov v2.s[3], w11
; CHECK-CVT-NEXT: mov v1.s[3], w8 ; CHECK-CVT-NEXT: mov v1.s[3], w8
; CHECK-CVT-NEXT: uzp1 v0.8h, v1.8h, v2.8h ; CHECK-CVT-NEXT: uzp1 v0.8h, v1.8h, v0.8h
; CHECK-CVT-NEXT: xtn v0.8b, v0.8h ; CHECK-CVT-NEXT: xtn v0.8b, v0.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_signed_v8f16_v8i1: ; CHECK-FP16-LABEL: test_signed_v8f16_v8i1:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: movi v1.2d, #0000000000000000
; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h ; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
; CHECK-FP16-NEXT: movi v2.2d, #0xffffffffffffffff ; CHECK-FP16-NEXT: movi v1.2d, #0000000000000000
; CHECK-FP16-NEXT: smin v0.8h, v0.8h, v1.8h ; CHECK-FP16-NEXT: smin v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: smax v0.8h, v0.8h, v2.8h ; CHECK-FP16-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-FP16-NEXT: smax v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: xtn v0.8b, v0.8h ; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <8 x i1> @llvm.fptosi.sat.v8f16.v8i1(<8 x half> %f) %x = call <8 x i1> @llvm.fptosi.sat.v8f16.v8i1(<8 x half> %f)
ret <8 x i1> %x ret <8 x i1> %x
} }
define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) { define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; CHECK-CVT-LABEL: test_signed_v8f16_v8i8: ; CHECK-CVT-LABEL: test_signed_v8f16_v8i8:
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; CHECK-CVT-NEXT: cmp w12, #127 ; CHECK-CVT-NEXT: cmp w12, #127
; CHECK-CVT-NEXT: csel w12, w12, w8, lt ; CHECK-CVT-NEXT: csel w12, w12, w8, lt
; CHECK-CVT-NEXT: fcvtzs w14, s2 ; CHECK-CVT-NEXT: fcvtzs w14, s2
; CHECK-CVT-NEXT: cmn w12, #128 ; CHECK-CVT-NEXT: cmn w12, #128
; CHECK-CVT-NEXT: mov s0, v0.s[3] ; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: csel w12, w12, w10, gt ; CHECK-CVT-NEXT: csel w12, w12, w10, gt
; CHECK-CVT-NEXT: cmp w13, #127 ; CHECK-CVT-NEXT: cmp w13, #127
; CHECK-CVT-NEXT: csel w13, w13, w8, lt ; CHECK-CVT-NEXT: csel w13, w13, w8, lt
; CHECK-CVT-NEXT: fmov s2, w11 ; CHECK-CVT-NEXT: fcvtzs w16, s1
; CHECK-CVT-NEXT: cmn w13, #128 ; CHECK-CVT-NEXT: cmn w13, #128
; CHECK-CVT-NEXT: csel w13, w13, w10, gt ; CHECK-CVT-NEXT: csel w13, w13, w10, gt
; CHECK-CVT-NEXT: cmp w14, #127 ; CHECK-CVT-NEXT: cmp w14, #127
; CHECK-CVT-NEXT: csel w14, w14, w8, lt ; CHECK-CVT-NEXT: csel w14, w14, w8, lt
; CHECK-CVT-NEXT: fcvtzs w17, s0
; CHECK-CVT-NEXT: cmn w14, #128 ; CHECK-CVT-NEXT: cmn w14, #128
; CHECK-CVT-NEXT: fmov s0, w11
; CHECK-CVT-NEXT: csel w14, w14, w10, gt ; CHECK-CVT-NEXT: csel w14, w14, w10, gt
; CHECK-CVT-NEXT: cmp w15, #127 ; CHECK-CVT-NEXT: cmp w15, #127
; CHECK-CVT-NEXT: csel w15, w15, w8, lt ; CHECK-CVT-NEXT: csel w15, w15, w8, lt
; CHECK-CVT-NEXT: cmn w15, #128 ; CHECK-CVT-NEXT: cmn w15, #128
; CHECK-CVT-NEXT: csel w11, w15, w10, gt ; CHECK-CVT-NEXT: mov v0.s[1], w9
; CHECK-CVT-NEXT: fcvtzs w15, s1 ; CHECK-CVT-NEXT: csel w15, w15, w10, gt
; CHECK-CVT-NEXT: mov v2.s[1], w9 ; CHECK-CVT-NEXT: cmp w16, #127
; CHECK-CVT-NEXT: fmov s1, w11 ; CHECK-CVT-NEXT: csel w11, w16, w8, lt
; CHECK-CVT-NEXT: cmp w15, #127 ; CHECK-CVT-NEXT: mov v0.s[2], w12
; CHECK-CVT-NEXT: csel w9, w15, w8, lt ; CHECK-CVT-NEXT: cmn w11, #128
; CHECK-CVT-NEXT: fcvtzs w11, s0 ; CHECK-CVT-NEXT: fmov s1, w15
; CHECK-CVT-NEXT: cmn w9, #128 ; CHECK-CVT-NEXT: csel w11, w11, w10, gt
; CHECK-CVT-NEXT: cmp w17, #127
; CHECK-CVT-NEXT: mov v0.s[3], w13
; CHECK-CVT-NEXT: csel w8, w17, w8, lt
; CHECK-CVT-NEXT: mov v1.s[1], w14 ; CHECK-CVT-NEXT: mov v1.s[1], w14
; CHECK-CVT-NEXT: csel w9, w9, w10, gt
; CHECK-CVT-NEXT: cmp w11, #127
; CHECK-CVT-NEXT: csel w8, w11, w8, lt
; CHECK-CVT-NEXT: mov v2.s[2], w12
; CHECK-CVT-NEXT: cmn w8, #128 ; CHECK-CVT-NEXT: cmn w8, #128
; CHECK-CVT-NEXT: mov v1.s[2], w9
; CHECK-CVT-NEXT: csel w8, w8, w10, gt ; CHECK-CVT-NEXT: csel w8, w8, w10, gt
; CHECK-CVT-NEXT: mov v2.s[3], w13 ; CHECK-CVT-NEXT: mov v1.s[2], w11
; CHECK-CVT-NEXT: mov v1.s[3], w8 ; CHECK-CVT-NEXT: mov v1.s[3], w8
; CHECK-CVT-NEXT: uzp1 v0.8h, v1.8h, v2.8h ; CHECK-CVT-NEXT: uzp1 v0.8h, v1.8h, v0.8h
; CHECK-CVT-NEXT: xtn v0.8b, v0.8h ; CHECK-CVT-NEXT: xtn v0.8b, v0.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_signed_v8f16_v8i8: ; CHECK-FP16-LABEL: test_signed_v8f16_v8i8:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h ; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
; CHECK-FP16-NEXT: sqxtn v0.8b, v0.8h ; CHECK-FP16-NEXT: sqxtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
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; CHECK-CVT-NEXT: cmp w12, #4095 ; CHECK-CVT-NEXT: cmp w12, #4095
; CHECK-CVT-NEXT: csel w12, w12, w8, lt ; CHECK-CVT-NEXT: csel w12, w12, w8, lt
; CHECK-CVT-NEXT: fcvtzs w14, s2 ; CHECK-CVT-NEXT: fcvtzs w14, s2
; CHECK-CVT-NEXT: cmn w12, #1, lsl #12 // =4096 ; CHECK-CVT-NEXT: cmn w12, #1, lsl #12 // =4096
; CHECK-CVT-NEXT: mov s0, v0.s[3] ; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: csel w12, w12, w10, gt ; CHECK-CVT-NEXT: csel w12, w12, w10, gt
; CHECK-CVT-NEXT: cmp w13, #4095 ; CHECK-CVT-NEXT: cmp w13, #4095
; CHECK-CVT-NEXT: csel w13, w13, w8, lt ; CHECK-CVT-NEXT: csel w13, w13, w8, lt
; CHECK-CVT-NEXT: fmov s2, w11 ; CHECK-CVT-NEXT: fcvtzs w16, s1
; CHECK-CVT-NEXT: cmn w13, #1, lsl #12 // =4096 ; CHECK-CVT-NEXT: cmn w13, #1, lsl #12 // =4096
; CHECK-CVT-NEXT: csel w13, w13, w10, gt ; CHECK-CVT-NEXT: csel w13, w13, w10, gt
; CHECK-CVT-NEXT: cmp w14, #4095 ; CHECK-CVT-NEXT: cmp w14, #4095
; CHECK-CVT-NEXT: csel w14, w14, w8, lt ; CHECK-CVT-NEXT: csel w14, w14, w8, lt
; CHECK-CVT-NEXT: fcvtzs w17, s0
; CHECK-CVT-NEXT: cmn w14, #1, lsl #12 // =4096 ; CHECK-CVT-NEXT: cmn w14, #1, lsl #12 // =4096
; CHECK-CVT-NEXT: fmov s0, w11
; CHECK-CVT-NEXT: csel w14, w14, w10, gt ; CHECK-CVT-NEXT: csel w14, w14, w10, gt
; CHECK-CVT-NEXT: cmp w15, #4095 ; CHECK-CVT-NEXT: cmp w15, #4095
; CHECK-CVT-NEXT: csel w15, w15, w8, lt ; CHECK-CVT-NEXT: csel w15, w15, w8, lt
; CHECK-CVT-NEXT: cmn w15, #1, lsl #12 // =4096 ; CHECK-CVT-NEXT: cmn w15, #1, lsl #12 // =4096
; CHECK-CVT-NEXT: csel w11, w15, w10, gt ; CHECK-CVT-NEXT: mov v0.s[1], w9
; CHECK-CVT-NEXT: fcvtzs w15, s1 ; CHECK-CVT-NEXT: csel w15, w15, w10, gt
; CHECK-CVT-NEXT: mov v2.s[1], w9 ; CHECK-CVT-NEXT: cmp w16, #4095
; CHECK-CVT-NEXT: fmov s1, w11 ; CHECK-CVT-NEXT: csel w11, w16, w8, lt
; CHECK-CVT-NEXT: cmp w15, #4095 ; CHECK-CVT-NEXT: mov v0.s[2], w12
; CHECK-CVT-NEXT: csel w9, w15, w8, lt ; CHECK-CVT-NEXT: cmn w11, #1, lsl #12 // =4096
; CHECK-CVT-NEXT: fcvtzs w11, s0 ; CHECK-CVT-NEXT: fmov s1, w15
; CHECK-CVT-NEXT: cmn w9, #1, lsl #12 // =4096 ; CHECK-CVT-NEXT: csel w11, w11, w10, gt
; CHECK-CVT-NEXT: cmp w17, #4095
; CHECK-CVT-NEXT: mov v0.s[3], w13
; CHECK-CVT-NEXT: csel w8, w17, w8, lt
; CHECK-CVT-NEXT: mov v1.s[1], w14 ; CHECK-CVT-NEXT: mov v1.s[1], w14
; CHECK-CVT-NEXT: csel w9, w9, w10, gt
; CHECK-CVT-NEXT: cmp w11, #4095
; CHECK-CVT-NEXT: csel w8, w11, w8, lt
; CHECK-CVT-NEXT: mov v2.s[2], w12
; CHECK-CVT-NEXT: cmn w8, #1, lsl #12 // =4096 ; CHECK-CVT-NEXT: cmn w8, #1, lsl #12 // =4096
; CHECK-CVT-NEXT: mov v1.s[2], w9
; CHECK-CVT-NEXT: csel w8, w8, w10, gt ; CHECK-CVT-NEXT: csel w8, w8, w10, gt
; CHECK-CVT-NEXT: mov v2.s[3], w13 ; CHECK-CVT-NEXT: mov v1.s[2], w11
; CHECK-CVT-NEXT: mov v1.s[3], w8 ; CHECK-CVT-NEXT: mov v1.s[3], w8
; CHECK-CVT-NEXT: uzp1 v0.8h, v1.8h, v2.8h ; CHECK-CVT-NEXT: uzp1 v0.8h, v1.8h, v0.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_signed_v8f16_v8i13: ; CHECK-FP16-LABEL: test_signed_v8f16_v8i13:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h ; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
; CHECK-FP16-NEXT: mvni v1.8h, #240, lsl #8
; CHECK-FP16-NEXT: smin v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: movi v1.8h, #240, lsl #8 ; CHECK-FP16-NEXT: movi v1.8h, #240, lsl #8
; CHECK-FP16-NEXT: mvni v2.8h, #240, lsl #8
; CHECK-FP16-NEXT: smin v0.8h, v0.8h, v2.8h
; CHECK-FP16-NEXT: smax v0.8h, v0.8h, v1.8h ; CHECK-FP16-NEXT: smax v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <8 x i13> @llvm.fptosi.sat.v8f16.v8i13(<8 x half> %f) %x = call <8 x i13> @llvm.fptosi.sat.v8f16.v8i13(<8 x half> %f)
ret <8 x i13> %x ret <8 x i13> %x
} }
define <8 x i16> @test_signed_v8f16_v8i16(<8 x half> %f) { define <8 x i16> @test_signed_v8f16_v8i16(<8 x half> %f) {
; CHECK-CVT-LABEL: test_signed_v8f16_v8i16: ; CHECK-CVT-LABEL: test_signed_v8f16_v8i16:
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; CHECK-CVT-NEXT: cmp w12, w8 ; CHECK-CVT-NEXT: cmp w12, w8
; CHECK-CVT-NEXT: csel w12, w12, w8, lt ; CHECK-CVT-NEXT: csel w12, w12, w8, lt
; CHECK-CVT-NEXT: fcvtzs w14, s2 ; CHECK-CVT-NEXT: fcvtzs w14, s2
; CHECK-CVT-NEXT: cmn w12, #8, lsl #12 // =32768 ; CHECK-CVT-NEXT: cmn w12, #8, lsl #12 // =32768
; CHECK-CVT-NEXT: mov s0, v0.s[3] ; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: csel w12, w12, w10, gt ; CHECK-CVT-NEXT: csel w12, w12, w10, gt
; CHECK-CVT-NEXT: cmp w13, w8 ; CHECK-CVT-NEXT: cmp w13, w8
; CHECK-CVT-NEXT: csel w13, w13, w8, lt ; CHECK-CVT-NEXT: csel w13, w13, w8, lt
; CHECK-CVT-NEXT: fmov s2, w11 ; CHECK-CVT-NEXT: fcvtzs w16, s1
; CHECK-CVT-NEXT: cmn w13, #8, lsl #12 // =32768 ; CHECK-CVT-NEXT: cmn w13, #8, lsl #12 // =32768
; CHECK-CVT-NEXT: csel w13, w13, w10, gt ; CHECK-CVT-NEXT: csel w13, w13, w10, gt
; CHECK-CVT-NEXT: cmp w14, w8 ; CHECK-CVT-NEXT: cmp w14, w8
; CHECK-CVT-NEXT: csel w14, w14, w8, lt ; CHECK-CVT-NEXT: csel w14, w14, w8, lt
; CHECK-CVT-NEXT: fcvtzs w17, s0
; CHECK-CVT-NEXT: cmn w14, #8, lsl #12 // =32768 ; CHECK-CVT-NEXT: cmn w14, #8, lsl #12 // =32768
; CHECK-CVT-NEXT: fmov s0, w11
; CHECK-CVT-NEXT: csel w14, w14, w10, gt ; CHECK-CVT-NEXT: csel w14, w14, w10, gt
; CHECK-CVT-NEXT: cmp w15, w8 ; CHECK-CVT-NEXT: cmp w15, w8
; CHECK-CVT-NEXT: csel w15, w15, w8, lt ; CHECK-CVT-NEXT: csel w15, w15, w8, lt
; CHECK-CVT-NEXT: cmn w15, #8, lsl #12 // =32768 ; CHECK-CVT-NEXT: cmn w15, #8, lsl #12 // =32768
; CHECK-CVT-NEXT: csel w11, w15, w10, gt ; CHECK-CVT-NEXT: mov v0.s[1], w9
; CHECK-CVT-NEXT: fcvtzs w15, s1 ; CHECK-CVT-NEXT: csel w15, w15, w10, gt
; CHECK-CVT-NEXT: mov v2.s[1], w9 ; CHECK-CVT-NEXT: cmp w16, w8
; CHECK-CVT-NEXT: fmov s1, w11 ; CHECK-CVT-NEXT: csel w11, w16, w8, lt
; CHECK-CVT-NEXT: cmp w15, w8 ; CHECK-CVT-NEXT: mov v0.s[2], w12
; CHECK-CVT-NEXT: csel w9, w15, w8, lt ; CHECK-CVT-NEXT: cmn w11, #8, lsl #12 // =32768
; CHECK-CVT-NEXT: fcvtzs w11, s0 ; CHECK-CVT-NEXT: fmov s1, w15
; CHECK-CVT-NEXT: cmn w9, #8, lsl #12 // =32768 ; CHECK-CVT-NEXT: csel w11, w11, w10, gt
; CHECK-CVT-NEXT: cmp w17, w8
; CHECK-CVT-NEXT: mov v0.s[3], w13
; CHECK-CVT-NEXT: csel w8, w17, w8, lt
; CHECK-CVT-NEXT: mov v1.s[1], w14 ; CHECK-CVT-NEXT: mov v1.s[1], w14
; CHECK-CVT-NEXT: csel w9, w9, w10, gt
; CHECK-CVT-NEXT: cmp w11, w8
; CHECK-CVT-NEXT: csel w8, w11, w8, lt
; CHECK-CVT-NEXT: mov v2.s[2], w12
; CHECK-CVT-NEXT: cmn w8, #8, lsl #12 // =32768 ; CHECK-CVT-NEXT: cmn w8, #8, lsl #12 // =32768
; CHECK-CVT-NEXT: mov v1.s[2], w9
; CHECK-CVT-NEXT: csel w8, w8, w10, gt ; CHECK-CVT-NEXT: csel w8, w8, w10, gt
; CHECK-CVT-NEXT: mov v2.s[3], w13 ; CHECK-CVT-NEXT: mov v1.s[2], w11
; CHECK-CVT-NEXT: mov v1.s[3], w8 ; CHECK-CVT-NEXT: mov v1.s[3], w8
; CHECK-CVT-NEXT: uzp1 v0.8h, v1.8h, v2.8h ; CHECK-CVT-NEXT: uzp1 v0.8h, v1.8h, v0.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_signed_v8f16_v8i16: ; CHECK-FP16-LABEL: test_signed_v8f16_v8i16:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h ; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <8 x i16> @llvm.fptosi.sat.v8f16.v8i16(<8 x half> %f) %x = call <8 x i16> @llvm.fptosi.sat.v8f16.v8i16(<8 x half> %f)
ret <8 x i16> %x ret <8 x i16> %x
} }
define <8 x i19> @test_signed_v8f16_v8i19(<8 x half> %f) { define <8 x i19> @test_signed_v8f16_v8i19(<8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i19: ; CHECK-LABEL: test_signed_v8f16_v8i19:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtl v2.4s, v0.4h ; CHECK-NEXT: fcvtl2 v1.4s, v0.8h
; CHECK-NEXT: fcvtl2 v0.4s, v0.8h ; CHECK-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NEXT: movi v1.4s, #3, msl #16 ; CHECK-NEXT: movi v2.4s, #3, msl #16
; CHECK-NEXT: fcvtzs v2.4s, v2.4s ; CHECK-NEXT: fcvtzs v1.4s, v1.4s
; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: smin v2.4s, v2.4s, v1.4s ; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s ; CHECK-NEXT: smin v0.4s, v0.4s, v2.4s
; CHECK-NEXT: mvni v1.4s, #3, msl #16 ; CHECK-NEXT: mvni v2.4s, #3, msl #16
; CHECK-NEXT: smax v2.4s, v2.4s, v1.4s ; CHECK-NEXT: smax v1.4s, v1.4s, v2.4s
; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s ; CHECK-NEXT: smax v0.4s, v0.4s, v2.4s
; CHECK-NEXT: mov w1, v2.s[1] ; CHECK-NEXT: fmov w4, s1
; CHECK-NEXT: mov w2, v2.s[2] ; CHECK-NEXT: mov w5, v1.s[1]
; CHECK-NEXT: mov w5, v0.s[1] ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: mov w3, v2.s[3] ; CHECK-NEXT: mov w6, v1.s[2]
; CHECK-NEXT: mov w6, v0.s[2] ; CHECK-NEXT: mov w7, v1.s[3]
; CHECK-NEXT: mov w7, v0.s[3] ; CHECK-NEXT: mov w1, v0.s[1]
; CHECK-NEXT: fmov w4, s0 ; CHECK-NEXT: mov w2, v0.s[2]
; CHECK-NEXT: fmov w0, s2 ; CHECK-NEXT: mov w3, v0.s[3]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <8 x i19> @llvm.fptosi.sat.v8f16.v8i19(<8 x half> %f) %x = call <8 x i19> @llvm.fptosi.sat.v8f16.v8i19(<8 x half> %f)
ret <8 x i19> %x ret <8 x i19> %x
} }
define <8 x i32> @test_signed_v8f16_v8i32_duplicate(<8 x half> %f) { define <8 x i32> @test_signed_v8f16_v8i32_duplicate(<8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i32_duplicate: ; CHECK-LABEL: test_signed_v8f16_v8i32_duplicate:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
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%x = call <8 x i50> @llvm.fptosi.sat.v8f16.v8i50(<8 x half> %f) %x = call <8 x i50> @llvm.fptosi.sat.v8f16.v8i50(<8 x half> %f)
ret <8 x i50> %x ret <8 x i50> %x
} }
define <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) { define <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
; CHECK-CVT-LABEL: test_signed_v8f16_v8i64: ; CHECK-CVT-LABEL: test_signed_v8f16_v8i64:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-CVT-NEXT: mov h4, v0.h[2] ; CHECK-CVT-NEXT: mov h2, v0.h[2]
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: fcvt s4, h0
; CHECK-CVT-NEXT: fcvt s2, h1 ; CHECK-CVT-NEXT: mov h5, v1.h[2]
; CHECK-CVT-NEXT: fcvt s7, h1
; CHECK-CVT-NEXT: mov h3, v1.h[1] ; CHECK-CVT-NEXT: mov h3, v1.h[1]
; CHECK-CVT-NEXT: mov h6, v1.h[2] ; CHECK-CVT-NEXT: mov h6, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: mov h1, v1.h[3]
; CHECK-CVT-NEXT: fcvtzs x9, s5
; CHECK-CVT-NEXT: fcvtzs x8, s2
; CHECK-CVT-NEXT: fcvt s2, h3
; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: mov h0, v0.h[3] ; CHECK-CVT-NEXT: mov h0, v0.h[3]
; CHECK-CVT-NEXT: fcvt s5, h6 ; CHECK-CVT-NEXT: mov h1, v1.h[3]
; CHECK-CVT-NEXT: fcvt s6, h1 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvtzs x10, s2
; CHECK-CVT-NEXT: fmov d2, x8
; CHECK-CVT-NEXT: fcvtzs x8, s4 ; CHECK-CVT-NEXT: fcvtzs x8, s4
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: fcvtzs x9, s7
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s4, h0 ; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: fmov d0, x9 ; CHECK-CVT-NEXT: fcvt s6, h0
; CHECK-CVT-NEXT: mov v2.d[1], x10 ; CHECK-CVT-NEXT: fcvt s7, h1
; CHECK-CVT-NEXT: fcvtzs x10, s5 ; CHECK-CVT-NEXT: fcvtzs x10, s2
; CHECK-CVT-NEXT: fmov d1, x8 ; CHECK-CVT-NEXT: fmov d2, x9
; CHECK-CVT-NEXT: fcvtzs x9, s3 ; CHECK-CVT-NEXT: fcvtzs x9, s4
; CHECK-CVT-NEXT: fcvtzs x8, s4 ; CHECK-CVT-NEXT: fmov d0, x8
; CHECK-CVT-NEXT: fmov d3, x10 ; CHECK-CVT-NEXT: fcvtzs x11, s3
; CHECK-CVT-NEXT: fcvtzs x8, s5
; CHECK-CVT-NEXT: fmov d1, x10
; CHECK-CVT-NEXT: fcvtzs x10, s6 ; CHECK-CVT-NEXT: fcvtzs x10, s6
; CHECK-CVT-NEXT: mov v0.d[1], x9 ; CHECK-CVT-NEXT: fmov d3, x9
; CHECK-CVT-NEXT: mov v1.d[1], x8 ; CHECK-CVT-NEXT: fcvtzs x9, s7
; CHECK-CVT-NEXT: mov v3.d[1], x10 ; CHECK-CVT-NEXT: mov v0.d[1], x8
; CHECK-CVT-NEXT: mov v2.d[1], x11
; CHECK-CVT-NEXT: mov v1.d[1], x10
; CHECK-CVT-NEXT: mov v3.d[1], x9
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_signed_v8f16_v8i64: ; CHECK-FP16-LABEL: test_signed_v8f16_v8i64:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-FP16-NEXT: ext v2.16b, v0.16b, v0.16b, #8
; CHECK-FP16-NEXT: mov h3, v0.h[2] ; CHECK-FP16-NEXT: mov h1, v0.h[2]
; CHECK-FP16-NEXT: mov h5, v0.h[3] ; CHECK-FP16-NEXT: mov h5, v0.h[3]
; CHECK-FP16-NEXT: fcvtzs x9, h0 ; CHECK-FP16-NEXT: mov h4, v2.h[2]
; CHECK-FP16-NEXT: mov h2, v1.h[1] ; CHECK-FP16-NEXT: fcvtzs x9, h2
; CHECK-FP16-NEXT: mov h3, v2.h[1]
; CHECK-FP16-NEXT: mov h6, v2.h[3]
; CHECK-FP16-NEXT: fcvtzs x8, h1 ; CHECK-FP16-NEXT: fcvtzs x8, h1
; CHECK-FP16-NEXT: mov h4, v1.h[2] ; CHECK-FP16-NEXT: mov h1, v0.h[1]
; CHECK-FP16-NEXT: mov h6, v1.h[3] ; CHECK-FP16-NEXT: fcvtzs x10, h0
; CHECK-FP16-NEXT: fcvtzs x10, h2 ; CHECK-FP16-NEXT: fmov d2, x9
; CHECK-FP16-NEXT: fmov d2, x8 ; CHECK-FP16-NEXT: fcvtzs x9, h4
; CHECK-FP16-NEXT: fcvtzs x8, h3 ; CHECK-FP16-NEXT: fcvtzs x11, h3
; CHECK-FP16-NEXT: mov h3, v0.h[1] ; CHECK-FP16-NEXT: fmov d0, x10
; CHECK-FP16-NEXT: fmov d0, x9 ; CHECK-FP16-NEXT: fcvtzs x10, h1
; CHECK-FP16-NEXT: mov v2.d[1], x10
; CHECK-FP16-NEXT: fcvtzs x10, h4
; CHECK-FP16-NEXT: fmov d1, x8 ; CHECK-FP16-NEXT: fmov d1, x8
; CHECK-FP16-NEXT: fcvtzs x9, h3
; CHECK-FP16-NEXT: fcvtzs x8, h5 ; CHECK-FP16-NEXT: fcvtzs x8, h5
; CHECK-FP16-NEXT: fmov d3, x10 ; CHECK-FP16-NEXT: fmov d3, x9
; CHECK-FP16-NEXT: fcvtzs x10, h6 ; CHECK-FP16-NEXT: fcvtzs x9, h6
; CHECK-FP16-NEXT: mov v0.d[1], x9 ; CHECK-FP16-NEXT: mov v0.d[1], x10
; CHECK-FP16-NEXT: mov v2.d[1], x11
; CHECK-FP16-NEXT: mov v1.d[1], x8 ; CHECK-FP16-NEXT: mov v1.d[1], x8
; CHECK-FP16-NEXT: mov v3.d[1], x10 ; CHECK-FP16-NEXT: mov v3.d[1], x9
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <8 x i64> @llvm.fptosi.sat.v8f16.v8i64(<8 x half> %f) %x = call <8 x i64> @llvm.fptosi.sat.v8f16.v8i64(<8 x half> %f)
ret <8 x i64> %x ret <8 x i64> %x
} }
define <8 x i100> @test_signed_v8f16_v8i100(<8 x half> %f) { define <8 x i100> @test_signed_v8f16_v8i100(<8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i100: ; CHECK-LABEL: test_signed_v8f16_v8i100:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: csel x9, x25, x1, lt ; CHECK-NEXT: csel x9, x25, x1, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: csel x9, x23, x9, gt ; CHECK-NEXT: csel x9, x23, x9, gt
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: fcmp s8, s8 ; CHECK-NEXT: fcmp s8, s8
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csel x20, xzr, x8, vs ; CHECK-NEXT: csel x28, xzr, x8, vs
; CHECK-NEXT: csel x28, xzr, x9, vs ; CHECK-NEXT: csel x26, xzr, x9, vs
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixsfti ; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: fcmp s8, s10 ; CHECK-NEXT: fcmp s8, s10
; CHECK-NEXT: mov h0, v0.h[2] ; CHECK-NEXT: mov h0, v0.h[2]
; CHECK-NEXT: csel x8, x25, x1, lt ; CHECK-NEXT: csel x8, x25, x1, lt
; CHECK-NEXT: csel x9, xzr, x0, lt ; CHECK-NEXT: csel x9, xzr, x0, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: csinv x9, x9, xzr, le ; CHECK-NEXT: csinv x9, x9, xzr, le
; CHECK-NEXT: csel x8, x23, x8, gt ; CHECK-NEXT: csel x8, x23, x8, gt
; CHECK-NEXT: fcmp s8, s8 ; CHECK-NEXT: fcmp s8, s8
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csel x21, xzr, x8, vs ; CHECK-NEXT: csel x21, xzr, x8, vs
; CHECK-NEXT: csel x26, xzr, x9, vs ; CHECK-NEXT: csel x20, xzr, x9, vs
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixsfti ; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: fmov d0, x20
; CHECK-NEXT: fcmp s8, s10 ; CHECK-NEXT: fcmp s8, s10
; CHECK-NEXT: ldr x11, [sp, #8] // 8-byte Folded Reload ; CHECK-NEXT: fmov d0, x28
; CHECK-NEXT: lsr x10, x28, #28
; CHECK-NEXT: ldr d1, [sp] // 8-byte Folded Reload ; CHECK-NEXT: ldr d1, [sp] // 8-byte Folded Reload
; CHECK-NEXT: lsr x12, x29, #28 ; CHECK-NEXT: lsr x10, x26, #28
; CHECK-NEXT: mov v0.d[1], x28 ; CHECK-NEXT: ldr x12, [sp, #8] // 8-byte Folded Reload
; CHECK-NEXT: lsr x11, x29, #28
; CHECK-NEXT: csel x8, x25, x1, lt ; CHECK-NEXT: csel x8, x25, x1, lt
; CHECK-NEXT: csel x9, xzr, x0, lt ; CHECK-NEXT: csel x9, xzr, x0, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: stur x11, [x19, #75] ; CHECK-NEXT: mov v0.d[1], x26
; CHECK-NEXT: ldr x13, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: stur x12, [x19, #75]
; CHECK-NEXT: mov v1.d[1], x29
; CHECK-NEXT: ldr d2, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: fmov x12, d0
; CHECK-NEXT: csinv x9, x9, xzr, le ; CHECK-NEXT: csinv x9, x9, xzr, le
; CHECK-NEXT: csel x8, x23, x8, gt ; CHECK-NEXT: csel x8, x23, x8, gt
; CHECK-NEXT: fcmp s8, s8 ; CHECK-NEXT: fcmp s8, s8
; CHECK-NEXT: fmov x11, d0
; CHECK-NEXT: stur x13, [x19, #50]
; CHECK-NEXT: mov v1.d[1], x29
; CHECK-NEXT: ldr d0, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: csel x9, xzr, x9, vs
; CHECK-NEXT: strb w10, [x19, #49] ; CHECK-NEXT: strb w10, [x19, #49]
; CHECK-NEXT: extr x10, x28, x11, #28 ; CHECK-NEXT: strb w11, [x19, #24]
; CHECK-NEXT: fmov x10, d1
; CHECK-NEXT: extr x11, x26, x12, #28
; CHECK-NEXT: mov v2.d[1], x22
; CHECK-NEXT: csel x9, xzr, x9, vs
; CHECK-NEXT: csel x8, xzr, x8, vs ; CHECK-NEXT: csel x8, xzr, x8, vs
; CHECK-NEXT: bfi x8, x11, #36, #28 ; CHECK-NEXT: bfi x8, x12, #36, #28
; CHECK-NEXT: strb w12, [x19, #24] ; CHECK-NEXT: bfi x21, x10, #36, #28
; CHECK-NEXT: stur x9, [x19, #25] ; CHECK-NEXT: stur x9, [x19, #25]
; CHECK-NEXT: fmov x12, d1 ; CHECK-NEXT: ldr x9, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: stur x10, [x19, #41] ; CHECK-NEXT: stur x11, [x19, #41]
; CHECK-NEXT: lsr x9, x22, #28 ; CHECK-NEXT: stur x9, [x19, #50]
; CHECK-NEXT: ldr d1, [sp, #24] // 8-byte Folded Reload ; CHECK-NEXT: extr x9, x29, x10, #28
; CHECK-NEXT: ldr d0, [sp, #24] // 8-byte Folded Reload
; CHECK-NEXT: stur x8, [x19, #33] ; CHECK-NEXT: stur x8, [x19, #33]
; CHECK-NEXT: fmov x8, d2
; CHECK-NEXT: str x9, [x19, #16]
; CHECK-NEXT: lsr x9, x22, #28
; CHECK-NEXT: ldr x11, [sp, #72] // 8-byte Folded Reload ; CHECK-NEXT: ldr x11, [sp, #72] // 8-byte Folded Reload
; CHECK-NEXT: extr x18, x29, x12, #28 ; CHECK-NEXT: stp x20, x21, [x19]
; CHECK-NEXT: mov v0.d[1], x22 ; CHECK-NEXT: extr x12, x22, x8, #28
; CHECK-NEXT: bfi x21, x12, #36, #28 ; CHECK-NEXT: bfi x27, x8, #36, #28
; CHECK-NEXT: str x26, [x19] ; CHECK-NEXT: strb w9, [x19, #99]
; CHECK-NEXT: mov v1.d[1], x11 ; CHECK-NEXT: mov v0.d[1], x11
; CHECK-NEXT: lsr x10, x11, #28 ; CHECK-NEXT: lsr x10, x11, #28
; CHECK-NEXT: mov x13, x11 ; CHECK-NEXT: mov x13, x11
; CHECK-NEXT: stp x21, x18, [x19, #8] ; CHECK-NEXT: stur x12, [x19, #91]
; CHECK-NEXT: fmov x8, d0 ; CHECK-NEXT: fmov x11, d0
; CHECK-NEXT: strb w9, [x19, #99] ; CHECK-NEXT: stur x27, [x19, #83]
; CHECK-NEXT: strb w10, [x19, #74] ; CHECK-NEXT: strb w10, [x19, #74]
; CHECK-NEXT: fmov x11, d1
; CHECK-NEXT: extr x12, x22, x8, #28
; CHECK-NEXT: bfi x27, x8, #36, #28
; CHECK-NEXT: extr x8, x13, x11, #28 ; CHECK-NEXT: extr x8, x13, x11, #28
; CHECK-NEXT: bfi x24, x11, #36, #28 ; CHECK-NEXT: bfi x24, x11, #36, #28
; CHECK-NEXT: stur x12, [x19, #91]
; CHECK-NEXT: stur x27, [x19, #83]
; CHECK-NEXT: stur x8, [x19, #66] ; CHECK-NEXT: stur x8, [x19, #66]
; CHECK-NEXT: stur x24, [x19, #58] ; CHECK-NEXT: stur x24, [x19, #58]
; CHECK-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #160] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #160] // 16-byte Folded Reload
; CHECK-NEXT: ldp x24, x23, [sp, #144] // 16-byte Folded Reload ; CHECK-NEXT: ldp x24, x23, [sp, #144] // 16-byte Folded Reload
; CHECK-NEXT: ldp x26, x25, [sp, #128] // 16-byte Folded Reload ; CHECK-NEXT: ldp x26, x25, [sp, #128] // 16-byte Folded Reload
; CHECK-NEXT: ldp x28, x27, [sp, #112] // 16-byte Folded Reload ; CHECK-NEXT: ldp x28, x27, [sp, #112] // 16-byte Folded Reload
; CHECK-NEXT: ldp x29, x30, [sp, #96] // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp, #96] // 16-byte Folded Reload
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declare <8 x i8> @llvm.fptosi.sat.v8f64.v8i8(<8 x double> %f) declare <8 x i8> @llvm.fptosi.sat.v8f64.v8i8(<8 x double> %f)
declare <8 x i16> @llvm.fptosi.sat.v8f64.v8i16(<8 x double> %f) declare <8 x i16> @llvm.fptosi.sat.v8f64.v8i16(<8 x double> %f)
declare <16 x i8> @llvm.fptosi.sat.v16f64.v16i8(<16 x double> %f) declare <16 x i8> @llvm.fptosi.sat.v16f64.v16i8(<16 x double> %f)
declare <16 x i16> @llvm.fptosi.sat.v16f64.v16i16(<16 x double> %f) declare <16 x i16> @llvm.fptosi.sat.v16f64.v16i16(<16 x double> %f)
define <8 x i8> @test_signed_v8f32_v8i8(<8 x float> %f) { define <8 x i8> @test_signed_v8f32_v8i8(<8 x float> %f) {
; CHECK-LABEL: test_signed_v8f32_v8i8: ; CHECK-LABEL: test_signed_v8f32_v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.4s, #127
; CHECK-NEXT: fcvtzs v1.4s, v1.4s ; CHECK-NEXT: fcvtzs v1.4s, v1.4s
; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: movi v2.4s, #127
; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s ; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
; CHECK-NEXT: smin v0.4s, v0.4s, v2.4s ; CHECK-NEXT: smin v0.4s, v0.4s, v2.4s
; CHECK-NEXT: mvni v2.4s, #127 ; CHECK-NEXT: mvni v2.4s, #127
; CHECK-NEXT: smax v1.4s, v1.4s, v2.4s ; CHECK-NEXT: smax v1.4s, v1.4s, v2.4s
; CHECK-NEXT: smax v0.4s, v0.4s, v2.4s ; CHECK-NEXT: smax v0.4s, v0.4s, v2.4s
; CHECK-NEXT: xtn v1.4h, v1.4s ; CHECK-NEXT: xtn v1.4h, v1.4s
; CHECK-NEXT: xtn v0.4h, v0.4s ; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: uzp1 v0.8b, v0.8b, v1.8b ; CHECK-NEXT: uzp1 v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <8 x i8> @llvm.fptosi.sat.v8f32.v8i8(<8 x float> %f) %x = call <8 x i8> @llvm.fptosi.sat.v8f32.v8i8(<8 x float> %f)
ret <8 x i8> %x ret <8 x i8> %x
} }
define <16 x i8> @test_signed_v16f32_v16i8(<16 x float> %f) { define <16 x i8> @test_signed_v16f32_v16i8(<16 x float> %f) {
; CHECK-LABEL: test_signed_v16f32_v16i8: ; CHECK-LABEL: test_signed_v16f32_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v4.4s, #127
; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: mvni v5.4s, #127
; CHECK-NEXT: fcvtzs v1.4s, v1.4s ; CHECK-NEXT: fcvtzs v1.4s, v1.4s
; CHECK-NEXT: movi v4.4s, #127
; CHECK-NEXT: fcvtzs v2.4s, v2.4s ; CHECK-NEXT: fcvtzs v2.4s, v2.4s
; CHECK-NEXT: mvni v5.4s, #127
; CHECK-NEXT: fcvtzs v3.4s, v3.4s
; CHECK-NEXT: smin v0.4s, v0.4s, v4.4s ; CHECK-NEXT: smin v0.4s, v0.4s, v4.4s
; CHECK-NEXT: smin v1.4s, v1.4s, v4.4s ; CHECK-NEXT: smin v1.4s, v1.4s, v4.4s
; CHECK-NEXT: smin v2.4s, v2.4s, v4.4s ; CHECK-NEXT: smin v2.4s, v2.4s, v4.4s
; CHECK-NEXT: smin v3.4s, v3.4s, v4.4s
; CHECK-NEXT: smax v0.4s, v0.4s, v5.4s ; CHECK-NEXT: smax v0.4s, v0.4s, v5.4s
; CHECK-NEXT: smax v1.4s, v1.4s, v5.4s ; CHECK-NEXT: smax v1.4s, v1.4s, v5.4s
; CHECK-NEXT: smax v2.4s, v2.4s, v5.4s ; CHECK-NEXT: smax v2.4s, v2.4s, v5.4s
; CHECK-NEXT: xtn v6.4h, v0.4s ; CHECK-NEXT: smax v3.4s, v3.4s, v5.4s
; CHECK-NEXT: umov w8, v6.h[0] ; CHECK-NEXT: xtn v4.4h, v0.4s
; CHECK-NEXT: umov w9, v6.h[1]
; CHECK-NEXT: xtn v1.4h, v1.4s ; CHECK-NEXT: xtn v1.4h, v1.4s
; CHECK-NEXT: umov w8, v4.h[0]
; CHECK-NEXT: umov w9, v4.h[2]
; CHECK-NEXT: xtn v2.4h, v2.4s
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: umov w8, v6.h[2] ; CHECK-NEXT: umov w8, v4.h[1]
; CHECK-NEXT: mov v0.b[1], w9 ; CHECK-NEXT: mov v0.b[1], w8
; CHECK-NEXT: mov v0.b[2], w8 ; CHECK-NEXT: umov w8, v4.h[3]
; CHECK-NEXT: umov w8, v6.h[3] ; CHECK-NEXT: mov v0.b[2], w9
; CHECK-NEXT: umov w9, v1.h[0]
; CHECK-NEXT: mov v0.b[3], w8 ; CHECK-NEXT: mov v0.b[3], w8
; CHECK-NEXT: umov w8, v1.h[0]
; CHECK-NEXT: mov v0.b[4], w8
; CHECK-NEXT: umov w8, v1.h[1] ; CHECK-NEXT: umov w8, v1.h[1]
; CHECK-NEXT: mov v0.b[4], w9
; CHECK-NEXT: umov w9, v1.h[2]
; CHECK-NEXT: mov v0.b[5], w8 ; CHECK-NEXT: mov v0.b[5], w8
; CHECK-NEXT: umov w8, v1.h[2]
; CHECK-NEXT: mov v0.b[6], w8
; CHECK-NEXT: umov w8, v1.h[3] ; CHECK-NEXT: umov w8, v1.h[3]
; CHECK-NEXT: xtn v1.4h, v2.4s ; CHECK-NEXT: xtn v1.4h, v3.4s
; CHECK-NEXT: fcvtzs v2.4s, v3.4s ; CHECK-NEXT: mov v0.b[6], w9
; CHECK-NEXT: umov w9, v2.h[0]
; CHECK-NEXT: mov v0.b[7], w8 ; CHECK-NEXT: mov v0.b[7], w8
; CHECK-NEXT: umov w8, v1.h[0] ; CHECK-NEXT: umov w8, v2.h[1]
; CHECK-NEXT: smin v2.4s, v2.4s, v4.4s ; CHECK-NEXT: mov v0.b[8], w9
; CHECK-NEXT: mov v0.b[8], w8 ; CHECK-NEXT: umov w9, v2.h[2]
; CHECK-NEXT: umov w8, v1.h[1]
; CHECK-NEXT: smax v2.4s, v2.4s, v5.4s
; CHECK-NEXT: mov v0.b[9], w8 ; CHECK-NEXT: mov v0.b[9], w8
; CHECK-NEXT: umov w8, v1.h[2] ; CHECK-NEXT: umov w8, v2.h[3]
; CHECK-NEXT: mov v0.b[10], w8 ; CHECK-NEXT: mov v0.b[10], w9
; CHECK-NEXT: umov w8, v1.h[3]
; CHECK-NEXT: xtn v1.4h, v2.4s
; CHECK-NEXT: mov v0.b[11], w8 ; CHECK-NEXT: mov v0.b[11], w8
; CHECK-NEXT: umov w8, v1.h[0] ; CHECK-NEXT: umov w8, v1.h[0]
; CHECK-NEXT: mov v0.b[12], w8 ; CHECK-NEXT: mov v0.b[12], w8
; CHECK-NEXT: umov w8, v1.h[1] ; CHECK-NEXT: umov w8, v1.h[1]
; CHECK-NEXT: mov v0.b[13], w8 ; CHECK-NEXT: mov v0.b[13], w8
; CHECK-NEXT: umov w8, v1.h[2] ; CHECK-NEXT: umov w8, v1.h[2]
; CHECK-NEXT: mov v0.b[14], w8 ; CHECK-NEXT: mov v0.b[14], w8
; CHECK-NEXT: umov w8, v1.h[3] ; CHECK-NEXT: umov w8, v1.h[3]
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <8 x i16> @llvm.fptosi.sat.v8f32.v8i16(<8 x float> %f) %x = call <8 x i16> @llvm.fptosi.sat.v8f32.v8i16(<8 x float> %f)
ret <8 x i16> %x ret <8 x i16> %x
} }
define <16 x i16> @test_signed_v16f32_v16i16(<16 x float> %f) { define <16 x i16> @test_signed_v16f32_v16i16(<16 x float> %f) {
; CHECK-LABEL: test_signed_v16f32_v16i16: ; CHECK-LABEL: test_signed_v16f32_v16i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: fcvtzs v2.4s, v2.4s ; CHECK-NEXT: fcvtzs v2.4s, v2.4s
; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: fcvtzs v4.4s, v1.4s ; CHECK-NEXT: fcvtzs v4.4s, v1.4s
; CHECK-NEXT: fcvtzs v3.4s, v3.4s ; CHECK-NEXT: fcvtzs v3.4s, v3.4s
; CHECK-NEXT: sqxtn v0.4h, v0.4s ; CHECK-NEXT: sqxtn v0.4h, v0.4s
; CHECK-NEXT: sqxtn v1.4h, v2.4s ; CHECK-NEXT: sqxtn v1.4h, v2.4s
; CHECK-NEXT: sqxtn2 v0.8h, v4.4s ; CHECK-NEXT: sqxtn2 v0.8h, v4.4s
; CHECK-NEXT: sqxtn2 v1.8h, v3.4s ; CHECK-NEXT: sqxtn2 v1.8h, v3.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <16 x i16> @llvm.fptosi.sat.v16f32.v16i16(<16 x float> %f) %x = call <16 x i16> @llvm.fptosi.sat.v16f32.v16i16(<16 x float> %f)
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; CHECK-CVT-NEXT: fcvtzs w1, s1 ; CHECK-CVT-NEXT: fcvtzs w1, s1
; CHECK-CVT-NEXT: cmn w18, #128 ; CHECK-CVT-NEXT: cmn w18, #128
; CHECK-CVT-NEXT: mov s1, v0.s[1] ; CHECK-CVT-NEXT: mov s1, v0.s[1]
; CHECK-CVT-NEXT: csel w18, w18, w9, gt ; CHECK-CVT-NEXT: csel w18, w18, w9, gt
; CHECK-CVT-NEXT: cmp w0, #127 ; CHECK-CVT-NEXT: cmp w0, #127
; CHECK-CVT-NEXT: csel w0, w0, w8, lt ; CHECK-CVT-NEXT: csel w0, w0, w8, lt
; CHECK-CVT-NEXT: fcvtzs w2, s2 ; CHECK-CVT-NEXT: fcvtzs w2, s2
; CHECK-CVT-NEXT: cmn w0, #128 ; CHECK-CVT-NEXT: cmn w0, #128
; CHECK-CVT-NEXT: fcvtzs w4, s0 ; CHECK-CVT-NEXT: mov s2, v0.s[2]
; CHECK-CVT-NEXT: csel w0, w0, w9, gt ; CHECK-CVT-NEXT: csel w0, w0, w9, gt
; CHECK-CVT-NEXT: cmp w1, #127 ; CHECK-CVT-NEXT: cmp w1, #127
; CHECK-CVT-NEXT: csel w1, w1, w8, lt ; CHECK-CVT-NEXT: csel w1, w1, w8, lt
; CHECK-CVT-NEXT: fcvtzs w3, s1 ; CHECK-CVT-NEXT: fcvtzs w3, s1
; CHECK-CVT-NEXT: cmn w1, #128 ; CHECK-CVT-NEXT: cmn w1, #128
; CHECK-CVT-NEXT: mov s1, v0.s[2] ; CHECK-CVT-NEXT: fmov s1, w11
; CHECK-CVT-NEXT: csel w1, w1, w9, gt ; CHECK-CVT-NEXT: csel w1, w1, w9, gt
; CHECK-CVT-NEXT: cmp w2, #127 ; CHECK-CVT-NEXT: cmp w2, #127
; CHECK-CVT-NEXT: csel w2, w2, w8, lt ; CHECK-CVT-NEXT: csel w11, w2, w8, lt
; CHECK-CVT-NEXT: fmov s2, w11 ; CHECK-CVT-NEXT: fcvtzs w2, s0
; CHECK-CVT-NEXT: cmn w2, #128 ; CHECK-CVT-NEXT: cmn w11, #128
; CHECK-CVT-NEXT: fmov s3, w14 ; CHECK-CVT-NEXT: mov v1.s[1], w10
; CHECK-CVT-NEXT: csel w2, w2, w9, gt ; CHECK-CVT-NEXT: csel w11, w11, w9, gt
; CHECK-CVT-NEXT: cmp w3, #127 ; CHECK-CVT-NEXT: cmp w3, #127
; CHECK-CVT-NEXT: csel w3, w3, w8, lt ; CHECK-CVT-NEXT: csel w3, w3, w8, lt
; CHECK-CVT-NEXT: fcvtzs w14, s1
; CHECK-CVT-NEXT: cmn w3, #128
; CHECK-CVT-NEXT: mov s0, v0.s[3] ; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: csel w3, w3, w9, gt ; CHECK-CVT-NEXT: cmn w3, #128
; CHECK-CVT-NEXT: cmp w4, #127 ; CHECK-CVT-NEXT: fmov s3, w14
; CHECK-CVT-NEXT: csel w11, w4, w8, lt ; CHECK-CVT-NEXT: csel w10, w3, w9, gt
; CHECK-CVT-NEXT: fmov s4, w0 ; CHECK-CVT-NEXT: cmp w2, #127
; CHECK-CVT-NEXT: cmn w11, #128 ; CHECK-CVT-NEXT: csel w14, w2, w8, lt
; CHECK-CVT-NEXT: csel w11, w11, w9, gt ; CHECK-CVT-NEXT: fcvtzs w2, s2
; CHECK-CVT-NEXT: cmn w14, #128
; CHECK-CVT-NEXT: mov v1.s[2], w13
; CHECK-CVT-NEXT: csel w13, w14, w9, gt
; CHECK-CVT-NEXT: fcvtzs w14, s0
; CHECK-CVT-NEXT: cmp w2, #127
; CHECK-CVT-NEXT: mov v3.s[1], w15
; CHECK-CVT-NEXT: csel w15, w2, w8, lt
; CHECK-CVT-NEXT: fmov s0, w0
; CHECK-CVT-NEXT: fmov s2, w13
; CHECK-CVT-NEXT: cmn w15, #128
; CHECK-CVT-NEXT: csel w13, w15, w9, gt
; CHECK-CVT-NEXT: cmp w14, #127 ; CHECK-CVT-NEXT: cmp w14, #127
; CHECK-CVT-NEXT: csel w8, w14, w8, lt
; CHECK-CVT-NEXT: mov v0.s[1], w18
; CHECK-CVT-NEXT: mov v2.s[1], w10 ; CHECK-CVT-NEXT: mov v2.s[1], w10
; CHECK-CVT-NEXT: csel w10, w14, w8, lt
; CHECK-CVT-NEXT: mov v3.s[1], w15
; CHECK-CVT-NEXT: cmn w10, #128
; CHECK-CVT-NEXT: fmov s1, w11
; CHECK-CVT-NEXT: csel w10, w10, w9, gt
; CHECK-CVT-NEXT: fcvtzs w11, s0
; CHECK-CVT-NEXT: mov v4.s[1], w18
; CHECK-CVT-NEXT: mov v1.s[1], w3
; CHECK-CVT-NEXT: cmp w11, #127
; CHECK-CVT-NEXT: csel w8, w11, w8, lt
; CHECK-CVT-NEXT: mov v2.s[2], w13
; CHECK-CVT-NEXT: cmn w8, #128 ; CHECK-CVT-NEXT: cmn w8, #128
; CHECK-CVT-NEXT: mov v3.s[2], w16
; CHECK-CVT-NEXT: csel w8, w8, w9, gt ; CHECK-CVT-NEXT: csel w8, w8, w9, gt
; CHECK-CVT-NEXT: mov v4.s[2], w1 ; CHECK-CVT-NEXT: mov v3.s[2], w16
; CHECK-CVT-NEXT: mov v1.s[2], w10 ; CHECK-CVT-NEXT: mov v0.s[2], w1
; CHECK-CVT-NEXT: mov v2.s[3], w12 ; CHECK-CVT-NEXT: mov v2.s[2], w13
; CHECK-CVT-NEXT: mov v1.s[3], w12
; CHECK-CVT-NEXT: mov v3.s[3], w17 ; CHECK-CVT-NEXT: mov v3.s[3], w17
; CHECK-CVT-NEXT: mov v4.s[3], w2 ; CHECK-CVT-NEXT: mov v0.s[3], w11
; CHECK-CVT-NEXT: mov v1.s[3], w8 ; CHECK-CVT-NEXT: mov v2.s[3], w8
; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v2.8h ; CHECK-CVT-NEXT: uzp1 v1.8h, v3.8h, v1.8h
; CHECK-CVT-NEXT: uzp1 v1.8h, v1.8h, v4.8h ; CHECK-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
; CHECK-CVT-NEXT: uzp1 v0.16b, v1.16b, v0.16b ; CHECK-CVT-NEXT: uzp1 v0.16b, v0.16b, v1.16b
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_signed_v16f16_v16i8: ; CHECK-FP16-LABEL: test_signed_v16f16_v16i8:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h ; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
; CHECK-FP16-NEXT: fcvtzs v1.8h, v1.8h ; CHECK-FP16-NEXT: fcvtzs v1.8h, v1.8h
; CHECK-FP16-NEXT: sqxtn v0.8b, v0.8h ; CHECK-FP16-NEXT: sqxtn v0.8b, v0.8h
; CHECK-FP16-NEXT: sqxtn2 v0.16b, v1.8h ; CHECK-FP16-NEXT: sqxtn2 v0.16b, v1.8h
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; CHECK-CVT-NEXT: fcvtzs w1, s1 ; CHECK-CVT-NEXT: fcvtzs w1, s1
; CHECK-CVT-NEXT: cmn w18, #8, lsl #12 // =32768 ; CHECK-CVT-NEXT: cmn w18, #8, lsl #12 // =32768
; CHECK-CVT-NEXT: mov s1, v0.s[1] ; CHECK-CVT-NEXT: mov s1, v0.s[1]
; CHECK-CVT-NEXT: csel w18, w18, w9, gt ; CHECK-CVT-NEXT: csel w18, w18, w9, gt
; CHECK-CVT-NEXT: cmp w0, w8 ; CHECK-CVT-NEXT: cmp w0, w8
; CHECK-CVT-NEXT: csel w0, w0, w8, lt ; CHECK-CVT-NEXT: csel w0, w0, w8, lt
; CHECK-CVT-NEXT: fcvtzs w2, s2 ; CHECK-CVT-NEXT: fcvtzs w2, s2
; CHECK-CVT-NEXT: cmn w0, #8, lsl #12 // =32768 ; CHECK-CVT-NEXT: cmn w0, #8, lsl #12 // =32768
; CHECK-CVT-NEXT: fcvtzs w4, s0 ; CHECK-CVT-NEXT: mov s2, v0.s[2]
; CHECK-CVT-NEXT: csel w0, w0, w9, gt ; CHECK-CVT-NEXT: csel w0, w0, w9, gt
; CHECK-CVT-NEXT: cmp w1, w8 ; CHECK-CVT-NEXT: cmp w1, w8
; CHECK-CVT-NEXT: csel w1, w1, w8, lt ; CHECK-CVT-NEXT: csel w1, w1, w8, lt
; CHECK-CVT-NEXT: fcvtzs w3, s1 ; CHECK-CVT-NEXT: fcvtzs w3, s1
; CHECK-CVT-NEXT: cmn w1, #8, lsl #12 // =32768 ; CHECK-CVT-NEXT: cmn w1, #8, lsl #12 // =32768
; CHECK-CVT-NEXT: mov s1, v0.s[2] ; CHECK-CVT-NEXT: fmov s1, w11
; CHECK-CVT-NEXT: csel w1, w1, w9, gt ; CHECK-CVT-NEXT: csel w1, w1, w9, gt
; CHECK-CVT-NEXT: cmp w2, w8 ; CHECK-CVT-NEXT: cmp w2, w8
; CHECK-CVT-NEXT: csel w2, w2, w8, lt ; CHECK-CVT-NEXT: csel w11, w2, w8, lt
; CHECK-CVT-NEXT: fmov s2, w11 ; CHECK-CVT-NEXT: fcvtzs w2, s0
; CHECK-CVT-NEXT: cmn w2, #8, lsl #12 // =32768 ; CHECK-CVT-NEXT: cmn w11, #8, lsl #12 // =32768
; CHECK-CVT-NEXT: fmov s3, w14 ; CHECK-CVT-NEXT: mov v1.s[1], w10
; CHECK-CVT-NEXT: csel w2, w2, w9, gt ; CHECK-CVT-NEXT: csel w11, w11, w9, gt
; CHECK-CVT-NEXT: cmp w3, w8 ; CHECK-CVT-NEXT: cmp w3, w8
; CHECK-CVT-NEXT: csel w3, w3, w8, lt ; CHECK-CVT-NEXT: csel w3, w3, w8, lt
; CHECK-CVT-NEXT: fcvtzs w14, s1
; CHECK-CVT-NEXT: cmn w3, #8, lsl #12 // =32768
; CHECK-CVT-NEXT: mov s0, v0.s[3] ; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: csel w3, w3, w9, gt ; CHECK-CVT-NEXT: cmn w3, #8, lsl #12 // =32768
; CHECK-CVT-NEXT: cmp w4, w8 ; CHECK-CVT-NEXT: fmov s3, w14
; CHECK-CVT-NEXT: csel w11, w4, w8, lt ; CHECK-CVT-NEXT: csel w10, w3, w9, gt
; CHECK-CVT-NEXT: fmov s4, w0 ; CHECK-CVT-NEXT: cmp w2, w8
; CHECK-CVT-NEXT: cmn w11, #8, lsl #12 // =32768 ; CHECK-CVT-NEXT: csel w14, w2, w8, lt
; CHECK-CVT-NEXT: csel w11, w11, w9, gt ; CHECK-CVT-NEXT: fcvtzs w2, s2
; CHECK-CVT-NEXT: cmp w14, w8 ; CHECK-CVT-NEXT: cmn w14, #8, lsl #12 // =32768
; CHECK-CVT-NEXT: mov v2.s[1], w10 ; CHECK-CVT-NEXT: mov v1.s[2], w13
; CHECK-CVT-NEXT: csel w10, w14, w8, lt ; CHECK-CVT-NEXT: csel w13, w14, w9, gt
; CHECK-CVT-NEXT: fcvtzs w14, s0
; CHECK-CVT-NEXT: cmp w2, w8
; CHECK-CVT-NEXT: mov v3.s[1], w15 ; CHECK-CVT-NEXT: mov v3.s[1], w15
; CHECK-CVT-NEXT: cmn w10, #8, lsl #12 // =32768 ; CHECK-CVT-NEXT: csel w15, w2, w8, lt
; CHECK-CVT-NEXT: fmov s1, w11 ; CHECK-CVT-NEXT: fmov s2, w0
; CHECK-CVT-NEXT: csel w10, w10, w9, gt ; CHECK-CVT-NEXT: fmov s4, w13
; CHECK-CVT-NEXT: fcvtzs w11, s0 ; CHECK-CVT-NEXT: cmn w15, #8, lsl #12 // =32768
; CHECK-CVT-NEXT: mov v4.s[1], w18 ; CHECK-CVT-NEXT: csel w13, w15, w9, gt
; CHECK-CVT-NEXT: mov v1.s[1], w3 ; CHECK-CVT-NEXT: cmp w14, w8
; CHECK-CVT-NEXT: cmp w11, w8 ; CHECK-CVT-NEXT: csel w8, w14, w8, lt
; CHECK-CVT-NEXT: csel w8, w11, w8, lt ; CHECK-CVT-NEXT: mov v2.s[1], w18
; CHECK-CVT-NEXT: mov v2.s[2], w13 ; CHECK-CVT-NEXT: mov v4.s[1], w10
; CHECK-CVT-NEXT: cmn w8, #8, lsl #12 // =32768 ; CHECK-CVT-NEXT: cmn w8, #8, lsl #12 // =32768
; CHECK-CVT-NEXT: mov v3.s[2], w16
; CHECK-CVT-NEXT: csel w8, w8, w9, gt ; CHECK-CVT-NEXT: csel w8, w8, w9, gt
; CHECK-CVT-NEXT: mov v4.s[2], w1 ; CHECK-CVT-NEXT: mov v3.s[2], w16
; CHECK-CVT-NEXT: mov v1.s[2], w10 ; CHECK-CVT-NEXT: mov v2.s[2], w1
; CHECK-CVT-NEXT: mov v2.s[3], w12 ; CHECK-CVT-NEXT: mov v4.s[2], w13
; CHECK-CVT-NEXT: mov v1.s[3], w12
; CHECK-CVT-NEXT: mov v3.s[3], w17 ; CHECK-CVT-NEXT: mov v3.s[3], w17
; CHECK-CVT-NEXT: mov v4.s[3], w2 ; CHECK-CVT-NEXT: mov v2.s[3], w11
; CHECK-CVT-NEXT: mov v1.s[3], w8 ; CHECK-CVT-NEXT: mov v4.s[3], w8
; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v2.8h ; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v1.8h
; CHECK-CVT-NEXT: uzp1 v1.8h, v1.8h, v4.8h ; CHECK-CVT-NEXT: uzp1 v1.8h, v4.8h, v2.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_signed_v16f16_v16i16: ; CHECK-FP16-LABEL: test_signed_v16f16_v16i16:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h ; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
; CHECK-FP16-NEXT: fcvtzs v1.8h, v1.8h ; CHECK-FP16-NEXT: fcvtzs v1.8h, v1.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <16 x i16> @llvm.fptosi.sat.v16f16.v16i16(<16 x half> %f) %x = call <16 x i16> @llvm.fptosi.sat.v16f16.v16i16(<16 x half> %f)
ret <16 x i16> %x ret <16 x i16> %x
} }
define <8 x i8> @test_signed_v8f64_v8i8(<8 x double> %f) { define <8 x i8> @test_signed_v8f64_v8i8(<8 x double> %f) {
; CHECK-LABEL: test_signed_v8f64_v8i8: ; CHECK-LABEL: test_signed_v8f64_v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d4, v0.d[1] ; CHECK-NEXT: mov d4, v0.d[1]
; CHECK-NEXT: mov w8, #127 ; CHECK-NEXT: mov w8, #127
; CHECK-NEXT: fcvtzs w11, d0 ; CHECK-NEXT: fcvtzs w11, d0
; CHECK-NEXT: mov w9, #-128 ; CHECK-NEXT: mov w9, #-128
; CHECK-NEXT: mov d0, v2.d[1] ; CHECK-NEXT: mov d0, v2.d[1]
; CHECK-NEXT: fcvtzs w13, d1 ; CHECK-NEXT: fcvtzs w13, d1
; CHECK-NEXT: fcvtzs w15, d3 ; CHECK-NEXT: fcvtzs w15, d2
; CHECK-NEXT: fcvtzs w10, d4 ; CHECK-NEXT: fcvtzs w10, d4
; CHECK-NEXT: mov d4, v1.d[1] ; CHECK-NEXT: mov d4, v1.d[1]
; CHECK-NEXT: mov d1, v3.d[1]
; CHECK-NEXT: fcvtzs w14, d0 ; CHECK-NEXT: fcvtzs w14, d0
; CHECK-NEXT: mov d0, v3.d[1]
; CHECK-NEXT: cmp w10, #127 ; CHECK-NEXT: cmp w10, #127
; CHECK-NEXT: csel w10, w10, w8, lt ; CHECK-NEXT: csel w10, w10, w8, lt
; CHECK-NEXT: fcvtzs w12, d4 ; CHECK-NEXT: fcvtzs w12, d4
; CHECK-NEXT: cmn w10, #128 ; CHECK-NEXT: cmn w10, #128
; CHECK-NEXT: csel w10, w10, w9, gt ; CHECK-NEXT: csel w10, w10, w9, gt
; CHECK-NEXT: cmp w11, #127 ; CHECK-NEXT: cmp w11, #127
; CHECK-NEXT: csel w11, w11, w8, lt ; CHECK-NEXT: csel w11, w11, w8, lt
; CHECK-NEXT: fcvtzs w16, d0
; CHECK-NEXT: cmn w11, #128 ; CHECK-NEXT: cmn w11, #128
; CHECK-NEXT: csel w11, w11, w9, gt ; CHECK-NEXT: csel w11, w11, w9, gt
; CHECK-NEXT: cmp w12, #127 ; CHECK-NEXT: cmp w12, #127
; CHECK-NEXT: csel w12, w12, w8, lt ; CHECK-NEXT: csel w12, w12, w8, lt
; CHECK-NEXT: cmn w12, #128 ; CHECK-NEXT: cmn w12, #128
; CHECK-NEXT: csel w12, w12, w9, gt ; CHECK-NEXT: csel w12, w12, w9, gt
; CHECK-NEXT: cmp w13, #127 ; CHECK-NEXT: cmp w13, #127
; CHECK-NEXT: csel w13, w13, w8, lt
; CHECK-NEXT: fmov s0, w11 ; CHECK-NEXT: fmov s0, w11
; CHECK-NEXT: csel w11, w13, w8, lt ; CHECK-NEXT: cmn w13, #128
; CHECK-NEXT: cmn w11, #128 ; CHECK-NEXT: csel w13, w13, w9, gt
; CHECK-NEXT: fcvtzs w13, d2
; CHECK-NEXT: csel w11, w11, w9, gt
; CHECK-NEXT: cmp w14, #127 ; CHECK-NEXT: cmp w14, #127
; CHECK-NEXT: csel w14, w14, w8, lt
; CHECK-NEXT: mov v0.s[1], w10 ; CHECK-NEXT: mov v0.s[1], w10
; CHECK-NEXT: csel w10, w14, w8, lt ; CHECK-NEXT: cmn w14, #128
; CHECK-NEXT: csel w14, w14, w9, gt
; CHECK-NEXT: cmp w15, #127
; CHECK-NEXT: csel w15, w15, w8, lt
; CHECK-NEXT: fmov s1, w13
; CHECK-NEXT: cmn w15, #128
; CHECK-NEXT: fcvtzs w13, d3
; CHECK-NEXT: csel w11, w15, w9, gt
; CHECK-NEXT: cmp w16, #127
; CHECK-NEXT: csel w10, w16, w8, lt
; CHECK-NEXT: mov v1.s[1], w12
; CHECK-NEXT: cmn w10, #128 ; CHECK-NEXT: cmn w10, #128
; CHECK-NEXT: fmov s2, w11
; CHECK-NEXT: csel w10, w10, w9, gt ; CHECK-NEXT: csel w10, w10, w9, gt
; CHECK-NEXT: cmp w13, #127 ; CHECK-NEXT: cmp w13, #127
; CHECK-NEXT: csel w8, w13, w8, lt
; CHECK-NEXT: fmov s2, w11
; CHECK-NEXT: mov w11, v0.s[1] ; CHECK-NEXT: mov w11, v0.s[1]
; CHECK-NEXT: csel w13, w13, w8, lt
; CHECK-NEXT: mov v2.s[1], w12
; CHECK-NEXT: cmn w13, #128
; CHECK-NEXT: fcvtzs w12, d1
; CHECK-NEXT: csel w13, w13, w9, gt
; CHECK-NEXT: mov v0.b[1], w11
; CHECK-NEXT: fmov w14, s2
; CHECK-NEXT: cmp w12, #127
; CHECK-NEXT: fmov s1, w13
; CHECK-NEXT: csel w12, w12, w8, lt
; CHECK-NEXT: cmn w12, #128
; CHECK-NEXT: mov w11, v2.s[1]
; CHECK-NEXT: mov v0.b[2], w14
; CHECK-NEXT: csel w12, w12, w9, gt
; CHECK-NEXT: cmp w15, #127
; CHECK-NEXT: mov v1.s[1], w10
; CHECK-NEXT: csel w8, w15, w8, lt
; CHECK-NEXT: cmn w8, #128 ; CHECK-NEXT: cmn w8, #128
; CHECK-NEXT: csel w8, w8, w9, gt ; CHECK-NEXT: csel w8, w8, w9, gt
; CHECK-NEXT: mov v0.b[3], w11
; CHECK-NEXT: fmov w9, s1 ; CHECK-NEXT: fmov w9, s1
; CHECK-NEXT: fmov s2, w8 ; CHECK-NEXT: mov v0.b[1], w11
; CHECK-NEXT: mov w8, v1.s[1] ; CHECK-NEXT: mov v2.s[1], w14
; CHECK-NEXT: mov v0.b[4], w9 ; CHECK-NEXT: mov w11, v1.s[1]
; CHECK-NEXT: mov v2.s[1], w12 ; CHECK-NEXT: mov v0.b[2], w9
; CHECK-NEXT: mov v0.b[5], w8 ; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: fmov w8, s2 ; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: mov w9, v2.s[1] ; CHECK-NEXT: mov w9, v2.s[1]
; CHECK-NEXT: mov v0.b[3], w11
; CHECK-NEXT: mov v1.s[1], w10
; CHECK-NEXT: mov v0.b[4], w8
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov v0.b[5], w9
; CHECK-NEXT: mov w9, v1.s[1]
; CHECK-NEXT: mov v0.b[6], w8 ; CHECK-NEXT: mov v0.b[6], w8
; CHECK-NEXT: mov v0.b[7], w9 ; CHECK-NEXT: mov v0.b[7], w9
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <8 x i8> @llvm.fptosi.sat.v8f64.v8i8(<8 x double> %f) %x = call <8 x i8> @llvm.fptosi.sat.v8f64.v8i8(<8 x double> %f)
ret <8 x i8> %x ret <8 x i8> %x
} }
define <16 x i8> @test_signed_v16f64_v16i8(<16 x double> %f) { define <16 x i8> @test_signed_v16f64_v16i8(<16 x double> %f) {
; CHECK-LABEL: test_signed_v16f64_v16i8: ; CHECK-LABEL: test_signed_v16f64_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d16, v0.d[1] ; CHECK-NEXT: mov d16, v0.d[1]
; CHECK-NEXT: mov w8, #127 ; CHECK-NEXT: mov w8, #127
; CHECK-NEXT: fcvtzs w11, d0 ; CHECK-NEXT: fcvtzs w13, d0
; CHECK-NEXT: mov w9, #-128 ; CHECK-NEXT: mov w9, #-128
; CHECK-NEXT: fcvtzs w13, d1
; CHECK-NEXT: mov d0, v2.d[1] ; CHECK-NEXT: mov d0, v2.d[1]
; CHECK-NEXT: fcvtzs w14, d2 ; CHECK-NEXT: fcvtzs w10, d1
; CHECK-NEXT: fcvtzs w10, d16 ; CHECK-NEXT: fcvtzs w11, d2
; CHECK-NEXT: mov d2, v4.d[1]
; CHECK-NEXT: fcvtzs w12, d16
; CHECK-NEXT: mov d16, v1.d[1] ; CHECK-NEXT: mov d16, v1.d[1]
; CHECK-NEXT: mov d1, v3.d[1] ; CHECK-NEXT: mov d1, v3.d[1]
; CHECK-NEXT: fcvtzs w15, d0 ; CHECK-NEXT: fcvtzs w15, d3
; CHECK-NEXT: cmp w10, #127 ; CHECK-NEXT: fcvtzs w17, d0
; CHECK-NEXT: csel w10, w10, w8, lt ; CHECK-NEXT: mov d3, v5.d[1]
; CHECK-NEXT: fcvtzs w12, d16
; CHECK-NEXT: cmn w10, #128
; CHECK-NEXT: csel w10, w10, w9, gt
; CHECK-NEXT: cmp w11, #127
; CHECK-NEXT: csel w11, w11, w8, lt
; CHECK-NEXT: cmn w11, #128
; CHECK-NEXT: csel w11, w11, w9, gt
; CHECK-NEXT: cmp w12, #127 ; CHECK-NEXT: cmp w12, #127
; CHECK-NEXT: fcvtzs w16, d4
; CHECK-NEXT: csel w12, w12, w8, lt ; CHECK-NEXT: csel w12, w12, w8, lt
; CHECK-NEXT: fcvtzs w14, d16
; CHECK-NEXT: cmn w12, #128 ; CHECK-NEXT: cmn w12, #128
; CHECK-NEXT: csel w12, w12, w9, gt ; CHECK-NEXT: csel w12, w12, w9, gt
; CHECK-NEXT: cmp w13, #127 ; CHECK-NEXT: cmp w13, #127
; CHECK-NEXT: csel w13, w13, w8, lt ; CHECK-NEXT: csel w13, w13, w8, lt
; CHECK-NEXT: fmov s0, w11
; CHECK-NEXT: cmn w13, #128 ; CHECK-NEXT: cmn w13, #128
; CHECK-NEXT: csel w11, w13, w9, gt ; CHECK-NEXT: csel w13, w13, w9, gt
; CHECK-NEXT: cmp w15, #127
; CHECK-NEXT: mov v0.s[1], w10
; CHECK-NEXT: csel w10, w15, w8, lt
; CHECK-NEXT: cmn w10, #128
; CHECK-NEXT: fcvtzs w13, d3
; CHECK-NEXT: fmov s2, w11
; CHECK-NEXT: csel w10, w10, w9, gt
; CHECK-NEXT: cmp w14, #127 ; CHECK-NEXT: cmp w14, #127
; CHECK-NEXT: fcvtzs w11, d1
; CHECK-NEXT: mov w15, v0.s[1]
; CHECK-NEXT: csel w14, w14, w8, lt ; CHECK-NEXT: csel w14, w14, w8, lt
; CHECK-NEXT: mov v2.s[1], w12
; CHECK-NEXT: cmn w14, #128 ; CHECK-NEXT: cmn w14, #128
; CHECK-NEXT: csel w12, w14, w9, gt ; CHECK-NEXT: csel w14, w14, w9, gt
; CHECK-NEXT: cmp w10, #127
; CHECK-NEXT: csel w10, w10, w8, lt
; CHECK-NEXT: fmov s0, w13
; CHECK-NEXT: cmn w10, #128
; CHECK-NEXT: fcvtzs w13, d1
; CHECK-NEXT: csel w10, w10, w9, gt
; CHECK-NEXT: cmp w17, #127
; CHECK-NEXT: mov v0.s[1], w12
; CHECK-NEXT: csel w12, w17, w8, lt
; CHECK-NEXT: cmn w12, #128
; CHECK-NEXT: fcvtzs w17, d7
; CHECK-NEXT: fmov s1, w10
; CHECK-NEXT: csel w10, w12, w9, gt
; CHECK-NEXT: cmp w11, #127 ; CHECK-NEXT: cmp w11, #127
; CHECK-NEXT: mov w12, v0.s[1]
; CHECK-NEXT: csel w11, w11, w8, lt ; CHECK-NEXT: csel w11, w11, w8, lt
; CHECK-NEXT: mov d1, v4.d[1]
; CHECK-NEXT: mov v0.b[1], w15
; CHECK-NEXT: cmn w11, #128 ; CHECK-NEXT: cmn w11, #128
; CHECK-NEXT: fmov w14, s2 ; CHECK-NEXT: mov v1.s[1], w14
; CHECK-NEXT: csel w11, w11, w9, gt ; CHECK-NEXT: csel w11, w11, w9, gt
; CHECK-NEXT: fmov s3, w12
; CHECK-NEXT: cmp w13, #127 ; CHECK-NEXT: cmp w13, #127
; CHECK-NEXT: mov w12, v2.s[1] ; CHECK-NEXT: mov v0.b[1], w12
; CHECK-NEXT: csel w13, w13, w8, lt ; CHECK-NEXT: csel w12, w13, w8, lt
; CHECK-NEXT: mov v0.b[2], w14 ; CHECK-NEXT: mov w13, v1.s[1]
; CHECK-NEXT: cmn w13, #128 ; CHECK-NEXT: fmov w14, s1
; CHECK-NEXT: mov v3.s[1], w10 ; CHECK-NEXT: cmn w12, #128
; CHECK-NEXT: csel w13, w13, w9, gt ; CHECK-NEXT: fmov s1, w11
; CHECK-NEXT: fcvtzs w15, d1 ; CHECK-NEXT: csel w11, w12, w9, gt
; CHECK-NEXT: fcvtzs w14, d4
; CHECK-NEXT: mov d1, v5.d[1]
; CHECK-NEXT: mov v0.b[3], w12
; CHECK-NEXT: fmov s4, w13
; CHECK-NEXT: cmp w15, #127 ; CHECK-NEXT: cmp w15, #127
; CHECK-NEXT: fmov w13, s3 ; CHECK-NEXT: fcvtzs w12, d2
; CHECK-NEXT: csel w10, w15, w8, lt ; CHECK-NEXT: csel w15, w15, w8, lt
; CHECK-NEXT: mov w12, v3.s[1] ; CHECK-NEXT: cmn w15, #128
; CHECK-NEXT: cmn w10, #128 ; CHECK-NEXT: mov v1.s[1], w10
; CHECK-NEXT: fcvtzs w15, d1 ; CHECK-NEXT: mov v0.b[2], w14
; CHECK-NEXT: csel w10, w10, w9, gt ; CHECK-NEXT: csel w10, w15, w9, gt
; CHECK-NEXT: cmp w14, #127 ; CHECK-NEXT: cmp w12, #127
; CHECK-NEXT: mov v0.b[4], w13 ; CHECK-NEXT: fmov w14, s1
; CHECK-NEXT: csel w14, w14, w8, lt ; CHECK-NEXT: csel w12, w12, w8, lt
; CHECK-NEXT: mov v4.s[1], w11 ; CHECK-NEXT: mov v0.b[3], w13
; CHECK-NEXT: cmn w12, #128
; CHECK-NEXT: mov w13, v1.s[1]
; CHECK-NEXT: fmov s1, w10
; CHECK-NEXT: csel w10, w12, w9, gt
; CHECK-NEXT: cmp w16, #127
; CHECK-NEXT: fcvtzs w12, d3
; CHECK-NEXT: mov v0.b[4], w14
; CHECK-NEXT: csel w14, w16, w8, lt
; CHECK-NEXT: cmn w14, #128 ; CHECK-NEXT: cmn w14, #128
; CHECK-NEXT: csel w14, w14, w9, gt
; CHECK-NEXT: fcvtzs w13, d5
; CHECK-NEXT: cmp w15, #127
; CHECK-NEXT: mov d2, v6.d[1] ; CHECK-NEXT: mov d2, v6.d[1]
; CHECK-NEXT: mov v0.b[5], w12 ; CHECK-NEXT: mov v1.s[1], w11
; CHECK-NEXT: csel w11, w15, w8, lt ; CHECK-NEXT: csel w11, w14, w9, gt
; CHECK-NEXT: fmov w12, s4 ; CHECK-NEXT: cmp w12, #127
; CHECK-NEXT: cmn w11, #128 ; CHECK-NEXT: fcvtzs w15, d5
; CHECK-NEXT: fmov s1, w14 ; CHECK-NEXT: csel w12, w12, w8, lt
; CHECK-NEXT: csel w11, w11, w9, gt ; CHECK-NEXT: mov v0.b[5], w13
; CHECK-NEXT: cmn w12, #128
; CHECK-NEXT: fcvtzs w13, d2
; CHECK-NEXT: csel w12, w12, w9, gt
; CHECK-NEXT: cmp w15, #127
; CHECK-NEXT: fmov w16, s1
; CHECK-NEXT: csel w15, w15, w8, lt
; CHECK-NEXT: cmn w15, #128
; CHECK-NEXT: mov d2, v7.d[1]
; CHECK-NEXT: mov w14, v1.s[1]
; CHECK-NEXT: fmov s1, w11
; CHECK-NEXT: csel w11, w15, w9, gt
; CHECK-NEXT: cmp w13, #127 ; CHECK-NEXT: cmp w13, #127
; CHECK-NEXT: mov w14, v4.s[1] ; CHECK-NEXT: fcvtzs w15, d6
; CHECK-NEXT: mov v0.b[6], w12 ; CHECK-NEXT: mov v0.b[6], w16
; CHECK-NEXT: csel w13, w13, w8, lt ; CHECK-NEXT: csel w13, w13, w8, lt
; CHECK-NEXT: mov v1.s[1], w10 ; CHECK-NEXT: mov v1.s[1], w10
; CHECK-NEXT: cmn w13, #128 ; CHECK-NEXT: cmn w13, #128
; CHECK-NEXT: fcvtzs w15, d2
; CHECK-NEXT: csel w13, w13, w9, gt
; CHECK-NEXT: fcvtzs w10, d6
; CHECK-NEXT: mov v0.b[7], w14 ; CHECK-NEXT: mov v0.b[7], w14
; CHECK-NEXT: csel w10, w13, w9, gt
; CHECK-NEXT: cmp w15, #127 ; CHECK-NEXT: cmp w15, #127
; CHECK-NEXT: fmov w14, s1 ; CHECK-NEXT: fcvtzs w14, d2
; CHECK-NEXT: csel w12, w15, w8, lt ; CHECK-NEXT: csel w13, w15, w8, lt
; CHECK-NEXT: fmov s2, w13 ; CHECK-NEXT: cmn w13, #128
; CHECK-NEXT: mov w13, v1.s[1] ; CHECK-NEXT: mov w15, v1.s[1]
; CHECK-NEXT: mov d1, v7.d[1] ; CHECK-NEXT: csel w13, w13, w9, gt
; CHECK-NEXT: cmn w12, #128 ; CHECK-NEXT: fmov w16, s1
; CHECK-NEXT: fcvtzs w15, d7 ; CHECK-NEXT: cmp w14, #127
; CHECK-NEXT: csel w12, w12, w9, gt ; CHECK-NEXT: fmov s1, w11
; CHECK-NEXT: cmp w10, #127 ; CHECK-NEXT: csel w11, w14, w8, lt
; CHECK-NEXT: mov v0.b[8], w14 ; CHECK-NEXT: cmn w11, #128
; CHECK-NEXT: csel w10, w10, w8, lt ; CHECK-NEXT: mov v0.b[8], w16
; CHECK-NEXT: mov v2.s[1], w11 ; CHECK-NEXT: csel w11, w11, w9, gt
; CHECK-NEXT: cmn w10, #128 ; CHECK-NEXT: cmp w17, #127
; CHECK-NEXT: fcvtzs w11, d1
; CHECK-NEXT: csel w10, w10, w9, gt
; CHECK-NEXT: mov v0.b[9], w13
; CHECK-NEXT: fmov w14, s2
; CHECK-NEXT: cmp w11, #127
; CHECK-NEXT: fmov s1, w10
; CHECK-NEXT: csel w10, w11, w8, lt
; CHECK-NEXT: cmn w10, #128
; CHECK-NEXT: mov w13, v2.s[1]
; CHECK-NEXT: mov v0.b[10], w14
; CHECK-NEXT: csel w10, w10, w9, gt
; CHECK-NEXT: cmp w15, #127
; CHECK-NEXT: mov v1.s[1], w12 ; CHECK-NEXT: mov v1.s[1], w12
; CHECK-NEXT: csel w8, w15, w8, lt ; CHECK-NEXT: csel w8, w17, w8, lt
; CHECK-NEXT: fmov s2, w13
; CHECK-NEXT: cmn w8, #128 ; CHECK-NEXT: cmn w8, #128
; CHECK-NEXT: csel w8, w8, w9, gt ; CHECK-NEXT: csel w8, w8, w9, gt
; CHECK-NEXT: mov v0.b[11], w13
; CHECK-NEXT: fmov w9, s1 ; CHECK-NEXT: fmov w9, s1
; CHECK-NEXT: fmov s2, w8 ; CHECK-NEXT: mov v0.b[9], w15
; CHECK-NEXT: mov w8, v1.s[1] ; CHECK-NEXT: mov w12, v1.s[1]
; CHECK-NEXT: mov v0.b[12], w9
; CHECK-NEXT: mov v2.s[1], w10 ; CHECK-NEXT: mov v2.s[1], w10
; CHECK-NEXT: mov v0.b[13], w8 ; CHECK-NEXT: mov v0.b[10], w9
; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: fmov w8, s2 ; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: mov w9, v2.s[1] ; CHECK-NEXT: mov w9, v2.s[1]
; CHECK-NEXT: mov v0.b[11], w12
; CHECK-NEXT: mov v1.s[1], w11
; CHECK-NEXT: mov v0.b[12], w8
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov v0.b[13], w9
; CHECK-NEXT: mov w9, v1.s[1]
; CHECK-NEXT: mov v0.b[14], w8 ; CHECK-NEXT: mov v0.b[14], w8
; CHECK-NEXT: mov v0.b[15], w9 ; CHECK-NEXT: mov v0.b[15], w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <16 x i8> @llvm.fptosi.sat.v16f64.v16i8(<16 x double> %f) %x = call <16 x i8> @llvm.fptosi.sat.v16f64.v16i8(<16 x double> %f)
ret <16 x i8> %x ret <16 x i8> %x
} }
define <8 x i16> @test_signed_v8f64_v8i16(<8 x double> %f) { define <8 x i16> @test_signed_v8f64_v8i16(<8 x double> %f) {
; CHECK-LABEL: test_signed_v8f64_v8i16: ; CHECK-LABEL: test_signed_v8f64_v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d4, v0.d[1] ; CHECK-NEXT: mov d4, v0.d[1]
; CHECK-NEXT: mov w8, #32767 ; CHECK-NEXT: mov w8, #32767
; CHECK-NEXT: fcvtzs w10, d0 ; CHECK-NEXT: fcvtzs w10, d0
; CHECK-NEXT: mov w11, #-32768 ; CHECK-NEXT: mov w11, #-32768
; CHECK-NEXT: mov d0, v2.d[1] ; CHECK-NEXT: mov d0, v2.d[1]
; CHECK-NEXT: fcvtzs w13, d1 ; CHECK-NEXT: fcvtzs w13, d1
; CHECK-NEXT: fcvtzs w15, d3 ; CHECK-NEXT: fcvtzs w15, d2
; CHECK-NEXT: fcvtzs w9, d4 ; CHECK-NEXT: fcvtzs w9, d4
; CHECK-NEXT: mov d4, v1.d[1] ; CHECK-NEXT: mov d4, v1.d[1]
; CHECK-NEXT: mov d1, v3.d[1]
; CHECK-NEXT: fcvtzs w14, d0 ; CHECK-NEXT: fcvtzs w14, d0
; CHECK-NEXT: mov d0, v3.d[1]
; CHECK-NEXT: cmp w9, w8 ; CHECK-NEXT: cmp w9, w8
; CHECK-NEXT: csel w9, w9, w8, lt ; CHECK-NEXT: csel w9, w9, w8, lt
; CHECK-NEXT: fcvtzs w12, d4 ; CHECK-NEXT: fcvtzs w12, d4
; CHECK-NEXT: cmn w9, #8, lsl #12 // =32768 ; CHECK-NEXT: cmn w9, #8, lsl #12 // =32768
; CHECK-NEXT: csel w9, w9, w11, gt ; CHECK-NEXT: csel w9, w9, w11, gt
; CHECK-NEXT: cmp w10, w8 ; CHECK-NEXT: cmp w10, w8
; CHECK-NEXT: csel w10, w10, w8, lt ; CHECK-NEXT: csel w10, w10, w8, lt
; CHECK-NEXT: fcvtzs w16, d0
; CHECK-NEXT: cmn w10, #8, lsl #12 // =32768 ; CHECK-NEXT: cmn w10, #8, lsl #12 // =32768
; CHECK-NEXT: csel w10, w10, w11, gt ; CHECK-NEXT: csel w10, w10, w11, gt
; CHECK-NEXT: cmp w12, w8 ; CHECK-NEXT: cmp w12, w8
; CHECK-NEXT: csel w12, w12, w8, lt ; CHECK-NEXT: csel w12, w12, w8, lt
; CHECK-NEXT: cmn w12, #8, lsl #12 // =32768 ; CHECK-NEXT: cmn w12, #8, lsl #12 // =32768
; CHECK-NEXT: csel w12, w12, w11, gt ; CHECK-NEXT: csel w12, w12, w11, gt
; CHECK-NEXT: cmp w13, w8 ; CHECK-NEXT: cmp w13, w8
; CHECK-NEXT: csel w13, w13, w8, lt
; CHECK-NEXT: fmov s0, w10 ; CHECK-NEXT: fmov s0, w10
; CHECK-NEXT: csel w10, w13, w8, lt ; CHECK-NEXT: cmn w13, #8, lsl #12 // =32768
; CHECK-NEXT: cmn w10, #8, lsl #12 // =32768 ; CHECK-NEXT: csel w13, w13, w11, gt
; CHECK-NEXT: fcvtzs w13, d2
; CHECK-NEXT: csel w10, w10, w11, gt
; CHECK-NEXT: cmp w14, w8 ; CHECK-NEXT: cmp w14, w8
; CHECK-NEXT: csel w14, w14, w8, lt
; CHECK-NEXT: mov v0.s[1], w9 ; CHECK-NEXT: mov v0.s[1], w9
; CHECK-NEXT: csel w9, w14, w8, lt ; CHECK-NEXT: cmn w14, #8, lsl #12 // =32768
; CHECK-NEXT: csel w14, w14, w11, gt
; CHECK-NEXT: cmp w15, w8
; CHECK-NEXT: csel w15, w15, w8, lt
; CHECK-NEXT: fmov s1, w13
; CHECK-NEXT: cmn w15, #8, lsl #12 // =32768
; CHECK-NEXT: fcvtzs w13, d3
; CHECK-NEXT: csel w10, w15, w11, gt
; CHECK-NEXT: cmp w16, w8
; CHECK-NEXT: csel w9, w16, w8, lt
; CHECK-NEXT: mov v1.s[1], w12
; CHECK-NEXT: cmn w9, #8, lsl #12 // =32768 ; CHECK-NEXT: cmn w9, #8, lsl #12 // =32768
; CHECK-NEXT: fmov s2, w10
; CHECK-NEXT: csel w9, w9, w11, gt ; CHECK-NEXT: csel w9, w9, w11, gt
; CHECK-NEXT: cmp w13, w8 ; CHECK-NEXT: cmp w13, w8
; CHECK-NEXT: csel w8, w13, w8, lt
; CHECK-NEXT: fmov s2, w10
; CHECK-NEXT: mov w10, v0.s[1] ; CHECK-NEXT: mov w10, v0.s[1]
; CHECK-NEXT: csel w13, w13, w8, lt
; CHECK-NEXT: mov v2.s[1], w12
; CHECK-NEXT: cmn w13, #8, lsl #12 // =32768
; CHECK-NEXT: fcvtzs w12, d1
; CHECK-NEXT: csel w13, w13, w11, gt
; CHECK-NEXT: mov v0.h[1], w10
; CHECK-NEXT: fmov w14, s2
; CHECK-NEXT: cmp w12, w8
; CHECK-NEXT: fmov s1, w13
; CHECK-NEXT: csel w12, w12, w8, lt
; CHECK-NEXT: cmn w12, #8, lsl #12 // =32768
; CHECK-NEXT: mov w10, v2.s[1]
; CHECK-NEXT: mov v0.h[2], w14
; CHECK-NEXT: csel w12, w12, w11, gt
; CHECK-NEXT: cmp w15, w8
; CHECK-NEXT: mov v1.s[1], w9
; CHECK-NEXT: csel w8, w15, w8, lt
; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768 ; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768
; CHECK-NEXT: csel w8, w8, w11, gt ; CHECK-NEXT: csel w8, w8, w11, gt
; CHECK-NEXT: mov v0.h[3], w10 ; CHECK-NEXT: fmov w11, s1
; CHECK-NEXT: fmov w9, s1 ; CHECK-NEXT: mov v0.h[1], w10
; CHECK-NEXT: fmov s2, w8 ; CHECK-NEXT: mov v2.s[1], w14
; CHECK-NEXT: mov w8, v1.s[1] ; CHECK-NEXT: mov w10, v1.s[1]
; CHECK-NEXT: mov v0.h[4], w9 ; CHECK-NEXT: mov v0.h[2], w11
; CHECK-NEXT: mov v2.s[1], w12 ; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: mov v0.h[5], w8
; CHECK-NEXT: fmov w8, s2 ; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: mov v0.h[3], w10
; CHECK-NEXT: mov v1.s[1], w9
; CHECK-NEXT: mov w9, v2.s[1] ; CHECK-NEXT: mov w9, v2.s[1]
; CHECK-NEXT: mov v0.h[4], w8
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov v0.h[5], w9
; CHECK-NEXT: mov w9, v1.s[1]
; CHECK-NEXT: mov v0.h[6], w8 ; CHECK-NEXT: mov v0.h[6], w8
; CHECK-NEXT: mov v0.h[7], w9 ; CHECK-NEXT: mov v0.h[7], w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <8 x i16> @llvm.fptosi.sat.v8f64.v8i16(<8 x double> %f) %x = call <8 x i16> @llvm.fptosi.sat.v8f64.v8i16(<8 x double> %f)
ret <8 x i16> %x ret <8 x i16> %x
} }
define <16 x i16> @test_signed_v16f64_v16i16(<16 x double> %f) { define <16 x i16> @test_signed_v16f64_v16i16(<16 x double> %f) {
; CHECK-LABEL: test_signed_v16f64_v16i16: ; CHECK-LABEL: test_signed_v16f64_v16i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d16, v0.d[1] ; CHECK-NEXT: mov d17, v0.d[1]
; CHECK-NEXT: mov w9, #32767 ; CHECK-NEXT: mov w8, #32767
; CHECK-NEXT: fcvtzs w11, d0
; CHECK-NEXT: mov w8, #-32768
; CHECK-NEXT: mov d0, v2.d[1]
; CHECK-NEXT: fcvtzs w12, d1
; CHECK-NEXT: fcvtzs w14, d2
; CHECK-NEXT: mov d2, v4.d[1]
; CHECK-NEXT: fcvtzs w10, d16
; CHECK-NEXT: mov d16, v1.d[1] ; CHECK-NEXT: mov d16, v1.d[1]
; CHECK-NEXT: fcvtzs w12, d0
; CHECK-NEXT: mov w9, #-32768
; CHECK-NEXT: mov d0, v2.d[1]
; CHECK-NEXT: fcvtzs w10, d1
; CHECK-NEXT: mov d1, v3.d[1] ; CHECK-NEXT: mov d1, v3.d[1]
; CHECK-NEXT: fcvtzs w16, d3 ; CHECK-NEXT: fcvtzs w14, d17
; CHECK-NEXT: fcvtzs w15, d0 ; CHECK-NEXT: fcvtzs w11, d2
; CHECK-NEXT: mov d3, v6.d[1] ; CHECK-NEXT: fcvtzs w15, d16
; CHECK-NEXT: cmp w10, w9 ; CHECK-NEXT: mov d2, v4.d[1]
; CHECK-NEXT: csel w10, w10, w9, lt ; CHECK-NEXT: fcvtzs w17, d0
; CHECK-NEXT: fcvtzs w13, d16 ; CHECK-NEXT: fcvtzs w13, d3
; CHECK-NEXT: cmn w10, #8, lsl #12 // =32768 ; CHECK-NEXT: cmp w14, w8
; CHECK-NEXT: fcvtzs w17, d1 ; CHECK-NEXT: fcvtzs w18, d1
; CHECK-NEXT: csel w10, w10, w8, gt ; CHECK-NEXT: csel w14, w14, w8, lt
; CHECK-NEXT: cmp w11, w9 ; CHECK-NEXT: mov d3, v5.d[1]
; CHECK-NEXT: csel w11, w11, w9, lt
; CHECK-NEXT: mov d1, v5.d[1]
; CHECK-NEXT: cmn w11, #8, lsl #12 // =32768
; CHECK-NEXT: csel w11, w11, w8, gt
; CHECK-NEXT: cmp w13, w9
; CHECK-NEXT: csel w13, w13, w9, lt
; CHECK-NEXT: cmn w13, #8, lsl #12 // =32768
; CHECK-NEXT: csel w13, w13, w8, gt
; CHECK-NEXT: cmp w12, w9
; CHECK-NEXT: csel w12, w12, w9, lt
; CHECK-NEXT: fmov s0, w11
; CHECK-NEXT: cmn w12, #8, lsl #12 // =32768
; CHECK-NEXT: csel w12, w12, w8, gt
; CHECK-NEXT: cmp w15, w9
; CHECK-NEXT: csel w15, w15, w9, lt
; CHECK-NEXT: cmn w15, #8, lsl #12 // =32768
; CHECK-NEXT: csel w11, w15, w8, gt
; CHECK-NEXT: cmp w14, w9
; CHECK-NEXT: csel w14, w14, w9, lt
; CHECK-NEXT: fcvtzs w15, d4
; CHECK-NEXT: cmn w14, #8, lsl #12 // =32768 ; CHECK-NEXT: cmn w14, #8, lsl #12 // =32768
; CHECK-NEXT: csel w14, w14, w8, gt ; CHECK-NEXT: fcvtzs w16, d4
; CHECK-NEXT: cmp w17, w9 ; CHECK-NEXT: csel w14, w14, w9, gt
; CHECK-NEXT: mov v0.s[1], w10 ; CHECK-NEXT: cmp w12, w8
; CHECK-NEXT: csel w10, w17, w9, lt ; CHECK-NEXT: csel w12, w12, w8, lt
; CHECK-NEXT: cmn w10, #8, lsl #12 // =32768 ; CHECK-NEXT: mov d4, v6.d[1]
; CHECK-NEXT: fcvtzs w17, d2
; CHECK-NEXT: csel w10, w10, w8, gt
; CHECK-NEXT: cmp w16, w9
; CHECK-NEXT: fmov s2, w12
; CHECK-NEXT: csel w12, w16, w9, lt
; CHECK-NEXT: cmn w12, #8, lsl #12 // =32768 ; CHECK-NEXT: cmn w12, #8, lsl #12 // =32768
; CHECK-NEXT: mov w16, v0.s[1] ; CHECK-NEXT: csel w12, w12, w9, gt
; CHECK-NEXT: csel w12, w12, w8, gt ; CHECK-NEXT: cmp w15, w8
; CHECK-NEXT: cmp w17, w9 ; CHECK-NEXT: csel w15, w15, w8, lt
; CHECK-NEXT: mov v2.s[1], w13
; CHECK-NEXT: csel w13, w17, w9, lt
; CHECK-NEXT: cmn w13, #8, lsl #12 // =32768
; CHECK-NEXT: fcvtzs w17, d1
; CHECK-NEXT: csel w13, w13, w8, gt
; CHECK-NEXT: cmp w15, w9
; CHECK-NEXT: csel w15, w15, w9, lt
; CHECK-NEXT: fmov s4, w14
; CHECK-NEXT: cmn w15, #8, lsl #12 // =32768 ; CHECK-NEXT: cmn w15, #8, lsl #12 // =32768
; CHECK-NEXT: mov v0.h[1], w16 ; CHECK-NEXT: csel w15, w15, w9, gt
; CHECK-NEXT: fcvtzs w16, d5 ; CHECK-NEXT: cmp w10, w8
; CHECK-NEXT: csel w15, w15, w8, gt ; CHECK-NEXT: csel w10, w10, w8, lt
; CHECK-NEXT: cmp w17, w9 ; CHECK-NEXT: fmov s0, w12
; CHECK-NEXT: csel w17, w17, w9, lt ; CHECK-NEXT: cmn w10, #8, lsl #12 // =32768
; CHECK-NEXT: fcvtzs w12, d2
; CHECK-NEXT: csel w10, w10, w9, gt
; CHECK-NEXT: cmp w17, w8
; CHECK-NEXT: csel w17, w17, w8, lt
; CHECK-NEXT: mov v0.s[1], w14
; CHECK-NEXT: cmn w17, #8, lsl #12 // =32768 ; CHECK-NEXT: cmn w17, #8, lsl #12 // =32768
; CHECK-NEXT: csel w14, w17, w8, gt ; CHECK-NEXT: csel w14, w17, w9, gt
; CHECK-NEXT: cmp w16, w9 ; CHECK-NEXT: cmp w11, w8
; CHECK-NEXT: fmov s1, w15 ; CHECK-NEXT: csel w11, w11, w8, lt
; CHECK-NEXT: csel w15, w16, w9, lt ; CHECK-NEXT: fmov s1, w10
; CHECK-NEXT: fcvtzs w16, d3 ; CHECK-NEXT: cmn w11, #8, lsl #12 // =32768
; CHECK-NEXT: cmn w15, #8, lsl #12 // =32768 ; CHECK-NEXT: fcvtzs w17, d3
; CHECK-NEXT: mov v4.s[1], w11 ; CHECK-NEXT: csel w10, w11, w9, gt
; CHECK-NEXT: csel w11, w15, w8, gt ; CHECK-NEXT: cmp w18, w8
; CHECK-NEXT: fcvtzs w15, d6 ; CHECK-NEXT: csel w18, w18, w8, lt
; CHECK-NEXT: mov v1.s[1], w13 ; CHECK-NEXT: mov w11, v0.s[1]
; CHECK-NEXT: cmp w16, w9 ; CHECK-NEXT: cmn w18, #8, lsl #12 // =32768
; CHECK-NEXT: fmov s3, w11 ; CHECK-NEXT: mov v1.s[1], w15
; CHECK-NEXT: csel w16, w16, w9, lt ; CHECK-NEXT: csel w15, w18, w9, gt
; CHECK-NEXT: fmov w11, s2 ; CHECK-NEXT: cmp w13, w8
; CHECK-NEXT: mov w13, v2.s[1] ; CHECK-NEXT: mov v0.h[1], w11
; CHECK-NEXT: mov d2, v7.d[1] ; CHECK-NEXT: csel w11, w13, w8, lt
; CHECK-NEXT: cmn w11, #8, lsl #12 // =32768
; CHECK-NEXT: fmov s2, w10
; CHECK-NEXT: csel w11, w11, w9, gt
; CHECK-NEXT: cmp w12, w8
; CHECK-NEXT: csel w12, w12, w8, lt
; CHECK-NEXT: fmov w18, s1
; CHECK-NEXT: cmn w12, #8, lsl #12 // =32768
; CHECK-NEXT: mov v2.s[1], w14
; CHECK-NEXT: csel w10, w12, w9, gt
; CHECK-NEXT: cmp w16, w8
; CHECK-NEXT: csel w16, w16, w8, lt
; CHECK-NEXT: fcvtzs w12, d5
; CHECK-NEXT: cmn w16, #8, lsl #12 // =32768 ; CHECK-NEXT: cmn w16, #8, lsl #12 // =32768
; CHECK-NEXT: csel w16, w16, w8, gt ; CHECK-NEXT: mov v0.h[2], w18
; CHECK-NEXT: cmp w15, w9 ; CHECK-NEXT: csel w16, w16, w9, gt
; CHECK-NEXT: mov v0.h[2], w11 ; CHECK-NEXT: cmp w17, w8
; CHECK-NEXT: csel w11, w15, w9, lt ; CHECK-NEXT: csel w17, w17, w8, lt
; CHECK-NEXT: mov w15, v1.s[1] ; CHECK-NEXT: fcvtzs w18, d4
; CHECK-NEXT: cmn w17, #8, lsl #12 // =32768
; CHECK-NEXT: mov d3, v7.d[1]
; CHECK-NEXT: csel w14, w17, w9, gt
; CHECK-NEXT: cmp w12, w8
; CHECK-NEXT: csel w12, w12, w8, lt
; CHECK-NEXT: fcvtzs w17, d6
; CHECK-NEXT: cmn w12, #8, lsl #12 // =32768
; CHECK-NEXT: fmov s4, w11
; CHECK-NEXT: csel w12, w12, w9, gt
; CHECK-NEXT: cmp w18, w8
; CHECK-NEXT: csel w11, w18, w8, lt
; CHECK-NEXT: mov w13, v1.s[1]
; CHECK-NEXT: cmn w11, #8, lsl #12 // =32768 ; CHECK-NEXT: cmn w11, #8, lsl #12 // =32768
; CHECK-NEXT: fmov s1, w16
; CHECK-NEXT: csel w11, w11, w9, gt
; CHECK-NEXT: cmp w17, w8
; CHECK-NEXT: fcvtzs w16, d3
; CHECK-NEXT: csel w17, w17, w8, lt
; CHECK-NEXT: fmov s3, w12
; CHECK-NEXT: cmn w17, #8, lsl #12 // =32768
; CHECK-NEXT: mov v1.s[1], w10
; CHECK-NEXT: csel w10, w17, w9, gt
; CHECK-NEXT: fcvtzs w12, d7
; CHECK-NEXT: cmp w16, w8
; CHECK-NEXT: mov v3.s[1], w14 ; CHECK-NEXT: mov v3.s[1], w14
; CHECK-NEXT: fcvtzs w14, d2 ; CHECK-NEXT: csel w14, w16, w8, lt
; CHECK-NEXT: csel w11, w11, w8, gt
; CHECK-NEXT: mov v0.h[3], w13
; CHECK-NEXT: mov v1.h[1], w15
; CHECK-NEXT: cmp w14, w9
; CHECK-NEXT: fmov w13, s3
; CHECK-NEXT: csel w14, w14, w9, lt
; CHECK-NEXT: fcvtzs w15, d7
; CHECK-NEXT: fmov s2, w11
; CHECK-NEXT: cmn w14, #8, lsl #12 // =32768 ; CHECK-NEXT: cmn w14, #8, lsl #12 // =32768
; CHECK-NEXT: mov w11, v3.s[1] ; CHECK-NEXT: fmov s5, w10
; CHECK-NEXT: mov v1.h[2], w13 ; CHECK-NEXT: csel w10, w14, w9, gt
; CHECK-NEXT: csel w13, w14, w8, gt ; CHECK-NEXT: cmp w12, w8
; CHECK-NEXT: cmp w15, w9 ; CHECK-NEXT: csel w8, w12, w8, lt
; CHECK-NEXT: fmov s3, w12 ; CHECK-NEXT: mov w14, v1.s[1]
; CHECK-NEXT: mov v2.s[1], w16 ; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768
; CHECK-NEXT: csel w9, w15, w9, lt ; CHECK-NEXT: mov v5.s[1], w11
; CHECK-NEXT: cmn w9, #8, lsl #12 // =32768 ; CHECK-NEXT: csel w8, w8, w9, gt
; CHECK-NEXT: fmov w12, s4 ; CHECK-NEXT: fmov w9, s3
; CHECK-NEXT: csel w8, w9, w8, gt ; CHECK-NEXT: mov v1.h[1], w14
; CHECK-NEXT: mov w14, v4.s[1] ; CHECK-NEXT: mov w12, v3.s[1]
; CHECK-NEXT: mov v1.h[3], w11 ; CHECK-NEXT: mov w14, v2.s[1]
; CHECK-NEXT: fmov w11, s2 ; CHECK-NEXT: fmov w11, s2
; CHECK-NEXT: mov w9, v2.s[1] ; CHECK-NEXT: mov v1.h[2], w9
; CHECK-NEXT: fmov s2, w8 ; CHECK-NEXT: fmov s2, w8
; CHECK-NEXT: mov v0.h[4], w12 ; CHECK-NEXT: fmov w9, s5
; CHECK-NEXT: mov v1.h[4], w11 ; CHECK-NEXT: mov v0.h[3], w13
; CHECK-NEXT: mov v3.s[1], w10 ; CHECK-NEXT: mov v1.h[3], w12
; CHECK-NEXT: mov v2.s[1], w13 ; CHECK-NEXT: mov v4.s[1], w15
; CHECK-NEXT: mov v2.s[1], w10
; CHECK-NEXT: mov w8, v5.s[1]
; CHECK-NEXT: mov v0.h[4], w11
; CHECK-NEXT: mov v1.h[4], w9
; CHECK-NEXT: fmov w9, s4
; CHECK-NEXT: fmov w10, s2
; CHECK-NEXT: mov v0.h[5], w14 ; CHECK-NEXT: mov v0.h[5], w14
; CHECK-NEXT: mov v1.h[5], w9 ; CHECK-NEXT: mov v1.h[5], w8
; CHECK-NEXT: fmov w8, s3 ; CHECK-NEXT: mov w8, v4.s[1]
; CHECK-NEXT: fmov w9, s2
; CHECK-NEXT: mov w10, v3.s[1]
; CHECK-NEXT: mov w11, v2.s[1] ; CHECK-NEXT: mov w11, v2.s[1]
; CHECK-NEXT: mov v0.h[6], w8 ; CHECK-NEXT: mov v0.h[6], w9
; CHECK-NEXT: mov v1.h[6], w9 ; CHECK-NEXT: mov v1.h[6], w10
; CHECK-NEXT: mov v0.h[7], w10 ; CHECK-NEXT: mov v0.h[7], w8
; CHECK-NEXT: mov v1.h[7], w11 ; CHECK-NEXT: mov v1.h[7], w11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <16 x i16> @llvm.fptosi.sat.v16f64.v16i16(<16 x double> %f) %x = call <16 x i16> @llvm.fptosi.sat.v16f64.v16i16(<16 x double> %f)
ret <16 x i16> %x ret <16 x i16> %x
} }

llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1 ; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2 ; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3 ; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3
; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4 ; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4
; CHECK-NEXT: mov v0.s[1], v1.s[0] ; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: fcvtzu v4.4s, v4.4s ; CHECK-NEXT: fcvtzu v4.4s, v4.4s
; CHECK-NEXT: mov v0.s[2], v2.s[0] ; CHECK-NEXT: mov v0.s[2], v2.s[0]
; CHECK-NEXT: fmov w4, s4
; CHECK-NEXT: mov v0.s[3], v3.s[0] ; CHECK-NEXT: mov v0.s[3], v3.s[0]
; CHECK-NEXT: fmov w4, s4
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: mov w1, v0.s[1] ; CHECK-NEXT: mov w1, v0.s[1]
; CHECK-NEXT: mov w2, v0.s[2] ; CHECK-NEXT: mov w2, v0.s[2]
; CHECK-NEXT: mov w3, v0.s[3] ; CHECK-NEXT: mov w3, v0.s[3]
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <5 x i32> @llvm.fptoui.sat.v5f32.v5i32(<5 x float> %f) %x = call <5 x i32> @llvm.fptoui.sat.v5f32.v5i32(<5 x float> %f)
ret <5 x i32> %x ret <5 x i32> %x
} }
define <6 x i32> @test_unsigned_v6f32_v6i32(<6 x float> %f) { define <6 x i32> @test_unsigned_v6f32_v6i32(<6 x float> %f) {
; CHECK-LABEL: test_unsigned_v6f32_v6i32: ; CHECK-LABEL: test_unsigned_v6f32_v6i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1 ; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2 ; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4 ; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4
; CHECK-NEXT: // kill: def $s5 killed $s5 def $q5 ; CHECK-NEXT: // kill: def $s5 killed $s5 def $q5
; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3 ; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3
; CHECK-NEXT: mov v0.s[1], v1.s[0] ; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: mov v4.s[1], v5.s[0] ; CHECK-NEXT: mov v4.s[1], v5.s[0]
; CHECK-NEXT: mov v0.s[2], v2.s[0] ; CHECK-NEXT: mov v0.s[2], v2.s[0]
; CHECK-NEXT: fcvtzu v1.4s, v4.4s ; CHECK-NEXT: fcvtzu v1.4s, v4.4s
; CHECK-NEXT: mov v0.s[3], v3.s[0] ; CHECK-NEXT: mov v0.s[3], v3.s[0]
; CHECK-NEXT: mov w5, v1.s[1]
; CHECK-NEXT: fmov w4, s1
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: fmov w4, s1
; CHECK-NEXT: mov w5, v1.s[1]
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: mov w1, v0.s[1] ; CHECK-NEXT: mov w1, v0.s[1]
; CHECK-NEXT: mov w2, v0.s[2] ; CHECK-NEXT: mov w2, v0.s[2]
; CHECK-NEXT: mov w3, v0.s[3] ; CHECK-NEXT: mov w3, v0.s[3]
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <6 x i32> @llvm.fptoui.sat.v6f32.v6i32(<6 x float> %f) %x = call <6 x i32> @llvm.fptoui.sat.v6f32.v6i32(<6 x float> %f)
ret <6 x i32> %x ret <6 x i32> %x
} }
define <7 x i32> @test_unsigned_v7f32_v7i32(<7 x float> %f) { define <7 x i32> @test_unsigned_v7f32_v7i32(<7 x float> %f) {
; CHECK-LABEL: test_unsigned_v7f32_v7i32: ; CHECK-LABEL: test_unsigned_v7f32_v7i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1 ; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4 ; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4
; CHECK-NEXT: // kill: def $s5 killed $s5 def $q5 ; CHECK-NEXT: // kill: def $s5 killed $s5 def $q5
; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2 ; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
; CHECK-NEXT: // kill: def $s6 killed $s6 def $q6 ; CHECK-NEXT: // kill: def $s6 killed $s6 def $q6
; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3 ; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3
; CHECK-NEXT: mov v0.s[1], v1.s[0] ; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: mov v4.s[1], v5.s[0] ; CHECK-NEXT: mov v4.s[1], v5.s[0]
; CHECK-NEXT: mov v0.s[2], v2.s[0] ; CHECK-NEXT: mov v0.s[2], v2.s[0]
; CHECK-NEXT: mov v4.s[2], v6.s[0] ; CHECK-NEXT: mov v4.s[2], v6.s[0]
; CHECK-NEXT: mov v0.s[3], v3.s[0] ; CHECK-NEXT: mov v0.s[3], v3.s[0]
; CHECK-NEXT: fcvtzu v1.4s, v4.4s ; CHECK-NEXT: fcvtzu v1.4s, v4.4s
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: fmov w4, s1
; CHECK-NEXT: mov w5, v1.s[1] ; CHECK-NEXT: mov w5, v1.s[1]
; CHECK-NEXT: mov w6, v1.s[2] ; CHECK-NEXT: mov w6, v1.s[2]
; CHECK-NEXT: fmov w4, s1 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: mov w1, v0.s[1] ; CHECK-NEXT: mov w1, v0.s[1]
; CHECK-NEXT: mov w2, v0.s[2] ; CHECK-NEXT: mov w2, v0.s[2]
; CHECK-NEXT: mov w3, v0.s[3] ; CHECK-NEXT: mov w3, v0.s[3]
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <7 x i32> @llvm.fptoui.sat.v7f32.v7i32(<7 x float> %f) %x = call <7 x i32> @llvm.fptoui.sat.v7f32.v7i32(<7 x float> %f)
ret <7 x i32> %x ret <7 x i32> %x
} }
define <8 x i32> @test_unsigned_v8f32_v8i32(<8 x float> %f) { define <8 x i32> @test_unsigned_v8f32_v8i32(<8 x float> %f) {
; CHECK-LABEL: test_unsigned_v8f32_v8i32: ; CHECK-LABEL: test_unsigned_v8f32_v8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f) %x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f)
ret <2 x i32> %x ret <2 x i32> %x
} }
define <3 x i32> @test_unsigned_v3f64_v3i32(<3 x double> %f) { define <3 x i32> @test_unsigned_v3f64_v3i32(<3 x double> %f) {
; CHECK-LABEL: test_unsigned_v3f64_v3i32: ; CHECK-LABEL: test_unsigned_v3f64_v3i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu w8, d0 ; CHECK-NEXT: fcvtzu w9, d0
; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: fcvtzu w8, d1 ; CHECK-NEXT: fcvtzu w8, d1
; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: fcvtzu w9, d2
; CHECK-NEXT: mov v0.s[1], w8 ; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: fcvtzu w8, d2
; CHECK-NEXT: mov v0.s[2], w8
; CHECK-NEXT: fcvtzu w8, d0 ; CHECK-NEXT: fcvtzu w8, d0
; CHECK-NEXT: mov v0.s[2], w9
; CHECK-NEXT: mov v0.s[3], w8 ; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <3 x i32> @llvm.fptoui.sat.v3f64.v3i32(<3 x double> %f) %x = call <3 x i32> @llvm.fptoui.sat.v3f64.v3i32(<3 x double> %f)
ret <3 x i32> %x ret <3 x i32> %x
} }
define <4 x i32> @test_unsigned_v4f64_v4i32(<4 x double> %f) { define <4 x i32> @test_unsigned_v4f64_v4i32(<4 x double> %f) {
; CHECK-LABEL: test_unsigned_v4f64_v4i32: ; CHECK-LABEL: test_unsigned_v4f64_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d2, v0.d[1] ; CHECK-NEXT: mov d2, v0.d[1]
; CHECK-NEXT: fcvtzu w8, d0 ; CHECK-NEXT: fcvtzu w8, d0
; CHECK-NEXT: fcvtzu w9, d1
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: fcvtzu w8, d2 ; CHECK-NEXT: fcvtzu w8, d2
; CHECK-NEXT: mov d2, v1.d[1]
; CHECK-NEXT: mov v0.s[1], w8 ; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: fcvtzu w8, d1 ; CHECK-NEXT: fcvtzu w8, d2
; CHECK-NEXT: mov d1, v1.d[1] ; CHECK-NEXT: mov v0.s[2], w9
; CHECK-NEXT: mov v0.s[2], w8
; CHECK-NEXT: fcvtzu w8, d1
; CHECK-NEXT: mov v0.s[3], w8 ; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i32> @llvm.fptoui.sat.v4f64.v4i32(<4 x double> %f) %x = call <4 x i32> @llvm.fptoui.sat.v4f64.v4i32(<4 x double> %f)
ret <4 x i32> %x ret <4 x i32> %x
} }
define <5 x i32> @test_unsigned_v5f64_v5i32(<5 x double> %f) { define <5 x i32> @test_unsigned_v5f64_v5i32(<5 x double> %f) {
; CHECK-LABEL: test_unsigned_v5f64_v5i32: ; CHECK-LABEL: test_unsigned_v5f64_v5i32:
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define <5 x i32> @test_unsigned_v5f16_v5i32(<5 x half> %f) { define <5 x i32> @test_unsigned_v5f16_v5i32(<5 x half> %f) {
; CHECK-LABEL: test_unsigned_v5f16_v5i32: ; CHECK-LABEL: test_unsigned_v5f16_v5i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtl v1.4s, v0.4h ; CHECK-NEXT: fcvtl v1.4s, v0.4h
; CHECK-NEXT: fcvtl2 v0.4s, v0.8h ; CHECK-NEXT: fcvtl2 v0.4s, v0.8h
; CHECK-NEXT: fcvtzu v1.4s, v1.4s ; CHECK-NEXT: fcvtzu v1.4s, v1.4s
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: fmov w4, s0
; CHECK-NEXT: mov w1, v1.s[1] ; CHECK-NEXT: mov w1, v1.s[1]
; CHECK-NEXT: mov w2, v1.s[2] ; CHECK-NEXT: mov w2, v1.s[2]
; CHECK-NEXT: mov w3, v1.s[3] ; CHECK-NEXT: mov w3, v1.s[3]
; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: fmov w4, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <5 x i32> @llvm.fptoui.sat.v5f16.v5i32(<5 x half> %f) %x = call <5 x i32> @llvm.fptoui.sat.v5f16.v5i32(<5 x half> %f)
ret <5 x i32> %x ret <5 x i32> %x
} }
define <6 x i32> @test_unsigned_v6f16_v6i32(<6 x half> %f) { define <6 x i32> @test_unsigned_v6f16_v6i32(<6 x half> %f) {
; CHECK-LABEL: test_unsigned_v6f16_v6i32: ; CHECK-LABEL: test_unsigned_v6f16_v6i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtl v1.4s, v0.4h ; CHECK-NEXT: fcvtl v1.4s, v0.4h
; CHECK-NEXT: fcvtl2 v0.4s, v0.8h ; CHECK-NEXT: fcvtl2 v0.4s, v0.8h
; CHECK-NEXT: fcvtzu v1.4s, v1.4s ; CHECK-NEXT: fcvtzu v1.4s, v1.4s
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: fmov w4, s0
; CHECK-NEXT: mov w1, v1.s[1] ; CHECK-NEXT: mov w1, v1.s[1]
; CHECK-NEXT: mov w2, v1.s[2] ; CHECK-NEXT: mov w2, v1.s[2]
; CHECK-NEXT: mov w3, v1.s[3] ; CHECK-NEXT: mov w3, v1.s[3]
; CHECK-NEXT: mov w5, v0.s[1] ; CHECK-NEXT: mov w5, v0.s[1]
; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: fmov w4, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <6 x i32> @llvm.fptoui.sat.v6f16.v6i32(<6 x half> %f) %x = call <6 x i32> @llvm.fptoui.sat.v6f16.v6i32(<6 x half> %f)
ret <6 x i32> %x ret <6 x i32> %x
} }
define <7 x i32> @test_unsigned_v7f16_v7i32(<7 x half> %f) { define <7 x i32> @test_unsigned_v7f16_v7i32(<7 x half> %f) {
; CHECK-LABEL: test_unsigned_v7f16_v7i32: ; CHECK-LABEL: test_unsigned_v7f16_v7i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtl v1.4s, v0.4h ; CHECK-NEXT: fcvtl2 v1.4s, v0.8h
; CHECK-NEXT: fcvtl2 v0.4s, v0.8h ; CHECK-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NEXT: fcvtzu v1.4s, v1.4s ; CHECK-NEXT: fcvtzu v1.4s, v1.4s
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: mov w1, v1.s[1] ; CHECK-NEXT: fmov w4, s1
; CHECK-NEXT: mov w2, v1.s[2] ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: mov w3, v1.s[3] ; CHECK-NEXT: mov w5, v1.s[1]
; CHECK-NEXT: mov w5, v0.s[1] ; CHECK-NEXT: mov w1, v0.s[1]
; CHECK-NEXT: mov w6, v0.s[2] ; CHECK-NEXT: mov w2, v0.s[2]
; CHECK-NEXT: fmov w0, s1 ; CHECK-NEXT: mov w3, v0.s[3]
; CHECK-NEXT: fmov w4, s0 ; CHECK-NEXT: mov w6, v1.s[2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <7 x i32> @llvm.fptoui.sat.v7f16.v7i32(<7 x half> %f) %x = call <7 x i32> @llvm.fptoui.sat.v7f16.v7i32(<7 x half> %f)
ret <7 x i32> %x ret <7 x i32> %x
} }
define <8 x i32> @test_unsigned_v8f16_v8i32(<8 x half> %f) { define <8 x i32> @test_unsigned_v8f16_v8i32(<8 x half> %f) {
; CHECK-LABEL: test_unsigned_v8f16_v8i32: ; CHECK-LABEL: test_unsigned_v8f16_v8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
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declare <2 x i50> @llvm.fptoui.sat.v2f32.v2i50 (<2 x float>) declare <2 x i50> @llvm.fptoui.sat.v2f32.v2i50 (<2 x float>)
declare <2 x i64> @llvm.fptoui.sat.v2f32.v2i64 (<2 x float>) declare <2 x i64> @llvm.fptoui.sat.v2f32.v2i64 (<2 x float>)
declare <2 x i100> @llvm.fptoui.sat.v2f32.v2i100(<2 x float>) declare <2 x i100> @llvm.fptoui.sat.v2f32.v2i100(<2 x float>)
declare <2 x i128> @llvm.fptoui.sat.v2f32.v2i128(<2 x float>) declare <2 x i128> @llvm.fptoui.sat.v2f32.v2i128(<2 x float>)
define <2 x i1> @test_unsigned_v2f32_v2i1(<2 x float> %f) { define <2 x i1> @test_unsigned_v2f32_v2i1(<2 x float> %f) {
; CHECK-LABEL: test_unsigned_v2f32_v2i1: ; CHECK-LABEL: test_unsigned_v2f32_v2i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2s, #1
; CHECK-NEXT: fcvtzu v0.2s, v0.2s ; CHECK-NEXT: fcvtzu v0.2s, v0.2s
; CHECK-NEXT: movi v1.2s, #1
; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s ; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i1> @llvm.fptoui.sat.v2f32.v2i1(<2 x float> %f) %x = call <2 x i1> @llvm.fptoui.sat.v2f32.v2i1(<2 x float> %f)
ret <2 x i1> %x ret <2 x i1> %x
} }
define <2 x i8> @test_unsigned_v2f32_v2i8(<2 x float> %f) { define <2 x i8> @test_unsigned_v2f32_v2i8(<2 x float> %f) {
; CHECK-LABEL: test_unsigned_v2f32_v2i8: ; CHECK-LABEL: test_unsigned_v2f32_v2i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi d1, #0x0000ff000000ff
; CHECK-NEXT: fcvtzu v0.2s, v0.2s ; CHECK-NEXT: fcvtzu v0.2s, v0.2s
; CHECK-NEXT: movi d1, #0x0000ff000000ff
; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s ; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i8> @llvm.fptoui.sat.v2f32.v2i8(<2 x float> %f) %x = call <2 x i8> @llvm.fptoui.sat.v2f32.v2i8(<2 x float> %f)
ret <2 x i8> %x ret <2 x i8> %x
} }
define <2 x i13> @test_unsigned_v2f32_v2i13(<2 x float> %f) { define <2 x i13> @test_unsigned_v2f32_v2i13(<2 x float> %f) {
; CHECK-LABEL: test_unsigned_v2f32_v2i13: ; CHECK-LABEL: test_unsigned_v2f32_v2i13:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2s, #31, msl #8
; CHECK-NEXT: fcvtzu v0.2s, v0.2s ; CHECK-NEXT: fcvtzu v0.2s, v0.2s
; CHECK-NEXT: movi v1.2s, #31, msl #8
; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s ; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i13> @llvm.fptoui.sat.v2f32.v2i13(<2 x float> %f) %x = call <2 x i13> @llvm.fptoui.sat.v2f32.v2i13(<2 x float> %f)
ret <2 x i13> %x ret <2 x i13> %x
} }
define <2 x i16> @test_unsigned_v2f32_v2i16(<2 x float> %f) { define <2 x i16> @test_unsigned_v2f32_v2i16(<2 x float> %f) {
; CHECK-LABEL: test_unsigned_v2f32_v2i16: ; CHECK-LABEL: test_unsigned_v2f32_v2i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi d1, #0x00ffff0000ffff
; CHECK-NEXT: fcvtzu v0.2s, v0.2s ; CHECK-NEXT: fcvtzu v0.2s, v0.2s
; CHECK-NEXT: movi d1, #0x00ffff0000ffff
; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s ; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i16> @llvm.fptoui.sat.v2f32.v2i16(<2 x float> %f) %x = call <2 x i16> @llvm.fptoui.sat.v2f32.v2i16(<2 x float> %f)
ret <2 x i16> %x ret <2 x i16> %x
} }
define <2 x i19> @test_unsigned_v2f32_v2i19(<2 x float> %f) { define <2 x i19> @test_unsigned_v2f32_v2i19(<2 x float> %f) {
; CHECK-LABEL: test_unsigned_v2f32_v2i19: ; CHECK-LABEL: test_unsigned_v2f32_v2i19:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2s, #7, msl #16
; CHECK-NEXT: fcvtzu v0.2s, v0.2s ; CHECK-NEXT: fcvtzu v0.2s, v0.2s
; CHECK-NEXT: movi v1.2s, #7, msl #16
; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s ; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i19> @llvm.fptoui.sat.v2f32.v2i19(<2 x float> %f) %x = call <2 x i19> @llvm.fptoui.sat.v2f32.v2i19(<2 x float> %f)
ret <2 x i19> %x ret <2 x i19> %x
} }
define <2 x i32> @test_unsigned_v2f32_v2i32_duplicate(<2 x float> %f) { define <2 x i32> @test_unsigned_v2f32_v2i32_duplicate(<2 x float> %f) {
; CHECK-LABEL: test_unsigned_v2f32_v2i32_duplicate: ; CHECK-LABEL: test_unsigned_v2f32_v2i32_duplicate:
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declare <4 x i50> @llvm.fptoui.sat.v4f32.v4i50 (<4 x float>) declare <4 x i50> @llvm.fptoui.sat.v4f32.v4i50 (<4 x float>)
declare <4 x i64> @llvm.fptoui.sat.v4f32.v4i64 (<4 x float>) declare <4 x i64> @llvm.fptoui.sat.v4f32.v4i64 (<4 x float>)
declare <4 x i100> @llvm.fptoui.sat.v4f32.v4i100(<4 x float>) declare <4 x i100> @llvm.fptoui.sat.v4f32.v4i100(<4 x float>)
declare <4 x i128> @llvm.fptoui.sat.v4f32.v4i128(<4 x float>) declare <4 x i128> @llvm.fptoui.sat.v4f32.v4i128(<4 x float>)
define <4 x i1> @test_unsigned_v4f32_v4i1(<4 x float> %f) { define <4 x i1> @test_unsigned_v4f32_v4i1(<4 x float> %f) {
; CHECK-LABEL: test_unsigned_v4f32_v4i1: ; CHECK-LABEL: test_unsigned_v4f32_v4i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s ; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
; CHECK-NEXT: xtn v0.4h, v0.4s ; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i1> @llvm.fptoui.sat.v4f32.v4i1(<4 x float> %f) %x = call <4 x i1> @llvm.fptoui.sat.v4f32.v4i1(<4 x float> %f)
ret <4 x i1> %x ret <4 x i1> %x
} }
define <4 x i8> @test_unsigned_v4f32_v4i8(<4 x float> %f) { define <4 x i8> @test_unsigned_v4f32_v4i8(<4 x float> %f) {
; CHECK-LABEL: test_unsigned_v4f32_v4i8: ; CHECK-LABEL: test_unsigned_v4f32_v4i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0x0000ff000000ff
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: movi v1.2d, #0x0000ff000000ff
; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s ; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
; CHECK-NEXT: xtn v0.4h, v0.4s ; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i8> @llvm.fptoui.sat.v4f32.v4i8(<4 x float> %f) %x = call <4 x i8> @llvm.fptoui.sat.v4f32.v4i8(<4 x float> %f)
ret <4 x i8> %x ret <4 x i8> %x
} }
define <4 x i13> @test_unsigned_v4f32_v4i13(<4 x float> %f) { define <4 x i13> @test_unsigned_v4f32_v4i13(<4 x float> %f) {
; CHECK-LABEL: test_unsigned_v4f32_v4i13: ; CHECK-LABEL: test_unsigned_v4f32_v4i13:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #31, msl #8
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: movi v1.4s, #31, msl #8
; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s ; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
; CHECK-NEXT: xtn v0.4h, v0.4s ; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i13> @llvm.fptoui.sat.v4f32.v4i13(<4 x float> %f) %x = call <4 x i13> @llvm.fptoui.sat.v4f32.v4i13(<4 x float> %f)
ret <4 x i13> %x ret <4 x i13> %x
} }
define <4 x i16> @test_unsigned_v4f32_v4i16(<4 x float> %f) { define <4 x i16> @test_unsigned_v4f32_v4i16(<4 x float> %f) {
; CHECK-LABEL: test_unsigned_v4f32_v4i16: ; CHECK-LABEL: test_unsigned_v4f32_v4i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: uqxtn v0.4h, v0.4s ; CHECK-NEXT: uqxtn v0.4h, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i16> @llvm.fptoui.sat.v4f32.v4i16(<4 x float> %f) %x = call <4 x i16> @llvm.fptoui.sat.v4f32.v4i16(<4 x float> %f)
ret <4 x i16> %x ret <4 x i16> %x
} }
define <4 x i19> @test_unsigned_v4f32_v4i19(<4 x float> %f) { define <4 x i19> @test_unsigned_v4f32_v4i19(<4 x float> %f) {
; CHECK-LABEL: test_unsigned_v4f32_v4i19: ; CHECK-LABEL: test_unsigned_v4f32_v4i19:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #7, msl #16
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: movi v1.4s, #7, msl #16
; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s ; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i19> @llvm.fptoui.sat.v4f32.v4i19(<4 x float> %f) %x = call <4 x i19> @llvm.fptoui.sat.v4f32.v4i19(<4 x float> %f)
ret <4 x i19> %x ret <4 x i19> %x
} }
define <4 x i32> @test_unsigned_v4f32_v4i32_duplicate(<4 x float> %f) { define <4 x i32> @test_unsigned_v4f32_v4i32_duplicate(<4 x float> %f) {
; CHECK-LABEL: test_unsigned_v4f32_v4i32_duplicate: ; CHECK-LABEL: test_unsigned_v4f32_v4i32_duplicate:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i32> @llvm.fptoui.sat.v4f32.v4i32(<4 x float> %f) %x = call <4 x i32> @llvm.fptoui.sat.v4f32.v4i32(<4 x float> %f)
ret <4 x i32> %x ret <4 x i32> %x
} }
define <4 x i50> @test_unsigned_v4f32_v4i50(<4 x float> %f) { define <4 x i50> @test_unsigned_v4f32_v4i50(<4 x float> %f) {
; CHECK-LABEL: test_unsigned_v4f32_v4i50: ; CHECK-LABEL: test_unsigned_v4f32_v4i50:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: mov x8, #1125899906842623 ; CHECK-NEXT: mov x8, #1125899906842623
; CHECK-NEXT: mov s3, v0.s[1] ; CHECK-NEXT: mov s3, v0.s[1]
; CHECK-NEXT: fcvtzu x11, s0
; CHECK-NEXT: mov s2, v1.s[1] ; CHECK-NEXT: mov s2, v1.s[1]
; CHECK-NEXT: fcvtzu x9, s1 ; CHECK-NEXT: fcvtzu x9, s1
; CHECK-NEXT: fcvtzu x11, s0
; CHECK-NEXT: fcvtzu x12, s3 ; CHECK-NEXT: fcvtzu x12, s3
; CHECK-NEXT: cmp x9, x8 ; CHECK-NEXT: cmp x9, x8
; CHECK-NEXT: fcvtzu x10, s2 ; CHECK-NEXT: fcvtzu x10, s2
; CHECK-NEXT: csel x2, x9, x8, lo ; CHECK-NEXT: csel x2, x9, x8, lo
; CHECK-NEXT: cmp x10, x8 ; CHECK-NEXT: cmp x10, x8
; CHECK-NEXT: csel x3, x10, x8, lo ; CHECK-NEXT: csel x3, x10, x8, lo
; CHECK-NEXT: cmp x11, x8 ; CHECK-NEXT: cmp x11, x8
; CHECK-NEXT: csel x0, x11, x8, lo ; CHECK-NEXT: csel x0, x11, x8, lo
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; CHECK-NEXT: .cfi_offset w30, -64 ; CHECK-NEXT: .cfi_offset w30, -64
; CHECK-NEXT: .cfi_offset b8, -72 ; CHECK-NEXT: .cfi_offset b8, -72
; CHECK-NEXT: .cfi_offset b9, -80 ; CHECK-NEXT: .cfi_offset b9, -80
; CHECK-NEXT: mov s8, v0.s[1] ; CHECK-NEXT: mov s8, v0.s[1]
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: mov w8, #1904214015 ; CHECK-NEXT: mov w8, #1904214015
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov x25, #68719476735 ; CHECK-NEXT: mov x25, #68719476735
; CHECK-NEXT: fmov s9, w8 ; CHECK-NEXT: fmov s9, w8
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: csel x19, x25, x9, gt ; CHECK-NEXT: csel x19, x25, x9, gt
; CHECK-NEXT: csinv x20, x8, xzr, le ; CHECK-NEXT: csinv x20, x8, xzr, le
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: mov s8, v0.s[1] ; CHECK-NEXT: mov s8, v0.s[1]
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; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp s0, s9 ; CHECK-NEXT: fcmp s0, s9
; CHECK-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csel x1, x25, x9, gt ; CHECK-NEXT: csel x1, x25, x9, gt
; CHECK-NEXT: ldp x24, x23, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldp x24, x23, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ldp x30, x25, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x25, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #112 ; CHECK-NEXT: add sp, sp, #112
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i100> @llvm.fptoui.sat.v4f32.v4i100(<4 x float> %f) %x = call <4 x i100> @llvm.fptoui.sat.v4f32.v4i100(<4 x float> %f)
ret <4 x i100> %x ret <4 x i100> %x
} }
define <4 x i128> @test_unsigned_v4f32_v4i128(<4 x float> %f) { define <4 x i128> @test_unsigned_v4f32_v4i128(<4 x float> %f) {
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; CHECK-NEXT: .cfi_offset w30, -64 ; CHECK-NEXT: .cfi_offset w30, -64
; CHECK-NEXT: .cfi_offset b8, -72 ; CHECK-NEXT: .cfi_offset b8, -72
; CHECK-NEXT: .cfi_offset b9, -80 ; CHECK-NEXT: .cfi_offset b9, -80
; CHECK-NEXT: mov s8, v0.s[1] ; CHECK-NEXT: mov s8, v0.s[1]
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: mov w8, #2139095039 ; CHECK-NEXT: mov w8, #2139095039
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: fmov s9, w8 ; CHECK-NEXT: fmov s9, w8
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: csel x8, xzr, x1, lt ; CHECK-NEXT: csel x8, xzr, x1, lt
; CHECK-NEXT: csel x9, xzr, x0, lt ; CHECK-NEXT: csel x9, xzr, x0, lt
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: csinv x19, x9, xzr, le ; CHECK-NEXT: csinv x19, x9, xzr, le
; CHECK-NEXT: csinv x20, x8, xzr, le ; CHECK-NEXT: csinv x20, x8, xzr, le
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: mov s8, v0.s[1] ; CHECK-NEXT: mov s8, v0.s[1]
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; CHECK-CVT-NEXT: movi v1.4s, #1 ; CHECK-CVT-NEXT: movi v1.4s, #1
; CHECK-CVT-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-CVT-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-CVT-NEXT: umin v0.4s, v0.4s, v1.4s ; CHECK-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
; CHECK-CVT-NEXT: xtn v0.4h, v0.4s ; CHECK-CVT-NEXT: xtn v0.4h, v0.4s
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_unsigned_v4f16_v4i1: ; CHECK-FP16-LABEL: test_unsigned_v4f16_v4i1:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: movi v1.4h, #1
; CHECK-FP16-NEXT: fcvtzu v0.4h, v0.4h ; CHECK-FP16-NEXT: fcvtzu v0.4h, v0.4h
; CHECK-FP16-NEXT: movi v1.4h, #1
; CHECK-FP16-NEXT: umin v0.4h, v0.4h, v1.4h ; CHECK-FP16-NEXT: umin v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <4 x i1> @llvm.fptoui.sat.v4f16.v4i1(<4 x half> %f) %x = call <4 x i1> @llvm.fptoui.sat.v4f16.v4i1(<4 x half> %f)
ret <4 x i1> %x ret <4 x i1> %x
} }
define <4 x i8> @test_unsigned_v4f16_v4i8(<4 x half> %f) { define <4 x i8> @test_unsigned_v4f16_v4i8(<4 x half> %f) {
; CHECK-CVT-LABEL: test_unsigned_v4f16_v4i8: ; CHECK-CVT-LABEL: test_unsigned_v4f16_v4i8:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h ; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT: movi v1.2d, #0x0000ff000000ff ; CHECK-CVT-NEXT: movi v1.2d, #0x0000ff000000ff
; CHECK-CVT-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-CVT-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-CVT-NEXT: umin v0.4s, v0.4s, v1.4s ; CHECK-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
; CHECK-CVT-NEXT: xtn v0.4h, v0.4s ; CHECK-CVT-NEXT: xtn v0.4h, v0.4s
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_unsigned_v4f16_v4i8: ; CHECK-FP16-LABEL: test_unsigned_v4f16_v4i8:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: movi d1, #0xff00ff00ff00ff
; CHECK-FP16-NEXT: fcvtzu v0.4h, v0.4h ; CHECK-FP16-NEXT: fcvtzu v0.4h, v0.4h
; CHECK-FP16-NEXT: movi d1, #0xff00ff00ff00ff
; CHECK-FP16-NEXT: umin v0.4h, v0.4h, v1.4h ; CHECK-FP16-NEXT: umin v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <4 x i8> @llvm.fptoui.sat.v4f16.v4i8(<4 x half> %f) %x = call <4 x i8> @llvm.fptoui.sat.v4f16.v4i8(<4 x half> %f)
ret <4 x i8> %x ret <4 x i8> %x
} }
define <4 x i13> @test_unsigned_v4f16_v4i13(<4 x half> %f) { define <4 x i13> @test_unsigned_v4f16_v4i13(<4 x half> %f) {
; CHECK-CVT-LABEL: test_unsigned_v4f16_v4i13: ; CHECK-CVT-LABEL: test_unsigned_v4f16_v4i13:
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; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: mov x7, x23 ; CHECK-NEXT: mov x7, x23
; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csel x1, x25, x9, gt ; CHECK-NEXT: csel x1, x25, x9, gt
; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: ldp x30, x25, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x25, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #96 ; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i100> @llvm.fptoui.sat.v4f16.v4i100(<4 x half> %f) %x = call <4 x i100> @llvm.fptoui.sat.v4f16.v4i100(<4 x half> %f)
ret <4 x i100> %x ret <4 x i100> %x
} }
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; CHECK-NEXT: mov x7, x24 ; CHECK-NEXT: mov x7, x24
; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csinv x1, x9, xzr, le ; CHECK-NEXT: csinv x1, x9, xzr, le
; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #96 ; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i128> @llvm.fptoui.sat.v4f16.v4i128(<4 x half> %f) %x = call <4 x i128> @llvm.fptoui.sat.v4f16.v4i128(<4 x half> %f)
ret <4 x i128> %x ret <4 x i128> %x
} }
; ;
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; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i1: ; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i1:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: fcvtl2 v1.4s, v0.8h ; CHECK-CVT-NEXT: fcvtl2 v1.4s, v0.8h
; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h ; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT: mov s2, v1.s[1] ; CHECK-CVT-NEXT: mov s2, v1.s[1]
; CHECK-CVT-NEXT: mov s3, v1.s[2] ; CHECK-CVT-NEXT: mov s3, v1.s[2]
; CHECK-CVT-NEXT: mov s4, v1.s[3] ; CHECK-CVT-NEXT: mov s4, v1.s[3]
; CHECK-CVT-NEXT: mov s5, v0.s[1] ; CHECK-CVT-NEXT: mov s5, v0.s[1]
; CHECK-CVT-NEXT: fcvtzu w9, s1 ; CHECK-CVT-NEXT: fcvtzu w8, s1
; CHECK-CVT-NEXT: fcvtzu w10, s0 ; CHECK-CVT-NEXT: fcvtzu w10, s0
; CHECK-CVT-NEXT: mov s1, v0.s[2] ; CHECK-CVT-NEXT: mov s1, v0.s[2]
; CHECK-CVT-NEXT: mov s0, v0.s[3] ; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: fcvtzu w8, s2 ; CHECK-CVT-NEXT: fcvtzu w9, s2
; CHECK-CVT-NEXT: fcvtzu w11, s3 ; CHECK-CVT-NEXT: fcvtzu w11, s3
; CHECK-CVT-NEXT: fcvtzu w12, s4 ; CHECK-CVT-NEXT: fcvtzu w12, s4
; CHECK-CVT-NEXT: fcvtzu w13, s5 ; CHECK-CVT-NEXT: fcvtzu w13, s5
; CHECK-CVT-NEXT: cmp w8, #1
; CHECK-CVT-NEXT: csinc w8, w8, wzr, lo
; CHECK-CVT-NEXT: cmp w9, #1 ; CHECK-CVT-NEXT: cmp w9, #1
; CHECK-CVT-NEXT: fcvtzu w14, s1
; CHECK-CVT-NEXT: csinc w9, w9, wzr, lo ; CHECK-CVT-NEXT: csinc w9, w9, wzr, lo
; CHECK-CVT-NEXT: cmp w8, #1
; CHECK-CVT-NEXT: csinc w8, w8, wzr, lo
; CHECK-CVT-NEXT: cmp w11, #1 ; CHECK-CVT-NEXT: cmp w11, #1
; CHECK-CVT-NEXT: csinc w11, w11, wzr, lo ; CHECK-CVT-NEXT: csinc w11, w11, wzr, lo
; CHECK-CVT-NEXT: cmp w12, #1 ; CHECK-CVT-NEXT: cmp w12, #1
; CHECK-CVT-NEXT: csinc w12, w12, wzr, lo ; CHECK-CVT-NEXT: csinc w12, w12, wzr, lo
; CHECK-CVT-NEXT: cmp w13, #1 ; CHECK-CVT-NEXT: cmp w13, #1
; CHECK-CVT-NEXT: csinc w13, w13, wzr, lo ; CHECK-CVT-NEXT: csinc w13, w13, wzr, lo
; CHECK-CVT-NEXT: cmp w10, #1 ; CHECK-CVT-NEXT: cmp w10, #1
; CHECK-CVT-NEXT: csinc w10, w10, wzr, lo ; CHECK-CVT-NEXT: csinc w10, w10, wzr, lo
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: fmov s1, w8
; CHECK-CVT-NEXT: fcvtzu w9, s1 ; CHECK-CVT-NEXT: fcvtzu w8, s0
; CHECK-CVT-NEXT: fmov s3, w10 ; CHECK-CVT-NEXT: cmp w14, #1
; CHECK-CVT-NEXT: mov v2.s[1], w8 ; CHECK-CVT-NEXT: fmov s2, w10
; CHECK-CVT-NEXT: cmp w9, #1 ; CHECK-CVT-NEXT: mov v1.s[1], w9
; CHECK-CVT-NEXT: csinc w8, w9, wzr, lo ; CHECK-CVT-NEXT: csinc w9, w14, wzr, lo
; CHECK-CVT-NEXT: fcvtzu w9, s0 ; CHECK-CVT-NEXT: cmp w8, #1
; CHECK-CVT-NEXT: mov v3.s[1], w13 ; CHECK-CVT-NEXT: csinc w8, w8, wzr, lo
; CHECK-CVT-NEXT: mov v2.s[2], w11 ; CHECK-CVT-NEXT: mov v1.s[2], w11
; CHECK-CVT-NEXT: cmp w9, #1 ; CHECK-CVT-NEXT: mov v2.s[1], w13
; CHECK-CVT-NEXT: mov v3.s[2], w8 ; CHECK-CVT-NEXT: mov v1.s[3], w12
; CHECK-CVT-NEXT: csinc w8, w9, wzr, lo ; CHECK-CVT-NEXT: mov v2.s[2], w9
; CHECK-CVT-NEXT: mov v2.s[3], w12 ; CHECK-CVT-NEXT: mov v2.s[3], w8
; CHECK-CVT-NEXT: mov v3.s[3], w8 ; CHECK-CVT-NEXT: uzp1 v0.8h, v2.8h, v1.8h
; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v2.8h
; CHECK-CVT-NEXT: xtn v0.8b, v0.8h ; CHECK-CVT-NEXT: xtn v0.8b, v0.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i1: ; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i1:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: movi v1.8h, #1
; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h ; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
; CHECK-FP16-NEXT: movi v1.8h, #1
; CHECK-FP16-NEXT: umin v0.8h, v0.8h, v1.8h ; CHECK-FP16-NEXT: umin v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: xtn v0.8b, v0.8h ; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <8 x i1> @llvm.fptoui.sat.v8f16.v8i1(<8 x half> %f) %x = call <8 x i1> @llvm.fptoui.sat.v8f16.v8i1(<8 x half> %f)
ret <8 x i1> %x ret <8 x i1> %x
} }
define <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) { define <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) {
; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i8: ; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i8:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: fcvtl2 v1.4s, v0.8h ; CHECK-CVT-NEXT: fcvtl2 v1.4s, v0.8h
; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h ; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT: mov w8, #255 ; CHECK-CVT-NEXT: mov w8, #255
; CHECK-CVT-NEXT: mov s2, v1.s[1] ; CHECK-CVT-NEXT: mov s2, v1.s[1]
; CHECK-CVT-NEXT: mov s3, v1.s[2] ; CHECK-CVT-NEXT: mov s3, v1.s[2]
; CHECK-CVT-NEXT: mov s4, v1.s[3] ; CHECK-CVT-NEXT: mov s4, v1.s[3]
; CHECK-CVT-NEXT: mov s5, v0.s[1] ; CHECK-CVT-NEXT: mov s5, v0.s[1]
; CHECK-CVT-NEXT: fcvtzu w10, s1 ; CHECK-CVT-NEXT: fcvtzu w9, s1
; CHECK-CVT-NEXT: fcvtzu w11, s0 ; CHECK-CVT-NEXT: fcvtzu w11, s0
; CHECK-CVT-NEXT: mov s1, v0.s[2] ; CHECK-CVT-NEXT: mov s1, v0.s[2]
; CHECK-CVT-NEXT: mov s0, v0.s[3] ; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: fcvtzu w9, s2 ; CHECK-CVT-NEXT: fcvtzu w10, s2
; CHECK-CVT-NEXT: fcvtzu w12, s3 ; CHECK-CVT-NEXT: fcvtzu w12, s3
; CHECK-CVT-NEXT: fcvtzu w13, s4 ; CHECK-CVT-NEXT: fcvtzu w13, s4
; CHECK-CVT-NEXT: fcvtzu w14, s5 ; CHECK-CVT-NEXT: fcvtzu w14, s5
; CHECK-CVT-NEXT: cmp w9, #255
; CHECK-CVT-NEXT: csel w9, w9, w8, lo
; CHECK-CVT-NEXT: cmp w10, #255 ; CHECK-CVT-NEXT: cmp w10, #255
; CHECK-CVT-NEXT: fcvtzu w15, s1
; CHECK-CVT-NEXT: csel w10, w10, w8, lo ; CHECK-CVT-NEXT: csel w10, w10, w8, lo
; CHECK-CVT-NEXT: cmp w9, #255
; CHECK-CVT-NEXT: csel w9, w9, w8, lo
; CHECK-CVT-NEXT: cmp w12, #255 ; CHECK-CVT-NEXT: cmp w12, #255
; CHECK-CVT-NEXT: csel w12, w12, w8, lo ; CHECK-CVT-NEXT: csel w12, w12, w8, lo
; CHECK-CVT-NEXT: cmp w13, #255 ; CHECK-CVT-NEXT: cmp w13, #255
; CHECK-CVT-NEXT: csel w13, w13, w8, lo ; CHECK-CVT-NEXT: csel w13, w13, w8, lo
; CHECK-CVT-NEXT: cmp w14, #255 ; CHECK-CVT-NEXT: cmp w14, #255
; CHECK-CVT-NEXT: csel w14, w14, w8, lo ; CHECK-CVT-NEXT: csel w14, w14, w8, lo
; CHECK-CVT-NEXT: cmp w11, #255 ; CHECK-CVT-NEXT: cmp w11, #255
; CHECK-CVT-NEXT: csel w11, w11, w8, lo ; CHECK-CVT-NEXT: csel w11, w11, w8, lo
; CHECK-CVT-NEXT: fmov s2, w10 ; CHECK-CVT-NEXT: fmov s1, w9
; CHECK-CVT-NEXT: fcvtzu w10, s1 ; CHECK-CVT-NEXT: fcvtzu w9, s0
; CHECK-CVT-NEXT: fmov s3, w11 ; CHECK-CVT-NEXT: cmp w15, #255
; CHECK-CVT-NEXT: mov v2.s[1], w9 ; CHECK-CVT-NEXT: fmov s2, w11
; CHECK-CVT-NEXT: cmp w10, #255 ; CHECK-CVT-NEXT: mov v1.s[1], w10
; CHECK-CVT-NEXT: csel w9, w10, w8, lo ; CHECK-CVT-NEXT: csel w10, w15, w8, lo
; CHECK-CVT-NEXT: fcvtzu w10, s0 ; CHECK-CVT-NEXT: cmp w9, #255
; CHECK-CVT-NEXT: mov v3.s[1], w14 ; CHECK-CVT-NEXT: csel w8, w9, w8, lo
; CHECK-CVT-NEXT: mov v2.s[2], w12 ; CHECK-CVT-NEXT: mov v1.s[2], w12
; CHECK-CVT-NEXT: cmp w10, #255 ; CHECK-CVT-NEXT: mov v2.s[1], w14
; CHECK-CVT-NEXT: csel w8, w10, w8, lo ; CHECK-CVT-NEXT: mov v1.s[3], w13
; CHECK-CVT-NEXT: mov v3.s[2], w9 ; CHECK-CVT-NEXT: mov v2.s[2], w10
; CHECK-CVT-NEXT: mov v2.s[3], w13 ; CHECK-CVT-NEXT: mov v2.s[3], w8
; CHECK-CVT-NEXT: mov v3.s[3], w8 ; CHECK-CVT-NEXT: uzp1 v0.8h, v2.8h, v1.8h
; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v2.8h
; CHECK-CVT-NEXT: xtn v0.8b, v0.8h ; CHECK-CVT-NEXT: xtn v0.8b, v0.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i8: ; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i8:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h ; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
; CHECK-FP16-NEXT: uqxtn v0.8b, v0.8h ; CHECK-FP16-NEXT: uqxtn v0.8b, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <8 x i8> @llvm.fptoui.sat.v8f16.v8i8(<8 x half> %f) %x = call <8 x i8> @llvm.fptoui.sat.v8f16.v8i8(<8 x half> %f)
ret <8 x i8> %x ret <8 x i8> %x
} }
define <8 x i13> @test_unsigned_v8f16_v8i13(<8 x half> %f) { define <8 x i13> @test_unsigned_v8f16_v8i13(<8 x half> %f) {
; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i13: ; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i13:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: fcvtl2 v1.4s, v0.8h ; CHECK-CVT-NEXT: fcvtl2 v1.4s, v0.8h
; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h ; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT: mov w8, #8191 ; CHECK-CVT-NEXT: mov w8, #8191
; CHECK-CVT-NEXT: mov s2, v1.s[1] ; CHECK-CVT-NEXT: mov s2, v1.s[1]
; CHECK-CVT-NEXT: mov s3, v1.s[2] ; CHECK-CVT-NEXT: mov s3, v1.s[2]
; CHECK-CVT-NEXT: mov s4, v1.s[3] ; CHECK-CVT-NEXT: mov s4, v1.s[3]
; CHECK-CVT-NEXT: mov s5, v0.s[1] ; CHECK-CVT-NEXT: mov s5, v0.s[1]
; CHECK-CVT-NEXT: fcvtzu w10, s1 ; CHECK-CVT-NEXT: fcvtzu w9, s1
; CHECK-CVT-NEXT: fcvtzu w11, s0 ; CHECK-CVT-NEXT: fcvtzu w11, s0
; CHECK-CVT-NEXT: mov s1, v0.s[2] ; CHECK-CVT-NEXT: mov s1, v0.s[2]
; CHECK-CVT-NEXT: mov s0, v0.s[3] ; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: fcvtzu w9, s2 ; CHECK-CVT-NEXT: fcvtzu w10, s2
; CHECK-CVT-NEXT: fcvtzu w12, s3 ; CHECK-CVT-NEXT: fcvtzu w12, s3
; CHECK-CVT-NEXT: fcvtzu w13, s4 ; CHECK-CVT-NEXT: fcvtzu w13, s4
; CHECK-CVT-NEXT: fcvtzu w14, s5 ; CHECK-CVT-NEXT: fcvtzu w14, s5
; CHECK-CVT-NEXT: cmp w9, w8
; CHECK-CVT-NEXT: csel w9, w9, w8, lo
; CHECK-CVT-NEXT: cmp w10, w8 ; CHECK-CVT-NEXT: cmp w10, w8
; CHECK-CVT-NEXT: fcvtzu w15, s1
; CHECK-CVT-NEXT: csel w10, w10, w8, lo ; CHECK-CVT-NEXT: csel w10, w10, w8, lo
; CHECK-CVT-NEXT: cmp w9, w8
; CHECK-CVT-NEXT: csel w9, w9, w8, lo
; CHECK-CVT-NEXT: cmp w12, w8 ; CHECK-CVT-NEXT: cmp w12, w8
; CHECK-CVT-NEXT: csel w12, w12, w8, lo ; CHECK-CVT-NEXT: csel w12, w12, w8, lo
; CHECK-CVT-NEXT: cmp w13, w8 ; CHECK-CVT-NEXT: cmp w13, w8
; CHECK-CVT-NEXT: csel w13, w13, w8, lo ; CHECK-CVT-NEXT: csel w13, w13, w8, lo
; CHECK-CVT-NEXT: cmp w14, w8 ; CHECK-CVT-NEXT: cmp w14, w8
; CHECK-CVT-NEXT: csel w14, w14, w8, lo ; CHECK-CVT-NEXT: csel w14, w14, w8, lo
; CHECK-CVT-NEXT: cmp w11, w8 ; CHECK-CVT-NEXT: cmp w11, w8
; CHECK-CVT-NEXT: csel w11, w11, w8, lo ; CHECK-CVT-NEXT: csel w11, w11, w8, lo
; CHECK-CVT-NEXT: fmov s2, w10 ; CHECK-CVT-NEXT: fmov s1, w9
; CHECK-CVT-NEXT: fcvtzu w10, s1 ; CHECK-CVT-NEXT: fcvtzu w9, s0
; CHECK-CVT-NEXT: fmov s3, w11 ; CHECK-CVT-NEXT: cmp w15, w8
; CHECK-CVT-NEXT: mov v2.s[1], w9 ; CHECK-CVT-NEXT: fmov s2, w11
; CHECK-CVT-NEXT: cmp w10, w8 ; CHECK-CVT-NEXT: mov v1.s[1], w10
; CHECK-CVT-NEXT: csel w9, w10, w8, lo ; CHECK-CVT-NEXT: csel w10, w15, w8, lo
; CHECK-CVT-NEXT: fcvtzu w10, s0 ; CHECK-CVT-NEXT: cmp w9, w8
; CHECK-CVT-NEXT: mov v3.s[1], w14 ; CHECK-CVT-NEXT: csel w8, w9, w8, lo
; CHECK-CVT-NEXT: mov v2.s[2], w12 ; CHECK-CVT-NEXT: mov v1.s[2], w12
; CHECK-CVT-NEXT: cmp w10, w8 ; CHECK-CVT-NEXT: mov v2.s[1], w14
; CHECK-CVT-NEXT: csel w8, w10, w8, lo ; CHECK-CVT-NEXT: mov v1.s[3], w13
; CHECK-CVT-NEXT: mov v3.s[2], w9 ; CHECK-CVT-NEXT: mov v2.s[2], w10
; CHECK-CVT-NEXT: mov v2.s[3], w13 ; CHECK-CVT-NEXT: mov v2.s[3], w8
; CHECK-CVT-NEXT: mov v3.s[3], w8 ; CHECK-CVT-NEXT: uzp1 v0.8h, v2.8h, v1.8h
; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v2.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i13: ; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i13:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h ; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
; CHECK-FP16-NEXT: mvni v1.8h, #224, lsl #8 ; CHECK-FP16-NEXT: mvni v1.8h, #224, lsl #8
; CHECK-FP16-NEXT: umin v0.8h, v0.8h, v1.8h ; CHECK-FP16-NEXT: umin v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <8 x i13> @llvm.fptoui.sat.v8f16.v8i13(<8 x half> %f) %x = call <8 x i13> @llvm.fptoui.sat.v8f16.v8i13(<8 x half> %f)
ret <8 x i13> %x ret <8 x i13> %x
} }
define <8 x i16> @test_unsigned_v8f16_v8i16(<8 x half> %f) { define <8 x i16> @test_unsigned_v8f16_v8i16(<8 x half> %f) {
; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i16: ; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i16:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: fcvtl2 v1.4s, v0.8h ; CHECK-CVT-NEXT: fcvtl2 v1.4s, v0.8h
; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h ; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT: mov w8, #65535 ; CHECK-CVT-NEXT: mov w8, #65535
; CHECK-CVT-NEXT: mov s2, v1.s[1] ; CHECK-CVT-NEXT: mov s2, v1.s[1]
; CHECK-CVT-NEXT: mov s3, v1.s[2] ; CHECK-CVT-NEXT: mov s3, v1.s[2]
; CHECK-CVT-NEXT: mov s4, v1.s[3] ; CHECK-CVT-NEXT: mov s4, v1.s[3]
; CHECK-CVT-NEXT: mov s5, v0.s[1] ; CHECK-CVT-NEXT: mov s5, v0.s[1]
; CHECK-CVT-NEXT: fcvtzu w10, s1 ; CHECK-CVT-NEXT: fcvtzu w9, s1
; CHECK-CVT-NEXT: fcvtzu w11, s0 ; CHECK-CVT-NEXT: fcvtzu w11, s0
; CHECK-CVT-NEXT: mov s1, v0.s[2] ; CHECK-CVT-NEXT: mov s1, v0.s[2]
; CHECK-CVT-NEXT: mov s0, v0.s[3] ; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: fcvtzu w9, s2 ; CHECK-CVT-NEXT: fcvtzu w10, s2
; CHECK-CVT-NEXT: fcvtzu w12, s3 ; CHECK-CVT-NEXT: fcvtzu w12, s3
; CHECK-CVT-NEXT: fcvtzu w13, s4 ; CHECK-CVT-NEXT: fcvtzu w13, s4
; CHECK-CVT-NEXT: fcvtzu w14, s5 ; CHECK-CVT-NEXT: fcvtzu w14, s5
; CHECK-CVT-NEXT: cmp w9, w8
; CHECK-CVT-NEXT: csel w9, w9, w8, lo
; CHECK-CVT-NEXT: cmp w10, w8 ; CHECK-CVT-NEXT: cmp w10, w8
; CHECK-CVT-NEXT: fcvtzu w15, s1
; CHECK-CVT-NEXT: csel w10, w10, w8, lo ; CHECK-CVT-NEXT: csel w10, w10, w8, lo
; CHECK-CVT-NEXT: cmp w9, w8
; CHECK-CVT-NEXT: csel w9, w9, w8, lo
; CHECK-CVT-NEXT: cmp w12, w8 ; CHECK-CVT-NEXT: cmp w12, w8
; CHECK-CVT-NEXT: csel w12, w12, w8, lo ; CHECK-CVT-NEXT: csel w12, w12, w8, lo
; CHECK-CVT-NEXT: cmp w13, w8 ; CHECK-CVT-NEXT: cmp w13, w8
; CHECK-CVT-NEXT: csel w13, w13, w8, lo ; CHECK-CVT-NEXT: csel w13, w13, w8, lo
; CHECK-CVT-NEXT: cmp w14, w8 ; CHECK-CVT-NEXT: cmp w14, w8
; CHECK-CVT-NEXT: csel w14, w14, w8, lo ; CHECK-CVT-NEXT: csel w14, w14, w8, lo
; CHECK-CVT-NEXT: cmp w11, w8 ; CHECK-CVT-NEXT: cmp w11, w8
; CHECK-CVT-NEXT: csel w11, w11, w8, lo ; CHECK-CVT-NEXT: csel w11, w11, w8, lo
; CHECK-CVT-NEXT: fmov s2, w10 ; CHECK-CVT-NEXT: fmov s1, w9
; CHECK-CVT-NEXT: fcvtzu w10, s1 ; CHECK-CVT-NEXT: fcvtzu w9, s0
; CHECK-CVT-NEXT: fmov s3, w11 ; CHECK-CVT-NEXT: cmp w15, w8
; CHECK-CVT-NEXT: mov v2.s[1], w9 ; CHECK-CVT-NEXT: fmov s2, w11
; CHECK-CVT-NEXT: cmp w10, w8 ; CHECK-CVT-NEXT: mov v1.s[1], w10
; CHECK-CVT-NEXT: csel w9, w10, w8, lo ; CHECK-CVT-NEXT: csel w10, w15, w8, lo
; CHECK-CVT-NEXT: fcvtzu w10, s0 ; CHECK-CVT-NEXT: cmp w9, w8
; CHECK-CVT-NEXT: mov v3.s[1], w14 ; CHECK-CVT-NEXT: csel w8, w9, w8, lo
; CHECK-CVT-NEXT: mov v2.s[2], w12 ; CHECK-CVT-NEXT: mov v1.s[2], w12
; CHECK-CVT-NEXT: cmp w10, w8 ; CHECK-CVT-NEXT: mov v2.s[1], w14
; CHECK-CVT-NEXT: csel w8, w10, w8, lo ; CHECK-CVT-NEXT: mov v1.s[3], w13
; CHECK-CVT-NEXT: mov v3.s[2], w9 ; CHECK-CVT-NEXT: mov v2.s[2], w10
; CHECK-CVT-NEXT: mov v2.s[3], w13 ; CHECK-CVT-NEXT: mov v2.s[3], w8
; CHECK-CVT-NEXT: mov v3.s[3], w8 ; CHECK-CVT-NEXT: uzp1 v0.8h, v2.8h, v1.8h
; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v2.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i16: ; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i16:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h ; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <8 x i16> @llvm.fptoui.sat.v8f16.v8i16(<8 x half> %f) %x = call <8 x i16> @llvm.fptoui.sat.v8f16.v8i16(<8 x half> %f)
ret <8 x i16> %x ret <8 x i16> %x
} }
define <8 x i19> @test_unsigned_v8f16_v8i19(<8 x half> %f) { define <8 x i19> @test_unsigned_v8f16_v8i19(<8 x half> %f) {
; CHECK-LABEL: test_unsigned_v8f16_v8i19: ; CHECK-LABEL: test_unsigned_v8f16_v8i19:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtl v2.4s, v0.4h ; CHECK-NEXT: fcvtl2 v2.4s, v0.8h
; CHECK-NEXT: fcvtl2 v0.4s, v0.8h ; CHECK-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NEXT: movi v1.4s, #7, msl #16 ; CHECK-NEXT: movi v1.4s, #7, msl #16
; CHECK-NEXT: fcvtzu v2.4s, v2.4s ; CHECK-NEXT: fcvtzu v2.4s, v2.4s
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: umin v2.4s, v2.4s, v1.4s ; CHECK-NEXT: umin v2.4s, v2.4s, v1.4s
; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s ; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
; CHECK-NEXT: mov w1, v2.s[1] ; CHECK-NEXT: fmov w4, s2
; CHECK-NEXT: mov w2, v2.s[2] ; CHECK-NEXT: mov w5, v2.s[1]
; CHECK-NEXT: mov w5, v0.s[1] ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: mov w3, v2.s[3] ; CHECK-NEXT: mov w6, v2.s[2]
; CHECK-NEXT: mov w6, v0.s[2] ; CHECK-NEXT: mov w7, v2.s[3]
; CHECK-NEXT: mov w7, v0.s[3] ; CHECK-NEXT: mov w1, v0.s[1]
; CHECK-NEXT: fmov w4, s0 ; CHECK-NEXT: mov w2, v0.s[2]
; CHECK-NEXT: fmov w0, s2 ; CHECK-NEXT: mov w3, v0.s[3]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <8 x i19> @llvm.fptoui.sat.v8f16.v8i19(<8 x half> %f) %x = call <8 x i19> @llvm.fptoui.sat.v8f16.v8i19(<8 x half> %f)
ret <8 x i19> %x ret <8 x i19> %x
} }
define <8 x i32> @test_unsigned_v8f16_v8i32_duplicate(<8 x half> %f) { define <8 x i32> @test_unsigned_v8f16_v8i32_duplicate(<8 x half> %f) {
; CHECK-LABEL: test_unsigned_v8f16_v8i32_duplicate: ; CHECK-LABEL: test_unsigned_v8f16_v8i32_duplicate:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtl2 v1.4s, v0.8h ; CHECK-NEXT: fcvtl2 v1.4s, v0.8h
; CHECK-NEXT: fcvtl v0.4s, v0.4h ; CHECK-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NEXT: fcvtzu v1.4s, v1.4s ; CHECK-NEXT: fcvtzu v1.4s, v1.4s
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <8 x i32> @llvm.fptoui.sat.v8f16.v8i32(<8 x half> %f) %x = call <8 x i32> @llvm.fptoui.sat.v8f16.v8i32(<8 x half> %f)
ret <8 x i32> %x ret <8 x i32> %x
} }
define <8 x i50> @test_unsigned_v8f16_v8i50(<8 x half> %f) { define <8 x i50> @test_unsigned_v8f16_v8i50(<8 x half> %f) {
; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i50: ; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i50:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-CVT-NEXT: mov x8, #1125899906842623 ; CHECK-CVT-NEXT: mov x8, #1125899906842623
; CHECK-CVT-NEXT: mov h2, v0.h[1] ; CHECK-CVT-NEXT: mov h2, v0.h[1]
; CHECK-CVT-NEXT: mov h4, v1.h[1]
; CHECK-CVT-NEXT: mov h6, v1.h[2]
; CHECK-CVT-NEXT: mov h3, v0.h[2] ; CHECK-CVT-NEXT: mov h3, v0.h[2]
; CHECK-CVT-NEXT: mov h5, v0.h[3] ; CHECK-CVT-NEXT: mov h5, v0.h[3]
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov h4, v1.h[1]
; CHECK-CVT-NEXT: mov h6, v1.h[2]
; CHECK-CVT-NEXT: mov h7, v1.h[3] ; CHECK-CVT-NEXT: mov h7, v1.h[3]
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvtzu x9, s0
; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvt s4, h4 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcvt s6, h6 ; CHECK-CVT-NEXT: fcvt s6, h6
; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvtzu x9, s0
; CHECK-CVT-NEXT: fcvt s0, h7 ; CHECK-CVT-NEXT: fcvt s0, h7
; CHECK-CVT-NEXT: fcvtzu x10, s1 ; CHECK-CVT-NEXT: fcvtzu x10, s1
; CHECK-CVT-NEXT: fcvtzu x11, s2 ; CHECK-CVT-NEXT: fcvtzu x11, s2
; CHECK-CVT-NEXT: fcvtzu x12, s3
; CHECK-CVT-NEXT: fcvtzu x14, s5
; CHECK-CVT-NEXT: fcvtzu x13, s4 ; CHECK-CVT-NEXT: fcvtzu x13, s4
; CHECK-CVT-NEXT: fcvtzu x15, s6 ; CHECK-CVT-NEXT: fcvtzu x15, s6
; CHECK-CVT-NEXT: fcvtzu x12, s3
; CHECK-CVT-NEXT: fcvtzu x14, s5
; CHECK-CVT-NEXT: cmp x10, x8 ; CHECK-CVT-NEXT: cmp x10, x8
; CHECK-CVT-NEXT: fcvtzu x16, s0 ; CHECK-CVT-NEXT: fcvtzu x16, s0
; CHECK-CVT-NEXT: csel x4, x10, x8, lo ; CHECK-CVT-NEXT: csel x4, x10, x8, lo
; CHECK-CVT-NEXT: cmp x13, x8 ; CHECK-CVT-NEXT: cmp x13, x8
; CHECK-CVT-NEXT: csel x5, x13, x8, lo ; CHECK-CVT-NEXT: csel x5, x13, x8, lo
; CHECK-CVT-NEXT: cmp x15, x8 ; CHECK-CVT-NEXT: cmp x15, x8
; CHECK-CVT-NEXT: csel x6, x15, x8, lo ; CHECK-CVT-NEXT: csel x6, x15, x8, lo
; CHECK-CVT-NEXT: cmp x16, x8 ; CHECK-CVT-NEXT: cmp x16, x8
; CHECK-CVT-NEXT: csel x7, x16, x8, lo ; CHECK-CVT-NEXT: csel x7, x16, x8, lo
; CHECK-CVT-NEXT: cmp x9, x8 ; CHECK-CVT-NEXT: cmp x9, x8
; CHECK-CVT-NEXT: csel x0, x9, x8, lo ; CHECK-CVT-NEXT: csel x0, x9, x8, lo
; CHECK-CVT-NEXT: cmp x11, x8 ; CHECK-CVT-NEXT: cmp x11, x8
; CHECK-CVT-NEXT: csel x1, x11, x8, lo ; CHECK-CVT-NEXT: csel x1, x11, x8, lo
; CHECK-CVT-NEXT: cmp x12, x8 ; CHECK-CVT-NEXT: cmp x12, x8
; CHECK-CVT-NEXT: csel x2, x12, x8, lo ; CHECK-CVT-NEXT: csel x2, x12, x8, lo
; CHECK-CVT-NEXT: cmp x14, x8 ; CHECK-CVT-NEXT: cmp x14, x8
; CHECK-CVT-NEXT: csel x3, x14, x8, lo ; CHECK-CVT-NEXT: csel x3, x14, x8, lo
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i50: ; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i50:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-FP16-NEXT: mov x8, #1125899906842623 ; CHECK-FP16-NEXT: mov x8, #1125899906842623
; CHECK-FP16-NEXT: mov h2, v0.h[1] ; CHECK-FP16-NEXT: mov h2, v0.h[1]
; CHECK-FP16-NEXT: mov h4, v1.h[1]
; CHECK-FP16-NEXT: mov h6, v1.h[2]
; CHECK-FP16-NEXT: mov h3, v0.h[2] ; CHECK-FP16-NEXT: mov h3, v0.h[2]
; CHECK-FP16-NEXT: mov h5, v0.h[3] ; CHECK-FP16-NEXT: mov h5, v0.h[3]
; CHECK-FP16-NEXT: fcvtzu x9, h0 ; CHECK-FP16-NEXT: fcvtzu x9, h0
; CHECK-FP16-NEXT: mov h4, v1.h[1]
; CHECK-FP16-NEXT: mov h6, v1.h[2]
; CHECK-FP16-NEXT: mov h0, v1.h[3] ; CHECK-FP16-NEXT: mov h0, v1.h[3]
; CHECK-FP16-NEXT: fcvtzu x10, h1 ; CHECK-FP16-NEXT: fcvtzu x10, h1
; CHECK-FP16-NEXT: fcvtzu x11, h2 ; CHECK-FP16-NEXT: fcvtzu x11, h2
; CHECK-FP16-NEXT: fcvtzu x12, h3
; CHECK-FP16-NEXT: fcvtzu x14, h5
; CHECK-FP16-NEXT: fcvtzu x13, h4 ; CHECK-FP16-NEXT: fcvtzu x13, h4
; CHECK-FP16-NEXT: fcvtzu x15, h6 ; CHECK-FP16-NEXT: fcvtzu x15, h6
; CHECK-FP16-NEXT: fcvtzu x12, h3
; CHECK-FP16-NEXT: fcvtzu x14, h5
; CHECK-FP16-NEXT: cmp x10, x8 ; CHECK-FP16-NEXT: cmp x10, x8
; CHECK-FP16-NEXT: fcvtzu x16, h0 ; CHECK-FP16-NEXT: fcvtzu x16, h0
; CHECK-FP16-NEXT: csel x4, x10, x8, lo ; CHECK-FP16-NEXT: csel x4, x10, x8, lo
; CHECK-FP16-NEXT: cmp x13, x8 ; CHECK-FP16-NEXT: cmp x13, x8
; CHECK-FP16-NEXT: csel x5, x13, x8, lo ; CHECK-FP16-NEXT: csel x5, x13, x8, lo
; CHECK-FP16-NEXT: cmp x15, x8 ; CHECK-FP16-NEXT: cmp x15, x8
; CHECK-FP16-NEXT: csel x6, x15, x8, lo ; CHECK-FP16-NEXT: csel x6, x15, x8, lo
; CHECK-FP16-NEXT: cmp x16, x8 ; CHECK-FP16-NEXT: cmp x16, x8
Show All 10 Lines; CHECK-FP16-NEXT: ret
%x = call <8 x i50> @llvm.fptoui.sat.v8f16.v8i50(<8 x half> %f) %x = call <8 x i50> @llvm.fptoui.sat.v8f16.v8i50(<8 x half> %f)
ret <8 x i50> %x ret <8 x i50> %x
} }
define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) { define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i64: ; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i64:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-CVT-NEXT: mov h4, v0.h[2] ; CHECK-CVT-NEXT: mov h2, v0.h[2]
; CHECK-CVT-NEXT: fcvt s5, h0 ; CHECK-CVT-NEXT: fcvt s4, h0
; CHECK-CVT-NEXT: fcvt s2, h1 ; CHECK-CVT-NEXT: mov h5, v1.h[2]
; CHECK-CVT-NEXT: fcvt s7, h1
; CHECK-CVT-NEXT: mov h3, v1.h[1] ; CHECK-CVT-NEXT: mov h3, v1.h[1]
; CHECK-CVT-NEXT: mov h6, v1.h[2] ; CHECK-CVT-NEXT: mov h6, v0.h[1]
; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: mov h1, v1.h[3]
; CHECK-CVT-NEXT: fcvtzu x9, s5
; CHECK-CVT-NEXT: fcvtzu x8, s2
; CHECK-CVT-NEXT: fcvt s2, h3
; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: mov h0, v0.h[3] ; CHECK-CVT-NEXT: mov h0, v0.h[3]
; CHECK-CVT-NEXT: fcvt s5, h6 ; CHECK-CVT-NEXT: mov h1, v1.h[3]
; CHECK-CVT-NEXT: fcvt s6, h1 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvtzu x10, s2
; CHECK-CVT-NEXT: fmov d2, x8
; CHECK-CVT-NEXT: fcvtzu x8, s4 ; CHECK-CVT-NEXT: fcvtzu x8, s4
; CHECK-CVT-NEXT: fcvt s4, h5
; CHECK-CVT-NEXT: fcvtzu x9, s7
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s4, h0 ; CHECK-CVT-NEXT: fcvt s5, h6
; CHECK-CVT-NEXT: fmov d0, x9 ; CHECK-CVT-NEXT: fcvt s6, h0
; CHECK-CVT-NEXT: mov v2.d[1], x10 ; CHECK-CVT-NEXT: fcvt s7, h1
; CHECK-CVT-NEXT: fcvtzu x10, s5 ; CHECK-CVT-NEXT: fcvtzu x10, s2
; CHECK-CVT-NEXT: fmov d1, x8 ; CHECK-CVT-NEXT: fmov d2, x9
; CHECK-CVT-NEXT: fcvtzu x9, s3 ; CHECK-CVT-NEXT: fcvtzu x9, s4
; CHECK-CVT-NEXT: fcvtzu x8, s4 ; CHECK-CVT-NEXT: fmov d0, x8
; CHECK-CVT-NEXT: fmov d3, x10 ; CHECK-CVT-NEXT: fcvtzu x11, s3
; CHECK-CVT-NEXT: fcvtzu x8, s5
; CHECK-CVT-NEXT: fmov d1, x10
; CHECK-CVT-NEXT: fcvtzu x10, s6 ; CHECK-CVT-NEXT: fcvtzu x10, s6
; CHECK-CVT-NEXT: mov v0.d[1], x9 ; CHECK-CVT-NEXT: fmov d3, x9
; CHECK-CVT-NEXT: mov v1.d[1], x8 ; CHECK-CVT-NEXT: fcvtzu x9, s7
; CHECK-CVT-NEXT: mov v3.d[1], x10 ; CHECK-CVT-NEXT: mov v0.d[1], x8
; CHECK-CVT-NEXT: mov v2.d[1], x11
; CHECK-CVT-NEXT: mov v1.d[1], x10
; CHECK-CVT-NEXT: mov v3.d[1], x9
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i64: ; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i64:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-FP16-NEXT: ext v2.16b, v0.16b, v0.16b, #8
; CHECK-FP16-NEXT: mov h3, v0.h[2] ; CHECK-FP16-NEXT: mov h1, v0.h[2]
; CHECK-FP16-NEXT: mov h5, v0.h[3] ; CHECK-FP16-NEXT: mov h5, v0.h[3]
; CHECK-FP16-NEXT: fcvtzu x9, h0 ; CHECK-FP16-NEXT: mov h4, v2.h[2]
; CHECK-FP16-NEXT: mov h2, v1.h[1] ; CHECK-FP16-NEXT: fcvtzu x9, h2
; CHECK-FP16-NEXT: mov h3, v2.h[1]
; CHECK-FP16-NEXT: mov h6, v2.h[3]
; CHECK-FP16-NEXT: fcvtzu x8, h1 ; CHECK-FP16-NEXT: fcvtzu x8, h1
; CHECK-FP16-NEXT: mov h4, v1.h[2] ; CHECK-FP16-NEXT: mov h1, v0.h[1]
; CHECK-FP16-NEXT: mov h6, v1.h[3] ; CHECK-FP16-NEXT: fcvtzu x10, h0
; CHECK-FP16-NEXT: fcvtzu x10, h2 ; CHECK-FP16-NEXT: fmov d2, x9
; CHECK-FP16-NEXT: fmov d2, x8 ; CHECK-FP16-NEXT: fcvtzu x9, h4
; CHECK-FP16-NEXT: fcvtzu x8, h3 ; CHECK-FP16-NEXT: fcvtzu x11, h3
; CHECK-FP16-NEXT: mov h3, v0.h[1] ; CHECK-FP16-NEXT: fmov d0, x10
; CHECK-FP16-NEXT: fmov d0, x9 ; CHECK-FP16-NEXT: fcvtzu x10, h1
; CHECK-FP16-NEXT: mov v2.d[1], x10
; CHECK-FP16-NEXT: fcvtzu x10, h4
; CHECK-FP16-NEXT: fmov d1, x8 ; CHECK-FP16-NEXT: fmov d1, x8
; CHECK-FP16-NEXT: fcvtzu x9, h3
; CHECK-FP16-NEXT: fcvtzu x8, h5 ; CHECK-FP16-NEXT: fcvtzu x8, h5
; CHECK-FP16-NEXT: fmov d3, x10 ; CHECK-FP16-NEXT: fmov d3, x9
; CHECK-FP16-NEXT: fcvtzu x10, h6 ; CHECK-FP16-NEXT: fcvtzu x9, h6
; CHECK-FP16-NEXT: mov v0.d[1], x9 ; CHECK-FP16-NEXT: mov v0.d[1], x10
; CHECK-FP16-NEXT: mov v2.d[1], x11
; CHECK-FP16-NEXT: mov v1.d[1], x8 ; CHECK-FP16-NEXT: mov v1.d[1], x8
; CHECK-FP16-NEXT: mov v3.d[1], x10 ; CHECK-FP16-NEXT: mov v3.d[1], x9
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <8 x i64> @llvm.fptoui.sat.v8f16.v8i64(<8 x half> %f) %x = call <8 x i64> @llvm.fptoui.sat.v8f16.v8i64(<8 x half> %f)
ret <8 x i64> %x ret <8 x i64> %x
} }
define <8 x i100> @test_unsigned_v8f16_v8i100(<8 x half> %f) { define <8 x i100> @test_unsigned_v8f16_v8i100(<8 x half> %f) {
; CHECK-LABEL: test_unsigned_v8f16_v8i100: ; CHECK-LABEL: test_unsigned_v8f16_v8i100:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
Show All 26 Lines
; CHECK-NEXT: str q0, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: mov h0, v0.h[1] ; CHECK-NEXT: mov h0, v0.h[1]
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: mov w8, #1904214015 ; CHECK-NEXT: mov w8, #1904214015
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: mov x21, #68719476735 ; CHECK-NEXT: mov x24, #68719476735
; CHECK-NEXT: mov h0, v0.h[3] ; CHECK-NEXT: mov h0, v0.h[3]
; CHECK-NEXT: fmov s9, w8 ; CHECK-NEXT: fmov s9, w8
; CHECK-NEXT: csel x8, xzr, x1, lt ; CHECK-NEXT: csel x8, xzr, x1, lt
; CHECK-NEXT: csel x9, xzr, x0, lt ; CHECK-NEXT: csel x9, xzr, x0, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csinv x9, x9, xzr, le ; CHECK-NEXT: csinv x9, x9, xzr, le
; CHECK-NEXT: csel x20, x21, x8, gt ; CHECK-NEXT: csel x20, x24, x8, gt
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: str x9, [sp, #24] // 8-byte Folded Spill ; CHECK-NEXT: str x9, [sp, #24] // 8-byte Folded Spill
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: csel x8, xzr, x1, lt ; CHECK-NEXT: csel x8, xzr, x1, lt
; CHECK-NEXT: csel x9, xzr, x0, lt ; CHECK-NEXT: csel x9, xzr, x0, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csinv x9, x9, xzr, le ; CHECK-NEXT: csinv x9, x9, xzr, le
; CHECK-NEXT: csel x23, x21, x8, gt ; CHECK-NEXT: csel x22, x24, x8, gt
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: str x9, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x9, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: mov h0, v0.h[2] ; CHECK-NEXT: mov h0, v0.h[2]
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csel x24, x21, x9, gt ; CHECK-NEXT: csel x23, x24, x9, gt
; CHECK-NEXT: str x8, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x8, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: mov h0, v0.h[1] ; CHECK-NEXT: mov h0, v0.h[1]
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csel x26, x21, x9, gt ; CHECK-NEXT: csel x26, x24, x9, gt
; CHECK-NEXT: str x8, [sp, #8] // 8-byte Folded Spill ; CHECK-NEXT: str x8, [sp, #8] // 8-byte Folded Spill
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: mov h0, v0.h[3] ; CHECK-NEXT: mov h0, v0.h[3]
; CHECK-NEXT: csel x8, xzr, x1, lt ; CHECK-NEXT: csel x8, xzr, x1, lt
; CHECK-NEXT: csel x9, xzr, x0, lt ; CHECK-NEXT: csel x9, xzr, x0, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csinv x29, x9, xzr, le ; CHECK-NEXT: csinv x27, x9, xzr, le
; CHECK-NEXT: csel x28, x21, x8, gt ; CHECK-NEXT: csel x29, x24, x8, gt
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: csel x8, xzr, x1, lt ; CHECK-NEXT: csel x8, xzr, x1, lt
; CHECK-NEXT: csel x9, xzr, x0, lt ; CHECK-NEXT: csel x9, xzr, x0, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csinv x27, x9, xzr, le ; CHECK-NEXT: csinv x28, x9, xzr, le
; CHECK-NEXT: csel x22, x21, x8, gt ; CHECK-NEXT: csel x25, x24, x8, gt
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: mov h0, v0.h[2] ; CHECK-NEXT: mov h0, v0.h[2]
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csel x25, x21, x9, gt ; CHECK-NEXT: csel x21, x24, x9, gt
; CHECK-NEXT: str x8, [sp] // 8-byte Folded Spill ; CHECK-NEXT: str x8, [sp] // 8-byte Folded Spill
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: ldr x11, [sp, #8] // 8-byte Folded Reload
; CHECK-NEXT: fmov d0, x27
; CHECK-NEXT: fmov d1, x29
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: lsr x10, x22, #28 ; CHECK-NEXT: lsr x8, x25, #28
; CHECK-NEXT: stur x11, [x19, #75] ; CHECK-NEXT: fmov d0, x28
; CHECK-NEXT: lsr x11, x28, #28 ; CHECK-NEXT: lsr x11, x29, #28
; CHECK-NEXT: mov v0.d[1], x22 ; CHECK-NEXT: fmov d1, x27
; CHECK-NEXT: ldr x12, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: csel x9, xzr, x0, lt
; CHECK-NEXT: mov v1.d[1], x28 ; CHECK-NEXT: csel x10, xzr, x1, lt
; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: stur x12, [x19, #50] ; CHECK-NEXT: strb w8, [x19, #49]
; CHECK-NEXT: fmov x12, d0 ; CHECK-NEXT: mov v0.d[1], x25
; CHECK-NEXT: fmov x13, d1
; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: ldp d0, d1, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: csel x9, x21, x9, gt
; CHECK-NEXT: strb w10, [x19, #49]
; CHECK-NEXT: extr x10, x22, x12, #28
; CHECK-NEXT: bfi x9, x12, #36, #28
; CHECK-NEXT: stur x8, [x19, #25]
; CHECK-NEXT: extr x8, x28, x13, #28
; CHECK-NEXT: mov v0.d[1], x23
; CHECK-NEXT: strb w11, [x19, #24] ; CHECK-NEXT: strb w11, [x19, #24]
; CHECK-NEXT: mov v1.d[1], x20 ; CHECK-NEXT: ldr x11, [sp, #8] // 8-byte Folded Reload
; CHECK-NEXT: stur x10, [x19, #41] ; CHECK-NEXT: mov v1.d[1], x29
; CHECK-NEXT: stur x9, [x19, #33] ; CHECK-NEXT: csinv x8, x9, xzr, le
; CHECK-NEXT: bfi x25, x13, #36, #28 ; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: str x8, [x19, #16] ; CHECK-NEXT: csel x10, x24, x10, gt
; CHECK-NEXT: lsr x9, x23, #28 ; CHECK-NEXT: stur x11, [x19, #75]
; CHECK-NEXT: fmov x11, d1
; CHECK-NEXT: stur x8, [x19, #25]
; CHECK-NEXT: extr x8, x25, x9, #28
; CHECK-NEXT: bfi x10, x9, #36, #28
; CHECK-NEXT: ldr x9, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: ldr d0, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: bfi x21, x11, #36, #28
; CHECK-NEXT: stur x8, [x19, #41]
; CHECK-NEXT: stur x9, [x19, #50]
; CHECK-NEXT: extr x9, x29, x11, #28
; CHECK-NEXT: ldr d1, [sp, #24] // 8-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x22
; CHECK-NEXT: stur x10, [x19, #33]
; CHECK-NEXT: lsr x10, x20, #28
; CHECK-NEXT: str x9, [x19, #16]
; CHECK-NEXT: fmov x8, d0 ; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: mov v1.d[1], x20
; CHECK-NEXT: ldr x12, [sp] // 8-byte Folded Reload ; CHECK-NEXT: ldr x12, [sp] // 8-byte Folded Reload
; CHECK-NEXT: lsr x9, x22, #28
; CHECK-NEXT: strb w10, [x19, #74]
; CHECK-NEXT: fmov x11, d1 ; CHECK-NEXT: fmov x11, d1
; CHECK-NEXT: lsr x10, x20, #28
; CHECK-NEXT: strb w9, [x19, #99]
; CHECK-NEXT: stp x12, x25, [x19]
; CHECK-NEXT: extr x12, x23, x8, #28
; CHECK-NEXT: bfi x26, x8, #36, #28 ; CHECK-NEXT: bfi x26, x8, #36, #28
; CHECK-NEXT: stp x12, x21, [x19]
; CHECK-NEXT: extr x12, x22, x8, #28
; CHECK-NEXT: strb w9, [x19, #99]
; CHECK-NEXT: extr x8, x20, x11, #28 ; CHECK-NEXT: extr x8, x20, x11, #28
; CHECK-NEXT: bfi x24, x11, #36, #28 ; CHECK-NEXT: bfi x23, x11, #36, #28
; CHECK-NEXT: strb w10, [x19, #74]
; CHECK-NEXT: stur x12, [x19, #91] ; CHECK-NEXT: stur x12, [x19, #91]
; CHECK-NEXT: stur x26, [x19, #83] ; CHECK-NEXT: stur x26, [x19, #83]
; CHECK-NEXT: stur x8, [x19, #66] ; CHECK-NEXT: stur x8, [x19, #66]
; CHECK-NEXT: stur x24, [x19, #58] ; CHECK-NEXT: stur x23, [x19, #58]
; CHECK-NEXT: ldp x20, x19, [sp, #160] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #160] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #144] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #144] // 16-byte Folded Reload
; CHECK-NEXT: ldp x24, x23, [sp, #128] // 16-byte Folded Reload ; CHECK-NEXT: ldp x24, x23, [sp, #128] // 16-byte Folded Reload
; CHECK-NEXT: ldp x26, x25, [sp, #112] // 16-byte Folded Reload ; CHECK-NEXT: ldp x26, x25, [sp, #112] // 16-byte Folded Reload
; CHECK-NEXT: ldp x28, x27, [sp, #96] // 16-byte Folded Reload ; CHECK-NEXT: ldp x28, x27, [sp, #96] // 16-byte Folded Reload
; CHECK-NEXT: ldp x29, x30, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #176 ; CHECK-NEXT: add sp, sp, #176
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Lines
declare <8 x i8> @llvm.fptoui.sat.v8f64.v8i8(<8 x double> %f) declare <8 x i8> @llvm.fptoui.sat.v8f64.v8i8(<8 x double> %f)
declare <8 x i16> @llvm.fptoui.sat.v8f64.v8i16(<8 x double> %f) declare <8 x i16> @llvm.fptoui.sat.v8f64.v8i16(<8 x double> %f)
declare <16 x i8> @llvm.fptoui.sat.v16f64.v16i8(<16 x double> %f) declare <16 x i8> @llvm.fptoui.sat.v16f64.v16i8(<16 x double> %f)
declare <16 x i16> @llvm.fptoui.sat.v16f64.v16i16(<16 x double> %f) declare <16 x i16> @llvm.fptoui.sat.v16f64.v16i16(<16 x double> %f)
define <8 x i8> @test_unsigned_v8f32_v8i8(<8 x float> %f) { define <8 x i8> @test_unsigned_v8f32_v8i8(<8 x float> %f) {
; CHECK-LABEL: test_unsigned_v8f32_v8i8: ; CHECK-LABEL: test_unsigned_v8f32_v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.2d, #0x0000ff000000ff
; CHECK-NEXT: fcvtzu v1.4s, v1.4s ; CHECK-NEXT: fcvtzu v1.4s, v1.4s
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: movi v2.2d, #0x0000ff000000ff
; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s ; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s
; CHECK-NEXT: umin v0.4s, v0.4s, v2.4s ; CHECK-NEXT: umin v0.4s, v0.4s, v2.4s
; CHECK-NEXT: xtn v1.4h, v1.4s ; CHECK-NEXT: xtn v1.4h, v1.4s
; CHECK-NEXT: xtn v0.4h, v0.4s ; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: uzp1 v0.8b, v0.8b, v1.8b ; CHECK-NEXT: uzp1 v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <8 x i8> @llvm.fptoui.sat.v8f32.v8i8(<8 x float> %f) %x = call <8 x i8> @llvm.fptoui.sat.v8f32.v8i8(<8 x float> %f)
ret <8 x i8> %x ret <8 x i8> %x
} }
define <16 x i8> @test_unsigned_v16f32_v16i8(<16 x float> %f) { define <16 x i8> @test_unsigned_v16f32_v16i8(<16 x float> %f) {
; CHECK-LABEL: test_unsigned_v16f32_v16i8: ; CHECK-LABEL: test_unsigned_v16f32_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v4.2d, #0x0000ff000000ff
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: fcvtzu v1.4s, v1.4s ; CHECK-NEXT: fcvtzu v1.4s, v1.4s
; CHECK-NEXT: movi v4.2d, #0x0000ff000000ff
; CHECK-NEXT: fcvtzu v2.4s, v2.4s ; CHECK-NEXT: fcvtzu v2.4s, v2.4s
; CHECK-NEXT: fcvtzu v3.4s, v3.4s
; CHECK-NEXT: umin v0.4s, v0.4s, v4.4s ; CHECK-NEXT: umin v0.4s, v0.4s, v4.4s
; CHECK-NEXT: umin v1.4s, v1.4s, v4.4s ; CHECK-NEXT: umin v1.4s, v1.4s, v4.4s
; CHECK-NEXT: umin v2.4s, v2.4s, v4.4s ; CHECK-NEXT: umin v2.4s, v2.4s, v4.4s
; CHECK-NEXT: umin v3.4s, v3.4s, v4.4s
; CHECK-NEXT: xtn v5.4h, v0.4s ; CHECK-NEXT: xtn v5.4h, v0.4s
; CHECK-NEXT: xtn v1.4h, v1.4s ; CHECK-NEXT: xtn v1.4h, v1.4s
; CHECK-NEXT: umov w8, v5.h[0] ; CHECK-NEXT: umov w8, v5.h[0]
; CHECK-NEXT: umov w9, v5.h[1] ; CHECK-NEXT: umov w9, v5.h[2]
; CHECK-NEXT: xtn v2.4h, v2.4s
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: umov w8, v5.h[2] ; CHECK-NEXT: umov w8, v5.h[1]
; CHECK-NEXT: mov v0.b[1], w9 ; CHECK-NEXT: mov v0.b[1], w8
; CHECK-NEXT: mov v0.b[2], w8
; CHECK-NEXT: umov w8, v5.h[3] ; CHECK-NEXT: umov w8, v5.h[3]
; CHECK-NEXT: mov v0.b[2], w9
; CHECK-NEXT: umov w9, v1.h[0]
; CHECK-NEXT: mov v0.b[3], w8 ; CHECK-NEXT: mov v0.b[3], w8
; CHECK-NEXT: umov w8, v1.h[0]
; CHECK-NEXT: mov v0.b[4], w8
; CHECK-NEXT: umov w8, v1.h[1] ; CHECK-NEXT: umov w8, v1.h[1]
; CHECK-NEXT: mov v0.b[4], w9
; CHECK-NEXT: umov w9, v1.h[2]
; CHECK-NEXT: mov v0.b[5], w8 ; CHECK-NEXT: mov v0.b[5], w8
; CHECK-NEXT: umov w8, v1.h[2]
; CHECK-NEXT: mov v0.b[6], w8
; CHECK-NEXT: umov w8, v1.h[3] ; CHECK-NEXT: umov w8, v1.h[3]
; CHECK-NEXT: xtn v1.4h, v2.4s ; CHECK-NEXT: xtn v1.4h, v3.4s
; CHECK-NEXT: fcvtzu v2.4s, v3.4s ; CHECK-NEXT: mov v0.b[6], w9
; CHECK-NEXT: umov w9, v2.h[0]
; CHECK-NEXT: mov v0.b[7], w8 ; CHECK-NEXT: mov v0.b[7], w8
; CHECK-NEXT: umov w8, v1.h[0] ; CHECK-NEXT: umov w8, v2.h[1]
; CHECK-NEXT: umin v2.4s, v2.4s, v4.4s ; CHECK-NEXT: mov v0.b[8], w9
; CHECK-NEXT: mov v0.b[8], w8 ; CHECK-NEXT: umov w9, v2.h[2]
; CHECK-NEXT: umov w8, v1.h[1]
; CHECK-NEXT: mov v0.b[9], w8 ; CHECK-NEXT: mov v0.b[9], w8
; CHECK-NEXT: umov w8, v1.h[2] ; CHECK-NEXT: umov w8, v2.h[3]
; CHECK-NEXT: mov v0.b[10], w8 ; CHECK-NEXT: mov v0.b[10], w9
; CHECK-NEXT: umov w8, v1.h[3]
; CHECK-NEXT: xtn v1.4h, v2.4s
; CHECK-NEXT: mov v0.b[11], w8 ; CHECK-NEXT: mov v0.b[11], w8
; CHECK-NEXT: umov w8, v1.h[0] ; CHECK-NEXT: umov w8, v1.h[0]
; CHECK-NEXT: mov v0.b[12], w8 ; CHECK-NEXT: mov v0.b[12], w8
; CHECK-NEXT: umov w8, v1.h[1] ; CHECK-NEXT: umov w8, v1.h[1]
; CHECK-NEXT: mov v0.b[13], w8 ; CHECK-NEXT: mov v0.b[13], w8
; CHECK-NEXT: umov w8, v1.h[2] ; CHECK-NEXT: umov w8, v1.h[2]
; CHECK-NEXT: mov v0.b[14], w8 ; CHECK-NEXT: mov v0.b[14], w8
; CHECK-NEXT: umov w8, v1.h[3] ; CHECK-NEXT: umov w8, v1.h[3]
; CHECK-NEXT: mov v0.b[15], w8 ; CHECK-NEXT: mov v0.b[15], w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <16 x i8> @llvm.fptoui.sat.v16f32.v16i8(<16 x float> %f) %x = call <16 x i8> @llvm.fptoui.sat.v16f32.v16i8(<16 x float> %f)
ret <16 x i8> %x ret <16 x i8> %x
} }
define <8 x i16> @test_unsigned_v8f32_v8i16(<8 x float> %f) { define <8 x i16> @test_unsigned_v8f32_v8i16(<8 x float> %f) {
; CHECK-LABEL: test_unsigned_v8f32_v8i16: ; CHECK-LABEL: test_unsigned_v8f32_v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
; CHECK-NEXT: fcvtzu v1.4s, v1.4s ; CHECK-NEXT: fcvtzu v1.4s, v1.4s
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s ; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s
; CHECK-NEXT: umin v0.4s, v0.4s, v2.4s ; CHECK-NEXT: umin v0.4s, v0.4s, v2.4s
; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <8 x i16> @llvm.fptoui.sat.v8f32.v8i16(<8 x float> %f) %x = call <8 x i16> @llvm.fptoui.sat.v8f32.v8i16(<8 x float> %f)
ret <8 x i16> %x ret <8 x i16> %x
} }
define <16 x i16> @test_unsigned_v16f32_v16i16(<16 x float> %f) { define <16 x i16> @test_unsigned_v16f32_v16i16(<16 x float> %f) {
; CHECK-LABEL: test_unsigned_v16f32_v16i16: ; CHECK-LABEL: test_unsigned_v16f32_v16i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v4.2d, #0x00ffff0000ffff
; CHECK-NEXT: fcvtzu v1.4s, v1.4s ; CHECK-NEXT: fcvtzu v1.4s, v1.4s
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: fcvtzu v3.4s, v3.4s ; CHECK-NEXT: fcvtzu v3.4s, v3.4s
; CHECK-NEXT: fcvtzu v2.4s, v2.4s ; CHECK-NEXT: fcvtzu v2.4s, v2.4s
; CHECK-NEXT: movi v4.2d, #0x00ffff0000ffff
; CHECK-NEXT: umin v1.4s, v1.4s, v4.4s ; CHECK-NEXT: umin v1.4s, v1.4s, v4.4s
; CHECK-NEXT: umin v0.4s, v0.4s, v4.4s ; CHECK-NEXT: umin v0.4s, v0.4s, v4.4s
; CHECK-NEXT: umin v3.4s, v3.4s, v4.4s ; CHECK-NEXT: umin v3.4s, v3.4s, v4.4s
; CHECK-NEXT: umin v2.4s, v2.4s, v4.4s ; CHECK-NEXT: umin v2.4s, v2.4s, v4.4s
; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h
; CHECK-NEXT: uzp1 v1.8h, v2.8h, v3.8h ; CHECK-NEXT: uzp1 v1.8h, v2.8h, v3.8h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <16 x i16> @llvm.fptoui.sat.v16f32.v16i16(<16 x float> %f) %x = call <16 x i16> @llvm.fptoui.sat.v16f32.v16i16(<16 x float> %f)
ret <16 x i16> %x ret <16 x i16> %x
} }
define <16 x i8> @test_unsigned_v16f16_v16i8(<16 x half> %f) { define <16 x i8> @test_unsigned_v16f16_v16i8(<16 x half> %f) {
; CHECK-CVT-LABEL: test_unsigned_v16f16_v16i8: ; CHECK-CVT-LABEL: test_unsigned_v16f16_v16i8:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: fcvtl2 v2.4s, v1.8h ; CHECK-CVT-NEXT: fcvtl2 v2.4s, v1.8h
; CHECK-CVT-NEXT: fcvtl v1.4s, v1.4h ; CHECK-CVT-NEXT: fcvtl v1.4s, v1.4h
; CHECK-CVT-NEXT: fcvtl2 v5.4s, v0.8h ; CHECK-CVT-NEXT: fcvtl2 v4.4s, v0.8h
; CHECK-CVT-NEXT: mov w8, #255 ; CHECK-CVT-NEXT: mov w8, #255
; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h ; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT: mov s3, v2.s[1] ; CHECK-CVT-NEXT: mov s3, v2.s[1]
; CHECK-CVT-NEXT: mov s4, v2.s[2] ; CHECK-CVT-NEXT: mov s5, v2.s[2]
; CHECK-CVT-NEXT: fcvtzu w9, s2 ; CHECK-CVT-NEXT: fcvtzu w9, s2
; CHECK-CVT-NEXT: mov s2, v2.s[3] ; CHECK-CVT-NEXT: mov s2, v2.s[3]
; CHECK-CVT-NEXT: fcvtzu w12, s1 ; CHECK-CVT-NEXT: mov s6, v1.s[1]
; CHECK-CVT-NEXT: fcvtzu w16, s5 ; CHECK-CVT-NEXT: fcvtzu w10, s1
; CHECK-CVT-NEXT: fcvtzu w14, s4
; CHECK-CVT-NEXT: fcvtzu w2, s0 ; CHECK-CVT-NEXT: fcvtzu w2, s0
; CHECK-CVT-NEXT: fcvtzu w10, s3 ; CHECK-CVT-NEXT: fcvtzu w11, s3
; CHECK-CVT-NEXT: mov s3, v1.s[1] ; CHECK-CVT-NEXT: mov s3, v1.s[2]
; CHECK-CVT-NEXT: fcvtzu w11, s4 ; CHECK-CVT-NEXT: fcvtzu w12, s5
; CHECK-CVT-NEXT: mov s4, v1.s[2]
; CHECK-CVT-NEXT: mov s1, v1.s[3] ; CHECK-CVT-NEXT: mov s1, v1.s[3]
; CHECK-CVT-NEXT: fcvtzu w13, s2 ; CHECK-CVT-NEXT: fcvtzu w13, s2
; CHECK-CVT-NEXT: cmp w10, #255 ; CHECK-CVT-NEXT: mov s5, v4.s[1]
; CHECK-CVT-NEXT: mov s2, v5.s[1]
; CHECK-CVT-NEXT: fcvtzu w14, s3
; CHECK-CVT-NEXT: csel w10, w10, w8, lo
; CHECK-CVT-NEXT: cmp w9, #255
; CHECK-CVT-NEXT: fcvtzu w15, s4
; CHECK-CVT-NEXT: csel w9, w9, w8, lo
; CHECK-CVT-NEXT: cmp w11, #255 ; CHECK-CVT-NEXT: cmp w11, #255
; CHECK-CVT-NEXT: fcvtzu w15, s6
; CHECK-CVT-NEXT: csel w11, w11, w8, lo ; CHECK-CVT-NEXT: csel w11, w11, w8, lo
; CHECK-CVT-NEXT: cmp w9, #255
; CHECK-CVT-NEXT: csel w9, w9, w8, lo
; CHECK-CVT-NEXT: cmp w12, #255
; CHECK-CVT-NEXT: fcvtzu w16, s3
; CHECK-CVT-NEXT: csel w12, w12, w8, lo
; CHECK-CVT-NEXT: cmp w13, #255 ; CHECK-CVT-NEXT: cmp w13, #255
; CHECK-CVT-NEXT: mov s3, v5.s[2] ; CHECK-CVT-NEXT: mov s2, v4.s[2]
; CHECK-CVT-NEXT: fcvtzu w17, s1 ; CHECK-CVT-NEXT: fcvtzu w17, s1
; CHECK-CVT-NEXT: csel w13, w13, w8, lo ; CHECK-CVT-NEXT: csel w13, w13, w8, lo
; CHECK-CVT-NEXT: cmp w14, #255
; CHECK-CVT-NEXT: mov s4, v5.s[3]
; CHECK-CVT-NEXT: fcvtzu w18, s2
; CHECK-CVT-NEXT: csel w14, w14, w8, lo
; CHECK-CVT-NEXT: cmp w12, #255
; CHECK-CVT-NEXT: mov s1, v0.s[1]
; CHECK-CVT-NEXT: csel w12, w12, w8, lo
; CHECK-CVT-NEXT: cmp w15, #255 ; CHECK-CVT-NEXT: cmp w15, #255
; CHECK-CVT-NEXT: fcvtzu w0, s3 ; CHECK-CVT-NEXT: mov s4, v4.s[3]
; CHECK-CVT-NEXT: fcvtzu w18, s5
; CHECK-CVT-NEXT: csel w15, w15, w8, lo ; CHECK-CVT-NEXT: csel w15, w15, w8, lo
; CHECK-CVT-NEXT: cmp w10, #255
; CHECK-CVT-NEXT: mov s1, v0.s[1]
; CHECK-CVT-NEXT: csel w10, w10, w8, lo
; CHECK-CVT-NEXT: cmp w16, #255
; CHECK-CVT-NEXT: csel w16, w16, w8, lo
; CHECK-CVT-NEXT: cmp w17, #255 ; CHECK-CVT-NEXT: cmp w17, #255
; CHECK-CVT-NEXT: fcvtzu w0, s2
; CHECK-CVT-NEXT: csel w17, w17, w8, lo ; CHECK-CVT-NEXT: csel w17, w17, w8, lo
; CHECK-CVT-NEXT: cmp w18, #255 ; CHECK-CVT-NEXT: cmp w18, #255
; CHECK-CVT-NEXT: fcvtzu w1, s4
; CHECK-CVT-NEXT: csel w18, w18, w8, lo
; CHECK-CVT-NEXT: cmp w14, #255
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: fmov s2, w9
; CHECK-CVT-NEXT: csel w9, w18, w8, lo ; CHECK-CVT-NEXT: csel w9, w14, w8, lo
; CHECK-CVT-NEXT: fcvtzu w18, s4 ; CHECK-CVT-NEXT: fcvtzu w14, s1
; CHECK-CVT-NEXT: cmp w16, #255
; CHECK-CVT-NEXT: fcvtzu w1, s1
; CHECK-CVT-NEXT: csel w16, w16, w8, lo
; CHECK-CVT-NEXT: cmp w0, #255 ; CHECK-CVT-NEXT: cmp w0, #255
; CHECK-CVT-NEXT: mov s1, v0.s[2]
; CHECK-CVT-NEXT: csel w0, w0, w8, lo ; CHECK-CVT-NEXT: csel w0, w0, w8, lo
; CHECK-CVT-NEXT: cmp w18, #255
; CHECK-CVT-NEXT: mov v2.s[1], w10
; CHECK-CVT-NEXT: csel w10, w18, w8, lo
; CHECK-CVT-NEXT: cmp w1, #255 ; CHECK-CVT-NEXT: cmp w1, #255
; CHECK-CVT-NEXT: fmov s3, w12 ; CHECK-CVT-NEXT: mov s1, v0.s[2]
; CHECK-CVT-NEXT: csel w18, w1, w8, lo ; CHECK-CVT-NEXT: csel w1, w1, w8, lo
; CHECK-CVT-NEXT: cmp w2, #255 ; CHECK-CVT-NEXT: cmp w14, #255
; CHECK-CVT-NEXT: csel w1, w2, w8, lo
; CHECK-CVT-NEXT: fmov s4, w16
; CHECK-CVT-NEXT: mov v2.s[2], w11
; CHECK-CVT-NEXT: fcvtzu w11, s1
; CHECK-CVT-NEXT: mov s0, v0.s[3] ; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: fmov s1, w1 ; CHECK-CVT-NEXT: csel w14, w14, w8, lo
; CHECK-CVT-NEXT: mov v3.s[1], w14 ; CHECK-CVT-NEXT: cmp w2, #255
; CHECK-CVT-NEXT: cmp w11, #255 ; CHECK-CVT-NEXT: mov v2.s[1], w11
; CHECK-CVT-NEXT: mov v4.s[1], w9 ; CHECK-CVT-NEXT: csel w11, w2, w8, lo
; CHECK-CVT-NEXT: csel w9, w11, w8, lo ; CHECK-CVT-NEXT: fmov s3, w10
; CHECK-CVT-NEXT: fcvtzu w10, s1
; CHECK-CVT-NEXT: fmov s1, w9
; CHECK-CVT-NEXT: fcvtzu w9, s0
; CHECK-CVT-NEXT: fmov s4, w11
; CHECK-CVT-NEXT: mov v2.s[2], w12
; CHECK-CVT-NEXT: cmp w10, #255
; CHECK-CVT-NEXT: mov v3.s[1], w15
; CHECK-CVT-NEXT: csel w10, w10, w8, lo
; CHECK-CVT-NEXT: mov v1.s[1], w18 ; CHECK-CVT-NEXT: mov v1.s[1], w18
; CHECK-CVT-NEXT: fcvtzu w11, s0 ; CHECK-CVT-NEXT: mov v4.s[1], w14
; CHECK-CVT-NEXT: mov v3.s[2], w15 ; CHECK-CVT-NEXT: cmp w9, #255
; CHECK-CVT-NEXT: mov v4.s[2], w0 ; CHECK-CVT-NEXT: csel w8, w9, w8, lo
; CHECK-CVT-NEXT: mov v1.s[2], w9 ; CHECK-CVT-NEXT: mov v3.s[2], w16
; CHECK-CVT-NEXT: cmp w11, #255 ; CHECK-CVT-NEXT: mov v1.s[2], w0
; CHECK-CVT-NEXT: csel w8, w11, w8, lo ; CHECK-CVT-NEXT: mov v4.s[2], w10
; CHECK-CVT-NEXT: mov v2.s[3], w13 ; CHECK-CVT-NEXT: mov v2.s[3], w13
; CHECK-CVT-NEXT: mov v3.s[3], w17 ; CHECK-CVT-NEXT: mov v3.s[3], w17
; CHECK-CVT-NEXT: mov v4.s[3], w10 ; CHECK-CVT-NEXT: mov v1.s[3], w1
; CHECK-CVT-NEXT: mov v1.s[3], w8 ; CHECK-CVT-NEXT: mov v4.s[3], w8
; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v2.8h ; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v2.8h
; CHECK-CVT-NEXT: uzp1 v1.8h, v1.8h, v4.8h ; CHECK-CVT-NEXT: uzp1 v1.8h, v4.8h, v1.8h
; CHECK-CVT-NEXT: uzp1 v0.16b, v1.16b, v0.16b ; CHECK-CVT-NEXT: uzp1 v0.16b, v1.16b, v0.16b
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_unsigned_v16f16_v16i8: ; CHECK-FP16-LABEL: test_unsigned_v16f16_v16i8:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: movi v2.2d, #0xff00ff00ff00ff
; CHECK-FP16-NEXT: fcvtzu v1.8h, v1.8h ; CHECK-FP16-NEXT: fcvtzu v1.8h, v1.8h
; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h ; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
; CHECK-FP16-NEXT: movi v2.2d, #0xff00ff00ff00ff
; CHECK-FP16-NEXT: umin v1.8h, v1.8h, v2.8h ; CHECK-FP16-NEXT: umin v1.8h, v1.8h, v2.8h
; CHECK-FP16-NEXT: umin v0.8h, v0.8h, v2.8h ; CHECK-FP16-NEXT: umin v0.8h, v0.8h, v2.8h
; CHECK-FP16-NEXT: uzp1 v0.16b, v0.16b, v1.16b ; CHECK-FP16-NEXT: uzp1 v0.16b, v0.16b, v1.16b
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <16 x i8> @llvm.fptoui.sat.v16f16.v16i8(<16 x half> %f) %x = call <16 x i8> @llvm.fptoui.sat.v16f16.v16i8(<16 x half> %f)
ret <16 x i8> %x ret <16 x i8> %x
} }
define <16 x i16> @test_unsigned_v16f16_v16i16(<16 x half> %f) { define <16 x i16> @test_unsigned_v16f16_v16i16(<16 x half> %f) {
; CHECK-CVT-LABEL: test_unsigned_v16f16_v16i16: ; CHECK-CVT-LABEL: test_unsigned_v16f16_v16i16:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: fcvtl2 v2.4s, v0.8h ; CHECK-CVT-NEXT: fcvtl2 v2.4s, v0.8h
; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h ; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT: fcvtl2 v5.4s, v1.8h ; CHECK-CVT-NEXT: fcvtl2 v4.4s, v1.8h
; CHECK-CVT-NEXT: mov w8, #65535 ; CHECK-CVT-NEXT: mov w8, #65535
; CHECK-CVT-NEXT: fcvtl v1.4s, v1.4h ; CHECK-CVT-NEXT: fcvtl v1.4s, v1.4h
; CHECK-CVT-NEXT: mov s3, v2.s[1] ; CHECK-CVT-NEXT: mov s3, v2.s[1]
; CHECK-CVT-NEXT: mov s4, v2.s[2] ; CHECK-CVT-NEXT: mov s5, v2.s[2]
; CHECK-CVT-NEXT: fcvtzu w9, s2 ; CHECK-CVT-NEXT: fcvtzu w9, s2
; CHECK-CVT-NEXT: mov s2, v2.s[3] ; CHECK-CVT-NEXT: mov s2, v2.s[3]
; CHECK-CVT-NEXT: fcvtzu w12, s0 ; CHECK-CVT-NEXT: mov s6, v0.s[1]
; CHECK-CVT-NEXT: fcvtzu w16, s5 ; CHECK-CVT-NEXT: fcvtzu w10, s0
; CHECK-CVT-NEXT: fcvtzu w14, s4
; CHECK-CVT-NEXT: fcvtzu w2, s1 ; CHECK-CVT-NEXT: fcvtzu w2, s1
; CHECK-CVT-NEXT: fcvtzu w10, s3 ; CHECK-CVT-NEXT: fcvtzu w11, s3
; CHECK-CVT-NEXT: mov s3, v0.s[1] ; CHECK-CVT-NEXT: mov s3, v0.s[2]
; CHECK-CVT-NEXT: fcvtzu w11, s4 ; CHECK-CVT-NEXT: fcvtzu w12, s5
; CHECK-CVT-NEXT: mov s4, v0.s[2]
; CHECK-CVT-NEXT: mov s0, v0.s[3] ; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: fcvtzu w13, s2 ; CHECK-CVT-NEXT: fcvtzu w13, s2
; CHECK-CVT-NEXT: cmp w10, w8 ; CHECK-CVT-NEXT: mov s5, v4.s[1]
; CHECK-CVT-NEXT: mov s2, v5.s[1]
; CHECK-CVT-NEXT: fcvtzu w14, s3
; CHECK-CVT-NEXT: csel w10, w10, w8, lo
; CHECK-CVT-NEXT: cmp w9, w8
; CHECK-CVT-NEXT: fcvtzu w15, s4
; CHECK-CVT-NEXT: csel w9, w9, w8, lo
; CHECK-CVT-NEXT: cmp w11, w8 ; CHECK-CVT-NEXT: cmp w11, w8
; CHECK-CVT-NEXT: fcvtzu w15, s6
; CHECK-CVT-NEXT: csel w11, w11, w8, lo ; CHECK-CVT-NEXT: csel w11, w11, w8, lo
; CHECK-CVT-NEXT: cmp w9, w8
; CHECK-CVT-NEXT: csel w9, w9, w8, lo
; CHECK-CVT-NEXT: cmp w12, w8
; CHECK-CVT-NEXT: fcvtzu w16, s3
; CHECK-CVT-NEXT: csel w12, w12, w8, lo
; CHECK-CVT-NEXT: cmp w13, w8 ; CHECK-CVT-NEXT: cmp w13, w8
; CHECK-CVT-NEXT: mov s3, v5.s[2] ; CHECK-CVT-NEXT: mov s2, v4.s[2]
; CHECK-CVT-NEXT: fcvtzu w17, s0 ; CHECK-CVT-NEXT: fcvtzu w17, s0
; CHECK-CVT-NEXT: csel w13, w13, w8, lo ; CHECK-CVT-NEXT: csel w13, w13, w8, lo
; CHECK-CVT-NEXT: cmp w14, w8
; CHECK-CVT-NEXT: mov s4, v5.s[3]
; CHECK-CVT-NEXT: fcvtzu w18, s2
; CHECK-CVT-NEXT: csel w14, w14, w8, lo
; CHECK-CVT-NEXT: cmp w12, w8
; CHECK-CVT-NEXT: mov s0, v1.s[1]
; CHECK-CVT-NEXT: csel w12, w12, w8, lo
; CHECK-CVT-NEXT: cmp w15, w8 ; CHECK-CVT-NEXT: cmp w15, w8
; CHECK-CVT-NEXT: fcvtzu w0, s3 ; CHECK-CVT-NEXT: mov s4, v4.s[3]
; CHECK-CVT-NEXT: fcvtzu w18, s5
; CHECK-CVT-NEXT: csel w15, w15, w8, lo ; CHECK-CVT-NEXT: csel w15, w15, w8, lo
; CHECK-CVT-NEXT: cmp w10, w8
; CHECK-CVT-NEXT: mov s0, v1.s[1]
; CHECK-CVT-NEXT: csel w10, w10, w8, lo
; CHECK-CVT-NEXT: cmp w16, w8
; CHECK-CVT-NEXT: csel w16, w16, w8, lo
; CHECK-CVT-NEXT: cmp w17, w8 ; CHECK-CVT-NEXT: cmp w17, w8
; CHECK-CVT-NEXT: fcvtzu w0, s2
; CHECK-CVT-NEXT: csel w17, w17, w8, lo ; CHECK-CVT-NEXT: csel w17, w17, w8, lo
; CHECK-CVT-NEXT: cmp w18, w8 ; CHECK-CVT-NEXT: cmp w18, w8
; CHECK-CVT-NEXT: fcvtzu w1, s4
; CHECK-CVT-NEXT: csel w18, w18, w8, lo
; CHECK-CVT-NEXT: cmp w14, w8
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: fmov s2, w9
; CHECK-CVT-NEXT: csel w9, w18, w8, lo ; CHECK-CVT-NEXT: csel w9, w14, w8, lo
; CHECK-CVT-NEXT: fcvtzu w18, s4 ; CHECK-CVT-NEXT: fcvtzu w14, s0
; CHECK-CVT-NEXT: cmp w16, w8
; CHECK-CVT-NEXT: fcvtzu w1, s0
; CHECK-CVT-NEXT: csel w16, w16, w8, lo
; CHECK-CVT-NEXT: cmp w0, w8 ; CHECK-CVT-NEXT: cmp w0, w8
; CHECK-CVT-NEXT: mov s0, v1.s[2]
; CHECK-CVT-NEXT: csel w0, w0, w8, lo ; CHECK-CVT-NEXT: csel w0, w0, w8, lo
; CHECK-CVT-NEXT: cmp w18, w8
; CHECK-CVT-NEXT: mov v2.s[1], w10
; CHECK-CVT-NEXT: csel w10, w18, w8, lo
; CHECK-CVT-NEXT: cmp w1, w8 ; CHECK-CVT-NEXT: cmp w1, w8
; CHECK-CVT-NEXT: fmov s3, w12 ; CHECK-CVT-NEXT: mov s0, v1.s[2]
; CHECK-CVT-NEXT: csel w18, w1, w8, lo ; CHECK-CVT-NEXT: csel w1, w1, w8, lo
; CHECK-CVT-NEXT: cmp w14, w8
; CHECK-CVT-NEXT: mov s1, v1.s[3]
; CHECK-CVT-NEXT: csel w14, w14, w8, lo
; CHECK-CVT-NEXT: cmp w2, w8 ; CHECK-CVT-NEXT: cmp w2, w8
; CHECK-CVT-NEXT: csel w1, w2, w8, lo ; CHECK-CVT-NEXT: mov v2.s[1], w11
; CHECK-CVT-NEXT: fmov s4, w16 ; CHECK-CVT-NEXT: csel w11, w2, w8, lo
; CHECK-CVT-NEXT: mov v2.s[2], w11 ; CHECK-CVT-NEXT: fmov s3, w10
; CHECK-CVT-NEXT: fcvtzu w11, s0 ; CHECK-CVT-NEXT: fcvtzu w10, s0
; CHECK-CVT-NEXT: mov s0, v1.s[3] ; CHECK-CVT-NEXT: fmov s4, w9
; CHECK-CVT-NEXT: fmov s5, w1 ; CHECK-CVT-NEXT: fcvtzu w9, s1
; CHECK-CVT-NEXT: mov v3.s[1], w14 ; CHECK-CVT-NEXT: fmov s5, w11
; CHECK-CVT-NEXT: cmp w11, w8 ; CHECK-CVT-NEXT: mov v2.s[2], w12
; CHECK-CVT-NEXT: mov v4.s[1], w9 ; CHECK-CVT-NEXT: cmp w10, w8
; CHECK-CVT-NEXT: csel w9, w11, w8, lo ; CHECK-CVT-NEXT: mov v3.s[1], w15
; CHECK-CVT-NEXT: mov v5.s[1], w18 ; CHECK-CVT-NEXT: csel w10, w10, w8, lo
; CHECK-CVT-NEXT: fcvtzu w11, s0 ; CHECK-CVT-NEXT: mov v4.s[1], w18
; CHECK-CVT-NEXT: mov v3.s[2], w15 ; CHECK-CVT-NEXT: mov v5.s[1], w14
; CHECK-CVT-NEXT: cmp w9, w8
; CHECK-CVT-NEXT: csel w8, w9, w8, lo
; CHECK-CVT-NEXT: mov v3.s[2], w16
; CHECK-CVT-NEXT: mov v4.s[2], w0 ; CHECK-CVT-NEXT: mov v4.s[2], w0
; CHECK-CVT-NEXT: mov v5.s[2], w9 ; CHECK-CVT-NEXT: mov v5.s[2], w10
; CHECK-CVT-NEXT: cmp w11, w8
; CHECK-CVT-NEXT: csel w8, w11, w8, lo
; CHECK-CVT-NEXT: mov v2.s[3], w13 ; CHECK-CVT-NEXT: mov v2.s[3], w13
; CHECK-CVT-NEXT: mov v3.s[3], w17 ; CHECK-CVT-NEXT: mov v3.s[3], w17
; CHECK-CVT-NEXT: mov v4.s[3], w10 ; CHECK-CVT-NEXT: mov v4.s[3], w1
; CHECK-CVT-NEXT: mov v5.s[3], w8 ; CHECK-CVT-NEXT: mov v5.s[3], w8
; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v2.8h ; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v2.8h
; CHECK-CVT-NEXT: uzp1 v1.8h, v5.8h, v4.8h ; CHECK-CVT-NEXT: uzp1 v1.8h, v5.8h, v4.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_unsigned_v16f16_v16i16: ; CHECK-FP16-LABEL: test_unsigned_v16f16_v16i16:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h ; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
; CHECK-FP16-NEXT: fcvtzu v1.8h, v1.8h ; CHECK-FP16-NEXT: fcvtzu v1.8h, v1.8h
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <16 x i16> @llvm.fptoui.sat.v16f16.v16i16(<16 x half> %f) %x = call <16 x i16> @llvm.fptoui.sat.v16f16.v16i16(<16 x half> %f)
ret <16 x i16> %x ret <16 x i16> %x
} }
define <8 x i8> @test_unsigned_v8f64_v8i8(<8 x double> %f) { define <8 x i8> @test_unsigned_v8f64_v8i8(<8 x double> %f) {
; CHECK-LABEL: test_unsigned_v8f64_v8i8: ; CHECK-LABEL: test_unsigned_v8f64_v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d5, v0.d[1] ; CHECK-NEXT: mov d5, v0.d[1]
; CHECK-NEXT: mov d6, v1.d[1]
; CHECK-NEXT: fcvtzu w10, d0 ; CHECK-NEXT: fcvtzu w10, d0
; CHECK-NEXT: mov d0, v1.d[1]
; CHECK-NEXT: mov w8, #255
; CHECK-NEXT: fcvtzu w12, d1
; CHECK-NEXT: mov d4, v2.d[1] ; CHECK-NEXT: mov d4, v2.d[1]
; CHECK-NEXT: fcvtzu w13, d3 ; CHECK-NEXT: mov w8, #255
; CHECK-NEXT: fcvtzu w11, d1
; CHECK-NEXT: mov d1, v3.d[1]
; CHECK-NEXT: fcvtzu w12, d2
; CHECK-NEXT: fcvtzu w9, d5 ; CHECK-NEXT: fcvtzu w9, d5
; CHECK-NEXT: fcvtzu w11, d0 ; CHECK-NEXT: fcvtzu w13, d6
; CHECK-NEXT: fcvtzu w14, d4
; CHECK-NEXT: cmp w9, #255 ; CHECK-NEXT: cmp w9, #255
; CHECK-NEXT: csel w9, w9, w8, lo ; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: cmp w10, #255 ; CHECK-NEXT: cmp w10, #255
; CHECK-NEXT: csel w10, w10, w8, lo ; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: cmp w13, #255
; CHECK-NEXT: csel w13, w13, w8, lo
; CHECK-NEXT: cmp w11, #255 ; CHECK-NEXT: cmp w11, #255
; CHECK-NEXT: csel w11, w11, w8, lo
; CHECK-NEXT: cmp w14, #255
; CHECK-NEXT: fmov s0, w10 ; CHECK-NEXT: fmov s0, w10
; CHECK-NEXT: csel w10, w11, w8, lo ; CHECK-NEXT: csel w10, w14, w8, lo
; CHECK-NEXT: cmp w12, #255 ; CHECK-NEXT: cmp w12, #255
; CHECK-NEXT: csel w11, w12, w8, lo ; CHECK-NEXT: fmov s2, w11
; CHECK-NEXT: fcvtzu w11, d1
; CHECK-NEXT: csel w12, w12, w8, lo
; CHECK-NEXT: mov v0.s[1], w9 ; CHECK-NEXT: mov v0.s[1], w9
; CHECK-NEXT: fcvtzu w9, d4 ; CHECK-NEXT: fcvtzu w9, d3
; CHECK-NEXT: fmov s1, w11 ; CHECK-NEXT: mov v2.s[1], w13
; CHECK-NEXT: fcvtzu w11, d2
; CHECK-NEXT: cmp w9, #255
; CHECK-NEXT: mov d2, v3.d[1]
; CHECK-NEXT: mov w12, v0.s[1]
; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: mov v1.s[1], w10
; CHECK-NEXT: cmp w11, #255 ; CHECK-NEXT: cmp w11, #255
; CHECK-NEXT: csel w10, w11, w8, lo ; CHECK-NEXT: fmov s1, w12
; CHECK-NEXT: mov w12, v0.s[1]
; CHECK-NEXT: csel w11, w11, w8, lo
; CHECK-NEXT: cmp w9, #255
; CHECK-NEXT: csel w8, w9, w8, lo
; CHECK-NEXT: fmov w9, s2
; CHECK-NEXT: mov v0.b[1], w12 ; CHECK-NEXT: mov v0.b[1], w12
; CHECK-NEXT: fmov w11, s1 ; CHECK-NEXT: mov v1.s[1], w10
; CHECK-NEXT: fmov s4, w10 ; CHECK-NEXT: mov w12, v2.s[1]
; CHECK-NEXT: fcvtzu w10, d2 ; CHECK-NEXT: mov v0.b[2], w9
; CHECK-NEXT: mov w12, v1.s[1] ; CHECK-NEXT: fmov s2, w8
; CHECK-NEXT: mov v0.b[2], w11
; CHECK-NEXT: mov v4.s[1], w9
; CHECK-NEXT: cmp w10, #255
; CHECK-NEXT: csel w9, w10, w8, lo
; CHECK-NEXT: cmp w13, #255
; CHECK-NEXT: csel w8, w13, w8, lo
; CHECK-NEXT: mov v0.b[3], w12
; CHECK-NEXT: fmov w10, s4
; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: mov w8, v4.s[1]
; CHECK-NEXT: mov v0.b[4], w10
; CHECK-NEXT: mov v1.s[1], w9
; CHECK-NEXT: mov v0.b[5], w8
; CHECK-NEXT: fmov w8, s1 ; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov w9, v1.s[1] ; CHECK-NEXT: mov w9, v1.s[1]
; CHECK-NEXT: mov v0.b[3], w12
; CHECK-NEXT: mov v2.s[1], w11
; CHECK-NEXT: mov v0.b[4], w8
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: mov v0.b[5], w9
; CHECK-NEXT: mov w9, v2.s[1]
; CHECK-NEXT: mov v0.b[6], w8 ; CHECK-NEXT: mov v0.b[6], w8
; CHECK-NEXT: mov v0.b[7], w9 ; CHECK-NEXT: mov v0.b[7], w9
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <8 x i8> @llvm.fptoui.sat.v8f64.v8i8(<8 x double> %f) %x = call <8 x i8> @llvm.fptoui.sat.v8f64.v8i8(<8 x double> %f)
ret <8 x i8> %x ret <8 x i8> %x
} }
define <16 x i8> @test_unsigned_v16f64_v16i8(<16 x double> %f) { define <16 x i8> @test_unsigned_v16f64_v16i8(<16 x double> %f) {
; CHECK-LABEL: test_unsigned_v16f64_v16i8: ; CHECK-LABEL: test_unsigned_v16f64_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d16, v0.d[1] ; CHECK-NEXT: mov d16, v0.d[1]
; CHECK-NEXT: fcvtzu w10, d0 ; CHECK-NEXT: mov d17, v1.d[1]
; CHECK-NEXT: mov d0, v1.d[1] ; CHECK-NEXT: fcvtzu w9, d0
; CHECK-NEXT: mov d0, v2.d[1]
; CHECK-NEXT: mov w8, #255 ; CHECK-NEXT: mov w8, #255
; CHECK-NEXT: fcvtzu w12, d1 ; CHECK-NEXT: fcvtzu w11, d1
; CHECK-NEXT: mov d1, v2.d[1] ; CHECK-NEXT: mov d1, v3.d[1]
; CHECK-NEXT: fcvtzu w9, d16 ; CHECK-NEXT: fcvtzu w12, d2
; CHECK-NEXT: fcvtzu w11, d0 ; CHECK-NEXT: fcvtzu w10, d16
; CHECK-NEXT: cmp w9, #255 ; CHECK-NEXT: fcvtzu w13, d17
; CHECK-NEXT: csel w9, w9, w8, lo ; CHECK-NEXT: fcvtzu w14, d0
; CHECK-NEXT: fcvtzu w15, d3
; CHECK-NEXT: mov d2, v4.d[1]
; CHECK-NEXT: cmp w10, #255 ; CHECK-NEXT: cmp w10, #255
; CHECK-NEXT: csel w10, w10, w8, lo ; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: cmp w9, #255
; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: cmp w13, #255
; CHECK-NEXT: csel w13, w13, w8, lo
; CHECK-NEXT: cmp w11, #255 ; CHECK-NEXT: cmp w11, #255
; CHECK-NEXT: fmov s0, w10 ; CHECK-NEXT: csel w11, w11, w8, lo
; CHECK-NEXT: csel w10, w11, w8, lo ; CHECK-NEXT: cmp w14, #255
; CHECK-NEXT: cmp w12, #255 ; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: csel w11, w12, w8, lo
; CHECK-NEXT: mov v0.s[1], w9
; CHECK-NEXT: fcvtzu w9, d1 ; CHECK-NEXT: fcvtzu w9, d1
; CHECK-NEXT: csel w14, w14, w8, lo
; CHECK-NEXT: cmp w12, #255
; CHECK-NEXT: fmov s1, w11 ; CHECK-NEXT: fmov s1, w11
; CHECK-NEXT: fcvtzu w11, d2 ; CHECK-NEXT: csel w11, w12, w8, lo
; CHECK-NEXT: mov v0.s[1], w10
; CHECK-NEXT: cmp w9, #255 ; CHECK-NEXT: cmp w9, #255
; CHECK-NEXT: mov d2, v3.d[1]
; CHECK-NEXT: mov w12, v0.s[1]
; CHECK-NEXT: csel w9, w9, w8, lo ; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: mov v1.s[1], w10 ; CHECK-NEXT: cmp w15, #255
; CHECK-NEXT: cmp w11, #255 ; CHECK-NEXT: mov w12, v0.s[1]
; CHECK-NEXT: csel w11, w11, w8, lo ; CHECK-NEXT: mov v1.s[1], w13
; CHECK-NEXT: fcvtzu w10, d2 ; CHECK-NEXT: fcvtzu w13, d2
; CHECK-NEXT: mov d2, v4.d[1] ; CHECK-NEXT: fmov s2, w11
; CHECK-NEXT: mov v0.b[1], w12 ; CHECK-NEXT: mov v0.b[1], w12
; CHECK-NEXT: fmov w13, s1
; CHECK-NEXT: mov w12, v1.s[1]
; CHECK-NEXT: fmov s1, w11
; CHECK-NEXT: fcvtzu w11, d3
; CHECK-NEXT: cmp w10, #255
; CHECK-NEXT: mov v0.b[2], w13
; CHECK-NEXT: mov v1.s[1], w9
; CHECK-NEXT: csel w9, w10, w8, lo
; CHECK-NEXT: cmp w11, #255
; CHECK-NEXT: fcvtzu w10, d2
; CHECK-NEXT: csel w11, w11, w8, lo
; CHECK-NEXT: mov d2, v5.d[1]
; CHECK-NEXT: mov v0.b[3], w12
; CHECK-NEXT: fmov w12, s1 ; CHECK-NEXT: fmov w12, s1
; CHECK-NEXT: csel w15, w15, w8, lo
; CHECK-NEXT: fcvtzu w10, d4
; CHECK-NEXT: mov w11, v1.s[1]
; CHECK-NEXT: mov v2.s[1], w14
; CHECK-NEXT: mov v0.b[2], w12
; CHECK-NEXT: cmp w13, #255
; CHECK-NEXT: fmov s1, w15
; CHECK-NEXT: mov w12, v2.s[1]
; CHECK-NEXT: fmov w14, s2
; CHECK-NEXT: mov v0.b[3], w11
; CHECK-NEXT: mov d2, v5.d[1]
; CHECK-NEXT: csel w11, w13, w8, lo
; CHECK-NEXT: cmp w10, #255 ; CHECK-NEXT: cmp w10, #255
; CHECK-NEXT: mov w13, v1.s[1]
; CHECK-NEXT: fmov s1, w11
; CHECK-NEXT: fcvtzu w11, d4
; CHECK-NEXT: mov v0.b[4], w12
; CHECK-NEXT: mov v1.s[1], w9 ; CHECK-NEXT: mov v1.s[1], w9
; CHECK-NEXT: csel w9, w10, w8, lo ; CHECK-NEXT: csel w9, w10, w8, lo
; CHECK-NEXT: cmp w11, #255 ; CHECK-NEXT: mov v0.b[4], w14
; CHECK-NEXT: csel w10, w11, w8, lo ; CHECK-NEXT: fmov w10, s1
; CHECK-NEXT: mov v0.b[5], w13 ; CHECK-NEXT: mov w13, v1.s[1]
; CHECK-NEXT: fcvtzu w13, d2 ; CHECK-NEXT: mov v0.b[5], w12
; CHECK-NEXT: fmov w11, s1 ; CHECK-NEXT: fcvtzu w12, d5
; CHECK-NEXT: mov w12, v1.s[1] ; CHECK-NEXT: fmov s3, w9
; CHECK-NEXT: fmov s1, w10 ; CHECK-NEXT: fcvtzu w9, d2
; CHECK-NEXT: fcvtzu w10, d5
; CHECK-NEXT: cmp w13, #255
; CHECK-NEXT: mov v0.b[6], w11
; CHECK-NEXT: mov d2, v6.d[1] ; CHECK-NEXT: mov d2, v6.d[1]
; CHECK-NEXT: mov v1.s[1], w9 ; CHECK-NEXT: mov v0.b[6], w10
; CHECK-NEXT: csel w9, w13, w8, lo ; CHECK-NEXT: mov d1, v7.d[1]
; CHECK-NEXT: cmp w10, #255 ; CHECK-NEXT: fcvtzu w15, d7
; CHECK-NEXT: fcvtzu w13, d6 ; CHECK-NEXT: cmp w9, #255
; CHECK-NEXT: csel w10, w10, w8, lo ; CHECK-NEXT: mov v3.s[1], w11
; CHECK-NEXT: mov v0.b[7], w12 ; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: fcvtzu w12, d2 ; CHECK-NEXT: cmp w12, #255
; CHECK-NEXT: fmov w11, s1 ; CHECK-NEXT: fcvtzu w11, d2
; CHECK-NEXT: csel w10, w12, w8, lo
; CHECK-NEXT: fcvtzu w12, d6
; CHECK-NEXT: mov v0.b[7], w13
; CHECK-NEXT: fmov w13, s3
; CHECK-NEXT: mov w14, v3.s[1]
; CHECK-NEXT: cmp w11, #255
; CHECK-NEXT: fmov s2, w10 ; CHECK-NEXT: fmov s2, w10
; CHECK-NEXT: mov w10, v1.s[1] ; CHECK-NEXT: csel w10, w11, w8, lo
; CHECK-NEXT: cmp w12, #255 ; CHECK-NEXT: cmp w12, #255
; CHECK-NEXT: mov d1, v7.d[1] ; CHECK-NEXT: csel w11, w12, w8, lo
; CHECK-NEXT: mov v0.b[8], w11 ; CHECK-NEXT: fcvtzu w12, d1
; CHECK-NEXT: mov v2.s[1], w9 ; CHECK-NEXT: mov v2.s[1], w9
; CHECK-NEXT: mov v0.b[8], w13
; CHECK-NEXT: cmp w12, #255
; CHECK-NEXT: fmov s1, w11
; CHECK-NEXT: csel w9, w12, w8, lo ; CHECK-NEXT: csel w9, w12, w8, lo
; CHECK-NEXT: cmp w13, #255 ; CHECK-NEXT: cmp w15, #255
; CHECK-NEXT: csel w11, w13, w8, lo ; CHECK-NEXT: csel w8, w15, w8, lo
; CHECK-NEXT: fcvtzu w13, d7 ; CHECK-NEXT: fmov w11, s2
; CHECK-NEXT: mov v0.b[9], w10 ; CHECK-NEXT: mov v0.b[9], w14
; CHECK-NEXT: fmov w10, s2 ; CHECK-NEXT: mov v1.s[1], w10
; CHECK-NEXT: fmov s3, w11
; CHECK-NEXT: fcvtzu w11, d1
; CHECK-NEXT: mov w12, v2.s[1] ; CHECK-NEXT: mov w12, v2.s[1]
; CHECK-NEXT: mov v0.b[10], w10 ; CHECK-NEXT: mov v0.b[10], w11
; CHECK-NEXT: mov v3.s[1], w9 ; CHECK-NEXT: fmov s2, w8
; CHECK-NEXT: cmp w11, #255
; CHECK-NEXT: csel w9, w11, w8, lo
; CHECK-NEXT: cmp w13, #255
; CHECK-NEXT: csel w8, w13, w8, lo
; CHECK-NEXT: mov v0.b[11], w12
; CHECK-NEXT: fmov w10, s3
; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: mov w8, v3.s[1]
; CHECK-NEXT: mov v0.b[12], w10
; CHECK-NEXT: mov v1.s[1], w9
; CHECK-NEXT: mov v0.b[13], w8
; CHECK-NEXT: fmov w8, s1 ; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov v0.b[11], w12
; CHECK-NEXT: mov v2.s[1], w9
; CHECK-NEXT: mov w9, v1.s[1] ; CHECK-NEXT: mov w9, v1.s[1]
; CHECK-NEXT: mov v0.b[12], w8
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: mov v0.b[13], w9
; CHECK-NEXT: mov w9, v2.s[1]
; CHECK-NEXT: mov v0.b[14], w8 ; CHECK-NEXT: mov v0.b[14], w8
; CHECK-NEXT: mov v0.b[15], w9 ; CHECK-NEXT: mov v0.b[15], w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <16 x i8> @llvm.fptoui.sat.v16f64.v16i8(<16 x double> %f) %x = call <16 x i8> @llvm.fptoui.sat.v16f64.v16i8(<16 x double> %f)
ret <16 x i8> %x ret <16 x i8> %x
} }
define <8 x i16> @test_unsigned_v8f64_v8i16(<8 x double> %f) { define <8 x i16> @test_unsigned_v8f64_v8i16(<8 x double> %f) {
; CHECK-LABEL: test_unsigned_v8f64_v8i16: ; CHECK-LABEL: test_unsigned_v8f64_v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d5, v0.d[1] ; CHECK-NEXT: mov d5, v0.d[1]
; CHECK-NEXT: mov d6, v1.d[1]
; CHECK-NEXT: fcvtzu w10, d0 ; CHECK-NEXT: fcvtzu w10, d0
; CHECK-NEXT: mov d0, v1.d[1]
; CHECK-NEXT: mov w8, #65535 ; CHECK-NEXT: mov w8, #65535
; CHECK-NEXT: fcvtzu w12, d1
; CHECK-NEXT: mov d4, v2.d[1] ; CHECK-NEXT: mov d4, v2.d[1]
; CHECK-NEXT: fcvtzu w13, d3 ; CHECK-NEXT: fcvtzu w11, d1
; CHECK-NEXT: mov d1, v3.d[1]
; CHECK-NEXT: fcvtzu w12, d2
; CHECK-NEXT: fcvtzu w9, d5 ; CHECK-NEXT: fcvtzu w9, d5
; CHECK-NEXT: fcvtzu w11, d0 ; CHECK-NEXT: fcvtzu w13, d6
; CHECK-NEXT: fcvtzu w14, d4
; CHECK-NEXT: cmp w9, w8 ; CHECK-NEXT: cmp w9, w8
; CHECK-NEXT: csel w9, w9, w8, lo ; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: cmp w10, w8 ; CHECK-NEXT: cmp w10, w8
; CHECK-NEXT: csel w10, w10, w8, lo ; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: cmp w13, w8
; CHECK-NEXT: csel w13, w13, w8, lo
; CHECK-NEXT: cmp w11, w8 ; CHECK-NEXT: cmp w11, w8
; CHECK-NEXT: csel w11, w11, w8, lo
; CHECK-NEXT: cmp w14, w8
; CHECK-NEXT: fmov s0, w10 ; CHECK-NEXT: fmov s0, w10
; CHECK-NEXT: csel w10, w11, w8, lo ; CHECK-NEXT: csel w10, w14, w8, lo
; CHECK-NEXT: cmp w12, w8 ; CHECK-NEXT: cmp w12, w8
; CHECK-NEXT: csel w11, w12, w8, lo ; CHECK-NEXT: fmov s2, w11
; CHECK-NEXT: fcvtzu w11, d1
; CHECK-NEXT: csel w12, w12, w8, lo
; CHECK-NEXT: mov v0.s[1], w9 ; CHECK-NEXT: mov v0.s[1], w9
; CHECK-NEXT: fcvtzu w9, d4 ; CHECK-NEXT: fcvtzu w9, d3
; CHECK-NEXT: fmov s1, w11 ; CHECK-NEXT: mov v2.s[1], w13
; CHECK-NEXT: fcvtzu w11, d2
; CHECK-NEXT: cmp w9, w8
; CHECK-NEXT: mov d2, v3.d[1]
; CHECK-NEXT: mov w12, v0.s[1]
; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: mov v1.s[1], w10
; CHECK-NEXT: cmp w11, w8 ; CHECK-NEXT: cmp w11, w8
; CHECK-NEXT: csel w10, w11, w8, lo ; CHECK-NEXT: fmov s1, w12
; CHECK-NEXT: mov w12, v0.s[1]
; CHECK-NEXT: csel w11, w11, w8, lo
; CHECK-NEXT: cmp w9, w8
; CHECK-NEXT: csel w8, w9, w8, lo
; CHECK-NEXT: fmov w9, s2
; CHECK-NEXT: mov v0.h[1], w12 ; CHECK-NEXT: mov v0.h[1], w12
; CHECK-NEXT: fmov w11, s1 ; CHECK-NEXT: mov v1.s[1], w10
; CHECK-NEXT: fmov s4, w10 ; CHECK-NEXT: mov w12, v2.s[1]
; CHECK-NEXT: fcvtzu w10, d2 ; CHECK-NEXT: mov v0.h[2], w9
; CHECK-NEXT: mov w12, v1.s[1] ; CHECK-NEXT: fmov s2, w8
; CHECK-NEXT: mov v0.h[2], w11
; CHECK-NEXT: mov v4.s[1], w9
; CHECK-NEXT: cmp w10, w8
; CHECK-NEXT: csel w9, w10, w8, lo
; CHECK-NEXT: cmp w13, w8
; CHECK-NEXT: csel w8, w13, w8, lo
; CHECK-NEXT: mov v0.h[3], w12
; CHECK-NEXT: fmov w10, s4
; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: mov w8, v4.s[1]
; CHECK-NEXT: mov v0.h[4], w10
; CHECK-NEXT: mov v1.s[1], w9
; CHECK-NEXT: mov v0.h[5], w8
; CHECK-NEXT: fmov w8, s1 ; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov w9, v1.s[1] ; CHECK-NEXT: mov w9, v1.s[1]
; CHECK-NEXT: mov v0.h[3], w12
; CHECK-NEXT: mov v2.s[1], w11
; CHECK-NEXT: mov v0.h[4], w8
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: mov v0.h[5], w9
; CHECK-NEXT: mov w9, v2.s[1]
; CHECK-NEXT: mov v0.h[6], w8 ; CHECK-NEXT: mov v0.h[6], w8
; CHECK-NEXT: mov v0.h[7], w9 ; CHECK-NEXT: mov v0.h[7], w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <8 x i16> @llvm.fptoui.sat.v8f64.v8i16(<8 x double> %f) %x = call <8 x i16> @llvm.fptoui.sat.v8f64.v8i16(<8 x double> %f)
ret <8 x i16> %x ret <8 x i16> %x
} }
define <16 x i16> @test_unsigned_v16f64_v16i16(<16 x double> %f) { define <16 x i16> @test_unsigned_v16f64_v16i16(<16 x double> %f) {
; CHECK-LABEL: test_unsigned_v16f64_v16i16: ; CHECK-LABEL: test_unsigned_v16f64_v16i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d16, v0.d[1] ; CHECK-NEXT: mov d17, v0.d[1]
; CHECK-NEXT: mov d18, v1.d[1]
; CHECK-NEXT: fcvtzu w9, d0 ; CHECK-NEXT: fcvtzu w9, d0
; CHECK-NEXT: mov d0, v1.d[1]
; CHECK-NEXT: mov d17, v2.d[1]
; CHECK-NEXT: fcvtzu w10, d1
; CHECK-NEXT: mov d1, v3.d[1]
; CHECK-NEXT: mov w8, #65535 ; CHECK-NEXT: mov w8, #65535
; CHECK-NEXT: fcvtzu w10, d1
; CHECK-NEXT: mov d16, v2.d[1]
; CHECK-NEXT: mov d0, v3.d[1]
; CHECK-NEXT: mov d1, v4.d[1]
; CHECK-NEXT: fcvtzu w11, d17
; CHECK-NEXT: fcvtzu w13, d18
; CHECK-NEXT: fcvtzu w12, d2 ; CHECK-NEXT: fcvtzu w12, d2
; CHECK-NEXT: fcvtzu w11, d16 ; CHECK-NEXT: mov d2, v5.d[1]
; CHECK-NEXT: mov d2, v4.d[1] ; CHECK-NEXT: fcvtzu w14, d16
; CHECK-NEXT: fcvtzu w13, d0 ; CHECK-NEXT: fcvtzu w15, d3
; CHECK-NEXT: fcvtzu w14, d17
; CHECK-NEXT: fcvtzu w15, d1
; CHECK-NEXT: fcvtzu w16, d3
; CHECK-NEXT: cmp w11, w8 ; CHECK-NEXT: cmp w11, w8
; CHECK-NEXT: mov d1, v5.d[1] ; CHECK-NEXT: fcvtzu w16, d0
; CHECK-NEXT: csel w11, w11, w8, lo ; CHECK-NEXT: csel w11, w11, w8, lo
; CHECK-NEXT: cmp w9, w8 ; CHECK-NEXT: cmp w9, w8
; CHECK-NEXT: csel w9, w9, w8, lo ; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: cmp w13, w8 ; CHECK-NEXT: cmp w13, w8
; CHECK-NEXT: csel w13, w13, w8, lo ; CHECK-NEXT: csel w13, w13, w8, lo
; CHECK-NEXT: cmp w10, w8 ; CHECK-NEXT: cmp w10, w8
; CHECK-NEXT: csel w10, w10, w8, lo ; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: fcvtzu w17, d1
; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: cmp w14, w8 ; CHECK-NEXT: cmp w14, w8
; CHECK-NEXT: csel w14, w14, w8, lo ; CHECK-NEXT: csel w9, w14, w8, lo
; CHECK-NEXT: cmp w12, w8 ; CHECK-NEXT: cmp w12, w8
; CHECK-NEXT: csel w12, w12, w8, lo ; CHECK-NEXT: fmov s1, w10
; CHECK-NEXT: cmp w15, w8 ; CHECK-NEXT: csel w10, w12, w8, lo
; CHECK-NEXT: fcvtzu w17, d2
; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: csel w9, w15, w8, lo
; CHECK-NEXT: fcvtzu w15, d4
; CHECK-NEXT: cmp w16, w8
; CHECK-NEXT: fcvtzu w18, d1
; CHECK-NEXT: csel w16, w16, w8, lo
; CHECK-NEXT: cmp w17, w8
; CHECK-NEXT: csel w17, w17, w8, lo
; CHECK-NEXT: cmp w15, w8
; CHECK-NEXT: mov v0.s[1], w11 ; CHECK-NEXT: mov v0.s[1], w11
; CHECK-NEXT: fcvtzu w0, d5 ; CHECK-NEXT: cmp w16, w8
; CHECK-NEXT: csel w11, w15, w8, lo ; CHECK-NEXT: csel w11, w16, w8, lo
; CHECK-NEXT: fmov s2, w10
; CHECK-NEXT: cmp w18, w8
; CHECK-NEXT: mov d4, v6.d[1]
; CHECK-NEXT: csel w10, w18, w8, lo
; CHECK-NEXT: cmp w0, w8
; CHECK-NEXT: fmov s1, w11
; CHECK-NEXT: csel w11, w0, w8, lo
; CHECK-NEXT: mov v2.s[1], w13
; CHECK-NEXT: mov w13, v0.s[1]
; CHECK-NEXT: fcvtzu w15, d4
; CHECK-NEXT: mov v1.s[1], w17
; CHECK-NEXT: fmov s3, w11
; CHECK-NEXT: mov d4, v7.d[1]
; CHECK-NEXT: mov v0.h[1], w13
; CHECK-NEXT: fmov w11, s2
; CHECK-NEXT: mov v3.s[1], w10
; CHECK-NEXT: cmp w15, w8 ; CHECK-NEXT: cmp w15, w8
; CHECK-NEXT: mov w10, v1.s[1] ; CHECK-NEXT: mov v1.s[1], w13
; CHECK-NEXT: mov w13, v2.s[1] ; CHECK-NEXT: mov w12, v0.s[1]
; CHECK-NEXT: fmov s2, w12 ; CHECK-NEXT: fmov s3, w10
; CHECK-NEXT: mov v0.h[2], w11
; CHECK-NEXT: fcvtzu w11, d6
; CHECK-NEXT: csel w12, w15, w8, lo
; CHECK-NEXT: mov v1.h[1], w10
; CHECK-NEXT: fmov w10, s3
; CHECK-NEXT: cmp w11, w8
; CHECK-NEXT: csel w11, w11, w8, lo
; CHECK-NEXT: mov v0.h[3], w13
; CHECK-NEXT: fcvtzu w13, d7
; CHECK-NEXT: mov v1.h[2], w10
; CHECK-NEXT: fmov s5, w11
; CHECK-NEXT: fcvtzu w10, d4 ; CHECK-NEXT: fcvtzu w10, d4
; CHECK-NEXT: mov w11, v3.s[1] ; CHECK-NEXT: fmov w14, s1
; CHECK-NEXT: mov v2.s[1], w14 ; CHECK-NEXT: mov v0.h[1], w12
; CHECK-NEXT: fmov s3, w16 ; CHECK-NEXT: fcvtzu w12, d2
; CHECK-NEXT: mov v5.s[1], w12 ; CHECK-NEXT: csel w15, w15, w8, lo
; CHECK-NEXT: cmp w17, w8
; CHECK-NEXT: mov w13, v1.s[1]
; CHECK-NEXT: mov v0.h[2], w14
; CHECK-NEXT: fcvtzu w14, d5
; CHECK-NEXT: mov d1, v6.d[1]
; CHECK-NEXT: csel w16, w17, w8, lo
; CHECK-NEXT: cmp w10, w8 ; CHECK-NEXT: cmp w10, w8
; CHECK-NEXT: mov d2, v7.d[1]
; CHECK-NEXT: csel w10, w10, w8, lo ; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: cmp w13, w8 ; CHECK-NEXT: cmp w12, w8
; CHECK-NEXT: csel w8, w13, w8, lo ; CHECK-NEXT: csel w12, w12, w8, lo
; CHECK-NEXT: fmov w12, s2 ; CHECK-NEXT: cmp w14, w8
; CHECK-NEXT: mov v1.h[3], w11 ; CHECK-NEXT: csel w14, w14, w8, lo
; CHECK-NEXT: fmov w13, s5 ; CHECK-NEXT: fcvtzu w17, d1
; CHECK-NEXT: mov w14, v2.s[1]
; CHECK-NEXT: fmov s2, w8
; CHECK-NEXT: mov w11, v5.s[1]
; CHECK-NEXT: mov v0.h[4], w12
; CHECK-NEXT: mov v1.h[4], w13
; CHECK-NEXT: mov v3.s[1], w9 ; CHECK-NEXT: mov v3.s[1], w9
; CHECK-NEXT: fcvtzu w9, d6
; CHECK-NEXT: fmov s1, w10
; CHECK-NEXT: fmov s5, w15
; CHECK-NEXT: fmov s4, w14
; CHECK-NEXT: cmp w17, w8
; CHECK-NEXT: csel w10, w17, w8, lo
; CHECK-NEXT: cmp w9, w8
; CHECK-NEXT: fcvtzu w14, d2
; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: mov v4.s[1], w12
; CHECK-NEXT: fcvtzu w12, d7
; CHECK-NEXT: mov v1.s[1], w16
; CHECK-NEXT: mov v0.h[3], w13
; CHECK-NEXT: cmp w14, w8
; CHECK-NEXT: fmov s2, w9
; CHECK-NEXT: mov w15, v1.s[1]
; CHECK-NEXT: csel w14, w14, w8, lo
; CHECK-NEXT: cmp w12, w8
; CHECK-NEXT: mov w9, v4.s[1]
; CHECK-NEXT: csel w8, w12, w8, lo
; CHECK-NEXT: fmov w12, s4
; CHECK-NEXT: mov v1.h[1], w15
; CHECK-NEXT: mov v2.s[1], w10 ; CHECK-NEXT: mov v2.s[1], w10
; CHECK-NEXT: mov v0.h[5], w14 ; CHECK-NEXT: mov w15, v3.s[1]
; CHECK-NEXT: mov v1.h[5], w11 ; CHECK-NEXT: fmov w10, s3
; CHECK-NEXT: fmov w8, s3 ; CHECK-NEXT: mov v1.h[2], w12
; CHECK-NEXT: fmov w9, s2 ; CHECK-NEXT: fmov s3, w8
; CHECK-NEXT: mov w10, v3.s[1] ; CHECK-NEXT: fmov w12, s2
; CHECK-NEXT: mov w11, v2.s[1] ; CHECK-NEXT: mov v5.s[1], w11
; CHECK-NEXT: mov v0.h[6], w8 ; CHECK-NEXT: mov v1.h[3], w9
; CHECK-NEXT: mov v1.h[6], w9 ; CHECK-NEXT: mov w8, v2.s[1]
; CHECK-NEXT: mov v0.h[7], w10 ; CHECK-NEXT: mov v3.s[1], w14
; CHECK-NEXT: mov v0.h[4], w10
; CHECK-NEXT: mov v1.h[4], w12
; CHECK-NEXT: fmov w9, s5
; CHECK-NEXT: fmov w10, s3
; CHECK-NEXT: mov v0.h[5], w15
; CHECK-NEXT: mov v1.h[5], w8
; CHECK-NEXT: mov w8, v5.s[1]
; CHECK-NEXT: mov w11, v3.s[1]
; CHECK-NEXT: mov v0.h[6], w9
; CHECK-NEXT: mov v1.h[6], w10
; CHECK-NEXT: mov v0.h[7], w8
; CHECK-NEXT: mov v1.h[7], w11 ; CHECK-NEXT: mov v1.h[7], w11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <16 x i16> @llvm.fptoui.sat.v16f64.v16i16(<16 x double> %f) %x = call <16 x i16> @llvm.fptoui.sat.v16f64.v16i16(<16 x double> %f)
ret <16 x i16> %x ret <16 x i16> %x
} }

llvm/test/CodeGen/AArch64/funnel-shift-rot.ll

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret i64 %f ret i64 %f
} }
; Vector rotate. ; Vector rotate.
define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) { define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
; CHECK-LABEL: rotl_v4i32: ; CHECK-LABEL: rotl_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.4s, #31
; CHECK-NEXT: neg v3.4s, v1.4s ; CHECK-NEXT: neg v3.4s, v1.4s
; CHECK-NEXT: movi v2.4s, #31
; CHECK-NEXT: and v1.16b, v1.16b, v2.16b ; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
; CHECK-NEXT: and v2.16b, v3.16b, v2.16b ; CHECK-NEXT: and v2.16b, v3.16b, v2.16b
; CHECK-NEXT: neg v2.4s, v2.4s ; CHECK-NEXT: neg v2.4s, v2.4s
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z) %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
▲ Show 20 Lines • Show All 138 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; A few trivial vector tests ; A few trivial vector tests
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: vec_4xi32_splat_eq: ; CHECK-LABEL: vec_4xi32_splat_eq:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-NEXT: xtn v0.4h, v0.4s ; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = lshr <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y %t0 = lshr <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
%t1 = and <4 x i32> %t0, %x %t1 = and <4 x i32> %t0, %x
%res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0> %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
ret <4 x i1> %res ret <4 x i1> %res
} }
Show All 13 Lines; CHECK-NEXT: ret
%t1 = and <4 x i32> %t0, %x %t1 = and <4 x i32> %t0, %x
%res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0> %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
ret <4 x i1> %res ret <4 x i1> %res
} }
define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: vec_4xi32_nonsplat_undef0_eq: ; CHECK-LABEL: vec_4xi32_nonsplat_undef0_eq:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-NEXT: xtn v0.4h, v0.4s ; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = lshr <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y %t0 = lshr <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y
%t1 = and <4 x i32> %t0, %x %t1 = and <4 x i32> %t0, %x
%res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0> %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
ret <4 x i1> %res ret <4 x i1> %res
} }
define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: vec_4xi32_nonsplat_undef1_eq: ; CHECK-LABEL: vec_4xi32_nonsplat_undef1_eq:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: neg v1.4s, v1.4s ; CHECK-NEXT: neg v1.4s, v1.4s
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: and v0.16b, v1.16b, v0.16b ; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-NEXT: xtn v0.4h, v0.4s ; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = lshr <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y %t0 = lshr <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
%t1 = and <4 x i32> %t0, %x %t1 = and <4 x i32> %t0, %x
%res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0> %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>
ret <4 x i1> %res ret <4 x i1> %res
} }
define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: vec_4xi32_nonsplat_undef2_eq: ; CHECK-LABEL: vec_4xi32_nonsplat_undef2_eq:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: neg v1.4s, v1.4s ; CHECK-NEXT: neg v1.4s, v1.4s
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: and v0.16b, v1.16b, v0.16b ; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-NEXT: xtn v0.4h, v0.4s ; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = lshr <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y %t0 = lshr <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y
%t1 = and <4 x i32> %t0, %x %t1 = and <4 x i32> %t0, %x
%res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0> %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>
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llvm/test/CodeGen/AArch64/lowerMUL-newload.ll

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Linesentry:
%v5 = trunc <4 x i32> %v4 to <4 x i16> %v5 = trunc <4 x i32> %v4 to <4 x i16>
ret <4 x i16> %v5 ret <4 x i16> %v5
} }
define <4 x i32> @addmuli16_and(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) { define <4 x i32> @addmuli16_and(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) {
; CHECK-LABEL: addmuli16_and: ; CHECK-LABEL: addmuli16_and:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: smull v1.4s, v1.4h, v2.4h ; CHECK-NEXT: smull v1.4s, v1.4h, v2.4h
; CHECK-NEXT: movi v3.2d, #0x00ffff0000ffff
; CHECK-NEXT: smlal v1.4s, v0.4h, v2.4h ; CHECK-NEXT: smlal v1.4s, v0.4h, v2.4h
; CHECK-NEXT: and v0.16b, v1.16b, v3.16b ; CHECK-NEXT: movi v0.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%v0 = sext <4 x i16> %vec0 to <4 x i32> %v0 = sext <4 x i16> %vec0 to <4 x i32>
%v1 = sext <4 x i16> %vec1 to <4 x i32> %v1 = sext <4 x i16> %vec1 to <4 x i32>
%v2 = sext <4 x i16> %vec2 to <4 x i32> %v2 = sext <4 x i16> %vec2 to <4 x i32>
%v3 = add <4 x i32> %v1, %v0 %v3 = add <4 x i32> %v1, %v0
%v4 = mul <4 x i32> %v3, %v2 %v4 = mul <4 x i32> %v3, %v2
%v5 = and <4 x i32> %v4, <i32 65535, i32 65535, i32 65535, i32 65535> %v5 = and <4 x i32> %v4, <i32 65535, i32 65535, i32 65535, i32 65535>
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Linesentry:
%v5 = trunc <2 x i64> %v4 to <2 x i32> %v5 = trunc <2 x i64> %v4 to <2 x i32>
ret <2 x i32> %v5 ret <2 x i32> %v5
} }
define <2 x i64> @addmuli32_and(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2) { define <2 x i64> @addmuli32_and(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2) {
; CHECK-LABEL: addmuli32_and: ; CHECK-LABEL: addmuli32_and:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: smull v1.2d, v1.2s, v2.2s ; CHECK-NEXT: smull v1.2d, v1.2s, v2.2s
; CHECK-NEXT: movi v3.2d, #0x000000ffffffff
; CHECK-NEXT: smlal v1.2d, v0.2s, v2.2s ; CHECK-NEXT: smlal v1.2d, v0.2s, v2.2s
; CHECK-NEXT: and v0.16b, v1.16b, v3.16b ; CHECK-NEXT: movi v0.2d, #0x000000ffffffff
; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%v0 = sext <2 x i32> %vec0 to <2 x i64> %v0 = sext <2 x i32> %vec0 to <2 x i64>
%v1 = sext <2 x i32> %vec1 to <2 x i64> %v1 = sext <2 x i32> %vec1 to <2 x i64>
%v2 = sext <2 x i32> %vec2 to <2 x i64> %v2 = sext <2 x i32> %vec2 to <2 x i64>
%v3 = add <2 x i64> %v1, %v0 %v3 = add <2 x i64> %v1, %v0
%v4 = mul <2 x i64> %v3, %v2 %v4 = mul <2 x i64> %v3, %v2
%v5 = and <2 x i64> %v4, <i64 4294967295, i64 4294967295> %v5 = and <2 x i64> %v4, <i64 4294967295, i64 4294967295>
▲ Show 20 Lines • Show All 175 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/minmax.ll

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <16 x i32> %t2 ret <16 x i32> %t2
} }
; The icmp is used by two instructions, so don't produce a umin node. ; The icmp is used by two instructions, so don't produce a umin node.
define <16 x i8> @t12(<16 x i8> %a, <16 x i8> %b) { define <16 x i8> @t12(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: t12: ; CHECK-LABEL: t12:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmhi v2.16b, v1.16b, v0.16b ; CHECK-NEXT: cmhi v2.16b, v1.16b, v0.16b
; CHECK-NEXT: movi v3.16b, #1
; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-NEXT: and v1.16b, v2.16b, v3.16b ; CHECK-NEXT: movi v1.16b, #1
; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
; CHECK-NEXT: add v0.16b, v1.16b, v0.16b ; CHECK-NEXT: add v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t1 = icmp ugt <16 x i8> %b, %a %t1 = icmp ugt <16 x i8> %b, %a
%t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b
%t3 = zext <16 x i1> %t1 to <16 x i8> %t3 = zext <16 x i1> %t1 to <16 x i8>
%t4 = add <16 x i8> %t3, %t2 %t4 = add <16 x i8> %t3, %t2
ret <16 x i8> %t4 ret <16 x i8> %t4
} }
Show All 35 Lines

llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; Verify splitvec type legalisation works as expected. ; Verify splitvec type legalisation works as expected.
define <16 x float> @splice_v16f32_idx(<16 x float> %a, <16 x float> %b) #0 { define <16 x float> @splice_v16f32_idx(<16 x float> %a, <16 x float> %b) #0 {
; CHECK-LABEL: splice_v16f32_idx: ; CHECK-LABEL: splice_v16f32_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v5.16b, v4.16b, v5.16b, #12 ; CHECK-NEXT: ext v5.16b, v4.16b, v5.16b, #12
; CHECK-NEXT: ext v6.16b, v2.16b, v3.16b, #12 ; CHECK-NEXT: ext v6.16b, v2.16b, v3.16b, #12
; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #12 ; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #12
; CHECK-NEXT: ext v2.16b, v3.16b, v4.16b, #12 ; CHECK-NEXT: ext v2.16b, v3.16b, v4.16b, #12
; CHECK-NEXT: mov v3.16b, v5.16b
; CHECK-NEXT: mov v1.16b, v6.16b ; CHECK-NEXT: mov v1.16b, v6.16b
; CHECK-NEXT: mov v3.16b, v5.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 7) %res = call <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 7)
ret <16 x float> %res ret <16 x float> %res
} }
; ;
; VECTOR_SPLICE (trailing elements) ; VECTOR_SPLICE (trailing elements)
; ;
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; Verify splitvec type legalisation works as expected. ; Verify splitvec type legalisation works as expected.
define <16 x float> @splice_v16f32(<16 x float> %a, <16 x float> %b) #0 { define <16 x float> @splice_v16f32(<16 x float> %a, <16 x float> %b) #0 {
; CHECK-LABEL: splice_v16f32: ; CHECK-LABEL: splice_v16f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v5.16b, v4.16b, v5.16b, #12 ; CHECK-NEXT: ext v5.16b, v4.16b, v5.16b, #12
; CHECK-NEXT: ext v6.16b, v2.16b, v3.16b, #12 ; CHECK-NEXT: ext v6.16b, v2.16b, v3.16b, #12
; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #12 ; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #12
; CHECK-NEXT: ext v2.16b, v3.16b, v4.16b, #12 ; CHECK-NEXT: ext v2.16b, v3.16b, v4.16b, #12
; CHECK-NEXT: mov v3.16b, v5.16b
; CHECK-NEXT: mov v1.16b, v6.16b ; CHECK-NEXT: mov v1.16b, v6.16b
; CHECK-NEXT: mov v3.16b, v5.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 -9) %res = call <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 -9)
ret <16 x float> %res ret <16 x float> %res
} }
declare <2 x i8> @llvm.experimental.vector.splice.v2i8(<2 x i8>, <2 x i8>, i32) declare <2 x i8> @llvm.experimental.vector.splice.v2i8(<2 x i8>, <2 x i8>, i32)
declare <16 x i8> @llvm.experimental.vector.splice.v16i8(<16 x i8>, <16 x i8>, i32) declare <16 x i8> @llvm.experimental.vector.splice.v16i8(<16 x i8>, <16 x i8>, i32)
declare <8 x i32> @llvm.experimental.vector.splice.v8i32(<8 x i32>, <8 x i32>, i32) declare <8 x i32> @llvm.experimental.vector.splice.v8i32(<8 x i32>, <8 x i32>, i32)
declare <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float>, <16 x float>, i32) declare <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float>, <16 x float>, i32)
declare <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double>, <2 x double>, i32) declare <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double>, <2 x double>, i32)
attributes #0 = { nounwind "target-features"="+neon" } attributes #0 = { nounwind "target-features"="+neon" }

llvm/test/CodeGen/AArch64/neon-abd.ll

Show First 20 Lines • Show All 139 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true) %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)
ret <4 x i32> %abs ret <4 x i32> %abs
} }
define <2 x i64> @sabd_2d(<2 x i64> %a, <2 x i64> %b) #0 { define <2 x i64> @sabd_2d(<2 x i64> %a, <2 x i64> %b) #0 {
; CHECK-LABEL: sabd_2d: ; CHECK-LABEL: sabd_2d:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, v0.d[1] ; CHECK-NEXT: mov x8, v0.d[1]
; CHECK-NEXT: fmov x10, d0 ; CHECK-NEXT: mov x10, v1.d[1]
; CHECK-NEXT: mov x9, v1.d[1] ; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: asr x11, x10, #63
; CHECK-NEXT: asr x12, x8, #63 ; CHECK-NEXT: asr x12, x8, #63
; CHECK-NEXT: asr x13, x9, #63 ; CHECK-NEXT: asr x13, x10, #63
; CHECK-NEXT: subs x8, x8, x9 ; CHECK-NEXT: subs x8, x8, x10
; CHECK-NEXT: fmov x9, d1 ; CHECK-NEXT: fmov x10, d1
; CHECK-NEXT: sbcs x12, x12, x13 ; CHECK-NEXT: sbcs x12, x12, x13
; CHECK-NEXT: asr x13, x9, #63 ; CHECK-NEXT: asr x11, x9, #63
; CHECK-NEXT: subs x9, x10, x9 ; CHECK-NEXT: asr x13, x10, #63
; CHECK-NEXT: subs x9, x9, x10
; CHECK-NEXT: sbcs x10, x11, x13 ; CHECK-NEXT: sbcs x10, x11, x13
; CHECK-NEXT: cmp x10, #0 ; CHECK-NEXT: cmp x10, #0
; CHECK-NEXT: cneg x9, x9, lt ; CHECK-NEXT: cneg x9, x9, lt
; CHECK-NEXT: cmp x12, #0 ; CHECK-NEXT: cmp x12, #0
; CHECK-NEXT: cneg x8, x8, lt ; CHECK-NEXT: cneg x8, x8, lt
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: fmov d1, x8 ; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: mov v0.d[1], v1.d[0] ; CHECK-NEXT: mov v0.d[1], v1.d[0]
▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true) %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)
ret <4 x i32> %abs ret <4 x i32> %abs
} }
define <2 x i64> @uabd_2d(<2 x i64> %a, <2 x i64> %b) #0 { define <2 x i64> @uabd_2d(<2 x i64> %a, <2 x i64> %b) #0 {
; CHECK-LABEL: uabd_2d: ; CHECK-LABEL: uabd_2d:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, v0.d[1] ; CHECK-NEXT: mov x8, v0.d[1]
; CHECK-NEXT: fmov x10, d0
; CHECK-NEXT: mov x9, v1.d[1] ; CHECK-NEXT: mov x9, v1.d[1]
; CHECK-NEXT: fmov x10, d0
; CHECK-NEXT: subs x8, x8, x9 ; CHECK-NEXT: subs x8, x8, x9
; CHECK-NEXT: fmov x9, d1 ; CHECK-NEXT: fmov x9, d1
; CHECK-NEXT: ngcs x11, xzr ; CHECK-NEXT: ngcs x11, xzr
; CHECK-NEXT: subs x9, x10, x9 ; CHECK-NEXT: subs x9, x10, x9
; CHECK-NEXT: ngcs x10, xzr ; CHECK-NEXT: ngcs x10, xzr
; CHECK-NEXT: cmp x10, #0 ; CHECK-NEXT: cmp x10, #0
; CHECK-NEXT: cneg x9, x9, lt ; CHECK-NEXT: cneg x9, x9, lt
; CHECK-NEXT: cmp x11, #0 ; CHECK-NEXT: cmp x11, #0
▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll

Show First 20 Lines • Show All 886 Lines • ▼ Show 20 Lines
define <8 x i8> @vselect_equivalent_shuffle_v8i8(<8 x i8> %a, <8 x i8> %b) { define <8 x i8> @vselect_equivalent_shuffle_v8i8(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: vselect_equivalent_shuffle_v8i8: ; CHECK-LABEL: vselect_equivalent_shuffle_v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI89_0 ; CHECK-NEXT: adrp x8, .LCPI89_0
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 ; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: mov v0.d[1], v1.d[0] ; CHECK-NEXT: mov v0.d[1], v1.d[0]
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI89_0] ; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI89_0]
; CHECK-NEXT: tbl v0.8b, { v0.16b }, v1.8b ; CHECK-NEXT: tbl v0.8b, { v0.16b }, v2.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7> %c = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
ret <8 x i8> %c ret <8 x i8> %c
} }
define <8 x i16> @vselect_equivalent_shuffle_v8i16(<8 x i16> %a, <8 x i16> %b) { define <8 x i16> @vselect_equivalent_shuffle_v8i16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: vselect_equivalent_shuffle_v8i16: ; CHECK-LABEL: vselect_equivalent_shuffle_v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/neon-dotreduce.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+dotprod < %s | FileCheck %s ; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+dotprod < %s | FileCheck %s
declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>) declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>) declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
define i32 @test_udot_v8i8(i8* nocapture readonly %a, i8* nocapture readonly %b) { define i32 @test_udot_v8i8(i8* nocapture readonly %a, i8* nocapture readonly %b) {
; CHECK-LABEL: test_udot_v8i8: ; CHECK-LABEL: test_udot_v8i8:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x0] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: ldr d2, [x1] ; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: udot v0.2s, v2.8b, v1.8b ; CHECK-NEXT: udot v2.2s, v1.8b, v0.8b
; CHECK-NEXT: addp v0.2s, v0.2s, v0.2s ; CHECK-NEXT: addp v0.2s, v2.2s, v2.2s
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = bitcast i8* %a to <8 x i8>* %0 = bitcast i8* %a to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0 %1 = load <8 x i8>, <8 x i8>* %0
%2 = zext <8 x i8> %1 to <8 x i32> %2 = zext <8 x i8> %1 to <8 x i32>
%3 = bitcast i8* %b to <8 x i8>* %3 = bitcast i8* %b to <8 x i8>*
%4 = load <8 x i8>, <8 x i8>* %3 %4 = load <8 x i8>, <8 x i8>* %3
%5 = zext <8 x i8> %4 to <8 x i32> %5 = zext <8 x i8> %4 to <8 x i32>
%6 = mul nuw nsw <8 x i32> %5, %2 %6 = mul nuw nsw <8 x i32> %5, %2
%7 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %6) %7 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %6)
ret i32 %7 ret i32 %7
} }
define i32 @test_udot_v8i8_nomla(i8* nocapture readonly %a1) { define i32 @test_udot_v8i8_nomla(i8* nocapture readonly %a1) {
; CHECK-LABEL: test_udot_v8i8_nomla: ; CHECK-LABEL: test_udot_v8i8_nomla:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr d1, [x0]
; CHECK-NEXT: movi v0.8b, #1 ; CHECK-NEXT: movi v0.8b, #1
; CHECK-NEXT: ldr d2, [x0] ; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: movi v1.2d, #0000000000000000 ; CHECK-NEXT: udot v2.2s, v1.8b, v0.8b
; CHECK-NEXT: udot v1.2s, v2.8b, v0.8b ; CHECK-NEXT: addp v0.2s, v2.2s, v2.2s
; CHECK-NEXT: addp v0.2s, v1.2s, v1.2s
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = bitcast i8* %a1 to <8 x i8>* %0 = bitcast i8* %a1 to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0 %1 = load <8 x i8>, <8 x i8>* %0
%2 = zext <8 x i8> %1 to <8 x i32> %2 = zext <8 x i8> %1 to <8 x i32>
%3 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %2) %3 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %2)
ret i32 %3 ret i32 %3
} }
define i32 @test_sdot_v8i8(i8* nocapture readonly %a, i8* nocapture readonly %b) { define i32 @test_sdot_v8i8(i8* nocapture readonly %a, i8* nocapture readonly %b) {
; CHECK-LABEL: test_sdot_v8i8: ; CHECK-LABEL: test_sdot_v8i8:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x0] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: ldr d2, [x1] ; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: sdot v0.2s, v2.8b, v1.8b ; CHECK-NEXT: sdot v2.2s, v1.8b, v0.8b
; CHECK-NEXT: addp v0.2s, v0.2s, v0.2s ; CHECK-NEXT: addp v0.2s, v2.2s, v2.2s
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = bitcast i8* %a to <8 x i8>* %0 = bitcast i8* %a to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0 %1 = load <8 x i8>, <8 x i8>* %0
%2 = sext <8 x i8> %1 to <8 x i32> %2 = sext <8 x i8> %1 to <8 x i32>
%3 = bitcast i8* %b to <8 x i8>* %3 = bitcast i8* %b to <8 x i8>*
%4 = load <8 x i8>, <8 x i8>* %3 %4 = load <8 x i8>, <8 x i8>* %3
%5 = sext <8 x i8> %4 to <8 x i32> %5 = sext <8 x i8> %4 to <8 x i32>
%6 = mul nsw <8 x i32> %5, %2 %6 = mul nsw <8 x i32> %5, %2
%7 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %6) %7 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %6)
ret i32 %7 ret i32 %7
} }
define i32 @test_sdot_v8i8_nomla(i8* nocapture readonly %a1) { define i32 @test_sdot_v8i8_nomla(i8* nocapture readonly %a1) {
; CHECK-LABEL: test_sdot_v8i8_nomla: ; CHECK-LABEL: test_sdot_v8i8_nomla:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr d1, [x0]
; CHECK-NEXT: movi v0.8b, #1 ; CHECK-NEXT: movi v0.8b, #1
; CHECK-NEXT: ldr d2, [x0] ; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: movi v1.2d, #0000000000000000 ; CHECK-NEXT: sdot v2.2s, v1.8b, v0.8b
; CHECK-NEXT: sdot v1.2s, v2.8b, v0.8b ; CHECK-NEXT: addp v0.2s, v2.2s, v2.2s
; CHECK-NEXT: addp v0.2s, v1.2s, v1.2s
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = bitcast i8* %a1 to <8 x i8>* %0 = bitcast i8* %a1 to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0 %1 = load <8 x i8>, <8 x i8>* %0
%2 = sext <8 x i8> %1 to <8 x i32> %2 = sext <8 x i8> %1 to <8 x i32>
%3 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %2) %3 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %2)
ret i32 %3 ret i32 %3
} }
define i32 @test_udot_v16i8(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %sum) { define i32 @test_udot_v16i8(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %sum) {
; CHECK-LABEL: test_udot_v16i8: ; CHECK-LABEL: test_udot_v16i8:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: ldr q0, [x1]
; CHECK-NEXT: ldr q1, [x1] ; CHECK-NEXT: ldr q1, [x0]
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: udot v0.4s, v1.16b, v2.16b ; CHECK-NEXT: udot v2.4s, v0.16b, v1.16b
; CHECK-NEXT: addv s0, v0.4s ; CHECK-NEXT: addv s0, v2.4s
; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: add w0, w8, w2 ; CHECK-NEXT: add w0, w8, w2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = bitcast i8* %a to <16 x i8>* %0 = bitcast i8* %a to <16 x i8>*
%1 = load <16 x i8>, <16 x i8>* %0 %1 = load <16 x i8>, <16 x i8>* %0
%2 = zext <16 x i8> %1 to <16 x i32> %2 = zext <16 x i8> %1 to <16 x i32>
%3 = bitcast i8* %b to <16 x i8>* %3 = bitcast i8* %b to <16 x i8>*
%4 = load <16 x i8>, <16 x i8>* %3 %4 = load <16 x i8>, <16 x i8>* %3
%5 = zext <16 x i8> %4 to <16 x i32> %5 = zext <16 x i8> %4 to <16 x i32>
%6 = mul nuw nsw <16 x i32> %5, %2 %6 = mul nuw nsw <16 x i32> %5, %2
%7 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %6) %7 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %6)
%op.extra = add i32 %7, %sum %op.extra = add i32 %7, %sum
ret i32 %op.extra ret i32 %op.extra
} }
define i32 @test_udot_v16i8_nomla(i8* nocapture readonly %a1) { define i32 @test_udot_v16i8_nomla(i8* nocapture readonly %a1) {
; CHECK-LABEL: test_udot_v16i8_nomla: ; CHECK-LABEL: test_udot_v16i8_nomla:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v0.16b, #1 ; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: movi v1.16b, #1
; CHECK-NEXT: movi v1.2d, #0000000000000000 ; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: udot v1.4s, v2.16b, v0.16b ; CHECK-NEXT: udot v2.4s, v0.16b, v1.16b
; CHECK-NEXT: addv s0, v1.4s ; CHECK-NEXT: addv s0, v2.4s
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = bitcast i8* %a1 to <16 x i8>* %0 = bitcast i8* %a1 to <16 x i8>*
%1 = load <16 x i8>, <16 x i8>* %0 %1 = load <16 x i8>, <16 x i8>* %0
%2 = zext <16 x i8> %1 to <16 x i32> %2 = zext <16 x i8> %1 to <16 x i32>
%3 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %2) %3 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %2)
ret i32 %3 ret i32 %3
} }
define i32 @test_sdot_v16i8(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %sum) { define i32 @test_sdot_v16i8(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %sum) {
; CHECK-LABEL: test_sdot_v16i8: ; CHECK-LABEL: test_sdot_v16i8:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: ldr q0, [x1]
; CHECK-NEXT: ldr q1, [x1] ; CHECK-NEXT: ldr q1, [x0]
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: sdot v0.4s, v1.16b, v2.16b ; CHECK-NEXT: sdot v2.4s, v0.16b, v1.16b
; CHECK-NEXT: addv s0, v0.4s ; CHECK-NEXT: addv s0, v2.4s
; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: add w0, w8, w2 ; CHECK-NEXT: add w0, w8, w2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = bitcast i8* %a to <16 x i8>* %0 = bitcast i8* %a to <16 x i8>*
%1 = load <16 x i8>, <16 x i8>* %0 %1 = load <16 x i8>, <16 x i8>* %0
%2 = sext <16 x i8> %1 to <16 x i32> %2 = sext <16 x i8> %1 to <16 x i32>
%3 = bitcast i8* %b to <16 x i8>* %3 = bitcast i8* %b to <16 x i8>*
%4 = load <16 x i8>, <16 x i8>* %3 %4 = load <16 x i8>, <16 x i8>* %3
%5 = sext <16 x i8> %4 to <16 x i32> %5 = sext <16 x i8> %4 to <16 x i32>
%6 = mul nsw <16 x i32> %5, %2 %6 = mul nsw <16 x i32> %5, %2
%7 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %6) %7 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %6)
%op.extra = add nsw i32 %7, %sum %op.extra = add nsw i32 %7, %sum
ret i32 %op.extra ret i32 %op.extra
} }
define i32 @test_sdot_v16i8_nomla(i8* nocapture readonly %a1) { define i32 @test_sdot_v16i8_nomla(i8* nocapture readonly %a1) {
; CHECK-LABEL: test_sdot_v16i8_nomla: ; CHECK-LABEL: test_sdot_v16i8_nomla:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v0.16b, #1 ; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: movi v1.16b, #1
; CHECK-NEXT: movi v1.2d, #0000000000000000 ; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: sdot v1.4s, v2.16b, v0.16b ; CHECK-NEXT: sdot v2.4s, v0.16b, v1.16b
; CHECK-NEXT: addv s0, v1.4s ; CHECK-NEXT: addv s0, v2.4s
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = bitcast i8* %a1 to <16 x i8>* %0 = bitcast i8* %a1 to <16 x i8>*
%1 = load <16 x i8>, <16 x i8>* %0 %1 = load <16 x i8>, <16 x i8>* %0
%2 = sext <16 x i8> %1 to <16 x i32> %2 = sext <16 x i8> %1 to <16 x i32>
%3 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %2) %3 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %2)
ret i32 %3 ret i32 %3
Show All 20 Linesentry:
%r2 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %m2) %r2 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %m2)
%x = add i32 %r1, %r2 %x = add i32 %r1, %r2
ret i32 %x ret i32 %x
} }
define i32 @test_udot_v8i8_double_nomla(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) { define i32 @test_udot_v8i8_double_nomla(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) {
; CHECK-LABEL: test_udot_v8i8_double_nomla: ; CHECK-LABEL: test_udot_v8i8_double_nomla:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v1.8b, #1 ; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: movi v3.2d, #0000000000000000 ; CHECK-NEXT: movi v3.8b, #1
; CHECK-NEXT: udot v3.2s, v2.8b, v1.8b ; CHECK-NEXT: udot v1.2s, v2.8b, v3.8b
; CHECK-NEXT: udot v3.2s, v0.8b, v1.8b ; CHECK-NEXT: udot v1.2s, v0.8b, v3.8b
; CHECK-NEXT: addp v0.2s, v3.2s, v3.2s ; CHECK-NEXT: addp v0.2s, v1.2s, v1.2s
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%az = zext <8 x i8> %a to <8 x i32> %az = zext <8 x i8> %a to <8 x i32>
%r1 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %az) %r1 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %az)
%cz = zext <8 x i8> %c to <8 x i32> %cz = zext <8 x i8> %c to <8 x i32>
%r2 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %cz) %r2 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %cz)
%x = add i32 %r1, %r2 %x = add i32 %r1, %r2
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Linesentry:
%r2 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %m2) %r2 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %m2)
%x = add i32 %r1, %r2 %x = add i32 %r1, %r2
ret i32 %x ret i32 %x
} }
define i32 @test_sdot_v8i8_double_nomla(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) { define i32 @test_sdot_v8i8_double_nomla(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) {
; CHECK-LABEL: test_sdot_v8i8_double_nomla: ; CHECK-LABEL: test_sdot_v8i8_double_nomla:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v1.8b, #1 ; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: movi v3.2d, #0000000000000000 ; CHECK-NEXT: movi v3.8b, #1
; CHECK-NEXT: sdot v3.2s, v2.8b, v1.8b ; CHECK-NEXT: sdot v1.2s, v2.8b, v3.8b
; CHECK-NEXT: sdot v3.2s, v0.8b, v1.8b ; CHECK-NEXT: sdot v1.2s, v0.8b, v3.8b
; CHECK-NEXT: addp v0.2s, v3.2s, v3.2s ; CHECK-NEXT: addp v0.2s, v1.2s, v1.2s
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%az = sext <8 x i8> %a to <8 x i32> %az = sext <8 x i8> %a to <8 x i32>
%r1 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %az) %r1 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %az)
%cz = sext <8 x i8> %c to <8 x i32> %cz = sext <8 x i8> %c to <8 x i32>
%r2 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %cz) %r2 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %cz)
%x = add i32 %r1, %r2 %x = add i32 %r1, %r2
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llvm/test/CodeGen/AArch64/neon-truncstore.ll

Show All 36 Lines; CHECK-NEXT: ret
store <8 x i32> %b, <8 x i32>* %result store <8 x i32> %b, <8 x i32>* %result
ret void ret void
} }
define void @v2i32_v2i16(<2 x i32> %a, <2 x i16>* %result) { define void @v2i32_v2i16(<2 x i32> %a, <2 x i16>* %result) {
; CHECK-LABEL: v2i32_v2i16: ; CHECK-LABEL: v2i32_v2i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strh w9, [x0] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: strh w8, [x0, #2] ; CHECK-NEXT: strh w8, [x0, #2]
; CHECK-NEXT: strh w9, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%b = trunc <2 x i32> %a to <2 x i16> %b = trunc <2 x i32> %a to <2 x i16>
store <2 x i16> %b, <2 x i16>* %result store <2 x i16> %b, <2 x i16>* %result
ret void ret void
} }
define void @v4i32_v4i16(<4 x i32> %a, <4 x i16>* %result) { define void @v4i32_v4i16(<4 x i32> %a, <4 x i16>* %result) {
; CHECK-LABEL: v4i32_v4i16: ; CHECK-LABEL: v4i32_v4i16:
Show All 28 Lines; CHECK-NEXT: ret
store <16 x i16> %b, <16 x i16>* %result store <16 x i16> %b, <16 x i16>* %result
ret void ret void
} }
define void @v2i32_v2i8(<2 x i32> %a, <2 x i8>* %result) { define void @v2i32_v2i8(<2 x i32> %a, <2 x i8>* %result) {
; CHECK-LABEL: v2i32_v2i8: ; CHECK-LABEL: v2i32_v2i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strb w9, [x0] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: strb w8, [x0, #1] ; CHECK-NEXT: strb w8, [x0, #1]
; CHECK-NEXT: strb w9, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%b = trunc <2 x i32> %a to <2 x i8> %b = trunc <2 x i32> %a to <2 x i8>
store <2 x i8> %b, <2 x i8>* %result store <2 x i8> %b, <2 x i8>* %result
ret void ret void
} }
define void @v4i32_v4i8(<4 x i32> %a, <4 x i8>* %result) { define void @v4i32_v4i8(<4 x i32> %a, <4 x i8>* %result) {
; CHECK-LABEL: v4i32_v4i8: ; CHECK-LABEL: v4i32_v4i8:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
store <32 x i8> %b, <32 x i8>* %result store <32 x i8> %b, <32 x i8>* %result
ret void ret void
} }
define void @v2i16_v2i8(<2 x i16> %a, <2 x i8>* %result) { define void @v2i16_v2i8(<2 x i16> %a, <2 x i8>* %result) {
; CHECK-LABEL: v2i16_v2i8: ; CHECK-LABEL: v2i16_v2i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strb w9, [x0] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: strb w8, [x0, #1] ; CHECK-NEXT: strb w8, [x0, #1]
; CHECK-NEXT: strb w9, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%b = trunc <2 x i16> %a to <2 x i8> %b = trunc <2 x i16> %a to <2 x i8>
store <2 x i8> %b, <2 x i8>* %result store <2 x i8> %b, <2 x i8>* %result
ret void ret void
} }
define void @v4i16_v4i8(<4 x i16> %a, <4 x i8>* %result) { define void @v4i16_v4i8(<4 x i16> %a, <4 x i8>* %result) {
; CHECK-LABEL: v4i16_v4i8: ; CHECK-LABEL: v4i16_v4i8:
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llvm/test/CodeGen/AArch64/nontemporal.ll

Show First 20 Lines • Show All 449 Lines • ▼ Show 20 Lines
define void @test_stnp_v17f32(<17 x float> %v, <17 x float>* %ptr) { define void @test_stnp_v17f32(<17 x float> %v, <17 x float>* %ptr) {
; CHECK-LABEL: test_stnp_v17f32: ; CHECK-LABEL: test_stnp_v17f32:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: ldr s16, [sp, #16] ; CHECK-NEXT: ldr s16, [sp, #16]
; CHECK-NEXT: add x8, sp, #20 ; CHECK-NEXT: add x8, sp, #20
; CHECK-NEXT: ldr s17, [sp] ; CHECK-NEXT: ldr s17, [sp]
; CHECK-NEXT: add x9, sp, #4 ; CHECK-NEXT: add x9, sp, #4
; CHECK-NEXT: ; kill: def $s4 killed $s4 def $q4 ; CHECK-NEXT: ; kill: def $s4 killed $s4 def $q4
; CHECK-NEXT: ; kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ; kill: def $s5 killed $s5 def $q5 ; CHECK-NEXT: ; kill: def $s5 killed $s5 def $q5
; CHECK-NEXT: ; kill: def $s1 killed $s1 def $q1 ; CHECK-NEXT: ; kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ; kill: def $s6 killed $s6 def $q6 ; CHECK-NEXT: ; kill: def $s6 killed $s6 def $q6
; CHECK-NEXT: ; kill: def $s2 killed $s2 def $q2 ; CHECK-NEXT: ; kill: def $s1 killed $s1 def $q1
; CHECK-NEXT: ; kill: def $s7 killed $s7 def $q7 ; CHECK-NEXT: ; kill: def $s7 killed $s7 def $q7
; CHECK-NEXT: ; kill: def $s2 killed $s2 def $q2
; CHECK-NEXT: ; kill: def $s3 killed $s3 def $q3 ; CHECK-NEXT: ; kill: def $s3 killed $s3 def $q3
; CHECK-NEXT: ld1.s { v16 }[1], [x8] ; CHECK-NEXT: ld1.s { v16 }[1], [x8]
; CHECK-NEXT: add x8, sp, #24 ; CHECK-NEXT: add x8, sp, #24
; CHECK-NEXT: ld1.s { v17 }[1], [x9] ; CHECK-NEXT: ld1.s { v17 }[1], [x9]
; CHECK-NEXT: add x9, sp, #8 ; CHECK-NEXT: add x9, sp, #8
; CHECK-NEXT: mov.s v4[1], v5[0] ; CHECK-NEXT: mov.s v4[1], v5[0]
; CHECK-NEXT: mov.s v0[1], v1[0] ; CHECK-NEXT: mov.s v0[1], v1[0]
; CHECK-NEXT: ld1.s { v16 }[2], [x8] ; CHECK-NEXT: ld1.s { v16 }[2], [x8]
; CHECK-NEXT: add x8, sp, #28 ; CHECK-NEXT: add x8, sp, #28
; CHECK-NEXT: ld1.s { v17 }[2], [x9] ; CHECK-NEXT: ld1.s { v17 }[2], [x9]
; CHECK-NEXT: add x9, sp, #12
; CHECK-NEXT: mov.s v4[2], v6[0] ; CHECK-NEXT: mov.s v4[2], v6[0]
; CHECK-NEXT: add x9, sp, #12
; CHECK-NEXT: mov.s v0[2], v2[0] ; CHECK-NEXT: mov.s v0[2], v2[0]
; CHECK-NEXT: ld1.s { v16 }[3], [x8]
; CHECK-NEXT: ld1.s { v17 }[3], [x9]
; CHECK-NEXT: mov.s v4[3], v7[0] ; CHECK-NEXT: mov.s v4[3], v7[0]
; CHECK-NEXT: ld1.s { v16 }[3], [x8]
; CHECK-NEXT: mov.s v0[3], v3[0] ; CHECK-NEXT: mov.s v0[3], v3[0]
; CHECK-NEXT: mov d1, v16[1] ; CHECK-NEXT: ld1.s { v17 }[3], [x9]
; CHECK-NEXT: mov d2, v17[1] ; CHECK-NEXT: mov d1, v4[1]
; CHECK-NEXT: mov d3, v4[1] ; CHECK-NEXT: mov d2, v0[1]
; CHECK-NEXT: mov d5, v0[1] ; CHECK-NEXT: mov d3, v16[1]
; CHECK-NEXT: stnp d16, d1, [x0, #48] ; CHECK-NEXT: mov d5, v17[1]
; CHECK-NEXT: stnp d4, d1, [x0, #16]
; CHECK-NEXT: ldr s1, [sp, #32] ; CHECK-NEXT: ldr s1, [sp, #32]
; CHECK-NEXT: stnp d17, d2, [x0, #32] ; CHECK-NEXT: stnp d0, d2, [x0]
; CHECK-NEXT: stnp d4, d3, [x0, #16] ; CHECK-NEXT: stnp d16, d3, [x0, #48]
; CHECK-NEXT: stnp d0, d5, [x0] ; CHECK-NEXT: stnp d17, d5, [x0, #32]
; CHECK-NEXT: str s1, [x0, #64] ; CHECK-NEXT: str s1, [x0, #64]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
store <17 x float> %v, <17 x float>* %ptr, align 4, !nontemporal !0 store <17 x float> %v, <17 x float>* %ptr, align 4, !nontemporal !0
ret void ret void
} }
define void @test_stnp_v16i32_invalid_offset(<16 x i32> %v, <16 x i32>* %ptr) { define void @test_stnp_v16i32_invalid_offset(<16 x i32> %v, <16 x i32>* %ptr) {
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/pow.ll

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov s0, v0.s[2] ; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v1.s[2], v0.s[0] ; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov s0, v0.s[3]
; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
; CHECK-NEXT: fmov s1, #0.25000000 ; CHECK-NEXT: fmov s1, #0.25000000
; CHECK-NEXT: mov s0, v0.s[3]
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: mov v1.s[3], v0.s[0] ; CHECK-NEXT: mov v1.s[3], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Show All 28 Lines

llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -consider-local-interval-cost -mtriple=aarch64-arm-none-eabi < %s | FileCheck %s ; RUN: llc -consider-local-interval-cost -mtriple=aarch64-arm-none-eabi < %s | FileCheck %s
@A = external dso_local local_unnamed_addr global [8 x [8 x i64]], align 8 @A = external dso_local local_unnamed_addr global [8 x [8 x i64]], align 8
@B = external dso_local local_unnamed_addr global [8 x [8 x i64]], align 8 @B = external dso_local local_unnamed_addr global [8 x [8 x i64]], align 8
@C = external dso_local local_unnamed_addr global [8 x [8 x i64]], align 8 @C = external dso_local local_unnamed_addr global [8 x [8 x i64]], align 8
define dso_local void @run_test() local_unnamed_addr #0 { define dso_local void @run_test() local_unnamed_addr #0 {
; CHECK-LABEL: run_test: ; CHECK-LABEL: run_test:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #96 ; CHECK-NEXT: sub sp, sp, #80
; CHECK-NEXT: stp d15, d14, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: stp d15, d14, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: stp d13, d12, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: stp d13, d12, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: stp d11, d10, [sp, #64] // 16-byte Folded Spill ; CHECK-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: stp d9, d8, [sp, #80] // 16-byte Folded Spill ; CHECK-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 96 ; CHECK-NEXT: .cfi_def_cfa_offset 80
; CHECK-NEXT: .cfi_offset b8, -8 ; CHECK-NEXT: .cfi_offset b8, -8
; CHECK-NEXT: .cfi_offset b9, -16 ; CHECK-NEXT: .cfi_offset b9, -16
; CHECK-NEXT: .cfi_offset b10, -24 ; CHECK-NEXT: .cfi_offset b10, -24
; CHECK-NEXT: .cfi_offset b11, -32 ; CHECK-NEXT: .cfi_offset b11, -32
; CHECK-NEXT: .cfi_offset b12, -40 ; CHECK-NEXT: .cfi_offset b12, -40
; CHECK-NEXT: .cfi_offset b13, -48 ; CHECK-NEXT: .cfi_offset b13, -48
; CHECK-NEXT: .cfi_offset b14, -56 ; CHECK-NEXT: .cfi_offset b14, -56
; CHECK-NEXT: .cfi_offset b15, -64 ; CHECK-NEXT: .cfi_offset b15, -64
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: adrp x10, B+48 ; CHECK-NEXT: adrp x10, B+48
; CHECK-NEXT: adrp x11, A ; CHECK-NEXT: adrp x11, A
; CHECK-NEXT: mov x8, xzr ; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: mov x9, xzr ; CHECK-NEXT: mov x9, xzr
; CHECK-NEXT: add x10, x10, :lo12:B+48 ; CHECK-NEXT: add x10, x10, :lo12:B+48
; CHECK-NEXT: add x11, x11, :lo12:A ; CHECK-NEXT: add x11, x11, :lo12:A
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: // implicit-def: $q1
; CHECK-NEXT: // implicit-def: $q2 ; CHECK-NEXT: // implicit-def: $q2
; CHECK-NEXT: // implicit-def: $q3 ; CHECK-NEXT: // implicit-def: $q3
; CHECK-NEXT: // implicit-def: $q4 ; CHECK-NEXT: // implicit-def: $q4
; CHECK-NEXT: // implicit-def: $q5 ; CHECK-NEXT: // implicit-def: $q5
; CHECK-NEXT: // implicit-def: $q6 ; CHECK-NEXT: // implicit-def: $q6
; CHECK-NEXT: // implicit-def: $q7 ; CHECK-NEXT: // implicit-def: $q7
; CHECK-NEXT: // implicit-def: $q16 ; CHECK-NEXT: // implicit-def: $q16
; CHECK-NEXT: // implicit-def: $q17 ; CHECK-NEXT: // implicit-def: $q17
Show All 12 Lines
; CHECK-NEXT: // implicit-def: $q30 ; CHECK-NEXT: // implicit-def: $q30
; CHECK-NEXT: // implicit-def: $q31 ; CHECK-NEXT: // implicit-def: $q31
; CHECK-NEXT: // implicit-def: $q8 ; CHECK-NEXT: // implicit-def: $q8
; CHECK-NEXT: // implicit-def: $q9 ; CHECK-NEXT: // implicit-def: $q9
; CHECK-NEXT: // implicit-def: $q10 ; CHECK-NEXT: // implicit-def: $q10
; CHECK-NEXT: // implicit-def: $q11 ; CHECK-NEXT: // implicit-def: $q11
; CHECK-NEXT: // implicit-def: $q12 ; CHECK-NEXT: // implicit-def: $q12
; CHECK-NEXT: // implicit-def: $q13 ; CHECK-NEXT: // implicit-def: $q13
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: // implicit-def: $q0
; CHECK-NEXT: // kill: killed $q0
; CHECK-NEXT: .LBB0_1: // %for.cond1.preheader ; CHECK-NEXT: .LBB0_1: // %for.cond1.preheader
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: mov x12, xzr ; CHECK-NEXT: mov x12, xzr
; CHECK-NEXT: ldr q14, [x8] ; CHECK-NEXT: ldr q14, [x8]
; CHECK-NEXT: ldr q15, [x10], #64 ; CHECK-NEXT: ldr q15, [x10], #64
; CHECK-NEXT: add x15, x11, x8 ; CHECK-NEXT: add x15, x11, x8
; CHECK-NEXT: add x9, x9, #1 ; CHECK-NEXT: add x9, x9, #1
; CHECK-NEXT: ldr x13, [x12]
; CHECK-NEXT: fmov x14, d14
; CHECK-NEXT: ldr q0, [x12] ; CHECK-NEXT: ldr q0, [x12]
; CHECK-NEXT: fmov x13, d14 ; CHECK-NEXT: fmov x12, d15
; CHECK-NEXT: ldr x12, [x12] ; CHECK-NEXT: mov x17, v14.d[1]
; CHECK-NEXT: fmov x0, d15
; CHECK-NEXT: mov x14, v14.d[1]
; CHECK-NEXT: ldr x15, [x15, #128] ; CHECK-NEXT: ldr x15, [x15, #128]
; CHECK-NEXT: fmov x16, d0 ; CHECK-NEXT: mul x16, x14, x13
; CHECK-NEXT: mul x17, x13, x12 ; CHECK-NEXT: mov x2, v15.d[1]
; CHECK-NEXT: mov x18, v0.d[1] ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: mul x4, x0, x12 ; CHECK-NEXT: mul x18, x12, x13
; CHECK-NEXT: mul x1, x16, x12 ; CHECK-NEXT: mul x1, x17, x13
; CHECK-NEXT: mul x3, x14, x12 ; CHECK-NEXT: mul x4, x14, x15
; CHECK-NEXT: fmov d0, x17 ; CHECK-NEXT: fmov d14, x16
; CHECK-NEXT: mul x5, x13, x15 ; CHECK-NEXT: mul x3, x0, x13
; CHECK-NEXT: mov x17, v15.d[1] ; CHECK-NEXT: mov x16, v0.d[1]
; CHECK-NEXT: fmov d15, x4 ; CHECK-NEXT: fmov d0, x18
; CHECK-NEXT: fmov d14, x1 ; CHECK-NEXT: mul x18, x2, x13
; CHECK-NEXT: mul x1, x18, x12
; CHECK-NEXT: ldr x2, [x8], #8
; CHECK-NEXT: mov v0.d[1], x3
; CHECK-NEXT: mul x3, x16, x15
; CHECK-NEXT: mul x12, x17, x12
; CHECK-NEXT: fmov d1, x5
; CHECK-NEXT: mul x13, x13, x2
; CHECK-NEXT: cmp x8, #64
; CHECK-NEXT: mov v14.d[1], x1 ; CHECK-NEXT: mov v14.d[1], x1
; CHECK-NEXT: mul x1, x14, x15 ; CHECK-NEXT: mul x13, x16, x13
; CHECK-NEXT: add v12.2d, v12.2d, v0.2d ; CHECK-NEXT: fmov d15, x3
; CHECK-NEXT: mul x14, x14, x2 ; CHECK-NEXT: mul x3, x17, x15
; CHECK-NEXT: mov v15.d[1], x12 ; CHECK-NEXT: add v12.2d, v12.2d, v14.2d
; CHECK-NEXT: mul x12, x18, x2 ; CHECK-NEXT: fmov d14, x4
; CHECK-NEXT: mul x18, x18, x15 ; CHECK-NEXT: ldr x1, [x8], #8
; CHECK-NEXT: fmov d0, x3 ; CHECK-NEXT: mov v15.d[1], x13
; CHECK-NEXT: mov v1.d[1], x1 ; CHECK-NEXT: mul x13, x0, x15
; CHECK-NEXT: mul x16, x16, x2 ; CHECK-NEXT: mov v14.d[1], x3
; CHECK-NEXT: mul x3, x0, x15 ; CHECK-NEXT: mul x3, x12, x15
; CHECK-NEXT: add v10.2d, v10.2d, v15.2d
; CHECK-NEXT: fmov d15, x13
; CHECK-NEXT: mov v0.d[1], x18 ; CHECK-NEXT: mov v0.d[1], x18
; CHECK-NEXT: mul x13, x0, x2 ; CHECK-NEXT: mul x14, x14, x1
; CHECK-NEXT: add v29.2d, v29.2d, v1.2d ; CHECK-NEXT: add v13.2d, v13.2d, v15.2d
; CHECK-NEXT: mul x15, x17, x15 ; CHECK-NEXT: mul x17, x17, x1
; CHECK-NEXT: mov v15.d[1], x14 ; CHECK-NEXT: add v11.2d, v11.2d, v15.2d
; CHECK-NEXT: fmov d1, x16 ; CHECK-NEXT: mul x18, x16, x1
; CHECK-NEXT: add v28.2d, v28.2d, v0.2d ; CHECK-NEXT: fmov d15, x13
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: mul x13, x16, x15
; CHECK-NEXT: add v13.2d, v13.2d, v14.2d ; CHECK-NEXT: mul x15, x2, x15
; CHECK-NEXT: mov v1.d[1], x12 ; CHECK-NEXT: cmp x8, #64
; CHECK-NEXT: mul x12, x17, x2 ; CHECK-NEXT: add v10.2d, v10.2d, v0.2d
; CHECK-NEXT: add v0.2d, v0.2d, v15.2d ; CHECK-NEXT: fmov d0, x3
; CHECK-NEXT: add v11.2d, v11.2d, v14.2d ; CHECK-NEXT: add v29.2d, v29.2d, v14.2d
; CHECK-NEXT: fmov d14, x3 ; CHECK-NEXT: mul x16, x0, x1
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: fmov d14, x14
; CHECK-NEXT: fmov d0, x13 ; CHECK-NEXT: mul x12, x12, x1
; CHECK-NEXT: add v9.2d, v9.2d, v1.2d ; CHECK-NEXT: mov v0.d[1], x15
; CHECK-NEXT: mov v14.d[1], x15 ; CHECK-NEXT: mov v15.d[1], x13
; CHECK-NEXT: mov v0.d[1], x12 ; CHECK-NEXT: mul x13, x2, x1
; CHECK-NEXT: add v31.2d, v31.2d, v1.2d ; CHECK-NEXT: add v27.2d, v27.2d, v0.2d
; CHECK-NEXT: add v26.2d, v26.2d, v1.2d ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: add v23.2d, v23.2d, v1.2d ; CHECK-NEXT: mov v14.d[1], x17
; CHECK-NEXT: add v21.2d, v21.2d, v1.2d ; CHECK-NEXT: add v28.2d, v28.2d, v15.2d
; CHECK-NEXT: add v19.2d, v19.2d, v1.2d ; CHECK-NEXT: fmov d15, x16
; CHECK-NEXT: add v17.2d, v17.2d, v1.2d ; CHECK-NEXT: add v0.2d, v0.2d, v14.2d
; CHECK-NEXT: add v7.2d, v7.2d, v1.2d ; CHECK-NEXT: add v8.2d, v8.2d, v14.2d
; CHECK-NEXT: add v5.2d, v5.2d, v1.2d ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: add v3.2d, v3.2d, v1.2d ; CHECK-NEXT: fmov d0, x12
; CHECK-NEXT: add v2.2d, v2.2d, v1.2d ; CHECK-NEXT: mov v15.d[1], x18
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: add v25.2d, v25.2d, v14.2d
; CHECK-NEXT: add v27.2d, v27.2d, v14.2d ; CHECK-NEXT: mov v0.d[1], x13
; CHECK-NEXT: add v8.2d, v8.2d, v15.2d ; CHECK-NEXT: add v22.2d, v22.2d, v14.2d
; CHECK-NEXT: add v25.2d, v25.2d, v15.2d ; CHECK-NEXT: add v18.2d, v18.2d, v14.2d
; CHECK-NEXT: add v22.2d, v22.2d, v15.2d ; CHECK-NEXT: add v6.2d, v6.2d, v14.2d
; CHECK-NEXT: add v18.2d, v18.2d, v15.2d ; CHECK-NEXT: add v9.2d, v9.2d, v15.2d
; CHECK-NEXT: add v6.2d, v6.2d, v15.2d ; CHECK-NEXT: add v31.2d, v31.2d, v15.2d
; CHECK-NEXT: add v26.2d, v26.2d, v15.2d
; CHECK-NEXT: add v23.2d, v23.2d, v15.2d
; CHECK-NEXT: add v21.2d, v21.2d, v15.2d
; CHECK-NEXT: add v19.2d, v19.2d, v15.2d
; CHECK-NEXT: add v17.2d, v17.2d, v15.2d
; CHECK-NEXT: add v7.2d, v7.2d, v15.2d
; CHECK-NEXT: add v5.2d, v5.2d, v15.2d
; CHECK-NEXT: add v3.2d, v3.2d, v15.2d
; CHECK-NEXT: add v2.2d, v2.2d, v15.2d
; CHECK-NEXT: add v30.2d, v30.2d, v0.2d ; CHECK-NEXT: add v30.2d, v30.2d, v0.2d
; CHECK-NEXT: add v24.2d, v24.2d, v0.2d ; CHECK-NEXT: add v24.2d, v24.2d, v0.2d
; CHECK-NEXT: add v20.2d, v20.2d, v0.2d ; CHECK-NEXT: add v20.2d, v20.2d, v0.2d
; CHECK-NEXT: add v16.2d, v16.2d, v0.2d ; CHECK-NEXT: add v16.2d, v16.2d, v0.2d
; CHECK-NEXT: add v4.2d, v4.2d, v0.2d ; CHECK-NEXT: add v4.2d, v4.2d, v0.2d
; CHECK-NEXT: add v1.2d, v1.2d, v0.2d ; CHECK-NEXT: add v1.2d, v1.2d, v0.2d
; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
; CHECK-NEXT: b.ne .LBB0_1 ; CHECK-NEXT: b.ne .LBB0_1
; CHECK-NEXT: // %bb.2: // %for.cond.cleanup ; CHECK-NEXT: // %bb.2: // %for.cond.cleanup
; CHECK-NEXT: adrp x8, C ; CHECK-NEXT: adrp x8, C
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: add x8, x8, :lo12:C ; CHECK-NEXT: add x8, x8, :lo12:C
; CHECK-NEXT: ldp d15, d14, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldp d15, d14, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: stp q13, q12, [x8] ; CHECK-NEXT: stp q13, q12, [x8]
; CHECK-NEXT: stp q11, q10, [x8, #32] ; CHECK-NEXT: stp q11, q10, [x8, #32]
; CHECK-NEXT: stp q9, q8, [x8, #64] ; CHECK-NEXT: stp q9, q8, [x8, #64]
; CHECK-NEXT: ldp d9, d8, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: stp q0, q2, [x8, #464]
; CHECK-NEXT: ldp d11, d10, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: stp q31, q30, [x8, #96] ; CHECK-NEXT: stp q31, q30, [x8, #96]
; CHECK-NEXT: ldp d13, d12, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: stp q29, q28, [x8, #144] ; CHECK-NEXT: stp q29, q28, [x8, #144]
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldp d13, d12, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: stp q27, q26, [x8, #176] ; CHECK-NEXT: stp q27, q26, [x8, #176]
; CHECK-NEXT: str q25, [x8, #208] ; CHECK-NEXT: str q25, [x8, #208]
; CHECK-NEXT: stp q24, q23, [x8, #240] ; CHECK-NEXT: stp q24, q23, [x8, #240]
; CHECK-NEXT: stp q22, q21, [x8, #272] ; CHECK-NEXT: stp q22, q21, [x8, #272]
; CHECK-NEXT: stp q20, q19, [x8, #304] ; CHECK-NEXT: stp q20, q19, [x8, #304]
; CHECK-NEXT: stp q18, q17, [x8, #336] ; CHECK-NEXT: stp q18, q17, [x8, #336]
; CHECK-NEXT: stp q16, q7, [x8, #368] ; CHECK-NEXT: stp q16, q7, [x8, #368]
; CHECK-NEXT: stp q6, q5, [x8, #400] ; CHECK-NEXT: stp q6, q5, [x8, #400]
; CHECK-NEXT: stp q4, q3, [x8, #432] ; CHECK-NEXT: stp q4, q3, [x8, #432]
; CHECK-NEXT: str q0, [x8, #496] ; CHECK-NEXT: stp q0, q2, [x8, #464]
; CHECK-NEXT: add sp, sp, #96 ; CHECK-NEXT: str q1, [x8, #496]
; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
br label %for.cond1.preheader br label %for.cond1.preheader
for.cond1.preheader: ; preds = %for.cond1.preheader, %entry for.cond1.preheader: ; preds = %for.cond1.preheader, %entry
%0 = phi <2 x i64> [ undef, %entry ], [ %118, %for.cond1.preheader ] %0 = phi <2 x i64> [ undef, %entry ], [ %118, %for.cond1.preheader ]
%1 = phi <2 x i64> [ undef, %entry ], [ %116, %for.cond1.preheader ] %1 = phi <2 x i64> [ undef, %entry ], [ %116, %for.cond1.preheader ]
%2 = phi <2 x i64> [ zeroinitializer, %entry ], [ %114, %for.cond1.preheader ] %2 = phi <2 x i64> [ zeroinitializer, %entry ], [ %114, %for.cond1.preheader ]
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llvm/test/CodeGen/AArch64/reduce-and.ll

Show All 15 Lines; GISEL-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a) %or_result = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
ret i1 %or_result ret i1 %or_result
} }
define i1 @test_redand_v2i1(<2 x i1> %a) { define i1 @test_redand_v2i1(<2 x i1> %a) {
; CHECK-LABEL: test_redand_v2i1: ; CHECK-LABEL: test_redand_v2i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: and w8, w9, w8 ; CHECK-NEXT: and w8, w9, w8
; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redand_v2i1: ; GISEL-LABEL: test_redand_v2i1:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov s1, v0.s[1] ; GISEL-NEXT: mov s1, v0.s[1]
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define i1 @test_redand_v8i1(<8 x i1> %a) { define i1 @test_redand_v8i1(<8 x i1> %a) {
; CHECK-LABEL: test_redand_v8i1: ; CHECK-LABEL: test_redand_v8i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0] ; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3] ; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: umov w13, v0.b[5]
; CHECK-NEXT: and w8, w9, w8 ; CHECK-NEXT: and w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[6] ; CHECK-NEXT: umov w9, v0.b[4]
; CHECK-NEXT: and w8, w8, w10 ; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[7] ; CHECK-NEXT: umov w10, v0.b[5]
; CHECK-NEXT: and w8, w8, w11 ; CHECK-NEXT: and w8, w8, w11
; CHECK-NEXT: and w8, w8, w12 ; CHECK-NEXT: umov w11, v0.b[6]
; CHECK-NEXT: and w8, w8, w13
; CHECK-NEXT: and w8, w8, w9 ; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[7]
; CHECK-NEXT: and w8, w8, w10 ; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: and w8, w8, w11
; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redand_v8i1: ; GISEL-LABEL: test_redand_v8i1:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov b1, v0.b[1] ; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2] ; GISEL-NEXT: mov b2, v0.b[2]
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define i1 @test_redand_v16i1(<16 x i1> %a) { define i1 @test_redand_v16i1(<16 x i1> %a) {
; CHECK-LABEL: test_redand_v16i1: ; CHECK-LABEL: test_redand_v16i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0] ; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: and w8, w9, w8 ; CHECK-NEXT: and w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[3]
; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[4]
; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[5] ; CHECK-NEXT: umov w9, v0.b[5]
; CHECK-NEXT: and w8, w8, w10 ; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[6] ; CHECK-NEXT: umov w10, v0.b[6]
; CHECK-NEXT: and w8, w8, w11
; CHECK-NEXT: umov w11, v0.b[7]
; CHECK-NEXT: and w8, w8, w12
; CHECK-NEXT: and w8, w8, w9 ; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[7]
; CHECK-NEXT: and w8, w8, w10 ; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: and w8, w8, w11 ; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redand_v16i1: ; GISEL-LABEL: test_redand_v16i1:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: mov b1, v0.b[1] ; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2] ; GISEL-NEXT: mov b2, v0.b[2]
; GISEL-NEXT: mov b3, v0.b[3] ; GISEL-NEXT: mov b3, v0.b[3]
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define i8 @test_redand_v8i8(<8 x i8> %a) { define i8 @test_redand_v8i8(<8 x i8> %a) {
; CHECK-LABEL: test_redand_v8i8: ; CHECK-LABEL: test_redand_v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0] ; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3] ; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: umov w13, v0.b[5]
; CHECK-NEXT: and w8, w9, w8 ; CHECK-NEXT: and w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[6] ; CHECK-NEXT: umov w9, v0.b[4]
; CHECK-NEXT: and w8, w8, w10 ; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[7] ; CHECK-NEXT: umov w10, v0.b[5]
; CHECK-NEXT: and w8, w8, w11 ; CHECK-NEXT: and w8, w8, w11
; CHECK-NEXT: and w8, w8, w12 ; CHECK-NEXT: umov w11, v0.b[6]
; CHECK-NEXT: and w8, w8, w13
; CHECK-NEXT: and w8, w8, w9 ; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: and w0, w8, w10 ; CHECK-NEXT: umov w9, v0.b[7]
; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: and w8, w8, w11
; CHECK-NEXT: and w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redand_v8i8: ; GISEL-LABEL: test_redand_v8i8:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov b1, v0.b[1] ; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2] ; GISEL-NEXT: mov b2, v0.b[2]
; GISEL-NEXT: mov b3, v0.b[3] ; GISEL-NEXT: mov b3, v0.b[3]
Show All 24 Lines
define i8 @test_redand_v16i8(<16 x i8> %a) { define i8 @test_redand_v16i8(<16 x i8> %a) {
; CHECK-LABEL: test_redand_v16i8: ; CHECK-LABEL: test_redand_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0] ; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: and w8, w9, w8 ; CHECK-NEXT: and w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[3]
; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[4]
; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[5] ; CHECK-NEXT: umov w9, v0.b[5]
; CHECK-NEXT: and w8, w8, w10 ; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[6] ; CHECK-NEXT: umov w10, v0.b[6]
; CHECK-NEXT: and w8, w8, w11
; CHECK-NEXT: umov w11, v0.b[7]
; CHECK-NEXT: and w8, w8, w12
; CHECK-NEXT: and w8, w8, w9 ; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[7]
; CHECK-NEXT: and w8, w8, w10 ; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: and w0, w8, w11 ; CHECK-NEXT: and w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redand_v16i8: ; GISEL-LABEL: test_redand_v16i8:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: and v0.8b, v0.8b, v1.8b ; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov b1, v0.b[1] ; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2] ; GISEL-NEXT: mov b2, v0.b[2]
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; CHECK-LABEL: test_redand_v32i8: ; CHECK-LABEL: test_redand_v32i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0] ; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: and w8, w9, w8 ; CHECK-NEXT: and w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[3]
; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[4]
; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[5] ; CHECK-NEXT: umov w9, v0.b[5]
; CHECK-NEXT: and w8, w8, w10 ; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[6] ; CHECK-NEXT: umov w10, v0.b[6]
; CHECK-NEXT: and w8, w8, w11
; CHECK-NEXT: umov w11, v0.b[7]
; CHECK-NEXT: and w8, w8, w12
; CHECK-NEXT: and w8, w8, w9 ; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[7]
; CHECK-NEXT: and w8, w8, w10 ; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: and w0, w8, w11 ; CHECK-NEXT: and w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redand_v32i8: ; GISEL-LABEL: test_redand_v32i8:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: and v0.16b, v0.16b, v1.16b ; GISEL-NEXT: and v0.16b, v0.16b, v1.16b
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: and v0.8b, v0.8b, v1.8b ; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov b1, v0.b[1] ; GISEL-NEXT: mov b1, v0.b[1]
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define i16 @test_redand_v8i16(<8 x i16> %a) { define i16 @test_redand_v8i16(<8 x i16> %a) {
; CHECK-LABEL: test_redand_v8i16: ; CHECK-LABEL: test_redand_v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.h[1] ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: umov w9, v0.h[0] ; CHECK-NEXT: umov w9, v0.h[0]
; CHECK-NEXT: umov w10, v0.h[2] ; CHECK-NEXT: umov w10, v0.h[2]
; CHECK-NEXT: umov w11, v0.h[3]
; CHECK-NEXT: and w8, w9, w8 ; CHECK-NEXT: and w8, w9, w8
; CHECK-NEXT: umov w9, v0.h[3]
; CHECK-NEXT: and w8, w8, w10 ; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: and w0, w8, w11 ; CHECK-NEXT: and w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redand_v8i16: ; GISEL-LABEL: test_redand_v8i16:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: and v0.8b, v0.8b, v1.8b ; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov h1, v0.h[1] ; GISEL-NEXT: mov h1, v0.h[1]
; GISEL-NEXT: mov h2, v0.h[2] ; GISEL-NEXT: mov h2, v0.h[2]
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; CHECK-LABEL: test_redand_v16i16: ; CHECK-LABEL: test_redand_v16i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.h[1] ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: umov w9, v0.h[0] ; CHECK-NEXT: umov w9, v0.h[0]
; CHECK-NEXT: umov w10, v0.h[2] ; CHECK-NEXT: umov w10, v0.h[2]
; CHECK-NEXT: umov w11, v0.h[3]
; CHECK-NEXT: and w8, w9, w8 ; CHECK-NEXT: and w8, w9, w8
; CHECK-NEXT: umov w9, v0.h[3]
; CHECK-NEXT: and w8, w8, w10 ; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: and w0, w8, w11 ; CHECK-NEXT: and w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redand_v16i16: ; GISEL-LABEL: test_redand_v16i16:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: and v0.16b, v0.16b, v1.16b ; GISEL-NEXT: and v0.16b, v0.16b, v1.16b
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: and v0.8b, v0.8b, v1.8b ; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov h1, v0.h[1] ; GISEL-NEXT: mov h1, v0.h[1]
Show All 10 Lines; GISEL-NEXT: ret
%and_result = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %a) %and_result = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %a)
ret i16 %and_result ret i16 %and_result
} }
define i32 @test_redand_v2i32(<2 x i32> %a) { define i32 @test_redand_v2i32(<2 x i32> %a) {
; CHECK-LABEL: test_redand_v2i32: ; CHECK-LABEL: test_redand_v2i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: and w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redand_v2i32: ; GISEL-LABEL: test_redand_v2i32:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov s1, v0.s[1] ; GISEL-NEXT: mov s1, v0.s[1]
; GISEL-NEXT: fmov w8, s0 ; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1 ; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: and w0, w8, w9 ; GISEL-NEXT: and w0, w8, w9
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%and_result = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %a) %and_result = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %a)
ret i32 %and_result ret i32 %and_result
} }
define i32 @test_redand_v4i32(<4 x i32> %a) { define i32 @test_redand_v4i32(<4 x i32> %a) {
; CHECK-LABEL: test_redand_v4i32: ; CHECK-LABEL: test_redand_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: and w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redand_v4i32: ; GISEL-LABEL: test_redand_v4i32:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: and v0.8b, v0.8b, v1.8b ; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov s1, v0.s[1] ; GISEL-NEXT: mov s1, v0.s[1]
; GISEL-NEXT: fmov w8, s0 ; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1 ; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: and w0, w8, w9 ; GISEL-NEXT: and w0, w8, w9
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%and_result = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %a) %and_result = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %a)
ret i32 %and_result ret i32 %and_result
} }
define i32 @test_redand_v8i32(<8 x i32> %a) { define i32 @test_redand_v8i32(<8 x i32> %a) {
; CHECK-LABEL: test_redand_v8i32: ; CHECK-LABEL: test_redand_v8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: and w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redand_v8i32: ; GISEL-LABEL: test_redand_v8i32:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: and v0.16b, v0.16b, v1.16b ; GISEL-NEXT: and v0.16b, v0.16b, v1.16b
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: and v0.8b, v0.8b, v1.8b ; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
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llvm/test/CodeGen/AArch64/reduce-or.ll

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%or_result = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %a) %or_result = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %a)
ret i1 %or_result ret i1 %or_result
} }
define i1 @test_redor_v2i1(<2 x i1> %a) { define i1 @test_redor_v2i1(<2 x i1> %a) {
; CHECK-LABEL: test_redor_v2i1: ; CHECK-LABEL: test_redor_v2i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: orr w8, w9, w8 ; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redor_v2i1: ; GISEL-LABEL: test_redor_v2i1:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov s1, v0.s[1] ; GISEL-NEXT: mov s1, v0.s[1]
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define i1 @test_redor_v8i1(<8 x i1> %a) { define i1 @test_redor_v8i1(<8 x i1> %a) {
; CHECK-LABEL: test_redor_v8i1: ; CHECK-LABEL: test_redor_v8i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0] ; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3] ; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: umov w13, v0.b[5]
; CHECK-NEXT: orr w8, w9, w8 ; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[6] ; CHECK-NEXT: umov w9, v0.b[4]
; CHECK-NEXT: orr w8, w8, w10 ; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[7] ; CHECK-NEXT: umov w10, v0.b[5]
; CHECK-NEXT: orr w8, w8, w11 ; CHECK-NEXT: orr w8, w8, w11
; CHECK-NEXT: orr w8, w8, w12 ; CHECK-NEXT: umov w11, v0.b[6]
; CHECK-NEXT: orr w8, w8, w13
; CHECK-NEXT: orr w8, w8, w9 ; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[7]
; CHECK-NEXT: orr w8, w8, w10 ; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: orr w8, w8, w11
; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redor_v8i1: ; GISEL-LABEL: test_redor_v8i1:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov b1, v0.b[1] ; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2] ; GISEL-NEXT: mov b2, v0.b[2]
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define i1 @test_redor_v16i1(<16 x i1> %a) { define i1 @test_redor_v16i1(<16 x i1> %a) {
; CHECK-LABEL: test_redor_v16i1: ; CHECK-LABEL: test_redor_v16i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0] ; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: orr w8, w9, w8 ; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[3]
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[4]
; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[5] ; CHECK-NEXT: umov w9, v0.b[5]
; CHECK-NEXT: orr w8, w8, w10 ; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[6] ; CHECK-NEXT: umov w10, v0.b[6]
; CHECK-NEXT: orr w8, w8, w11
; CHECK-NEXT: umov w11, v0.b[7]
; CHECK-NEXT: orr w8, w8, w12
; CHECK-NEXT: orr w8, w8, w9 ; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[7]
; CHECK-NEXT: orr w8, w8, w10 ; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: orr w8, w8, w11 ; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redor_v16i1: ; GISEL-LABEL: test_redor_v16i1:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: mov b1, v0.b[1] ; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2] ; GISEL-NEXT: mov b2, v0.b[2]
; GISEL-NEXT: mov b3, v0.b[3] ; GISEL-NEXT: mov b3, v0.b[3]
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define i8 @test_redor_v8i8(<8 x i8> %a) { define i8 @test_redor_v8i8(<8 x i8> %a) {
; CHECK-LABEL: test_redor_v8i8: ; CHECK-LABEL: test_redor_v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0] ; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3] ; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: umov w13, v0.b[5]
; CHECK-NEXT: orr w8, w9, w8 ; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[6] ; CHECK-NEXT: umov w9, v0.b[4]
; CHECK-NEXT: orr w8, w8, w10 ; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[7] ; CHECK-NEXT: umov w10, v0.b[5]
; CHECK-NEXT: orr w8, w8, w11 ; CHECK-NEXT: orr w8, w8, w11
; CHECK-NEXT: orr w8, w8, w12 ; CHECK-NEXT: umov w11, v0.b[6]
; CHECK-NEXT: orr w8, w8, w13
; CHECK-NEXT: orr w8, w8, w9 ; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: orr w0, w8, w10 ; CHECK-NEXT: umov w9, v0.b[7]
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: orr w8, w8, w11
; CHECK-NEXT: orr w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redor_v8i8: ; GISEL-LABEL: test_redor_v8i8:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov b1, v0.b[1] ; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2] ; GISEL-NEXT: mov b2, v0.b[2]
; GISEL-NEXT: mov b3, v0.b[3] ; GISEL-NEXT: mov b3, v0.b[3]
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define i8 @test_redor_v16i8(<16 x i8> %a) { define i8 @test_redor_v16i8(<16 x i8> %a) {
; CHECK-LABEL: test_redor_v16i8: ; CHECK-LABEL: test_redor_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0] ; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: orr w8, w9, w8 ; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[3]
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[4]
; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[5] ; CHECK-NEXT: umov w9, v0.b[5]
; CHECK-NEXT: orr w8, w8, w10 ; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[6] ; CHECK-NEXT: umov w10, v0.b[6]
; CHECK-NEXT: orr w8, w8, w11
; CHECK-NEXT: umov w11, v0.b[7]
; CHECK-NEXT: orr w8, w8, w12
; CHECK-NEXT: orr w8, w8, w9 ; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[7]
; CHECK-NEXT: orr w8, w8, w10 ; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: orr w0, w8, w11 ; CHECK-NEXT: orr w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redor_v16i8: ; GISEL-LABEL: test_redor_v16i8:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b ; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov b1, v0.b[1] ; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2] ; GISEL-NEXT: mov b2, v0.b[2]
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; CHECK-LABEL: test_redor_v32i8: ; CHECK-LABEL: test_redor_v32i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0] ; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: orr w8, w9, w8 ; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[3]
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[4]
; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[5] ; CHECK-NEXT: umov w9, v0.b[5]
; CHECK-NEXT: orr w8, w8, w10 ; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[6] ; CHECK-NEXT: umov w10, v0.b[6]
; CHECK-NEXT: orr w8, w8, w11
; CHECK-NEXT: umov w11, v0.b[7]
; CHECK-NEXT: orr w8, w8, w12
; CHECK-NEXT: orr w8, w8, w9 ; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[7]
; CHECK-NEXT: orr w8, w8, w10 ; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: orr w0, w8, w11 ; CHECK-NEXT: orr w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redor_v32i8: ; GISEL-LABEL: test_redor_v32i8:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b ; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b ; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov b1, v0.b[1] ; GISEL-NEXT: mov b1, v0.b[1]
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define i16 @test_redor_v8i16(<8 x i16> %a) { define i16 @test_redor_v8i16(<8 x i16> %a) {
; CHECK-LABEL: test_redor_v8i16: ; CHECK-LABEL: test_redor_v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.h[1] ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: umov w9, v0.h[0] ; CHECK-NEXT: umov w9, v0.h[0]
; CHECK-NEXT: umov w10, v0.h[2] ; CHECK-NEXT: umov w10, v0.h[2]
; CHECK-NEXT: umov w11, v0.h[3]
; CHECK-NEXT: orr w8, w9, w8 ; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: umov w9, v0.h[3]
; CHECK-NEXT: orr w8, w8, w10 ; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: orr w0, w8, w11 ; CHECK-NEXT: orr w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redor_v8i16: ; GISEL-LABEL: test_redor_v8i16:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b ; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov h1, v0.h[1] ; GISEL-NEXT: mov h1, v0.h[1]
; GISEL-NEXT: mov h2, v0.h[2] ; GISEL-NEXT: mov h2, v0.h[2]
Show All 14 Lines
; CHECK-LABEL: test_redor_v16i16: ; CHECK-LABEL: test_redor_v16i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.h[1] ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: umov w9, v0.h[0] ; CHECK-NEXT: umov w9, v0.h[0]
; CHECK-NEXT: umov w10, v0.h[2] ; CHECK-NEXT: umov w10, v0.h[2]
; CHECK-NEXT: umov w11, v0.h[3]
; CHECK-NEXT: orr w8, w9, w8 ; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: umov w9, v0.h[3]
; CHECK-NEXT: orr w8, w8, w10 ; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: orr w0, w8, w11 ; CHECK-NEXT: orr w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redor_v16i16: ; GISEL-LABEL: test_redor_v16i16:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b ; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b ; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov h1, v0.h[1] ; GISEL-NEXT: mov h1, v0.h[1]
Show All 10 Lines; GISEL-NEXT: ret
%or_result = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %a) %or_result = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %a)
ret i16 %or_result ret i16 %or_result
} }
define i32 @test_redor_v2i32(<2 x i32> %a) { define i32 @test_redor_v2i32(<2 x i32> %a) {
; CHECK-LABEL: test_redor_v2i32: ; CHECK-LABEL: test_redor_v2i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: orr w0, w9, w8 ; CHECK-NEXT: orr w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redor_v2i32: ; GISEL-LABEL: test_redor_v2i32:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov s1, v0.s[1] ; GISEL-NEXT: mov s1, v0.s[1]
; GISEL-NEXT: fmov w8, s0 ; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1 ; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: orr w0, w8, w9 ; GISEL-NEXT: orr w0, w8, w9
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%or_result = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %a) %or_result = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %a)
ret i32 %or_result ret i32 %or_result
} }
define i32 @test_redor_v4i32(<4 x i32> %a) { define i32 @test_redor_v4i32(<4 x i32> %a) {
; CHECK-LABEL: test_redor_v4i32: ; CHECK-LABEL: test_redor_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: orr w0, w9, w8 ; CHECK-NEXT: orr w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redor_v4i32: ; GISEL-LABEL: test_redor_v4i32:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b ; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov s1, v0.s[1] ; GISEL-NEXT: mov s1, v0.s[1]
; GISEL-NEXT: fmov w8, s0 ; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1 ; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: orr w0, w8, w9 ; GISEL-NEXT: orr w0, w8, w9
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%or_result = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %a) %or_result = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %a)
ret i32 %or_result ret i32 %or_result
} }
define i32 @test_redor_v8i32(<8 x i32> %a) { define i32 @test_redor_v8i32(<8 x i32> %a) {
; CHECK-LABEL: test_redor_v8i32: ; CHECK-LABEL: test_redor_v8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: orr w0, w9, w8 ; CHECK-NEXT: orr w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redor_v8i32: ; GISEL-LABEL: test_redor_v8i32:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b ; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b ; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
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llvm/test/CodeGen/AArch64/reduce-xor.ll

Show All 14 Lines; GISEL-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %a) %or_result = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %a)
ret i1 %or_result ret i1 %or_result
} }
define i1 @test_redxor_v2i1(<2 x i1> %a) { define i1 @test_redxor_v2i1(<2 x i1> %a) {
; CHECK-LABEL: test_redxor_v2i1: ; CHECK-LABEL: test_redxor_v2i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: eor w8, w9, w8 ; CHECK-NEXT: eor w8, w9, w8
; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redxor_v2i1: ; GISEL-LABEL: test_redxor_v2i1:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov s1, v0.s[1] ; GISEL-NEXT: mov s1, v0.s[1]
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define i1 @test_redxor_v8i1(<8 x i1> %a) { define i1 @test_redxor_v8i1(<8 x i1> %a) {
; CHECK-LABEL: test_redxor_v8i1: ; CHECK-LABEL: test_redxor_v8i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0] ; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3] ; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: umov w13, v0.b[5]
; CHECK-NEXT: eor w8, w9, w8 ; CHECK-NEXT: eor w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[6] ; CHECK-NEXT: umov w9, v0.b[4]
; CHECK-NEXT: eor w8, w8, w10 ; CHECK-NEXT: eor w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[7] ; CHECK-NEXT: umov w10, v0.b[5]
; CHECK-NEXT: eor w8, w8, w11 ; CHECK-NEXT: eor w8, w8, w11
; CHECK-NEXT: eor w8, w8, w12 ; CHECK-NEXT: umov w11, v0.b[6]
; CHECK-NEXT: eor w8, w8, w13
; CHECK-NEXT: eor w8, w8, w9 ; CHECK-NEXT: eor w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[7]
; CHECK-NEXT: eor w8, w8, w10 ; CHECK-NEXT: eor w8, w8, w10
; CHECK-NEXT: eor w8, w8, w11
; CHECK-NEXT: eor w8, w8, w9
; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redxor_v8i1: ; GISEL-LABEL: test_redxor_v8i1:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov b1, v0.b[1] ; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2] ; GISEL-NEXT: mov b2, v0.b[2]
Show All 26 Lines
define i1 @test_redxor_v16i1(<16 x i1> %a) { define i1 @test_redxor_v16i1(<16 x i1> %a) {
; CHECK-LABEL: test_redxor_v16i1: ; CHECK-LABEL: test_redxor_v16i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0] ; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: eor w8, w9, w8 ; CHECK-NEXT: eor w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[3]
; CHECK-NEXT: eor w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[4]
; CHECK-NEXT: eor w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[5] ; CHECK-NEXT: umov w9, v0.b[5]
; CHECK-NEXT: eor w8, w8, w10 ; CHECK-NEXT: eor w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[6] ; CHECK-NEXT: umov w10, v0.b[6]
; CHECK-NEXT: eor w8, w8, w11
; CHECK-NEXT: umov w11, v0.b[7]
; CHECK-NEXT: eor w8, w8, w12
; CHECK-NEXT: eor w8, w8, w9 ; CHECK-NEXT: eor w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[7]
; CHECK-NEXT: eor w8, w8, w10 ; CHECK-NEXT: eor w8, w8, w10
; CHECK-NEXT: eor w8, w8, w11 ; CHECK-NEXT: eor w8, w8, w9
; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redxor_v16i1: ; GISEL-LABEL: test_redxor_v16i1:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: mov b1, v0.b[1] ; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2] ; GISEL-NEXT: mov b2, v0.b[2]
; GISEL-NEXT: mov b3, v0.b[3] ; GISEL-NEXT: mov b3, v0.b[3]
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
define i8 @test_redxor_v8i8(<8 x i8> %a) { define i8 @test_redxor_v8i8(<8 x i8> %a) {
; CHECK-LABEL: test_redxor_v8i8: ; CHECK-LABEL: test_redxor_v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0] ; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3] ; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: umov w13, v0.b[5]
; CHECK-NEXT: eor w8, w9, w8 ; CHECK-NEXT: eor w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[6] ; CHECK-NEXT: umov w9, v0.b[4]
; CHECK-NEXT: eor w8, w8, w10 ; CHECK-NEXT: eor w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[7] ; CHECK-NEXT: umov w10, v0.b[5]
; CHECK-NEXT: eor w8, w8, w11 ; CHECK-NEXT: eor w8, w8, w11
; CHECK-NEXT: eor w8, w8, w12 ; CHECK-NEXT: umov w11, v0.b[6]
; CHECK-NEXT: eor w8, w8, w13
; CHECK-NEXT: eor w8, w8, w9 ; CHECK-NEXT: eor w8, w8, w9
; CHECK-NEXT: eor w0, w8, w10 ; CHECK-NEXT: umov w9, v0.b[7]
; CHECK-NEXT: eor w8, w8, w10
; CHECK-NEXT: eor w8, w8, w11
; CHECK-NEXT: eor w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redxor_v8i8: ; GISEL-LABEL: test_redxor_v8i8:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov b1, v0.b[1] ; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2] ; GISEL-NEXT: mov b2, v0.b[2]
; GISEL-NEXT: mov b3, v0.b[3] ; GISEL-NEXT: mov b3, v0.b[3]
Show All 24 Lines
define i8 @test_redxor_v16i8(<16 x i8> %a) { define i8 @test_redxor_v16i8(<16 x i8> %a) {
; CHECK-LABEL: test_redxor_v16i8: ; CHECK-LABEL: test_redxor_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0] ; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: eor w8, w9, w8 ; CHECK-NEXT: eor w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[3]
; CHECK-NEXT: eor w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[4]
; CHECK-NEXT: eor w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[5] ; CHECK-NEXT: umov w9, v0.b[5]
; CHECK-NEXT: eor w8, w8, w10 ; CHECK-NEXT: eor w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[6] ; CHECK-NEXT: umov w10, v0.b[6]
; CHECK-NEXT: eor w8, w8, w11
; CHECK-NEXT: umov w11, v0.b[7]
; CHECK-NEXT: eor w8, w8, w12
; CHECK-NEXT: eor w8, w8, w9 ; CHECK-NEXT: eor w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[7]
; CHECK-NEXT: eor w8, w8, w10 ; CHECK-NEXT: eor w8, w8, w10
; CHECK-NEXT: eor w0, w8, w11 ; CHECK-NEXT: eor w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redxor_v16i8: ; GISEL-LABEL: test_redxor_v16i8:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b ; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov b1, v0.b[1] ; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2] ; GISEL-NEXT: mov b2, v0.b[2]
Show All 26 Lines
; CHECK-LABEL: test_redxor_v32i8: ; CHECK-LABEL: test_redxor_v32i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0] ; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: eor w8, w9, w8 ; CHECK-NEXT: eor w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[3]
; CHECK-NEXT: eor w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[4]
; CHECK-NEXT: eor w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[5] ; CHECK-NEXT: umov w9, v0.b[5]
; CHECK-NEXT: eor w8, w8, w10 ; CHECK-NEXT: eor w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[6] ; CHECK-NEXT: umov w10, v0.b[6]
; CHECK-NEXT: eor w8, w8, w11
; CHECK-NEXT: umov w11, v0.b[7]
; CHECK-NEXT: eor w8, w8, w12
; CHECK-NEXT: eor w8, w8, w9 ; CHECK-NEXT: eor w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[7]
; CHECK-NEXT: eor w8, w8, w10 ; CHECK-NEXT: eor w8, w8, w10
; CHECK-NEXT: eor w0, w8, w11 ; CHECK-NEXT: eor w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redxor_v32i8: ; GISEL-LABEL: test_redxor_v32i8:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: eor v0.16b, v0.16b, v1.16b ; GISEL-NEXT: eor v0.16b, v0.16b, v1.16b
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b ; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov b1, v0.b[1] ; GISEL-NEXT: mov b1, v0.b[1]
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define i16 @test_redxor_v8i16(<8 x i16> %a) { define i16 @test_redxor_v8i16(<8 x i16> %a) {
; CHECK-LABEL: test_redxor_v8i16: ; CHECK-LABEL: test_redxor_v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.h[1] ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: umov w9, v0.h[0] ; CHECK-NEXT: umov w9, v0.h[0]
; CHECK-NEXT: umov w10, v0.h[2] ; CHECK-NEXT: umov w10, v0.h[2]
; CHECK-NEXT: umov w11, v0.h[3]
; CHECK-NEXT: eor w8, w9, w8 ; CHECK-NEXT: eor w8, w9, w8
; CHECK-NEXT: umov w9, v0.h[3]
; CHECK-NEXT: eor w8, w8, w10 ; CHECK-NEXT: eor w8, w8, w10
; CHECK-NEXT: eor w0, w8, w11 ; CHECK-NEXT: eor w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redxor_v8i16: ; GISEL-LABEL: test_redxor_v8i16:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b ; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov h1, v0.h[1] ; GISEL-NEXT: mov h1, v0.h[1]
; GISEL-NEXT: mov h2, v0.h[2] ; GISEL-NEXT: mov h2, v0.h[2]
Show All 14 Lines
; CHECK-LABEL: test_redxor_v16i16: ; CHECK-LABEL: test_redxor_v16i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.h[1] ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: umov w9, v0.h[0] ; CHECK-NEXT: umov w9, v0.h[0]
; CHECK-NEXT: umov w10, v0.h[2] ; CHECK-NEXT: umov w10, v0.h[2]
; CHECK-NEXT: umov w11, v0.h[3]
; CHECK-NEXT: eor w8, w9, w8 ; CHECK-NEXT: eor w8, w9, w8
; CHECK-NEXT: umov w9, v0.h[3]
; CHECK-NEXT: eor w8, w8, w10 ; CHECK-NEXT: eor w8, w8, w10
; CHECK-NEXT: eor w0, w8, w11 ; CHECK-NEXT: eor w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redxor_v16i16: ; GISEL-LABEL: test_redxor_v16i16:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: eor v0.16b, v0.16b, v1.16b ; GISEL-NEXT: eor v0.16b, v0.16b, v1.16b
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b ; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov h1, v0.h[1] ; GISEL-NEXT: mov h1, v0.h[1]
Show All 10 Lines; GISEL-NEXT: ret
%xor_result = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %a) %xor_result = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %a)
ret i16 %xor_result ret i16 %xor_result
} }
define i32 @test_redxor_v2i32(<2 x i32> %a) { define i32 @test_redxor_v2i32(<2 x i32> %a) {
; CHECK-LABEL: test_redxor_v2i32: ; CHECK-LABEL: test_redxor_v2i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: eor w0, w9, w8 ; CHECK-NEXT: eor w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redxor_v2i32: ; GISEL-LABEL: test_redxor_v2i32:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov s1, v0.s[1] ; GISEL-NEXT: mov s1, v0.s[1]
; GISEL-NEXT: fmov w8, s0 ; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1 ; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: eor w0, w8, w9 ; GISEL-NEXT: eor w0, w8, w9
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%xor_result = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %a) %xor_result = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %a)
ret i32 %xor_result ret i32 %xor_result
} }
define i32 @test_redxor_v4i32(<4 x i32> %a) { define i32 @test_redxor_v4i32(<4 x i32> %a) {
; CHECK-LABEL: test_redxor_v4i32: ; CHECK-LABEL: test_redxor_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: eor w0, w9, w8 ; CHECK-NEXT: eor w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redxor_v4i32: ; GISEL-LABEL: test_redxor_v4i32:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b ; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov s1, v0.s[1] ; GISEL-NEXT: mov s1, v0.s[1]
; GISEL-NEXT: fmov w8, s0 ; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1 ; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: eor w0, w8, w9 ; GISEL-NEXT: eor w0, w8, w9
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%xor_result = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %a) %xor_result = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %a)
ret i32 %xor_result ret i32 %xor_result
} }
define i32 @test_redxor_v8i32(<8 x i32> %a) { define i32 @test_redxor_v8i32(<8 x i32> %a) {
; CHECK-LABEL: test_redxor_v8i32: ; CHECK-LABEL: test_redxor_v8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: eor w0, w9, w8 ; CHECK-NEXT: eor w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_redxor_v8i32: ; GISEL-LABEL: test_redxor_v8i32:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: eor v0.16b, v0.16b, v1.16b ; GISEL-NEXT: eor v0.16b, v0.16b, v1.16b
; GISEL-NEXT: mov d1, v0.d[1] ; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b ; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b
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llvm/test/CodeGen/AArch64/sadd_sat_vec.ll

Show First 20 Lines • Show All 137 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ld1 { v1.b }[0], [x0] ; CHECK-NEXT: ld1 { v1.b }[0], [x0]
; CHECK-NEXT: add x9, x0, #1 ; CHECK-NEXT: add x9, x0, #1
; CHECK-NEXT: ld1 { v0.b }[4], [x8] ; CHECK-NEXT: ld1 { v0.b }[4], [x8]
; CHECK-NEXT: ld1 { v1.b }[4], [x9] ; CHECK-NEXT: ld1 { v1.b }[4], [x9]
; CHECK-NEXT: shl v0.2s, v0.2s, #24 ; CHECK-NEXT: shl v0.2s, v0.2s, #24
; CHECK-NEXT: shl v1.2s, v1.2s, #24 ; CHECK-NEXT: shl v1.2s, v1.2s, #24
; CHECK-NEXT: sqadd v0.2s, v1.2s, v0.2s ; CHECK-NEXT: sqadd v0.2s, v1.2s, v0.2s
; CHECK-NEXT: ushr v0.2s, v0.2s, #24 ; CHECK-NEXT: ushr v0.2s, v0.2s, #24
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: mov w9, v0.s[1]
; CHECK-NEXT: strb w9, [x2] ; CHECK-NEXT: strb w9, [x2, #1]
; CHECK-NEXT: strb w8, [x2, #1] ; CHECK-NEXT: strb w8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i8>, <2 x i8>* %px %x = load <2 x i8>, <2 x i8>* %px
%y = load <2 x i8>, <2 x i8>* %py %y = load <2 x i8>, <2 x i8>* %py
%z = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %x, <2 x i8> %y) %z = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
store <2 x i8> %z, <2 x i8>* %pz store <2 x i8> %z, <2 x i8>* %pz
ret void ret void
} }
Show All 20 Lines
; CHECK-NEXT: ld1 { v1.h }[0], [x0] ; CHECK-NEXT: ld1 { v1.h }[0], [x0]
; CHECK-NEXT: add x9, x0, #2 ; CHECK-NEXT: add x9, x0, #2
; CHECK-NEXT: ld1 { v0.h }[2], [x8] ; CHECK-NEXT: ld1 { v0.h }[2], [x8]
; CHECK-NEXT: ld1 { v1.h }[2], [x9] ; CHECK-NEXT: ld1 { v1.h }[2], [x9]
; CHECK-NEXT: shl v0.2s, v0.2s, #16 ; CHECK-NEXT: shl v0.2s, v0.2s, #16
; CHECK-NEXT: shl v1.2s, v1.2s, #16 ; CHECK-NEXT: shl v1.2s, v1.2s, #16
; CHECK-NEXT: sqadd v0.2s, v1.2s, v0.2s ; CHECK-NEXT: sqadd v0.2s, v1.2s, v0.2s
; CHECK-NEXT: ushr v0.2s, v0.2s, #16 ; CHECK-NEXT: ushr v0.2s, v0.2s, #16
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: mov w9, v0.s[1]
; CHECK-NEXT: strh w9, [x2] ; CHECK-NEXT: strh w9, [x2, #2]
; CHECK-NEXT: strh w8, [x2, #2] ; CHECK-NEXT: strh w8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i16>, <2 x i16>* %px %x = load <2 x i16>, <2 x i16>* %px
%y = load <2 x i16>, <2 x i16>* %py %y = load <2 x i16>, <2 x i16>* %py
%z = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %x, <2 x i16> %y) %z = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
store <2 x i16> %z, <2 x i16>* %pz store <2 x i16> %z, <2 x i16>* %pz
ret void ret void
} }
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llvm/test/CodeGen/AArch64/sat-add.ll

Show First 20 Lines • Show All 340 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%r = select i1 %c, i64 -1, i64 %a %r = select i1 %c, i64 -1, i64 %a
ret i64 %r ret i64 %r
} }
define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) { define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) {
; CHECK-LABEL: unsigned_sat_constant_v16i8_using_min: ; CHECK-LABEL: unsigned_sat_constant_v16i8_using_min:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.16b, #213 ; CHECK-NEXT: movi v1.16b, #213
; CHECK-NEXT: movi v2.16b, #42
; CHECK-NEXT: umin v0.16b, v0.16b, v1.16b ; CHECK-NEXT: umin v0.16b, v0.16b, v1.16b
; CHECK-NEXT: add v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.16b, #42
; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp ult <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43> %c = icmp ult <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
%s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43> %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
%r = add <16 x i8> %s, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42> %r = add <16 x i8> %s, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
ret <16 x i8> %r ret <16 x i8> %r
} }
define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) { define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) {
Show All 18 Lines; CHECK-NEXT: ret
%c = icmp ugt <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43> %c = icmp ugt <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
%r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
ret <16 x i8> %r ret <16 x i8> %r
} }
define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) { define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) {
; CHECK-LABEL: unsigned_sat_constant_v8i16_using_min: ; CHECK-LABEL: unsigned_sat_constant_v8i16_using_min:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mvni v1.8h, #42
; CHECK-NEXT: umin v0.8h, v0.8h, v1.8h
; CHECK-NEXT: movi v1.8h, #42 ; CHECK-NEXT: movi v1.8h, #42
; CHECK-NEXT: mvni v2.8h, #42
; CHECK-NEXT: umin v0.8h, v0.8h, v2.8h
; CHECK-NEXT: add v0.8h, v0.8h, v1.8h ; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp ult <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43> %c = icmp ult <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
%s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43> %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
%r = add <8 x i16> %s, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42> %r = add <8 x i16> %s, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
ret <8 x i16> %r ret <8 x i16> %r
} }
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llvm/test/CodeGen/AArch64/select_cc.ll

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Linesentry:
%cc = icmp ne i32 %a, %b %cc = icmp ne i32 %a, %b
%sel = select i1 %cc, i64 0, i64 4 %sel = select i1 %cc, i64 0, i64 4
ret i64 %sel ret i64 %sel
} }
define <2 x double> @select_olt_load_cmp(<2 x double> %a, <2 x float>* %src) { define <2 x double> @select_olt_load_cmp(<2 x double> %a, <2 x float>* %src) {
; CHECK-LABEL: select_olt_load_cmp: ; CHECK-LABEL: select_olt_load_cmp:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi d1, #0000000000000000 ; CHECK-NEXT: ldr d1, [x0]
; CHECK-NEXT: ldr d2, [x0] ; CHECK-NEXT: movi d2, #0000000000000000
; CHECK-NEXT: fcmgt v1.2s, v2.2s, v1.2s ; CHECK-NEXT: fcmgt v1.2s, v1.2s, v2.2s
; CHECK-NEXT: sshll v1.2d, v1.2s, #0 ; CHECK-NEXT: sshll v1.2d, v1.2s, #0
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%l = load <2 x float>, <2 x float>* %src, align 4 %l = load <2 x float>, <2 x float>* %src, align 4
%cmp = fcmp olt <2 x float> zeroinitializer, %l %cmp = fcmp olt <2 x float> zeroinitializer, %l
%sel = select <2 x i1> %cmp, <2 x double> %a, <2 x double> zeroinitializer %sel = select <2 x i1> %cmp, <2 x double> %a, <2 x double> zeroinitializer
ret <2 x double> %sel ret <2 x double> %sel
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llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll

Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shl = select i1 %t, i64 65536, i64 0 %shl = select i1 %t, i64 65536, i64 0
ret i64 %shl ret i64 %shl
} }
define <16 x i8> @sel_shift_bool_v16i8(<16 x i1> %t) { define <16 x i8> @sel_shift_bool_v16i8(<16 x i1> %t) {
; CHECK-LABEL: sel_shift_bool_v16i8: ; CHECK-LABEL: sel_shift_bool_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.16b, #128
; CHECK-NEXT: shl v0.16b, v0.16b, #7 ; CHECK-NEXT: shl v0.16b, v0.16b, #7
; CHECK-NEXT: movi v1.16b, #128
; CHECK-NEXT: cmlt v0.16b, v0.16b, #0 ; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shl = select <16 x i1> %t, <16 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>, <16 x i8> zeroinitializer %shl = select <16 x i1> %t, <16 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>, <16 x i8> zeroinitializer
ret <16 x i8> %shl ret <16 x i8> %shl
} }
define <8 x i16> @sel_shift_bool_v8i16(<8 x i1> %t) { define <8 x i16> @sel_shift_bool_v8i16(<8 x i1> %t) {
Show All 38 Lines

llvm/test/CodeGen/AArch64/shift-mod.ll

Show First 20 Lines • Show All 96 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%sext = add i64 %conv, 72057594037927936 %sext = add i64 %conv, 72057594037927936
%conv1 = ashr i64 %sext, 56 %conv1 = ashr i64 %sext, 56
ret i64 %conv1 ret i64 %conv1
} }
define <4 x i32> @ashr_add_shl_v4i8(<4 x i32> %r) { define <4 x i32> @ashr_add_shl_v4i8(<4 x i32> %r) {
; CHECK-LABEL: ashr_add_shl_v4i8: ; CHECK-LABEL: ashr_add_shl_v4i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #1, lsl #24
; CHECK-NEXT: shl v0.4s, v0.4s, #24 ; CHECK-NEXT: shl v0.4s, v0.4s, #24
; CHECK-NEXT: movi v1.4s, #1, lsl #24
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: sshr v0.4s, v0.4s, #24 ; CHECK-NEXT: sshr v0.4s, v0.4s, #24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%conv = shl <4 x i32> %r, <i32 24, i32 24, i32 24, i32 24> %conv = shl <4 x i32> %r, <i32 24, i32 24, i32 24, i32 24>
%sext = add <4 x i32> %conv, <i32 16777216, i32 16777216, i32 16777216, i32 16777216> %sext = add <4 x i32> %conv, <i32 16777216, i32 16777216, i32 16777216, i32 16777216>
%conv1 = ashr <4 x i32> %sext, <i32 24, i32 24, i32 24, i32 24> %conv1 = ashr <4 x i32> %sext, <i32 24, i32 24, i32 24, i32 24>
ret <4 x i32> %conv1 ret <4 x i32> %conv1
} }
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llvm/test/CodeGen/AArch64/signbit-shift.ll

Show All 24 Lines; CHECK-NEXT: ret
%r = add i32 %e, 41 %r = add i32 %e, 41
ret i32 %r ret i32 %r
} }
define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) { define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: add_zext_ifpos_vec_splat: ; CHECK-LABEL: add_zext_ifpos_vec_splat:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT: movi v2.4s, #41
; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s ; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s
; CHECK-NEXT: sub v0.4s, v2.4s, v0.4s ; CHECK-NEXT: movi v1.4s, #41
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = zext <4 x i1> %c to <4 x i32> %e = zext <4 x i1> %c to <4 x i32>
%r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41> %r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>
ret <4 x i32> %r ret <4 x i32> %r
} }
define i32 @sel_ifpos_tval_bigger(i32 %x) { define i32 @sel_ifpos_tval_bigger(i32 %x) {
Show All 30 Lines; CHECK-NEXT: ret
%r = add i32 %e, 42 %r = add i32 %e, 42
ret i32 %r ret i32 %r
} }
define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) { define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: add_sext_ifpos_vec_splat: ; CHECK-LABEL: add_sext_ifpos_vec_splat:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT: movi v2.4s, #42
; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s ; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s
; CHECK-NEXT: add v0.4s, v0.4s, v2.4s ; CHECK-NEXT: movi v1.4s, #42
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = sext <4 x i1> %c to <4 x i32> %e = sext <4 x i1> %c to <4 x i32>
%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42> %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
ret <4 x i32> %r ret <4 x i32> %r
} }
define i32 @sel_ifpos_fval_bigger(i32 %x) { define i32 @sel_ifpos_fval_bigger(i32 %x) {
▲ Show 20 Lines • Show All 176 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/sinksplat.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
define <4 x i32> @smull(<4 x i16> %x, <4 x i16> *%y) { define <4 x i32> @smull(<4 x i16> %x, <4 x i16> *%y) {
; CHECK-LABEL: smull: ; CHECK-LABEL: smull:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov d1, d0
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: .LBB0_1: // %l1 ; CHECK-NEXT: .LBB0_1: // %l1
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr d2, [x0] ; CHECK-NEXT: ldr d2, [x0]
; CHECK-NEXT: subs w8, w8, #1 ; CHECK-NEXT: subs w8, w8, #1
; CHECK-NEXT: smlal v0.4s, v2.4h, v1.h[3] ; CHECK-NEXT: smlal v1.4s, v2.4h, v0.h[3]
; CHECK-NEXT: b.eq .LBB0_1 ; CHECK-NEXT: b.eq .LBB0_1
; CHECK-NEXT: // %bb.2: // %l2 ; CHECK-NEXT: // %bb.2: // %l2
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = shufflevector <4 x i16> %x, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> %a = shufflevector <4 x i16> %x, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
br label %l1 br label %l1
l1: l1:
%p = phi i32 [ 0, %entry ], [ %pa, %l1 ] %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]
%q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ] %q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ]
%l = load <4 x i16>, <4 x i16> *%y %l = load <4 x i16>, <4 x i16> *%y
%b = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %l, <4 x i16> %a) %b = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %l, <4 x i16> %a)
%c = add nsw <4 x i32> %q, %b %c = add nsw <4 x i32> %q, %b
%pa = add i32 %p, 1 %pa = add i32 %p, 1
%c1 = icmp eq i32 %p, 0 %c1 = icmp eq i32 %p, 0
br i1 %c1, label %l1, label %l2 br i1 %c1, label %l1, label %l2
l2: l2:
ret <4 x i32> %c ret <4 x i32> %c
} }
define <4 x i32> @umull(<4 x i16> %x, <4 x i16> *%y) { define <4 x i32> @umull(<4 x i16> %x, <4 x i16> *%y) {
; CHECK-LABEL: umull: ; CHECK-LABEL: umull:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov d1, d0
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: .LBB1_1: // %l1 ; CHECK-NEXT: .LBB1_1: // %l1
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr d2, [x0] ; CHECK-NEXT: ldr d2, [x0]
; CHECK-NEXT: subs w8, w8, #1 ; CHECK-NEXT: subs w8, w8, #1
; CHECK-NEXT: umlal v0.4s, v2.4h, v1.h[3] ; CHECK-NEXT: umlal v1.4s, v2.4h, v0.h[3]
; CHECK-NEXT: b.eq .LBB1_1 ; CHECK-NEXT: b.eq .LBB1_1
; CHECK-NEXT: // %bb.2: // %l2 ; CHECK-NEXT: // %bb.2: // %l2
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = shufflevector <4 x i16> %x, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> %a = shufflevector <4 x i16> %x, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
br label %l1 br label %l1
l1: l1:
%p = phi i32 [ 0, %entry ], [ %pa, %l1 ] %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]
%q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ] %q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ]
%l = load <4 x i16>, <4 x i16> *%y %l = load <4 x i16>, <4 x i16> *%y
%b = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %l, <4 x i16> %a) %b = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %l, <4 x i16> %a)
%c = add nsw <4 x i32> %q, %b %c = add nsw <4 x i32> %q, %b
%pa = add i32 %p, 1 %pa = add i32 %p, 1
%c1 = icmp eq i32 %p, 0 %c1 = icmp eq i32 %p, 0
br i1 %c1, label %l1, label %l2 br i1 %c1, label %l1, label %l2
l2: l2:
ret <4 x i32> %c ret <4 x i32> %c
} }
define <4 x i32> @sqadd(<4 x i32> %x, <4 x i32> *%y) { define <4 x i32> @sqadd(<4 x i32> %x, <4 x i32> *%y) {
; CHECK-LABEL: sqadd: ; CHECK-LABEL: sqadd:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: .LBB2_1: // %l1 ; CHECK-NEXT: .LBB2_1: // %l1
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: ldr q2, [x0]
; CHECK-NEXT: subs w8, w8, #1 ; CHECK-NEXT: subs w8, w8, #1
; CHECK-NEXT: sqrdmulh v2.4s, v2.4s, v1.s[3] ; CHECK-NEXT: sqrdmulh v2.4s, v2.4s, v0.s[3]
; CHECK-NEXT: sqadd v0.4s, v0.4s, v2.4s ; CHECK-NEXT: sqadd v1.4s, v1.4s, v2.4s
; CHECK-NEXT: b.eq .LBB2_1 ; CHECK-NEXT: b.eq .LBB2_1
; CHECK-NEXT: // %bb.2: // %l2 ; CHECK-NEXT: // %bb.2: // %l2
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
br label %l1 br label %l1
l1: l1:
%p = phi i32 [ 0, %entry ], [ %pa, %l1 ] %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]
%q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ] %q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ]
%l = load <4 x i32>, <4 x i32> *%y %l = load <4 x i32>, <4 x i32> *%y
%b = tail call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %l, <4 x i32> %a) %b = tail call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %l, <4 x i32> %a)
%c = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %q, <4 x i32> %b) %c = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %q, <4 x i32> %b)
%pa = add i32 %p, 1 %pa = add i32 %p, 1
%c1 = icmp eq i32 %p, 0 %c1 = icmp eq i32 %p, 0
br i1 %c1, label %l1, label %l2 br i1 %c1, label %l1, label %l2
l2: l2:
ret <4 x i32> %c ret <4 x i32> %c
} }
define <4 x i32> @sqsub(<4 x i32> %x, <4 x i32> *%y) { define <4 x i32> @sqsub(<4 x i32> %x, <4 x i32> *%y) {
; CHECK-LABEL: sqsub: ; CHECK-LABEL: sqsub:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: .LBB3_1: // %l1 ; CHECK-NEXT: .LBB3_1: // %l1
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: ldr q2, [x0]
; CHECK-NEXT: subs w8, w8, #1 ; CHECK-NEXT: subs w8, w8, #1
; CHECK-NEXT: sqrdmulh v2.4s, v2.4s, v1.s[3] ; CHECK-NEXT: sqrdmulh v2.4s, v2.4s, v0.s[3]
; CHECK-NEXT: sqsub v0.4s, v0.4s, v2.4s ; CHECK-NEXT: sqsub v1.4s, v1.4s, v2.4s
; CHECK-NEXT: b.eq .LBB3_1 ; CHECK-NEXT: b.eq .LBB3_1
; CHECK-NEXT: // %bb.2: // %l2 ; CHECK-NEXT: // %bb.2: // %l2
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
br label %l1 br label %l1
l1: l1:
%p = phi i32 [ 0, %entry ], [ %pa, %l1 ] %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]
%q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ] %q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ]
%l = load <4 x i32>, <4 x i32> *%y %l = load <4 x i32>, <4 x i32> *%y
%b = tail call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %l, <4 x i32> %a) %b = tail call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %l, <4 x i32> %a)
%c = tail call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %q, <4 x i32> %b) %c = tail call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %q, <4 x i32> %b)
%pa = add i32 %p, 1 %pa = add i32 %p, 1
%c1 = icmp eq i32 %p, 0 %c1 = icmp eq i32 %p, 0
br i1 %c1, label %l1, label %l2 br i1 %c1, label %l1, label %l2
l2: l2:
ret <4 x i32> %c ret <4 x i32> %c
} }
define <4 x i32> @sqdmulh(<4 x i32> %x, <4 x i32> *%y) { define <4 x i32> @sqdmulh(<4 x i32> %x, <4 x i32> *%y) {
; CHECK-LABEL: sqdmulh: ; CHECK-LABEL: sqdmulh:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: .LBB4_1: // %l1 ; CHECK-NEXT: .LBB4_1: // %l1
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: ldr q2, [x0]
; CHECK-NEXT: subs w8, w8, #1 ; CHECK-NEXT: subs w8, w8, #1
; CHECK-NEXT: sqdmulh v2.4s, v2.4s, v1.s[3] ; CHECK-NEXT: sqdmulh v2.4s, v2.4s, v0.s[3]
; CHECK-NEXT: add v0.4s, v0.4s, v2.4s ; CHECK-NEXT: add v1.4s, v1.4s, v2.4s
; CHECK-NEXT: b.eq .LBB4_1 ; CHECK-NEXT: b.eq .LBB4_1
; CHECK-NEXT: // %bb.2: // %l2 ; CHECK-NEXT: // %bb.2: // %l2
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
br label %l1 br label %l1
l1: l1:
%p = phi i32 [ 0, %entry ], [ %pa, %l1 ] %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]
%q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ] %q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ]
%l = load <4 x i32>, <4 x i32> *%y %l = load <4 x i32>, <4 x i32> *%y
%b = tail call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> %l, <4 x i32> %a) %b = tail call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> %l, <4 x i32> %a)
%c = add nsw <4 x i32> %q, %b %c = add nsw <4 x i32> %q, %b
%pa = add i32 %p, 1 %pa = add i32 %p, 1
%c1 = icmp eq i32 %p, 0 %c1 = icmp eq i32 %p, 0
br i1 %c1, label %l1, label %l2 br i1 %c1, label %l1, label %l2
l2: l2:
ret <4 x i32> %c ret <4 x i32> %c
} }
define <4 x i32> @sqdmull(<4 x i16> %x, <4 x i16> *%y) { define <4 x i32> @sqdmull(<4 x i16> %x, <4 x i16> *%y) {
; CHECK-LABEL: sqdmull: ; CHECK-LABEL: sqdmull:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov d1, d0
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: .LBB5_1: // %l1 ; CHECK-NEXT: .LBB5_1: // %l1
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr d2, [x0] ; CHECK-NEXT: ldr d2, [x0]
; CHECK-NEXT: subs w8, w8, #1 ; CHECK-NEXT: subs w8, w8, #1
; CHECK-NEXT: sqdmull v2.4s, v2.4h, v1.h[3] ; CHECK-NEXT: sqdmull v2.4s, v2.4h, v0.h[3]
; CHECK-NEXT: add v0.4s, v0.4s, v2.4s ; CHECK-NEXT: add v1.4s, v1.4s, v2.4s
; CHECK-NEXT: b.eq .LBB5_1 ; CHECK-NEXT: b.eq .LBB5_1
; CHECK-NEXT: // %bb.2: // %l2 ; CHECK-NEXT: // %bb.2: // %l2
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = shufflevector <4 x i16> %x, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> %a = shufflevector <4 x i16> %x, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
br label %l1 br label %l1
l1: l1:
%p = phi i32 [ 0, %entry ], [ %pa, %l1 ] %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]
%q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ] %q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ]
%l = load <4 x i16>, <4 x i16> *%y %l = load <4 x i16>, <4 x i16> *%y
%b = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %l, <4 x i16> %a) %b = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %l, <4 x i16> %a)
%c = add nsw <4 x i32> %q, %b %c = add nsw <4 x i32> %q, %b
%pa = add i32 %p, 1 %pa = add i32 %p, 1
%c1 = icmp eq i32 %p, 0 %c1 = icmp eq i32 %p, 0
br i1 %c1, label %l1, label %l2 br i1 %c1, label %l1, label %l2
l2: l2:
ret <4 x i32> %c ret <4 x i32> %c
} }
define <4 x i32> @mlal(<4 x i32> %x, <4 x i32> *%y) { define <4 x i32> @mlal(<4 x i32> %x, <4 x i32> *%y) {
; CHECK-LABEL: mlal: ; CHECK-LABEL: mlal:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: dup v1.4s, v0.s[3]
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: dup v1.4s, v1.s[3]
; CHECK-NEXT: .LBB6_1: // %l1 ; CHECK-NEXT: .LBB6_1: // %l1
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: ldr q2, [x0]
; CHECK-NEXT: subs w8, w8, #1 ; CHECK-NEXT: subs w8, w8, #1
; CHECK-NEXT: mla v0.4s, v2.4s, v1.4s ; CHECK-NEXT: mla v0.4s, v2.4s, v1.4s
; CHECK-NEXT: b.eq .LBB6_1 ; CHECK-NEXT: b.eq .LBB6_1
; CHECK-NEXT: // %bb.2: // %l2 ; CHECK-NEXT: // %bb.2: // %l2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Show All 13 Lines
l2: l2:
ret <4 x i32> %c ret <4 x i32> %c
} }
define <4 x float> @fmul(<4 x float> %x, <4 x float> *%y) { define <4 x float> @fmul(<4 x float> %x, <4 x float> *%y) {
; CHECK-LABEL: fmul: ; CHECK-LABEL: fmul:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: .LBB7_1: // %l1 ; CHECK-NEXT: .LBB7_1: // %l1
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: ldr q2, [x0]
; CHECK-NEXT: subs w8, w8, #1 ; CHECK-NEXT: subs w8, w8, #1
; CHECK-NEXT: fmul v2.4s, v2.4s, v1.s[3] ; CHECK-NEXT: fmul v2.4s, v2.4s, v0.s[3]
; CHECK-NEXT: fadd v0.4s, v2.4s, v0.4s ; CHECK-NEXT: fadd v1.4s, v2.4s, v1.4s
; CHECK-NEXT: b.eq .LBB7_1 ; CHECK-NEXT: b.eq .LBB7_1
; CHECK-NEXT: // %bb.2: // %l2 ; CHECK-NEXT: // %bb.2: // %l2
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
br label %l1 br label %l1
l1: l1:
%p = phi i32 [ 0, %entry ], [ %pa, %l1 ] %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]
%q = phi <4 x float> [ zeroinitializer, %entry ], [ %c, %l1 ] %q = phi <4 x float> [ zeroinitializer, %entry ], [ %c, %l1 ]
%l = load <4 x float>, <4 x float> *%y %l = load <4 x float>, <4 x float> *%y
%b = fmul <4 x float> %l, %a %b = fmul <4 x float> %l, %a
%c = fadd <4 x float> %b, %q %c = fadd <4 x float> %b, %q
%pa = add i32 %p, 1 %pa = add i32 %p, 1
%c1 = icmp eq i32 %p, 0 %c1 = icmp eq i32 %p, 0
br i1 %c1, label %l1, label %l2 br i1 %c1, label %l1, label %l2
l2: l2:
ret <4 x float> %c ret <4 x float> %c
} }
define <4 x float> @fmuladd(<4 x float> %x, <4 x float> *%y) { define <4 x float> @fmuladd(<4 x float> %x, <4 x float> *%y) {
; CHECK-LABEL: fmuladd: ; CHECK-LABEL: fmuladd:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: dup v1.4s, v0.s[3]
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: dup v1.4s, v1.s[3]
; CHECK-NEXT: .LBB8_1: // %l1 ; CHECK-NEXT: .LBB8_1: // %l1
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: ldr q2, [x0]
; CHECK-NEXT: subs w8, w8, #1 ; CHECK-NEXT: subs w8, w8, #1
; CHECK-NEXT: fmla v0.4s, v1.4s, v2.4s ; CHECK-NEXT: fmla v0.4s, v1.4s, v2.4s
; CHECK-NEXT: b.eq .LBB8_1 ; CHECK-NEXT: b.eq .LBB8_1
; CHECK-NEXT: // %bb.2: // %l2 ; CHECK-NEXT: // %bb.2: // %l2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
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l2: l2:
ret <4 x float> %c ret <4 x float> %c
} }
define <4 x float> @fma(<4 x float> %x, <4 x float> *%y) { define <4 x float> @fma(<4 x float> %x, <4 x float> *%y) {
; CHECK-LABEL: fma: ; CHECK-LABEL: fma:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: dup v1.4s, v0.s[3]
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: dup v1.4s, v1.s[3]
; CHECK-NEXT: .LBB9_1: // %l1 ; CHECK-NEXT: .LBB9_1: // %l1
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q3, [x0] ; CHECK-NEXT: ldr q3, [x0]
; CHECK-NEXT: subs w8, w8, #1 ; CHECK-NEXT: subs w8, w8, #1
; CHECK-NEXT: mov v2.16b, v0.16b ; CHECK-NEXT: mov v2.16b, v0.16b
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: fmla v0.4s, v2.4s, v3.4s ; CHECK-NEXT: fmla v0.4s, v2.4s, v3.4s
; CHECK-NEXT: b.eq .LBB9_1 ; CHECK-NEXT: b.eq .LBB9_1
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l2: l2:
ret <4 x float> %c ret <4 x float> %c
} }
define <4 x i32> @smull_nonsplat(<4 x i16> %x, <4 x i16> *%y) { define <4 x i32> @smull_nonsplat(<4 x i16> %x, <4 x i16> *%y) {
; CHECK-LABEL: smull_nonsplat: ; CHECK-LABEL: smull_nonsplat:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov d1, d0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: dup v1.4h, v0.h[3]
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: ext v1.8b, v0.8b, v1.8b, #4
; CHECK-NEXT: ext v1.8b, v0.8b, v1.8b, #6
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: dup v2.4h, v1.h[3]
; CHECK-NEXT: ext v2.8b, v1.8b, v2.8b, #4
; CHECK-NEXT: ext v1.8b, v1.8b, v2.8b, #6
; CHECK-NEXT: .LBB10_1: // %l1 ; CHECK-NEXT: .LBB10_1: // %l1
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr d2, [x0] ; CHECK-NEXT: ldr d2, [x0]
; CHECK-NEXT: subs w8, w8, #1 ; CHECK-NEXT: subs w8, w8, #1
; CHECK-NEXT: smlal v0.4s, v2.4h, v1.4h ; CHECK-NEXT: smlal v0.4s, v2.4h, v1.4h
; CHECK-NEXT: b.eq .LBB10_1 ; CHECK-NEXT: b.eq .LBB10_1
; CHECK-NEXT: // %bb.2: // %l2 ; CHECK-NEXT: // %bb.2: // %l2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
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llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%srem = srem i6 %X, 4 %srem = srem i6 %X, 4
%cmp = icmp ne i6 %srem, 0 %cmp = icmp ne i6 %srem, 0
ret i1 %cmp ret i1 %cmp
} }
define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind { define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
; CHECK-LABEL: test_srem_vec: ; CHECK-LABEL: test_srem_vec:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #7282 ; CHECK-NEXT: mov x11, #7282
; CHECK-NEXT: sbfx x9, x0, #0, #33 ; CHECK-NEXT: mov x9, #7281
; CHECK-NEXT: movk x8, #29127, lsl #16
; CHECK-NEXT: mov x11, #7281
; CHECK-NEXT: movk x8, #50972, lsl #32
; CHECK-NEXT: movk x11, #29127, lsl #16 ; CHECK-NEXT: movk x11, #29127, lsl #16
; CHECK-NEXT: movk x8, #7281, lsl #48 ; CHECK-NEXT: movk x9, #29127, lsl #16
; CHECK-NEXT: movk x11, #50972, lsl #32 ; CHECK-NEXT: movk x11, #50972, lsl #32
; CHECK-NEXT: sbfx x12, x1, #0, #33 ; CHECK-NEXT: movk x9, #50972, lsl #32
; CHECK-NEXT: sbfx x10, x2, #0, #33 ; CHECK-NEXT: sbfx x10, x0, #0, #33
; CHECK-NEXT: smulh x13, x9, x8
; CHECK-NEXT: movk x11, #7281, lsl #48 ; CHECK-NEXT: movk x11, #7281, lsl #48
; CHECK-NEXT: smulh x8, x12, x8 ; CHECK-NEXT: sbfx x8, x2, #0, #33
; CHECK-NEXT: smulh x11, x10, x11 ; CHECK-NEXT: movk x9, #7281, lsl #48
; CHECK-NEXT: smulh x13, x10, x11
; CHECK-NEXT: sbfx x12, x1, #0, #33
; CHECK-NEXT: smulh x9, x8, x9
; CHECK-NEXT: smulh x11, x12, x11
; CHECK-NEXT: sub x9, x9, x8
; CHECK-NEXT: add x13, x13, x13, lsr #63 ; CHECK-NEXT: add x13, x13, x13, lsr #63
; CHECK-NEXT: sub x11, x11, x10 ; CHECK-NEXT: asr x14, x9, #3
; CHECK-NEXT: add x8, x8, x8, lsr #63 ; CHECK-NEXT: add x9, x14, x9, lsr #63
; CHECK-NEXT: add x13, x13, x13, lsl #3 ; CHECK-NEXT: add x13, x13, x13, lsl #3
; CHECK-NEXT: asr x14, x11, #3 ; CHECK-NEXT: add x11, x11, x11, lsr #63
; CHECK-NEXT: sub x9, x9, x13 ; CHECK-NEXT: sub x10, x10, x13
; CHECK-NEXT: add x11, x14, x11, lsr #63 ; CHECK-NEXT: add x9, x9, x9, lsl #3
; CHECK-NEXT: add x8, x8, x8, lsl #3 ; CHECK-NEXT: add x8, x8, x9
; CHECK-NEXT: sub x8, x12, x8
; CHECK-NEXT: add x11, x11, x11, lsl #3 ; CHECK-NEXT: add x11, x11, x11, lsl #3
; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: add x10, x10, x11
; CHECK-NEXT: mov x9, #8589934591 ; CHECK-NEXT: mov x9, #8589934591
; CHECK-NEXT: adrp x11, .LCPI3_0 ; CHECK-NEXT: sub x11, x12, x11
; CHECK-NEXT: adrp x12, .LCPI3_1 ; CHECK-NEXT: adrp x12, .LCPI3_0
; CHECK-NEXT: mov v0.d[1], x8 ; CHECK-NEXT: fmov d0, x10
; CHECK-NEXT: fmov d1, x10 ; CHECK-NEXT: adrp x10, .LCPI3_1
; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: dup v2.2d, x9 ; CHECK-NEXT: dup v2.2d, x9
; CHECK-NEXT: ldr q3, [x11, :lo12:.LCPI3_0] ; CHECK-NEXT: ldr q3, [x12, :lo12:.LCPI3_0]
; CHECK-NEXT: ldr q4, [x12, :lo12:.LCPI3_1] ; CHECK-NEXT: mov v0.d[1], x11
; CHECK-NEXT: ldr q4, [x10, :lo12:.LCPI3_1]
; CHECK-NEXT: and v1.16b, v1.16b, v2.16b ; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
; CHECK-NEXT: cmeq v0.2d, v0.2d, v3.2d
; CHECK-NEXT: cmeq v1.2d, v1.2d, v4.2d ; CHECK-NEXT: cmeq v1.2d, v1.2d, v4.2d
; CHECK-NEXT: cmeq v0.2d, v0.2d, v3.2d
; CHECK-NEXT: mvn v1.16b, v1.16b
; CHECK-NEXT: mvn v0.16b, v0.16b ; CHECK-NEXT: mvn v0.16b, v0.16b
; CHECK-NEXT: xtn v0.2s, v0.2d ; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: mvn v1.16b, v1.16b
; CHECK-NEXT: xtn v1.2s, v1.2d ; CHECK-NEXT: xtn v1.2s, v1.2d
; CHECK-NEXT: mov w1, v0.s[1]
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: mov w1, v0.s[1]
; CHECK-NEXT: fmov w2, s1 ; CHECK-NEXT: fmov w2, s1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <3 x i33> %X, <i33 9, i33 9, i33 -9> %srem = srem <3 x i33> %X, <i33 9, i33 9, i33 -9>
%cmp = icmp ne <3 x i33> %srem, <i33 3, i33 -3, i33 3> %cmp = icmp ne <3 x i33> %srem, <i33 3, i33 -3, i33 3>
ret <3 x i1> %cmp ret <3 x i1> %cmp
} }

llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
; Odd+Even divisors ; Odd+Even divisors
define <4 x i32> @test_srem_odd_even(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_even(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_even: ; CHECK-LABEL: test_srem_odd_even:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI0_0 ; CHECK-NEXT: adrp x8, .LCPI0_0
; CHECK-NEXT: adrp x9, .LCPI0_1 ; CHECK-NEXT: adrp x9, .LCPI0_1
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
; CHECK-NEXT: adrp x8, .LCPI0_2 ; CHECK-NEXT: adrp x8, .LCPI0_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI0_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI0_1]
; CHECK-NEXT: adrp x9, .LCPI0_3 ; CHECK-NEXT: adrp x9, .LCPI0_3
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI0_2] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI0_2]
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI0_3] ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI0_3]
; CHECK-NEXT: adrp x8, .LCPI0_4 ; CHECK-NEXT: adrp x8, .LCPI0_4
; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s ; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_4] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_4]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 5, i32 14, i32 25, i32 100> %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 25, i32 100>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;==============================================================================; ;==============================================================================;
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; One all-ones divisor in even divisor ; One all-ones divisor in even divisor
define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_even_allones_eq: ; CHECK-LABEL: test_srem_even_allones_eq:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #28087 ; CHECK-NEXT: mov w8, #28087
; CHECK-NEXT: mov w9, #9362 ; CHECK-NEXT: mov w9, #9362
; CHECK-NEXT: movk w8, #46811, lsl #16 ; CHECK-NEXT: movk w8, #46811, lsl #16
; CHECK-NEXT: movk w9, #4681, lsl #16 ; CHECK-NEXT: movk w9, #4681, lsl #16
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: dup v1.4s, w8 ; CHECK-NEXT: dup v1.4s, w8
; CHECK-NEXT: dup v2.4s, w9 ; CHECK-NEXT: dup v2.4s, w9
; CHECK-NEXT: adrp x8, .LCPI3_0 ; CHECK-NEXT: adrp x8, .LCPI3_0
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: shl v0.4s, v2.4s, #31 ; CHECK-NEXT: shl v0.4s, v2.4s, #31
; CHECK-NEXT: ushr v1.4s, v2.4s, #1 ; CHECK-NEXT: ushr v1.4s, v2.4s, #1
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_0] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_0]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14> %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_even_allones_ne: ; CHECK-LABEL: test_srem_even_allones_ne:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #28087 ; CHECK-NEXT: mov w8, #28087
; CHECK-NEXT: mov w9, #9362 ; CHECK-NEXT: mov w9, #9362
; CHECK-NEXT: movk w8, #46811, lsl #16 ; CHECK-NEXT: movk w8, #46811, lsl #16
; CHECK-NEXT: movk w9, #4681, lsl #16 ; CHECK-NEXT: movk w9, #4681, lsl #16
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: dup v1.4s, w8 ; CHECK-NEXT: dup v1.4s, w8
; CHECK-NEXT: dup v2.4s, w9 ; CHECK-NEXT: dup v2.4s, w9
; CHECK-NEXT: adrp x8, .LCPI4_0 ; CHECK-NEXT: adrp x8, .LCPI4_0
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: shl v0.4s, v2.4s, #31 ; CHECK-NEXT: shl v0.4s, v2.4s, #31
; CHECK-NEXT: ushr v1.4s, v2.4s, #1 ; CHECK-NEXT: ushr v1.4s, v2.4s, #1
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI4_0] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI4_0]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s ; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14> %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
%cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One all-ones divisor in odd+even divisor ; One all-ones divisor in odd+even divisor
define <4 x i32> @test_srem_odd_even_allones_eq(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_even_allones_eq: ; CHECK-LABEL: test_srem_odd_even_allones_eq:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI5_0 ; CHECK-NEXT: adrp x8, .LCPI5_0
; CHECK-NEXT: adrp x9, .LCPI5_1 ; CHECK-NEXT: adrp x9, .LCPI5_1
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0]
; CHECK-NEXT: adrp x8, .LCPI5_2 ; CHECK-NEXT: adrp x8, .LCPI5_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI5_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI5_1]
; CHECK-NEXT: adrp x9, .LCPI5_3 ; CHECK-NEXT: adrp x9, .LCPI5_3
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI5_2] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI5_2]
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI5_3] ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI5_3]
; CHECK-NEXT: adrp x8, .LCPI5_4 ; CHECK-NEXT: adrp x8, .LCPI5_4
; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s ; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI5_4] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI5_4]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100> %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
define <4 x i32> @test_srem_odd_even_allones_ne(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_even_allones_ne: ; CHECK-LABEL: test_srem_odd_even_allones_ne:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI6_0 ; CHECK-NEXT: adrp x8, .LCPI6_0
; CHECK-NEXT: adrp x9, .LCPI6_1 ; CHECK-NEXT: adrp x9, .LCPI6_1
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI6_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI6_0]
; CHECK-NEXT: adrp x8, .LCPI6_2 ; CHECK-NEXT: adrp x8, .LCPI6_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI6_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI6_1]
; CHECK-NEXT: adrp x9, .LCPI6_3 ; CHECK-NEXT: adrp x9, .LCPI6_3
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI6_2] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI6_2]
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI6_3] ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI6_3]
; CHECK-NEXT: adrp x8, .LCPI6_4 ; CHECK-NEXT: adrp x8, .LCPI6_4
; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s ; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI6_4] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI6_4]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s ; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100> %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
%cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; One power-of-two divisor in odd divisor ; One power-of-two divisor in odd divisor
define <4 x i32> @test_srem_odd_poweroftwo(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_poweroftwo: ; CHECK-LABEL: test_srem_odd_poweroftwo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI7_0 ; CHECK-NEXT: adrp x8, .LCPI7_0
; CHECK-NEXT: adrp x9, .LCPI7_1 ; CHECK-NEXT: adrp x9, .LCPI7_1
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI7_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI7_0]
; CHECK-NEXT: adrp x8, .LCPI7_2 ; CHECK-NEXT: adrp x8, .LCPI7_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI7_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI7_1]
; CHECK-NEXT: adrp x9, .LCPI7_3 ; CHECK-NEXT: adrp x9, .LCPI7_3
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI7_2] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI7_2]
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI7_3] ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI7_3]
; CHECK-NEXT: adrp x8, .LCPI7_4 ; CHECK-NEXT: adrp x8, .LCPI7_4
; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s ; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI7_4] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI7_4]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 5, i32 5, i32 16, i32 5> %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 16, i32 5>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One power-of-two divisor in even divisor ; One power-of-two divisor in even divisor
define <4 x i32> @test_srem_even_poweroftwo(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_even_poweroftwo: ; CHECK-LABEL: test_srem_even_poweroftwo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI8_0 ; CHECK-NEXT: adrp x8, .LCPI8_0
; CHECK-NEXT: adrp x9, .LCPI8_1 ; CHECK-NEXT: adrp x9, .LCPI8_1
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI8_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI8_0]
; CHECK-NEXT: adrp x8, .LCPI8_2 ; CHECK-NEXT: adrp x8, .LCPI8_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI8_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI8_1]
; CHECK-NEXT: adrp x9, .LCPI8_3 ; CHECK-NEXT: adrp x9, .LCPI8_3
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI8_2] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI8_2]
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI8_3] ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI8_3]
; CHECK-NEXT: adrp x8, .LCPI8_4 ; CHECK-NEXT: adrp x8, .LCPI8_4
; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s ; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI8_4] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI8_4]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 14, i32 14, i32 16, i32 14> %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 16, i32 14>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One power-of-two divisor in odd+even divisor ; One power-of-two divisor in odd+even divisor
define <4 x i32> @test_srem_odd_even_poweroftwo(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_even_poweroftwo: ; CHECK-LABEL: test_srem_odd_even_poweroftwo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI9_0 ; CHECK-NEXT: adrp x8, .LCPI9_0
; CHECK-NEXT: adrp x9, .LCPI9_1 ; CHECK-NEXT: adrp x9, .LCPI9_1
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI9_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI9_0]
; CHECK-NEXT: adrp x8, .LCPI9_2 ; CHECK-NEXT: adrp x8, .LCPI9_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI9_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI9_1]
; CHECK-NEXT: adrp x9, .LCPI9_3 ; CHECK-NEXT: adrp x9, .LCPI9_3
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI9_2] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI9_2]
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI9_3] ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI9_3]
; CHECK-NEXT: adrp x8, .LCPI9_4 ; CHECK-NEXT: adrp x8, .LCPI9_4
; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s ; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI9_4] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI9_4]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 5, i32 14, i32 16, i32 100> %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 16, i32 100>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
Show All 24 Lines
; One one divisor in even divisor ; One one divisor in even divisor
define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_even_one: ; CHECK-LABEL: test_srem_even_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #28087 ; CHECK-NEXT: mov w8, #28087
; CHECK-NEXT: mov w9, #9362 ; CHECK-NEXT: mov w9, #9362
; CHECK-NEXT: movk w8, #46811, lsl #16 ; CHECK-NEXT: movk w8, #46811, lsl #16
; CHECK-NEXT: movk w9, #4681, lsl #16 ; CHECK-NEXT: movk w9, #4681, lsl #16
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: dup v1.4s, w8 ; CHECK-NEXT: dup v1.4s, w8
; CHECK-NEXT: dup v2.4s, w9 ; CHECK-NEXT: dup v2.4s, w9
; CHECK-NEXT: adrp x8, .LCPI11_0 ; CHECK-NEXT: adrp x8, .LCPI11_0
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: shl v0.4s, v2.4s, #31 ; CHECK-NEXT: shl v0.4s, v2.4s, #31
; CHECK-NEXT: ushr v1.4s, v2.4s, #1 ; CHECK-NEXT: ushr v1.4s, v2.4s, #1
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI11_0] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI11_0]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 14, i32 14, i32 1, i32 14> %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 1, i32 14>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One one divisor in odd+even divisor ; One one divisor in odd+even divisor
define <4 x i32> @test_srem_odd_even_one(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_even_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_even_one: ; CHECK-LABEL: test_srem_odd_even_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI12_0 ; CHECK-NEXT: adrp x8, .LCPI12_0
; CHECK-NEXT: adrp x9, .LCPI12_1 ; CHECK-NEXT: adrp x9, .LCPI12_1
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI12_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI12_0]
; CHECK-NEXT: adrp x8, .LCPI12_2 ; CHECK-NEXT: adrp x8, .LCPI12_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI12_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI12_1]
; CHECK-NEXT: adrp x9, .LCPI12_3 ; CHECK-NEXT: adrp x9, .LCPI12_3
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI12_2] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI12_2]
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI12_3] ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI12_3]
; CHECK-NEXT: adrp x8, .LCPI12_4 ; CHECK-NEXT: adrp x8, .LCPI12_4
; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s ; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI12_4] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI12_4]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 5, i32 14, i32 1, i32 100> %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 1, i32 100>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; One INT_MIN divisor in odd divisor ; One INT_MIN divisor in odd divisor
define <4 x i32> @test_srem_odd_INT_MIN(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_INT_MIN: ; CHECK-LABEL: test_srem_odd_INT_MIN:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI13_0 ; CHECK-NEXT: adrp x8, .LCPI13_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI13_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI13_0]
; CHECK-NEXT: adrp x8, .LCPI13_1 ; CHECK-NEXT: adrp x8, .LCPI13_1
; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s ; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s
; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI13_1]
; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_1]
; CHECK-NEXT: adrp x8, .LCPI13_2 ; CHECK-NEXT: adrp x8, .LCPI13_2
; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_2] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_2]
; CHECK-NEXT: adrp x8, .LCPI13_3 ; CHECK-NEXT: adrp x8, .LCPI13_3
; CHECK-NEXT: mla v1.4s, v0.4s, v3.4s
; CHECK-NEXT: sshl v2.4s, v1.4s, v2.4s ; CHECK-NEXT: sshl v2.4s, v1.4s, v2.4s
; CHECK-NEXT: usra v2.4s, v1.4s, #31 ; CHECK-NEXT: usra v2.4s, v1.4s, #31
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI13_3] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI13_3]
; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s ; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s
; CHECK-NEXT: movi v1.4s, #1 ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 5, i32 5, i32 2147483648, i32 5> %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 2147483648, i32 5>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One INT_MIN divisor in even divisor ; One INT_MIN divisor in even divisor
define <4 x i32> @test_srem_even_INT_MIN(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_even_INT_MIN: ; CHECK-LABEL: test_srem_even_INT_MIN:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI14_0 ; CHECK-NEXT: adrp x8, .LCPI14_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]
; CHECK-NEXT: adrp x8, .LCPI14_1 ; CHECK-NEXT: adrp x8, .LCPI14_1
; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s ; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s
; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI14_1]
; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI14_1]
; CHECK-NEXT: adrp x8, .LCPI14_2 ; CHECK-NEXT: adrp x8, .LCPI14_2
; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI14_2] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI14_2]
; CHECK-NEXT: adrp x8, .LCPI14_3 ; CHECK-NEXT: adrp x8, .LCPI14_3
; CHECK-NEXT: mla v1.4s, v0.4s, v3.4s
; CHECK-NEXT: sshl v2.4s, v1.4s, v2.4s ; CHECK-NEXT: sshl v2.4s, v1.4s, v2.4s
; CHECK-NEXT: usra v2.4s, v1.4s, #31 ; CHECK-NEXT: usra v2.4s, v1.4s, #31
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_3] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_3]
; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s ; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s
; CHECK-NEXT: movi v1.4s, #1 ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 14, i32 14, i32 2147483648, i32 14> %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 2147483648, i32 14>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One INT_MIN divisor in odd+even divisor ; One INT_MIN divisor in odd+even divisor
define <4 x i32> @test_srem_odd_even_INT_MIN(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_even_INT_MIN: ; CHECK-LABEL: test_srem_odd_even_INT_MIN:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI15_0 ; CHECK-NEXT: adrp x8, .LCPI15_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]
; CHECK-NEXT: adrp x8, .LCPI15_1 ; CHECK-NEXT: adrp x8, .LCPI15_1
; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s ; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s
; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI15_1]
; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI15_1]
; CHECK-NEXT: adrp x8, .LCPI15_2 ; CHECK-NEXT: adrp x8, .LCPI15_2
; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI15_2] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI15_2]
; CHECK-NEXT: adrp x8, .LCPI15_3 ; CHECK-NEXT: adrp x8, .LCPI15_3
; CHECK-NEXT: mla v1.4s, v0.4s, v3.4s
; CHECK-NEXT: sshl v2.4s, v1.4s, v2.4s ; CHECK-NEXT: sshl v2.4s, v1.4s, v2.4s
; CHECK-NEXT: usra v2.4s, v1.4s, #31 ; CHECK-NEXT: usra v2.4s, v1.4s, #31
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_3] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_3]
; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s ; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s
; CHECK-NEXT: movi v1.4s, #1 ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 5, i32 14, i32 2147483648, i32 100> %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 2147483648, i32 100>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;==============================================================================; ;==============================================================================;
; One all-ones divisor and power-of-two divisor divisor in odd divisor ; One all-ones divisor and power-of-two divisor divisor in odd divisor
define <4 x i32> @test_srem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_allones_and_poweroftwo: ; CHECK-LABEL: test_srem_odd_allones_and_poweroftwo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI16_0 ; CHECK-NEXT: adrp x8, .LCPI16_0
; CHECK-NEXT: adrp x9, .LCPI16_1 ; CHECK-NEXT: adrp x9, .LCPI16_1
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
; CHECK-NEXT: adrp x8, .LCPI16_2 ; CHECK-NEXT: adrp x8, .LCPI16_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI16_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI16_1]
; CHECK-NEXT: adrp x9, .LCPI16_3 ; CHECK-NEXT: adrp x9, .LCPI16_3
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI16_2] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI16_2]
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI16_3] ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI16_3]
; CHECK-NEXT: adrp x8, .LCPI16_4 ; CHECK-NEXT: adrp x8, .LCPI16_4
; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s ; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI16_4] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI16_4]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 5> %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 5>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One all-ones divisor and power-of-two divisor divisor in even divisor ; One all-ones divisor and power-of-two divisor divisor in even divisor
define <4 x i32> @test_srem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_even_allones_and_poweroftwo: ; CHECK-LABEL: test_srem_even_allones_and_poweroftwo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI17_0 ; CHECK-NEXT: adrp x8, .LCPI17_0
; CHECK-NEXT: adrp x9, .LCPI17_1 ; CHECK-NEXT: adrp x9, .LCPI17_1
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_0]
; CHECK-NEXT: adrp x8, .LCPI17_2 ; CHECK-NEXT: adrp x8, .LCPI17_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI17_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI17_1]
; CHECK-NEXT: adrp x9, .LCPI17_3 ; CHECK-NEXT: adrp x9, .LCPI17_3
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI17_2] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI17_2]
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI17_3] ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI17_3]
; CHECK-NEXT: adrp x8, .LCPI17_4 ; CHECK-NEXT: adrp x8, .LCPI17_4
; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s ; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI17_4] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI17_4]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 14> %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 14>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One all-ones divisor and power-of-two divisor divisor in odd+even divisor ; One all-ones divisor and power-of-two divisor divisor in odd+even divisor
define <4 x i32> @test_srem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_even_allones_and_poweroftwo: ; CHECK-LABEL: test_srem_odd_even_allones_and_poweroftwo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI18_0 ; CHECK-NEXT: adrp x8, .LCPI18_0
; CHECK-NEXT: adrp x9, .LCPI18_1 ; CHECK-NEXT: adrp x9, .LCPI18_1
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI18_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI18_0]
; CHECK-NEXT: adrp x8, .LCPI18_2 ; CHECK-NEXT: adrp x8, .LCPI18_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI18_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI18_1]
; CHECK-NEXT: adrp x9, .LCPI18_3 ; CHECK-NEXT: adrp x9, .LCPI18_3
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI18_2] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI18_2]
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI18_3] ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI18_3]
; CHECK-NEXT: adrp x8, .LCPI18_4 ; CHECK-NEXT: adrp x8, .LCPI18_4
; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s ; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI18_4] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI18_4]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 100> %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 100>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
Show All 24 Lines
; One all-ones divisor and one one divisor in even divisor ; One all-ones divisor and one one divisor in even divisor
define <4 x i32> @test_srem_even_allones_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_even_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_even_allones_and_one: ; CHECK-LABEL: test_srem_even_allones_and_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #28087 ; CHECK-NEXT: mov w8, #28087
; CHECK-NEXT: mov w9, #9362 ; CHECK-NEXT: mov w9, #9362
; CHECK-NEXT: movk w8, #46811, lsl #16 ; CHECK-NEXT: movk w8, #46811, lsl #16
; CHECK-NEXT: movk w9, #4681, lsl #16 ; CHECK-NEXT: movk w9, #4681, lsl #16
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: dup v1.4s, w8 ; CHECK-NEXT: dup v1.4s, w8
; CHECK-NEXT: dup v2.4s, w9 ; CHECK-NEXT: dup v2.4s, w9
; CHECK-NEXT: adrp x8, .LCPI20_0 ; CHECK-NEXT: adrp x8, .LCPI20_0
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: shl v0.4s, v2.4s, #31 ; CHECK-NEXT: shl v0.4s, v2.4s, #31
; CHECK-NEXT: ushr v1.4s, v2.4s, #1 ; CHECK-NEXT: ushr v1.4s, v2.4s, #1
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI20_0] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI20_0]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 1, i32 14> %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 1, i32 14>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One all-ones divisor and one one divisor in odd+even divisor ; One all-ones divisor and one one divisor in odd+even divisor
define <4 x i32> @test_srem_odd_even_allones_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_even_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_even_allones_and_one: ; CHECK-LABEL: test_srem_odd_even_allones_and_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI21_0 ; CHECK-NEXT: adrp x8, .LCPI21_0
; CHECK-NEXT: adrp x9, .LCPI21_1 ; CHECK-NEXT: adrp x9, .LCPI21_1
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI21_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI21_0]
; CHECK-NEXT: adrp x8, .LCPI21_2 ; CHECK-NEXT: adrp x8, .LCPI21_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI21_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI21_1]
; CHECK-NEXT: adrp x9, .LCPI21_3 ; CHECK-NEXT: adrp x9, .LCPI21_3
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI21_2] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI21_2]
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI21_3] ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI21_3]
; CHECK-NEXT: adrp x8, .LCPI21_4 ; CHECK-NEXT: adrp x8, .LCPI21_4
; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s ; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI21_4] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI21_4]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 100> %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 100>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; One power-of-two divisor divisor and one divisor in odd divisor ; One power-of-two divisor divisor and one divisor in odd divisor
define <4 x i32> @test_srem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_poweroftwo_and_one: ; CHECK-LABEL: test_srem_odd_poweroftwo_and_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI22_0 ; CHECK-NEXT: adrp x8, .LCPI22_0
; CHECK-NEXT: adrp x9, .LCPI22_1 ; CHECK-NEXT: adrp x9, .LCPI22_1
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI22_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI22_0]
; CHECK-NEXT: adrp x8, .LCPI22_2 ; CHECK-NEXT: adrp x8, .LCPI22_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI22_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI22_1]
; CHECK-NEXT: adrp x9, .LCPI22_3 ; CHECK-NEXT: adrp x9, .LCPI22_3
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI22_2] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI22_2]
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI22_3] ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI22_3]
; CHECK-NEXT: adrp x8, .LCPI22_4 ; CHECK-NEXT: adrp x8, .LCPI22_4
; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s ; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI22_4] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI22_4]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 5> %srem = srem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 5>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One power-of-two divisor divisor and one divisor in even divisor ; One power-of-two divisor divisor and one divisor in even divisor
define <4 x i32> @test_srem_even_poweroftwo_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_even_poweroftwo_and_one: ; CHECK-LABEL: test_srem_even_poweroftwo_and_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI23_0 ; CHECK-NEXT: adrp x8, .LCPI23_0
; CHECK-NEXT: adrp x9, .LCPI23_1 ; CHECK-NEXT: adrp x9, .LCPI23_1
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI23_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI23_0]
; CHECK-NEXT: adrp x8, .LCPI23_2 ; CHECK-NEXT: adrp x8, .LCPI23_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI23_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI23_1]
; CHECK-NEXT: adrp x9, .LCPI23_3 ; CHECK-NEXT: adrp x9, .LCPI23_3
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI23_2] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI23_2]
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI23_3] ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI23_3]
; CHECK-NEXT: adrp x8, .LCPI23_4 ; CHECK-NEXT: adrp x8, .LCPI23_4
; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s ; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI23_4] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI23_4]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 14, i32 16, i32 1, i32 14> %srem = srem <4 x i32> %X, <i32 14, i32 16, i32 1, i32 14>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One power-of-two divisor divisor and one divisor in odd+even divisor ; One power-of-two divisor divisor and one divisor in odd+even divisor
define <4 x i32> @test_srem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_even_poweroftwo_and_one: ; CHECK-LABEL: test_srem_odd_even_poweroftwo_and_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI24_0 ; CHECK-NEXT: adrp x8, .LCPI24_0
; CHECK-NEXT: adrp x9, .LCPI24_1 ; CHECK-NEXT: adrp x9, .LCPI24_1
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI24_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI24_0]
; CHECK-NEXT: adrp x8, .LCPI24_2 ; CHECK-NEXT: adrp x8, .LCPI24_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI24_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI24_1]
; CHECK-NEXT: adrp x9, .LCPI24_3 ; CHECK-NEXT: adrp x9, .LCPI24_3
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI24_2] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI24_2]
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI24_3] ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI24_3]
; CHECK-NEXT: adrp x8, .LCPI24_4 ; CHECK-NEXT: adrp x8, .LCPI24_4
; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s ; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI24_4] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI24_4]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 100> %srem = srem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 100>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
define <4 x i32> @test_srem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_allones_and_poweroftwo_and_one: ; CHECK-LABEL: test_srem_odd_allones_and_poweroftwo_and_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI25_0 ; CHECK-NEXT: adrp x8, .LCPI25_0
; CHECK-NEXT: adrp x9, .LCPI25_1 ; CHECK-NEXT: adrp x9, .LCPI25_1
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI25_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI25_0]
; CHECK-NEXT: adrp x8, .LCPI25_2 ; CHECK-NEXT: adrp x8, .LCPI25_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI25_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI25_1]
; CHECK-NEXT: adrp x9, .LCPI25_3 ; CHECK-NEXT: adrp x9, .LCPI25_3
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI25_2] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI25_2]
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI25_3] ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI25_3]
; CHECK-NEXT: adrp x8, .LCPI25_4 ; CHECK-NEXT: adrp x8, .LCPI25_4
; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s ; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI25_4] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI25_4]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 1> %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 1>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
define <4 x i32> @test_srem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_even_allones_and_poweroftwo_and_one: ; CHECK-LABEL: test_srem_even_allones_and_poweroftwo_and_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI26_0 ; CHECK-NEXT: adrp x8, .LCPI26_0
; CHECK-NEXT: adrp x9, .LCPI26_1 ; CHECK-NEXT: adrp x9, .LCPI26_1
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI26_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI26_0]
; CHECK-NEXT: adrp x8, .LCPI26_2 ; CHECK-NEXT: adrp x8, .LCPI26_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI26_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI26_1]
; CHECK-NEXT: adrp x9, .LCPI26_3 ; CHECK-NEXT: adrp x9, .LCPI26_3
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI26_2] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI26_2]
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI26_3] ; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI26_3]
; CHECK-NEXT: adrp x8, .LCPI26_4 ; CHECK-NEXT: adrp x8, .LCPI26_4
; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s ; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI26_4] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI26_4]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 1> %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 1>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }

llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll

Show All 27 Lines
; Even divisors ; Even divisors
define <4 x i32> @test_srem_even_100(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_even_100(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_even_100: ; CHECK-LABEL: test_srem_even_100:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #23593 ; CHECK-NEXT: mov w8, #23593
; CHECK-NEXT: mov w9, #47184 ; CHECK-NEXT: mov w9, #47184
; CHECK-NEXT: movk w8, #49807, lsl #16 ; CHECK-NEXT: movk w8, #49807, lsl #16
; CHECK-NEXT: movk w9, #1310, lsl #16 ; CHECK-NEXT: movk w9, #1310, lsl #16
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: dup v1.4s, w8 ; CHECK-NEXT: dup v1.4s, w8
; CHECK-NEXT: dup v2.4s, w9 ; CHECK-NEXT: dup v2.4s, w9
; CHECK-NEXT: mov w8, #23592 ; CHECK-NEXT: mov w8, #23592
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: movk w8, #655, lsl #16 ; CHECK-NEXT: movk w8, #655, lsl #16
; CHECK-NEXT: shl v0.4s, v2.4s, #30 ; CHECK-NEXT: shl v0.4s, v2.4s, #30
; CHECK-NEXT: ushr v1.4s, v2.4s, #2 ; CHECK-NEXT: ushr v1.4s, v2.4s, #2
; CHECK-NEXT: dup v2.4s, w8 ; CHECK-NEXT: dup v2.4s, w8
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 100, i32 100, i32 100, i32 100> %srem = srem <4 x i32> %X, <i32 100, i32 100, i32 100, i32 100>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; Negative divisors should be negated, and thus this is still splat vectors. ; Negative divisors should be negated, and thus this is still splat vectors.
Show All 25 Lines
; Even divisors ; Even divisors
define <4 x i32> @test_srem_even_neg100(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_even_neg100(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_even_neg100: ; CHECK-LABEL: test_srem_even_neg100:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #23593 ; CHECK-NEXT: mov w8, #23593
; CHECK-NEXT: mov w9, #47184 ; CHECK-NEXT: mov w9, #47184
; CHECK-NEXT: movk w8, #49807, lsl #16 ; CHECK-NEXT: movk w8, #49807, lsl #16
; CHECK-NEXT: movk w9, #1310, lsl #16 ; CHECK-NEXT: movk w9, #1310, lsl #16
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: dup v1.4s, w8 ; CHECK-NEXT: dup v1.4s, w8
; CHECK-NEXT: dup v2.4s, w9 ; CHECK-NEXT: dup v2.4s, w9
; CHECK-NEXT: mov w8, #23592 ; CHECK-NEXT: mov w8, #23592
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
; CHECK-NEXT: movk w8, #655, lsl #16 ; CHECK-NEXT: movk w8, #655, lsl #16
; CHECK-NEXT: shl v0.4s, v2.4s, #30 ; CHECK-NEXT: shl v0.4s, v2.4s, #30
; CHECK-NEXT: ushr v1.4s, v2.4s, #2 ; CHECK-NEXT: ushr v1.4s, v2.4s, #2
; CHECK-NEXT: dup v2.4s, w8 ; CHECK-NEXT: dup v2.4s, w8
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 -100, i32 100, i32 -100, i32 100> %srem = srem <4 x i32> %X, <i32 -100, i32 100, i32 -100, i32 100>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; Comparison constant has undef elements. ; Comparison constant has undef elements.
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
define <4 x i32> @test_srem_odd_undef1(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_undef1(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_odd_undef1: ; CHECK-LABEL: test_srem_odd_undef1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #34079 ; CHECK-NEXT: mov w8, #34079
; CHECK-NEXT: movk w8, #20971, lsl #16 ; CHECK-NEXT: movk w8, #20971, lsl #16
; CHECK-NEXT: movi v3.4s, #25
; CHECK-NEXT: dup v1.4s, w8 ; CHECK-NEXT: dup v1.4s, w8
; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s ; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s
; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s
; CHECK-NEXT: sshr v2.4s, v1.4s, #3 ; CHECK-NEXT: sshr v2.4s, v1.4s, #3
; CHECK-NEXT: usra v2.4s, v1.4s, #31 ; CHECK-NEXT: usra v2.4s, v1.4s, #31
; CHECK-NEXT: movi v1.4s, #25
; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s
; CHECK-NEXT: movi v1.4s, #1 ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: mls v0.4s, v2.4s, v3.4s
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 25, i32 25, i32 25, i32 25> %srem = srem <4 x i32> %X, <i32 25, i32 25, i32 25, i32 25>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 undef, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 undef, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
define <4 x i32> @test_srem_even_undef1(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_even_undef1(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_even_undef1: ; CHECK-LABEL: test_srem_even_undef1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #34079 ; CHECK-NEXT: mov w8, #34079
; CHECK-NEXT: movk w8, #20971, lsl #16 ; CHECK-NEXT: movk w8, #20971, lsl #16
; CHECK-NEXT: movi v3.4s, #100
; CHECK-NEXT: dup v1.4s, w8 ; CHECK-NEXT: dup v1.4s, w8
; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s ; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s
; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s
; CHECK-NEXT: sshr v2.4s, v1.4s, #5 ; CHECK-NEXT: sshr v2.4s, v1.4s, #5
; CHECK-NEXT: usra v2.4s, v1.4s, #31 ; CHECK-NEXT: usra v2.4s, v1.4s, #31
; CHECK-NEXT: movi v1.4s, #100
; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s
; CHECK-NEXT: movi v1.4s, #1 ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: mls v0.4s, v2.4s, v3.4s
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 100, i32 100, i32 100, i32 100> %srem = srem <4 x i32> %X, <i32 100, i32 100, i32 100, i32 100>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 undef, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 undef, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
Show All 22 Lines; CHECK-NEXT: ret
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; We can lower remainder of division by powers of two much better elsewhere. ; We can lower remainder of division by powers of two much better elsewhere.
define <4 x i32> @test_srem_pow2(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_pow2(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_pow2: ; CHECK-LABEL: test_srem_pow2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmlt v3.4s, v0.4s, #0 ; CHECK-NEXT: cmlt v2.4s, v0.4s, #0
; CHECK-NEXT: mov v2.16b, v0.16b ; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: usra v2.4s, v3.4s, #28 ; CHECK-NEXT: usra v1.4s, v2.4s, #28
; CHECK-NEXT: bic v1.4s, #15
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: movi v1.4s, #1 ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: bic v2.4s, #15
; CHECK-NEXT: sub v0.4s, v0.4s, v2.4s
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 16, i32 16, i32 16, i32 16> %srem = srem <4 x i32> %X, <i32 16, i32 16, i32 16, i32 16>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; We could lower remainder of division by INT_MIN much better elsewhere. ; We could lower remainder of division by INT_MIN much better elsewhere.
define <4 x i32> @test_srem_int_min(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_int_min(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_srem_int_min: ; CHECK-LABEL: test_srem_int_min:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmlt v2.4s, v0.4s, #0 ; CHECK-NEXT: cmlt v2.4s, v0.4s, #0
; CHECK-NEXT: mov v1.16b, v0.16b ; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: movi v3.4s, #128, lsl #24
; CHECK-NEXT: usra v1.4s, v2.4s, #1 ; CHECK-NEXT: usra v1.4s, v2.4s, #1
; CHECK-NEXT: and v1.16b, v1.16b, v3.16b ; CHECK-NEXT: movi v2.4s, #128, lsl #24
; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: movi v1.4s, #1 ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem <4 x i32> %X, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648> %srem = srem <4 x i32> %X, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
Show All 14 Lines

llvm/test/CodeGen/AArch64/srem-vector-lkk.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) { define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; CHECK-LABEL: fold_srem_vec_1: ; CHECK-LABEL: fold_srem_vec_1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #33437
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: smov w8, v0.h[1] ; CHECK-NEXT: smov w9, v0.h[2]
; CHECK-NEXT: smov w9, v0.h[0] ; CHECK-NEXT: movk w8, #21399, lsl #16
; CHECK-NEXT: mov w10, #63421 ; CHECK-NEXT: mov w10, #37253
; CHECK-NEXT: mov w11, #37253 ; CHECK-NEXT: movk w10, #44150, lsl #16
; CHECK-NEXT: movk w10, #31710, lsl #16 ; CHECK-NEXT: smov w11, v0.h[0]
; CHECK-NEXT: movk w11, #44150, lsl #16 ; CHECK-NEXT: smull x8, w9, w8
; CHECK-NEXT: smov w13, v0.h[2] ; CHECK-NEXT: mov w12, #63421
; CHECK-NEXT: mov w12, #33437 ; CHECK-NEXT: smull x10, w11, w10
; CHECK-NEXT: smull x10, w8, w10 ; CHECK-NEXT: movk w12, #31710, lsl #16
; CHECK-NEXT: movk w12, #21399, lsl #16 ; CHECK-NEXT: lsr x13, x8, #63
; CHECK-NEXT: smull x11, w9, w11 ; CHECK-NEXT: asr x8, x8, #37
; CHECK-NEXT: smov w14, v0.h[1]
; CHECK-NEXT: add w8, w8, w13
; CHECK-NEXT: mov w13, #98
; CHECK-NEXT: lsr x10, x10, #32 ; CHECK-NEXT: lsr x10, x10, #32
; CHECK-NEXT: lsr x11, x11, #32 ; CHECK-NEXT: smull x12, w14, w12
; CHECK-NEXT: sub w10, w10, w8 ; CHECK-NEXT: add w10, w10, w11
; CHECK-NEXT: add w11, w11, w9 ; CHECK-NEXT: msub w8, w8, w13, w9
; CHECK-NEXT: asr w14, w10, #6 ; CHECK-NEXT: asr w9, w10, #6
; CHECK-NEXT: asr w15, w11, #6 ; CHECK-NEXT: mov w13, #95
; CHECK-NEXT: add w10, w14, w10, lsr #31 ; CHECK-NEXT: add w9, w9, w10, lsr #31
; CHECK-NEXT: add w11, w15, w11, lsr #31 ; CHECK-NEXT: lsr x12, x12, #32
; CHECK-NEXT: mov w14, #95 ; CHECK-NEXT: mov w10, #63249
; CHECK-NEXT: mov w15, #-124 ; CHECK-NEXT: sub w12, w12, w14
; CHECK-NEXT: smull x12, w13, w12 ; CHECK-NEXT: movk w10, #48808, lsl #16
; CHECK-NEXT: msub w9, w11, w14, w9 ; CHECK-NEXT: msub w9, w9, w13, w11
; CHECK-NEXT: msub w8, w10, w15, w8 ; CHECK-NEXT: smov w11, v0.h[3]
; CHECK-NEXT: lsr x10, x12, #63 ; CHECK-NEXT: asr w13, w12, #6
; CHECK-NEXT: asr x11, x12, #37 ; CHECK-NEXT: add w12, w13, w12, lsr #31
; CHECK-NEXT: smov w12, v0.h[3] ; CHECK-NEXT: mov w13, #-124
; CHECK-NEXT: add w10, w11, w10 ; CHECK-NEXT: smull x10, w11, w10
; CHECK-NEXT: mov w11, #98 ; CHECK-NEXT: msub w12, w12, w13, w14
; CHECK-NEXT: fmov s0, w9 ; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: mov w9, #63249 ; CHECK-NEXT: lsr x9, x10, #63
; CHECK-NEXT: movk w9, #48808, lsl #16 ; CHECK-NEXT: asr x10, x10, #40
; CHECK-NEXT: msub w10, w10, w11, w13 ; CHECK-NEXT: add w9, w10, w9
; CHECK-NEXT: smull x9, w12, w9 ; CHECK-NEXT: mov w10, #-1003
; CHECK-NEXT: mov v0.h[1], w8 ; CHECK-NEXT: mov v0.h[1], w12
; CHECK-NEXT: lsr x8, x9, #63 ; CHECK-NEXT: msub w9, w9, w10, w11
; CHECK-NEXT: asr x9, x9, #40 ; CHECK-NEXT: mov v0.h[2], w8
; CHECK-NEXT: add w8, w9, w8 ; CHECK-NEXT: mov v0.h[3], w9
; CHECK-NEXT: mov w9, #-1003
; CHECK-NEXT: mov v0.h[2], w10
; CHECK-NEXT: msub w8, w8, w9, w12
; CHECK-NEXT: mov v0.h[3], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003> %1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003>
ret <4 x i16> %1 ret <4 x i16> %1
} }
define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) { define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
; CHECK-LABEL: fold_srem_vec_2: ; CHECK-LABEL: fold_srem_vec_2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #37253
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: smov w9, v0.h[0] ; CHECK-NEXT: smov w9, v0.h[0]
; CHECK-NEXT: mov w8, #37253
; CHECK-NEXT: movk w8, #44150, lsl #16 ; CHECK-NEXT: movk w8, #44150, lsl #16
; CHECK-NEXT: smov w10, v0.h[1] ; CHECK-NEXT: smov w10, v0.h[1]
; CHECK-NEXT: smov w14, v0.h[2] ; CHECK-NEXT: smov w13, v0.h[2]
; CHECK-NEXT: mov w12, #95 ; CHECK-NEXT: mov w12, #95
; CHECK-NEXT: smull x11, w9, w8 ; CHECK-NEXT: smull x11, w9, w8
; CHECK-NEXT: smull x13, w10, w8
; CHECK-NEXT: lsr x11, x11, #32
; CHECK-NEXT: add w11, w11, w9
; CHECK-NEXT: lsr x13, x13, #32
; CHECK-NEXT: asr w15, w11, #6
; CHECK-NEXT: add w13, w13, w10
; CHECK-NEXT: add w11, w15, w11, lsr #31
; CHECK-NEXT: smov w15, v0.h[3] ; CHECK-NEXT: smov w15, v0.h[3]
; CHECK-NEXT: asr w16, w13, #6 ; CHECK-NEXT: smull x14, w10, w8
; CHECK-NEXT: msub w9, w11, w12, w9
; CHECK-NEXT: add w13, w16, w13, lsr #31
; CHECK-NEXT: smull x11, w14, w8
; CHECK-NEXT: msub w10, w13, w12, w10
; CHECK-NEXT: lsr x11, x11, #32 ; CHECK-NEXT: lsr x11, x11, #32
; CHECK-NEXT: add w11, w11, w9
; CHECK-NEXT: lsr x14, x14, #32
; CHECK-NEXT: asr w16, w11, #6
; CHECK-NEXT: add w14, w14, w10
; CHECK-NEXT: add w11, w16, w11, lsr #31
; CHECK-NEXT: smull x16, w13, w8
; CHECK-NEXT: asr w17, w14, #6
; CHECK-NEXT: smull x8, w15, w8 ; CHECK-NEXT: smull x8, w15, w8
; CHECK-NEXT: add w11, w11, w14 ; CHECK-NEXT: add w14, w17, w14, lsr #31
; CHECK-NEXT: fmov s0, w9 ; CHECK-NEXT: msub w9, w11, w12, w9
; CHECK-NEXT: asr w9, w11, #6 ; CHECK-NEXT: lsr x11, x16, #32
; CHECK-NEXT: lsr x8, x8, #32 ; CHECK-NEXT: lsr x8, x8, #32
; CHECK-NEXT: add w9, w9, w11, lsr #31 ; CHECK-NEXT: add w11, w11, w13
; CHECK-NEXT: msub w10, w14, w12, w10
; CHECK-NEXT: asr w14, w11, #6
; CHECK-NEXT: add w8, w8, w15 ; CHECK-NEXT: add w8, w8, w15
; CHECK-NEXT: add w11, w14, w11, lsr #31
; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: asr w9, w8, #6
; CHECK-NEXT: msub w11, w11, w12, w13
; CHECK-NEXT: add w8, w9, w8, lsr #31
; CHECK-NEXT: mov v0.h[1], w10 ; CHECK-NEXT: mov v0.h[1], w10
; CHECK-NEXT: asr w10, w8, #6
; CHECK-NEXT: msub w9, w9, w12, w14
; CHECK-NEXT: add w8, w10, w8, lsr #31
; CHECK-NEXT: msub w8, w8, w12, w15 ; CHECK-NEXT: msub w8, w8, w12, w15
; CHECK-NEXT: mov v0.h[2], w9 ; CHECK-NEXT: mov v0.h[2], w11
; CHECK-NEXT: mov v0.h[3], w8 ; CHECK-NEXT: mov v0.h[3], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if we can combine srem with sdiv. ; Don't fold if we can combine srem with sdiv.
define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) { define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
; CHECK-LABEL: combine_srem_sdiv: ; CHECK-LABEL: combine_srem_sdiv:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #37253
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: smov w9, v0.h[0] ; CHECK-NEXT: smov w9, v0.h[0]
; CHECK-NEXT: mov w8, #37253
; CHECK-NEXT: movk w8, #44150, lsl #16 ; CHECK-NEXT: movk w8, #44150, lsl #16
; CHECK-NEXT: smov w10, v0.h[1] ; CHECK-NEXT: smov w11, v0.h[1]
; CHECK-NEXT: smov w11, v0.h[2] ; CHECK-NEXT: smov w12, v0.h[2]
; CHECK-NEXT: smov w12, v0.h[3] ; CHECK-NEXT: mov w10, #95
; CHECK-NEXT: mov w14, #95
; CHECK-NEXT: smull x13, w9, w8 ; CHECK-NEXT: smull x13, w9, w8
; CHECK-NEXT: smull x15, w10, w8 ; CHECK-NEXT: smov w14, v0.h[3]
; CHECK-NEXT: smull x15, w11, w8
; CHECK-NEXT: lsr x13, x13, #32 ; CHECK-NEXT: lsr x13, x13, #32
; CHECK-NEXT: smull x16, w11, w8 ; CHECK-NEXT: smull x16, w12, w8
; CHECK-NEXT: add w13, w13, w9 ; CHECK-NEXT: add w13, w13, w9
; CHECK-NEXT: lsr x15, x15, #32 ; CHECK-NEXT: lsr x15, x15, #32
; CHECK-NEXT: asr w17, w13, #6 ; CHECK-NEXT: asr w17, w13, #6
; CHECK-NEXT: add w15, w15, w10 ; CHECK-NEXT: add w15, w15, w11
; CHECK-NEXT: add w13, w17, w13, lsr #31 ; CHECK-NEXT: add w13, w17, w13, lsr #31
; CHECK-NEXT: smull x8, w14, w8
; CHECK-NEXT: lsr x16, x16, #32
; CHECK-NEXT: asr w17, w15, #6 ; CHECK-NEXT: asr w17, w15, #6
; CHECK-NEXT: msub w9, w13, w10, w9
; CHECK-NEXT: add w16, w16, w12
; CHECK-NEXT: add w15, w17, w15, lsr #31 ; CHECK-NEXT: add w15, w17, w15, lsr #31
; CHECK-NEXT: smull x8, w12, w8
; CHECK-NEXT: msub w9, w13, w14, w9
; CHECK-NEXT: lsr x16, x16, #32
; CHECK-NEXT: add w16, w16, w11
; CHECK-NEXT: msub w10, w15, w14, w10
; CHECK-NEXT: asr w17, w16, #6 ; CHECK-NEXT: asr w17, w16, #6
; CHECK-NEXT: lsr x8, x8, #32 ; CHECK-NEXT: lsr x8, x8, #32
; CHECK-NEXT: fmov s1, w13
; CHECK-NEXT: add w16, w17, w16, lsr #31 ; CHECK-NEXT: add w16, w17, w16, lsr #31
; CHECK-NEXT: msub w11, w15, w10, w11
; CHECK-NEXT: add w8, w8, w14
; CHECK-NEXT: fmov s0, w9 ; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: add w8, w8, w12 ; CHECK-NEXT: fmov s1, w13
; CHECK-NEXT: asr w9, w8, #6 ; CHECK-NEXT: asr w9, w8, #6
; CHECK-NEXT: add w8, w9, w8, lsr #31 ; CHECK-NEXT: add w8, w9, w8, lsr #31
; CHECK-NEXT: msub w9, w16, w14, w11 ; CHECK-NEXT: msub w9, w16, w10, w12
; CHECK-NEXT: mov v0.h[1], w10 ; CHECK-NEXT: mov v0.h[1], w11
; CHECK-NEXT: mov v1.h[1], w15 ; CHECK-NEXT: mov v1.h[1], w15
; CHECK-NEXT: msub w10, w8, w14, w12 ; CHECK-NEXT: msub w10, w8, w10, w14
; CHECK-NEXT: mov v0.h[2], w9
; CHECK-NEXT: mov v1.h[2], w16 ; CHECK-NEXT: mov v1.h[2], w16
; CHECK-NEXT: mov v0.h[3], w10 ; CHECK-NEXT: mov v0.h[2], w9
; CHECK-NEXT: mov v1.h[3], w8 ; CHECK-NEXT: mov v1.h[3], w8
; CHECK-NEXT: mov v0.h[3], w10
; CHECK-NEXT: add v0.4h, v0.4h, v1.4h ; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
%2 = sdiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %2 = sdiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
%3 = add <4 x i16> %1, %2 %3 = add <4 x i16> %1, %2
ret <4 x i16> %3 ret <4 x i16> %3
} }
; Don't fold for divisors that are a power of two. ; Don't fold for divisors that are a power of two.
define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) { define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
; CHECK-LABEL: dont_fold_srem_power_of_two: ; CHECK-LABEL: dont_fold_srem_power_of_two:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: smov w9, v0.h[1] ; CHECK-NEXT: smov w9, v0.h[1]
; CHECK-NEXT: smov w10, v0.h[0] ; CHECK-NEXT: smov w10, v0.h[0]
; CHECK-NEXT: mov w8, #37253 ; CHECK-NEXT: mov w8, #37253
; CHECK-NEXT: movk w8, #44150, lsl #16 ; CHECK-NEXT: smov w11, v0.h[3]
; CHECK-NEXT: add w11, w9, #31 ; CHECK-NEXT: add w12, w9, #31
; CHECK-NEXT: cmp w9, #0 ; CHECK-NEXT: cmp w9, #0
; CHECK-NEXT: add w12, w10, #63 ; CHECK-NEXT: movk w8, #44150, lsl #16
; CHECK-NEXT: csel w11, w11, w9, lt ; CHECK-NEXT: add w13, w10, #63
; CHECK-NEXT: csel w12, w12, w9, lt
; CHECK-NEXT: cmp w10, #0 ; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: and w11, w11, #0xffffffe0 ; CHECK-NEXT: and w12, w12, #0xffffffe0
; CHECK-NEXT: csel w12, w12, w10, lt ; CHECK-NEXT: csel w13, w13, w10, lt
; CHECK-NEXT: sub w9, w9, w11 ; CHECK-NEXT: sub w9, w9, w12
; CHECK-NEXT: and w12, w12, #0xffffffc0 ; CHECK-NEXT: smov w12, v0.h[2]
; CHECK-NEXT: sub w10, w10, w12 ; CHECK-NEXT: and w13, w13, #0xffffffc0
; CHECK-NEXT: smov w12, v0.h[3] ; CHECK-NEXT: smull x8, w11, w8
; CHECK-NEXT: fmov s1, w10 ; CHECK-NEXT: sub w10, w10, w13
; CHECK-NEXT: smov w10, v0.h[2] ; CHECK-NEXT: add w13, w12, #7
; CHECK-NEXT: smull x8, w12, w8 ; CHECK-NEXT: cmp w12, #0
; CHECK-NEXT: mov v1.h[1], w9
; CHECK-NEXT: lsr x8, x8, #32 ; CHECK-NEXT: lsr x8, x8, #32
; CHECK-NEXT: add w9, w10, #7 ; CHECK-NEXT: csel w13, w13, w12, lt
; CHECK-NEXT: cmp w10, #0 ; CHECK-NEXT: add w8, w8, w11
; CHECK-NEXT: csel w9, w9, w10, lt ; CHECK-NEXT: fmov s0, w10
; CHECK-NEXT: add w8, w8, w12 ; CHECK-NEXT: and w10, w13, #0xfffffff8
; CHECK-NEXT: and w9, w9, #0xfffffff8 ; CHECK-NEXT: asr w13, w8, #6
; CHECK-NEXT: sub w9, w10, w9 ; CHECK-NEXT: sub w10, w12, w10
; CHECK-NEXT: asr w10, w8, #6 ; CHECK-NEXT: add w8, w13, w8, lsr #31
; CHECK-NEXT: add w8, w10, w8, lsr #31 ; CHECK-NEXT: mov w13, #95
; CHECK-NEXT: mov w10, #95 ; CHECK-NEXT: mov v0.h[1], w9
; CHECK-NEXT: mov v1.h[2], w9 ; CHECK-NEXT: msub w8, w8, w13, w11
; CHECK-NEXT: msub w8, w8, w10, w12 ; CHECK-NEXT: mov v0.h[2], w10
; CHECK-NEXT: mov v1.h[3], w8 ; CHECK-NEXT: mov v0.h[3], w8
; CHECK-NEXT: fmov d0, d1 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = srem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95> %1 = srem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is one. ; Don't fold if the divisor is one.
define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) { define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; CHECK-LABEL: dont_fold_srem_one: ; CHECK-LABEL: dont_fold_srem_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #17097
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: smov w8, v0.h[1]
; CHECK-NEXT: smov w9, v0.h[2] ; CHECK-NEXT: smov w9, v0.h[2]
; CHECK-NEXT: movk w8, #45590, lsl #16
; CHECK-NEXT: mov w10, #30865 ; CHECK-NEXT: mov w10, #30865
; CHECK-NEXT: mov w11, #17097
; CHECK-NEXT: movk w10, #51306, lsl #16 ; CHECK-NEXT: movk w10, #51306, lsl #16
; CHECK-NEXT: movk w11, #45590, lsl #16 ; CHECK-NEXT: smov w11, v0.h[1]
; CHECK-NEXT: mov w12, #654 ; CHECK-NEXT: smull x8, w9, w8
; CHECK-NEXT: smull x10, w8, w10 ; CHECK-NEXT: mov w13, #23
; CHECK-NEXT: smull x11, w9, w11 ; CHECK-NEXT: smull x10, w11, w10
; CHECK-NEXT: lsr x8, x8, #32
; CHECK-NEXT: add w8, w8, w9
; CHECK-NEXT: lsr x10, x10, #32 ; CHECK-NEXT: lsr x10, x10, #32
; CHECK-NEXT: lsr x11, x11, #32 ; CHECK-NEXT: asr w12, w8, #4
; CHECK-NEXT: add w10, w10, w8 ; CHECK-NEXT: add w10, w10, w11
; CHECK-NEXT: add w11, w11, w9 ; CHECK-NEXT: add w8, w12, w8, lsr #31
; CHECK-NEXT: asr w13, w10, #9
; CHECK-NEXT: add w10, w13, w10, lsr #31
; CHECK-NEXT: asr w13, w11, #4
; CHECK-NEXT: add w11, w13, w11, lsr #31
; CHECK-NEXT: smov w13, v0.h[3]
; CHECK-NEXT: msub w8, w10, w12, w8
; CHECK-NEXT: movi d0, #0000000000000000
; CHECK-NEXT: mov w12, #47143 ; CHECK-NEXT: mov w12, #47143
; CHECK-NEXT: mov w10, #23
; CHECK-NEXT: movk w12, #24749, lsl #16 ; CHECK-NEXT: movk w12, #24749, lsl #16
; CHECK-NEXT: msub w9, w11, w10, w9 ; CHECK-NEXT: msub w8, w8, w13, w9
; CHECK-NEXT: smull x10, w13, w12 ; CHECK-NEXT: smov w9, v0.h[3]
; CHECK-NEXT: mov v0.h[1], w8 ; CHECK-NEXT: asr w13, w10, #9
; CHECK-NEXT: lsr x8, x10, #63 ; CHECK-NEXT: movi d0, #0000000000000000
; CHECK-NEXT: asr x10, x10, #43 ; CHECK-NEXT: add w10, w13, w10, lsr #31
; CHECK-NEXT: add w8, w10, w8 ; CHECK-NEXT: mov w13, #654
; CHECK-NEXT: mov w10, #5423 ; CHECK-NEXT: smull x12, w9, w12
; CHECK-NEXT: mov v0.h[2], w9 ; CHECK-NEXT: msub w10, w10, w13, w11
; CHECK-NEXT: msub w8, w8, w10, w13 ; CHECK-NEXT: lsr x11, x12, #63
; CHECK-NEXT: mov v0.h[3], w8 ; CHECK-NEXT: asr x12, x12, #43
; CHECK-NEXT: add w11, w12, w11
; CHECK-NEXT: mov w12, #5423
; CHECK-NEXT: mov v0.h[1], w10
; CHECK-NEXT: msub w9, w11, w12, w9
; CHECK-NEXT: mov v0.h[2], w8
; CHECK-NEXT: mov v0.h[3], w9
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = srem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423> %1 = srem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is 2^15. ; Don't fold if the divisor is 2^15.
define <4 x i16> @dont_fold_srem_i16_smax(<4 x i16> %x) { define <4 x i16> @dont_fold_srem_i16_smax(<4 x i16> %x) {
; CHECK-LABEL: dont_fold_srem_i16_smax: ; CHECK-LABEL: dont_fold_srem_i16_smax:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #17097
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: smov w8, v0.h[2] ; CHECK-NEXT: smov w9, v0.h[2]
; CHECK-NEXT: mov w9, #17097 ; CHECK-NEXT: movk w8, #45590, lsl #16
; CHECK-NEXT: smov w10, v0.h[1]
; CHECK-NEXT: movk w9, #45590, lsl #16
; CHECK-NEXT: mov w11, #32767
; CHECK-NEXT: smov w12, v0.h[3]
; CHECK-NEXT: movi d1, #0000000000000000
; CHECK-NEXT: smull x9, w8, w9
; CHECK-NEXT: add w11, w10, w11
; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: lsr x9, x9, #32
; CHECK-NEXT: csel w11, w11, w10, lt
; CHECK-NEXT: add w9, w9, w8
; CHECK-NEXT: and w11, w11, #0xffff8000
; CHECK-NEXT: asr w13, w9, #4
; CHECK-NEXT: sub w10, w10, w11
; CHECK-NEXT: mov w11, #47143 ; CHECK-NEXT: mov w11, #47143
; CHECK-NEXT: add w9, w13, w9, lsr #31 ; CHECK-NEXT: smov w12, v0.h[1]
; CHECK-NEXT: mov w13, #23 ; CHECK-NEXT: mov w10, #32767
; CHECK-NEXT: smull x8, w9, w8
; CHECK-NEXT: movk w11, #24749, lsl #16 ; CHECK-NEXT: movk w11, #24749, lsl #16
; CHECK-NEXT: mov v1.h[1], w10 ; CHECK-NEXT: smov w13, v0.h[3]
; CHECK-NEXT: msub w8, w9, w13, w8 ; CHECK-NEXT: add w10, w12, w10
; CHECK-NEXT: smull x9, w12, w11 ; CHECK-NEXT: lsr x8, x8, #32
; CHECK-NEXT: lsr x10, x9, #63 ; CHECK-NEXT: cmp w12, #0
; CHECK-NEXT: asr x9, x9, #43 ; CHECK-NEXT: add w8, w8, w9
; CHECK-NEXT: add w9, w9, w10 ; CHECK-NEXT: csel w10, w10, w12, lt
; CHECK-NEXT: mov w10, #5423 ; CHECK-NEXT: asr w14, w8, #4
; CHECK-NEXT: mov v1.h[2], w8 ; CHECK-NEXT: smull x11, w13, w11
; CHECK-NEXT: msub w8, w9, w10, w12 ; CHECK-NEXT: add w8, w14, w8, lsr #31
; CHECK-NEXT: mov v1.h[3], w8 ; CHECK-NEXT: mov w14, #23
; CHECK-NEXT: fmov d0, d1 ; CHECK-NEXT: and w10, w10, #0xffff8000
; CHECK-NEXT: movi d0, #0000000000000000
; CHECK-NEXT: msub w8, w8, w14, w9
; CHECK-NEXT: sub w9, w12, w10
; CHECK-NEXT: lsr x10, x11, #63
; CHECK-NEXT: asr x11, x11, #43
; CHECK-NEXT: add w10, w11, w10
; CHECK-NEXT: mov w11, #5423
; CHECK-NEXT: mov v0.h[1], w9
; CHECK-NEXT: msub w10, w10, w11, w13
; CHECK-NEXT: mov v0.h[2], w8
; CHECK-NEXT: mov v0.h[3], w10
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = srem <4 x i16> %x, <i16 1, i16 32768, i16 23, i16 5423> %1 = srem <4 x i16> %x, <i16 1, i16 32768, i16 23, i16 5423>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold i64 srem. ; Don't fold i64 srem.
define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) { define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; CHECK-LABEL: dont_fold_srem_i64: ; CHECK-LABEL: dont_fold_srem_i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #8549 ; CHECK-NEXT: mov x8, #8549
; CHECK-NEXT: fmov x9, d1 ; CHECK-NEXT: fmov x9, d1
; CHECK-NEXT: movk x8, #22795, lsl #16 ; CHECK-NEXT: movk x8, #22795, lsl #16
; CHECK-NEXT: mov x12, #6055 ; CHECK-NEXT: mov x11, #6055
; CHECK-NEXT: movk x8, #17096, lsl #32 ; CHECK-NEXT: movk x8, #17096, lsl #32
; CHECK-NEXT: movk x12, #58853, lsl #16 ; CHECK-NEXT: movk x11, #58853, lsl #16
; CHECK-NEXT: movk x8, #45590, lsl #48 ; CHECK-NEXT: movk x8, #45590, lsl #48
; CHECK-NEXT: mov x14, #21445 ; CHECK-NEXT: mov x12, #21445
; CHECK-NEXT: mov x10, v1.d[1] ; CHECK-NEXT: movk x11, #47142, lsl #32
; CHECK-NEXT: movk x12, #47142, lsl #32 ; CHECK-NEXT: movk x12, #1603, lsl #16
; CHECK-NEXT: smulh x8, x9, x8 ; CHECK-NEXT: smulh x8, x9, x8
; CHECK-NEXT: movk x14, #1603, lsl #16 ; CHECK-NEXT: mov x10, v1.d[1]
; CHECK-NEXT: mov x11, v0.d[1] ; CHECK-NEXT: movk x11, #24749, lsl #48
; CHECK-NEXT: movk x12, #24749, lsl #48 ; CHECK-NEXT: movk x12, #15432, lsl #32
; CHECK-NEXT: movk x12, #25653, lsl #48
; CHECK-NEXT: mov x13, v0.d[1]
; CHECK-NEXT: add x8, x8, x9 ; CHECK-NEXT: add x8, x8, x9
; CHECK-NEXT: movk x14, #15432, lsl #32 ; CHECK-NEXT: smulh x11, x10, x11
; CHECK-NEXT: asr x13, x8, #4 ; CHECK-NEXT: asr x14, x8, #4
; CHECK-NEXT: movk x14, #25653, lsl #48 ; CHECK-NEXT: mov w15, #23
; CHECK-NEXT: add x8, x13, x8, lsr #63 ; CHECK-NEXT: add x8, x14, x8, lsr #63
; CHECK-NEXT: mov w13, #23 ; CHECK-NEXT: smulh x12, x13, x12
; CHECK-NEXT: smulh x12, x10, x12 ; CHECK-NEXT: asr x14, x11, #11
; CHECK-NEXT: smulh x14, x11, x14 ; CHECK-NEXT: add x11, x14, x11, lsr #63
; CHECK-NEXT: msub x8, x8, x13, x9 ; CHECK-NEXT: msub x8, x8, x15, x9
; CHECK-NEXT: asr x13, x12, #11 ; CHECK-NEXT: asr x14, x12, #8
; CHECK-NEXT: add x12, x13, x12, lsr #63
; CHECK-NEXT: asr x13, x14, #8
; CHECK-NEXT: mov w9, #5423 ; CHECK-NEXT: mov w9, #5423
; CHECK-NEXT: add x13, x13, x14, lsr #63 ; CHECK-NEXT: add x12, x14, x12, lsr #63
; CHECK-NEXT: mov w14, #654 ; CHECK-NEXT: mov w14, #654
; CHECK-NEXT: msub x9, x12, x9, x10 ; CHECK-NEXT: msub x9, x11, x9, x10
; CHECK-NEXT: msub x10, x12, x14, x13
; CHECK-NEXT: fmov d1, x8 ; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: msub x10, x13, x14, x11
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v1.d[1], x9 ; CHECK-NEXT: mov v1.d[1], x9
; CHECK-NEXT: mov v0.d[1], x10 ; CHECK-NEXT: mov v0.d[1], x10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423> %1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1 ret <4 x i64> %1
} }

llvm/test/CodeGen/AArch64/ssub_sat_vec.ll

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; CHECK-NEXT: ld1 { v1.b }[0], [x0] ; CHECK-NEXT: ld1 { v1.b }[0], [x0]
; CHECK-NEXT: add x9, x0, #1 ; CHECK-NEXT: add x9, x0, #1
; CHECK-NEXT: ld1 { v0.b }[4], [x8] ; CHECK-NEXT: ld1 { v0.b }[4], [x8]
; CHECK-NEXT: ld1 { v1.b }[4], [x9] ; CHECK-NEXT: ld1 { v1.b }[4], [x9]
; CHECK-NEXT: shl v0.2s, v0.2s, #24 ; CHECK-NEXT: shl v0.2s, v0.2s, #24
; CHECK-NEXT: shl v1.2s, v1.2s, #24 ; CHECK-NEXT: shl v1.2s, v1.2s, #24
; CHECK-NEXT: sqsub v0.2s, v1.2s, v0.2s ; CHECK-NEXT: sqsub v0.2s, v1.2s, v0.2s
; CHECK-NEXT: ushr v0.2s, v0.2s, #24 ; CHECK-NEXT: ushr v0.2s, v0.2s, #24
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: mov w9, v0.s[1]
; CHECK-NEXT: strb w9, [x2] ; CHECK-NEXT: strb w9, [x2, #1]
; CHECK-NEXT: strb w8, [x2, #1] ; CHECK-NEXT: strb w8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i8>, <2 x i8>* %px %x = load <2 x i8>, <2 x i8>* %px
%y = load <2 x i8>, <2 x i8>* %py %y = load <2 x i8>, <2 x i8>* %py
%z = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %x, <2 x i8> %y) %z = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
store <2 x i8> %z, <2 x i8>* %pz store <2 x i8> %z, <2 x i8>* %pz
ret void ret void
} }
Show All 20 Lines
; CHECK-NEXT: ld1 { v1.h }[0], [x0] ; CHECK-NEXT: ld1 { v1.h }[0], [x0]
; CHECK-NEXT: add x9, x0, #2 ; CHECK-NEXT: add x9, x0, #2
; CHECK-NEXT: ld1 { v0.h }[2], [x8] ; CHECK-NEXT: ld1 { v0.h }[2], [x8]
; CHECK-NEXT: ld1 { v1.h }[2], [x9] ; CHECK-NEXT: ld1 { v1.h }[2], [x9]
; CHECK-NEXT: shl v0.2s, v0.2s, #16 ; CHECK-NEXT: shl v0.2s, v0.2s, #16
; CHECK-NEXT: shl v1.2s, v1.2s, #16 ; CHECK-NEXT: shl v1.2s, v1.2s, #16
; CHECK-NEXT: sqsub v0.2s, v1.2s, v0.2s ; CHECK-NEXT: sqsub v0.2s, v1.2s, v0.2s
; CHECK-NEXT: ushr v0.2s, v0.2s, #16 ; CHECK-NEXT: ushr v0.2s, v0.2s, #16
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: mov w9, v0.s[1]
; CHECK-NEXT: strh w9, [x2] ; CHECK-NEXT: strh w9, [x2, #2]
; CHECK-NEXT: strh w8, [x2, #2] ; CHECK-NEXT: strh w8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i16>, <2 x i16>* %px %x = load <2 x i16>, <2 x i16>* %px
%y = load <2 x i16>, <2 x i16>* %py %y = load <2 x i16>, <2 x i16>* %py
%z = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %x, <2 x i16> %y) %z = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
store <2 x i16> %z, <2 x i16>* %pz store <2 x i16> %z, <2 x i16>* %pz
ret void ret void
} }
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llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll

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} }
; Predicates ; Predicates
define <2 x i1> @extract_v2i1_nxv2i1(<vscale x 2 x i1> %inmask) { define <2 x i1> @extract_v2i1_nxv2i1(<vscale x 2 x i1> %inmask) {
; CHECK-LABEL: extract_v2i1_nxv2i1: ; CHECK-LABEL: extract_v2i1_nxv2i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, p0/z, #1 // =0x1 ; CHECK-NEXT: mov z1.d, p0/z, #1 // =0x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d1
; CHECK-NEXT: mov x8, v0.d[1] ; CHECK-NEXT: mov x8, v1.d[1]
; CHECK-NEXT: fmov s0, w0 ; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: mov v0.s[1], w8 ; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %inmask, i64 0) %mask = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %inmask, i64 0)
ret <2 x i1> %mask ret <2 x i1> %mask
} }
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llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll

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; i16 ; i16
; Don't use SVE for 64-bit vectors. ; Don't use SVE for 64-bit vectors.
define <2 x i16> @extract_subvector_v4i16(<4 x i16> %op) #0 { define <2 x i16> @extract_subvector_v4i16(<4 x i16> %op) #0 {
; CHECK-LABEL: extract_subvector_v4i16: ; CHECK-LABEL: extract_subvector_v4i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.h[2] ; CHECK-NEXT: umov w8, v0.h[2]
; CHECK-NEXT: umov w9, v0.h[3] ; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: umov w8, v0.h[3]
; CHECK-NEXT: mov v0.s[1], w9 ; CHECK-NEXT: mov v1.s[1], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: fmov d0, d1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ret = call <2 x i16> @llvm.experimental.vector.extract.v2i16.v4i16(<4 x i16> %op, i64 2) %ret = call <2 x i16> @llvm.experimental.vector.extract.v2i16.v4i16(<4 x i16> %op, i64 2)
ret <2 x i16> %ret ret <2 x i16> %ret
} }
; Don't use SVE for 128-bit vectors. ; Don't use SVE for 128-bit vectors.
define <4 x i16> @extract_subvector_v8i16(<8 x i16> %op) #0 { define <4 x i16> @extract_subvector_v8i16(<8 x i16> %op) #0 {
; CHECK-LABEL: extract_subvector_v8i16: ; CHECK-LABEL: extract_subvector_v8i16:
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llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll

Show All 27 Lines
; CHECK: ptrue [[PG0:p[0-9]+]].s, vl8 ; CHECK: ptrue [[PG0:p[0-9]+]].s, vl8
; CHECK-NEXT: sunpklo [[OP2_LO:z[0-9]+]].h, z1.b ; CHECK-NEXT: sunpklo [[OP2_LO:z[0-9]+]].h, z1.b
; CHECK-NEXT: sunpklo [[OP1_LO:z[0-9]+]].h, z0.b ; CHECK-NEXT: sunpklo [[OP1_LO:z[0-9]+]].h, z0.b
; CHECK-NEXT: sunpklo [[OP2_LO_LO:z[0-9]+]].s, z1.h ; CHECK-NEXT: sunpklo [[OP2_LO_LO:z[0-9]+]].s, z1.h
; CHECK-NEXT: sunpklo [[OP1_LO_LO:z[0-9]+]].s, z0.h ; CHECK-NEXT: sunpklo [[OP1_LO_LO:z[0-9]+]].s, z0.h
; CHECK-NEXT: sdiv [[DIV:z[0-9]+]].s, [[PG0]]/m, [[OP1_LO_LO]].s, [[OP2_LO_LO]].s ; CHECK-NEXT: sdiv [[DIV:z[0-9]+]].s, [[PG0]]/m, [[OP1_LO_LO]].s, [[OP2_LO_LO]].s
; CHECK-NEXT: uzp1 [[RES:z[0-9]+]].h, [[DIV]].h, [[DIV]].h ; CHECK-NEXT: uzp1 [[RES:z[0-9]+]].h, [[DIV]].h, [[DIV]].h
; CHECK-NEXT: umov [[SCALAR0:w[0-9]+]], [[VEC:v[0-9]+]].h[0] ; CHECK-NEXT: umov [[SCALAR0:w[0-9]+]], [[VEC:v[0-9]+]].h[0]
; CHECK-NEXT: umov [[SCALAR1:w[0-9]+]], [[VEC]].h[1]
; CHECK-NEXT: fmov s0, [[SCALAR0]] ; CHECK-NEXT: fmov s0, [[SCALAR0]]
; CHECK-NEXT: umov [[SCALAR2:w[0-9]+]], [[VEC]].h[2] ; CHECK-NEXT: umov [[SCALAR1:w[0-9]+]], [[VEC]].h[1]
; CHECK-NEXT: mov [[FINAL:v[0-9]+]].b[1], [[SCALAR1]] ; CHECK-NEXT: mov [[FINAL:v[0-9]+]].b[1], [[SCALAR1]]
; CHECK-NEXT: umov [[SCALAR2:w[0-9]+]], [[VEC]].h[2]
; CHECK-NEXT: mov [[FINAL]].b[2], [[SCALAR2]] ; CHECK-NEXT: mov [[FINAL]].b[2], [[SCALAR2]]
; CHECK-NEXT: umov [[SCALAR3:w[0-9]+]], [[VEC]].h[3] ; CHECK-NEXT: umov [[SCALAR3:w[0-9]+]], [[VEC]].h[3]
; CHECK-NEXT: mov [[FINAL]].b[3], [[SCALAR3]] ; CHECK-NEXT: mov [[FINAL]].b[3], [[SCALAR3]]
; CHECK-NEXT: umov [[SCALAR4:w[0-9]+]], [[VEC]].h[4] ; CHECK-NEXT: umov [[SCALAR4:w[0-9]+]], [[VEC]].h[4]
; CHECK-NEXT: mov [[FINAL]].b[4], [[SCALAR4]] ; CHECK-NEXT: mov [[FINAL]].b[4], [[SCALAR4]]
; CHECK-NEXT: umov [[SCALAR5:w[0-9]+]], [[VEC]].h[5] ; CHECK-NEXT: umov [[SCALAR5:w[0-9]+]], [[VEC]].h[5]
; CHECK-NEXT: mov [[FINAL]].b[5], [[SCALAR5]] ; CHECK-NEXT: mov [[FINAL]].b[5], [[SCALAR5]]
; CHECK-NEXT: umov [[SCALAR6:w[0-9]+]], [[VEC]].h[6] ; CHECK-NEXT: umov [[SCALAR6:w[0-9]+]], [[VEC]].h[6]
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; CHECK: ptrue [[PG0:p[0-9]+]].s, vl8 ; CHECK: ptrue [[PG0:p[0-9]+]].s, vl8
; CHECK-NEXT: uunpklo [[OP2_LO:z[0-9]+]].h, z1.b ; CHECK-NEXT: uunpklo [[OP2_LO:z[0-9]+]].h, z1.b
; CHECK-NEXT: uunpklo [[OP1_LO:z[0-9]+]].h, z0.b ; CHECK-NEXT: uunpklo [[OP1_LO:z[0-9]+]].h, z0.b
; CHECK-NEXT: uunpklo [[OP2_LO_LO:z[0-9]+]].s, z1.h ; CHECK-NEXT: uunpklo [[OP2_LO_LO:z[0-9]+]].s, z1.h
; CHECK-NEXT: uunpklo [[OP1_LO_LO:z[0-9]+]].s, z0.h ; CHECK-NEXT: uunpklo [[OP1_LO_LO:z[0-9]+]].s, z0.h
; CHECK-NEXT: udiv [[DIV:z[0-9]+]].s, [[PG0]]/m, [[OP1_LO_LO]].s, [[OP2_LO_LO]].s ; CHECK-NEXT: udiv [[DIV:z[0-9]+]].s, [[PG0]]/m, [[OP1_LO_LO]].s, [[OP2_LO_LO]].s
; CHECK-NEXT: uzp1 [[RES:z[0-9]+]].h, [[DIV]].h, [[DIV]].h ; CHECK-NEXT: uzp1 [[RES:z[0-9]+]].h, [[DIV]].h, [[DIV]].h
; CHECK-NEXT: umov [[SCALAR0:w[0-9]+]], [[VEC:v[0-9]+]].h[0] ; CHECK-NEXT: umov [[SCALAR0:w[0-9]+]], [[VEC:v[0-9]+]].h[0]
; CHECK-NEXT: umov [[SCALAR1:w[0-9]+]], [[VEC]].h[1]
; CHECK-NEXT: fmov s0, [[SCALAR0]] ; CHECK-NEXT: fmov s0, [[SCALAR0]]
; CHECK-NEXT: umov [[SCALAR2:w[0-9]+]], [[VEC]].h[2] ; CHECK-NEXT: umov [[SCALAR1:w[0-9]+]], [[VEC]].h[1]
; CHECK-NEXT: mov [[FINAL:v[0-9]+]].b[1], [[SCALAR1]] ; CHECK-NEXT: mov [[FINAL:v[0-9]+]].b[1], [[SCALAR1]]
; CHECK-NEXT: umov [[SCALAR2:w[0-9]+]], [[VEC]].h[2]
; CHECK-NEXT: mov [[FINAL]].b[2], [[SCALAR2]] ; CHECK-NEXT: mov [[FINAL]].b[2], [[SCALAR2]]
; CHECK-NEXT: umov [[SCALAR3:w[0-9]+]], [[VEC]].h[3] ; CHECK-NEXT: umov [[SCALAR3:w[0-9]+]], [[VEC]].h[3]
; CHECK-NEXT: mov [[FINAL]].b[3], [[SCALAR3]] ; CHECK-NEXT: mov [[FINAL]].b[3], [[SCALAR3]]
; CHECK-NEXT: umov [[SCALAR4:w[0-9]+]], [[VEC]].h[4] ; CHECK-NEXT: umov [[SCALAR4:w[0-9]+]], [[VEC]].h[4]
; CHECK-NEXT: mov [[FINAL]].b[4], [[SCALAR4]] ; CHECK-NEXT: mov [[FINAL]].b[4], [[SCALAR4]]
; CHECK-NEXT: umov [[SCALAR5:w[0-9]+]], [[VEC]].h[5] ; CHECK-NEXT: umov [[SCALAR5:w[0-9]+]], [[VEC]].h[5]
; CHECK-NEXT: mov [[FINAL]].b[5], [[SCALAR5]] ; CHECK-NEXT: mov [[FINAL]].b[5], [[SCALAR5]]
; CHECK-NEXT: umov [[SCALAR6:w[0-9]+]], [[VEC]].h[6] ; CHECK-NEXT: umov [[SCALAR6:w[0-9]+]], [[VEC]].h[6]
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llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll

Show All 31 Lines
; Don't use SVE for 64-bit vectors. ; Don't use SVE for 64-bit vectors.
; FIXME: The codegen for the >=256 bits case can be improved. ; FIXME: The codegen for the >=256 bits case can be improved.
define <8 x i8> @smulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 { define <8 x i8> @smulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
; CHECK-LABEL: smulh_v8i8: ; CHECK-LABEL: smulh_v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: smull v0.8h, v0.8b, v1.8b ; CHECK-NEXT: smull v0.8h, v0.8b, v1.8b
; CHECK-NEXT: ushr v1.8h, v0.8h, #8 ; CHECK-NEXT: ushr v1.8h, v0.8h, #8
; CHECK-NEXT: umov w8, v1.h[0] ; CHECK-NEXT: umov w8, v1.h[0]
; CHECK-NEXT: umov w9, v1.h[1]
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: umov w8, v1.h[1]
; CHECK-NEXT: mov v0.b[1], w8
; CHECK-NEXT: umov w8, v1.h[2] ; CHECK-NEXT: umov w8, v1.h[2]
; CHECK-NEXT: mov v0.b[1], w9
; CHECK-NEXT: mov v0.b[2], w8 ; CHECK-NEXT: mov v0.b[2], w8
; CHECK-NEXT: umov w8, v1.h[3] ; CHECK-NEXT: umov w8, v1.h[3]
; CHECK-NEXT: mov v0.b[3], w8 ; CHECK-NEXT: mov v0.b[3], w8
; CHECK-NEXT: umov w8, v1.h[4] ; CHECK-NEXT: umov w8, v1.h[4]
; CHECK-NEXT: mov v0.b[4], w8 ; CHECK-NEXT: mov v0.b[4], w8
; CHECK-NEXT: umov w8, v1.h[5] ; CHECK-NEXT: umov w8, v1.h[5]
; CHECK-NEXT: mov v0.b[5], w8 ; CHECK-NEXT: mov v0.b[5], w8
; CHECK-NEXT: umov w8, v1.h[6] ; CHECK-NEXT: umov w8, v1.h[6]
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; Don't use SVE for 64-bit vectors. ; Don't use SVE for 64-bit vectors.
; FIXME: The codegen for the >=256 bits case can be improved. ; FIXME: The codegen for the >=256 bits case can be improved.
define <8 x i8> @umulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 { define <8 x i8> @umulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
; CHECK-LABEL: umulh_v8i8: ; CHECK-LABEL: umulh_v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umull v0.8h, v0.8b, v1.8b ; CHECK-NEXT: umull v0.8h, v0.8b, v1.8b
; CHECK-NEXT: ushr v1.8h, v0.8h, #8 ; CHECK-NEXT: ushr v1.8h, v0.8h, #8
; CHECK-NEXT: umov w8, v1.h[0] ; CHECK-NEXT: umov w8, v1.h[0]
; CHECK-NEXT: umov w9, v1.h[1]
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: umov w8, v1.h[1]
; CHECK-NEXT: mov v0.b[1], w8
; CHECK-NEXT: umov w8, v1.h[2] ; CHECK-NEXT: umov w8, v1.h[2]
; CHECK-NEXT: mov v0.b[1], w9
; CHECK-NEXT: mov v0.b[2], w8 ; CHECK-NEXT: mov v0.b[2], w8
; CHECK-NEXT: umov w8, v1.h[3] ; CHECK-NEXT: umov w8, v1.h[3]
; CHECK-NEXT: mov v0.b[3], w8 ; CHECK-NEXT: mov v0.b[3], w8
; CHECK-NEXT: umov w8, v1.h[4] ; CHECK-NEXT: umov w8, v1.h[4]
; CHECK-NEXT: mov v0.b[4], w8 ; CHECK-NEXT: mov v0.b[4], w8
; CHECK-NEXT: umov w8, v1.h[5] ; CHECK-NEXT: umov w8, v1.h[5]
; CHECK-NEXT: mov v0.b[5], w8 ; CHECK-NEXT: mov v0.b[5], w8
; CHECK-NEXT: umov w8, v1.h[6] ; CHECK-NEXT: umov w8, v1.h[6]
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llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll

Show All 27 Lines
; CHECK: sunpklo [[OP2_LO:z[0-9]+]].h, [[OP2:z[0-9]+]].b ; CHECK: sunpklo [[OP2_LO:z[0-9]+]].h, [[OP2:z[0-9]+]].b
; CHECK-NEXT: sunpklo [[OP1_LO:z[0-9]+]].h, [[OP1:z[0-9]+]].b ; CHECK-NEXT: sunpklo [[OP1_LO:z[0-9]+]].h, [[OP1:z[0-9]+]].b
; CHECK-NEXT: ptrue [[PG1:p[0-9]+]].s, vl8 ; CHECK-NEXT: ptrue [[PG1:p[0-9]+]].s, vl8
; CHECK-NEXT: sunpklo [[OP2_LO_LO:z[0-9]+]].s, [[OP2_LO]].h ; CHECK-NEXT: sunpklo [[OP2_LO_LO:z[0-9]+]].s, [[OP2_LO]].h
; CHECK-NEXT: sunpklo [[OP1_LO_LO:z[0-9]+]].s, [[OP1_LO]].h ; CHECK-NEXT: sunpklo [[OP1_LO_LO:z[0-9]+]].s, [[OP1_LO]].h
; CHECK-NEXT: sdivr [[DIV1:z[0-9]+]].s, [[PG1]]/m, [[OP2_LO_LO]].s, [[OP1_LO_LO]].s ; CHECK-NEXT: sdivr [[DIV1:z[0-9]+]].s, [[PG1]]/m, [[OP2_LO_LO]].s, [[OP1_LO_LO]].s
; CHECK-NEXT: uzp1 [[UZP1:z[0-9]+]].h, [[DIV1]].h, [[DIV1]].h ; CHECK-NEXT: uzp1 [[UZP1:z[0-9]+]].h, [[DIV1]].h, [[DIV1]].h
; CHECK-NEXT: umov [[SCALAR1:w[0-9]+]], [[VEC:v[0-9]+]].h[0] ; CHECK-NEXT: umov [[SCALAR1:w[0-9]+]], [[VEC:v[0-9]+]].h[0]
; CHECK-NEXT: umov [[SCALAR2:w[0-9]+]], [[VEC]].h[1]
; CHECK-NEXT: fmov s3, [[SCALAR1]] ; CHECK-NEXT: fmov s3, [[SCALAR1]]
; CHECK-NEXT: umov [[SCALAR3:w[0-9]+]], [[VEC]].h[2] ; CHECK-NEXT: umov [[SCALAR2:w[0-9]+]], [[VEC]].h[1]
; CHECK-NEXT: mov [[FINAL:v[0-9]+]].b[1], [[SCALAR2]] ; CHECK-NEXT: mov [[FINAL:v[0-9]+]].b[1], [[SCALAR2]]
; CHECK-NEXT: umov [[SCALAR3:w[0-9]+]], [[VEC]].h[2]
; CHECK-NEXT: mov [[FINAL]].b[2], [[SCALAR3]] ; CHECK-NEXT: mov [[FINAL]].b[2], [[SCALAR3]]
; CHECK-NEXT: umov [[SCALAR4:w[0-9]+]], [[VEC]].h[3] ; CHECK-NEXT: umov [[SCALAR4:w[0-9]+]], [[VEC]].h[3]
; CHECK-NEXT: mov [[FINAL]].b[3], [[SCALAR4]] ; CHECK-NEXT: mov [[FINAL]].b[3], [[SCALAR4]]
; CHECK-NEXT: umov [[SCALAR5:w[0-9]+]], [[VEC]].h[4] ; CHECK-NEXT: umov [[SCALAR5:w[0-9]+]], [[VEC]].h[4]
; CHECK-NEXT: mov [[FINAL]].b[4], [[SCALAR5]] ; CHECK-NEXT: mov [[FINAL]].b[4], [[SCALAR5]]
; CHECK-NEXT: umov [[SCALAR6:w[0-9]+]], [[VEC]].h[5] ; CHECK-NEXT: umov [[SCALAR6:w[0-9]+]], [[VEC]].h[5]
; CHECK-NEXT: mov [[FINAL]].b[5], [[SCALAR6]] ; CHECK-NEXT: mov [[FINAL]].b[5], [[SCALAR6]]
; CHECK-NEXT: umov [[SCALAR7:w[0-9]+]], [[VEC]].h[6] ; CHECK-NEXT: umov [[SCALAR7:w[0-9]+]], [[VEC]].h[6]
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; CHECK: uunpklo [[OP2_LO:z[0-9]+]].h, [[OP2:z[0-9]+]].b ; CHECK: uunpklo [[OP2_LO:z[0-9]+]].h, [[OP2:z[0-9]+]].b
; CHECK-NEXT: uunpklo [[OP1_LO:z[0-9]+]].h, [[OP1:z[0-9]+]].b ; CHECK-NEXT: uunpklo [[OP1_LO:z[0-9]+]].h, [[OP1:z[0-9]+]].b
; CHECK-NEXT: ptrue [[PG1:p[0-9]+]].s, vl8 ; CHECK-NEXT: ptrue [[PG1:p[0-9]+]].s, vl8
; CHECK-NEXT: uunpklo [[OP2_LO_LO:z[0-9]+]].s, [[OP2_LO]].h ; CHECK-NEXT: uunpklo [[OP2_LO_LO:z[0-9]+]].s, [[OP2_LO]].h
; CHECK-NEXT: uunpklo [[OP1_LO_LO:z[0-9]+]].s, [[OP1_LO]].h ; CHECK-NEXT: uunpklo [[OP1_LO_LO:z[0-9]+]].s, [[OP1_LO]].h
; CHECK-NEXT: udivr [[DIV1:z[0-9]+]].s, [[PG1]]/m, [[OP2_LO_LO]].s, [[OP1_LO_LO]].s ; CHECK-NEXT: udivr [[DIV1:z[0-9]+]].s, [[PG1]]/m, [[OP2_LO_LO]].s, [[OP1_LO_LO]].s
; CHECK-NEXT: uzp1 [[UZP1:z[0-9]+]].h, [[DIV1]].h, [[DIV1]].h ; CHECK-NEXT: uzp1 [[UZP1:z[0-9]+]].h, [[DIV1]].h, [[DIV1]].h
; CHECK-NEXT: umov [[SCALAR0:w[0-9]+]], [[VEC:v[0-9]+]].h[0] ; CHECK-NEXT: umov [[SCALAR0:w[0-9]+]], [[VEC:v[0-9]+]].h[0]
; CHECK-NEXT: umov [[SCALAR1:w[0-9]+]], [[VEC]].h[1]
; CHECK-NEXT: fmov s3, [[SCALAR0]] ; CHECK-NEXT: fmov s3, [[SCALAR0]]
; CHECK-NEXT: umov [[SCALAR2:w[0-9]+]], [[VEC]].h[2] ; CHECK-NEXT: umov [[SCALAR1:w[0-9]+]], [[VEC]].h[1]
; CHECK-NEXT: mov [[FINAL:v[0-9]+]].b[1], [[SCALAR1]] ; CHECK-NEXT: mov [[FINAL:v[0-9]+]].b[1], [[SCALAR1]]
; CHECK-NEXT: umov [[SCALAR2:w[0-9]+]], [[VEC]].h[2]
; CHECK-NEXT: mov [[FINAL]].b[2], [[SCALAR2]] ; CHECK-NEXT: mov [[FINAL]].b[2], [[SCALAR2]]
; CHECK-NEXT: umov [[SCALAR3:w[0-9]+]], [[VEC]].h[3] ; CHECK-NEXT: umov [[SCALAR3:w[0-9]+]], [[VEC]].h[3]
; CHECK-NEXT: mov [[FINAL]].b[3], [[SCALAR3]] ; CHECK-NEXT: mov [[FINAL]].b[3], [[SCALAR3]]
; CHECK-NEXT: umov [[SCALAR4:w[0-9]+]], [[VEC]].h[4] ; CHECK-NEXT: umov [[SCALAR4:w[0-9]+]], [[VEC]].h[4]
; CHECK-NEXT: mov [[FINAL]].b[4], [[SCALAR4]] ; CHECK-NEXT: mov [[FINAL]].b[4], [[SCALAR4]]
; CHECK-NEXT: umov [[SCALAR5:w[0-9]+]], [[VEC]].h[5] ; CHECK-NEXT: umov [[SCALAR5:w[0-9]+]], [[VEC]].h[5]
; CHECK-NEXT: mov [[FINAL]].b[5], [[SCALAR5]] ; CHECK-NEXT: mov [[FINAL]].b[5], [[SCALAR5]]
; CHECK-NEXT: umov [[SCALAR6:w[0-9]+]], [[VEC]].h[6] ; CHECK-NEXT: umov [[SCALAR6:w[0-9]+]], [[VEC]].h[6]
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llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll

Show First 20 Lines • Show All 272 Lines • ▼ Show 20 Lines
; VBITS_EQ_256-LABEL: ucvtf_v8i16_v8f64: ; VBITS_EQ_256-LABEL: ucvtf_v8i16_v8f64:
; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256: // %bb.0:
; VBITS_EQ_256-NEXT: ldr q0, [x0] ; VBITS_EQ_256-NEXT: ldr q0, [x0]
; VBITS_EQ_256-NEXT: mov x8, #4 ; VBITS_EQ_256-NEXT: mov x8, #4
; VBITS_EQ_256-NEXT: ptrue p0.d, vl4 ; VBITS_EQ_256-NEXT: ptrue p0.d, vl4
; VBITS_EQ_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; VBITS_EQ_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; VBITS_EQ_256-NEXT: uunpklo z0.s, z0.h ; VBITS_EQ_256-NEXT: uunpklo z0.s, z0.h
; VBITS_EQ_256-NEXT: uunpklo z0.d, z0.s ; VBITS_EQ_256-NEXT: uunpklo z0.d, z0.s
; VBITS_EQ_256-NEXT: ucvtf z0.d, p0/m, z0.d
; VBITS_EQ_256-NEXT: st1d { z0.d }, p0, [x1]
; VBITS_EQ_256-NEXT: uunpklo z1.s, z1.h ; VBITS_EQ_256-NEXT: uunpklo z1.s, z1.h
; VBITS_EQ_256-NEXT: ucvtf z0.d, p0/m, z0.d
; VBITS_EQ_256-NEXT: uunpklo z1.d, z1.s ; VBITS_EQ_256-NEXT: uunpklo z1.d, z1.s
; VBITS_EQ_256-NEXT: st1d { z0.d }, p0, [x1]
; VBITS_EQ_256-NEXT: ucvtf z1.d, p0/m, z1.d ; VBITS_EQ_256-NEXT: ucvtf z1.d, p0/m, z1.d
; VBITS_EQ_256-NEXT: st1d { z1.d }, p0, [x1, x8, lsl #3] ; VBITS_EQ_256-NEXT: st1d { z1.d }, p0, [x1, x8, lsl #3]
; VBITS_EQ_256-NEXT: ret ; VBITS_EQ_256-NEXT: ret
; ;
; VBITS_GE_512-LABEL: ucvtf_v8i16_v8f64: ; VBITS_GE_512-LABEL: ucvtf_v8i16_v8f64:
; VBITS_GE_512: // %bb.0: ; VBITS_GE_512: // %bb.0:
; VBITS_GE_512-NEXT: ldr q0, [x0] ; VBITS_GE_512-NEXT: ldr q0, [x0]
; VBITS_GE_512-NEXT: ptrue p0.d, vl8 ; VBITS_GE_512-NEXT: ptrue p0.d, vl8
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; VBITS_EQ_256-LABEL: scvtf_v8i16_v8f64: ; VBITS_EQ_256-LABEL: scvtf_v8i16_v8f64:
; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256: // %bb.0:
; VBITS_EQ_256-NEXT: ldr q0, [x0] ; VBITS_EQ_256-NEXT: ldr q0, [x0]
; VBITS_EQ_256-NEXT: mov x8, #4 ; VBITS_EQ_256-NEXT: mov x8, #4
; VBITS_EQ_256-NEXT: ptrue p0.d, vl4 ; VBITS_EQ_256-NEXT: ptrue p0.d, vl4
; VBITS_EQ_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; VBITS_EQ_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; VBITS_EQ_256-NEXT: sunpklo z0.s, z0.h ; VBITS_EQ_256-NEXT: sunpklo z0.s, z0.h
; VBITS_EQ_256-NEXT: sunpklo z0.d, z0.s ; VBITS_EQ_256-NEXT: sunpklo z0.d, z0.s
; VBITS_EQ_256-NEXT: scvtf z0.d, p0/m, z0.d
; VBITS_EQ_256-NEXT: st1d { z0.d }, p0, [x1]
; VBITS_EQ_256-NEXT: sunpklo z1.s, z1.h ; VBITS_EQ_256-NEXT: sunpklo z1.s, z1.h
; VBITS_EQ_256-NEXT: scvtf z0.d, p0/m, z0.d
; VBITS_EQ_256-NEXT: sunpklo z1.d, z1.s ; VBITS_EQ_256-NEXT: sunpklo z1.d, z1.s
; VBITS_EQ_256-NEXT: st1d { z0.d }, p0, [x1]
; VBITS_EQ_256-NEXT: scvtf z1.d, p0/m, z1.d ; VBITS_EQ_256-NEXT: scvtf z1.d, p0/m, z1.d
; VBITS_EQ_256-NEXT: st1d { z1.d }, p0, [x1, x8, lsl #3] ; VBITS_EQ_256-NEXT: st1d { z1.d }, p0, [x1, x8, lsl #3]
; VBITS_EQ_256-NEXT: ret ; VBITS_EQ_256-NEXT: ret
; ;
; VBITS_GE_512-LABEL: scvtf_v8i16_v8f64: ; VBITS_GE_512-LABEL: scvtf_v8i16_v8f64:
; VBITS_GE_512: // %bb.0: ; VBITS_GE_512: // %bb.0:
; VBITS_GE_512-NEXT: ldr q0, [x0] ; VBITS_GE_512-NEXT: ldr q0, [x0]
; VBITS_GE_512-NEXT: ptrue p0.d, vl8 ; VBITS_GE_512-NEXT: ptrue p0.d, vl8
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llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll

Show First 20 Lines • Show All 239 Lines • ▼ Show 20 Lines
; VBITS_EQ_256-NEXT: mov x8, #4 ; VBITS_EQ_256-NEXT: mov x8, #4
; VBITS_EQ_256-NEXT: ptrue p0.d, vl4 ; VBITS_EQ_256-NEXT: ptrue p0.d, vl4
; VBITS_EQ_256-NEXT: cmeq v0.8h, v0.8h, #0 ; VBITS_EQ_256-NEXT: cmeq v0.8h, v0.8h, #0
; VBITS_EQ_256-NEXT: ld1d { z2.d }, p0/z, [x1, x8, lsl #3] ; VBITS_EQ_256-NEXT: ld1d { z2.d }, p0/z, [x1, x8, lsl #3]
; VBITS_EQ_256-NEXT: ld1d { z3.d }, p0/z, [x1] ; VBITS_EQ_256-NEXT: ld1d { z3.d }, p0/z, [x1]
; VBITS_EQ_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; VBITS_EQ_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; VBITS_EQ_256-NEXT: sunpklo z0.s, z0.h ; VBITS_EQ_256-NEXT: sunpklo z0.s, z0.h
; VBITS_EQ_256-NEXT: sunpklo z0.d, z0.s ; VBITS_EQ_256-NEXT: sunpklo z0.d, z0.s
; VBITS_EQ_256-NEXT: cmpne p1.d, p0/z, z0.d, #0
; VBITS_EQ_256-NEXT: ld1h { z0.d }, p1/z, [z3.d]
; VBITS_EQ_256-NEXT: sunpklo z1.s, z1.h ; VBITS_EQ_256-NEXT: sunpklo z1.s, z1.h
; VBITS_EQ_256-NEXT: cmpne p1.d, p0/z, z0.d, #0
; VBITS_EQ_256-NEXT: sunpklo z1.d, z1.s ; VBITS_EQ_256-NEXT: sunpklo z1.d, z1.s
; VBITS_EQ_256-NEXT: ld1h { z0.d }, p1/z, [z3.d]
; VBITS_EQ_256-NEXT: cmpne p0.d, p0/z, z1.d, #0 ; VBITS_EQ_256-NEXT: cmpne p0.d, p0/z, z1.d, #0
; VBITS_EQ_256-NEXT: ld1h { z1.d }, p0/z, [z2.d] ; VBITS_EQ_256-NEXT: ld1h { z1.d }, p0/z, [z2.d]
; VBITS_EQ_256-NEXT: uzp1 z0.s, z0.s, z0.s ; VBITS_EQ_256-NEXT: uzp1 z0.s, z0.s, z0.s
; VBITS_EQ_256-NEXT: uzp1 z0.h, z0.h, z0.h ; VBITS_EQ_256-NEXT: uzp1 z0.h, z0.h, z0.h
; VBITS_EQ_256-NEXT: uzp1 z1.s, z1.s, z1.s ; VBITS_EQ_256-NEXT: uzp1 z1.s, z1.s, z1.s
; VBITS_EQ_256-NEXT: uzp1 z1.h, z1.h, z1.h ; VBITS_EQ_256-NEXT: uzp1 z1.h, z1.h, z1.h
; VBITS_EQ_256-NEXT: mov v0.d[1], v1.d[0] ; VBITS_EQ_256-NEXT: mov v0.d[1], v1.d[0]
; VBITS_EQ_256-NEXT: str q0, [x0] ; VBITS_EQ_256-NEXT: str q0, [x0]
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define void @masked_gather_v2f16(<2 x half>* %a, <2 x half*>* %b) #0 { define void @masked_gather_v2f16(<2 x half>* %a, <2 x half*>* %b) #0 {
; CHECK-LABEL: masked_gather_v2f16: ; CHECK-LABEL: masked_gather_v2f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr s1, [x0] ; CHECK-NEXT: ldr s1, [x0]
; CHECK-NEXT: movi d0, #0000000000000000 ; CHECK-NEXT: movi d0, #0000000000000000
; CHECK-NEXT: ptrue p0.d, vl4 ; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: fcmeq v1.4h, v1.4h, #0.0 ; CHECK-NEXT: fcmeq v1.4h, v1.4h, #0.0
; CHECK-NEXT: umov w8, v1.h[0] ; CHECK-NEXT: umov w8, v1.h[0]
; CHECK-NEXT: umov w9, v1.h[1] ; CHECK-NEXT: fmov s2, w8
; CHECK-NEXT: fmov s1, w8 ; CHECK-NEXT: umov w8, v1.h[1]
; CHECK-NEXT: mov v1.s[1], w9 ; CHECK-NEXT: mov v2.s[1], w8
; CHECK-NEXT: shl v1.2s, v1.2s, #16 ; CHECK-NEXT: shl v1.2s, v2.2s, #16
; CHECK-NEXT: sshr v1.2s, v1.2s, #16 ; CHECK-NEXT: sshr v1.2s, v1.2s, #16
; CHECK-NEXT: fmov w8, s1 ; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov w9, v1.s[1] ; CHECK-NEXT: mov w9, v1.s[1]
; CHECK-NEXT: ldr q1, [x1] ; CHECK-NEXT: ldr q1, [x1]
; CHECK-NEXT: mov v0.h[0], w8 ; CHECK-NEXT: mov v0.h[0], w8
; CHECK-NEXT: mov v0.h[1], w9 ; CHECK-NEXT: mov v0.h[1], w9
; CHECK-NEXT: shl v0.4h, v0.4h, #15 ; CHECK-NEXT: shl v0.4h, v0.4h, #15
; CHECK-NEXT: cmlt v0.4h, v0.4h, #0 ; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
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llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll

Show All 26 Lines
; CHECK-LABEL: masked_load_v2f16: ; CHECK-LABEL: masked_load_v2f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr s1, [x0] ; CHECK-NEXT: ldr s1, [x0]
; CHECK-NEXT: movi d0, #0000000000000000 ; CHECK-NEXT: movi d0, #0000000000000000
; CHECK-NEXT: ldr s2, [x1] ; CHECK-NEXT: ldr s2, [x1]
; CHECK-NEXT: ptrue p0.h, vl4 ; CHECK-NEXT: ptrue p0.h, vl4
; CHECK-NEXT: fcmeq v1.4h, v1.4h, v2.4h ; CHECK-NEXT: fcmeq v1.4h, v1.4h, v2.4h
; CHECK-NEXT: umov w8, v1.h[0] ; CHECK-NEXT: umov w8, v1.h[0]
; CHECK-NEXT: umov w9, v1.h[1] ; CHECK-NEXT: fmov s2, w8
; CHECK-NEXT: fmov s1, w8 ; CHECK-NEXT: umov w8, v1.h[1]
; CHECK-NEXT: mov v1.s[1], w9 ; CHECK-NEXT: mov v2.s[1], w8
; CHECK-NEXT: shl v1.2s, v1.2s, #16 ; CHECK-NEXT: shl v1.2s, v2.2s, #16
; CHECK-NEXT: sshr v1.2s, v1.2s, #16 ; CHECK-NEXT: sshr v1.2s, v1.2s, #16
; CHECK-NEXT: fmov w8, s1 ; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov w9, v1.s[1] ; CHECK-NEXT: mov w9, v1.s[1]
; CHECK-NEXT: mov v0.h[0], w8 ; CHECK-NEXT: mov v0.h[0], w8
; CHECK-NEXT: mov v0.h[1], w9 ; CHECK-NEXT: mov v0.h[1], w9
; CHECK-NEXT: shl v0.4h, v0.4h, #15 ; CHECK-NEXT: shl v0.4h, v0.4h, #15
; CHECK-NEXT: cmlt v0.4h, v0.4h, #0 ; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #0 ; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #0
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llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --function masked_scatter_v8i8,masked_scatter_v8i16,masked_scatter_v8i32,masked_scatter_v8i64 --prefix VBITS_EQ_256
; RUN: llc -aarch64-sve-vector-bits-min=128 < %s | FileCheck %s -check-prefix=NO_SVE ; RUN: llc -aarch64-sve-vector-bits-min=128 < %s | FileCheck %s -check-prefix=NO_SVE
; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_EQ_256 ; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_EQ_256
; RUN: llc -aarch64-sve-vector-bits-min=384 < %s | FileCheck %s -check-prefixes=CHECK ; RUN: llc -aarch64-sve-vector-bits-min=384 < %s | FileCheck %s -check-prefixes=CHECK
; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 ; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
; RUN: llc -aarch64-sve-vector-bits-min=640 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 ; RUN: llc -aarch64-sve-vector-bits-min=640 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
; RUN: llc -aarch64-sve-vector-bits-min=768 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 ; RUN: llc -aarch64-sve-vector-bits-min=768 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
; RUN: llc -aarch64-sve-vector-bits-min=896 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 ; RUN: llc -aarch64-sve-vector-bits-min=896 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
; RUN: llc -aarch64-sve-vector-bits-min=1024 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 ; RUN: llc -aarch64-sve-vector-bits-min=1024 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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define void @masked_scatter_v8i8(<8 x i8>* %a, <8 x i8*>* %b) #0 { define void @masked_scatter_v8i8(<8 x i8>* %a, <8 x i8*>* %b) #0 {
; Ensure sensible type legalisation. ; Ensure sensible type legalisation.
; VBITS_EQ_256-LABEL: masked_scatter_v8i8: ; VBITS_EQ_256-LABEL: masked_scatter_v8i8:
; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256: // %bb.0:
; VBITS_EQ_256-NEXT: ldr d0, [x0] ; VBITS_EQ_256-NEXT: ldr d0, [x0]
; VBITS_EQ_256-NEXT: mov x8, #4 ; VBITS_EQ_256-NEXT: mov x8, #4
; VBITS_EQ_256-NEXT: ptrue p0.d, vl4 ; VBITS_EQ_256-NEXT: ptrue p0.d, vl4
; VBITS_EQ_256-NEXT: cmeq v1.8b, v0.8b, #0 ; VBITS_EQ_256-NEXT: cmeq v1.8b, v0.8b, #0
; VBITS_EQ_256-NEXT: zip1 v5.8b, v0.8b, v0.8b
; VBITS_EQ_256-NEXT: ld1d { z3.d }, p0/z, [x1, x8, lsl #3] ; VBITS_EQ_256-NEXT: ld1d { z3.d }, p0/z, [x1, x8, lsl #3]
; VBITS_EQ_256-NEXT: ld1d { z4.d }, p0/z, [x1] ; VBITS_EQ_256-NEXT: ld1d { z4.d }, p0/z, [x1]
; VBITS_EQ_256-NEXT: zip1 v5.8b, v0.8b, v0.8b
; VBITS_EQ_256-NEXT: zip1 v2.8b, v1.8b, v0.8b ; VBITS_EQ_256-NEXT: zip1 v2.8b, v1.8b, v0.8b
; VBITS_EQ_256-NEXT: zip2 v1.8b, v1.8b, v0.8b ; VBITS_EQ_256-NEXT: zip2 v1.8b, v1.8b, v0.8b
; VBITS_EQ_256-NEXT: zip2 v0.8b, v0.8b, v0.8b ; VBITS_EQ_256-NEXT: zip2 v0.8b, v0.8b, v0.8b
; VBITS_EQ_256-NEXT: shl v2.4h, v2.4h, #8 ; VBITS_EQ_256-NEXT: shl v2.4h, v2.4h, #8
; VBITS_EQ_256-NEXT: shl v1.4h, v1.4h, #8 ; VBITS_EQ_256-NEXT: shl v1.4h, v1.4h, #8
; VBITS_EQ_256-NEXT: uunpklo z0.s, z0.h ; VBITS_EQ_256-NEXT: uunpklo z0.s, z0.h
; VBITS_EQ_256-NEXT: sshr v2.4h, v2.4h, #8 ; VBITS_EQ_256-NEXT: sshr v2.4h, v2.4h, #8
; VBITS_EQ_256-NEXT: sshr v1.4h, v1.4h, #8 ; VBITS_EQ_256-NEXT: sshr v1.4h, v1.4h, #8
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define void @masked_scatter_v8i16(<8 x i16>* %a, <8 x i16*>* %b) #0 { define void @masked_scatter_v8i16(<8 x i16>* %a, <8 x i16*>* %b) #0 {
; Ensure sensible type legalisation. ; Ensure sensible type legalisation.
; VBITS_EQ_256-LABEL: masked_scatter_v8i16: ; VBITS_EQ_256-LABEL: masked_scatter_v8i16:
; VBITS_EQ_256: // %bb.0: ; VBITS_EQ_256: // %bb.0:
; VBITS_EQ_256-NEXT: ldr q0, [x0] ; VBITS_EQ_256-NEXT: ldr q0, [x0]
; VBITS_EQ_256-NEXT: mov x8, #4 ; VBITS_EQ_256-NEXT: mov x8, #4
; VBITS_EQ_256-NEXT: ptrue p0.d, vl4 ; VBITS_EQ_256-NEXT: ptrue p0.d, vl4
; VBITS_EQ_256-NEXT: cmeq v1.8h, v0.8h, #0 ; VBITS_EQ_256-NEXT: cmeq v1.8h, v0.8h, #0
; VBITS_EQ_256-NEXT: ld1d { z4.d }, p0/z, [x1, x8, lsl #3] ; VBITS_EQ_256-NEXT: ld1d { z2.d }, p0/z, [x1, x8, lsl #3]
; VBITS_EQ_256-NEXT: ext v3.16b, v0.16b, v0.16b, #8 ; VBITS_EQ_256-NEXT: ld1d { z4.d }, p0/z, [x1]
; VBITS_EQ_256-NEXT: uunpklo z0.s, z0.h ; VBITS_EQ_256-NEXT: sunpklo z3.s, z1.h
; VBITS_EQ_256-NEXT: sunpklo z2.s, z1.h ; VBITS_EQ_256-NEXT: sunpklo z3.d, z3.s
; VBITS_EQ_256-NEXT: uunpklo z0.d, z0.s
; VBITS_EQ_256-NEXT: ext v1.16b, v1.16b, v1.16b, #8 ; VBITS_EQ_256-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; VBITS_EQ_256-NEXT: sunpklo z2.d, z2.s ; VBITS_EQ_256-NEXT: cmpne p1.d, p0/z, z3.d, #0
; VBITS_EQ_256-NEXT: cmpne p1.d, p0/z, z2.d, #0 ; VBITS_EQ_256-NEXT: uunpklo z3.s, z0.h
; VBITS_EQ_256-NEXT: ld1d { z2.d }, p0/z, [x1] ; VBITS_EQ_256-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; VBITS_EQ_256-NEXT: uunpklo z3.s, z3.h
; VBITS_EQ_256-NEXT: sunpklo z1.s, z1.h ; VBITS_EQ_256-NEXT: sunpklo z1.s, z1.h
; VBITS_EQ_256-NEXT: sunpklo z1.d, z1.s ; VBITS_EQ_256-NEXT: sunpklo z1.d, z1.s
; VBITS_EQ_256-NEXT: st1h { z0.d }, p1, [z2.d] ; VBITS_EQ_256-NEXT: uunpklo z3.d, z3.s
; VBITS_EQ_256-NEXT: uunpklo z0.s, z0.h
; VBITS_EQ_256-NEXT: cmpne p0.d, p0/z, z1.d, #0 ; VBITS_EQ_256-NEXT: cmpne p0.d, p0/z, z1.d, #0
; VBITS_EQ_256-NEXT: uunpklo z1.d, z3.s ; VBITS_EQ_256-NEXT: uunpklo z0.d, z0.s
; VBITS_EQ_256-NEXT: st1h { z1.d }, p0, [z4.d] ; VBITS_EQ_256-NEXT: st1h { z3.d }, p1, [z4.d]
; VBITS_EQ_256-NEXT: st1h { z0.d }, p0, [z2.d]
; VBITS_EQ_256-NEXT: ret ; VBITS_EQ_256-NEXT: ret
; VBITS_GE_512-LABEL: masked_scatter_v8i16: ; VBITS_GE_512-LABEL: masked_scatter_v8i16:
; VBITS_GE_512: // %bb.0: ; VBITS_GE_512: // %bb.0:
; VBITS_GE_512-NEXT: ldr q0, [x0] ; VBITS_GE_512-NEXT: ldr q0, [x0]
; VBITS_GE_512-NEXT: ptrue p0.d, vl8 ; VBITS_GE_512-NEXT: ptrue p0.d, vl8
; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1] ; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]
; VBITS_GE_512-NEXT: cmeq v2.8h, v0.8h, #0 ; VBITS_GE_512-NEXT: cmeq v2.8h, v0.8h, #0
; VBITS_GE_512-NEXT: uunpklo z0.s, z0.h ; VBITS_GE_512-NEXT: uunpklo z0.s, z0.h
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; CHECK-LABEL: masked_scatter_v2f16: ; CHECK-LABEL: masked_scatter_v2f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr s1, [x0] ; CHECK-NEXT: ldr s1, [x0]
; CHECK-NEXT: movi d0, #0000000000000000 ; CHECK-NEXT: movi d0, #0000000000000000
; CHECK-NEXT: ptrue p0.d, vl4 ; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: fcmeq v2.4h, v1.4h, #0.0 ; CHECK-NEXT: fcmeq v2.4h, v1.4h, #0.0
; CHECK-NEXT: uunpklo z1.s, z1.h ; CHECK-NEXT: uunpklo z1.s, z1.h
; CHECK-NEXT: umov w8, v2.h[0] ; CHECK-NEXT: umov w8, v2.h[0]
; CHECK-NEXT: umov w9, v2.h[1] ; CHECK-NEXT: fmov s3, w8
; CHECK-NEXT: fmov s2, w8 ; CHECK-NEXT: umov w8, v2.h[1]
; CHECK-NEXT: mov v2.s[1], w9 ; CHECK-NEXT: mov v3.s[1], w8
; CHECK-NEXT: shl v2.2s, v2.2s, #16 ; CHECK-NEXT: shl v2.2s, v3.2s, #16
; CHECK-NEXT: sshr v2.2s, v2.2s, #16 ; CHECK-NEXT: sshr v2.2s, v2.2s, #16
; CHECK-NEXT: fmov w8, s2 ; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: mov w9, v2.s[1] ; CHECK-NEXT: mov w9, v2.s[1]
; CHECK-NEXT: ldr q2, [x1] ; CHECK-NEXT: ldr q2, [x1]
; CHECK-NEXT: mov v0.h[0], w8 ; CHECK-NEXT: mov v0.h[0], w8
; CHECK-NEXT: mov v0.h[1], w9 ; CHECK-NEXT: mov v0.h[1], w9
; CHECK-NEXT: shl v0.4h, v0.4h, #15 ; CHECK-NEXT: shl v0.4h, v0.4h, #15
; CHECK-NEXT: cmlt v0.4h, v0.4h, #0 ; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
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ret void ret void
} }
define void @masked_scatter_v2f64(<2 x double>* %a, <2 x double*>* %b) #0 { define void @masked_scatter_v2f64(<2 x double>* %a, <2 x double*>* %b) #0 {
; CHECK-LABEL: masked_scatter_v2f64: ; CHECK-LABEL: masked_scatter_v2f64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ptrue p0.d, vl2 ; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: ldr q2, [x1] ; CHECK-NEXT: ldr q1, [x1]
; CHECK-NEXT: fcmeq v1.2d, v0.2d, #0.0 ; CHECK-NEXT: fcmeq v2.2d, v0.2d, #0.0
; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #0 ; CHECK-NEXT: cmpne p0.d, p0/z, z2.d, #0
; CHECK-NEXT: st1d { z0.d }, p0, [z2.d] ; CHECK-NEXT: st1d { z0.d }, p0, [z1.d]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vals = load <2 x double>, <2 x double>* %a %vals = load <2 x double>, <2 x double>* %a
%ptrs = load <2 x double*>, <2 x double*>* %b %ptrs = load <2 x double*>, <2 x double*>* %b
%mask = fcmp oeq <2 x double> %vals, zeroinitializer %mask = fcmp oeq <2 x double> %vals, zeroinitializer
call void @llvm.masked.scatter.v2f64(<2 x double> %vals, <2 x double*> %ptrs, i32 8, <2 x i1> %mask) call void @llvm.masked.scatter.v2f64(<2 x double> %vals, <2 x double*> %ptrs, i32 8, <2 x i1> %mask)
ret void ret void
} }
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llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll

Show All 26 Lines
; CHECK-LABEL: masked_store_v2f16: ; CHECK-LABEL: masked_store_v2f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr s1, [x0] ; CHECK-NEXT: ldr s1, [x0]
; CHECK-NEXT: movi d0, #0000000000000000 ; CHECK-NEXT: movi d0, #0000000000000000
; CHECK-NEXT: ldr s2, [x1] ; CHECK-NEXT: ldr s2, [x1]
; CHECK-NEXT: ptrue p0.h, vl4 ; CHECK-NEXT: ptrue p0.h, vl4
; CHECK-NEXT: fcmeq v2.4h, v1.4h, v2.4h ; CHECK-NEXT: fcmeq v2.4h, v1.4h, v2.4h
; CHECK-NEXT: umov w8, v2.h[0] ; CHECK-NEXT: umov w8, v2.h[0]
; CHECK-NEXT: umov w9, v2.h[1] ; CHECK-NEXT: fmov s3, w8
; CHECK-NEXT: fmov s2, w8 ; CHECK-NEXT: umov w8, v2.h[1]
; CHECK-NEXT: mov v2.s[1], w9 ; CHECK-NEXT: mov v3.s[1], w8
; CHECK-NEXT: shl v2.2s, v2.2s, #16 ; CHECK-NEXT: shl v2.2s, v3.2s, #16
; CHECK-NEXT: sshr v2.2s, v2.2s, #16 ; CHECK-NEXT: sshr v2.2s, v2.2s, #16
; CHECK-NEXT: fmov w8, s2 ; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: mov w9, v2.s[1] ; CHECK-NEXT: mov w9, v2.s[1]
; CHECK-NEXT: mov v0.h[0], w8 ; CHECK-NEXT: mov v0.h[0], w8
; CHECK-NEXT: mov v0.h[1], w9 ; CHECK-NEXT: mov v0.h[1], w9
; CHECK-NEXT: shl v0.4h, v0.4h, #15 ; CHECK-NEXT: shl v0.4h, v0.4h, #15
; CHECK-NEXT: cmlt v0.4h, v0.4h, #0 ; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #0 ; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #0
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llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll

Show First 20 Lines • Show All 199 Lines • ▼ Show 20 Lines
; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0 ; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
; CHECK-NEXT: .cfi_def_cfa w29, 16 ; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-NEXT: mov z1.d, z0.d[2] ; CHECK-NEXT: mov z1.d, z0.d[2]
; CHECK-NEXT: mov z2.d, z0.d[3] ; CHECK-NEXT: mov z2.d, z0.d[3]
; CHECK-NEXT: mov x10, v0.d[1]
; CHECK-NEXT: fmov x8, d1 ; CHECK-NEXT: fmov x8, d1
; CHECK-NEXT: fmov x9, d2 ; CHECK-NEXT: fmov x9, d2
; CHECK-NEXT: fmov x11, d0 ; CHECK-NEXT: fmov x10, d0
; CHECK-NEXT: stp x9, x8, [sp, #16] ; CHECK-NEXT: stp x9, x8, [sp, #16]
; CHECK-NEXT: stp x10, x11, [sp] ; CHECK-NEXT: mov x8, v0.d[1]
; CHECK-NEXT: stp x8, x10, [sp]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT: st1d { z0.d }, p0, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <4 x i64>, <4 x i64>* %a %tmp1 = load <4 x i64>, <4 x i64>* %a
%tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> %tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
store <4 x i64> %tmp2, <4 x i64>* %a store <4 x i64> %tmp2, <4 x i64>* %a
Show All 12 Lines
; CHECK-NEXT: sub x9, sp, #48 ; CHECK-NEXT: sub x9, sp, #48
; CHECK-NEXT: mov x29, sp ; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0 ; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
; CHECK-NEXT: .cfi_def_cfa w29, 16 ; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ptrue p0.s, vl8 ; CHECK-NEXT: ptrue p0.s, vl8
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
; CHECK-NEXT: fmov w11, s0
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: mov w9, v0.s[2] ; CHECK-NEXT: mov w9, v0.s[2]
; CHECK-NEXT: mov w11, v0.s[3] ; CHECK-NEXT: mov w10, v0.s[3]
; CHECK-NEXT: fmov w10, s0
; CHECK-NEXT: mov z1.s, z0.s[4] ; CHECK-NEXT: mov z1.s, z0.s[4]
; CHECK-NEXT: mov z2.s, z0.s[5] ; CHECK-NEXT: mov z2.s, z0.s[5]
; CHECK-NEXT: mov z3.s, z0.s[6] ; CHECK-NEXT: mov z3.s, z0.s[6]
; CHECK-NEXT: mov z0.s, z0.s[7] ; CHECK-NEXT: mov z0.s, z0.s[7]
; CHECK-NEXT: stp w8, w10, [sp, #24] ; CHECK-NEXT: stp w10, w9, [sp, #16]
; CHECK-NEXT: fmov w10, s1 ; CHECK-NEXT: fmov w9, s1
; CHECK-NEXT: fmov w8, s2 ; CHECK-NEXT: fmov w10, s2
; CHECK-NEXT: stp w11, w9, [sp, #16] ; CHECK-NEXT: stp w8, w11, [sp, #24]
; CHECK-NEXT: fmov w9, s3 ; CHECK-NEXT: fmov w11, s3
; CHECK-NEXT: fmov w11, s0 ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: stp w8, w10, [sp, #8] ; CHECK-NEXT: stp w10, w9, [sp, #8]
; CHECK-NEXT: stp w11, w9, [sp] ; CHECK-NEXT: stp w8, w11, [sp]
; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp]
; CHECK-NEXT: st1w { z0.s }, p0, [x0] ; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <8 x i32>, <8 x i32>* %a %tmp1 = load <8 x i32>, <8 x i32>* %a
%tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
store <8 x i32> %tmp2, <8 x i32>* %a store <8 x i32> %tmp2, <8 x i32>* %a
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; CHECK-NEXT: sub x9, sp, #48 ; CHECK-NEXT: sub x9, sp, #48
; CHECK-NEXT: mov x29, sp ; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0 ; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
; CHECK-NEXT: .cfi_def_cfa w29, 16 ; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
; CHECK-NEXT: mov z1.h, z0.h[8]
; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: fmov w9, s1 ; CHECK-NEXT: mov z1.h, z0.h[8]
; CHECK-NEXT: mov z5.h, z0.h[12]
; CHECK-NEXT: mov z2.h, z0.h[9] ; CHECK-NEXT: mov z2.h, z0.h[9]
; CHECK-NEXT: mov z3.h, z0.h[10] ; CHECK-NEXT: mov z3.h, z0.h[10]
; CHECK-NEXT: mov z4.h, z0.h[11] ; CHECK-NEXT: fmov w9, s1
; CHECK-NEXT: fmov w11, s2 ; CHECK-NEXT: fmov w10, s2
; CHECK-NEXT: strh w9, [sp, #30]
; CHECK-NEXT: fmov w9, s5
; CHECK-NEXT: fmov w12, s3
; CHECK-NEXT: strh w8, [sp, #14] ; CHECK-NEXT: strh w8, [sp, #14]
; CHECK-NEXT: fmov w8, s4 ; CHECK-NEXT: fmov w8, s3
; CHECK-NEXT: mov z4.h, z0.h[11]
; CHECK-NEXT: mov z5.h, z0.h[12]
; CHECK-NEXT: mov z6.h, z0.h[13] ; CHECK-NEXT: mov z6.h, z0.h[13]
; CHECK-NEXT: strh w9, [sp, #30]
; CHECK-NEXT: fmov w9, s4
; CHECK-NEXT: strh w10, [sp, #28]
; CHECK-NEXT: fmov w10, s5
; CHECK-NEXT: strh w8, [sp, #26]
; CHECK-NEXT: fmov w8, s6
; CHECK-NEXT: mov z7.h, z0.h[14] ; CHECK-NEXT: mov z7.h, z0.h[14]
; CHECK-NEXT: mov z16.h, z0.h[15] ; CHECK-NEXT: mov z1.h, z0.h[15]
; CHECK-NEXT: umov w10, v0.h[1] ; CHECK-NEXT: strh w9, [sp, #24]
; CHECK-NEXT: strh w9, [sp, #22] ; CHECK-NEXT: fmov w9, s7
; CHECK-NEXT: strh w10, [sp, #22]
; CHECK-NEXT: fmov w10, s1
; CHECK-NEXT: strh w8, [sp, #20]
; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: strh w9, [sp, #18]
; CHECK-NEXT: umov w9, v0.h[2] ; CHECK-NEXT: umov w9, v0.h[2]
; CHECK-NEXT: strh w11, [sp, #28] ; CHECK-NEXT: strh w10, [sp, #16]
; CHECK-NEXT: fmov w11, s6 ; CHECK-NEXT: umov w10, v0.h[3]
; CHECK-NEXT: strh w12, [sp, #26] ; CHECK-NEXT: strh w8, [sp, #12]
; CHECK-NEXT: fmov w12, s7 ; CHECK-NEXT: umov w8, v0.h[4]
; CHECK-NEXT: strh w8, [sp, #24]
; CHECK-NEXT: fmov w8, s16
; CHECK-NEXT: strh w10, [sp, #12]
; CHECK-NEXT: strh w11, [sp, #20]
; CHECK-NEXT: umov w11, v0.h[3]
; CHECK-NEXT: strh w12, [sp, #18]
; CHECK-NEXT: umov w12, v0.h[4]
; CHECK-NEXT: strh w8, [sp, #16]
; CHECK-NEXT: umov w8, v0.h[5]
; CHECK-NEXT: umov w10, v0.h[6]
; CHECK-NEXT: strh w9, [sp, #10] ; CHECK-NEXT: strh w9, [sp, #10]
; CHECK-NEXT: umov w9, v0.h[7] ; CHECK-NEXT: umov w9, v0.h[5]
; CHECK-NEXT: strh w11, [sp, #8] ; CHECK-NEXT: strh w10, [sp, #8]
; CHECK-NEXT: strh w12, [sp, #6] ; CHECK-NEXT: umov w10, v0.h[6]
; CHECK-NEXT: strh w8, [sp, #4] ; CHECK-NEXT: strh w8, [sp, #6]
; CHECK-NEXT: umov w8, v0.h[7]
; CHECK-NEXT: strh w9, [sp, #4]
; CHECK-NEXT: strh w10, [sp, #2] ; CHECK-NEXT: strh w10, [sp, #2]
; CHECK-NEXT: strh w9, [sp] ; CHECK-NEXT: strh w8, [sp]
; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp]
; CHECK-NEXT: st1h { z0.h }, p0, [x0] ; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <16 x i16>, <16 x i16>* %a %tmp1 = load <16 x i16>, <16 x i16>* %a
%tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8> %tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
store <16 x i16> %tmp2, <16 x i16>* %a store <16 x i16> %tmp2, <16 x i16>* %a
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llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll

Show All 11 Lines; CHECK-LABEL: hang_when_merging_stores_after_legalisation:
%interleaved.vec = shufflevector <8 x i32> %splat, <8 x i32> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> %interleaved.vec = shufflevector <8 x i32> %splat, <8 x i32> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
store <8 x i32> %interleaved.vec, <8 x i32>* %a, align 4 store <8 x i32> %interleaved.vec, <8 x i32>* %a, align 4
ret void ret void
} }
; Ensure we don't crash when trying to lower a shuffle via and extract ; Ensure we don't crash when trying to lower a shuffle via and extract
define void @crash_when_lowering_extract_shuffle(<32 x i32>* %dst, i1 %cond) #0 { define void @crash_when_lowering_extract_shuffle(<32 x i32>* %dst, i1 %cond) #0 {
; CHECK-LABEL: crash_when_lowering_extract_shuffle: ; CHECK-LABEL: crash_when_lowering_extract_shuffle:
; CHECK: ld1w { z3.s }, p0/z, [x0] ; CHECK: ld1w { z3.s }, p0/z
; CHECK: st1w { z3.s }, p0, [x0] ; CHECK: st1w { z3.s }, p0
%broadcast.splat = shufflevector <32 x i1> zeroinitializer, <32 x i1> zeroinitializer, <32 x i32> zeroinitializer %broadcast.splat = shufflevector <32 x i1> zeroinitializer, <32 x i1> zeroinitializer, <32 x i32> zeroinitializer
br i1 %cond, label %exit, label %vector.body br i1 %cond, label %exit, label %vector.body
vector.body: vector.body:
%1 = load <32 x i32>, <32 x i32>* %dst, align 16 %1 = load <32 x i32>, <32 x i32>* %dst, align 16
%predphi = select <32 x i1> %broadcast.splat, <32 x i32> zeroinitializer, <32 x i32> %1 %predphi = select <32 x i1> %broadcast.splat, <32 x i32> zeroinitializer, <32 x i32> %1
store <32 x i32> %predphi, <32 x i32>* %dst, align 16 store <32 x i32> %predphi, <32 x i32>* %dst, align 16
br label %exit br label %exit
exit: exit:
ret void ret void
} }
attributes #0 = { vscale_range(2,2) "target-features"="+sve" } attributes #0 = { vscale_range(2,2) "target-features"="+sve" }

llvm/test/CodeGen/AArch64/sve-select.ll

Show First 20 Lines • Show All 635 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %fadd %sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %fadd
%sel2 = select <vscale x 4 x i1> %p, <vscale x 4 x float> %c, <vscale x 4 x float> %sel %sel2 = select <vscale x 4 x i1> %p, <vscale x 4 x float> %c, <vscale x 4 x float> %sel
ret <vscale x 4 x float> %sel2 ret <vscale x 4 x float> %sel2
} }
define <4 x float> @select_f32_no_invert_not_scalable(<4 x float> %a, <4 x float> %b) #0 { define <4 x float> @select_f32_no_invert_not_scalable(<4 x float> %a, <4 x float> %b) #0 {
; CHECK-LABEL: select_f32_no_invert_not_scalable: ; CHECK-LABEL: select_f32_no_invert_not_scalable:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcmeq v2.4s, v0.4s, #0.0
; CHECK-NEXT: fmul v1.4s, v0.4s, v1.4s ; CHECK-NEXT: fmul v1.4s, v0.4s, v1.4s
; CHECK-NEXT: fcmeq v2.4s, v0.4s, #0.0
; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%p = fcmp oeq <4 x float> %a, zeroinitializer %p = fcmp oeq <4 x float> %a, zeroinitializer
%fmul = fmul <4 x float> %a, %b %fmul = fmul <4 x float> %a, %b
%sel = select <4 x i1> %p, <4 x float> %a, <4 x float> %fmul %sel = select <4 x i1> %p, <4 x float> %a, <4 x float> %fmul
ret <4 x float> %sel ret <4 x float> %sel
} }

llvm/test/CodeGen/AArch64/uadd_sat_vec.ll

Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%z = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> %x, <8 x i8> %y) %z = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> %x, <8 x i8> %y)
store <8 x i8> %z, <8 x i8>* %pz store <8 x i8> %z, <8 x i8>* %pz
ret void ret void
} }
define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind { define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
; CHECK-LABEL: v4i8: ; CHECK-LABEL: v4i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr s1, [x0] ; CHECK-NEXT: ldr s0, [x0]
; CHECK-NEXT: movi d0, #0xff00ff00ff00ff ; CHECK-NEXT: ldr s1, [x1]
; CHECK-NEXT: ldr s2, [x1] ; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: ushll v1.8h, v1.8b, #0 ; CHECK-NEXT: ushll v1.8h, v1.8b, #0
; CHECK-NEXT: ushll v2.8h, v2.8b, #0 ; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
; CHECK-NEXT: add v1.4h, v1.4h, v2.4h ; CHECK-NEXT: movi d1, #0xff00ff00ff00ff
; CHECK-NEXT: umin v0.4h, v1.4h, v0.4h ; CHECK-NEXT: umin v0.4h, v0.4h, v1.4h
; CHECK-NEXT: xtn v0.8b, v0.8h ; CHECK-NEXT: xtn v0.8b, v0.8h
; CHECK-NEXT: str s0, [x2] ; CHECK-NEXT: str s0, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <4 x i8>, <4 x i8>* %px %x = load <4 x i8>, <4 x i8>* %px
%y = load <4 x i8>, <4 x i8>* %py %y = load <4 x i8>, <4 x i8>* %py
%z = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %x, <4 x i8> %y) %z = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %x, <4 x i8> %y)
store <4 x i8> %z, <4 x i8>* %pz store <4 x i8> %z, <4 x i8>* %pz
ret void ret void
} }
define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind { define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
; CHECK-LABEL: v2i8: ; CHECK-LABEL: v2i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldrb w8, [x1] ; CHECK-NEXT: ldrb w8, [x1]
; CHECK-NEXT: movi d0, #0x0000ff000000ff ; CHECK-NEXT: movi d0, #0x0000ff000000ff
; CHECK-NEXT: ldrb w9, [x0] ; CHECK-NEXT: ldrb w9, [x0]
; CHECK-NEXT: ldrb w10, [x1, #1] ; CHECK-NEXT: ldrb w10, [x1, #1]
; CHECK-NEXT: fmov s2, w8 ; CHECK-NEXT: fmov s2, w8
; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: ldrb w9, [x0, #1] ; CHECK-NEXT: ldrb w9, [x0, #1]
; CHECK-NEXT: mov v2.s[1], w10 ; CHECK-NEXT: mov v2.s[1], w10
; CHECK-NEXT: mov v1.s[1], w9 ; CHECK-NEXT: mov v1.s[1], w9
; CHECK-NEXT: add v1.2s, v1.2s, v2.2s ; CHECK-NEXT: add v1.2s, v1.2s, v2.2s
; CHECK-NEXT: umin v0.2s, v1.2s, v0.2s ; CHECK-NEXT: umin v0.2s, v1.2s, v0.2s
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: mov w9, v0.s[1]
; CHECK-NEXT: strb w9, [x2] ; CHECK-NEXT: strb w9, [x2, #1]
; CHECK-NEXT: strb w8, [x2, #1] ; CHECK-NEXT: strb w8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i8>, <2 x i8>* %px %x = load <2 x i8>, <2 x i8>* %px
%y = load <2 x i8>, <2 x i8>* %py %y = load <2 x i8>, <2 x i8>* %py
%z = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %x, <2 x i8> %y) %z = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
store <2 x i8> %z, <2 x i8>* %pz store <2 x i8> %z, <2 x i8>* %pz
ret void ret void
} }
Show All 21 Lines
; CHECK-NEXT: ldrh w10, [x1, #2] ; CHECK-NEXT: ldrh w10, [x1, #2]
; CHECK-NEXT: fmov s2, w8 ; CHECK-NEXT: fmov s2, w8
; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: ldrh w9, [x0, #2] ; CHECK-NEXT: ldrh w9, [x0, #2]
; CHECK-NEXT: mov v2.s[1], w10 ; CHECK-NEXT: mov v2.s[1], w10
; CHECK-NEXT: mov v1.s[1], w9 ; CHECK-NEXT: mov v1.s[1], w9
; CHECK-NEXT: add v1.2s, v1.2s, v2.2s ; CHECK-NEXT: add v1.2s, v1.2s, v2.2s
; CHECK-NEXT: umin v0.2s, v1.2s, v0.2s ; CHECK-NEXT: umin v0.2s, v1.2s, v0.2s
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: mov w9, v0.s[1]
; CHECK-NEXT: strh w9, [x2] ; CHECK-NEXT: strh w9, [x2, #2]
; CHECK-NEXT: strh w8, [x2, #2] ; CHECK-NEXT: strh w8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i16>, <2 x i16>* %px %x = load <2 x i16>, <2 x i16>* %px
%y = load <2 x i16>, <2 x i16>* %py %y = load <2 x i16>, <2 x i16>* %py
%z = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %x, <2 x i16> %y) %z = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
store <2 x i16> %z, <2 x i16>* %pz store <2 x i16> %z, <2 x i16>* %pz
ret void ret void
} }
▲ Show 20 Lines • Show All 179 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll

Show All 25 Lines
; 16-bit vector width ; 16-bit vector width
; ============================================================================ ; ; ============================================================================ ;
define <2 x i8> @out_v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> %mask) nounwind { define <2 x i8> @out_v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> %mask) nounwind {
; CHECK-LABEL: out_v2i8: ; CHECK-LABEL: out_v2i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi d3, #0x0000ff000000ff ; CHECK-NEXT: movi d3, #0x0000ff000000ff
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b ; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b ; CHECK-NEXT: eor v3.8b, v2.8b, v3.8b
; CHECK-NEXT: and v1.8b, v1.8b, v2.8b ; CHECK-NEXT: and v1.8b, v1.8b, v3.8b
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mx = and <2 x i8> %x, %mask %mx = and <2 x i8> %x, %mask
%notmask = xor <2 x i8> %mask, <i8 -1, i8 -1> %notmask = xor <2 x i8> %mask, <i8 -1, i8 -1>
%my = and <2 x i8> %y, %notmask %my = and <2 x i8> %y, %notmask
%r = or <2 x i8> %mx, %my %r = or <2 x i8> %mx, %my
ret <2 x i8> %r ret <2 x i8> %r
} }
Show All 14 Lines
; 32-bit vector width ; 32-bit vector width
; ============================================================================ ; ; ============================================================================ ;
define <4 x i8> @out_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind { define <4 x i8> @out_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {
; CHECK-LABEL: out_v4i8: ; CHECK-LABEL: out_v4i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi d3, #0xff00ff00ff00ff ; CHECK-NEXT: movi d3, #0xff00ff00ff00ff
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b ; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b ; CHECK-NEXT: eor v3.8b, v2.8b, v3.8b
; CHECK-NEXT: and v1.8b, v1.8b, v2.8b ; CHECK-NEXT: and v1.8b, v1.8b, v3.8b
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mx = and <4 x i8> %x, %mask %mx = and <4 x i8> %x, %mask
%notmask = xor <4 x i8> %mask, <i8 -1, i8 -1, i8 -1, i8 -1> %notmask = xor <4 x i8> %mask, <i8 -1, i8 -1, i8 -1, i8 -1>
%my = and <4 x i8> %y, %notmask %my = and <4 x i8> %y, %notmask
%r = or <4 x i8> %mx, %my %r = or <4 x i8> %mx, %my
ret <4 x i8> %r ret <4 x i8> %r
} }
define <4 x i8> @out_v4i8_undef(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind { define <4 x i8> @out_v4i8_undef(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {
; CHECK-LABEL: out_v4i8_undef: ; CHECK-LABEL: out_v4i8_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi d3, #0xff00ff00ff00ff ; CHECK-NEXT: movi d3, #0xff00ff00ff00ff
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b ; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b ; CHECK-NEXT: eor v3.8b, v2.8b, v3.8b
; CHECK-NEXT: and v1.8b, v1.8b, v2.8b ; CHECK-NEXT: and v1.8b, v1.8b, v3.8b
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mx = and <4 x i8> %x, %mask %mx = and <4 x i8> %x, %mask
%notmask = xor <4 x i8> %mask, <i8 -1, i8 -1, i8 undef, i8 -1> %notmask = xor <4 x i8> %mask, <i8 -1, i8 -1, i8 undef, i8 -1>
%my = and <4 x i8> %y, %notmask %my = and <4 x i8> %y, %notmask
%r = or <4 x i8> %mx, %my %r = or <4 x i8> %mx, %my
ret <4 x i8> %r ret <4 x i8> %r
} }
define <2 x i16> @out_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind { define <2 x i16> @out_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind {
; CHECK-LABEL: out_v2i16: ; CHECK-LABEL: out_v2i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi d3, #0x00ffff0000ffff ; CHECK-NEXT: movi d3, #0x00ffff0000ffff
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b ; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b ; CHECK-NEXT: eor v3.8b, v2.8b, v3.8b
; CHECK-NEXT: and v1.8b, v1.8b, v2.8b ; CHECK-NEXT: and v1.8b, v1.8b, v3.8b
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mx = and <2 x i16> %x, %mask %mx = and <2 x i16> %x, %mask
%notmask = xor <2 x i16> %mask, <i16 -1, i16 -1> %notmask = xor <2 x i16> %mask, <i16 -1, i16 -1>
%my = and <2 x i16> %y, %notmask %my = and <2 x i16> %y, %notmask
%r = or <2 x i16> %mx, %my %r = or <2 x i16> %mx, %my
ret <2 x i16> %r ret <2 x i16> %r
} }
▲ Show 20 Lines • Show All 318 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
} }
define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind { define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
; CHECK-LABEL: test_urem_vec: ; CHECK-LABEL: test_urem_vec:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fmov s0, w0 ; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: adrp x8, .LCPI4_0 ; CHECK-NEXT: adrp x8, .LCPI4_0
; CHECK-NEXT: adrp x9, .LCPI4_1 ; CHECK-NEXT: adrp x9, .LCPI4_1
; CHECK-NEXT: movi d3, #0x0000000000ffff
; CHECK-NEXT: mov v0.h[1], w1 ; CHECK-NEXT: mov v0.h[1], w1
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI4_0] ; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI4_0]
; CHECK-NEXT: ldr d2, [x9, :lo12:.LCPI4_1] ; CHECK-NEXT: ldr d2, [x9, :lo12:.LCPI4_1]
; CHECK-NEXT: adrp x8, .LCPI4_2 ; CHECK-NEXT: adrp x8, .LCPI4_2
; CHECK-NEXT: mov v0.h[2], w2 ; CHECK-NEXT: mov v0.h[2], w2
; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h ; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h
; CHECK-NEXT: movi d1, #0x0000000000ffff ; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI4_2]
; CHECK-NEXT: mul v0.4h, v0.4h, v2.4h
; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI4_2]
; CHECK-NEXT: adrp x8, .LCPI4_3 ; CHECK-NEXT: adrp x8, .LCPI4_3
; CHECK-NEXT: shl v3.4h, v0.4h, #1 ; CHECK-NEXT: mul v0.4h, v0.4h, v2.4h
; CHECK-NEXT: shl v2.4h, v0.4h, #1
; CHECK-NEXT: bic v0.4h, #248, lsl #8 ; CHECK-NEXT: bic v0.4h, #248, lsl #8
; CHECK-NEXT: ushl v0.4h, v0.4h, v1.4h ; CHECK-NEXT: ushl v0.4h, v0.4h, v3.4h
; CHECK-NEXT: ushl v1.4h, v3.4h, v2.4h ; CHECK-NEXT: ushl v1.4h, v2.4h, v1.4h
; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI4_3] ; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI4_3]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: bic v0.4h, #248, lsl #8 ; CHECK-NEXT: bic v0.4h, #248, lsl #8
; CHECK-NEXT: cmhi v0.4h, v0.4h, v2.4h ; CHECK-NEXT: cmhi v0.4h, v0.4h, v2.4h
; CHECK-NEXT: umov w0, v0.h[0] ; CHECK-NEXT: umov w0, v0.h[0]
; CHECK-NEXT: umov w1, v0.h[1] ; CHECK-NEXT: umov w1, v0.h[1]
; CHECK-NEXT: umov w2, v0.h[2] ; CHECK-NEXT: umov w2, v0.h[2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <3 x i11> %X, <i11 6, i11 7, i11 -5> %urem = urem <3 x i11> %X, <i11 6, i11 7, i11 -5>
%cmp = icmp ne <3 x i11> %urem, <i11 0, i11 1, i11 2> %cmp = icmp ne <3 x i11> %urem, <i11 0, i11 1, i11 2>
ret <3 x i1> %cmp ret <3 x i1> %cmp
} }

llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
; Odd+Even divisors ; Odd+Even divisors
define <4 x i32> @test_urem_odd_even(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_even(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_even: ; CHECK-LABEL: test_urem_odd_even:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI0_0 ; CHECK-NEXT: adrp x8, .LCPI0_0
; CHECK-NEXT: adrp x9, .LCPI0_2 ; CHECK-NEXT: adrp x9, .LCPI0_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
; CHECK-NEXT: adrp x8, .LCPI0_1 ; CHECK-NEXT: adrp x8, .LCPI0_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI0_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI0_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_1]
; CHECK-NEXT: adrp x8, .LCPI0_3 ; CHECK-NEXT: adrp x8, .LCPI0_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 14, i32 25, i32 100> %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 25, i32 100>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;==============================================================================; ;==============================================================================;
; One all-ones divisor in odd divisor ; One all-ones divisor in odd divisor
define <4 x i32> @test_urem_odd_allones_eq(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_allones_eq(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_allones_eq: ; CHECK-LABEL: test_urem_odd_allones_eq:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI1_0 ; CHECK-NEXT: adrp x8, .LCPI1_0
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
; CHECK-NEXT: adrp x8, .LCPI1_1 ; CHECK-NEXT: adrp x8, .LCPI1_1
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_1]
; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5> %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
define <4 x i32> @test_urem_odd_allones_ne(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_allones_ne(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_allones_ne: ; CHECK-LABEL: test_urem_odd_allones_ne:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI2_0 ; CHECK-NEXT: adrp x8, .LCPI2_0
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]
; CHECK-NEXT: adrp x8, .LCPI2_1 ; CHECK-NEXT: adrp x8, .LCPI2_1
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_1]
; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5> %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
%cmp = icmp ne <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp ne <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One all-ones divisor in even divisor ; One all-ones divisor in even divisor
define <4 x i32> @test_urem_even_allones_eq(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_even_allones_eq: ; CHECK-LABEL: test_urem_even_allones_eq:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI3_0 ; CHECK-NEXT: adrp x8, .LCPI3_0
; CHECK-NEXT: adrp x9, .LCPI3_2 ; CHECK-NEXT: adrp x9, .LCPI3_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]
; CHECK-NEXT: adrp x8, .LCPI3_1 ; CHECK-NEXT: adrp x8, .LCPI3_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI3_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI3_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_1]
; CHECK-NEXT: adrp x8, .LCPI3_3 ; CHECK-NEXT: adrp x8, .LCPI3_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14> %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
define <4 x i32> @test_urem_even_allones_ne(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_even_allones_ne: ; CHECK-LABEL: test_urem_even_allones_ne:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI4_0 ; CHECK-NEXT: adrp x8, .LCPI4_0
; CHECK-NEXT: adrp x9, .LCPI4_2 ; CHECK-NEXT: adrp x9, .LCPI4_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]
; CHECK-NEXT: adrp x8, .LCPI4_1 ; CHECK-NEXT: adrp x8, .LCPI4_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI4_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI4_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_1]
; CHECK-NEXT: adrp x8, .LCPI4_3 ; CHECK-NEXT: adrp x8, .LCPI4_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI4_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI4_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s ; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14> %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
%cmp = icmp ne <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp ne <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One all-ones divisor in odd+even divisor ; One all-ones divisor in odd+even divisor
define <4 x i32> @test_urem_odd_even_allones_eq(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_even_allones_eq: ; CHECK-LABEL: test_urem_odd_even_allones_eq:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI5_0 ; CHECK-NEXT: adrp x8, .LCPI5_0
; CHECK-NEXT: adrp x9, .LCPI5_2 ; CHECK-NEXT: adrp x9, .LCPI5_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0]
; CHECK-NEXT: adrp x8, .LCPI5_1 ; CHECK-NEXT: adrp x8, .LCPI5_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI5_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI5_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_1]
; CHECK-NEXT: adrp x8, .LCPI5_3 ; CHECK-NEXT: adrp x8, .LCPI5_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI5_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI5_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100> %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
define <4 x i32> @test_urem_odd_even_allones_ne(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_even_allones_ne: ; CHECK-LABEL: test_urem_odd_even_allones_ne:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI6_0 ; CHECK-NEXT: adrp x8, .LCPI6_0
; CHECK-NEXT: adrp x9, .LCPI6_2 ; CHECK-NEXT: adrp x9, .LCPI6_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI6_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI6_0]
; CHECK-NEXT: adrp x8, .LCPI6_1 ; CHECK-NEXT: adrp x8, .LCPI6_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI6_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI6_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI6_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI6_1]
; CHECK-NEXT: adrp x8, .LCPI6_3 ; CHECK-NEXT: adrp x8, .LCPI6_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI6_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI6_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s ; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100> %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
%cmp = icmp ne <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp ne <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; One power-of-two divisor in odd divisor ; One power-of-two divisor in odd divisor
define <4 x i32> @test_urem_odd_poweroftwo(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_poweroftwo: ; CHECK-LABEL: test_urem_odd_poweroftwo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI7_0 ; CHECK-NEXT: adrp x8, .LCPI7_0
; CHECK-NEXT: adrp x9, .LCPI7_2 ; CHECK-NEXT: adrp x9, .LCPI7_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI7_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI7_0]
; CHECK-NEXT: adrp x8, .LCPI7_1 ; CHECK-NEXT: adrp x8, .LCPI7_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI7_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI7_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI7_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI7_1]
; CHECK-NEXT: adrp x8, .LCPI7_3 ; CHECK-NEXT: adrp x8, .LCPI7_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI7_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI7_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 5, i32 16, i32 5> %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 16, i32 5>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One power-of-two divisor in even divisor ; One power-of-two divisor in even divisor
define <4 x i32> @test_urem_even_poweroftwo(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_even_poweroftwo: ; CHECK-LABEL: test_urem_even_poweroftwo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI8_0 ; CHECK-NEXT: adrp x8, .LCPI8_0
; CHECK-NEXT: adrp x9, .LCPI8_2 ; CHECK-NEXT: adrp x9, .LCPI8_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI8_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI8_0]
; CHECK-NEXT: adrp x8, .LCPI8_1 ; CHECK-NEXT: adrp x8, .LCPI8_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI8_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI8_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI8_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI8_1]
; CHECK-NEXT: adrp x8, .LCPI8_3 ; CHECK-NEXT: adrp x8, .LCPI8_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI8_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI8_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 14, i32 14, i32 16, i32 14> %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 16, i32 14>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One power-of-two divisor in odd+even divisor ; One power-of-two divisor in odd+even divisor
define <4 x i32> @test_urem_odd_even_poweroftwo(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_even_poweroftwo: ; CHECK-LABEL: test_urem_odd_even_poweroftwo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI9_0 ; CHECK-NEXT: adrp x8, .LCPI9_0
; CHECK-NEXT: adrp x9, .LCPI9_2 ; CHECK-NEXT: adrp x9, .LCPI9_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI9_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI9_0]
; CHECK-NEXT: adrp x8, .LCPI9_1 ; CHECK-NEXT: adrp x8, .LCPI9_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI9_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI9_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI9_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI9_1]
; CHECK-NEXT: adrp x8, .LCPI9_3 ; CHECK-NEXT: adrp x8, .LCPI9_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI9_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI9_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 14, i32 16, i32 100> %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 16, i32 100>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; One one divisor in odd divisor ; One one divisor in odd divisor
define <4 x i32> @test_urem_odd_one(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_one: ; CHECK-LABEL: test_urem_odd_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #52429 ; CHECK-NEXT: mov w8, #52429
; CHECK-NEXT: movk w8, #52428, lsl #16 ; CHECK-NEXT: movk w8, #52428, lsl #16
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: dup v1.4s, w8 ; CHECK-NEXT: dup v1.4s, w8
; CHECK-NEXT: adrp x8, .LCPI10_0 ; CHECK-NEXT: adrp x8, .LCPI10_0
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI10_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI10_0]
; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 5, i32 1, i32 5> %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 1, i32 5>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One one divisor in even divisor ; One one divisor in even divisor
define <4 x i32> @test_urem_even_one(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_even_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_even_one: ; CHECK-LABEL: test_urem_even_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #28087 ; CHECK-NEXT: mov w8, #28087
; CHECK-NEXT: movk w8, #46811, lsl #16 ; CHECK-NEXT: movk w8, #46811, lsl #16
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: dup v1.4s, w8 ; CHECK-NEXT: dup v1.4s, w8
; CHECK-NEXT: adrp x8, .LCPI11_0 ; CHECK-NEXT: adrp x8, .LCPI11_0
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI11_0] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI11_0]
; CHECK-NEXT: shl v1.4s, v0.4s, #31 ; CHECK-NEXT: shl v1.4s, v0.4s, #31
; CHECK-NEXT: ushr v0.4s, v0.4s, #1 ; CHECK-NEXT: ushr v0.4s, v0.4s, #1
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 14, i32 14, i32 1, i32 14> %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 1, i32 14>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One one divisor in odd+even divisor ; One one divisor in odd+even divisor
define <4 x i32> @test_urem_odd_even_one(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_even_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_even_one: ; CHECK-LABEL: test_urem_odd_even_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI12_0 ; CHECK-NEXT: adrp x8, .LCPI12_0
; CHECK-NEXT: adrp x9, .LCPI12_2 ; CHECK-NEXT: adrp x9, .LCPI12_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI12_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI12_0]
; CHECK-NEXT: adrp x8, .LCPI12_1 ; CHECK-NEXT: adrp x8, .LCPI12_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI12_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI12_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI12_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI12_1]
; CHECK-NEXT: adrp x8, .LCPI12_3 ; CHECK-NEXT: adrp x8, .LCPI12_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI12_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI12_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 14, i32 1, i32 100> %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 1, i32 100>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; One INT_MIN divisor in odd divisor ; One INT_MIN divisor in odd divisor
define <4 x i32> @test_urem_odd_INT_MIN(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_INT_MIN: ; CHECK-LABEL: test_urem_odd_INT_MIN:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI13_0 ; CHECK-NEXT: adrp x8, .LCPI13_0
; CHECK-NEXT: adrp x9, .LCPI13_2 ; CHECK-NEXT: adrp x9, .LCPI13_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI13_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI13_0]
; CHECK-NEXT: adrp x8, .LCPI13_1 ; CHECK-NEXT: adrp x8, .LCPI13_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI13_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI13_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI13_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI13_1]
; CHECK-NEXT: adrp x8, .LCPI13_3 ; CHECK-NEXT: adrp x8, .LCPI13_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 5, i32 2147483648, i32 5> %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 2147483648, i32 5>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One INT_MIN divisor in even divisor ; One INT_MIN divisor in even divisor
define <4 x i32> @test_urem_even_INT_MIN(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_even_INT_MIN: ; CHECK-LABEL: test_urem_even_INT_MIN:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI14_0 ; CHECK-NEXT: adrp x8, .LCPI14_0
; CHECK-NEXT: adrp x9, .LCPI14_2 ; CHECK-NEXT: adrp x9, .LCPI14_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]
; CHECK-NEXT: adrp x8, .LCPI14_1 ; CHECK-NEXT: adrp x8, .LCPI14_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI14_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI14_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
; CHECK-NEXT: adrp x8, .LCPI14_3 ; CHECK-NEXT: adrp x8, .LCPI14_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI14_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI14_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 14, i32 14, i32 2147483648, i32 14> %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 2147483648, i32 14>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One INT_MIN divisor in odd+even divisor ; One INT_MIN divisor in odd+even divisor
define <4 x i32> @test_urem_odd_even_INT_MIN(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_even_INT_MIN: ; CHECK-LABEL: test_urem_odd_even_INT_MIN:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI15_0 ; CHECK-NEXT: adrp x8, .LCPI15_0
; CHECK-NEXT: adrp x9, .LCPI15_2 ; CHECK-NEXT: adrp x9, .LCPI15_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]
; CHECK-NEXT: adrp x8, .LCPI15_1 ; CHECK-NEXT: adrp x8, .LCPI15_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI15_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI15_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
; CHECK-NEXT: adrp x8, .LCPI15_3 ; CHECK-NEXT: adrp x8, .LCPI15_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI15_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI15_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 14, i32 2147483648, i32 100> %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 2147483648, i32 100>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;==============================================================================; ;==============================================================================;
; One all-ones divisor and power-of-two divisor divisor in odd divisor ; One all-ones divisor and power-of-two divisor divisor in odd divisor
define <4 x i32> @test_urem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_allones_and_poweroftwo: ; CHECK-LABEL: test_urem_odd_allones_and_poweroftwo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI16_0 ; CHECK-NEXT: adrp x8, .LCPI16_0
; CHECK-NEXT: adrp x9, .LCPI16_2 ; CHECK-NEXT: adrp x9, .LCPI16_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
; CHECK-NEXT: adrp x8, .LCPI16_1 ; CHECK-NEXT: adrp x8, .LCPI16_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI16_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI16_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
; CHECK-NEXT: adrp x8, .LCPI16_3 ; CHECK-NEXT: adrp x8, .LCPI16_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI16_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI16_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 5> %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 5>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One all-ones divisor and power-of-two divisor divisor in even divisor ; One all-ones divisor and power-of-two divisor divisor in even divisor
define <4 x i32> @test_urem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_even_allones_and_poweroftwo: ; CHECK-LABEL: test_urem_even_allones_and_poweroftwo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI17_0 ; CHECK-NEXT: adrp x8, .LCPI17_0
; CHECK-NEXT: adrp x9, .LCPI17_2 ; CHECK-NEXT: adrp x9, .LCPI17_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_0]
; CHECK-NEXT: adrp x8, .LCPI17_1 ; CHECK-NEXT: adrp x8, .LCPI17_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI17_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI17_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
; CHECK-NEXT: adrp x8, .LCPI17_3 ; CHECK-NEXT: adrp x8, .LCPI17_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI17_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI17_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 14> %urem = urem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 14>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One all-ones divisor and power-of-two divisor divisor in odd+even divisor ; One all-ones divisor and power-of-two divisor divisor in odd+even divisor
define <4 x i32> @test_urem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_even_allones_and_poweroftwo: ; CHECK-LABEL: test_urem_odd_even_allones_and_poweroftwo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI18_0 ; CHECK-NEXT: adrp x8, .LCPI18_0
; CHECK-NEXT: adrp x9, .LCPI18_2 ; CHECK-NEXT: adrp x9, .LCPI18_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI18_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI18_0]
; CHECK-NEXT: adrp x8, .LCPI18_1 ; CHECK-NEXT: adrp x8, .LCPI18_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI18_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI18_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI18_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI18_1]
; CHECK-NEXT: adrp x8, .LCPI18_3 ; CHECK-NEXT: adrp x8, .LCPI18_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI18_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI18_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 100> %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 100>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; One all-ones divisor and one one divisor in odd divisor ; One all-ones divisor and one one divisor in odd divisor
define <4 x i32> @test_urem_odd_allones_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_allones_and_one: ; CHECK-LABEL: test_urem_odd_allones_and_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI19_0 ; CHECK-NEXT: adrp x8, .LCPI19_0
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI19_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI19_0]
; CHECK-NEXT: adrp x8, .LCPI19_1 ; CHECK-NEXT: adrp x8, .LCPI19_1
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI19_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI19_1]
; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 5> %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 5>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One all-ones divisor and one one divisor in even divisor ; One all-ones divisor and one one divisor in even divisor
define <4 x i32> @test_urem_even_allones_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_even_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_even_allones_and_one: ; CHECK-LABEL: test_urem_even_allones_and_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI20_0 ; CHECK-NEXT: adrp x8, .LCPI20_0
; CHECK-NEXT: adrp x9, .LCPI20_2 ; CHECK-NEXT: adrp x9, .LCPI20_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI20_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI20_0]
; CHECK-NEXT: adrp x8, .LCPI20_1 ; CHECK-NEXT: adrp x8, .LCPI20_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI20_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI20_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI20_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI20_1]
; CHECK-NEXT: adrp x8, .LCPI20_3 ; CHECK-NEXT: adrp x8, .LCPI20_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI20_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI20_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 14, i32 4294967295, i32 1, i32 14> %urem = urem <4 x i32> %X, <i32 14, i32 4294967295, i32 1, i32 14>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One all-ones divisor and one one divisor in odd+even divisor ; One all-ones divisor and one one divisor in odd+even divisor
define <4 x i32> @test_urem_odd_even_allones_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_even_allones_and_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_even_allones_and_one: ; CHECK-LABEL: test_urem_odd_even_allones_and_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI21_0 ; CHECK-NEXT: adrp x8, .LCPI21_0
; CHECK-NEXT: adrp x9, .LCPI21_2 ; CHECK-NEXT: adrp x9, .LCPI21_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI21_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI21_0]
; CHECK-NEXT: adrp x8, .LCPI21_1 ; CHECK-NEXT: adrp x8, .LCPI21_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI21_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI21_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI21_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI21_1]
; CHECK-NEXT: adrp x8, .LCPI21_3 ; CHECK-NEXT: adrp x8, .LCPI21_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI21_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI21_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 100> %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 100>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; One power-of-two divisor divisor and one divisor in odd divisor ; One power-of-two divisor divisor and one divisor in odd divisor
define <4 x i32> @test_urem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_poweroftwo_and_one: ; CHECK-LABEL: test_urem_odd_poweroftwo_and_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI22_0 ; CHECK-NEXT: adrp x8, .LCPI22_0
; CHECK-NEXT: adrp x9, .LCPI22_2 ; CHECK-NEXT: adrp x9, .LCPI22_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI22_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI22_0]
; CHECK-NEXT: adrp x8, .LCPI22_1 ; CHECK-NEXT: adrp x8, .LCPI22_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI22_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI22_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI22_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI22_1]
; CHECK-NEXT: adrp x8, .LCPI22_3 ; CHECK-NEXT: adrp x8, .LCPI22_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI22_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI22_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 5> %urem = urem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 5>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One power-of-two divisor divisor and one divisor in even divisor ; One power-of-two divisor divisor and one divisor in even divisor
define <4 x i32> @test_urem_even_poweroftwo_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_even_poweroftwo_and_one: ; CHECK-LABEL: test_urem_even_poweroftwo_and_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI23_0 ; CHECK-NEXT: adrp x8, .LCPI23_0
; CHECK-NEXT: adrp x9, .LCPI23_2 ; CHECK-NEXT: adrp x9, .LCPI23_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI23_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI23_0]
; CHECK-NEXT: adrp x8, .LCPI23_1 ; CHECK-NEXT: adrp x8, .LCPI23_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI23_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI23_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI23_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI23_1]
; CHECK-NEXT: adrp x8, .LCPI23_3 ; CHECK-NEXT: adrp x8, .LCPI23_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI23_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI23_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 14, i32 16, i32 1, i32 14> %urem = urem <4 x i32> %X, <i32 14, i32 16, i32 1, i32 14>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One power-of-two divisor divisor and one divisor in odd+even divisor ; One power-of-two divisor divisor and one divisor in odd+even divisor
define <4 x i32> @test_urem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_even_poweroftwo_and_one: ; CHECK-LABEL: test_urem_odd_even_poweroftwo_and_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI24_0 ; CHECK-NEXT: adrp x8, .LCPI24_0
; CHECK-NEXT: adrp x9, .LCPI24_2 ; CHECK-NEXT: adrp x9, .LCPI24_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI24_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI24_0]
; CHECK-NEXT: adrp x8, .LCPI24_1 ; CHECK-NEXT: adrp x8, .LCPI24_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI24_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI24_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI24_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI24_1]
; CHECK-NEXT: adrp x8, .LCPI24_3 ; CHECK-NEXT: adrp x8, .LCPI24_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI24_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI24_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 100> %urem = urem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 100>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
define <4 x i32> @test_urem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_allones_and_poweroftwo_and_one: ; CHECK-LABEL: test_urem_odd_allones_and_poweroftwo_and_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI25_0 ; CHECK-NEXT: adrp x8, .LCPI25_0
; CHECK-NEXT: adrp x9, .LCPI25_2 ; CHECK-NEXT: adrp x9, .LCPI25_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI25_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI25_0]
; CHECK-NEXT: adrp x8, .LCPI25_1 ; CHECK-NEXT: adrp x8, .LCPI25_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI25_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI25_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI25_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI25_1]
; CHECK-NEXT: adrp x8, .LCPI25_3 ; CHECK-NEXT: adrp x8, .LCPI25_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI25_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI25_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 1> %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 1>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
define <4 x i32> @test_urem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_even_allones_and_poweroftwo_and_one: ; CHECK-LABEL: test_urem_even_allones_and_poweroftwo_and_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI26_0 ; CHECK-NEXT: adrp x8, .LCPI26_0
; CHECK-NEXT: adrp x9, .LCPI26_2 ; CHECK-NEXT: adrp x9, .LCPI26_2
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI26_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI26_0]
; CHECK-NEXT: adrp x8, .LCPI26_1 ; CHECK-NEXT: adrp x8, .LCPI26_1
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI26_2] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI26_2]
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI26_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI26_1]
; CHECK-NEXT: adrp x8, .LCPI26_3 ; CHECK-NEXT: adrp x8, .LCPI26_3
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s ; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI26_3] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI26_3]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 1> %urem = urem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 1>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }

llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
; Odd divisor ; Odd divisor
define <4 x i32> @test_urem_odd_25(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_25(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_25: ; CHECK-LABEL: test_urem_odd_25:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #23593 ; CHECK-NEXT: mov w8, #23593
; CHECK-NEXT: movk w8, #49807, lsl #16 ; CHECK-NEXT: movk w8, #49807, lsl #16
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: dup v1.4s, w8 ; CHECK-NEXT: dup v1.4s, w8
; CHECK-NEXT: mov w8, #28835 ; CHECK-NEXT: mov w8, #28835
; CHECK-NEXT: movk w8, #2621, lsl #16 ; CHECK-NEXT: movk w8, #2621, lsl #16
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: dup v1.4s, w8 ; CHECK-NEXT: dup v1.4s, w8
; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 25, i32 25, i32 25, i32 25> %urem = urem <4 x i32> %X, <i32 25, i32 25, i32 25, i32 25>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; Even divisors ; Even divisors
define <4 x i32> @test_urem_even_100(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_even_100(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_even_100: ; CHECK-LABEL: test_urem_even_100:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #23593 ; CHECK-NEXT: mov w8, #23593
; CHECK-NEXT: movk w8, #49807, lsl #16 ; CHECK-NEXT: movk w8, #49807, lsl #16
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: dup v1.4s, w8 ; CHECK-NEXT: dup v1.4s, w8
; CHECK-NEXT: mov w8, #23592 ; CHECK-NEXT: mov w8, #23592
; CHECK-NEXT: movk w8, #655, lsl #16 ; CHECK-NEXT: movk w8, #655, lsl #16
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: dup v2.4s, w8 ; CHECK-NEXT: dup v2.4s, w8
; CHECK-NEXT: shl v1.4s, v0.4s, #30 ; CHECK-NEXT: shl v1.4s, v0.4s, #30
; CHECK-NEXT: ushr v0.4s, v0.4s, #2 ; CHECK-NEXT: ushr v0.4s, v0.4s, #2
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 100, i32 100, i32 100, i32 100> %urem = urem <4 x i32> %X, <i32 100, i32 100, i32 100, i32 100>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; Negative divisors should be negated, and thus this is still splat vectors. ; Negative divisors should be negated, and thus this is still splat vectors.
; Odd divisor ; Odd divisor
define <4 x i32> @test_urem_odd_neg25(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_odd_neg25(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_odd_neg25: ; CHECK-LABEL: test_urem_odd_neg25:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI2_0 ; CHECK-NEXT: adrp x8, .LCPI2_0
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]
; CHECK-NEXT: adrp x8, .LCPI2_1 ; CHECK-NEXT: adrp x8, .LCPI2_1
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_1]
; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 25, i32 -25, i32 -25, i32 25> %urem = urem <4 x i32> %X, <i32 25, i32 -25, i32 -25, i32 25>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; Even divisors ; Even divisors
define <4 x i32> @test_urem_even_neg100(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_even_neg100(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_even_neg100: ; CHECK-LABEL: test_urem_even_neg100:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI3_0 ; CHECK-NEXT: adrp x8, .LCPI3_0
; CHECK-NEXT: movi v3.4s, #1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]
; CHECK-NEXT: adrp x8, .LCPI3_1 ; CHECK-NEXT: adrp x8, .LCPI3_1
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_1] ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_1]
; CHECK-NEXT: shl v1.4s, v0.4s, #30 ; CHECK-NEXT: shl v1.4s, v0.4s, #30
; CHECK-NEXT: ushr v0.4s, v0.4s, #2 ; CHECK-NEXT: ushr v0.4s, v0.4s, #2
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 -100, i32 100, i32 -100, i32 100> %urem = urem <4 x i32> %X, <i32 -100, i32 100, i32 -100, i32 100>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; We can lower remainder of division by powers of two much better elsewhere. ; We can lower remainder of division by powers of two much better elsewhere.
define <4 x i32> @test_urem_pow2(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_pow2(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_pow2: ; CHECK-LABEL: test_urem_pow2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #15 ; CHECK-NEXT: movi v1.4s, #15
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 16, i32 16, i32 16, i32 16> %urem = urem <4 x i32> %X, <i32 16, i32 16, i32 16, i32 16>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; We could lower remainder of division by INT_MIN much better elsewhere. ; We could lower remainder of division by INT_MIN much better elsewhere.
define <4 x i32> @test_urem_int_min(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_int_min(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_int_min: ; CHECK-LABEL: test_urem_int_min:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: bic v0.4s, #128, lsl #24 ; CHECK-NEXT: bic v0.4s, #128, lsl #24
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648> %urem = urem <4 x i32> %X, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; We could lower remainder of division by all-ones much better elsewhere. ; We could lower remainder of division by all-ones much better elsewhere.
define <4 x i32> @test_urem_allones(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_allones(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_allones: ; CHECK-LABEL: test_urem_allones:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: neg v0.4s, v0.4s ; CHECK-NEXT: neg v0.4s, v0.4s
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s ; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295> %urem = urem <4 x i32> %X, <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }

llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; CHECK-LABEL: t3_wide: ; CHECK-LABEL: t3_wide:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-6148914691236517206 ; CHECK-NEXT: mov x8, #-6148914691236517206
; CHECK-NEXT: fmov x9, d0 ; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: movk x8, #43691 ; CHECK-NEXT: movk x8, #43691
; CHECK-NEXT: mov x10, v0.d[1] ; CHECK-NEXT: mov x10, v0.d[1]
; CHECK-NEXT: mul x9, x9, x8 ; CHECK-NEXT: mul x9, x9, x8
; CHECK-NEXT: mul x8, x10, x8 ; CHECK-NEXT: mul x8, x10, x8
; CHECK-NEXT: adrp x10, .LCPI4_0
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: adrp x9, .LCPI4_0 ; CHECK-NEXT: ldr q1, [x10, :lo12:.LCPI4_0]
; CHECK-NEXT: mov v0.d[1], x8 ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI4_0]
; CHECK-NEXT: cmhs v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhs v0.2d, v1.2d, v0.2d
; CHECK-NEXT: movi d1, #0xffffffff00000000 ; CHECK-NEXT: movi d1, #0xffffffff00000000
; CHECK-NEXT: xtn v0.2s, v0.2d ; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <2 x i64> %X, <i64 3, i64 1> %urem = urem <2 x i64> %X, <i64 3, i64 1>
%cmp = icmp eq <2 x i64> %urem, <i64 0, i64 42> %cmp = icmp eq <2 x i64> %urem, <i64 0, i64 42>
ret <2 x i1> %cmp ret <2 x i1> %cmp
} }

llvm/test/CodeGen/AArch64/urem-vector-lkk.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) { define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
; CHECK-LABEL: fold_urem_vec_1: ; CHECK-LABEL: fold_urem_vec_1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #8969
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.h[0] ; CHECK-NEXT: umov w9, v0.h[0]
; CHECK-NEXT: mov w9, #8969 ; CHECK-NEXT: movk w8, #22765, lsl #16
; CHECK-NEXT: movk w9, #22765, lsl #16
; CHECK-NEXT: umov w10, v0.h[1] ; CHECK-NEXT: umov w10, v0.h[1]
; CHECK-NEXT: mov w12, #16913 ; CHECK-NEXT: mov w11, #16913
; CHECK-NEXT: mov w13, #95
; CHECK-NEXT: movk w12, #8456, lsl #16
; CHECK-NEXT: umull x9, w8, w9
; CHECK-NEXT: ubfx w14, w10, #2, #14
; CHECK-NEXT: lsr x9, x9, #32
; CHECK-NEXT: sub w11, w8, w9
; CHECK-NEXT: umull x12, w14, w12
; CHECK-NEXT: add w9, w9, w11, lsr #1
; CHECK-NEXT: umov w11, v0.h[2]
; CHECK-NEXT: lsr w9, w9, #6
; CHECK-NEXT: lsr x12, x12, #34
; CHECK-NEXT: msub w8, w9, w13, w8
; CHECK-NEXT: mov w9, #33437
; CHECK-NEXT: movk w9, #21399, lsl #16
; CHECK-NEXT: mov w13, #124 ; CHECK-NEXT: mov w13, #124
; CHECK-NEXT: umull x9, w11, w9 ; CHECK-NEXT: umull x8, w9, w8
; CHECK-NEXT: msub w10, w12, w13, w10 ; CHECK-NEXT: movk w11, #8456, lsl #16
; CHECK-NEXT: umov w12, v0.h[3] ; CHECK-NEXT: ubfx w12, w10, #2, #14
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: mov w14, #95
; CHECK-NEXT: lsr x8, x8, #32
; CHECK-NEXT: umull x11, w12, w11
; CHECK-NEXT: sub w12, w9, w8
; CHECK-NEXT: lsr x11, x11, #34
; CHECK-NEXT: add w8, w8, w12, lsr #1
; CHECK-NEXT: mov w12, #33437
; CHECK-NEXT: lsr w8, w8, #6
; CHECK-NEXT: movk w12, #21399, lsl #16
; CHECK-NEXT: msub w10, w11, w13, w10
; CHECK-NEXT: umov w11, v0.h[2]
; CHECK-NEXT: msub w8, w8, w14, w9
; CHECK-NEXT: mov w13, #2287 ; CHECK-NEXT: mov w13, #2287
; CHECK-NEXT: lsr x8, x9, #37 ; CHECK-NEXT: mov w14, #98
; CHECK-NEXT: mov w9, #98 ; CHECK-NEXT: umull x9, w11, w12
; CHECK-NEXT: umov w12, v0.h[3]
; CHECK-NEXT: movk w13, #16727, lsl #16 ; CHECK-NEXT: movk w13, #16727, lsl #16
; CHECK-NEXT: msub w8, w8, w9, w11 ; CHECK-NEXT: lsr x9, x9, #37
; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: umull x13, w12, w13
; CHECK-NEXT: msub w9, w9, w14, w11
; CHECK-NEXT: mov w11, #1003
; CHECK-NEXT: lsr x8, x13, #40
; CHECK-NEXT: mov v0.h[1], w10 ; CHECK-NEXT: mov v0.h[1], w10
; CHECK-NEXT: umull x9, w12, w13 ; CHECK-NEXT: msub w8, w8, w11, w12
; CHECK-NEXT: mov w10, #1003 ; CHECK-NEXT: mov v0.h[2], w9
; CHECK-NEXT: lsr x9, x9, #40
; CHECK-NEXT: mov v0.h[2], w8
; CHECK-NEXT: msub w8, w9, w10, w12
; CHECK-NEXT: mov v0.h[3], w8 ; CHECK-NEXT: mov v0.h[3], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003> %1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003>
ret <4 x i16> %1 ret <4 x i16> %1
} }
define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) { define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; CHECK-LABEL: fold_urem_vec_2: ; CHECK-LABEL: fold_urem_vec_2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w10, v0.h[0]
; CHECK-NEXT: mov w8, #8969 ; CHECK-NEXT: mov w8, #8969
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w9, v0.h[1] ; CHECK-NEXT: umov w9, v0.h[1]
; CHECK-NEXT: movk w8, #22765, lsl #16 ; CHECK-NEXT: movk w8, #22765, lsl #16
; CHECK-NEXT: umov w10, v0.h[0]
; CHECK-NEXT: umov w15, v0.h[2] ; CHECK-NEXT: umov w15, v0.h[2]
; CHECK-NEXT: umov w16, v0.h[3] ; CHECK-NEXT: mov w16, #95
; CHECK-NEXT: umull x12, w10, w8
; CHECK-NEXT: umull x11, w9, w8 ; CHECK-NEXT: umull x11, w9, w8
; CHECK-NEXT: lsr x12, x12, #32 ; CHECK-NEXT: umull x12, w10, w8
; CHECK-NEXT: lsr x11, x11, #32 ; CHECK-NEXT: lsr x11, x11, #32
; CHECK-NEXT: sub w14, w10, w12 ; CHECK-NEXT: lsr x12, x12, #32
; CHECK-NEXT: sub w13, w9, w11 ; CHECK-NEXT: sub w13, w9, w11
; CHECK-NEXT: add w12, w12, w14, lsr #1 ; CHECK-NEXT: sub w14, w10, w12
; CHECK-NEXT: umull x14, w15, w8
; CHECK-NEXT: add w11, w11, w13, lsr #1 ; CHECK-NEXT: add w11, w11, w13, lsr #1
; CHECK-NEXT: mov w13, #95 ; CHECK-NEXT: umull x13, w15, w8
; CHECK-NEXT: add w12, w12, w14, lsr #1
; CHECK-NEXT: umov w14, v0.h[3]
; CHECK-NEXT: lsr w12, w12, #6 ; CHECK-NEXT: lsr w12, w12, #6
; CHECK-NEXT: lsr x13, x13, #32
; CHECK-NEXT: umull x8, w14, w8
; CHECK-NEXT: lsr w11, w11, #6 ; CHECK-NEXT: lsr w11, w11, #6
; CHECK-NEXT: umull x8, w16, w8 ; CHECK-NEXT: msub w10, w12, w16, w10
; CHECK-NEXT: msub w10, w12, w13, w10 ; CHECK-NEXT: sub w12, w15, w13
; CHECK-NEXT: lsr x12, x14, #32
; CHECK-NEXT: msub w9, w11, w13, w9
; CHECK-NEXT: sub w11, w15, w12
; CHECK-NEXT: lsr x8, x8, #32 ; CHECK-NEXT: lsr x8, x8, #32
; CHECK-NEXT: msub w9, w11, w16, w9
; CHECK-NEXT: add w12, w13, w12, lsr #1
; CHECK-NEXT: sub w13, w14, w8
; CHECK-NEXT: lsr w11, w12, #6
; CHECK-NEXT: fmov s0, w10 ; CHECK-NEXT: fmov s0, w10
; CHECK-NEXT: add w10, w12, w11, lsr #1 ; CHECK-NEXT: add w8, w8, w13, lsr #1
; CHECK-NEXT: lsr w10, w10, #6 ; CHECK-NEXT: msub w10, w11, w16, w15
; CHECK-NEXT: sub w11, w16, w8
; CHECK-NEXT: mov v0.h[1], w9
; CHECK-NEXT: msub w9, w10, w13, w15
; CHECK-NEXT: add w8, w8, w11, lsr #1
; CHECK-NEXT: lsr w8, w8, #6 ; CHECK-NEXT: lsr w8, w8, #6
; CHECK-NEXT: mov v0.h[2], w9 ; CHECK-NEXT: mov v0.h[1], w9
; CHECK-NEXT: msub w8, w8, w13, w16 ; CHECK-NEXT: msub w8, w8, w16, w14
; CHECK-NEXT: mov v0.h[2], w10
; CHECK-NEXT: mov v0.h[3], w8 ; CHECK-NEXT: mov v0.h[3], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if we can combine urem with udiv. ; Don't fold if we can combine urem with udiv.
define <4 x i16> @combine_urem_udiv(<4 x i16> %x) { define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
; CHECK-LABEL: combine_urem_udiv: ; CHECK-LABEL: combine_urem_udiv:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #8969
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w9, v0.h[0] ; CHECK-NEXT: umov w9, v0.h[0]
; CHECK-NEXT: mov w8, #8969
; CHECK-NEXT: movk w8, #22765, lsl #16 ; CHECK-NEXT: movk w8, #22765, lsl #16
; CHECK-NEXT: umov w10, v0.h[1] ; CHECK-NEXT: umov w10, v0.h[1]
; CHECK-NEXT: umov w11, v0.h[2] ; CHECK-NEXT: umov w13, v0.h[2]
; CHECK-NEXT: mov w15, #95 ; CHECK-NEXT: mov w12, #95
; CHECK-NEXT: umov w13, v0.h[3] ; CHECK-NEXT: umull x11, w9, w8
; CHECK-NEXT: umull x12, w9, w8 ; CHECK-NEXT: umov w15, v0.h[3]
; CHECK-NEXT: umull x14, w10, w8 ; CHECK-NEXT: umull x14, w10, w8
; CHECK-NEXT: lsr x12, x12, #32 ; CHECK-NEXT: lsr x11, x11, #32
; CHECK-NEXT: umull x17, w11, w8 ; CHECK-NEXT: umull x17, w13, w8
; CHECK-NEXT: sub w16, w9, w12 ; CHECK-NEXT: sub w16, w9, w11
; CHECK-NEXT: lsr x14, x14, #32 ; CHECK-NEXT: lsr x14, x14, #32
; CHECK-NEXT: umull x8, w15, w8
; CHECK-NEXT: lsr x17, x17, #32 ; CHECK-NEXT: lsr x17, x17, #32
; CHECK-NEXT: umull x8, w13, w8 ; CHECK-NEXT: add w11, w11, w16, lsr #1
; CHECK-NEXT: add w12, w12, w16, lsr #1
; CHECK-NEXT: sub w16, w10, w14 ; CHECK-NEXT: sub w16, w10, w14
; CHECK-NEXT: lsr w12, w12, #6 ; CHECK-NEXT: lsr w11, w11, #6
; CHECK-NEXT: lsr x8, x8, #32 ; CHECK-NEXT: lsr x8, x8, #32
; CHECK-NEXT: add w14, w14, w16, lsr #1 ; CHECK-NEXT: add w14, w14, w16, lsr #1
; CHECK-NEXT: sub w16, w11, w17 ; CHECK-NEXT: sub w16, w13, w17
; CHECK-NEXT: msub w9, w12, w15, w9 ; CHECK-NEXT: msub w9, w11, w12, w9
; CHECK-NEXT: lsr w14, w14, #6 ; CHECK-NEXT: lsr w14, w14, #6
; CHECK-NEXT: add w16, w17, w16, lsr #1 ; CHECK-NEXT: add w16, w17, w16, lsr #1
; CHECK-NEXT: fmov s1, w12 ; CHECK-NEXT: sub w17, w15, w8
; CHECK-NEXT: msub w10, w14, w15, w10 ; CHECK-NEXT: msub w10, w14, w12, w10
; CHECK-NEXT: sub w17, w13, w8 ; CHECK-NEXT: fmov s1, w11
; CHECK-NEXT: add w8, w8, w17, lsr #1
; CHECK-NEXT: fmov s0, w9 ; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: lsr w9, w16, #6 ; CHECK-NEXT: lsr w9, w16, #6
; CHECK-NEXT: mov v1.h[1], w14
; CHECK-NEXT: add w8, w8, w17, lsr #1
; CHECK-NEXT: msub w11, w9, w15, w11
; CHECK-NEXT: lsr w8, w8, #6 ; CHECK-NEXT: lsr w8, w8, #6
; CHECK-NEXT: mov v1.h[1], w14
; CHECK-NEXT: msub w11, w9, w12, w13
; CHECK-NEXT: mov v0.h[1], w10 ; CHECK-NEXT: mov v0.h[1], w10
; CHECK-NEXT: msub w10, w8, w15, w13 ; CHECK-NEXT: msub w10, w8, w12, w15
; CHECK-NEXT: mov v1.h[2], w9 ; CHECK-NEXT: mov v1.h[2], w9
; CHECK-NEXT: mov v0.h[2], w11 ; CHECK-NEXT: mov v0.h[2], w11
; CHECK-NEXT: mov v1.h[3], w8 ; CHECK-NEXT: mov v1.h[3], w8
; CHECK-NEXT: mov v0.h[3], w10 ; CHECK-NEXT: mov v0.h[3], w10
; CHECK-NEXT: add v0.4h, v0.4h, v1.4h ; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
%2 = udiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %2 = udiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
%3 = add <4 x i16> %1, %2 %3 = add <4 x i16> %1, %2
ret <4 x i16> %3 ret <4 x i16> %3
} }
; Don't fold for divisors that are a power of two. ; Don't fold for divisors that are a power of two.
define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) { define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
; CHECK-LABEL: dont_fold_urem_power_of_two: ; CHECK-LABEL: dont_fold_urem_power_of_two:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #8969
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w10, v0.h[0]
; CHECK-NEXT: umov w9, v0.h[3] ; CHECK-NEXT: umov w9, v0.h[3]
; CHECK-NEXT: mov w8, #8969
; CHECK-NEXT: umov w11, v0.h[1]
; CHECK-NEXT: movk w8, #22765, lsl #16 ; CHECK-NEXT: movk w8, #22765, lsl #16
; CHECK-NEXT: and w10, w10, #0x3f ; CHECK-NEXT: umov w10, v0.h[0]
; CHECK-NEXT: umov w12, v0.h[1]
; CHECK-NEXT: umull x8, w9, w8 ; CHECK-NEXT: umull x8, w9, w8
; CHECK-NEXT: and w11, w11, #0x1f ; CHECK-NEXT: and w10, w10, #0x3f
; CHECK-NEXT: lsr x8, x8, #32 ; CHECK-NEXT: lsr x8, x8, #32
; CHECK-NEXT: sub w11, w9, w8
; CHECK-NEXT: fmov s1, w10 ; CHECK-NEXT: fmov s1, w10
; CHECK-NEXT: umov w10, v0.h[2] ; CHECK-NEXT: and w10, w12, #0x1f
; CHECK-NEXT: sub w12, w9, w8 ; CHECK-NEXT: mov w12, #95
; CHECK-NEXT: mov v1.h[1], w11 ; CHECK-NEXT: add w8, w8, w11, lsr #1
; CHECK-NEXT: add w8, w8, w12, lsr #1 ; CHECK-NEXT: umov w11, v0.h[2]
; CHECK-NEXT: and w10, w10, #0x7
; CHECK-NEXT: lsr w8, w8, #6 ; CHECK-NEXT: lsr w8, w8, #6
; CHECK-NEXT: mov w11, #95 ; CHECK-NEXT: and w11, w11, #0x7
; CHECK-NEXT: msub w8, w8, w11, w9 ; CHECK-NEXT: mov v1.h[1], w10
; CHECK-NEXT: mov v1.h[2], w10 ; CHECK-NEXT: msub w8, w8, w12, w9
; CHECK-NEXT: mov v1.h[2], w11
; CHECK-NEXT: mov v1.h[3], w8 ; CHECK-NEXT: mov v1.h[3], w8
; CHECK-NEXT: fmov d0, d1 ; CHECK-NEXT: fmov d0, d1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95> %1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is one. ; Don't fold if the divisor is one.
define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) { define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; CHECK-LABEL: dont_fold_srem_one: ; CHECK-LABEL: dont_fold_srem_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w9, v0.h[1] ; CHECK-NEXT: umov w9, v0.h[1]
; CHECK-NEXT: mov w8, #30865 ; CHECK-NEXT: mov w8, #30865
; CHECK-NEXT: movk w8, #51306, lsl #16 ; CHECK-NEXT: movk w8, #51306, lsl #16
; CHECK-NEXT: umov w11, v0.h[2] ; CHECK-NEXT: umov w11, v0.h[2]
; CHECK-NEXT: ubfx w10, w9, #1, #15
; CHECK-NEXT: mov w12, #654 ; CHECK-NEXT: mov w12, #654
; CHECK-NEXT: movi d1, #0000000000000000
; CHECK-NEXT: mov w13, #47143 ; CHECK-NEXT: mov w13, #47143
; CHECK-NEXT: ubfx w10, w9, #1, #15
; CHECK-NEXT: movk w13, #24749, lsl #16
; CHECK-NEXT: umull x8, w10, w8 ; CHECK-NEXT: umull x8, w10, w8
; CHECK-NEXT: mov w10, #17097 ; CHECK-NEXT: mov w10, #17097
; CHECK-NEXT: movk w10, #45590, lsl #16 ; CHECK-NEXT: movk w10, #45590, lsl #16
; CHECK-NEXT: movk w13, #24749, lsl #16
; CHECK-NEXT: lsr x8, x8, #40 ; CHECK-NEXT: lsr x8, x8, #40
; CHECK-NEXT: umull x10, w11, w10 ; CHECK-NEXT: umull x10, w11, w10
; CHECK-NEXT: msub w8, w8, w12, w9 ; CHECK-NEXT: msub w8, w8, w12, w9
; CHECK-NEXT: umov w9, v0.h[3] ; CHECK-NEXT: umov w9, v0.h[3]
; CHECK-NEXT: lsr x10, x10, #36
; CHECK-NEXT: mov w12, #23 ; CHECK-NEXT: mov w12, #23
; CHECK-NEXT: lsr x10, x10, #36
; CHECK-NEXT: umull x13, w9, w13
; CHECK-NEXT: movi d0, #0000000000000000
; CHECK-NEXT: msub w10, w10, w12, w11 ; CHECK-NEXT: msub w10, w10, w12, w11
; CHECK-NEXT: mov w11, #5423 ; CHECK-NEXT: mov w12, #5423
; CHECK-NEXT: mov v1.h[1], w8 ; CHECK-NEXT: lsr x11, x13, #43
; CHECK-NEXT: umull x8, w9, w13 ; CHECK-NEXT: mov v0.h[1], w8
; CHECK-NEXT: lsr x8, x8, #43 ; CHECK-NEXT: msub w8, w11, w12, w9
; CHECK-NEXT: mov v1.h[2], w10 ; CHECK-NEXT: mov v0.h[2], w10
; CHECK-NEXT: msub w8, w8, w11, w9 ; CHECK-NEXT: mov v0.h[3], w8
; CHECK-NEXT: mov v1.h[3], w8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: fmov d0, d1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423> %1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is 2^16. ; Don't fold if the divisor is 2^16.
define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) { define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; CHECK-LABEL: dont_fold_urem_i16_smax: ; CHECK-LABEL: dont_fold_urem_i16_smax:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = urem <4 x i16> %x, <i16 1, i16 65536, i16 23, i16 5423> %1 = urem <4 x i16> %x, <i16 1, i16 65536, i16 23, i16 5423>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold i64 urem. ; Don't fold i64 urem.
define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) { define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
; CHECK-LABEL: dont_fold_urem_i64: ; CHECK-LABEL: dont_fold_urem_i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #17097 ; CHECK-NEXT: mov x8, #17097
; CHECK-NEXT: fmov x9, d1 ; CHECK-NEXT: mov x11, #21445
; CHECK-NEXT: movk x8, #45590, lsl #16 ; CHECK-NEXT: movk x8, #45590, lsl #16
; CHECK-NEXT: mov x13, #21445 ; CHECK-NEXT: fmov x9, d1
; CHECK-NEXT: movk x8, #34192, lsl #32 ; CHECK-NEXT: movk x8, #34192, lsl #32
; CHECK-NEXT: movk x13, #1603, lsl #16
; CHECK-NEXT: movk x8, #25644, lsl #48
; CHECK-NEXT: movk x13, #15432, lsl #32
; CHECK-NEXT: mov x10, v0.d[1] ; CHECK-NEXT: mov x10, v0.d[1]
; CHECK-NEXT: movk x13, #25653, lsl #48 ; CHECK-NEXT: movk x11, #1603, lsl #16
; CHECK-NEXT: movk x8, #25644, lsl #48
; CHECK-NEXT: movk x11, #15432, lsl #32
; CHECK-NEXT: lsr x12, x10, #1
; CHECK-NEXT: movk x11, #25653, lsl #48
; CHECK-NEXT: umulh x8, x9, x8 ; CHECK-NEXT: umulh x8, x9, x8
; CHECK-NEXT: mov x11, v1.d[1] ; CHECK-NEXT: mov x14, v1.d[1]
; CHECK-NEXT: sub x12, x9, x8 ; CHECK-NEXT: umulh x11, x12, x11
; CHECK-NEXT: lsr x14, x10, #1
; CHECK-NEXT: add x8, x8, x12, lsr #1
; CHECK-NEXT: mov x12, #12109 ; CHECK-NEXT: mov x12, #12109
; CHECK-NEXT: sub x13, x9, x8
; CHECK-NEXT: movk x12, #52170, lsl #16 ; CHECK-NEXT: movk x12, #52170, lsl #16
; CHECK-NEXT: umulh x13, x14, x13
; CHECK-NEXT: movk x12, #28749, lsl #32 ; CHECK-NEXT: movk x12, #28749, lsl #32
; CHECK-NEXT: mov w14, #23 ; CHECK-NEXT: lsr x11, x11, #7
; CHECK-NEXT: movk x12, #49499, lsl #48 ; CHECK-NEXT: movk x12, #49499, lsl #48
; CHECK-NEXT: add x8, x8, x13, lsr #1
; CHECK-NEXT: mov w13, #23
; CHECK-NEXT: lsr x8, x8, #4 ; CHECK-NEXT: lsr x8, x8, #4
; CHECK-NEXT: lsr x13, x13, #7 ; CHECK-NEXT: umulh x12, x14, x12
; CHECK-NEXT: umulh x12, x11, x12 ; CHECK-NEXT: msub x8, x8, x13, x9
; CHECK-NEXT: msub x8, x8, x14, x9 ; CHECK-NEXT: mov w13, #654
; CHECK-NEXT: mov w9, #5423 ; CHECK-NEXT: lsr x9, x12, #12
; CHECK-NEXT: lsr x12, x12, #12 ; CHECK-NEXT: mov w12, #5423
; CHECK-NEXT: mov w14, #654 ; CHECK-NEXT: msub x10, x11, x13, x10
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: msub x9, x9, x12, x14
; CHECK-NEXT: msub x9, x12, x9, x11
; CHECK-NEXT: msub x10, x13, x14, x10
; CHECK-NEXT: fmov d1, x8 ; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: mov v1.d[1], x9 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[1], x10 ; CHECK-NEXT: mov v0.d[1], x10
; CHECK-NEXT: mov v1.d[1], x9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423> %1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1 ret <4 x i64> %1
} }

llvm/test/CodeGen/AArch64/usub_sat_vec.ll

Show First 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ldrb w9, [x0] ; CHECK-NEXT: ldrb w9, [x0]
; CHECK-NEXT: ldrb w10, [x1, #1] ; CHECK-NEXT: ldrb w10, [x1, #1]
; CHECK-NEXT: fmov s1, w8 ; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: fmov s0, w9 ; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: ldrb w9, [x0, #1] ; CHECK-NEXT: ldrb w9, [x0, #1]
; CHECK-NEXT: mov v1.s[1], w10 ; CHECK-NEXT: mov v1.s[1], w10
; CHECK-NEXT: mov v0.s[1], w9 ; CHECK-NEXT: mov v0.s[1], w9
; CHECK-NEXT: uqsub v0.2s, v0.2s, v1.2s ; CHECK-NEXT: uqsub v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: mov w9, v0.s[1]
; CHECK-NEXT: strb w9, [x2] ; CHECK-NEXT: strb w9, [x2, #1]
; CHECK-NEXT: strb w8, [x2, #1] ; CHECK-NEXT: strb w8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i8>, <2 x i8>* %px %x = load <2 x i8>, <2 x i8>* %px
%y = load <2 x i8>, <2 x i8>* %py %y = load <2 x i8>, <2 x i8>* %py
%z = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %x, <2 x i8> %y) %z = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
store <2 x i8> %z, <2 x i8>* %pz store <2 x i8> %z, <2 x i8>* %pz
ret void ret void
} }
Show All 19 Lines
; CHECK-NEXT: ldrh w9, [x0] ; CHECK-NEXT: ldrh w9, [x0]
; CHECK-NEXT: ldrh w10, [x1, #2] ; CHECK-NEXT: ldrh w10, [x1, #2]
; CHECK-NEXT: fmov s1, w8 ; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: fmov s0, w9 ; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: ldrh w9, [x0, #2] ; CHECK-NEXT: ldrh w9, [x0, #2]
; CHECK-NEXT: mov v1.s[1], w10 ; CHECK-NEXT: mov v1.s[1], w10
; CHECK-NEXT: mov v0.s[1], w9 ; CHECK-NEXT: mov v0.s[1], w9
; CHECK-NEXT: uqsub v0.2s, v0.2s, v1.2s ; CHECK-NEXT: uqsub v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: mov w9, v0.s[1]
; CHECK-NEXT: strh w9, [x2] ; CHECK-NEXT: strh w9, [x2, #2]
; CHECK-NEXT: strh w8, [x2, #2] ; CHECK-NEXT: strh w8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i16>, <2 x i16>* %px %x = load <2 x i16>, <2 x i16>* %px
%y = load <2 x i16>, <2 x i16>* %py %y = load <2 x i16>, <2 x i16>* %py
%z = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %x, <2 x i16> %y) %z = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
store <2 x i16> %z, <2 x i16>* %pz store <2 x i16> %z, <2 x i16>* %pz
ret void ret void
} }
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llvm/test/CodeGen/AArch64/vec-extract-branch.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -verify-machineinstrs | FileCheck %s
define i32 @vec_extract_branch(<2 x double> %x, i32 %y) { define i32 @vec_extract_branch(<2 x double> %x, i32 %y) {
; CHECK-LABEL: vec_extract_branch: ; CHECK-LABEL: vec_extract_branch:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcmgt v0.2d, v0.2d, #0.0 ; CHECK-NEXT: fcmgt v0.2d, v0.2d, #0.0
; CHECK-NEXT: xtn v0.2s, v0.2d ; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: and w8, w9, w8 ; CHECK-NEXT: and w8, w9, w8
; CHECK-NEXT: tbz w8, #0, .LBB0_2 ; CHECK-NEXT: tbz w8, #0, .LBB0_2
; CHECK-NEXT: // %bb.1: // %true ; CHECK-NEXT: // %bb.1: // %true
; CHECK-NEXT: mov w8, #42 ; CHECK-NEXT: mov w8, #42
; CHECK-NEXT: sdiv w0, w8, w0 ; CHECK-NEXT: sdiv w0, w8, w0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: mov w0, #88 ; CHECK-NEXT: mov w0, #88
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llvm/test/CodeGen/AArch64/vec-libcalls.ll

Show First 20 Lines • Show All 118 Lines • ▼ Show 20 Lines
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov s0, v0.s[2] ; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v1.s[2], v0.s[0] ; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov s0, v0.s[3]
; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
; CHECK-NEXT: mov s0, v0.s[3]
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: mov v1.s[3], v0.s[0] ; CHECK-NEXT: mov v1.s[3], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
▲ Show 20 Lines • Show All 372 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/vec_uaddo.ll

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
store <4 x i32> %val, <4 x i32>* %p2 store <4 x i32> %val, <4 x i32>* %p2
ret <4 x i32> %res ret <4 x i32> %res
} }
define <6 x i32> @uaddo_v6i32(<6 x i32> %a0, <6 x i32> %a1, <6 x i32>* %p2) nounwind { define <6 x i32> @uaddo_v6i32(<6 x i32> %a0, <6 x i32> %a1, <6 x i32>* %p2) nounwind {
; CHECK-LABEL: uaddo_v6i32: ; CHECK-LABEL: uaddo_v6i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fmov s0, w6 ; CHECK-NEXT: fmov s0, w6
; CHECK-NEXT: fmov s1, w0
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: ldr s2, [sp, #16] ; CHECK-NEXT: fmov s2, w0
; CHECK-NEXT: ldr s1, [sp, #16]
; CHECK-NEXT: add x9, sp, #24 ; CHECK-NEXT: add x9, sp, #24
; CHECK-NEXT: add x10, sp, #8
; CHECK-NEXT: mov v0.s[1], w7
; CHECK-NEXT: fmov s3, w4 ; CHECK-NEXT: fmov s3, w4
; CHECK-NEXT: mov v1.s[1], w1 ; CHECK-NEXT: mov v0.s[1], w7
; CHECK-NEXT: ld1 { v2.s }[1], [x9] ; CHECK-NEXT: mov v2.s[1], w1
; CHECK-NEXT: mov v3.s[1], w5
; CHECK-NEXT: ld1 { v0.s }[2], [x8] ; CHECK-NEXT: ld1 { v0.s }[2], [x8]
; CHECK-NEXT: mov v1.s[2], w2 ; CHECK-NEXT: add x8, sp, #8
; CHECK-NEXT: ld1 { v1.s }[1], [x9]
; CHECK-NEXT: mov v2.s[2], w2
; CHECK-NEXT: mov v3.s[1], w5
; CHECK-NEXT: mov v2.s[3], w3
; CHECK-NEXT: ld1 { v0.s }[3], [x8]
; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
; CHECK-NEXT: ldr x8, [sp, #32] ; CHECK-NEXT: ldr x8, [sp, #32]
; CHECK-NEXT: add v2.4s, v3.4s, v2.4s ; CHECK-NEXT: cmhi v3.4s, v3.4s, v1.4s
; CHECK-NEXT: ld1 { v0.s }[3], [x10] ; CHECK-NEXT: add v0.4s, v2.4s, v0.4s
; CHECK-NEXT: mov v1.s[3], w3 ; CHECK-NEXT: str d1, [x8, #16]
; CHECK-NEXT: str d2, [x8, #16]
; CHECK-NEXT: cmhi v3.4s, v3.4s, v2.4s
; CHECK-NEXT: mov w5, v3.s[1]
; CHECK-NEXT: fmov w4, s3 ; CHECK-NEXT: fmov w4, s3
; CHECK-NEXT: add v0.4s, v1.4s, v0.4s ; CHECK-NEXT: cmhi v2.4s, v2.4s, v0.4s
; CHECK-NEXT: cmhi v1.4s, v1.4s, v0.4s ; CHECK-NEXT: mov w5, v3.s[1]
; CHECK-NEXT: str q0, [x8] ; CHECK-NEXT: str q0, [x8]
; CHECK-NEXT: mov w1, v1.s[1] ; CHECK-NEXT: fmov w0, s2
; CHECK-NEXT: mov w2, v1.s[2] ; CHECK-NEXT: mov w1, v2.s[1]
; CHECK-NEXT: mov w3, v1.s[3] ; CHECK-NEXT: mov w2, v2.s[2]
; CHECK-NEXT: fmov w0, s1 ; CHECK-NEXT: mov w3, v2.s[3]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<6 x i32>, <6 x i1>} @llvm.uadd.with.overflow.v6i32(<6 x i32> %a0, <6 x i32> %a1) %t = call {<6 x i32>, <6 x i1>} @llvm.uadd.with.overflow.v6i32(<6 x i32> %a0, <6 x i32> %a1)
%val = extractvalue {<6 x i32>, <6 x i1>} %t, 0 %val = extractvalue {<6 x i32>, <6 x i1>} %t, 0
%obit = extractvalue {<6 x i32>, <6 x i1>} %t, 1 %obit = extractvalue {<6 x i32>, <6 x i1>} %t, 1
%res = sext <6 x i1> %obit to <6 x i32> %res = sext <6 x i1> %obit to <6 x i32>
store <6 x i32> %val, <6 x i32>* %p2 store <6 x i32> %val, <6 x i32>* %p2
ret <6 x i32> %res ret <6 x i32> %res
} }
Show All 22 Lines
; CHECK-NEXT: cmhi v0.16b, v0.16b, v4.16b ; CHECK-NEXT: cmhi v0.16b, v0.16b, v4.16b
; CHECK-NEXT: str q4, [x0] ; CHECK-NEXT: str q4, [x0]
; CHECK-NEXT: zip1 v1.8b, v0.8b, v0.8b ; CHECK-NEXT: zip1 v1.8b, v0.8b, v0.8b
; CHECK-NEXT: zip2 v2.8b, v0.8b, v0.8b ; CHECK-NEXT: zip2 v2.8b, v0.8b, v0.8b
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: ushll v1.4s, v1.4h, #0 ; CHECK-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-NEXT: ushll v2.4s, v2.4h, #0 ; CHECK-NEXT: ushll v2.4s, v2.4h, #0
; CHECK-NEXT: zip1 v3.8b, v0.8b, v0.8b ; CHECK-NEXT: zip1 v3.8b, v0.8b, v0.8b
; CHECK-NEXT: zip2 v5.8b, v0.8b, v0.8b ; CHECK-NEXT: zip2 v0.8b, v0.8b, v0.8b
; CHECK-NEXT: shl v1.4s, v1.4s, #31 ; CHECK-NEXT: shl v1.4s, v1.4s, #31
; CHECK-NEXT: shl v2.4s, v2.4s, #31 ; CHECK-NEXT: shl v2.4s, v2.4s, #31
; CHECK-NEXT: ushll v3.4s, v3.4h, #0
; CHECK-NEXT: ushll v5.4s, v0.4h, #0
; CHECK-NEXT: cmlt v0.4s, v1.4s, #0 ; CHECK-NEXT: cmlt v0.4s, v1.4s, #0
; CHECK-NEXT: cmlt v1.4s, v2.4s, #0 ; CHECK-NEXT: cmlt v1.4s, v2.4s, #0
; CHECK-NEXT: ushll v2.4s, v3.4h, #0 ; CHECK-NEXT: shl v2.4s, v3.4s, #31
; CHECK-NEXT: ushll v3.4s, v5.4h, #0 ; CHECK-NEXT: shl v3.4s, v5.4s, #31
; CHECK-NEXT: shl v2.4s, v2.4s, #31
; CHECK-NEXT: shl v3.4s, v3.4s, #31
; CHECK-NEXT: cmlt v2.4s, v2.4s, #0 ; CHECK-NEXT: cmlt v2.4s, v2.4s, #0
; CHECK-NEXT: cmlt v3.4s, v3.4s, #0 ; CHECK-NEXT: cmlt v3.4s, v3.4s, #0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<16 x i8>, <16 x i1>} @llvm.uadd.with.overflow.v16i8(<16 x i8> %a0, <16 x i8> %a1) %t = call {<16 x i8>, <16 x i1>} @llvm.uadd.with.overflow.v16i8(<16 x i8> %a0, <16 x i8> %a1)
%val = extractvalue {<16 x i8>, <16 x i1>} %t, 0 %val = extractvalue {<16 x i8>, <16 x i1>} %t, 0
%obit = extractvalue {<16 x i8>, <16 x i1>} %t, 1 %obit = extractvalue {<16 x i8>, <16 x i1>} %t, 1
%res = sext <16 x i1> %obit to <16 x i32> %res = sext <16 x i1> %obit to <16 x i32>
store <16 x i8> %val, <16 x i8>* %p2 store <16 x i8> %val, <16 x i8>* %p2
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define <4 x i32> @uaddo_v4i24(<4 x i24> %a0, <4 x i24> %a1, <4 x i24>* %p2) nounwind { define <4 x i32> @uaddo_v4i24(<4 x i24> %a0, <4 x i24> %a1, <4 x i24>* %p2) nounwind {
; CHECK-LABEL: uaddo_v4i24: ; CHECK-LABEL: uaddo_v4i24:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: bic v1.4s, #255, lsl #24 ; CHECK-NEXT: bic v1.4s, #255, lsl #24
; CHECK-NEXT: bic v0.4s, #255, lsl #24 ; CHECK-NEXT: bic v0.4s, #255, lsl #24
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: mov w8, v0.s[3] ; CHECK-NEXT: mov w8, v0.s[3]
; CHECK-NEXT: mov w9, v0.s[2]
; CHECK-NEXT: mov w10, v0.s[1]
; CHECK-NEXT: fmov w11, s0 ; CHECK-NEXT: fmov w11, s0
; CHECK-NEXT: mov v1.16b, v0.16b ; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: bic v1.4s, #255, lsl #24 ; CHECK-NEXT: mov w9, v0.s[2]
; CHECK-NEXT: sturh w8, [x0, #9] ; CHECK-NEXT: sturh w8, [x0, #9]
; CHECK-NEXT: lsr w8, w8, #16 ; CHECK-NEXT: lsr w8, w8, #16
; CHECK-NEXT: cmeq v1.4s, v1.4s, v0.4s ; CHECK-NEXT: mov w10, v0.s[1]
; CHECK-NEXT: strh w9, [x0, #6] ; CHECK-NEXT: strh w9, [x0, #6]
; CHECK-NEXT: sturh w10, [x0, #3] ; CHECK-NEXT: bic v1.4s, #255, lsl #24
; CHECK-NEXT: lsr w9, w9, #16 ; CHECK-NEXT: lsr w9, w9, #16
; CHECK-NEXT: cmeq v1.4s, v1.4s, v0.4s
; CHECK-NEXT: sturh w10, [x0, #3]
; CHECK-NEXT: lsr w10, w10, #16 ; CHECK-NEXT: lsr w10, w10, #16
; CHECK-NEXT: strb w8, [x0, #11] ; CHECK-NEXT: strb w8, [x0, #11]
; CHECK-NEXT: lsr w8, w11, #16 ; CHECK-NEXT: lsr w8, w11, #16
; CHECK-NEXT: strh w11, [x0] ; CHECK-NEXT: strh w11, [x0]
; CHECK-NEXT: mvn v0.16b, v1.16b ; CHECK-NEXT: mvn v0.16b, v1.16b
; CHECK-NEXT: strb w9, [x0, #8] ; CHECK-NEXT: strb w9, [x0, #8]
; CHECK-NEXT: strb w10, [x0, #5] ; CHECK-NEXT: strb w10, [x0, #5]
; CHECK-NEXT: strb w8, [x0, #2] ; CHECK-NEXT: strb w8, [x0, #2]
Show All 11 Lines
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.4h, #1 ; CHECK-NEXT: movi v2.4h, #1
; CHECK-NEXT: and v1.8b, v1.8b, v2.8b ; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b ; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
; CHECK-NEXT: add v0.4h, v0.4h, v1.4h ; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
; CHECK-NEXT: umov w8, v0.h[1] ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: umov w9, v0.h[2] ; CHECK-NEXT: umov w9, v0.h[2]
; CHECK-NEXT: umov w10, v0.h[0] ; CHECK-NEXT: umov w10, v0.h[0]
; CHECK-NEXT: umov w11, v0.h[3]
; CHECK-NEXT: and v1.8b, v0.8b, v2.8b ; CHECK-NEXT: and v1.8b, v0.8b, v2.8b
; CHECK-NEXT: cmeq v0.4h, v1.4h, v0.4h
; CHECK-NEXT: and w8, w8, #0x1 ; CHECK-NEXT: and w8, w8, #0x1
; CHECK-NEXT: and w9, w9, #0x1 ; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: mvn v0.8b, v0.8b ; CHECK-NEXT: cmeq v1.4h, v1.4h, v0.4h
; CHECK-NEXT: sshll v0.4s, v0.4h, #0
; CHECK-NEXT: bfi w10, w8, #1, #1 ; CHECK-NEXT: bfi w10, w8, #1, #1
; CHECK-NEXT: umov w8, v0.h[3]
; CHECK-NEXT: bfi w10, w9, #2, #1 ; CHECK-NEXT: bfi w10, w9, #2, #1
; CHECK-NEXT: bfi w10, w11, #3, #29 ; CHECK-NEXT: mvn v0.8b, v1.8b
; CHECK-NEXT: bfi w10, w8, #3, #29
; CHECK-NEXT: and w8, w10, #0xf ; CHECK-NEXT: and w8, w10, #0xf
; CHECK-NEXT: sshll v0.4s, v0.4h, #0
; CHECK-NEXT: strb w8, [x0] ; CHECK-NEXT: strb w8, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<4 x i1>, <4 x i1>} @llvm.uadd.with.overflow.v4i1(<4 x i1> %a0, <4 x i1> %a1) %t = call {<4 x i1>, <4 x i1>} @llvm.uadd.with.overflow.v4i1(<4 x i1> %a0, <4 x i1> %a1)
%val = extractvalue {<4 x i1>, <4 x i1>} %t, 0 %val = extractvalue {<4 x i1>, <4 x i1>} %t, 0
%obit = extractvalue {<4 x i1>, <4 x i1>} %t, 1 %obit = extractvalue {<4 x i1>, <4 x i1>} %t, 1
%res = sext <4 x i1> %obit to <4 x i32> %res = sext <4 x i1> %obit to <4 x i32>
store <4 x i1> %val, <4 x i1>* %p2 store <4 x i1> %val, <4 x i1>* %p2
ret <4 x i32> %res ret <4 x i32> %res
Show All 14 Lines
; CHECK-NEXT: cmp x11, x0 ; CHECK-NEXT: cmp x11, x0
; CHECK-NEXT: cset w13, lo ; CHECK-NEXT: cset w13, lo
; CHECK-NEXT: cmp x12, x1 ; CHECK-NEXT: cmp x12, x1
; CHECK-NEXT: cset w14, lo ; CHECK-NEXT: cset w14, lo
; CHECK-NEXT: csel w13, w13, w14, eq ; CHECK-NEXT: csel w13, w13, w14, eq
; CHECK-NEXT: fmov s0, w13 ; CHECK-NEXT: fmov s0, w13
; CHECK-NEXT: mov v0.s[1], w10 ; CHECK-NEXT: mov v0.s[1], w10
; CHECK-NEXT: ldr x10, [sp] ; CHECK-NEXT: ldr x10, [sp]
; CHECK-NEXT: stp x8, x9, [x10, #16]
; CHECK-NEXT: shl v0.2s, v0.2s, #31 ; CHECK-NEXT: shl v0.2s, v0.2s, #31
; CHECK-NEXT: stp x11, x12, [x10] ; CHECK-NEXT: stp x8, x9, [x10, #16]
; CHECK-NEXT: cmlt v0.2s, v0.2s, #0 ; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
; CHECK-NEXT: stp x11, x12, [x10]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<2 x i128>, <2 x i1>} @llvm.uadd.with.overflow.v2i128(<2 x i128> %a0, <2 x i128> %a1) %t = call {<2 x i128>, <2 x i1>} @llvm.uadd.with.overflow.v2i128(<2 x i128> %a0, <2 x i128> %a1)
%val = extractvalue {<2 x i128>, <2 x i1>} %t, 0 %val = extractvalue {<2 x i128>, <2 x i1>} %t, 0
%obit = extractvalue {<2 x i128>, <2 x i1>} %t, 1 %obit = extractvalue {<2 x i128>, <2 x i1>} %t, 1
%res = sext <2 x i1> %obit to <2 x i32> %res = sext <2 x i1> %obit to <2 x i32>
store <2 x i128> %val, <2 x i128>* %p2 store <2 x i128> %val, <2 x i128>* %p2
ret <2 x i32> %res ret <2 x i32> %res
} }

llvm/test/CodeGen/AArch64/vec_umulo.ll

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; CHECK-LABEL: umulo_v3i32: ; CHECK-LABEL: umulo_v3i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s ; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s
; CHECK-NEXT: add x8, x0, #8 ; CHECK-NEXT: add x8, x0, #8
; CHECK-NEXT: umull v3.2d, v0.2s, v1.2s ; CHECK-NEXT: umull v3.2d, v0.2s, v1.2s
; CHECK-NEXT: mul v1.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v1.4s, v0.4s, v1.4s
; CHECK-NEXT: uzp2 v2.4s, v3.4s, v2.4s ; CHECK-NEXT: uzp2 v2.4s, v3.4s, v2.4s
; CHECK-NEXT: st1 { v1.s }[2], [x8] ; CHECK-NEXT: st1 { v1.s }[2], [x8]
; CHECK-NEXT: str d1, [x0]
; CHECK-NEXT: cmtst v2.4s, v2.4s, v2.4s ; CHECK-NEXT: cmtst v2.4s, v2.4s, v2.4s
; CHECK-NEXT: str d1, [x0]
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<3 x i32>, <3 x i1>} @llvm.umul.with.overflow.v3i32(<3 x i32> %a0, <3 x i32> %a1) %t = call {<3 x i32>, <3 x i1>} @llvm.umul.with.overflow.v3i32(<3 x i32> %a0, <3 x i32> %a1)
%val = extractvalue {<3 x i32>, <3 x i1>} %t, 0 %val = extractvalue {<3 x i32>, <3 x i1>} %t, 0
%obit = extractvalue {<3 x i32>, <3 x i1>} %t, 1 %obit = extractvalue {<3 x i32>, <3 x i1>} %t, 1
%res = sext <3 x i1> %obit to <3 x i32> %res = sext <3 x i1> %obit to <3 x i32>
store <3 x i32> %val, <3 x i32>* %p2 store <3 x i32> %val, <3 x i32>* %p2
ret <3 x i32> %res ret <3 x i32> %res
Show All 17 Lines; CHECK-NEXT: ret
store <4 x i32> %val, <4 x i32>* %p2 store <4 x i32> %val, <4 x i32>* %p2
ret <4 x i32> %res ret <4 x i32> %res
} }
define <6 x i32> @umulo_v6i32(<6 x i32> %a0, <6 x i32> %a1, <6 x i32>* %p2) nounwind { define <6 x i32> @umulo_v6i32(<6 x i32> %a0, <6 x i32> %a1, <6 x i32>* %p2) nounwind {
; CHECK-LABEL: umulo_v6i32: ; CHECK-LABEL: umulo_v6i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fmov s0, w6 ; CHECK-NEXT: fmov s0, w6
; CHECK-NEXT: fmov s1, w0
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: ldr s2, [sp, #16] ; CHECK-NEXT: fmov s2, w0
; CHECK-NEXT: ldr s1, [sp, #16]
; CHECK-NEXT: add x9, sp, #24 ; CHECK-NEXT: add x9, sp, #24
; CHECK-NEXT: add x10, sp, #8
; CHECK-NEXT: mov v0.s[1], w7
; CHECK-NEXT: fmov s3, w4 ; CHECK-NEXT: fmov s3, w4
; CHECK-NEXT: mov v1.s[1], w1 ; CHECK-NEXT: mov v0.s[1], w7
; CHECK-NEXT: ld1 { v2.s }[1], [x9] ; CHECK-NEXT: mov v2.s[1], w1
; CHECK-NEXT: mov v3.s[1], w5
; CHECK-NEXT: ld1 { v0.s }[2], [x8] ; CHECK-NEXT: ld1 { v0.s }[2], [x8]
; CHECK-NEXT: mov v1.s[2], w2 ; CHECK-NEXT: add x8, sp, #8
; CHECK-NEXT: ld1 { v1.s }[1], [x9]
; CHECK-NEXT: mov v2.s[2], w2
; CHECK-NEXT: mov v3.s[1], w5
; CHECK-NEXT: mov v2.s[3], w3
; CHECK-NEXT: ld1 { v0.s }[3], [x8]
; CHECK-NEXT: umull2 v4.2d, v3.4s, v1.4s
; CHECK-NEXT: ldr x8, [sp, #32] ; CHECK-NEXT: ldr x8, [sp, #32]
; CHECK-NEXT: umull2 v4.2d, v3.4s, v2.4s ; CHECK-NEXT: umull v5.2d, v3.2s, v1.2s
; CHECK-NEXT: ld1 { v0.s }[3], [x10] ; CHECK-NEXT: mul v1.4s, v3.4s, v1.4s
; CHECK-NEXT: mov v1.s[3], w3 ; CHECK-NEXT: umull2 v6.2d, v2.4s, v0.4s
; CHECK-NEXT: umull v7.2d, v3.2s, v2.2s ; CHECK-NEXT: umull v7.2d, v2.2s, v0.2s
; CHECK-NEXT: mul v2.4s, v3.4s, v2.4s ; CHECK-NEXT: uzp2 v3.4s, v5.4s, v4.4s
; CHECK-NEXT: umull2 v5.2d, v1.4s, v0.4s ; CHECK-NEXT: mul v0.4s, v2.4s, v0.4s
; CHECK-NEXT: umull v6.2d, v1.2s, v0.2s ; CHECK-NEXT: str d1, [x8, #16]
; CHECK-NEXT: uzp2 v4.4s, v7.4s, v4.4s ; CHECK-NEXT: cmtst v3.4s, v3.4s, v3.4s
; CHECK-NEXT: str d2, [x8, #16] ; CHECK-NEXT: uzp2 v4.4s, v7.4s, v6.4s
; CHECK-NEXT: mul v0.4s, v1.4s, v0.4s
; CHECK-NEXT: uzp2 v5.4s, v6.4s, v5.4s
; CHECK-NEXT: cmtst v4.4s, v4.4s, v4.4s ; CHECK-NEXT: cmtst v4.4s, v4.4s, v4.4s
; CHECK-NEXT: fmov w4, s3
; CHECK-NEXT: mov w5, v3.s[1]
; CHECK-NEXT: str q0, [x8] ; CHECK-NEXT: str q0, [x8]
; CHECK-NEXT: cmtst v3.4s, v5.4s, v5.4s ; CHECK-NEXT: fmov w0, s4
; CHECK-NEXT: mov w5, v4.s[1] ; CHECK-NEXT: mov w1, v4.s[1]
; CHECK-NEXT: fmov w4, s4 ; CHECK-NEXT: mov w2, v4.s[2]
; CHECK-NEXT: mov w1, v3.s[1] ; CHECK-NEXT: mov w3, v4.s[3]
; CHECK-NEXT: mov w2, v3.s[2]
; CHECK-NEXT: mov w3, v3.s[3]
; CHECK-NEXT: fmov w0, s3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<6 x i32>, <6 x i1>} @llvm.umul.with.overflow.v6i32(<6 x i32> %a0, <6 x i32> %a1) %t = call {<6 x i32>, <6 x i1>} @llvm.umul.with.overflow.v6i32(<6 x i32> %a0, <6 x i32> %a1)
%val = extractvalue {<6 x i32>, <6 x i1>} %t, 0 %val = extractvalue {<6 x i32>, <6 x i1>} %t, 0
%obit = extractvalue {<6 x i32>, <6 x i1>} %t, 1 %obit = extractvalue {<6 x i32>, <6 x i1>} %t, 1
%res = sext <6 x i1> %obit to <6 x i32> %res = sext <6 x i1> %obit to <6 x i32>
store <6 x i32> %val, <6 x i32>* %p2 store <6 x i32> %val, <6 x i32>* %p2
ret <6 x i32> %res ret <6 x i32> %res
} }
define <8 x i32> @umulo_v8i32(<8 x i32> %a0, <8 x i32> %a1, <8 x i32>* %p2) nounwind { define <8 x i32> @umulo_v8i32(<8 x i32> %a0, <8 x i32> %a1, <8 x i32>* %p2) nounwind {
; CHECK-LABEL: umulo_v8i32: ; CHECK-LABEL: umulo_v8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umull2 v4.2d, v1.4s, v3.4s ; CHECK-NEXT: umull2 v4.2d, v1.4s, v3.4s
; CHECK-NEXT: umull2 v5.2d, v0.4s, v2.4s ; CHECK-NEXT: umull2 v5.2d, v0.4s, v2.4s
; CHECK-NEXT: umull v6.2d, v0.2s, v2.2s ; CHECK-NEXT: umull v6.2d, v0.2s, v2.2s
; CHECK-NEXT: umull v7.2d, v1.2s, v3.2s ; CHECK-NEXT: umull v7.2d, v1.2s, v3.2s
; CHECK-NEXT: mul v3.4s, v1.4s, v3.4s ; CHECK-NEXT: mul v3.4s, v1.4s, v3.4s
; CHECK-NEXT: mul v2.4s, v0.4s, v2.4s ; CHECK-NEXT: mul v2.4s, v0.4s, v2.4s
; CHECK-NEXT: uzp2 v5.4s, v6.4s, v5.4s ; CHECK-NEXT: uzp2 v5.4s, v6.4s, v5.4s
; CHECK-NEXT: uzp2 v6.4s, v7.4s, v4.4s ; CHECK-NEXT: uzp2 v6.4s, v7.4s, v4.4s
; CHECK-NEXT: stp q2, q3, [x0]
; CHECK-NEXT: cmtst v4.4s, v5.4s, v5.4s ; CHECK-NEXT: cmtst v4.4s, v5.4s, v5.4s
; CHECK-NEXT: cmtst v5.4s, v6.4s, v6.4s ; CHECK-NEXT: cmtst v5.4s, v6.4s, v6.4s
; CHECK-NEXT: stp q2, q3, [x0]
; CHECK-NEXT: mov v0.16b, v4.16b ; CHECK-NEXT: mov v0.16b, v4.16b
; CHECK-NEXT: mov v1.16b, v5.16b ; CHECK-NEXT: mov v1.16b, v5.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<8 x i32>, <8 x i1>} @llvm.umul.with.overflow.v8i32(<8 x i32> %a0, <8 x i32> %a1) %t = call {<8 x i32>, <8 x i1>} @llvm.umul.with.overflow.v8i32(<8 x i32> %a0, <8 x i32> %a1)
%val = extractvalue {<8 x i32>, <8 x i1>} %t, 0 %val = extractvalue {<8 x i32>, <8 x i1>} %t, 0
%obit = extractvalue {<8 x i32>, <8 x i1>} %t, 1 %obit = extractvalue {<8 x i32>, <8 x i1>} %t, 1
%res = sext <8 x i1> %obit to <8 x i32> %res = sext <8 x i1> %obit to <8 x i32>
store <8 x i32> %val, <8 x i32>* %p2 store <8 x i32> %val, <8 x i32>* %p2
ret <8 x i32> %res ret <8 x i32> %res
} }
define <16 x i32> @umulo_v16i8(<16 x i8> %a0, <16 x i8> %a1, <16 x i8>* %p2) nounwind { define <16 x i32> @umulo_v16i8(<16 x i8> %a0, <16 x i8> %a1, <16 x i8>* %p2) nounwind {
; CHECK-LABEL: umulo_v16i8: ; CHECK-LABEL: umulo_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umull2 v2.8h, v0.16b, v1.16b ; CHECK-NEXT: umull2 v2.8h, v0.16b, v1.16b
; CHECK-NEXT: umull v3.8h, v0.8b, v1.8b ; CHECK-NEXT: umull v3.8h, v0.8b, v1.8b
; CHECK-NEXT: mul v5.16b, v0.16b, v1.16b ; CHECK-NEXT: mul v4.16b, v0.16b, v1.16b
; CHECK-NEXT: uzp2 v2.16b, v3.16b, v2.16b ; CHECK-NEXT: uzp2 v2.16b, v3.16b, v2.16b
; CHECK-NEXT: str q5, [x0] ; CHECK-NEXT: str q4, [x0]
; CHECK-NEXT: cmtst v2.16b, v2.16b, v2.16b ; CHECK-NEXT: cmtst v2.16b, v2.16b, v2.16b
; CHECK-NEXT: zip1 v0.8b, v2.8b, v0.8b
; CHECK-NEXT: zip2 v1.8b, v2.8b, v0.8b
; CHECK-NEXT: ext v2.16b, v2.16b, v2.16b, #8
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-NEXT: zip1 v3.8b, v2.8b, v0.8b ; CHECK-NEXT: zip1 v3.8b, v2.8b, v0.8b
; CHECK-NEXT: zip2 v4.8b, v2.8b, v0.8b ; CHECK-NEXT: zip2 v2.8b, v2.8b, v0.8b
; CHECK-NEXT: ext v0.16b, v2.16b, v2.16b, #8 ; CHECK-NEXT: shl v0.4s, v0.4s, #31
; CHECK-NEXT: ushll v1.4s, v3.4h, #0 ; CHECK-NEXT: ushll v3.4s, v3.4h, #0
; CHECK-NEXT: ushll v2.4s, v4.4h, #0
; CHECK-NEXT: zip1 v3.8b, v0.8b, v0.8b
; CHECK-NEXT: zip2 v4.8b, v0.8b, v0.8b
; CHECK-NEXT: shl v1.4s, v1.4s, #31 ; CHECK-NEXT: shl v1.4s, v1.4s, #31
; CHECK-NEXT: shl v2.4s, v2.4s, #31 ; CHECK-NEXT: ushll v2.4s, v2.4h, #0
; CHECK-NEXT: cmlt v0.4s, v1.4s, #0
; CHECK-NEXT: cmlt v1.4s, v2.4s, #0
; CHECK-NEXT: ushll v2.4s, v3.4h, #0
; CHECK-NEXT: ushll v3.4s, v4.4h, #0
; CHECK-NEXT: shl v2.4s, v2.4s, #31
; CHECK-NEXT: shl v3.4s, v3.4s, #31 ; CHECK-NEXT: shl v3.4s, v3.4s, #31
; CHECK-NEXT: cmlt v2.4s, v2.4s, #0 ; CHECK-NEXT: shl v5.4s, v2.4s, #31
; CHECK-NEXT: cmlt v3.4s, v3.4s, #0 ; CHECK-NEXT: cmlt v0.4s, v0.4s, #0
; CHECK-NEXT: cmlt v1.4s, v1.4s, #0
; CHECK-NEXT: cmlt v2.4s, v3.4s, #0
; CHECK-NEXT: cmlt v3.4s, v5.4s, #0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<16 x i8>, <16 x i1>} @llvm.umul.with.overflow.v16i8(<16 x i8> %a0, <16 x i8> %a1) %t = call {<16 x i8>, <16 x i1>} @llvm.umul.with.overflow.v16i8(<16 x i8> %a0, <16 x i8> %a1)
%val = extractvalue {<16 x i8>, <16 x i1>} %t, 0 %val = extractvalue {<16 x i8>, <16 x i1>} %t, 0
%obit = extractvalue {<16 x i8>, <16 x i1>} %t, 1 %obit = extractvalue {<16 x i8>, <16 x i1>} %t, 1
%res = sext <16 x i1> %obit to <16 x i32> %res = sext <16 x i1> %obit to <16 x i32>
store <16 x i8> %val, <16 x i8>* %p2 store <16 x i8> %val, <16 x i8>* %p2
ret <16 x i32> %res ret <16 x i32> %res
} }
Show All 26 Lines; CHECK-NEXT: ret
store <8 x i16> %val, <8 x i16>* %p2 store <8 x i16> %val, <8 x i16>* %p2
ret <8 x i32> %res ret <8 x i32> %res
} }
define <2 x i32> @umulo_v2i64(<2 x i64> %a0, <2 x i64> %a1, <2 x i64>* %p2) nounwind { define <2 x i32> @umulo_v2i64(<2 x i64> %a0, <2 x i64> %a1, <2 x i64>* %p2) nounwind {
; CHECK-LABEL: umulo_v2i64: ; CHECK-LABEL: umulo_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, v1.d[1] ; CHECK-NEXT: mov x8, v1.d[1]
; CHECK-NEXT: fmov x10, d1
; CHECK-NEXT: mov x9, v0.d[1] ; CHECK-NEXT: mov x9, v0.d[1]
; CHECK-NEXT: fmov x10, d1
; CHECK-NEXT: fmov x11, d0 ; CHECK-NEXT: fmov x11, d0
; CHECK-NEXT: umulh x12, x9, x8 ; CHECK-NEXT: umulh x12, x9, x8
; CHECK-NEXT: mul x8, x9, x8
; CHECK-NEXT: umulh x13, x11, x10 ; CHECK-NEXT: umulh x13, x11, x10
; CHECK-NEXT: cmp xzr, x12 ; CHECK-NEXT: cmp xzr, x12
; CHECK-NEXT: mul x10, x11, x10
; CHECK-NEXT: csetm x12, ne ; CHECK-NEXT: csetm x12, ne
; CHECK-NEXT: mul x10, x11, x10
; CHECK-NEXT: cmp xzr, x13 ; CHECK-NEXT: cmp xzr, x13
; CHECK-NEXT: csetm x13, ne ; CHECK-NEXT: csetm x13, ne
; CHECK-NEXT: mul x8, x9, x8
; CHECK-NEXT: fmov d1, x10 ; CHECK-NEXT: fmov d1, x10
; CHECK-NEXT: fmov d0, x13 ; CHECK-NEXT: fmov d0, x13
; CHECK-NEXT: mov v1.d[1], x8 ; CHECK-NEXT: mov v1.d[1], x8
; CHECK-NEXT: mov v0.d[1], x12 ; CHECK-NEXT: mov v0.d[1], x12
; CHECK-NEXT: str q1, [x0] ; CHECK-NEXT: str q1, [x0]
; CHECK-NEXT: xtn v0.2s, v0.2d ; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<2 x i64>, <2 x i1>} @llvm.umul.with.overflow.v2i64(<2 x i64> %a0, <2 x i64> %a1) %t = call {<2 x i64>, <2 x i1>} @llvm.umul.with.overflow.v2i64(<2 x i64> %a0, <2 x i64> %a1)
%val = extractvalue {<2 x i64>, <2 x i1>} %t, 0 %val = extractvalue {<2 x i64>, <2 x i1>} %t, 0
%obit = extractvalue {<2 x i64>, <2 x i1>} %t, 1 %obit = extractvalue {<2 x i64>, <2 x i1>} %t, 1
%res = sext <2 x i1> %obit to <2 x i32> %res = sext <2 x i1> %obit to <2 x i32>
store <2 x i64> %val, <2 x i64>* %p2 store <2 x i64> %val, <2 x i64>* %p2
ret <2 x i32> %res ret <2 x i32> %res
} }
define <4 x i32> @umulo_v4i24(<4 x i24> %a0, <4 x i24> %a1, <4 x i24>* %p2) nounwind { define <4 x i32> @umulo_v4i24(<4 x i24> %a0, <4 x i24> %a1, <4 x i24>* %p2) nounwind {
; CHECK-LABEL: umulo_v4i24: ; CHECK-LABEL: umulo_v4i24:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: bic v1.4s, #255, lsl #24 ; CHECK-NEXT: bic v1.4s, #255, lsl #24
; CHECK-NEXT: bic v0.4s, #255, lsl #24 ; CHECK-NEXT: bic v0.4s, #255, lsl #24
; CHECK-NEXT: mul v2.4s, v0.4s, v1.4s ; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s
; CHECK-NEXT: umull2 v3.2d, v0.4s, v1.4s ; CHECK-NEXT: umull v3.2d, v0.2s, v1.2s
; CHECK-NEXT: umull v0.2d, v0.2s, v1.2s ; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: mov w8, v2.s[3] ; CHECK-NEXT: uzp2 v1.4s, v3.4s, v2.4s
; CHECK-NEXT: mov w10, v2.s[2] ; CHECK-NEXT: mov w8, v0.s[3]
; CHECK-NEXT: mov w11, v2.s[1] ; CHECK-NEXT: ushr v2.4s, v0.4s, #24
; CHECK-NEXT: ushr v1.4s, v2.4s, #24 ; CHECK-NEXT: fmov w11, s0
; CHECK-NEXT: uzp2 v0.4s, v0.4s, v3.4s
; CHECK-NEXT: fmov w9, s2
; CHECK-NEXT: cmtst v1.4s, v1.4s, v1.4s
; CHECK-NEXT: sturh w8, [x0, #9] ; CHECK-NEXT: sturh w8, [x0, #9]
; CHECK-NEXT: lsr w8, w8, #16 ; CHECK-NEXT: lsr w8, w8, #16
; CHECK-NEXT: strh w10, [x0, #6] ; CHECK-NEXT: mov w9, v0.s[2]
; CHECK-NEXT: lsr w10, w10, #16 ; CHECK-NEXT: mov w10, v0.s[1]
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 ; CHECK-NEXT: cmeq v0.4s, v1.4s, #0
; CHECK-NEXT: sturh w11, [x0, #3] ; CHECK-NEXT: strh w11, [x0]
; CHECK-NEXT: lsr w11, w11, #16 ; CHECK-NEXT: cmtst v1.4s, v2.4s, v2.4s
; CHECK-NEXT: strh w9, [x0, #6]
; CHECK-NEXT: sturh w10, [x0, #3]
; CHECK-NEXT: lsr w9, w9, #16
; CHECK-NEXT: strb w8, [x0, #11] ; CHECK-NEXT: strb w8, [x0, #11]
; CHECK-NEXT: lsr w8, w9, #16 ; CHECK-NEXT: lsr w8, w10, #16
; CHECK-NEXT: strh w9, [x0] ; CHECK-NEXT: lsr w10, w11, #16
; CHECK-NEXT: orn v0.16b, v1.16b, v0.16b ; CHECK-NEXT: orn v0.16b, v1.16b, v0.16b
; CHECK-NEXT: strb w10, [x0, #8] ; CHECK-NEXT: strb w9, [x0, #8]
; CHECK-NEXT: strb w11, [x0, #5] ; CHECK-NEXT: strb w8, [x0, #5]
; CHECK-NEXT: strb w8, [x0, #2] ; CHECK-NEXT: strb w10, [x0, #2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<4 x i24>, <4 x i1>} @llvm.umul.with.overflow.v4i24(<4 x i24> %a0, <4 x i24> %a1) %t = call {<4 x i24>, <4 x i1>} @llvm.umul.with.overflow.v4i24(<4 x i24> %a0, <4 x i24> %a1)
%val = extractvalue {<4 x i24>, <4 x i1>} %t, 0 %val = extractvalue {<4 x i24>, <4 x i1>} %t, 0
%obit = extractvalue {<4 x i24>, <4 x i1>} %t, 1 %obit = extractvalue {<4 x i24>, <4 x i1>} %t, 1
%res = sext <4 x i1> %obit to <4 x i32> %res = sext <4 x i1> %obit to <4 x i32>
store <4 x i24> %val, <4 x i24>* %p2 store <4 x i24> %val, <4 x i24>* %p2
ret <4 x i32> %res ret <4 x i32> %res
} }
define <4 x i32> @umulo_v4i1(<4 x i1> %a0, <4 x i1> %a1, <4 x i1>* %p2) nounwind { define <4 x i32> @umulo_v4i1(<4 x i1> %a0, <4 x i1> %a1, <4 x i1>* %p2) nounwind {
; CHECK-LABEL: umulo_v4i1: ; CHECK-LABEL: umulo_v4i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fmov d2, d0 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: and v1.8b, v2.8b, v1.8b ; CHECK-NEXT: umov w9, v0.h[2]
; CHECK-NEXT: umov w8, v1.h[1] ; CHECK-NEXT: umov w10, v0.h[0]
; CHECK-NEXT: umov w9, v1.h[2]
; CHECK-NEXT: umov w10, v1.h[0]
; CHECK-NEXT: umov w11, v1.h[3]
; CHECK-NEXT: and w8, w8, #0x1 ; CHECK-NEXT: and w8, w8, #0x1
; CHECK-NEXT: and w9, w9, #0x1 ; CHECK-NEXT: and w9, w9, #0x1
; CHECK-NEXT: bfi w10, w8, #1, #1 ; CHECK-NEXT: bfi w10, w8, #1, #1
; CHECK-NEXT: umov w8, v0.h[3]
; CHECK-NEXT: bfi w10, w9, #2, #1 ; CHECK-NEXT: bfi w10, w9, #2, #1
; CHECK-NEXT: bfi w10, w11, #3, #29 ; CHECK-NEXT: bfi w10, w8, #3, #29
; CHECK-NEXT: and w8, w10, #0xf ; CHECK-NEXT: and w8, w10, #0xf
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: strb w8, [x0] ; CHECK-NEXT: strb w8, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<4 x i1>, <4 x i1>} @llvm.umul.with.overflow.v4i1(<4 x i1> %a0, <4 x i1> %a1) %t = call {<4 x i1>, <4 x i1>} @llvm.umul.with.overflow.v4i1(<4 x i1> %a0, <4 x i1> %a1)
%val = extractvalue {<4 x i1>, <4 x i1>} %t, 0 %val = extractvalue {<4 x i1>, <4 x i1>} %t, 0
%obit = extractvalue {<4 x i1>, <4 x i1>} %t, 1 %obit = extractvalue {<4 x i1>, <4 x i1>} %t, 1
%res = sext <4 x i1> %obit to <4 x i32> %res = sext <4 x i1> %obit to <4 x i32>
store <4 x i1> %val, <4 x i1>* %p2 store <4 x i1> %val, <4 x i1>* %p2
ret <4 x i32> %res ret <4 x i32> %res
Show All 38 Lines
; CHECK-NEXT: orr w8, w8, w11 ; CHECK-NEXT: orr w8, w8, w11
; CHECK-NEXT: mul x11, x0, x4 ; CHECK-NEXT: mul x11, x0, x4
; CHECK-NEXT: ldr x9, [sp] ; CHECK-NEXT: ldr x9, [sp]
; CHECK-NEXT: fmov s0, w12 ; CHECK-NEXT: fmov s0, w12
; CHECK-NEXT: stp x11, x15, [x9] ; CHECK-NEXT: stp x11, x15, [x9]
; CHECK-NEXT: mov v0.s[1], w8 ; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: mul x8, x2, x6 ; CHECK-NEXT: mul x8, x2, x6
; CHECK-NEXT: shl v0.2s, v0.2s, #31 ; CHECK-NEXT: shl v0.2s, v0.2s, #31
; CHECK-NEXT: stp x8, x10, [x9, #16]
; CHECK-NEXT: cmlt v0.2s, v0.2s, #0 ; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
; CHECK-NEXT: stp x8, x10, [x9, #16]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<2 x i128>, <2 x i1>} @llvm.umul.with.overflow.v2i128(<2 x i128> %a0, <2 x i128> %a1) %t = call {<2 x i128>, <2 x i1>} @llvm.umul.with.overflow.v2i128(<2 x i128> %a0, <2 x i128> %a1)
%val = extractvalue {<2 x i128>, <2 x i1>} %t, 0 %val = extractvalue {<2 x i128>, <2 x i1>} %t, 0
%obit = extractvalue {<2 x i128>, <2 x i1>} %t, 1 %obit = extractvalue {<2 x i128>, <2 x i1>} %t, 1
%res = sext <2 x i1> %obit to <2 x i32> %res = sext <2 x i1> %obit to <2 x i32>
store <2 x i128> %val, <2 x i128>* %p2 store <2 x i128> %val, <2 x i128>* %p2
ret <2 x i32> %res ret <2 x i32> %res
} }

llvm/test/CodeGen/AArch64/vecreduce-add.ll

Show First 20 Lines • Show All 870 Lines • ▼ Show 20 Lines
; CHECK-BASE-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-BASE-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-BASE-NEXT: uaddlv s0, v0.8h ; CHECK-BASE-NEXT: uaddlv s0, v0.8h
; CHECK-BASE-NEXT: fmov w8, s0 ; CHECK-BASE-NEXT: fmov w8, s0
; CHECK-BASE-NEXT: add w0, w8, w0 ; CHECK-BASE-NEXT: add w0, w8, w0
; CHECK-BASE-NEXT: ret ; CHECK-BASE-NEXT: ret
; ;
; CHECK-DOT-LABEL: add_v8i8_v8i32_acc_zext: ; CHECK-DOT-LABEL: add_v8i8_v8i32_acc_zext:
; CHECK-DOT: // %bb.0: // %entry ; CHECK-DOT: // %bb.0: // %entry
; CHECK-DOT-NEXT: movi v1.8b, #1 ; CHECK-DOT-NEXT: movi v1.2d, #0000000000000000
; CHECK-DOT-NEXT: movi v2.2d, #0000000000000000 ; CHECK-DOT-NEXT: movi v2.8b, #1
; CHECK-DOT-NEXT: udot v2.2s, v0.8b, v1.8b ; CHECK-DOT-NEXT: udot v1.2s, v0.8b, v2.8b
; CHECK-DOT-NEXT: addp v0.2s, v2.2s, v2.2s ; CHECK-DOT-NEXT: addp v0.2s, v1.2s, v1.2s
; CHECK-DOT-NEXT: fmov w8, s0 ; CHECK-DOT-NEXT: fmov w8, s0
; CHECK-DOT-NEXT: add w0, w8, w0 ; CHECK-DOT-NEXT: add w0, w8, w0
; CHECK-DOT-NEXT: ret ; CHECK-DOT-NEXT: ret
entry: entry:
%xx = zext <8 x i8> %x to <8 x i32> %xx = zext <8 x i8> %x to <8 x i32>
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx) %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
} }
define i32 @add_v8i8_v8i32_acc_sext(<8 x i8> %x, i32 %a) { define i32 @add_v8i8_v8i32_acc_sext(<8 x i8> %x, i32 %a) {
; CHECK-BASE-LABEL: add_v8i8_v8i32_acc_sext: ; CHECK-BASE-LABEL: add_v8i8_v8i32_acc_sext:
; CHECK-BASE: // %bb.0: // %entry ; CHECK-BASE: // %bb.0: // %entry
; CHECK-BASE-NEXT: sshll v0.8h, v0.8b, #0 ; CHECK-BASE-NEXT: sshll v0.8h, v0.8b, #0
; CHECK-BASE-NEXT: saddlv s0, v0.8h ; CHECK-BASE-NEXT: saddlv s0, v0.8h
; CHECK-BASE-NEXT: fmov w8, s0 ; CHECK-BASE-NEXT: fmov w8, s0
; CHECK-BASE-NEXT: add w0, w8, w0 ; CHECK-BASE-NEXT: add w0, w8, w0
; CHECK-BASE-NEXT: ret ; CHECK-BASE-NEXT: ret
; ;
; CHECK-DOT-LABEL: add_v8i8_v8i32_acc_sext: ; CHECK-DOT-LABEL: add_v8i8_v8i32_acc_sext:
; CHECK-DOT: // %bb.0: // %entry ; CHECK-DOT: // %bb.0: // %entry
; CHECK-DOT-NEXT: movi v1.8b, #1 ; CHECK-DOT-NEXT: movi v1.2d, #0000000000000000
; CHECK-DOT-NEXT: movi v2.2d, #0000000000000000 ; CHECK-DOT-NEXT: movi v2.8b, #1
; CHECK-DOT-NEXT: sdot v2.2s, v0.8b, v1.8b ; CHECK-DOT-NEXT: sdot v1.2s, v0.8b, v2.8b
; CHECK-DOT-NEXT: addp v0.2s, v2.2s, v2.2s ; CHECK-DOT-NEXT: addp v0.2s, v1.2s, v1.2s
; CHECK-DOT-NEXT: fmov w8, s0 ; CHECK-DOT-NEXT: fmov w8, s0
; CHECK-DOT-NEXT: add w0, w8, w0 ; CHECK-DOT-NEXT: add w0, w8, w0
; CHECK-DOT-NEXT: ret ; CHECK-DOT-NEXT: ret
entry: entry:
%xx = sext <8 x i8> %x to <8 x i32> %xx = sext <8 x i8> %x to <8 x i32>
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx) %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
▲ Show 20 Lines • Show All 659 Lines • ▼ Show 20 Lines
; CHECK-BASE-NEXT: uaddlp v0.4s, v0.8h ; CHECK-BASE-NEXT: uaddlp v0.4s, v0.8h
; CHECK-BASE-NEXT: uadalp v0.4s, v1.8h ; CHECK-BASE-NEXT: uadalp v0.4s, v1.8h
; CHECK-BASE-NEXT: addv s0, v0.4s ; CHECK-BASE-NEXT: addv s0, v0.4s
; CHECK-BASE-NEXT: fmov w0, s0 ; CHECK-BASE-NEXT: fmov w0, s0
; CHECK-BASE-NEXT: ret ; CHECK-BASE-NEXT: ret
; ;
; CHECK-DOT-LABEL: add_pair_v8i8_v8i32_zext: ; CHECK-DOT-LABEL: add_pair_v8i8_v8i32_zext:
; CHECK-DOT: // %bb.0: // %entry ; CHECK-DOT: // %bb.0: // %entry
; CHECK-DOT-NEXT: movi v2.8b, #1 ; CHECK-DOT-NEXT: movi v2.2d, #0000000000000000
; CHECK-DOT-NEXT: movi v3.2d, #0000000000000000 ; CHECK-DOT-NEXT: movi v3.8b, #1
; CHECK-DOT-NEXT: udot v3.2s, v1.8b, v2.8b ; CHECK-DOT-NEXT: udot v2.2s, v1.8b, v3.8b
; CHECK-DOT-NEXT: udot v3.2s, v0.8b, v2.8b ; CHECK-DOT-NEXT: udot v2.2s, v0.8b, v3.8b
; CHECK-DOT-NEXT: addp v0.2s, v3.2s, v3.2s ; CHECK-DOT-NEXT: addp v0.2s, v2.2s, v2.2s
; CHECK-DOT-NEXT: fmov w0, s0 ; CHECK-DOT-NEXT: fmov w0, s0
; CHECK-DOT-NEXT: ret ; CHECK-DOT-NEXT: ret
entry: entry:
%xx = zext <8 x i8> %x to <8 x i32> %xx = zext <8 x i8> %x to <8 x i32>
%z1 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx) %z1 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)
%yy = zext <8 x i8> %y to <8 x i32> %yy = zext <8 x i8> %y to <8 x i32>
%z2 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %yy) %z2 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %yy)
%z = add i32 %z1, %z2 %z = add i32 %z1, %z2
ret i32 %z ret i32 %z
} }
define i32 @add_pair_v8i8_v8i32_sext(<8 x i8> %x, <8 x i8> %y) { define i32 @add_pair_v8i8_v8i32_sext(<8 x i8> %x, <8 x i8> %y) {
; CHECK-BASE-LABEL: add_pair_v8i8_v8i32_sext: ; CHECK-BASE-LABEL: add_pair_v8i8_v8i32_sext:
; CHECK-BASE: // %bb.0: // %entry ; CHECK-BASE: // %bb.0: // %entry
; CHECK-BASE-NEXT: sshll v0.8h, v0.8b, #0 ; CHECK-BASE-NEXT: sshll v0.8h, v0.8b, #0
; CHECK-BASE-NEXT: sshll v1.8h, v1.8b, #0 ; CHECK-BASE-NEXT: sshll v1.8h, v1.8b, #0
; CHECK-BASE-NEXT: saddlp v0.4s, v0.8h ; CHECK-BASE-NEXT: saddlp v0.4s, v0.8h
; CHECK-BASE-NEXT: sadalp v0.4s, v1.8h ; CHECK-BASE-NEXT: sadalp v0.4s, v1.8h
; CHECK-BASE-NEXT: addv s0, v0.4s ; CHECK-BASE-NEXT: addv s0, v0.4s
; CHECK-BASE-NEXT: fmov w0, s0 ; CHECK-BASE-NEXT: fmov w0, s0
; CHECK-BASE-NEXT: ret ; CHECK-BASE-NEXT: ret
; ;
; CHECK-DOT-LABEL: add_pair_v8i8_v8i32_sext: ; CHECK-DOT-LABEL: add_pair_v8i8_v8i32_sext:
; CHECK-DOT: // %bb.0: // %entry ; CHECK-DOT: // %bb.0: // %entry
; CHECK-DOT-NEXT: movi v2.8b, #1 ; CHECK-DOT-NEXT: movi v2.2d, #0000000000000000
; CHECK-DOT-NEXT: movi v3.2d, #0000000000000000 ; CHECK-DOT-NEXT: movi v3.8b, #1
; CHECK-DOT-NEXT: sdot v3.2s, v1.8b, v2.8b ; CHECK-DOT-NEXT: sdot v2.2s, v1.8b, v3.8b
; CHECK-DOT-NEXT: sdot v3.2s, v0.8b, v2.8b ; CHECK-DOT-NEXT: sdot v2.2s, v0.8b, v3.8b
; CHECK-DOT-NEXT: addp v0.2s, v3.2s, v3.2s ; CHECK-DOT-NEXT: addp v0.2s, v2.2s, v2.2s
; CHECK-DOT-NEXT: fmov w0, s0 ; CHECK-DOT-NEXT: fmov w0, s0
; CHECK-DOT-NEXT: ret ; CHECK-DOT-NEXT: ret
entry: entry:
%xx = sext <8 x i8> %x to <8 x i32> %xx = sext <8 x i8> %x to <8 x i32>
%z1 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx) %z1 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)
%yy = sext <8 x i8> %y to <8 x i32> %yy = sext <8 x i8> %y to <8 x i32>
%z2 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %yy) %z2 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %yy)
%z = add i32 %z1, %z2 %z = add i32 %z1, %z2
▲ Show 20 Lines • Show All 394 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll

Show First 20 Lines • Show All 91 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%b = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %a) %b = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %a)
ret i8 %b ret i8 %b
} }
define i8 @test_v9i8(<9 x i8> %a) nounwind { define i8 @test_v9i8(<9 x i8> %a) nounwind {
; CHECK-LABEL: test_v9i8: ; CHECK-LABEL: test_v9i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-1 ; CHECK-NEXT: mov w8, #-1
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: mov v1.16b, v0.16b ; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: mov v1.b[9], w8 ; CHECK-NEXT: mov v1.b[9], w8
; CHECK-NEXT: mov v1.b[10], w8 ; CHECK-NEXT: mov v1.b[10], w8
; CHECK-NEXT: mov v1.b[11], w8 ; CHECK-NEXT: mov v1.b[11], w8
; CHECK-NEXT: mov v1.b[13], w8 ; CHECK-NEXT: mov v1.b[13], w8
; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8 ; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-NEXT: and v1.8b, v0.8b, v1.8b ; CHECK-NEXT: and v1.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v1.b[1] ; CHECK-NEXT: umov w8, v1.b[1]
; CHECK-NEXT: umov w9, v1.b[0] ; CHECK-NEXT: umov w9, v1.b[0]
; CHECK-NEXT: umov w10, v1.b[2] ; CHECK-NEXT: umov w10, v1.b[2]
; CHECK-NEXT: umov w11, v1.b[3]
; CHECK-NEXT: and w8, w9, w8 ; CHECK-NEXT: and w8, w9, w8
; CHECK-NEXT: umov w9, v1.b[3]
; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[4]
; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[5] ; CHECK-NEXT: umov w9, v0.b[5]
; CHECK-NEXT: and w8, w8, w10 ; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[6] ; CHECK-NEXT: umov w10, v0.b[6]
; CHECK-NEXT: and w8, w8, w11
; CHECK-NEXT: umov w11, v0.b[7]
; CHECK-NEXT: and w8, w8, w12
; CHECK-NEXT: and w8, w8, w9 ; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: umov w9, v0.b[7]
; CHECK-NEXT: and w8, w8, w10 ; CHECK-NEXT: and w8, w8, w10
; CHECK-NEXT: and w0, w8, w11 ; CHECK-NEXT: and w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%b = call i8 @llvm.vector.reduce.and.v9i8(<9 x i8> %a) %b = call i8 @llvm.vector.reduce.and.v9i8(<9 x i8> %a)
ret i8 %b ret i8 %b
} }
define i32 @test_v3i32(<3 x i32> %a) nounwind { define i32 @test_v3i32(<3 x i32> %a) nounwind {
; CHECK-LABEL: test_v3i32: ; CHECK-LABEL: test_v3i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b ; CHECK-NEXT: and v1.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s1
; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: and w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%b = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> %a) %b = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> %a)
ret i32 %b ret i32 %b
} }
define i1 @test_v4i1(<4 x i1> %a) nounwind { define i1 @test_v4i1(<4 x i1> %a) nounwind {
; CHECK-LABEL: test_v4i1: ; CHECK-LABEL: test_v4i1:
Show All 12 Lines; CHECK-NEXT: ret
ret i1 %b ret i1 %b
} }
define i24 @test_v4i24(<4 x i24> %a) nounwind { define i24 @test_v4i24(<4 x i24> %a) nounwind {
; CHECK-LABEL: test_v4i24: ; CHECK-LABEL: test_v4i24:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: and w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%b = call i24 @llvm.vector.reduce.and.v4i24(<4 x i24> %a) %b = call i24 @llvm.vector.reduce.and.v4i24(<4 x i24> %a)
ret i24 %b ret i24 %b
} }
define i128 @test_v2i128(<2 x i128> %a) nounwind { define i128 @test_v2i128(<2 x i128> %a) nounwind {
; CHECK-LABEL: test_v2i128: ; CHECK-LABEL: test_v2i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and x0, x0, x2 ; CHECK-NEXT: and x0, x0, x2
; CHECK-NEXT: and x1, x1, x3 ; CHECK-NEXT: and x1, x1, x3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%b = call i128 @llvm.vector.reduce.and.v2i128(<2 x i128> %a) %b = call i128 @llvm.vector.reduce.and.v2i128(<2 x i128> %a)
ret i128 %b ret i128 %b
} }
define i32 @test_v16i32(<16 x i32> %a) nounwind { define i32 @test_v16i32(<16 x i32> %a) nounwind {
; CHECK-LABEL: test_v16i32: ; CHECK-LABEL: test_v16i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and v1.16b, v1.16b, v3.16b ; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: and w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%b = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %a) %b = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %a)
ret i32 %b ret i32 %b
} }

llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll

Show First 20 Lines • Show All 178 Lines • ▼ Show 20 Lines
; CHECK-NOFP-NEXT: fcvt s1, h1 ; CHECK-NOFP-NEXT: fcvt s1, h1
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1 ; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt h0, s0 ; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: ret ; CHECK-NOFP-NEXT: ret
; ;
; CHECK-FP-LABEL: test_v11f16: ; CHECK-FP-LABEL: test_v11f16:
; CHECK-FP: // %bb.0: ; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0 ; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-FP-NEXT: mov x8, sp
; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1 ; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2 ; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3 ; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4 ; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
; CHECK-FP-NEXT: mov x8, sp
; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5 ; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6 ; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7 ; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
; CHECK-FP-NEXT: mov v0.h[1], v1.h[0] ; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
; CHECK-FP-NEXT: movi v1.8h, #252, lsl #8 ; CHECK-FP-NEXT: movi v1.8h, #252, lsl #8
; CHECK-FP-NEXT: mov v0.h[2], v2.h[0] ; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[0], [x8] ; CHECK-FP-NEXT: ld1 { v1.h }[0], [x8]
; CHECK-FP-NEXT: add x8, sp, #8 ; CHECK-FP-NEXT: add x8, sp, #8
; CHECK-FP-NEXT: mov v0.h[3], v3.h[0] ; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[1], [x8] ; CHECK-FP-NEXT: ld1 { v1.h }[1], [x8]
; CHECK-FP-NEXT: add x8, sp, #16 ; CHECK-FP-NEXT: add x8, sp, #16
; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[2], [x8]
; CHECK-FP-NEXT: mov v0.h[5], v5.h[0] ; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
; CHECK-FP-NEXT: mov v0.h[6], v6.h[0] ; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[2], [x8]
; CHECK-FP-NEXT: mov v0.h[7], v7.h[0] ; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
; CHECK-FP-NEXT: fmaxnm v0.8h, v0.8h, v1.8h ; CHECK-FP-NEXT: fmaxnm v0.8h, v0.8h, v1.8h
; CHECK-FP-NEXT: fmaxnmv h0, v0.8h ; CHECK-FP-NEXT: fmaxnmv h0, v0.8h
; CHECK-FP-NEXT: ret ; CHECK-FP-NEXT: ret
%b = call nnan half @llvm.vector.reduce.fmax.v11f16(<11 x half> %a) %b = call nnan half @llvm.vector.reduce.fmax.v11f16(<11 x half> %a)
ret half %b ret half %b
} }
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; CHECK-NOFP-NEXT: fcvt s1, h1 ; CHECK-NOFP-NEXT: fcvt s1, h1
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1 ; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt h0, s0 ; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: ret ; CHECK-NOFP-NEXT: ret
; ;
; CHECK-FP-LABEL: test_v11f16_ninf: ; CHECK-FP-LABEL: test_v11f16_ninf:
; CHECK-FP: // %bb.0: ; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0 ; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-FP-NEXT: mov x8, sp
; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1 ; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2 ; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3 ; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4 ; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
; CHECK-FP-NEXT: mov x8, sp
; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5 ; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6 ; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7 ; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
; CHECK-FP-NEXT: mov v0.h[1], v1.h[0] ; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
; CHECK-FP-NEXT: mvni v1.8h, #4, lsl #8 ; CHECK-FP-NEXT: mvni v1.8h, #4, lsl #8
; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[0], [x8] ; CHECK-FP-NEXT: ld1 { v1.h }[0], [x8]
; CHECK-FP-NEXT: add x8, sp, #8 ; CHECK-FP-NEXT: add x8, sp, #8
; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[1], [x8]
; CHECK-FP-NEXT: add x8, sp, #16
; CHECK-FP-NEXT: mov v0.h[3], v3.h[0] ; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[2], [x8]
; CHECK-FP-NEXT: mov v0.h[4], v4.h[0] ; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[1], [x8]
; CHECK-FP-NEXT: add x8, sp, #16
; CHECK-FP-NEXT: mov v0.h[5], v5.h[0] ; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
; CHECK-FP-NEXT: mov v0.h[6], v6.h[0] ; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[2], [x8]
; CHECK-FP-NEXT: mov v0.h[7], v7.h[0] ; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
; CHECK-FP-NEXT: fmaxnm v0.8h, v0.8h, v1.8h ; CHECK-FP-NEXT: fmaxnm v0.8h, v0.8h, v1.8h
; CHECK-FP-NEXT: fmaxnmv h0, v0.8h ; CHECK-FP-NEXT: fmaxnmv h0, v0.8h
; CHECK-FP-NEXT: ret ; CHECK-FP-NEXT: ret
%b = call nnan ninf half @llvm.vector.reduce.fmax.v11f16(<11 x half> %a) %b = call nnan ninf half @llvm.vector.reduce.fmax.v11f16(<11 x half> %a)
ret half %b ret half %b
} }
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llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll

Show First 20 Lines • Show All 178 Lines • ▼ Show 20 Lines
; CHECK-NOFP-NEXT: fcvt s1, h1 ; CHECK-NOFP-NEXT: fcvt s1, h1
; CHECK-NOFP-NEXT: fminnm s0, s0, s1 ; CHECK-NOFP-NEXT: fminnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt h0, s0 ; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: ret ; CHECK-NOFP-NEXT: ret
; ;
; CHECK-FP-LABEL: test_v11f16: ; CHECK-FP-LABEL: test_v11f16:
; CHECK-FP: // %bb.0: ; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0 ; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-FP-NEXT: mov x8, sp
; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1 ; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2 ; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3 ; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4 ; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
; CHECK-FP-NEXT: mov x8, sp
; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5 ; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6 ; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7 ; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
; CHECK-FP-NEXT: mov v0.h[1], v1.h[0] ; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
; CHECK-FP-NEXT: movi v1.8h, #124, lsl #8 ; CHECK-FP-NEXT: movi v1.8h, #124, lsl #8
; CHECK-FP-NEXT: mov v0.h[2], v2.h[0] ; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[0], [x8] ; CHECK-FP-NEXT: ld1 { v1.h }[0], [x8]
; CHECK-FP-NEXT: add x8, sp, #8 ; CHECK-FP-NEXT: add x8, sp, #8
; CHECK-FP-NEXT: mov v0.h[3], v3.h[0] ; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[1], [x8] ; CHECK-FP-NEXT: ld1 { v1.h }[1], [x8]
; CHECK-FP-NEXT: add x8, sp, #16 ; CHECK-FP-NEXT: add x8, sp, #16
; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[2], [x8]
; CHECK-FP-NEXT: mov v0.h[5], v5.h[0] ; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
; CHECK-FP-NEXT: mov v0.h[6], v6.h[0] ; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[2], [x8]
; CHECK-FP-NEXT: mov v0.h[7], v7.h[0] ; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v1.8h ; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v1.8h
; CHECK-FP-NEXT: fminnmv h0, v0.8h ; CHECK-FP-NEXT: fminnmv h0, v0.8h
; CHECK-FP-NEXT: ret ; CHECK-FP-NEXT: ret
%b = call nnan half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a) %b = call nnan half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a)
ret half %b ret half %b
} }
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; CHECK-NOFP-NEXT: fcvt s1, h1 ; CHECK-NOFP-NEXT: fcvt s1, h1
; CHECK-NOFP-NEXT: fminnm s0, s0, s1 ; CHECK-NOFP-NEXT: fminnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt h0, s0 ; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: ret ; CHECK-NOFP-NEXT: ret
; ;
; CHECK-FP-LABEL: test_v11f16_ninf: ; CHECK-FP-LABEL: test_v11f16_ninf:
; CHECK-FP: // %bb.0: ; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0 ; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-FP-NEXT: mov x8, sp
; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1 ; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2 ; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3 ; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4 ; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
; CHECK-FP-NEXT: mov x8, sp
; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5 ; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6 ; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7 ; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
; CHECK-FP-NEXT: mov v0.h[1], v1.h[0] ; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
; CHECK-FP-NEXT: mvni v1.8h, #132, lsl #8 ; CHECK-FP-NEXT: mvni v1.8h, #132, lsl #8
; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[0], [x8] ; CHECK-FP-NEXT: ld1 { v1.h }[0], [x8]
; CHECK-FP-NEXT: add x8, sp, #8 ; CHECK-FP-NEXT: add x8, sp, #8
; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[1], [x8]
; CHECK-FP-NEXT: add x8, sp, #16
; CHECK-FP-NEXT: mov v0.h[3], v3.h[0] ; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[2], [x8]
; CHECK-FP-NEXT: mov v0.h[4], v4.h[0] ; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[1], [x8]
; CHECK-FP-NEXT: add x8, sp, #16
; CHECK-FP-NEXT: mov v0.h[5], v5.h[0] ; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
; CHECK-FP-NEXT: mov v0.h[6], v6.h[0] ; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
; CHECK-FP-NEXT: ld1 { v1.h }[2], [x8]
; CHECK-FP-NEXT: mov v0.h[7], v7.h[0] ; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v1.8h ; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v1.8h
; CHECK-FP-NEXT: fminnmv h0, v0.8h ; CHECK-FP-NEXT: fminnmv h0, v0.8h
; CHECK-FP-NEXT: ret ; CHECK-FP-NEXT: ret
%b = call nnan ninf half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a) %b = call nnan ninf half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a)
ret half %b ret half %b
} }
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/vector-fcopysign.ll

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
;============ v4f64 ;============ v4f64
; SplitVecRes mismatched ; SplitVecRes mismatched
define <4 x double> @test_copysign_v4f64_v4f32(<4 x double> %a, <4 x float> %b) #0 { define <4 x double> @test_copysign_v4f64_v4f32(<4 x double> %a, <4 x float> %b) #0 {
; CHECK-LABEL: test_copysign_v4f64_v4f32: ; CHECK-LABEL: test_copysign_v4f64_v4f32:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: movi.2d v3, #0xffffffffffffffff ; CHECK-NEXT: movi.2d v3, #0xffffffffffffffff
; CHECK-NEXT: fcvtl2 v4.2d, v2.4s ; CHECK-NEXT: fcvtl2 v4.2d, v2.4s
; CHECK-NEXT: fcvtl v2.2d, v2.2s
; CHECK-NEXT: fneg.2d v3, v3 ; CHECK-NEXT: fneg.2d v3, v3
; CHECK-NEXT: fcvtl v2.2d, v2.2s
; CHECK-NEXT: bif.16b v1, v4, v3 ; CHECK-NEXT: bif.16b v1, v4, v3
; CHECK-NEXT: bif.16b v0, v2, v3 ; CHECK-NEXT: bif.16b v0, v2, v3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = fpext <4 x float> %b to <4 x double> %tmp0 = fpext <4 x float> %b to <4 x double>
%r = call <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %tmp0) %r = call <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %tmp0)
ret <4 x double> %r ret <4 x double> %r
} }
Show All 14 Lines
;============ v4f16 ;============ v4f16
define <4 x half> @test_copysign_v4f16_v4f16(<4 x half> %a, <4 x half> %b) #0 { define <4 x half> @test_copysign_v4f16_v4f16(<4 x half> %a, <4 x half> %b) #0 {
; NOFP16-LABEL: test_copysign_v4f16_v4f16: ; NOFP16-LABEL: test_copysign_v4f16_v4f16:
; NOFP16: ; %bb.0: ; NOFP16: ; %bb.0:
; NOFP16-NEXT: ; kill: def $d1 killed $d1 def $q1 ; NOFP16-NEXT: ; kill: def $d1 killed $d1 def $q1
; NOFP16-NEXT: ; kill: def $d0 killed $d0 def $q0 ; NOFP16-NEXT: ; kill: def $d0 killed $d0 def $q0
; NOFP16-NEXT: mov h3, v1[1] ; NOFP16-NEXT: fcvt s3, h1
; NOFP16-NEXT: mov h4, v0[1] ; NOFP16-NEXT: fcvt s4, h0
; NOFP16-NEXT: fcvt s5, h1 ; NOFP16-NEXT: mov h5, v1[1]
; NOFP16-NEXT: fcvt s6, h0 ; NOFP16-NEXT: mov h6, v0[1]
; NOFP16-NEXT: mov h7, v1[2]
; NOFP16-NEXT: mov h16, v0[2]
; NOFP16-NEXT: mvni.4s v2, #128, lsl #24 ; NOFP16-NEXT: mvni.4s v2, #128, lsl #24
; NOFP16-NEXT: mov h7, v0[2]
; NOFP16-NEXT: mov h0, v0[3]
; NOFP16-NEXT: bit.16b v3, v4, v2
; NOFP16-NEXT: mov h4, v1[2]
; NOFP16-NEXT: fcvt s5, h5
; NOFP16-NEXT: fcvt s6, h6
; NOFP16-NEXT: mov h1, v1[3] ; NOFP16-NEXT: mov h1, v1[3]
; NOFP16-NEXT: fcvt s3, h3 ; NOFP16-NEXT: fcvt s7, h7
; NOFP16-NEXT: fcvt s4, h4 ; NOFP16-NEXT: fcvt s4, h4
; NOFP16-NEXT: bit.16b v5, v6, v2 ; NOFP16-NEXT: bit.16b v5, v6, v2
; NOFP16-NEXT: fcvt s6, h7
; NOFP16-NEXT: fcvt s7, h16
; NOFP16-NEXT: fcvt s1, h1 ; NOFP16-NEXT: fcvt s1, h1
; NOFP16-NEXT: bit.16b v3, v4, v2 ; NOFP16-NEXT: fcvt s6, h0
; NOFP16-NEXT: mov h4, v0[3] ; NOFP16-NEXT: bit.16b v4, v7, v2
; NOFP16-NEXT: fcvt h0, s5 ; NOFP16-NEXT: fcvt h0, s3
; NOFP16-NEXT: bit.16b v6, v7, v2 ; NOFP16-NEXT: fcvt h3, s5
; NOFP16-NEXT: fcvt h3, s3 ; NOFP16-NEXT: bit.16b v1, v6, v2
; NOFP16-NEXT: fcvt s4, h4 ; NOFP16-NEXT: fcvt h2, s4
; NOFP16-NEXT: fcvt h5, s6
; NOFP16-NEXT: mov.h v0[1], v3[0] ; NOFP16-NEXT: mov.h v0[1], v3[0]
; NOFP16-NEXT: bit.16b v1, v4, v2
; NOFP16-NEXT: mov.h v0[2], v5[0]
; NOFP16-NEXT: fcvt h1, s1 ; NOFP16-NEXT: fcvt h1, s1
; NOFP16-NEXT: mov.h v0[2], v2[0]
; NOFP16-NEXT: mov.h v0[3], v1[0] ; NOFP16-NEXT: mov.h v0[3], v1[0]
; NOFP16-NEXT: ; kill: def $d0 killed $d0 killed $q0 ; NOFP16-NEXT: ; kill: def $d0 killed $d0 killed $q0
; NOFP16-NEXT: ret ; NOFP16-NEXT: ret
; ;
; FP16-LABEL: test_copysign_v4f16_v4f16: ; FP16-LABEL: test_copysign_v4f16_v4f16:
; FP16: ; %bb.0: ; FP16: ; %bb.0:
; FP16-NEXT: mvni.4h v2, #128, lsl #8 ; FP16-NEXT: mvni.4h v2, #128, lsl #8
; FP16-NEXT: bif.8b v0, v1, v2 ; FP16-NEXT: bif.8b v0, v1, v2
; FP16-NEXT: ret ; FP16-NEXT: ret
%r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %b) %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %b)
ret <4 x half> %r ret <4 x half> %r
} }
define <4 x half> @test_copysign_v4f16_v4f32(<4 x half> %a, <4 x float> %b) #0 { define <4 x half> @test_copysign_v4f16_v4f32(<4 x half> %a, <4 x float> %b) #0 {
; NOFP16-LABEL: test_copysign_v4f16_v4f32: ; NOFP16-LABEL: test_copysign_v4f16_v4f32:
; NOFP16: ; %bb.0: ; NOFP16: ; %bb.0:
; NOFP16-NEXT: fcvtn v1.4h, v1.4s ; NOFP16-NEXT: fcvtn v1.4h, v1.4s
; NOFP16-NEXT: ; kill: def $d0 killed $d0 def $q0 ; NOFP16-NEXT: ; kill: def $d0 killed $d0 def $q0
; NOFP16-NEXT: mov h3, v0[1] ; NOFP16-NEXT: fcvt s3, h0
; NOFP16-NEXT: fcvt s5, h0 ; NOFP16-NEXT: mov h5, v0[1]
; NOFP16-NEXT: mov h7, v0[2]
; NOFP16-NEXT: mvni.4s v2, #128, lsl #24 ; NOFP16-NEXT: mvni.4s v2, #128, lsl #24
; NOFP16-NEXT: mov h4, v1[1] ; NOFP16-NEXT: fcvt s4, h1
; NOFP16-NEXT: fcvt s6, h1 ; NOFP16-NEXT: mov h6, v1[1]
; NOFP16-NEXT: mov h16, v1[2] ; NOFP16-NEXT: mov h7, v1[2]
; NOFP16-NEXT: fcvt s3, h3 ; NOFP16-NEXT: fcvt s5, h5
; NOFP16-NEXT: mov h1, v1[3] ; NOFP16-NEXT: mov h1, v1[3]
; NOFP16-NEXT: fcvt s4, h4
; NOFP16-NEXT: bif.16b v5, v6, v2
; NOFP16-NEXT: fcvt s6, h7
; NOFP16-NEXT: fcvt s7, h16
; NOFP16-NEXT: fcvt s1, h1
; NOFP16-NEXT: bif.16b v3, v4, v2 ; NOFP16-NEXT: bif.16b v3, v4, v2
; NOFP16-NEXT: mov h4, v0[3] ; NOFP16-NEXT: mov h4, v0[2]
; NOFP16-NEXT: fcvt h0, s5 ; NOFP16-NEXT: fcvt s6, h6
; NOFP16-NEXT: bif.16b v6, v7, v2 ; NOFP16-NEXT: mov h0, v0[3]
; NOFP16-NEXT: fcvt h3, s3 ; NOFP16-NEXT: fcvt s7, h7
; NOFP16-NEXT: fcvt s1, h1
; NOFP16-NEXT: fcvt s4, h4 ; NOFP16-NEXT: fcvt s4, h4
; NOFP16-NEXT: fcvt h5, s6 ; NOFP16-NEXT: bif.16b v5, v6, v2
; NOFP16-NEXT: fcvt s6, h0
; NOFP16-NEXT: fcvt h0, s3
; NOFP16-NEXT: fcvt h3, s5
; NOFP16-NEXT: bif.16b v4, v7, v2
; NOFP16-NEXT: bit.16b v1, v6, v2
; NOFP16-NEXT: fcvt h2, s4
; NOFP16-NEXT: mov.h v0[1], v3[0] ; NOFP16-NEXT: mov.h v0[1], v3[0]
; NOFP16-NEXT: bit.16b v1, v4, v2
; NOFP16-NEXT: mov.h v0[2], v5[0]
; NOFP16-NEXT: fcvt h1, s1 ; NOFP16-NEXT: fcvt h1, s1
; NOFP16-NEXT: mov.h v0[2], v2[0]
; NOFP16-NEXT: mov.h v0[3], v1[0] ; NOFP16-NEXT: mov.h v0[3], v1[0]
; NOFP16-NEXT: ; kill: def $d0 killed $d0 killed $q0 ; NOFP16-NEXT: ; kill: def $d0 killed $d0 killed $q0
; NOFP16-NEXT: ret ; NOFP16-NEXT: ret
; ;
; FP16-LABEL: test_copysign_v4f16_v4f32: ; FP16-LABEL: test_copysign_v4f16_v4f32:
; FP16: ; %bb.0: ; FP16: ; %bb.0:
; FP16-NEXT: fcvtn v1.4h, v1.4s ; FP16-NEXT: fcvtn v1.4h, v1.4s
; FP16-NEXT: mvni.4h v2, #128, lsl #8 ; FP16-NEXT: mvni.4h v2, #128, lsl #8
; FP16-NEXT: bif.8b v0, v1, v2 ; FP16-NEXT: bif.8b v0, v1, v2
; FP16-NEXT: ret ; FP16-NEXT: ret
%tmp0 = fptrunc <4 x float> %b to <4 x half> %tmp0 = fptrunc <4 x float> %b to <4 x half>
%r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %tmp0) %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %tmp0)
ret <4 x half> %r ret <4 x half> %r
} }
define <4 x half> @test_copysign_v4f16_v4f64(<4 x half> %a, <4 x double> %b) #0 { define <4 x half> @test_copysign_v4f16_v4f64(<4 x half> %a, <4 x double> %b) #0 {
; NOFP16-LABEL: test_copysign_v4f16_v4f64: ; NOFP16-LABEL: test_copysign_v4f16_v4f64:
; NOFP16: ; %bb.0: ; NOFP16: ; %bb.0:
; NOFP16-NEXT: ; kill: def $d0 killed $d0 def $q0 ; NOFP16-NEXT: ; kill: def $d0 killed $d0 def $q0
; NOFP16-NEXT: mov d4, v1[1] ; NOFP16-NEXT: mov d4, v1[1]
; NOFP16-NEXT: mov h5, v0[1] ; NOFP16-NEXT: mov h5, v0[1]
; NOFP16-NEXT: fcvt s1, d1 ; NOFP16-NEXT: fcvt s1, d1
; NOFP16-NEXT: fcvt s6, h0 ; NOFP16-NEXT: fcvt s6, h0
; NOFP16-NEXT: mov h7, v0[2] ; NOFP16-NEXT: mov h7, v0[2]
; NOFP16-NEXT: mov h0, v0[3]
; NOFP16-NEXT: mvni.4s v3, #128, lsl #24 ; NOFP16-NEXT: mvni.4s v3, #128, lsl #24
; NOFP16-NEXT: fcvt s4, d4 ; NOFP16-NEXT: fcvt s4, d4
; NOFP16-NEXT: fcvt s5, h5 ; NOFP16-NEXT: fcvt s5, h5
; NOFP16-NEXT: bit.16b v1, v6, v3 ; NOFP16-NEXT: bit.16b v1, v6, v3
; NOFP16-NEXT: fcvt s6, d2 ; NOFP16-NEXT: mov d6, v2[1]
; NOFP16-NEXT: fcvt s2, d2
; NOFP16-NEXT: fcvt s7, h7 ; NOFP16-NEXT: fcvt s7, h7
; NOFP16-NEXT: mov d2, v2[1]
; NOFP16-NEXT: bit.16b v4, v5, v3 ; NOFP16-NEXT: bit.16b v4, v5, v3
; NOFP16-NEXT: mov h5, v0[3] ; NOFP16-NEXT: fcvt s5, d6
; NOFP16-NEXT: fcvt s6, h0
; NOFP16-NEXT: fcvt h0, s1 ; NOFP16-NEXT: fcvt h0, s1
; NOFP16-NEXT: bit.16b v6, v7, v3 ; NOFP16-NEXT: bit.16b v2, v7, v3
; NOFP16-NEXT: fcvt s2, d2
; NOFP16-NEXT: fcvt h1, s4 ; NOFP16-NEXT: fcvt h1, s4
; NOFP16-NEXT: fcvt s4, h5 ; NOFP16-NEXT: fcvt h2, s2
; NOFP16-NEXT: fcvt h5, s6 ; NOFP16-NEXT: bsl.16b v3, v6, v5
; NOFP16-NEXT: mov.h v0[1], v1[0] ; NOFP16-NEXT: mov.h v0[1], v1[0]
; NOFP16-NEXT: mov.16b v1, v3 ; NOFP16-NEXT: fcvt h1, s3
; NOFP16-NEXT: bsl.16b v1, v4, v2 ; NOFP16-NEXT: mov.h v0[2], v2[0]
; NOFP16-NEXT: mov.h v0[2], v5[0]
; NOFP16-NEXT: fcvt h1, s1
; NOFP16-NEXT: mov.h v0[3], v1[0] ; NOFP16-NEXT: mov.h v0[3], v1[0]
; NOFP16-NEXT: ; kill: def $d0 killed $d0 killed $q0 ; NOFP16-NEXT: ; kill: def $d0 killed $d0 killed $q0
; NOFP16-NEXT: ret ; NOFP16-NEXT: ret
; ;
; FP16-LABEL: test_copysign_v4f16_v4f64: ; FP16-LABEL: test_copysign_v4f16_v4f64:
; FP16: ; %bb.0: ; FP16: ; %bb.0:
; FP16-NEXT: mov d3, v1[1] ; FP16-NEXT: mov d3, v1[1]
; FP16-NEXT: fcvt h1, d1 ; FP16-NEXT: fcvt h1, d1
; FP16-NEXT: mov d4, v2[1]
; FP16-NEXT: fcvt h2, d2
; FP16-NEXT: fcvt h3, d3 ; FP16-NEXT: fcvt h3, d3
; FP16-NEXT: mov.h v1[1], v3[0] ; FP16-NEXT: mov.h v1[1], v3[0]
; FP16-NEXT: fcvt h3, d2 ; FP16-NEXT: fcvt h3, d4
; FP16-NEXT: mov d2, v2[1] ; FP16-NEXT: mov.h v1[2], v2[0]
; FP16-NEXT: mov.h v1[2], v3[0]
; FP16-NEXT: fcvt h2, d2
; FP16-NEXT: mov.h v1[3], v2[0]
; FP16-NEXT: mvni.4h v2, #128, lsl #8 ; FP16-NEXT: mvni.4h v2, #128, lsl #8
; FP16-NEXT: mov.h v1[3], v3[0]
; FP16-NEXT: bif.8b v0, v1, v2 ; FP16-NEXT: bif.8b v0, v1, v2
; FP16-NEXT: ret ; FP16-NEXT: ret
%tmp0 = fptrunc <4 x double> %b to <4 x half> %tmp0 = fptrunc <4 x double> %b to <4 x half>
%r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %tmp0) %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %tmp0)
ret <4 x half> %r ret <4 x half> %r
} }
declare <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %b) #0 declare <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %b) #0
;============ v8f16 ;============ v8f16
define <8 x half> @test_copysign_v8f16_v8f16(<8 x half> %a, <8 x half> %b) #0 { define <8 x half> @test_copysign_v8f16_v8f16(<8 x half> %a, <8 x half> %b) #0 {
; NOFP16-LABEL: test_copysign_v8f16_v8f16: ; NOFP16-LABEL: test_copysign_v8f16_v8f16:
; NOFP16: ; %bb.0: ; NOFP16: ; %bb.0:
; NOFP16-NEXT: mov h5, v1[1] ; NOFP16-NEXT: mov h3, v1[1]
; NOFP16-NEXT: mov h6, v0[1] ; NOFP16-NEXT: mov h4, v0[1]
; NOFP16-NEXT: fcvt s2, h1
; NOFP16-NEXT: fcvt s4, h0
; NOFP16-NEXT: mov h7, v1[2] ; NOFP16-NEXT: mov h7, v1[2]
; NOFP16-NEXT: mov h16, v0[2] ; NOFP16-NEXT: mov h16, v0[2]
; NOFP16-NEXT: mvni.4s v3, #128, lsl #24 ; NOFP16-NEXT: mov h17, v1[3]
; NOFP16-NEXT: mov h17, v0[3] ; NOFP16-NEXT: mov h18, v0[3]
; NOFP16-NEXT: fcvt s5, h5 ; NOFP16-NEXT: fcvt s5, h1
; NOFP16-NEXT: fcvt s6, h6 ; NOFP16-NEXT: fcvt s6, h0
; NOFP16-NEXT: mov h18, v0[5] ; NOFP16-NEXT: fcvt s3, h3
; NOFP16-NEXT: bit.16b v2, v4, v3 ; NOFP16-NEXT: fcvt s4, h4
; NOFP16-NEXT: mov h4, v1[3] ; NOFP16-NEXT: mov h19, v1[4]
; NOFP16-NEXT: mov h20, v0[4]
; NOFP16-NEXT: fcvt s7, h7 ; NOFP16-NEXT: fcvt s7, h7
; NOFP16-NEXT: fcvt s16, h16 ; NOFP16-NEXT: fcvt s16, h16
; NOFP16-NEXT: fcvt s17, h17 ; NOFP16-NEXT: fcvt s17, h17
; NOFP16-NEXT: bit.16b v5, v6, v3 ; NOFP16-NEXT: fcvt s18, h18
; NOFP16-NEXT: mov.16b v6, v3 ; NOFP16-NEXT: mvni.4s v2, #128, lsl #24
; NOFP16-NEXT: fcvt s4, h4 ; NOFP16-NEXT: bit.16b v5, v6, v2
; NOFP16-NEXT: bsl.16b v6, v16, v7 ; NOFP16-NEXT: bit.16b v3, v4, v2
; NOFP16-NEXT: mov h7, v1[4] ; NOFP16-NEXT: mov.16b v4, v2
; NOFP16-NEXT: mov h16, v0[4] ; NOFP16-NEXT: mov.16b v6, v2
; NOFP16-NEXT: fcvt h2, s2 ; NOFP16-NEXT: bsl.16b v4, v16, v7
; NOFP16-NEXT: fcvt h5, s5 ; NOFP16-NEXT: bsl.16b v6, v18, v17
; NOFP16-NEXT: bit.16b v4, v17, v3 ; NOFP16-NEXT: fcvt s7, h19
; NOFP16-NEXT: fcvt s16, h20
; NOFP16-NEXT: mov h17, v1[5] ; NOFP16-NEXT: mov h17, v1[5]
; NOFP16-NEXT: fcvt s7, h7 ; NOFP16-NEXT: mov h18, v0[5]
; NOFP16-NEXT: fcvt s16, h16 ; NOFP16-NEXT: mov h19, v1[6]
; NOFP16-NEXT: mov.h v2[1], v5[0] ; NOFP16-NEXT: mov h20, v0[6]
; NOFP16-NEXT: fcvt h5, s6
; NOFP16-NEXT: fcvt s6, h17
; NOFP16-NEXT: fcvt s17, h18
; NOFP16-NEXT: fcvt h4, s4
; NOFP16-NEXT: bit.16b v7, v16, v3
; NOFP16-NEXT: mov h16, v0[6]
; NOFP16-NEXT: mov.h v2[2], v5[0]
; NOFP16-NEXT: mov h5, v1[6]
; NOFP16-NEXT: bit.16b v6, v17, v3
; NOFP16-NEXT: mov h1, v1[7] ; NOFP16-NEXT: mov h1, v1[7]
; NOFP16-NEXT: fcvt s16, h16
; NOFP16-NEXT: mov.h v2[3], v4[0]
; NOFP16-NEXT: fcvt h4, s7
; NOFP16-NEXT: fcvt s5, h5
; NOFP16-NEXT: mov h0, v0[7] ; NOFP16-NEXT: mov h0, v0[7]
; NOFP16-NEXT: fcvt h3, s3
; NOFP16-NEXT: bit.16b v7, v16, v2
; NOFP16-NEXT: fcvt s16, h17
; NOFP16-NEXT: fcvt s17, h18
; NOFP16-NEXT: fcvt s18, h19
; NOFP16-NEXT: fcvt s19, h20
; NOFP16-NEXT: fcvt s1, h1 ; NOFP16-NEXT: fcvt s1, h1
; NOFP16-NEXT: mov.h v2[4], v4[0] ; NOFP16-NEXT: bit.16b v16, v17, v2
; NOFP16-NEXT: fcvt h4, s6 ; NOFP16-NEXT: mov.16b v17, v2
; NOFP16-NEXT: bit.16b v5, v16, v3 ; NOFP16-NEXT: bsl.16b v17, v19, v18
; NOFP16-NEXT: fcvt s0, h0 ; NOFP16-NEXT: fcvt s18, h0
; NOFP16-NEXT: mov.h v2[5], v4[0] ; NOFP16-NEXT: fcvt h0, s5
; NOFP16-NEXT: fcvt h5, s5 ; NOFP16-NEXT: bit.16b v1, v18, v2
; NOFP16-NEXT: bif.16b v0, v1, v3 ; NOFP16-NEXT: fcvt h2, s4
; NOFP16-NEXT: mov.h v2[6], v5[0] ; NOFP16-NEXT: mov.h v0[1], v3[0]
; NOFP16-NEXT: fcvt h0, s0 ; NOFP16-NEXT: fcvt h3, s6
; NOFP16-NEXT: mov.h v2[7], v0[0] ; NOFP16-NEXT: fcvt h1, s1
; NOFP16-NEXT: mov.16b v0, v2 ; NOFP16-NEXT: mov.h v0[2], v2[0]
; NOFP16-NEXT: fcvt h2, s7
; NOFP16-NEXT: mov.h v0[3], v3[0]
; NOFP16-NEXT: fcvt h3, s16
; NOFP16-NEXT: mov.h v0[4], v2[0]
; NOFP16-NEXT: fcvt h2, s17
; NOFP16-NEXT: mov.h v0[5], v3[0]
; NOFP16-NEXT: mov.h v0[6], v2[0]
; NOFP16-NEXT: mov.h v0[7], v1[0]
; NOFP16-NEXT: ret ; NOFP16-NEXT: ret
; ;
; FP16-LABEL: test_copysign_v8f16_v8f16: ; FP16-LABEL: test_copysign_v8f16_v8f16:
; FP16: ; %bb.0: ; FP16: ; %bb.0:
; FP16-NEXT: mvni.8h v2, #128, lsl #8 ; FP16-NEXT: mvni.8h v2, #128, lsl #8
; FP16-NEXT: bif.16b v0, v1, v2 ; FP16-NEXT: bif.16b v0, v1, v2
; FP16-NEXT: ret ; FP16-NEXT: ret
%r = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %b) %r = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %b)
ret <8 x half> %r ret <8 x half> %r
} }
define <8 x half> @test_copysign_v8f16_v8f32(<8 x half> %a, <8 x float> %b) #0 { define <8 x half> @test_copysign_v8f16_v8f32(<8 x half> %a, <8 x float> %b) #0 {
; NOFP16-LABEL: test_copysign_v8f16_v8f32: ; NOFP16-LABEL: test_copysign_v8f16_v8f32:
; NOFP16: ; %bb.0: ; NOFP16: ; %bb.0:
; NOFP16-NEXT: fcvtn v1.4h, v1.4s ; NOFP16-NEXT: fcvtn v1.4h, v1.4s
; NOFP16-NEXT: fcvt s4, h0
; NOFP16-NEXT: fcvtn v2.4h, v2.4s ; NOFP16-NEXT: fcvtn v2.4h, v2.4s
; NOFP16-NEXT: mov h4, v0[1] ; NOFP16-NEXT: mov h6, v0[1]
; NOFP16-NEXT: mov h5, v0[4] ; NOFP16-NEXT: mov h7, v0[4]
; NOFP16-NEXT: fcvt s7, h0 ; NOFP16-NEXT: mov h16, v0[2]
; NOFP16-NEXT: mov h17, v0[2]
; NOFP16-NEXT: mvni.4s v3, #128, lsl #24 ; NOFP16-NEXT: mvni.4s v3, #128, lsl #24
; NOFP16-NEXT: mov h6, v1[1] ; NOFP16-NEXT: mov h19, v0[3]
; NOFP16-NEXT: fcvt s16, h1 ; NOFP16-NEXT: fcvt s5, h1
; NOFP16-NEXT: fcvt s4, h4 ; NOFP16-NEXT: mov h17, v1[1]
; NOFP16-NEXT: mov h18, v1[2] ; NOFP16-NEXT: fcvt s18, h2
; NOFP16-NEXT: fcvt s5, h5 ; NOFP16-NEXT: fcvt s7, h7
; NOFP16-NEXT: fcvt s17, h17
; NOFP16-NEXT: fcvt s6, h6
; NOFP16-NEXT: bif.16b v7, v16, v3
; NOFP16-NEXT: fcvt s16, h2
; NOFP16-NEXT: fcvt s18, h18
; NOFP16-NEXT: bif.16b v4, v6, v3
; NOFP16-NEXT: mov h6, v0[3]
; NOFP16-NEXT: bif.16b v5, v16, v3
; NOFP16-NEXT: mov h16, v1[3]
; NOFP16-NEXT: fcvt h1, s7
; NOFP16-NEXT: mov.16b v7, v3
; NOFP16-NEXT: fcvt h4, s4
; NOFP16-NEXT: bsl.16b v7, v17, v18
; NOFP16-NEXT: fcvt s6, h6 ; NOFP16-NEXT: fcvt s6, h6
; NOFP16-NEXT: fcvt s16, h16 ; NOFP16-NEXT: fcvt s16, h16
; NOFP16-NEXT: mov h17, v0[5] ; NOFP16-NEXT: fcvt s19, h19
; NOFP16-NEXT: bif.16b v4, v5, v3
; NOFP16-NEXT: mov h5, v1[2]
; NOFP16-NEXT: fcvt s17, h17
; NOFP16-NEXT: mov h1, v1[3]
; NOFP16-NEXT: bif.16b v7, v18, v3
; NOFP16-NEXT: mov h18, v2[1] ; NOFP16-NEXT: mov h18, v2[1]
; NOFP16-NEXT: fcvt h5, s5 ; NOFP16-NEXT: fcvt s5, h5
; NOFP16-NEXT: mov.h v1[1], v4[0] ; NOFP16-NEXT: bif.16b v6, v17, v3
; NOFP16-NEXT: fcvt h4, s7 ; NOFP16-NEXT: mov h17, v0[5]
; NOFP16-NEXT: bif.16b v6, v16, v3 ; NOFP16-NEXT: fcvt s1, h1
; NOFP16-NEXT: fcvt s7, h17 ; NOFP16-NEXT: bit.16b v5, v16, v3
; NOFP16-NEXT: fcvt s16, h17
; NOFP16-NEXT: fcvt s17, h18 ; NOFP16-NEXT: fcvt s17, h18
; NOFP16-NEXT: mov.h v1[2], v4[0] ; NOFP16-NEXT: mov.16b v18, v3
; NOFP16-NEXT: mov h4, v0[6] ; NOFP16-NEXT: bsl.16b v18, v19, v1
; NOFP16-NEXT: mov h16, v2[2] ; NOFP16-NEXT: fcvt h1, s4
; NOFP16-NEXT: fcvt h6, s6 ; NOFP16-NEXT: fcvt h4, s6
; NOFP16-NEXT: mov h6, v0[6]
; NOFP16-NEXT: bif.16b v16, v17, v3
; NOFP16-NEXT: mov h17, v2[2]
; NOFP16-NEXT: mov h0, v0[7] ; NOFP16-NEXT: mov h0, v0[7]
; NOFP16-NEXT: bif.16b v7, v17, v3
; NOFP16-NEXT: mov h2, v2[3] ; NOFP16-NEXT: mov h2, v2[3]
; NOFP16-NEXT: fcvt s4, h4 ; NOFP16-NEXT: mov.h v1[1], v4[0]
; NOFP16-NEXT: fcvt s16, h16 ; NOFP16-NEXT: fcvt h4, s5
; NOFP16-NEXT: mov.h v1[3], v6[0] ; NOFP16-NEXT: fcvt s5, h6
; NOFP16-NEXT: fcvt s6, h17
; NOFP16-NEXT: fcvt s0, h0 ; NOFP16-NEXT: fcvt s0, h0
; NOFP16-NEXT: fcvt s2, h2 ; NOFP16-NEXT: fcvt s2, h2
; NOFP16-NEXT: bif.16b v4, v16, v3 ; NOFP16-NEXT: mov.h v1[2], v4[0]
; NOFP16-NEXT: mov.h v1[4], v5[0] ; NOFP16-NEXT: fcvt h4, s18
; NOFP16-NEXT: fcvt h5, s7 ; NOFP16-NEXT: bif.16b v5, v6, v3
; NOFP16-NEXT: fcvt h6, s7
; NOFP16-NEXT: bif.16b v0, v2, v3 ; NOFP16-NEXT: bif.16b v0, v2, v3
; NOFP16-NEXT: fcvt h4, s4 ; NOFP16-NEXT: fcvt h2, s5
; NOFP16-NEXT: mov.h v1[5], v5[0] ; NOFP16-NEXT: mov.h v1[3], v4[0]
; NOFP16-NEXT: fcvt h4, s16
; NOFP16-NEXT: fcvt h0, s0 ; NOFP16-NEXT: fcvt h0, s0
; NOFP16-NEXT: mov.h v1[6], v4[0] ; NOFP16-NEXT: mov.h v1[4], v6[0]
; NOFP16-NEXT: mov.h v1[5], v4[0]
; NOFP16-NEXT: mov.h v1[6], v2[0]
; NOFP16-NEXT: mov.h v1[7], v0[0] ; NOFP16-NEXT: mov.h v1[7], v0[0]
; NOFP16-NEXT: mov.16b v0, v1 ; NOFP16-NEXT: mov.16b v0, v1
; NOFP16-NEXT: ret ; NOFP16-NEXT: ret
; ;
; FP16-LABEL: test_copysign_v8f16_v8f32: ; FP16-LABEL: test_copysign_v8f16_v8f32:
; FP16: ; %bb.0: ; FP16: ; %bb.0:
; FP16-NEXT: fcvtn v2.4h, v2.4s ; FP16-NEXT: fcvtn v2.4h, v2.4s
; FP16-NEXT: fcvtn v1.4h, v1.4s ; FP16-NEXT: fcvtn v1.4h, v1.4s
Show All 12 Lines

llvm/test/CodeGen/AArch64/vector-gep.ll

; RUN: llc < %s -mtriple=arm64_32-apple-watchos2.0.0 --aarch64-neon-syntax=generic | FileCheck %s ; RUN: llc < %s -mtriple=arm64_32-apple-watchos2.0.0 --aarch64-neon-syntax=generic | FileCheck %s
target datalayout = "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128"
target triple = "arm64_32-apple-watchos2.0.0" target triple = "arm64_32-apple-watchos2.0.0"
; CHECK-LABEL: lCPI0_0: ; CHECK-LABEL: lCPI0_0:
; CHECK-NEXT: .quad 36 ; CHECK-NEXT: .quad 36
; CHECK-NEXT: .quad 4804 ; CHECK-NEXT: .quad 4804
define <2 x i8*> @vector_gep(<2 x i8*> %0) { define <2 x i8*> @vector_gep(<2 x i8*> %0) {
; CHECK-LABEL: vector_gep: ; CHECK-LABEL: vector_gep:
; CHECK: adrp x[[REG8:[123]?[0-9]]], lCPI0_0@PAGE ; CHECK: adrp x[[REG8:[123]?[0-9]]], lCPI0_0@PAGE
; CHECK: movi v[[REG1:[0-9]+]].2d, #0x000000ffffffff
; CHECK: ldr q[[REG2:[0-9]+]], [x[[REG8]], lCPI0_0@PAGEOFF] ; CHECK: ldr q[[REG2:[0-9]+]], [x[[REG8]], lCPI0_0@PAGEOFF]
; CHECK: add v[[REG0:[0-9]+]].2d, v[[REG0]].2d, v[[REG2]].2d ; CHECK: add v[[REG0:[0-9]+]].2d, v[[REG0]].2d, v[[REG2]].2d
; CHECK: movi v[[REG1:[0-9]+]].2d, #0x000000ffffffff
; CHECK: and v[[REG0]].16b, v[[REG0]].16b, v[[REG1]].16b ; CHECK: and v[[REG0]].16b, v[[REG0]].16b, v[[REG1]].16b
; CHECK: ret ; CHECK: ret
entry: entry:
%1 = getelementptr i8, <2 x i8*> %0, <2 x i32> <i32 36, i32 4804> %1 = getelementptr i8, <2 x i8*> %0, <2 x i32> <i32 36, i32 4804>
ret <2 x i8*> %1 ret <2 x i8*> %1
} }

llvm/test/CodeGen/AArch64/vector-popcnt-128-ult-ugt.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown- | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-unknown- | FileCheck %s
define <16 x i8> @ugt_1_v16i8(<16 x i8> %0) { define <16 x i8> @ugt_1_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ugt_1_v16i8: ; CHECK-LABEL: ugt_1_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.16b, #1
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: movi v1.16b, #1
; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b ; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
%3 = icmp ugt <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> %3 = icmp ugt <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
%4 = sext <16 x i1> %3 to <16 x i8> %4 = sext <16 x i1> %3 to <16 x i8>
ret <16 x i8> %4 ret <16 x i8> %4
} }
define <16 x i8> @ult_2_v16i8(<16 x i8> %0) { define <16 x i8> @ult_2_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ult_2_v16i8: ; CHECK-LABEL: ult_2_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.16b, #2
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: movi v1.16b, #2
; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b ; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
%3 = icmp ult <16 x i8> %2, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> %3 = icmp ult <16 x i8> %2, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
%4 = sext <16 x i1> %3 to <16 x i8> %4 = sext <16 x i1> %3 to <16 x i8>
ret <16 x i8> %4 ret <16 x i8> %4
} }
define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) { define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ugt_2_v16i8: ; CHECK-LABEL: ugt_2_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.16b, #2
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: movi v1.16b, #2
; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b ; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
%3 = icmp ugt <16 x i8> %2, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> %3 = icmp ugt <16 x i8> %2, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
%4 = sext <16 x i1> %3 to <16 x i8> %4 = sext <16 x i1> %3 to <16 x i8>
ret <16 x i8> %4 ret <16 x i8> %4
} }
define <16 x i8> @ult_3_v16i8(<16 x i8> %0) { define <16 x i8> @ult_3_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ult_3_v16i8: ; CHECK-LABEL: ult_3_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.16b, #3
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: movi v1.16b, #3
; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b ; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
%3 = icmp ult <16 x i8> %2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %3 = icmp ult <16 x i8> %2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
%4 = sext <16 x i1> %3 to <16 x i8> %4 = sext <16 x i1> %3 to <16 x i8>
ret <16 x i8> %4 ret <16 x i8> %4
} }
define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) { define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ugt_3_v16i8: ; CHECK-LABEL: ugt_3_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.16b, #3
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: movi v1.16b, #3
; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b ; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
%3 = icmp ugt <16 x i8> %2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %3 = icmp ugt <16 x i8> %2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
%4 = sext <16 x i1> %3 to <16 x i8> %4 = sext <16 x i1> %3 to <16 x i8>
ret <16 x i8> %4 ret <16 x i8> %4
} }
define <16 x i8> @ult_4_v16i8(<16 x i8> %0) { define <16 x i8> @ult_4_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ult_4_v16i8: ; CHECK-LABEL: ult_4_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.16b, #4
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: movi v1.16b, #4
; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b ; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
%3 = icmp ult <16 x i8> %2, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> %3 = icmp ult <16 x i8> %2, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
%4 = sext <16 x i1> %3 to <16 x i8> %4 = sext <16 x i1> %3 to <16 x i8>
ret <16 x i8> %4 ret <16 x i8> %4
} }
define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) { define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ugt_4_v16i8: ; CHECK-LABEL: ugt_4_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.16b, #4
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: movi v1.16b, #4
; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b ; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
%3 = icmp ugt <16 x i8> %2, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> %3 = icmp ugt <16 x i8> %2, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
%4 = sext <16 x i1> %3 to <16 x i8> %4 = sext <16 x i1> %3 to <16 x i8>
ret <16 x i8> %4 ret <16 x i8> %4
} }
define <16 x i8> @ult_5_v16i8(<16 x i8> %0) { define <16 x i8> @ult_5_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ult_5_v16i8: ; CHECK-LABEL: ult_5_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.16b, #5
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: movi v1.16b, #5
; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b ; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
%3 = icmp ult <16 x i8> %2, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> %3 = icmp ult <16 x i8> %2, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
%4 = sext <16 x i1> %3 to <16 x i8> %4 = sext <16 x i1> %3 to <16 x i8>
ret <16 x i8> %4 ret <16 x i8> %4
} }
define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) { define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ugt_5_v16i8: ; CHECK-LABEL: ugt_5_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.16b, #5
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: movi v1.16b, #5
; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b ; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
%3 = icmp ugt <16 x i8> %2, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> %3 = icmp ugt <16 x i8> %2, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
%4 = sext <16 x i1> %3 to <16 x i8> %4 = sext <16 x i1> %3 to <16 x i8>
ret <16 x i8> %4 ret <16 x i8> %4
} }
define <16 x i8> @ult_6_v16i8(<16 x i8> %0) { define <16 x i8> @ult_6_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ult_6_v16i8: ; CHECK-LABEL: ult_6_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.16b, #6
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: movi v1.16b, #6
; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b ; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
%3 = icmp ult <16 x i8> %2, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6> %3 = icmp ult <16 x i8> %2, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
%4 = sext <16 x i1> %3 to <16 x i8> %4 = sext <16 x i1> %3 to <16 x i8>
ret <16 x i8> %4 ret <16 x i8> %4
} }
define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) { define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ugt_6_v16i8: ; CHECK-LABEL: ugt_6_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.16b, #6
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: movi v1.16b, #6
; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b ; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
%3 = icmp ugt <16 x i8> %2, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6> %3 = icmp ugt <16 x i8> %2, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
%4 = sext <16 x i1> %3 to <16 x i8> %4 = sext <16 x i1> %3 to <16 x i8>
ret <16 x i8> %4 ret <16 x i8> %4
} }
define <16 x i8> @ult_7_v16i8(<16 x i8> %0) { define <16 x i8> @ult_7_v16i8(<16 x i8> %0) {
; CHECK-LABEL: ult_7_v16i8: ; CHECK-LABEL: ult_7_v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.16b, #7
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: movi v1.16b, #7
; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b ; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
%3 = icmp ult <16 x i8> %2, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> %3 = icmp ult <16 x i8> %2, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
%4 = sext <16 x i1> %3 to <16 x i8> %4 = sext <16 x i1> %3 to <16 x i8>
ret <16 x i8> %4 ret <16 x i8> %4
} }
▲ Show 20 Lines • Show All 1,312 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_2_v2i64: ; CHECK-LABEL: ugt_2_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #2 ; CHECK-NEXT: mov w8, #2
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 2, i64 2> %3 = icmp ugt <2 x i64> %2, <i64 2, i64 2>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_3_v2i64(<2 x i64> %0) { define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_3_v2i64: ; CHECK-LABEL: ult_3_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #3 ; CHECK-NEXT: mov w8, #3
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 3, i64 3> %3 = icmp ult <2 x i64> %2, <i64 3, i64 3>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_3_v2i64: ; CHECK-LABEL: ugt_3_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #3 ; CHECK-NEXT: mov w8, #3
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 3, i64 3> %3 = icmp ugt <2 x i64> %2, <i64 3, i64 3>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_4_v2i64(<2 x i64> %0) { define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_4_v2i64: ; CHECK-LABEL: ult_4_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #4 ; CHECK-NEXT: mov w8, #4
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 4, i64 4> %3 = icmp ult <2 x i64> %2, <i64 4, i64 4>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_4_v2i64: ; CHECK-LABEL: ugt_4_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #4 ; CHECK-NEXT: mov w8, #4
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 4, i64 4> %3 = icmp ugt <2 x i64> %2, <i64 4, i64 4>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_5_v2i64(<2 x i64> %0) { define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_5_v2i64: ; CHECK-LABEL: ult_5_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #5 ; CHECK-NEXT: mov w8, #5
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 5, i64 5> %3 = icmp ult <2 x i64> %2, <i64 5, i64 5>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_5_v2i64: ; CHECK-LABEL: ugt_5_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #5 ; CHECK-NEXT: mov w8, #5
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 5, i64 5> %3 = icmp ugt <2 x i64> %2, <i64 5, i64 5>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_6_v2i64(<2 x i64> %0) { define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_6_v2i64: ; CHECK-LABEL: ult_6_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #6 ; CHECK-NEXT: mov w8, #6
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 6, i64 6> %3 = icmp ult <2 x i64> %2, <i64 6, i64 6>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_6_v2i64: ; CHECK-LABEL: ugt_6_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #6 ; CHECK-NEXT: mov w8, #6
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 6, i64 6> %3 = icmp ugt <2 x i64> %2, <i64 6, i64 6>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_7_v2i64(<2 x i64> %0) { define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_7_v2i64: ; CHECK-LABEL: ult_7_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #7 ; CHECK-NEXT: mov w8, #7
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 7, i64 7> %3 = icmp ult <2 x i64> %2, <i64 7, i64 7>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_7_v2i64: ; CHECK-LABEL: ugt_7_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #7 ; CHECK-NEXT: mov w8, #7
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 7, i64 7> %3 = icmp ugt <2 x i64> %2, <i64 7, i64 7>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_8_v2i64(<2 x i64> %0) { define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_8_v2i64: ; CHECK-LABEL: ult_8_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #8 ; CHECK-NEXT: mov w8, #8
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 8, i64 8> %3 = icmp ult <2 x i64> %2, <i64 8, i64 8>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_8_v2i64: ; CHECK-LABEL: ugt_8_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #8 ; CHECK-NEXT: mov w8, #8
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 8, i64 8> %3 = icmp ugt <2 x i64> %2, <i64 8, i64 8>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_9_v2i64(<2 x i64> %0) { define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_9_v2i64: ; CHECK-LABEL: ult_9_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #9 ; CHECK-NEXT: mov w8, #9
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 9, i64 9> %3 = icmp ult <2 x i64> %2, <i64 9, i64 9>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_9_v2i64: ; CHECK-LABEL: ugt_9_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #9 ; CHECK-NEXT: mov w8, #9
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 9, i64 9> %3 = icmp ugt <2 x i64> %2, <i64 9, i64 9>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_10_v2i64(<2 x i64> %0) { define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_10_v2i64: ; CHECK-LABEL: ult_10_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #10 ; CHECK-NEXT: mov w8, #10
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 10, i64 10> %3 = icmp ult <2 x i64> %2, <i64 10, i64 10>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_10_v2i64: ; CHECK-LABEL: ugt_10_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #10 ; CHECK-NEXT: mov w8, #10
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 10, i64 10> %3 = icmp ugt <2 x i64> %2, <i64 10, i64 10>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_11_v2i64(<2 x i64> %0) { define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_11_v2i64: ; CHECK-LABEL: ult_11_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #11 ; CHECK-NEXT: mov w8, #11
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 11, i64 11> %3 = icmp ult <2 x i64> %2, <i64 11, i64 11>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_11_v2i64: ; CHECK-LABEL: ugt_11_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #11 ; CHECK-NEXT: mov w8, #11
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 11, i64 11> %3 = icmp ugt <2 x i64> %2, <i64 11, i64 11>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_12_v2i64(<2 x i64> %0) { define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_12_v2i64: ; CHECK-LABEL: ult_12_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #12 ; CHECK-NEXT: mov w8, #12
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 12, i64 12> %3 = icmp ult <2 x i64> %2, <i64 12, i64 12>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_12_v2i64: ; CHECK-LABEL: ugt_12_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #12 ; CHECK-NEXT: mov w8, #12
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 12, i64 12> %3 = icmp ugt <2 x i64> %2, <i64 12, i64 12>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_13_v2i64(<2 x i64> %0) { define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_13_v2i64: ; CHECK-LABEL: ult_13_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #13 ; CHECK-NEXT: mov w8, #13
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 13, i64 13> %3 = icmp ult <2 x i64> %2, <i64 13, i64 13>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_13_v2i64: ; CHECK-LABEL: ugt_13_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #13 ; CHECK-NEXT: mov w8, #13
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 13, i64 13> %3 = icmp ugt <2 x i64> %2, <i64 13, i64 13>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_14_v2i64(<2 x i64> %0) { define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_14_v2i64: ; CHECK-LABEL: ult_14_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #14 ; CHECK-NEXT: mov w8, #14
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 14, i64 14> %3 = icmp ult <2 x i64> %2, <i64 14, i64 14>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_14_v2i64: ; CHECK-LABEL: ugt_14_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #14 ; CHECK-NEXT: mov w8, #14
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 14, i64 14> %3 = icmp ugt <2 x i64> %2, <i64 14, i64 14>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_15_v2i64(<2 x i64> %0) { define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_15_v2i64: ; CHECK-LABEL: ult_15_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #15 ; CHECK-NEXT: mov w8, #15
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 15, i64 15> %3 = icmp ult <2 x i64> %2, <i64 15, i64 15>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_15_v2i64: ; CHECK-LABEL: ugt_15_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #15 ; CHECK-NEXT: mov w8, #15
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 15, i64 15> %3 = icmp ugt <2 x i64> %2, <i64 15, i64 15>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_16_v2i64(<2 x i64> %0) { define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_16_v2i64: ; CHECK-LABEL: ult_16_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #16 ; CHECK-NEXT: mov w8, #16
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 16, i64 16> %3 = icmp ult <2 x i64> %2, <i64 16, i64 16>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_16_v2i64: ; CHECK-LABEL: ugt_16_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #16 ; CHECK-NEXT: mov w8, #16
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 16, i64 16> %3 = icmp ugt <2 x i64> %2, <i64 16, i64 16>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_17_v2i64(<2 x i64> %0) { define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_17_v2i64: ; CHECK-LABEL: ult_17_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #17 ; CHECK-NEXT: mov w8, #17
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 17, i64 17> %3 = icmp ult <2 x i64> %2, <i64 17, i64 17>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_17_v2i64: ; CHECK-LABEL: ugt_17_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #17 ; CHECK-NEXT: mov w8, #17
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 17, i64 17> %3 = icmp ugt <2 x i64> %2, <i64 17, i64 17>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_18_v2i64(<2 x i64> %0) { define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_18_v2i64: ; CHECK-LABEL: ult_18_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #18 ; CHECK-NEXT: mov w8, #18
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 18, i64 18> %3 = icmp ult <2 x i64> %2, <i64 18, i64 18>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_18_v2i64: ; CHECK-LABEL: ugt_18_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #18 ; CHECK-NEXT: mov w8, #18
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 18, i64 18> %3 = icmp ugt <2 x i64> %2, <i64 18, i64 18>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_19_v2i64(<2 x i64> %0) { define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_19_v2i64: ; CHECK-LABEL: ult_19_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #19 ; CHECK-NEXT: mov w8, #19
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 19, i64 19> %3 = icmp ult <2 x i64> %2, <i64 19, i64 19>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_19_v2i64: ; CHECK-LABEL: ugt_19_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #19 ; CHECK-NEXT: mov w8, #19
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 19, i64 19> %3 = icmp ugt <2 x i64> %2, <i64 19, i64 19>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_20_v2i64(<2 x i64> %0) { define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_20_v2i64: ; CHECK-LABEL: ult_20_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #20 ; CHECK-NEXT: mov w8, #20
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 20, i64 20> %3 = icmp ult <2 x i64> %2, <i64 20, i64 20>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_20_v2i64: ; CHECK-LABEL: ugt_20_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #20 ; CHECK-NEXT: mov w8, #20
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 20, i64 20> %3 = icmp ugt <2 x i64> %2, <i64 20, i64 20>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_21_v2i64(<2 x i64> %0) { define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_21_v2i64: ; CHECK-LABEL: ult_21_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #21 ; CHECK-NEXT: mov w8, #21
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 21, i64 21> %3 = icmp ult <2 x i64> %2, <i64 21, i64 21>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_21_v2i64: ; CHECK-LABEL: ugt_21_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #21 ; CHECK-NEXT: mov w8, #21
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 21, i64 21> %3 = icmp ugt <2 x i64> %2, <i64 21, i64 21>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_22_v2i64(<2 x i64> %0) { define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_22_v2i64: ; CHECK-LABEL: ult_22_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #22 ; CHECK-NEXT: mov w8, #22
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 22, i64 22> %3 = icmp ult <2 x i64> %2, <i64 22, i64 22>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_22_v2i64: ; CHECK-LABEL: ugt_22_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #22 ; CHECK-NEXT: mov w8, #22
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 22, i64 22> %3 = icmp ugt <2 x i64> %2, <i64 22, i64 22>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_23_v2i64(<2 x i64> %0) { define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_23_v2i64: ; CHECK-LABEL: ult_23_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #23 ; CHECK-NEXT: mov w8, #23
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 23, i64 23> %3 = icmp ult <2 x i64> %2, <i64 23, i64 23>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_23_v2i64: ; CHECK-LABEL: ugt_23_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #23 ; CHECK-NEXT: mov w8, #23
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 23, i64 23> %3 = icmp ugt <2 x i64> %2, <i64 23, i64 23>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_24_v2i64(<2 x i64> %0) { define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_24_v2i64: ; CHECK-LABEL: ult_24_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #24 ; CHECK-NEXT: mov w8, #24
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 24, i64 24> %3 = icmp ult <2 x i64> %2, <i64 24, i64 24>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_24_v2i64: ; CHECK-LABEL: ugt_24_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #24 ; CHECK-NEXT: mov w8, #24
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 24, i64 24> %3 = icmp ugt <2 x i64> %2, <i64 24, i64 24>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_25_v2i64(<2 x i64> %0) { define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_25_v2i64: ; CHECK-LABEL: ult_25_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #25 ; CHECK-NEXT: mov w8, #25
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 25, i64 25> %3 = icmp ult <2 x i64> %2, <i64 25, i64 25>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_25_v2i64: ; CHECK-LABEL: ugt_25_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #25 ; CHECK-NEXT: mov w8, #25
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 25, i64 25> %3 = icmp ugt <2 x i64> %2, <i64 25, i64 25>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_26_v2i64(<2 x i64> %0) { define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_26_v2i64: ; CHECK-LABEL: ult_26_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #26 ; CHECK-NEXT: mov w8, #26
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 26, i64 26> %3 = icmp ult <2 x i64> %2, <i64 26, i64 26>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_26_v2i64: ; CHECK-LABEL: ugt_26_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #26 ; CHECK-NEXT: mov w8, #26
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 26, i64 26> %3 = icmp ugt <2 x i64> %2, <i64 26, i64 26>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_27_v2i64(<2 x i64> %0) { define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_27_v2i64: ; CHECK-LABEL: ult_27_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #27 ; CHECK-NEXT: mov w8, #27
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 27, i64 27> %3 = icmp ult <2 x i64> %2, <i64 27, i64 27>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_27_v2i64: ; CHECK-LABEL: ugt_27_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #27 ; CHECK-NEXT: mov w8, #27
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 27, i64 27> %3 = icmp ugt <2 x i64> %2, <i64 27, i64 27>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_28_v2i64(<2 x i64> %0) { define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_28_v2i64: ; CHECK-LABEL: ult_28_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #28 ; CHECK-NEXT: mov w8, #28
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 28, i64 28> %3 = icmp ult <2 x i64> %2, <i64 28, i64 28>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_28_v2i64: ; CHECK-LABEL: ugt_28_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #28 ; CHECK-NEXT: mov w8, #28
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 28, i64 28> %3 = icmp ugt <2 x i64> %2, <i64 28, i64 28>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_29_v2i64(<2 x i64> %0) { define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_29_v2i64: ; CHECK-LABEL: ult_29_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #29 ; CHECK-NEXT: mov w8, #29
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 29, i64 29> %3 = icmp ult <2 x i64> %2, <i64 29, i64 29>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_29_v2i64: ; CHECK-LABEL: ugt_29_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #29 ; CHECK-NEXT: mov w8, #29
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 29, i64 29> %3 = icmp ugt <2 x i64> %2, <i64 29, i64 29>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_30_v2i64(<2 x i64> %0) { define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_30_v2i64: ; CHECK-LABEL: ult_30_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #30 ; CHECK-NEXT: mov w8, #30
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 30, i64 30> %3 = icmp ult <2 x i64> %2, <i64 30, i64 30>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_30_v2i64: ; CHECK-LABEL: ugt_30_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #30 ; CHECK-NEXT: mov w8, #30
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 30, i64 30> %3 = icmp ugt <2 x i64> %2, <i64 30, i64 30>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_31_v2i64(<2 x i64> %0) { define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_31_v2i64: ; CHECK-LABEL: ult_31_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #31 ; CHECK-NEXT: mov w8, #31
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 31, i64 31> %3 = icmp ult <2 x i64> %2, <i64 31, i64 31>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_31_v2i64: ; CHECK-LABEL: ugt_31_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #31 ; CHECK-NEXT: mov w8, #31
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 31, i64 31> %3 = icmp ugt <2 x i64> %2, <i64 31, i64 31>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_32_v2i64(<2 x i64> %0) { define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_32_v2i64: ; CHECK-LABEL: ult_32_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #32 ; CHECK-NEXT: mov w8, #32
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 32, i64 32> %3 = icmp ult <2 x i64> %2, <i64 32, i64 32>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_32_v2i64: ; CHECK-LABEL: ugt_32_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #32 ; CHECK-NEXT: mov w8, #32
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 32, i64 32> %3 = icmp ugt <2 x i64> %2, <i64 32, i64 32>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_33_v2i64(<2 x i64> %0) { define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_33_v2i64: ; CHECK-LABEL: ult_33_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #33 ; CHECK-NEXT: mov w8, #33
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 33, i64 33> %3 = icmp ult <2 x i64> %2, <i64 33, i64 33>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_33_v2i64: ; CHECK-LABEL: ugt_33_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #33 ; CHECK-NEXT: mov w8, #33
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 33, i64 33> %3 = icmp ugt <2 x i64> %2, <i64 33, i64 33>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_34_v2i64(<2 x i64> %0) { define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_34_v2i64: ; CHECK-LABEL: ult_34_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #34 ; CHECK-NEXT: mov w8, #34
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 34, i64 34> %3 = icmp ult <2 x i64> %2, <i64 34, i64 34>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_34_v2i64: ; CHECK-LABEL: ugt_34_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #34 ; CHECK-NEXT: mov w8, #34
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 34, i64 34> %3 = icmp ugt <2 x i64> %2, <i64 34, i64 34>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_35_v2i64(<2 x i64> %0) { define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_35_v2i64: ; CHECK-LABEL: ult_35_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #35 ; CHECK-NEXT: mov w8, #35
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 35, i64 35> %3 = icmp ult <2 x i64> %2, <i64 35, i64 35>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_35_v2i64: ; CHECK-LABEL: ugt_35_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #35 ; CHECK-NEXT: mov w8, #35
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 35, i64 35> %3 = icmp ugt <2 x i64> %2, <i64 35, i64 35>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_36_v2i64(<2 x i64> %0) { define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_36_v2i64: ; CHECK-LABEL: ult_36_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #36 ; CHECK-NEXT: mov w8, #36
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 36, i64 36> %3 = icmp ult <2 x i64> %2, <i64 36, i64 36>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_36_v2i64: ; CHECK-LABEL: ugt_36_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #36 ; CHECK-NEXT: mov w8, #36
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 36, i64 36> %3 = icmp ugt <2 x i64> %2, <i64 36, i64 36>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_37_v2i64(<2 x i64> %0) { define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_37_v2i64: ; CHECK-LABEL: ult_37_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #37 ; CHECK-NEXT: mov w8, #37
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 37, i64 37> %3 = icmp ult <2 x i64> %2, <i64 37, i64 37>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_37_v2i64: ; CHECK-LABEL: ugt_37_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #37 ; CHECK-NEXT: mov w8, #37
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 37, i64 37> %3 = icmp ugt <2 x i64> %2, <i64 37, i64 37>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_38_v2i64(<2 x i64> %0) { define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_38_v2i64: ; CHECK-LABEL: ult_38_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #38 ; CHECK-NEXT: mov w8, #38
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 38, i64 38> %3 = icmp ult <2 x i64> %2, <i64 38, i64 38>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_38_v2i64: ; CHECK-LABEL: ugt_38_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #38 ; CHECK-NEXT: mov w8, #38
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 38, i64 38> %3 = icmp ugt <2 x i64> %2, <i64 38, i64 38>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_39_v2i64(<2 x i64> %0) { define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_39_v2i64: ; CHECK-LABEL: ult_39_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #39 ; CHECK-NEXT: mov w8, #39
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 39, i64 39> %3 = icmp ult <2 x i64> %2, <i64 39, i64 39>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_39_v2i64: ; CHECK-LABEL: ugt_39_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #39 ; CHECK-NEXT: mov w8, #39
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 39, i64 39> %3 = icmp ugt <2 x i64> %2, <i64 39, i64 39>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_40_v2i64(<2 x i64> %0) { define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_40_v2i64: ; CHECK-LABEL: ult_40_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #40 ; CHECK-NEXT: mov w8, #40
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 40, i64 40> %3 = icmp ult <2 x i64> %2, <i64 40, i64 40>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_40_v2i64: ; CHECK-LABEL: ugt_40_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #40 ; CHECK-NEXT: mov w8, #40
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 40, i64 40> %3 = icmp ugt <2 x i64> %2, <i64 40, i64 40>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_41_v2i64(<2 x i64> %0) { define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_41_v2i64: ; CHECK-LABEL: ult_41_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #41 ; CHECK-NEXT: mov w8, #41
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 41, i64 41> %3 = icmp ult <2 x i64> %2, <i64 41, i64 41>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_41_v2i64: ; CHECK-LABEL: ugt_41_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #41 ; CHECK-NEXT: mov w8, #41
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 41, i64 41> %3 = icmp ugt <2 x i64> %2, <i64 41, i64 41>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_42_v2i64(<2 x i64> %0) { define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_42_v2i64: ; CHECK-LABEL: ult_42_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #42 ; CHECK-NEXT: mov w8, #42
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 42, i64 42> %3 = icmp ult <2 x i64> %2, <i64 42, i64 42>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_42_v2i64: ; CHECK-LABEL: ugt_42_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #42 ; CHECK-NEXT: mov w8, #42
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 42, i64 42> %3 = icmp ugt <2 x i64> %2, <i64 42, i64 42>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_43_v2i64(<2 x i64> %0) { define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_43_v2i64: ; CHECK-LABEL: ult_43_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #43 ; CHECK-NEXT: mov w8, #43
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 43, i64 43> %3 = icmp ult <2 x i64> %2, <i64 43, i64 43>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_43_v2i64: ; CHECK-LABEL: ugt_43_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #43 ; CHECK-NEXT: mov w8, #43
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 43, i64 43> %3 = icmp ugt <2 x i64> %2, <i64 43, i64 43>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_44_v2i64(<2 x i64> %0) { define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_44_v2i64: ; CHECK-LABEL: ult_44_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #44 ; CHECK-NEXT: mov w8, #44
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 44, i64 44> %3 = icmp ult <2 x i64> %2, <i64 44, i64 44>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_44_v2i64: ; CHECK-LABEL: ugt_44_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #44 ; CHECK-NEXT: mov w8, #44
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 44, i64 44> %3 = icmp ugt <2 x i64> %2, <i64 44, i64 44>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_45_v2i64(<2 x i64> %0) { define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_45_v2i64: ; CHECK-LABEL: ult_45_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #45 ; CHECK-NEXT: mov w8, #45
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 45, i64 45> %3 = icmp ult <2 x i64> %2, <i64 45, i64 45>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_45_v2i64: ; CHECK-LABEL: ugt_45_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #45 ; CHECK-NEXT: mov w8, #45
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 45, i64 45> %3 = icmp ugt <2 x i64> %2, <i64 45, i64 45>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_46_v2i64(<2 x i64> %0) { define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_46_v2i64: ; CHECK-LABEL: ult_46_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #46 ; CHECK-NEXT: mov w8, #46
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 46, i64 46> %3 = icmp ult <2 x i64> %2, <i64 46, i64 46>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_46_v2i64: ; CHECK-LABEL: ugt_46_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #46 ; CHECK-NEXT: mov w8, #46
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 46, i64 46> %3 = icmp ugt <2 x i64> %2, <i64 46, i64 46>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_47_v2i64(<2 x i64> %0) { define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_47_v2i64: ; CHECK-LABEL: ult_47_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #47 ; CHECK-NEXT: mov w8, #47
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 47, i64 47> %3 = icmp ult <2 x i64> %2, <i64 47, i64 47>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_47_v2i64: ; CHECK-LABEL: ugt_47_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #47 ; CHECK-NEXT: mov w8, #47
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 47, i64 47> %3 = icmp ugt <2 x i64> %2, <i64 47, i64 47>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_48_v2i64(<2 x i64> %0) { define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_48_v2i64: ; CHECK-LABEL: ult_48_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #48 ; CHECK-NEXT: mov w8, #48
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 48, i64 48> %3 = icmp ult <2 x i64> %2, <i64 48, i64 48>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_48_v2i64: ; CHECK-LABEL: ugt_48_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #48 ; CHECK-NEXT: mov w8, #48
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 48, i64 48> %3 = icmp ugt <2 x i64> %2, <i64 48, i64 48>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_49_v2i64(<2 x i64> %0) { define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_49_v2i64: ; CHECK-LABEL: ult_49_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #49 ; CHECK-NEXT: mov w8, #49
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 49, i64 49> %3 = icmp ult <2 x i64> %2, <i64 49, i64 49>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_49_v2i64: ; CHECK-LABEL: ugt_49_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #49 ; CHECK-NEXT: mov w8, #49
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 49, i64 49> %3 = icmp ugt <2 x i64> %2, <i64 49, i64 49>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_50_v2i64(<2 x i64> %0) { define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_50_v2i64: ; CHECK-LABEL: ult_50_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #50 ; CHECK-NEXT: mov w8, #50
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 50, i64 50> %3 = icmp ult <2 x i64> %2, <i64 50, i64 50>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_50_v2i64: ; CHECK-LABEL: ugt_50_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #50 ; CHECK-NEXT: mov w8, #50
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 50, i64 50> %3 = icmp ugt <2 x i64> %2, <i64 50, i64 50>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_51_v2i64(<2 x i64> %0) { define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_51_v2i64: ; CHECK-LABEL: ult_51_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #51 ; CHECK-NEXT: mov w8, #51
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 51, i64 51> %3 = icmp ult <2 x i64> %2, <i64 51, i64 51>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_51_v2i64: ; CHECK-LABEL: ugt_51_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #51 ; CHECK-NEXT: mov w8, #51
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 51, i64 51> %3 = icmp ugt <2 x i64> %2, <i64 51, i64 51>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_52_v2i64(<2 x i64> %0) { define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_52_v2i64: ; CHECK-LABEL: ult_52_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #52 ; CHECK-NEXT: mov w8, #52
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 52, i64 52> %3 = icmp ult <2 x i64> %2, <i64 52, i64 52>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_52_v2i64: ; CHECK-LABEL: ugt_52_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #52 ; CHECK-NEXT: mov w8, #52
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 52, i64 52> %3 = icmp ugt <2 x i64> %2, <i64 52, i64 52>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_53_v2i64(<2 x i64> %0) { define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_53_v2i64: ; CHECK-LABEL: ult_53_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #53 ; CHECK-NEXT: mov w8, #53
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 53, i64 53> %3 = icmp ult <2 x i64> %2, <i64 53, i64 53>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_53_v2i64: ; CHECK-LABEL: ugt_53_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #53 ; CHECK-NEXT: mov w8, #53
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 53, i64 53> %3 = icmp ugt <2 x i64> %2, <i64 53, i64 53>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_54_v2i64(<2 x i64> %0) { define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_54_v2i64: ; CHECK-LABEL: ult_54_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #54 ; CHECK-NEXT: mov w8, #54
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 54, i64 54> %3 = icmp ult <2 x i64> %2, <i64 54, i64 54>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_54_v2i64: ; CHECK-LABEL: ugt_54_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #54 ; CHECK-NEXT: mov w8, #54
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 54, i64 54> %3 = icmp ugt <2 x i64> %2, <i64 54, i64 54>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_55_v2i64(<2 x i64> %0) { define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_55_v2i64: ; CHECK-LABEL: ult_55_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #55 ; CHECK-NEXT: mov w8, #55
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 55, i64 55> %3 = icmp ult <2 x i64> %2, <i64 55, i64 55>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_55_v2i64: ; CHECK-LABEL: ugt_55_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #55 ; CHECK-NEXT: mov w8, #55
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 55, i64 55> %3 = icmp ugt <2 x i64> %2, <i64 55, i64 55>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_56_v2i64(<2 x i64> %0) { define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_56_v2i64: ; CHECK-LABEL: ult_56_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #56 ; CHECK-NEXT: mov w8, #56
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 56, i64 56> %3 = icmp ult <2 x i64> %2, <i64 56, i64 56>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_56_v2i64: ; CHECK-LABEL: ugt_56_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #56 ; CHECK-NEXT: mov w8, #56
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 56, i64 56> %3 = icmp ugt <2 x i64> %2, <i64 56, i64 56>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_57_v2i64(<2 x i64> %0) { define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_57_v2i64: ; CHECK-LABEL: ult_57_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #57 ; CHECK-NEXT: mov w8, #57
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 57, i64 57> %3 = icmp ult <2 x i64> %2, <i64 57, i64 57>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_57_v2i64: ; CHECK-LABEL: ugt_57_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #57 ; CHECK-NEXT: mov w8, #57
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 57, i64 57> %3 = icmp ugt <2 x i64> %2, <i64 57, i64 57>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_58_v2i64(<2 x i64> %0) { define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_58_v2i64: ; CHECK-LABEL: ult_58_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #58 ; CHECK-NEXT: mov w8, #58
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 58, i64 58> %3 = icmp ult <2 x i64> %2, <i64 58, i64 58>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_58_v2i64: ; CHECK-LABEL: ugt_58_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #58 ; CHECK-NEXT: mov w8, #58
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 58, i64 58> %3 = icmp ugt <2 x i64> %2, <i64 58, i64 58>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_59_v2i64(<2 x i64> %0) { define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_59_v2i64: ; CHECK-LABEL: ult_59_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #59 ; CHECK-NEXT: mov w8, #59
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 59, i64 59> %3 = icmp ult <2 x i64> %2, <i64 59, i64 59>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_59_v2i64: ; CHECK-LABEL: ugt_59_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #59 ; CHECK-NEXT: mov w8, #59
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 59, i64 59> %3 = icmp ugt <2 x i64> %2, <i64 59, i64 59>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_60_v2i64(<2 x i64> %0) { define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_60_v2i64: ; CHECK-LABEL: ult_60_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #60 ; CHECK-NEXT: mov w8, #60
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 60, i64 60> %3 = icmp ult <2 x i64> %2, <i64 60, i64 60>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_60_v2i64: ; CHECK-LABEL: ugt_60_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #60 ; CHECK-NEXT: mov w8, #60
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 60, i64 60> %3 = icmp ugt <2 x i64> %2, <i64 60, i64 60>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_61_v2i64(<2 x i64> %0) { define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_61_v2i64: ; CHECK-LABEL: ult_61_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #61 ; CHECK-NEXT: mov w8, #61
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 61, i64 61> %3 = icmp ult <2 x i64> %2, <i64 61, i64 61>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_61_v2i64: ; CHECK-LABEL: ugt_61_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #61 ; CHECK-NEXT: mov w8, #61
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 61, i64 61> %3 = icmp ugt <2 x i64> %2, <i64 61, i64 61>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_62_v2i64(<2 x i64> %0) { define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_62_v2i64: ; CHECK-LABEL: ult_62_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #62 ; CHECK-NEXT: mov w8, #62
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 62, i64 62> %3 = icmp ult <2 x i64> %2, <i64 62, i64 62>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_62_v2i64: ; CHECK-LABEL: ugt_62_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #62 ; CHECK-NEXT: mov w8, #62
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 62, i64 62> %3 = icmp ugt <2 x i64> %2, <i64 62, i64 62>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_63_v2i64(<2 x i64> %0) { define <2 x i64> @ult_63_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_63_v2i64: ; CHECK-LABEL: ult_63_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: mov w8, #63 ; CHECK-NEXT: mov w8, #63
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b ; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.4s, v0.8h ; CHECK-NEXT: uaddlp v0.4s, v0.8h
; CHECK-NEXT: uaddlp v0.2d, v0.4s ; CHECK-NEXT: uaddlp v0.2d, v0.4s
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 63, i64 63> %3 = icmp ult <2 x i64> %2, <i64 63, i64 63>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)
declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>)
declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)
declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)

llvm/test/CodeGen/AArch64/vselect-constants.ll

Show First 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0> %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
ret <4 x i32> %add ret <4 x i32> %add
} }
define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: cmp_sel_1_or_0_vec: ; CHECK-LABEL: cmp_sel_1_or_0_vec:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s ; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%cond = icmp eq <4 x i32> %x, %y %cond = icmp eq <4 x i32> %x, %y
%add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0> %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
ret <4 x i32> %add ret <4 x i32> %add
} }
define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) { define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) {
; CHECK-LABEL: sel_0_or_1_vec: ; CHECK-LABEL: sel_0_or_1_vec:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-NEXT: movi v1.4s, #1 ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: shl v0.4s, v0.4s, #31 ; CHECK-NEXT: shl v0.4s, v0.4s, #31
; CHECK-NEXT: cmge v0.4s, v0.4s, #0 ; CHECK-NEXT: cmge v0.4s, v0.4s, #0
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %add ret <4 x i32> %add
} }
define <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: cmp_sel_0_or_1_vec: ; CHECK-LABEL: cmp_sel_0_or_1_vec:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s ; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
; CHECK-NEXT: bic v0.16b, v2.16b, v0.16b ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%cond = icmp eq <4 x i32> %x, %y %cond = icmp eq <4 x i32> %x, %y
%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %add ret <4 x i32> %add
} }
define <16 x i8> @signbit_mask_v16i8(<16 x i8> %a, <16 x i8> %b) { define <16 x i8> @signbit_mask_v16i8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: signbit_mask_v16i8: ; CHECK-LABEL: signbit_mask_v16i8:
▲ Show 20 Lines • Show All 186 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/xor.ll

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%t0 = sub <4 x i32> %x, %y %t0 = sub <4 x i32> %x, %y
%r = sub <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1> %r = sub <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %r ret <4 x i32> %r
} }
define <4 x i32> @vec_add_of_not_with_undef(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @vec_add_of_not_with_undef(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: vec_add_of_not_with_undef: ; CHECK-LABEL: vec_add_of_not_with_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.2d, #0xffffffffffffffff
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: add v0.4s, v0.4s, v2.4s ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> %x, %y %t0 = sub <4 x i32> %x, %y
%r = add <4 x i32> %t0, <i32 -1, i32 undef, i32 -1, i32 -1> %r = add <4 x i32> %t0, <i32 -1, i32 undef, i32 -1, i32 -1>
ret <4 x i32> %r ret <4 x i32> %r
} }
define <4 x i32> @vec_add_of_not_with_undef_decrement(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @vec_add_of_not_with_undef_decrement(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: vec_add_of_not_with_undef_decrement: ; CHECK-LABEL: vec_add_of_not_with_undef_decrement:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: add v0.4s, v0.4s, v2.4s ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> %x, %y %t0 = sub <4 x i32> %x, %y
%r = add <4 x i32> %t0, <i32 1, i32 undef, i32 1, i32 1> %r = add <4 x i32> %t0, <i32 1, i32 undef, i32 1, i32 1>
ret <4 x i32> %r ret <4 x i32> %r
} }

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-neon-instructions.s

Show First 20 Lines • Show All 1,055 Lines • ▼ Show 20 Lines
zip2 v0.16b, v0.16b, v0.16b zip2 v0.16b, v0.16b, v0.16b
zip2 v0.2d, v0.2d, v0.2d zip2 v0.2d, v0.2d, v0.2d
zip2 v0.2s, v0.2s, v0.2s zip2 v0.2s, v0.2s, v0.2s
zip2 v0.4h, v0.4h, v0.4h zip2 v0.4h, v0.4h, v0.4h
zip2 v0.4s, v0.4s, v0.4s zip2 v0.4s, v0.4s, v0.4s
zip2 v0.8b, v0.8b, v0.8b zip2 v0.8b, v0.8b, v0.8b
zip2 v0.8h, v0.8h, v0.8h zip2 v0.8h, v0.8h, v0.8h
# CHECK: Instruction Info: # CHECK: Instruction Info:
dmgreenUnsubmitted
Not Done
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Why has this file been rewritten?

dmgreen: Why has this file been rewritten?
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
Show All 13 Lines
# CHECK-NEXT: 1 3 1.00 addhn2 v0.16b, v0.8h, v0.8h # CHECK-NEXT: 1 3 1.00 addhn2 v0.16b, v0.8h, v0.8h
# CHECK-NEXT: 1 3 1.00 addhn2 v0.4s, v0.2d, v0.2d # CHECK-NEXT: 1 3 1.00 addhn2 v0.4s, v0.2d, v0.2d
# CHECK-NEXT: 1 3 1.00 addhn2 v0.8h, v0.4s, v0.4s # CHECK-NEXT: 1 3 1.00 addhn2 v0.8h, v0.4s, v0.4s
# CHECK-NEXT: 1 3 1.00 addp v0.2d, v0.2d, v0.2d # CHECK-NEXT: 1 3 1.00 addp v0.2d, v0.2d, v0.2d
# CHECK-NEXT: 1 3 0.50 addp v0.8b, v0.8b, v0.8b # CHECK-NEXT: 1 3 0.50 addp v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 1 0.50 and v0.8b, v0.8b, v0.8b # CHECK-NEXT: 1 1 0.50 and v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 1 0.50 bic v0.4h, #15, lsl #8 # CHECK-NEXT: 1 1 0.50 bic v0.4h, #15, lsl #8
# CHECK-NEXT: 1 1 0.50 bic v0.8b, v0.8b, v0.8b # CHECK-NEXT: 1 1 0.50 bic v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 4 1.00 bif v0.16b, v0.16b, v0.16b # CHECK-NEXT: 1 2 1.00 bif v0.16b, v0.16b, v0.16b
# CHECK-NEXT: 1 4 1.00 bit v0.16b, v0.16b, v0.16b # CHECK-NEXT: 1 2 1.00 bit v0.16b, v0.16b, v0.16b
# CHECK-NEXT: 1 4 0.50 bsl v0.8b, v0.8b, v0.8b # CHECK-NEXT: 1 2 0.50 bsl v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 4 1.00 cls v0.16b, v0.16b # CHECK-NEXT: 1 3 1.00 cls v0.16b, v0.16b
# CHECK-NEXT: 1 4 0.50 cls v0.2s, v0.2s # CHECK-NEXT: 1 3 0.50 cls v0.2s, v0.2s
# CHECK-NEXT: 1 4 0.50 cls v0.4h, v0.4h # CHECK-NEXT: 1 3 0.50 cls v0.4h, v0.4h
# CHECK-NEXT: 1 4 1.00 cls v0.4s, v0.4s # CHECK-NEXT: 1 3 1.00 cls v0.4s, v0.4s
# CHECK-NEXT: 1 4 0.50 cls v0.8b, v0.8b # CHECK-NEXT: 1 3 0.50 cls v0.8b, v0.8b
# CHECK-NEXT: 1 4 1.00 cls v0.8h, v0.8h # CHECK-NEXT: 1 3 1.00 cls v0.8h, v0.8h
# CHECK-NEXT: 1 4 1.00 clz v0.16b, v0.16b # CHECK-NEXT: 1 2 1.00 clz v0.16b, v0.16b
# CHECK-NEXT: 1 4 0.50 clz v0.2s, v0.2s # CHECK-NEXT: 1 2 0.50 clz v0.2s, v0.2s
# CHECK-NEXT: 1 4 0.50 clz v0.4h, v0.4h # CHECK-NEXT: 1 2 0.50 clz v0.4h, v0.4h
# CHECK-NEXT: 1 4 1.00 clz v0.4s, v0.4s # CHECK-NEXT: 1 2 1.00 clz v0.4s, v0.4s
# CHECK-NEXT: 1 4 0.50 clz v0.8b, v0.8b # CHECK-NEXT: 1 2 0.50 clz v0.8b, v0.8b
# CHECK-NEXT: 1 4 1.00 clz v0.8h, v0.8h # CHECK-NEXT: 1 2 1.00 clz v0.8h, v0.8h
# CHECK-NEXT: 1 2 0.50 cmeq d20, d21, #0 # CHECK-NEXT: 1 2 0.50 cmeq d20, d21, #0
# CHECK-NEXT: 1 2 0.50 cmeq d20, d21, d22 # CHECK-NEXT: 1 2 0.50 cmeq d20, d21, d22
# CHECK-NEXT: 1 2 1.00 cmeq v0.16b, v0.16b, #0 # CHECK-NEXT: 1 2 1.00 cmeq v0.16b, v0.16b, #0
# CHECK-NEXT: 1 2 1.00 cmeq v0.16b, v0.16b, v0.16b # CHECK-NEXT: 1 2 1.00 cmeq v0.16b, v0.16b, v0.16b
# CHECK-NEXT: 1 2 0.50 cmge d20, d21, #0 # CHECK-NEXT: 1 2 0.50 cmge d20, d21, #0
# CHECK-NEXT: 1 2 0.50 cmge d20, d21, d22 # CHECK-NEXT: 1 2 0.50 cmge d20, d21, d22
# CHECK-NEXT: 1 2 0.50 cmge v0.4h, v0.4h, v0.4h # CHECK-NEXT: 1 2 0.50 cmge v0.4h, v0.4h, v0.4h
# CHECK-NEXT: 1 2 0.50 cmge v0.8b, v0.8b, #0 # CHECK-NEXT: 1 2 0.50 cmge v0.8b, v0.8b, #0
# CHECK-NEXT: 1 2 0.50 cmgt d20, d21, #0 # CHECK-NEXT: 1 2 0.50 cmgt d20, d21, #0
# CHECK-NEXT: 1 2 0.50 cmgt d20, d21, d22 # CHECK-NEXT: 1 2 0.50 cmgt d20, d21, d22
# CHECK-NEXT: 1 2 0.50 cmgt v0.2s, v0.2s, #0 # CHECK-NEXT: 1 2 0.50 cmgt v0.2s, v0.2s, #0
# CHECK-NEXT: 1 2 1.00 cmgt v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 2 1.00 cmgt v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 2 0.50 cmhi d20, d21, d22 # CHECK-NEXT: 1 2 0.50 cmhi d20, d21, d22
# CHECK-NEXT: 1 2 1.00 cmhi v0.8h, v0.8h, v0.8h # CHECK-NEXT: 1 2 1.00 cmhi v0.8h, v0.8h, v0.8h
# CHECK-NEXT: 1 2 0.50 cmhs d20, d21, d22 # CHECK-NEXT: 1 2 0.50 cmhs d20, d21, d22
# CHECK-NEXT: 1 2 0.50 cmhs v0.8b, v0.8b, v0.8b # CHECK-NEXT: 1 2 0.50 cmhs v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 2 0.50 cmle d20, d21, #0 # CHECK-NEXT: 1 2 0.50 cmle d20, d21, #0
# CHECK-NEXT: 1 2 1.00 cmle v0.2d, v0.2d, #0 # CHECK-NEXT: 1 2 1.00 cmle v0.2d, v0.2d, #0
# CHECK-NEXT: 1 2 0.50 cmlt d20, d21, #0 # CHECK-NEXT: 1 2 0.50 cmlt d20, d21, #0
# CHECK-NEXT: 1 2 1.00 cmlt v0.8h, v0.8h, #0 # CHECK-NEXT: 1 2 1.00 cmlt v0.8h, v0.8h, #0
# CHECK-NEXT: 1 3 0.50 cmtst d20, d21, d22 # CHECK-NEXT: 1 3 0.50 cmtst d20, d21, d22
# CHECK-NEXT: 1 3 0.50 cmtst v0.2s, v0.2s, v0.2s # CHECK-NEXT: 1 3 0.50 cmtst v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 4 1.00 cnt v0.16b, v0.16b # CHECK-NEXT: 1 2 1.00 cnt v0.16b, v0.16b
# CHECK-NEXT: 1 4 0.50 cnt v0.8b, v0.8b # CHECK-NEXT: 1 2 0.50 cnt v0.8b, v0.8b
# CHECK-NEXT: 1 2 0.50 dup v0.16b, w28 # CHECK-NEXT: 1 2 0.50 dup v0.16b, w28
# CHECK-NEXT: 1 2 0.50 dup v0.2d, x28 # CHECK-NEXT: 1 2 0.50 dup v0.2d, x28
# CHECK-NEXT: 1 4 0.50 dup v0.2s, w28 # CHECK-NEXT: 1 4 0.50 dup v0.2s, w28
# CHECK-NEXT: 1 4 0.50 dup v0.4h, w28 # CHECK-NEXT: 1 4 0.50 dup v0.4h, w28
# CHECK-NEXT: 1 2 0.50 dup v0.4s, w28 # CHECK-NEXT: 1 2 0.50 dup v0.4s, w28
# CHECK-NEXT: 1 4 0.50 dup v0.8b, w28 # CHECK-NEXT: 1 4 0.50 dup v0.8b, w28
# CHECK-NEXT: 1 2 0.50 dup v0.8h, w28 # CHECK-NEXT: 1 2 0.50 dup v0.8h, w28
# CHECK-NEXT: 1 1 1.00 eor v0.16b, v0.16b, v0.16b # CHECK-NEXT: 1 1 1.00 eor v0.16b, v0.16b, v0.16b
# CHECK-NEXT: 1 4 1.00 ext v0.16b, v0.16b, v0.16b, #3 # CHECK-NEXT: 1 2 1.00 ext v0.16b, v0.16b, v0.16b, #3
# CHECK-NEXT: 1 4 0.50 ext v0.8b, v0.8b, v0.8b, #3 # CHECK-NEXT: 1 2 0.50 ext v0.8b, v0.8b, v0.8b, #3
# CHECK-NEXT: 1 4 0.50 fabd d29, d24, d20 # CHECK-NEXT: 1 4 0.50 fabd d29, d24, d20
# CHECK-NEXT: 1 4 0.50 fabd s29, s24, s20 # CHECK-NEXT: 1 4 0.50 fabd s29, s24, s20
# CHECK-NEXT: 1 4 1.00 fabd v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 4 1.00 fabd v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 4 1.00 fabs v0.2d, v0.2d # CHECK-NEXT: 1 4 1.00 fabs v0.2d, v0.2d
# CHECK-NEXT: 1 4 0.50 fabs v0.2s, v0.2s # CHECK-NEXT: 1 4 0.50 fabs v0.2s, v0.2s
# CHECK-NEXT: 1 4 0.50 fabs v0.4h, v0.4h # CHECK-NEXT: 1 4 0.50 fabs v0.4h, v0.4h
# CHECK-NEXT: 1 4 1.00 fabs v0.4s, v0.4s # CHECK-NEXT: 1 4 1.00 fabs v0.4s, v0.4s
# CHECK-NEXT: 1 4 1.00 fabs v0.8h, v0.8h # CHECK-NEXT: 1 4 1.00 fabs v0.8h, v0.8h
# CHECK-NEXT: 1 4 0.50 facge d20, d21, d22 # CHECK-NEXT: 1 2 0.50 facge d20, d21, d22
# CHECK-NEXT: 1 4 0.50 facge s10, s11, s12 # CHECK-NEXT: 1 2 0.50 facge s10, s11, s12
# CHECK-NEXT: 1 4 1.00 facge v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 2 1.00 facge v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 4 0.50 facgt d20, d21, d22 # CHECK-NEXT: 1 2 0.50 facgt d20, d21, d22
# CHECK-NEXT: 1 4 0.50 facgt s10, s11, s12 # CHECK-NEXT: 1 2 0.50 facgt s10, s11, s12
# CHECK-NEXT: 1 4 1.00 facgt v0.2d, v0.2d, v0.2d # CHECK-NEXT: 1 2 1.00 facgt v0.2d, v0.2d, v0.2d
# CHECK-NEXT: 1 4 1.00 fadd v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 4 1.00 fadd v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 4 0.50 faddp v0.2s, v0.2s, v0.2s # CHECK-NEXT: 1 4 0.50 faddp v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 4 1.00 faddp v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 4 1.00 faddp v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 4 0.50 fcmeq d20, d21, #0.0 # CHECK-NEXT: 1 2 0.50 fcmeq d20, d21, #0.0
# CHECK-NEXT: 1 4 0.50 fcmeq d20, d21, d22 # CHECK-NEXT: 1 2 0.50 fcmeq d20, d21, d22
# CHECK-NEXT: 1 4 0.50 fcmeq s10, s11, #0.0 # CHECK-NEXT: 1 2 0.50 fcmeq s10, s11, #0.0
# CHECK-NEXT: 1 4 0.50 fcmeq s10, s11, s12 # CHECK-NEXT: 1 2 0.50 fcmeq s10, s11, s12
# CHECK-NEXT: 1 4 0.50 fcmeq v0.2s, v0.2s, #0.0 # CHECK-NEXT: 1 2 0.50 fcmeq v0.2s, v0.2s, #0.0
# CHECK-NEXT: 1 4 0.50 fcmeq v0.2s, v0.2s, v0.2s # CHECK-NEXT: 1 2 0.50 fcmeq v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 4 0.50 fcmge d20, d21, #0.0 # CHECK-NEXT: 1 2 0.50 fcmge d20, d21, #0.0
# CHECK-NEXT: 1 4 0.50 fcmge d20, d21, d22 # CHECK-NEXT: 1 2 0.50 fcmge d20, d21, d22
# CHECK-NEXT: 1 4 0.50 fcmge s10, s11, #0.0 # CHECK-NEXT: 1 2 0.50 fcmge s10, s11, #0.0
# CHECK-NEXT: 1 4 0.50 fcmge s10, s11, s12 # CHECK-NEXT: 1 2 0.50 fcmge s10, s11, s12
# CHECK-NEXT: 1 4 1.00 fcmge v0.2d, v0.2d, #0.0 # CHECK-NEXT: 1 2 1.00 fcmge v0.2d, v0.2d, #0.0
# CHECK-NEXT: 1 4 1.00 fcmge v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 2 1.00 fcmge v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 4 0.50 fcmgt d20, d21, #0.0 # CHECK-NEXT: 1 2 0.50 fcmgt d20, d21, #0.0
# CHECK-NEXT: 1 4 0.50 fcmgt d20, d21, d22 # CHECK-NEXT: 1 2 0.50 fcmgt d20, d21, d22
# CHECK-NEXT: 1 4 0.50 fcmgt s10, s11, #0.0 # CHECK-NEXT: 1 2 0.50 fcmgt s10, s11, #0.0
# CHECK-NEXT: 1 4 0.50 fcmgt s10, s11, s12 # CHECK-NEXT: 1 2 0.50 fcmgt s10, s11, s12
# CHECK-NEXT: 1 4 1.00 fcmgt v0.4s, v0.4s, #0.0 # CHECK-NEXT: 1 2 1.00 fcmgt v0.4s, v0.4s, #0.0
# CHECK-NEXT: 1 4 1.00 fcmgt v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 2 1.00 fcmgt v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 4 0.50 fcmle d20, d21, #0.0 # CHECK-NEXT: 1 2 0.50 fcmle d20, d21, #0.0
# CHECK-NEXT: 1 4 0.50 fcmle s10, s11, #0.0 # CHECK-NEXT: 1 2 0.50 fcmle s10, s11, #0.0
# CHECK-NEXT: 1 4 1.00 fcmle v0.2d, v0.2d, #0.0 # CHECK-NEXT: 1 2 1.00 fcmle v0.2d, v0.2d, #0.0
# CHECK-NEXT: 1 4 0.50 fcmlt d20, d21, #0.0 # CHECK-NEXT: 1 2 0.50 fcmlt d20, d21, #0.0
# CHECK-NEXT: 1 4 0.50 fcmlt s10, s11, #0.0 # CHECK-NEXT: 1 2 0.50 fcmlt s10, s11, #0.0
# CHECK-NEXT: 1 4 1.00 fcmlt v0.4s, v0.4s, #0.0 # CHECK-NEXT: 1 2 1.00 fcmlt v0.4s, v0.4s, #0.0
# CHECK-NEXT: 1 4 0.50 fcvtas d21, d14 # CHECK-NEXT: 1 4 0.50 fcvtas d21, d14
# CHECK-NEXT: 1 4 0.50 fcvtas s12, s13 # CHECK-NEXT: 1 4 0.50 fcvtas s12, s13
# CHECK-NEXT: 1 4 0.50 fcvtas v0.2d, v0.2d # CHECK-NEXT: 1 4 0.50 fcvtas v0.2d, v0.2d
# CHECK-NEXT: 1 4 0.50 fcvtas v0.2s, v0.2s # CHECK-NEXT: 1 4 0.50 fcvtas v0.2s, v0.2s
# CHECK-NEXT: 1 4 0.50 fcvtas v0.4h, v0.4h # CHECK-NEXT: 1 4 0.50 fcvtas v0.4h, v0.4h
# CHECK-NEXT: 1 4 0.50 fcvtas v0.4s, v0.4s # CHECK-NEXT: 1 4 0.50 fcvtas v0.4s, v0.4s
# CHECK-NEXT: 1 4 0.50 fcvtas v0.8h, v0.8h # CHECK-NEXT: 1 4 0.50 fcvtas v0.8h, v0.8h
# CHECK-NEXT: 1 4 0.50 fcvtau d21, d14 # CHECK-NEXT: 1 4 0.50 fcvtau d21, d14
▲ Show 20 Lines • Show All 106 Lines • ▼ Show 20 Lines
# CHECK-NEXT: 1 4 0.50 fminp v0.2s, v0.2s, v0.2s # CHECK-NEXT: 1 4 0.50 fminp v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 4 1.00 fminp v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 4 1.00 fminp v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 4 0.50 fmla d0, d1, v0.d[1] # CHECK-NEXT: 1 4 0.50 fmla d0, d1, v0.d[1]
# CHECK-NEXT: 1 4 0.50 fmla s0, s1, v0.s[3] # CHECK-NEXT: 1 4 0.50 fmla s0, s1, v0.s[3]
# CHECK-NEXT: 1 4 0.50 fmla v0.2s, v0.2s, v0.2s # CHECK-NEXT: 1 4 0.50 fmla v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 4 0.50 fmls d0, d4, v0.d[1] # CHECK-NEXT: 1 4 0.50 fmls d0, d4, v0.d[1]
# CHECK-NEXT: 1 4 0.50 fmls s3, s5, v0.s[3] # CHECK-NEXT: 1 4 0.50 fmls s3, s5, v0.s[3]
# CHECK-NEXT: 1 4 0.50 fmls v0.2s, v0.2s, v0.2s # CHECK-NEXT: 1 4 0.50 fmls v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 4 1.00 fmov v0.2d, #-1.25000000 # CHECK-NEXT: 1 1 0.50 fmov v0.2d, #-1.25000000
# CHECK-NEXT: 1 4 0.50 fmov v0.2s, #13.00000000 # CHECK-NEXT: 1 1 0.50 fmov v0.2s, #13.00000000
# CHECK-NEXT: 1 4 1.00 fmov v0.4s, #1.00000000 # CHECK-NEXT: 1 1 0.50 fmov v0.4s, #1.00000000
# CHECK-NEXT: 1 4 0.50 fmul d0, d1, v0.d[1] # CHECK-NEXT: 1 4 1.00 fmul d0, d1, v0.d[1]
# CHECK-NEXT: 1 4 0.50 fmul s0, s1, v0.s[3] # CHECK-NEXT: 1 4 1.00 fmul s0, s1, v0.s[3]
# CHECK-NEXT: 1 4 0.50 fmul v0.2s, v0.2s, v0.2s # CHECK-NEXT: 1 4 0.50 fmul v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 4 0.50 fmulx d0, d4, v0.d[1] # CHECK-NEXT: 1 4 1.00 fmulx d0, d4, v0.d[1]
# CHECK-NEXT: 1 4 0.50 fmulx d23, d11, d1 # CHECK-NEXT: 1 4 0.50 fmulx d23, d11, d1
# CHECK-NEXT: 1 4 0.50 fmulx s20, s22, s15 # CHECK-NEXT: 1 4 0.50 fmulx s20, s22, s15
# CHECK-NEXT: 1 4 0.50 fmulx s3, s5, v0.s[3] # CHECK-NEXT: 1 4 1.00 fmulx s3, s5, v0.s[3]
# CHECK-NEXT: 1 4 1.00 fmulx v0.2d, v0.2d, v0.2d # CHECK-NEXT: 1 4 1.00 fmulx v0.2d, v0.2d, v0.2d
# CHECK-NEXT: 1 4 0.50 fmulx v0.2s, v0.2s, v0.2s # CHECK-NEXT: 1 4 0.50 fmulx v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 4 1.00 fmulx v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 4 1.00 fmulx v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 4 1.00 fneg v0.2d, v0.2d # CHECK-NEXT: 1 4 1.00 fneg v0.2d, v0.2d
# CHECK-NEXT: 1 4 0.50 fneg v0.2s, v0.2s # CHECK-NEXT: 1 4 0.50 fneg v0.2s, v0.2s
# CHECK-NEXT: 1 4 0.50 fneg v0.4h, v0.4h # CHECK-NEXT: 1 4 0.50 fneg v0.4h, v0.4h
# CHECK-NEXT: 1 4 1.00 fneg v0.4s, v0.4s # CHECK-NEXT: 1 4 1.00 fneg v0.4s, v0.4s
# CHECK-NEXT: 1 4 1.00 fneg v0.8h, v0.8h # CHECK-NEXT: 1 4 1.00 fneg v0.8h, v0.8h
▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
# CHECK-NEXT: 1 4 0.50 mla v0.8b, v0.8b, v0.8b # CHECK-NEXT: 1 4 0.50 mla v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 4 0.50 mls v0.4h, v0.4h, v0.4h # CHECK-NEXT: 1 4 0.50 mls v0.4h, v0.4h, v0.4h
# CHECK-NEXT: 1 4 0.50 mov b0, v0.b[15] # CHECK-NEXT: 1 4 0.50 mov b0, v0.b[15]
# CHECK-NEXT: 1 4 0.50 mov d6, v0.d[1] # CHECK-NEXT: 1 4 0.50 mov d6, v0.d[1]
# CHECK-NEXT: 1 4 0.50 mov h2, v0.h[5] # CHECK-NEXT: 1 4 0.50 mov h2, v0.h[5]
# CHECK-NEXT: 1 4 0.50 mov s17, v0.s[2] # CHECK-NEXT: 1 4 0.50 mov s17, v0.s[2]
# CHECK-NEXT: 1 1 1.00 mov v0.16b, v0.16b # CHECK-NEXT: 1 1 1.00 mov v0.16b, v0.16b
# CHECK-NEXT: 1 1 0.50 mov v0.8b, v0.8b # CHECK-NEXT: 1 1 0.50 mov v0.8b, v0.8b
# CHECK-NEXT: 1 4 0.50 movi d15, #0xff00ff00ff00ff # CHECK-NEXT: 1 1 0.50 movi d15, #0xff00ff00ff00ff
# CHECK-NEXT: 1 4 1.00 movi v0.16b, #31 # CHECK-NEXT: 1 1 1.00 movi v0.16b, #31
# CHECK-NEXT: 1 4 1.00 movi v0.2d, #0xff0000ff0000ffff # CHECK-NEXT: 1 1 1.00 movi v0.2d, #0xff0000ff0000ffff
# CHECK-NEXT: 1 4 0.50 movi v0.2s, #8, msl #8 # CHECK-NEXT: 1 1 0.50 movi v0.2s, #8, msl #8
# CHECK-NEXT: 1 4 1.00 movi v0.4s, #255, lsl #24 # CHECK-NEXT: 1 1 1.00 movi v0.4s, #255, lsl #24
# CHECK-NEXT: 1 4 0.50 movi v0.8b, #255 # CHECK-NEXT: 1 1 0.50 movi v0.8b, #255
# CHECK-NEXT: 1 4 0.50 mul v0.8b, v0.8b, v0.8b # CHECK-NEXT: 1 4 0.50 mul v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 1 0.50 mvni v0.2s, #0 # CHECK-NEXT: 1 1 0.50 mvni v0.2s, #0
# CHECK-NEXT: 1 1 1.00 mvni v0.4s, #16, msl #16 # CHECK-NEXT: 1 1 1.00 mvni v0.4s, #16, msl #16
# CHECK-NEXT: 1 2 0.50 neg d29, d24 # CHECK-NEXT: 1 2 0.50 neg d29, d24
# CHECK-NEXT: 1 2 1.00 neg v0.16b, v0.16b # CHECK-NEXT: 1 2 1.00 neg v0.16b, v0.16b
# CHECK-NEXT: 1 2 1.00 neg v0.2d, v0.2d # CHECK-NEXT: 1 2 1.00 neg v0.2d, v0.2d
# CHECK-NEXT: 1 2 0.50 neg v0.2s, v0.2s # CHECK-NEXT: 1 2 0.50 neg v0.2s, v0.2s
# CHECK-NEXT: 1 2 0.50 neg v0.4h, v0.4h # CHECK-NEXT: 1 2 0.50 neg v0.4h, v0.4h
Show All 10 Lines
# CHECK-NEXT: 1 3 1.00 pmull v0.8h, v0.8b, v0.8b # CHECK-NEXT: 1 3 1.00 pmull v0.8h, v0.8b, v0.8b
# CHECK-NEXT: 1 3 1.00 pmull2 v0.8h, v0.16b, v0.16b # CHECK-NEXT: 1 3 1.00 pmull2 v0.8h, v0.16b, v0.16b
# CHECK-NEXT: 1 4 2.00 raddhn v0.2s, v0.2d, v0.2d # CHECK-NEXT: 1 4 2.00 raddhn v0.2s, v0.2d, v0.2d
# CHECK-NEXT: 1 4 2.00 raddhn v0.4h, v0.4s, v0.4s # CHECK-NEXT: 1 4 2.00 raddhn v0.4h, v0.4s, v0.4s
# CHECK-NEXT: 1 4 2.00 raddhn v0.8b, v0.8h, v0.8h # CHECK-NEXT: 1 4 2.00 raddhn v0.8b, v0.8h, v0.8h
# CHECK-NEXT: 1 4 2.00 raddhn2 v0.16b, v0.8h, v0.8h # CHECK-NEXT: 1 4 2.00 raddhn2 v0.16b, v0.8h, v0.8h
# CHECK-NEXT: 1 4 2.00 raddhn2 v0.4s, v0.2d, v0.2d # CHECK-NEXT: 1 4 2.00 raddhn2 v0.4s, v0.2d, v0.2d
# CHECK-NEXT: 1 4 2.00 raddhn2 v0.8h, v0.4s, v0.4s # CHECK-NEXT: 1 4 2.00 raddhn2 v0.8h, v0.4s, v0.4s
# CHECK-NEXT: 1 4 1.00 rbit v0.16b, v0.16b # CHECK-NEXT: 1 2 1.00 rbit v0.16b, v0.16b
# CHECK-NEXT: 1 4 0.50 rbit v0.8b, v0.8b # CHECK-NEXT: 1 2 0.50 rbit v0.8b, v0.8b
# CHECK-NEXT: 1 4 0.50 rev16 v21.8b, v1.8b # CHECK-NEXT: 1 2 0.50 rev16 v21.8b, v1.8b
# CHECK-NEXT: 1 4 1.00 rev16 v30.16b, v31.16b # CHECK-NEXT: 1 2 1.00 rev16 v30.16b, v31.16b
# CHECK-NEXT: 1 4 0.50 rev32 v0.4h, v9.4h # CHECK-NEXT: 1 2 0.50 rev32 v0.4h, v9.4h
# CHECK-NEXT: 1 4 0.50 rev32 v21.8b, v1.8b # CHECK-NEXT: 1 2 0.50 rev32 v21.8b, v1.8b
# CHECK-NEXT: 1 4 1.00 rev32 v30.16b, v31.16b # CHECK-NEXT: 1 2 1.00 rev32 v30.16b, v31.16b
# CHECK-NEXT: 1 4 1.00 rev32 v4.8h, v7.8h # CHECK-NEXT: 1 2 1.00 rev32 v4.8h, v7.8h
# CHECK-NEXT: 1 4 1.00 rev64 v0.16b, v31.16b # CHECK-NEXT: 1 2 1.00 rev64 v0.16b, v31.16b
# CHECK-NEXT: 1 4 0.50 rev64 v1.8b, v9.8b # CHECK-NEXT: 1 2 0.50 rev64 v1.8b, v9.8b
# CHECK-NEXT: 1 4 0.50 rev64 v13.4h, v21.4h # CHECK-NEXT: 1 2 0.50 rev64 v13.4h, v21.4h
# CHECK-NEXT: 1 4 1.00 rev64 v2.8h, v4.8h # CHECK-NEXT: 1 2 1.00 rev64 v2.8h, v4.8h
# CHECK-NEXT: 1 4 0.50 rev64 v4.2s, v0.2s # CHECK-NEXT: 1 2 0.50 rev64 v4.2s, v0.2s
# CHECK-NEXT: 1 4 1.00 rev64 v6.4s, v8.4s # CHECK-NEXT: 1 2 1.00 rev64 v6.4s, v8.4s
# CHECK-NEXT: 1 3 0.50 rshrn v0.2s, v0.2d, #3 # CHECK-NEXT: 1 3 0.50 rshrn v0.2s, v0.2d, #3
# CHECK-NEXT: 1 3 0.50 rshrn v0.4h, v0.4s, #3 # CHECK-NEXT: 1 3 0.50 rshrn v0.4h, v0.4s, #3
# CHECK-NEXT: 1 3 0.50 rshrn v0.8b, v0.8h, #3 # CHECK-NEXT: 1 3 0.50 rshrn v0.8b, v0.8h, #3
# CHECK-NEXT: 1 3 1.00 rshrn2 v0.16b, v0.8h, #3 # CHECK-NEXT: 1 3 1.00 rshrn2 v0.16b, v0.8h, #3
# CHECK-NEXT: 1 3 1.00 rshrn2 v0.4s, v0.2d, #3 # CHECK-NEXT: 1 3 1.00 rshrn2 v0.4s, v0.2d, #3
# CHECK-NEXT: 1 3 1.00 rshrn2 v0.8h, v0.4s, #3 # CHECK-NEXT: 1 3 1.00 rshrn2 v0.8h, v0.4s, #3
# CHECK-NEXT: 1 4 2.00 rsubhn v0.2s, v0.2d, v0.2d # CHECK-NEXT: 1 4 2.00 rsubhn v0.2s, v0.2d, v0.2d
# CHECK-NEXT: 1 4 2.00 rsubhn v0.4h, v0.4s, v0.4s # CHECK-NEXT: 1 4 2.00 rsubhn v0.4h, v0.4s, v0.4s
▲ Show 20 Lines • Show All 243 Lines • ▼ Show 20 Lines
# CHECK-NEXT: 1 4 0.50 sqshrun v0.8b, v0.8h, #3 # CHECK-NEXT: 1 4 0.50 sqshrun v0.8b, v0.8h, #3
# CHECK-NEXT: 1 4 1.00 sqshrun2 v0.16b, v0.8h, #3 # CHECK-NEXT: 1 4 1.00 sqshrun2 v0.16b, v0.8h, #3
# CHECK-NEXT: 1 4 1.00 sqshrun2 v0.4s, v0.2d, #3 # CHECK-NEXT: 1 4 1.00 sqshrun2 v0.4s, v0.2d, #3
# CHECK-NEXT: 1 4 1.00 sqshrun2 v0.8h, v0.4s, #3 # CHECK-NEXT: 1 4 1.00 sqshrun2 v0.8h, v0.4s, #3
# CHECK-NEXT: 1 3 0.50 sqsub s20, s10, s7 # CHECK-NEXT: 1 3 0.50 sqsub s20, s10, s7
# CHECK-NEXT: 1 3 1.00 sqsub v0.2d, v0.2d, v0.2d # CHECK-NEXT: 1 3 1.00 sqsub v0.2d, v0.2d, v0.2d
# CHECK-NEXT: 1 3 1.00 sqsub v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 3 1.00 sqsub v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 3 0.50 sqsub v0.8b, v0.8b, v0.8b # CHECK-NEXT: 1 3 0.50 sqsub v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 4 0.50 sqxtn b18, h18 # CHECK-NEXT: 1 2 0.50 sqxtn b18, h18
# CHECK-NEXT: 1 4 0.50 sqxtn h20, s17 # CHECK-NEXT: 1 2 0.50 sqxtn h20, s17
# CHECK-NEXT: 1 4 0.50 sqxtn s19, d14 # CHECK-NEXT: 1 2 0.50 sqxtn s19, d14
# CHECK-NEXT: 1 4 1.00 sqxtn v0.2s, v0.2d # CHECK-NEXT: 1 2 0.50 sqxtn v0.2s, v0.2d
# CHECK-NEXT: 1 4 1.00 sqxtn v0.4h, v0.4s # CHECK-NEXT: 1 2 0.50 sqxtn v0.4h, v0.4s
# CHECK-NEXT: 1 4 1.00 sqxtn v0.8b, v0.8h # CHECK-NEXT: 1 2 0.50 sqxtn v0.8b, v0.8h
# CHECK-NEXT: 1 4 1.00 sqxtn2 v0.16b, v0.8h # CHECK-NEXT: 1 2 0.50 sqxtn2 v0.16b, v0.8h
# CHECK-NEXT: 1 4 1.00 sqxtn2 v0.4s, v0.2d # CHECK-NEXT: 1 2 0.50 sqxtn2 v0.4s, v0.2d
# CHECK-NEXT: 1 4 1.00 sqxtn2 v0.8h, v0.4s # CHECK-NEXT: 1 2 0.50 sqxtn2 v0.8h, v0.4s
# CHECK-NEXT: 1 4 0.50 sqxtun b19, h14 # CHECK-NEXT: 1 2 0.50 sqxtun b19, h14
# CHECK-NEXT: 1 4 0.50 sqxtun h21, s15 # CHECK-NEXT: 1 2 0.50 sqxtun h21, s15
# CHECK-NEXT: 1 4 0.50 sqxtun s20, d12 # CHECK-NEXT: 1 2 0.50 sqxtun s20, d12
# CHECK-NEXT: 1 4 1.00 sqxtun v0.2s, v0.2d # CHECK-NEXT: 1 2 0.50 sqxtun v0.2s, v0.2d
# CHECK-NEXT: 1 4 1.00 sqxtun v0.4h, v0.4s # CHECK-NEXT: 1 2 0.50 sqxtun v0.4h, v0.4s
# CHECK-NEXT: 1 4 1.00 sqxtun v0.8b, v0.8h # CHECK-NEXT: 1 2 0.50 sqxtun v0.8b, v0.8h
# CHECK-NEXT: 1 4 1.00 sqxtun2 v0.16b, v0.8h # CHECK-NEXT: 1 2 0.50 sqxtun2 v0.16b, v0.8h
# CHECK-NEXT: 1 4 1.00 sqxtun2 v0.4s, v0.2d # CHECK-NEXT: 1 2 0.50 sqxtun2 v0.4s, v0.2d
# CHECK-NEXT: 1 4 1.00 sqxtun2 v0.8h, v0.4s # CHECK-NEXT: 1 2 0.50 sqxtun2 v0.8h, v0.4s
# CHECK-NEXT: 1 2 0.50 srhadd v0.2s, v0.2s, v0.2s # CHECK-NEXT: 1 2 0.50 srhadd v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 2 0.50 srhadd v0.4h, v0.4h, v0.4h # CHECK-NEXT: 1 2 0.50 srhadd v0.4h, v0.4h, v0.4h
# CHECK-NEXT: 1 2 0.50 srhadd v0.8b, v0.8b, v0.8b # CHECK-NEXT: 1 2 0.50 srhadd v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 2 0.50 sri d10, d12, #14 # CHECK-NEXT: 1 2 0.50 sri d10, d12, #14
# CHECK-NEXT: 1 4 1.00 sri v0.16b, v0.16b, #3 # CHECK-NEXT: 1 4 1.00 sri v0.16b, v0.16b, #3
# CHECK-NEXT: 1 4 1.00 sri v0.2d, v0.2d, #3 # CHECK-NEXT: 1 4 1.00 sri v0.2d, v0.2d, #3
# CHECK-NEXT: 1 4 0.50 sri v0.2s, v0.2s, #3 # CHECK-NEXT: 1 4 0.50 sri v0.2s, v0.2s, #3
# CHECK-NEXT: 1 4 0.50 sri v0.4h, v0.4h, #3 # CHECK-NEXT: 1 4 0.50 sri v0.4h, v0.4h, #3
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
# CHECK-NEXT: 1 3 0.50 suqadd s21, s12 # CHECK-NEXT: 1 3 0.50 suqadd s21, s12
# CHECK-NEXT: 1 3 1.00 suqadd v0.16b, v0.16b # CHECK-NEXT: 1 3 1.00 suqadd v0.16b, v0.16b
# CHECK-NEXT: 1 3 1.00 suqadd v0.2d, v0.2d # CHECK-NEXT: 1 3 1.00 suqadd v0.2d, v0.2d
# CHECK-NEXT: 1 3 0.50 suqadd v0.2s, v0.2s # CHECK-NEXT: 1 3 0.50 suqadd v0.2s, v0.2s
# CHECK-NEXT: 1 3 0.50 suqadd v0.4h, v0.4h # CHECK-NEXT: 1 3 0.50 suqadd v0.4h, v0.4h
# CHECK-NEXT: 1 3 1.00 suqadd v0.4s, v0.4s # CHECK-NEXT: 1 3 1.00 suqadd v0.4s, v0.4s
# CHECK-NEXT: 1 3 0.50 suqadd v0.8b, v0.8b # CHECK-NEXT: 1 3 0.50 suqadd v0.8b, v0.8b
# CHECK-NEXT: 1 3 1.00 suqadd v0.8h, v0.8h # CHECK-NEXT: 1 3 1.00 suqadd v0.8h, v0.8h
# CHECK-NEXT: 1 4 1.00 tbl v0.16b, { v0.16b }, v0.16b # CHECK-NEXT: 1 2 1.00 tbl v0.16b, { v0.16b }, v0.16b
# CHECK-NEXT: 1 4 1.00 tbl v0.16b, { v0.16b, v1.16b }, v0.16b # CHECK-NEXT: 1 3 2.00 tbl v0.16b, { v0.16b, v1.16b }, v0.16b
# CHECK-NEXT: 1 4 1.00 tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b # CHECK-NEXT: 1 4 3.00 tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b
# CHECK-NEXT: 1 4 1.00 tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b # CHECK-NEXT: 1 5 4.00 tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b
# CHECK-NEXT: 1 4 0.50 tbl v0.8b, { v0.16b }, v0.8b # CHECK-NEXT: 1 2 1.00 tbl v0.8b, { v0.16b }, v0.8b
# CHECK-NEXT: 1 4 0.50 tbl v0.8b, { v0.16b, v1.16b }, v0.8b # CHECK-NEXT: 1 3 2.00 tbl v0.8b, { v0.16b, v1.16b }, v0.8b
# CHECK-NEXT: 1 4 0.50 tbl v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b # CHECK-NEXT: 1 4 3.00 tbl v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b
# CHECK-NEXT: 1 4 0.50 tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b # CHECK-NEXT: 1 5 4.00 tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b
# CHECK-NEXT: 1 4 1.00 tbx v0.16b, { v0.16b }, v0.16b # CHECK-NEXT: 1 3 2.00 tbx v0.16b, { v0.16b }, v0.16b
# CHECK-NEXT: 1 4 1.00 tbx v0.16b, { v0.16b, v1.16b }, v0.16b # CHECK-NEXT: 1 4 3.00 tbx v0.16b, { v0.16b, v1.16b }, v0.16b
# CHECK-NEXT: 1 4 1.00 tbx v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b # CHECK-NEXT: 1 5 4.00 tbx v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b
# CHECK-NEXT: 1 4 1.00 tbx v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b # CHECK-NEXT: 1 6 5.00 tbx v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b
# CHECK-NEXT: 1 4 0.50 tbx v0.8b, { v0.16b }, v0.8b # CHECK-NEXT: 1 3 2.00 tbx v0.8b, { v0.16b }, v0.8b
# CHECK-NEXT: 1 4 0.50 tbx v0.8b, { v0.16b, v1.16b }, v0.8b # CHECK-NEXT: 1 4 3.00 tbx v0.8b, { v0.16b, v1.16b }, v0.8b
# CHECK-NEXT: 1 4 0.50 tbx v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b # CHECK-NEXT: 1 5 4.00 tbx v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b
# CHECK-NEXT: 1 4 0.50 tbx v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b # CHECK-NEXT: 1 6 5.00 tbx v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b
# CHECK-NEXT: 1 4 1.00 trn1 v0.16b, v0.16b, v0.16b # CHECK-NEXT: 1 2 1.00 trn1 v0.16b, v0.16b, v0.16b
# CHECK-NEXT: 1 4 1.00 trn1 v0.2d, v0.2d, v0.2d # CHECK-NEXT: 1 2 1.00 trn1 v0.2d, v0.2d, v0.2d
# CHECK-NEXT: 1 4 0.50 trn1 v0.2s, v0.2s, v0.2s # CHECK-NEXT: 1 2 1.00 trn1 v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 4 0.50 trn1 v0.4h, v0.4h, v0.4h # CHECK-NEXT: 1 2 0.50 trn1 v0.4h, v0.4h, v0.4h
# CHECK-NEXT: 1 4 1.00 trn1 v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 2 1.00 trn1 v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 4 0.50 trn1 v0.8b, v0.8b, v0.8b # CHECK-NEXT: 1 2 0.50 trn1 v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 4 1.00 trn1 v0.8h, v0.8h, v0.8h # CHECK-NEXT: 1 2 1.00 trn1 v0.8h, v0.8h, v0.8h
# CHECK-NEXT: 1 4 1.00 trn2 v0.16b, v0.16b, v0.16b # CHECK-NEXT: 1 2 1.00 trn2 v0.16b, v0.16b, v0.16b
# CHECK-NEXT: 1 4 1.00 trn2 v0.2d, v0.2d, v0.2d # CHECK-NEXT: 1 2 1.00 trn2 v0.2d, v0.2d, v0.2d
# CHECK-NEXT: 1 4 0.50 trn2 v0.2s, v0.2s, v0.2s # CHECK-NEXT: 1 2 1.00 trn2 v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 4 0.50 trn2 v0.4h, v0.4h, v0.4h # CHECK-NEXT: 1 2 0.50 trn2 v0.4h, v0.4h, v0.4h
# CHECK-NEXT: 1 4 1.00 trn2 v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 2 1.00 trn2 v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 4 0.50 trn2 v0.8b, v0.8b, v0.8b # CHECK-NEXT: 1 2 0.50 trn2 v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 4 1.00 trn2 v0.8h, v0.8h, v0.8h # CHECK-NEXT: 1 2 1.00 trn2 v0.8h, v0.8h, v0.8h
# CHECK-NEXT: 1 4 2.00 uaba v0.8b, v0.8b, v0.8b # CHECK-NEXT: 1 4 2.00 uaba v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 4 2.00 uabal v0.2d, v0.2s, v0.2s # CHECK-NEXT: 1 4 2.00 uabal v0.2d, v0.2s, v0.2s
# CHECK-NEXT: 1 4 2.00 uabal v0.4s, v0.4h, v0.4h # CHECK-NEXT: 1 4 2.00 uabal v0.4s, v0.4h, v0.4h
# CHECK-NEXT: 1 4 2.00 uabal v0.8h, v0.8b, v0.8b # CHECK-NEXT: 1 4 2.00 uabal v0.8h, v0.8b, v0.8b
# CHECK-NEXT: 1 4 2.00 uabal2 v0.2d, v0.4s, v0.4s # CHECK-NEXT: 1 4 2.00 uabal2 v0.2d, v0.4s, v0.4s
# CHECK-NEXT: 1 4 2.00 uabal2 v0.4s, v0.8h, v0.8h # CHECK-NEXT: 1 4 2.00 uabal2 v0.4s, v0.8h, v0.8h
# CHECK-NEXT: 1 4 2.00 uabal2 v0.8h, v0.16b, v0.16b # CHECK-NEXT: 1 4 2.00 uabal2 v0.8h, v0.16b, v0.16b
# CHECK-NEXT: 1 3 0.50 uabd v0.4h, v0.4h, v0.4h # CHECK-NEXT: 1 3 0.50 uabd v0.4h, v0.4h, v0.4h
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
# CHECK-NEXT: 1 4 0.50 uqshrn v0.2s, v0.2d, #3 # CHECK-NEXT: 1 4 0.50 uqshrn v0.2s, v0.2d, #3
# CHECK-NEXT: 1 4 0.50 uqshrn v0.4h, v0.4s, #3 # CHECK-NEXT: 1 4 0.50 uqshrn v0.4h, v0.4s, #3
# CHECK-NEXT: 1 4 0.50 uqshrn v0.8b, v0.8h, #3 # CHECK-NEXT: 1 4 0.50 uqshrn v0.8b, v0.8h, #3
# CHECK-NEXT: 1 4 1.00 uqshrn2 v0.16b, v0.8h, #3 # CHECK-NEXT: 1 4 1.00 uqshrn2 v0.16b, v0.8h, #3
# CHECK-NEXT: 1 4 1.00 uqshrn2 v0.4s, v0.2d, #3 # CHECK-NEXT: 1 4 1.00 uqshrn2 v0.4s, v0.2d, #3
# CHECK-NEXT: 1 4 1.00 uqshrn2 v0.8h, v0.4s, #3 # CHECK-NEXT: 1 4 1.00 uqshrn2 v0.8h, v0.4s, #3
# CHECK-NEXT: 1 3 0.50 uqsub d16, d16, d16 # CHECK-NEXT: 1 3 0.50 uqsub d16, d16, d16
# CHECK-NEXT: 1 3 0.50 uqsub v0.4h, v0.4h, v0.4h # CHECK-NEXT: 1 3 0.50 uqsub v0.4h, v0.4h, v0.4h
# CHECK-NEXT: 1 4 0.50 uqxtn b18, h18 # CHECK-NEXT: 1 2 0.50 uqxtn b18, h18
# CHECK-NEXT: 1 4 0.50 uqxtn h20, s17 # CHECK-NEXT: 1 2 0.50 uqxtn h20, s17
# CHECK-NEXT: 1 4 0.50 uqxtn s19, d14 # CHECK-NEXT: 1 2 0.50 uqxtn s19, d14
# CHECK-NEXT: 1 4 1.00 uqxtn v0.2s, v0.2d # CHECK-NEXT: 1 2 0.50 uqxtn v0.2s, v0.2d
# CHECK-NEXT: 1 4 1.00 uqxtn v0.4h, v0.4s # CHECK-NEXT: 1 2 0.50 uqxtn v0.4h, v0.4s
# CHECK-NEXT: 1 4 1.00 uqxtn v0.8b, v0.8h # CHECK-NEXT: 1 2 0.50 uqxtn v0.8b, v0.8h
# CHECK-NEXT: 1 4 1.00 uqxtn2 v0.16b, v0.8h # CHECK-NEXT: 1 2 0.50 uqxtn2 v0.16b, v0.8h
# CHECK-NEXT: 1 4 1.00 uqxtn2 v0.4s, v0.2d # CHECK-NEXT: 1 2 0.50 uqxtn2 v0.4s, v0.2d
# CHECK-NEXT: 1 4 1.00 uqxtn2 v0.8h, v0.4s # CHECK-NEXT: 1 2 0.50 uqxtn2 v0.8h, v0.4s
# CHECK-NEXT: 1 4 0.50 urecpe v0.2s, v0.2s # CHECK-NEXT: 1 4 0.50 urecpe v0.2s, v0.2s
# CHECK-NEXT: 1 4 1.00 urecpe v0.4s, v0.4s # CHECK-NEXT: 1 4 1.00 urecpe v0.4s, v0.4s
# CHECK-NEXT: 1 2 1.00 urhadd v0.16b, v0.16b, v0.16b # CHECK-NEXT: 1 2 1.00 urhadd v0.16b, v0.16b, v0.16b
# CHECK-NEXT: 1 2 1.00 urhadd v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 2 1.00 urhadd v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 2 1.00 urhadd v0.8h, v0.8h, v0.8h # CHECK-NEXT: 1 2 1.00 urhadd v0.8h, v0.8h, v0.8h
# CHECK-NEXT: 1 3 0.50 urshl d8, d7, d4 # CHECK-NEXT: 1 3 0.50 urshl d8, d7, d4
# CHECK-NEXT: 1 3 1.00 urshl v0.16b, v0.16b, v0.16b # CHECK-NEXT: 1 3 1.00 urshl v0.16b, v0.16b, v0.16b
# CHECK-NEXT: 1 3 1.00 urshl v0.2d, v0.2d, v0.2d # CHECK-NEXT: 1 3 1.00 urshl v0.2d, v0.2d, v0.2d
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
# CHECK-NEXT: 1 3 1.00 usubl2 v0.4s, v0.8h, v0.8h # CHECK-NEXT: 1 3 1.00 usubl2 v0.4s, v0.8h, v0.8h
# CHECK-NEXT: 1 3 1.00 usubl2 v0.8h, v0.16b, v0.16b # CHECK-NEXT: 1 3 1.00 usubl2 v0.8h, v0.16b, v0.16b
# CHECK-NEXT: 1 3 1.00 usubw v0.2d, v0.2d, v0.2s # CHECK-NEXT: 1 3 1.00 usubw v0.2d, v0.2d, v0.2s
# CHECK-NEXT: 1 3 1.00 usubw v0.4s, v0.4s, v0.4h # CHECK-NEXT: 1 3 1.00 usubw v0.4s, v0.4s, v0.4h
# CHECK-NEXT: 1 3 1.00 usubw v0.8h, v0.8h, v0.8b # CHECK-NEXT: 1 3 1.00 usubw v0.8h, v0.8h, v0.8b
# CHECK-NEXT: 1 3 1.00 usubw2 v0.2d, v0.2d, v0.4s # CHECK-NEXT: 1 3 1.00 usubw2 v0.2d, v0.2d, v0.4s
# CHECK-NEXT: 1 3 1.00 usubw2 v0.4s, v0.4s, v0.8h # CHECK-NEXT: 1 3 1.00 usubw2 v0.4s, v0.4s, v0.8h
# CHECK-NEXT: 1 3 1.00 usubw2 v0.8h, v0.8h, v0.16b # CHECK-NEXT: 1 3 1.00 usubw2 v0.8h, v0.8h, v0.16b
# CHECK-NEXT: 1 4 1.00 uzp1 v0.16b, v0.16b, v0.16b # CHECK-NEXT: 1 2 1.00 uzp1 v0.16b, v0.16b, v0.16b
# CHECK-NEXT: 1 4 1.00 uzp1 v0.2d, v0.2d, v0.2d # CHECK-NEXT: 1 2 1.00 uzp1 v0.2d, v0.2d, v0.2d
# CHECK-NEXT: 1 4 0.50 uzp1 v0.2s, v0.2s, v0.2s # CHECK-NEXT: 1 2 0.50 uzp1 v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 4 0.50 uzp1 v0.4h, v0.4h, v0.4h # CHECK-NEXT: 1 2 0.50 uzp1 v0.4h, v0.4h, v0.4h
# CHECK-NEXT: 1 4 1.00 uzp1 v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 2 1.00 uzp1 v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 4 0.50 uzp1 v0.8b, v0.8b, v0.8b # CHECK-NEXT: 1 2 0.50 uzp1 v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 4 1.00 uzp1 v0.8h, v0.8h, v0.8h # CHECK-NEXT: 1 2 1.00 uzp1 v0.8h, v0.8h, v0.8h
# CHECK-NEXT: 1 4 1.00 uzp2 v0.16b, v0.16b, v0.16b # CHECK-NEXT: 1 2 1.00 uzp2 v0.16b, v0.16b, v0.16b
# CHECK-NEXT: 1 4 1.00 uzp2 v0.2d, v0.2d, v0.2d # CHECK-NEXT: 1 2 1.00 uzp2 v0.2d, v0.2d, v0.2d
# CHECK-NEXT: 1 4 0.50 uzp2 v0.2s, v0.2s, v0.2s # CHECK-NEXT: 1 2 0.50 uzp2 v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 4 0.50 uzp2 v0.4h, v0.4h, v0.4h # CHECK-NEXT: 1 2 0.50 uzp2 v0.4h, v0.4h, v0.4h
# CHECK-NEXT: 1 4 1.00 uzp2 v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 2 1.00 uzp2 v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 4 0.50 uzp2 v0.8b, v0.8b, v0.8b # CHECK-NEXT: 1 2 0.50 uzp2 v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 4 1.00 uzp2 v0.8h, v0.8h, v0.8h # CHECK-NEXT: 1 2 1.00 uzp2 v0.8h, v0.8h, v0.8h
# CHECK-NEXT: 1 2 0.50 xtn v0.2s, v0.2d # CHECK-NEXT: 1 2 0.50 xtn v0.2s, v0.2d
# CHECK-NEXT: 1 2 0.50 xtn v0.4h, v0.4s # CHECK-NEXT: 1 2 0.50 xtn v0.4h, v0.4s
# CHECK-NEXT: 1 2 0.50 xtn v0.8b, v0.8h # CHECK-NEXT: 1 2 0.50 xtn v0.8b, v0.8h
# CHECK-NEXT: 1 2 0.50 xtn2 v0.16b, v0.8h # CHECK-NEXT: 1 2 0.50 xtn2 v0.16b, v0.8h
# CHECK-NEXT: 1 2 0.50 xtn2 v0.4s, v0.2d # CHECK-NEXT: 1 2 0.50 xtn2 v0.4s, v0.2d
# CHECK-NEXT: 1 2 0.50 xtn2 v0.8h, v0.4s # CHECK-NEXT: 1 2 0.50 xtn2 v0.8h, v0.4s
# CHECK-NEXT: 1 4 1.00 zip1 v0.16b, v0.16b, v0.16b # CHECK-NEXT: 1 2 1.00 zip1 v0.16b, v0.16b, v0.16b
# CHECK-NEXT: 1 4 1.00 zip1 v0.2d, v0.2d, v0.2d # CHECK-NEXT: 1 2 1.00 zip1 v0.2d, v0.2d, v0.2d
# CHECK-NEXT: 1 4 0.50 zip1 v0.2s, v0.2s, v0.2s # CHECK-NEXT: 1 2 0.50 zip1 v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 4 0.50 zip1 v0.4h, v0.4h, v0.4h # CHECK-NEXT: 1 2 0.50 zip1 v0.4h, v0.4h, v0.4h
# CHECK-NEXT: 1 4 1.00 zip1 v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 2 1.00 zip1 v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 4 0.50 zip1 v0.8b, v0.8b, v0.8b # CHECK-NEXT: 1 2 0.50 zip1 v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 4 1.00 zip1 v0.8h, v0.8h, v0.8h # CHECK-NEXT: 1 2 1.00 zip1 v0.8h, v0.8h, v0.8h
# CHECK-NEXT: 1 4 1.00 zip2 v0.16b, v0.16b, v0.16b # CHECK-NEXT: 1 2 1.00 zip2 v0.16b, v0.16b, v0.16b
# CHECK-NEXT: 1 4 1.00 zip2 v0.2d, v0.2d, v0.2d # CHECK-NEXT: 1 2 1.00 zip2 v0.2d, v0.2d, v0.2d
# CHECK-NEXT: 1 4 0.50 zip2 v0.2s, v0.2s, v0.2s # CHECK-NEXT: 1 2 0.50 zip2 v0.2s, v0.2s, v0.2s
# CHECK-NEXT: 1 4 0.50 zip2 v0.4h, v0.4h, v0.4h # CHECK-NEXT: 1 2 0.50 zip2 v0.4h, v0.4h, v0.4h
# CHECK-NEXT: 1 4 1.00 zip2 v0.4s, v0.4s, v0.4s # CHECK-NEXT: 1 2 1.00 zip2 v0.4s, v0.4s, v0.4s
# CHECK-NEXT: 1 4 0.50 zip2 v0.8b, v0.8b, v0.8b # CHECK-NEXT: 1 2 0.50 zip2 v0.8b, v0.8b, v0.8b
# CHECK-NEXT: 1 4 1.00 zip2 v0.8h, v0.8h, v0.8h # CHECK-NEXT: 1 2 1.00 zip2 v0.8h, v0.8h, v0.8h
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0.0] - CortexA55UnitALU # CHECK-NEXT: [0.0] - CortexA55UnitALU
# CHECK-NEXT: [0.1] - CortexA55UnitALU # CHECK-NEXT: [0.1] - CortexA55UnitALU
# CHECK-NEXT: [1] - CortexA55UnitB # CHECK-NEXT: [1] - CortexA55UnitB
# CHECK-NEXT: [2] - CortexA55UnitDiv # CHECK-NEXT: [2] - CortexA55UnitDiv
# CHECK-NEXT: [3.0] - CortexA55UnitFPALU # CHECK-NEXT: [3.0] - CortexA55UnitFPALU
# CHECK-NEXT: [3.1] - CortexA55UnitFPALU # CHECK-NEXT: [3.1] - CortexA55UnitFPALU
# CHECK-NEXT: [4] - CortexA55UnitFPDIV # CHECK-NEXT: [4] - CortexA55UnitFPDIV
# CHECK-NEXT: [5.0] - CortexA55UnitFPMAC # CHECK-NEXT: [5.0] - CortexA55UnitFPMAC
# CHECK-NEXT: [5.1] - CortexA55UnitFPMAC # CHECK-NEXT: [5.1] - CortexA55UnitFPMAC
# CHECK-NEXT: [6] - CortexA55UnitLd # CHECK-NEXT: [6] - CortexA55UnitLd
# CHECK-NEXT: [7] - CortexA55UnitMAC # CHECK-NEXT: [7] - CortexA55UnitMAC
# CHECK-NEXT: [8] - CortexA55UnitSt # CHECK-NEXT: [8] - CortexA55UnitSt
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] # CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8]
# CHECK-NEXT: - - - - 780.00 780.00 197.00 3.00 3.00 107.00 - 52.00 # CHECK-NEXT: - - - - 809.00 809.00 197.00 3.00 3.00 107.00 - 52.00
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] Instructions: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] Instructions:
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - abs d29, d24 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - abs d29, d24
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - abs v0.16b, v0.16b # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - abs v0.16b, v0.16b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - abs v0.2d, v0.2d # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - abs v0.2d, v0.2d
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - abs v0.2s, v0.2s # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - abs v0.2s, v0.2s
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - abs v0.4h, v0.4h # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - abs v0.4h, v0.4h
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# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fminp v0.2s, v0.2s, v0.2s # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fminp v0.2s, v0.2s, v0.2s
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fminp v0.4s, v0.4s, v0.4s # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fminp v0.4s, v0.4s, v0.4s
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmla d0, d1, v0.d[1] # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmla d0, d1, v0.d[1]
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmla s0, s1, v0.s[3] # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmla s0, s1, v0.s[3]
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmla v0.2s, v0.2s, v0.2s # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmla v0.2s, v0.2s, v0.2s
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmls d0, d4, v0.d[1] # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmls d0, d4, v0.d[1]
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmls s3, s5, v0.s[3] # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmls s3, s5, v0.s[3]
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmls v0.2s, v0.2s, v0.2s # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmls v0.2s, v0.2s, v0.2s
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fmov v0.2d, #-1.25000000 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fmov v0.2d, #-1.25000000
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fmov v0.2s, #13.00000000 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fmov v0.2s, #13.00000000
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fmov v0.4s, #1.00000000 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fmov v0.4s, #1.00000000
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fmul d0, d1, v0.d[1] # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fmul d0, d1, v0.d[1]
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fmul s0, s1, v0.s[3] # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fmul s0, s1, v0.s[3]
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fmul v0.2s, v0.2s, v0.2s # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fmul v0.2s, v0.2s, v0.2s
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fmulx d0, d4, v0.d[1] # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fmulx d0, d4, v0.d[1]
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fmulx d23, d11, d1 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fmulx d23, d11, d1
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fmulx s20, s22, s15 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fmulx s20, s22, s15
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fmulx s3, s5, v0.s[3] # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fmulx s3, s5, v0.s[3]
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fmulx v0.2d, v0.2d, v0.2d # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fmulx v0.2d, v0.2d, v0.2d
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fmulx v0.2s, v0.2s, v0.2s # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fmulx v0.2s, v0.2s, v0.2s
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fmulx v0.4s, v0.4s, v0.4s # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fmulx v0.4s, v0.4s, v0.4s
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fneg v0.2d, v0.2d # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fneg v0.2d, v0.2d
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fneg v0.2s, v0.2s # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fneg v0.2s, v0.2s
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fneg v0.4h, v0.4h # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - fneg v0.4h, v0.4h
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fneg v0.4s, v0.4s # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fneg v0.4s, v0.4s
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fneg v0.8h, v0.8h # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - fneg v0.8h, v0.8h
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# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqshrun2 v0.8h, v0.4s, #3 # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqshrun2 v0.8h, v0.4s, #3
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqsub s20, s10, s7 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqsub s20, s10, s7
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqsub v0.2d, v0.2d, v0.2d # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqsub v0.2d, v0.2d, v0.2d
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqsub v0.4s, v0.4s, v0.4s # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqsub v0.4s, v0.4s, v0.4s
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqsub v0.8b, v0.8b, v0.8b # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqsub v0.8b, v0.8b, v0.8b
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtn b18, h18 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtn b18, h18
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtn h20, s17 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtn h20, s17
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtn s19, d14 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtn s19, d14
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqxtn v0.2s, v0.2d # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtn v0.2s, v0.2d
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqxtn v0.4h, v0.4s # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtn v0.4h, v0.4s
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqxtn v0.8b, v0.8h # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtn v0.8b, v0.8h
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqxtn2 v0.16b, v0.8h # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtn2 v0.16b, v0.8h
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqxtn2 v0.4s, v0.2d # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtn2 v0.4s, v0.2d
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqxtn2 v0.8h, v0.4s # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtn2 v0.8h, v0.4s
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtun b19, h14 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtun b19, h14
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtun h21, s15 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtun h21, s15
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtun s20, d12 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtun s20, d12
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqxtun v0.2s, v0.2d # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtun v0.2s, v0.2d
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqxtun v0.4h, v0.4s # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtun v0.4h, v0.4s
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqxtun v0.8b, v0.8h # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtun v0.8b, v0.8h
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqxtun2 v0.16b, v0.8h # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtun2 v0.16b, v0.8h
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqxtun2 v0.4s, v0.2d # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtun2 v0.4s, v0.2d
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sqxtun2 v0.8h, v0.4s # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sqxtun2 v0.8h, v0.4s
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - srhadd v0.2s, v0.2s, v0.2s # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - srhadd v0.2s, v0.2s, v0.2s
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - srhadd v0.4h, v0.4h, v0.4h # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - srhadd v0.4h, v0.4h, v0.4h
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - srhadd v0.8b, v0.8b, v0.8b # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - srhadd v0.8b, v0.8b, v0.8b
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sri d10, d12, #14 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sri d10, d12, #14
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sri v0.16b, v0.16b, #3 # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sri v0.16b, v0.16b, #3
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sri v0.2d, v0.2d, #3 # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - sri v0.2d, v0.2d, #3
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sri v0.2s, v0.2s, #3 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sri v0.2s, v0.2s, #3
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sri v0.4h, v0.4h, #3 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - sri v0.4h, v0.4h, #3
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# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - suqadd v0.16b, v0.16b # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - suqadd v0.16b, v0.16b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - suqadd v0.2d, v0.2d # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - suqadd v0.2d, v0.2d
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - suqadd v0.2s, v0.2s # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - suqadd v0.2s, v0.2s
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - suqadd v0.4h, v0.4h # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - suqadd v0.4h, v0.4h
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - suqadd v0.4s, v0.4s # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - suqadd v0.4s, v0.4s
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - suqadd v0.8b, v0.8b # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - suqadd v0.8b, v0.8b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - suqadd v0.8h, v0.8h # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - suqadd v0.8h, v0.8h
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - tbl v0.16b, { v0.16b }, v0.16b # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - tbl v0.16b, { v0.16b }, v0.16b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - tbl v0.16b, { v0.16b, v1.16b }, v0.16b # CHECK-NEXT: - - - - 2.00 2.00 - - - - - - tbl v0.16b, { v0.16b, v1.16b }, v0.16b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b # CHECK-NEXT: - - - - 3.00 3.00 - - - - - - tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b # CHECK-NEXT: - - - - 4.00 4.00 - - - - - - tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - tbl v0.8b, { v0.16b }, v0.8b # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - tbl v0.8b, { v0.16b }, v0.8b
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - tbl v0.8b, { v0.16b, v1.16b }, v0.8b # CHECK-NEXT: - - - - 2.00 2.00 - - - - - - tbl v0.8b, { v0.16b, v1.16b }, v0.8b
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - tbl v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b # CHECK-NEXT: - - - - 3.00 3.00 - - - - - - tbl v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b # CHECK-NEXT: - - - - 4.00 4.00 - - - - - - tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - tbx v0.16b, { v0.16b }, v0.16b # CHECK-NEXT: - - - - 2.00 2.00 - - - - - - tbx v0.16b, { v0.16b }, v0.16b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - tbx v0.16b, { v0.16b, v1.16b }, v0.16b # CHECK-NEXT: - - - - 3.00 3.00 - - - - - - tbx v0.16b, { v0.16b, v1.16b }, v0.16b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - tbx v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b # CHECK-NEXT: - - - - 4.00 4.00 - - - - - - tbx v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - tbx v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b # CHECK-NEXT: - - - - 5.00 5.00 - - - - - - tbx v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - tbx v0.8b, { v0.16b }, v0.8b # CHECK-NEXT: - - - - 2.00 2.00 - - - - - - tbx v0.8b, { v0.16b }, v0.8b
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - tbx v0.8b, { v0.16b, v1.16b }, v0.8b # CHECK-NEXT: - - - - 3.00 3.00 - - - - - - tbx v0.8b, { v0.16b, v1.16b }, v0.8b
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - tbx v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b # CHECK-NEXT: - - - - 4.00 4.00 - - - - - - tbx v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - tbx v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b # CHECK-NEXT: - - - - 5.00 5.00 - - - - - - tbx v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn1 v0.16b, v0.16b, v0.16b # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn1 v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn1 v0.2d, v0.2d, v0.2d # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn1 v0.2d, v0.2d, v0.2d
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - trn1 v0.2s, v0.2s, v0.2s # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn1 v0.2s, v0.2s, v0.2s
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - trn1 v0.4h, v0.4h, v0.4h # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - trn1 v0.4h, v0.4h, v0.4h
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn1 v0.4s, v0.4s, v0.4s # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn1 v0.4s, v0.4s, v0.4s
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - trn1 v0.8b, v0.8b, v0.8b # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - trn1 v0.8b, v0.8b, v0.8b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn1 v0.8h, v0.8h, v0.8h # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn1 v0.8h, v0.8h, v0.8h
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn2 v0.16b, v0.16b, v0.16b # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn2 v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn2 v0.2d, v0.2d, v0.2d # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn2 v0.2d, v0.2d, v0.2d
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - trn2 v0.2s, v0.2s, v0.2s # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn2 v0.2s, v0.2s, v0.2s
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - trn2 v0.4h, v0.4h, v0.4h # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - trn2 v0.4h, v0.4h, v0.4h
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn2 v0.4s, v0.4s, v0.4s # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn2 v0.4s, v0.4s, v0.4s
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - trn2 v0.8b, v0.8b, v0.8b # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - trn2 v0.8b, v0.8b, v0.8b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn2 v0.8h, v0.8h, v0.8h # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - trn2 v0.8h, v0.8h, v0.8h
# CHECK-NEXT: - - - - 2.00 2.00 - - - - - - uaba v0.8b, v0.8b, v0.8b # CHECK-NEXT: - - - - 2.00 2.00 - - - - - - uaba v0.8b, v0.8b, v0.8b
# CHECK-NEXT: - - - - 2.00 2.00 - - - - - - uabal v0.2d, v0.2s, v0.2s # CHECK-NEXT: - - - - 2.00 2.00 - - - - - - uabal v0.2d, v0.2s, v0.2s
# CHECK-NEXT: - - - - 2.00 2.00 - - - - - - uabal v0.4s, v0.4h, v0.4h # CHECK-NEXT: - - - - 2.00 2.00 - - - - - - uabal v0.4s, v0.4h, v0.4h
# CHECK-NEXT: - - - - 2.00 2.00 - - - - - - uabal v0.8h, v0.8b, v0.8b # CHECK-NEXT: - - - - 2.00 2.00 - - - - - - uabal v0.8h, v0.8b, v0.8b
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# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - uqshrn2 v0.16b, v0.8h, #3 # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - uqshrn2 v0.16b, v0.8h, #3
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - uqshrn2 v0.4s, v0.2d, #3 # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - uqshrn2 v0.4s, v0.2d, #3
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - uqshrn2 v0.8h, v0.4s, #3 # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - uqshrn2 v0.8h, v0.4s, #3
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - uqsub d16, d16, d16 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - uqsub d16, d16, d16
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - uqsub v0.4h, v0.4h, v0.4h # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - uqsub v0.4h, v0.4h, v0.4h
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - uqxtn b18, h18 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - uqxtn b18, h18
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - uqxtn h20, s17 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - uqxtn h20, s17
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - uqxtn s19, d14 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - uqxtn s19, d14
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - uqxtn v0.2s, v0.2d # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - uqxtn v0.2s, v0.2d
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - uqxtn v0.4h, v0.4s # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - uqxtn v0.4h, v0.4s
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - uqxtn v0.8b, v0.8h # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - uqxtn v0.8b, v0.8h
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - uqxtn2 v0.16b, v0.8h # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - uqxtn2 v0.16b, v0.8h
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - uqxtn2 v0.4s, v0.2d # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - uqxtn2 v0.4s, v0.2d
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - uqxtn2 v0.8h, v0.4s # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - uqxtn2 v0.8h, v0.4s
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - urecpe v0.2s, v0.2s # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - urecpe v0.2s, v0.2s
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - urecpe v0.4s, v0.4s # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - urecpe v0.4s, v0.4s
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - urhadd v0.16b, v0.16b, v0.16b # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - urhadd v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - urhadd v0.4s, v0.4s, v0.4s # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - urhadd v0.4s, v0.4s, v0.4s
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - urhadd v0.8h, v0.8h, v0.8h # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - urhadd v0.8h, v0.8h, v0.8h
# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - urshl d8, d7, d4 # CHECK-NEXT: - - - - 0.50 0.50 - - - - - - urshl d8, d7, d4
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - urshl v0.16b, v0.16b, v0.16b # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - urshl v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - 1.00 1.00 - - - - - - urshl v0.2d, v0.2d, v0.2d # CHECK-NEXT: - - - - 1.00 1.00 - - - - - - urshl v0.2d, v0.2d, v0.2d
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