Port Uber specific changes from swift 5.4.2 to swift 5.5

[jinlin]

Summary

Port Uber specific changes from swift 5.4.2 to swift 5.5

llvm/include/llvm/CodeGen/LiveRegUnits.h

public:
   }
 
 private:
   /// Adds pristine registers. Pristine registers are callee saved registers
   /// that are unused in the function.
   void addPristines(const MachineFunction &MF);
 };
 
-/// Returns an iterator range over all physical register and mask operands for
-/// \p MI and bundled instructions. This also skips any debug operands.
-inline iterator_range<filter_iterator<
-    ConstMIBundleOperands, std::function<bool(const MachineOperand &)>>>
-phys_regs_and_masks(const MachineInstr &MI) {
-  std::function<bool(const MachineOperand &)> Pred =
-      [](const MachineOperand &MOP) {
-        return MOP.isRegMask() || (MOP.isReg() && !MOP.isDebug() &&
-                                   Register::isPhysicalRegister(MOP.getReg()));
-      };
-  return make_filter_range(const_mi_bundle_ops(MI), Pred);
-}
-
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_LIVEREGUNITS_H

llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h

private:
   std::string MCpu;
   std::string MAttr;
   std::string NativeObjectPath;
   TargetOptions Options;
   CodeGenOpt::Level CGOptLevel = CodeGenOpt::Default;
   const Target *MArch = nullptr;
   std::string TripleStr;
   unsigned OptLevel = 2;
+  unsigned SizeLevel = 0;
   lto_diagnostic_handler_t DiagHandler = nullptr;
   void *DiagContext = nullptr;
   bool ShouldInternalize = EnableLTOInternalization;
   bool ShouldEmbedUselists = false;
   bool ShouldRestoreGlobalsLinkage = false;
   CodeGenFileType FileType = CGFT_ObjectFile;
   std::unique_ptr<ToolOutputFile> DiagnosticOutputFile;
   bool Freestanding = false;
   std::unique_ptr<ToolOutputFile> StatsFile = nullptr;
 };
 }
 #endif

llvm/lib/CodeGen/LivePhysRegs.cpp

 //===--- LivePhysRegs.cpp - Live Physical Register Set --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the LivePhysRegs utility for tracking liveness of
 // physical registers across machine instructions in forward or backward order.
 // A more detailed description can be found in the corresponding header file.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/LivePhysRegs.h"
-#include "llvm/CodeGen/LiveRegUnits.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBundle.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Config/llvm-config.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
if (MO.clobbersPhysReg(*LRI)) {
       LRI = LiveRegs.erase(LRI);
     } else
       ++LRI;
   }
 }
 
 /// Remove defined registers and regmask kills from the set.
 void LivePhysRegs::removeDefs(const MachineInstr &MI) {
-  for (const MachineOperand &MOP : phys_regs_and_masks(MI)) {
-    if (MOP.isRegMask()) {
-      removeRegsInMask(MOP);
+  for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
+    if (O->isReg()) {
+      if (!O->isDef() || O->isDebug())
         continue;
-    }
-
-    if (MOP.isDef())
-      removeReg(MOP.getReg());
+      Register Reg = O->getReg();
+      if (!Register::isPhysicalRegister(Reg))
+        continue;
+      removeReg(Reg);
+    } else if (O->isRegMask())
+      removeRegsInMask(*O);
   }
 }
 
 /// Add uses to the set.
 void LivePhysRegs::addUses(const MachineInstr &MI) {
-  for (const MachineOperand &MOP : phys_regs_and_masks(MI)) {
-    if (!MOP.isReg() || !MOP.readsReg())
+  for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
+    if (!O->isReg() || !O->readsReg() || O->isDebug())
+      continue;
+    Register Reg = O->getReg();
+    if (!Register::isPhysicalRegister(Reg))
       continue;
-    addReg(MOP.getReg());
+    addReg(Reg);
   }
 }
 
 /// Simulates liveness when stepping backwards over an instruction(bundle):
 /// Remove Defs, add uses. This is the recommended way of calculating liveness.
 void LivePhysRegs::stepBackward(const MachineInstr &MI) {
   // Remove defined registers and regmask kills from the set.
   removeDefs(MI);

llvm/lib/CodeGen/LiveRegUnits.cpp

for (MCRegUnitRootIterator RootReg(U, TRI); RootReg.isValid(); ++RootReg) {
       if (MachineOperand::clobbersPhysReg(RegMask, *RootReg))
         Units.set(U);
     }
   }
 }
 
 void LiveRegUnits::stepBackward(const MachineInstr &MI) {
   // Remove defined registers and regmask kills from the set.
-  for (const MachineOperand &MOP : phys_regs_and_masks(MI)) {
-    if (MOP.isRegMask()) {
-      removeRegsNotPreserved(MOP.getRegMask());
+  for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
+    if (O->isReg()) {
+      if (!O->isDef() || O->isDebug())
         continue;
-    }
-
-    if (MOP.isDef())
-      removeReg(MOP.getReg());
+      Register Reg = O->getReg();
+      if (!Register::isPhysicalRegister(Reg))
+        continue;
+      removeReg(Reg);
+    } else if (O->isRegMask())
+      removeRegsNotPreserved(O->getRegMask());
   }
 
   // Add uses to the set.
-  for (const MachineOperand &MOP : phys_regs_and_masks(MI)) {
-    if (!MOP.isReg() || !MOP.readsReg())
+  for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
+    if (!O->isReg() || !O->readsReg() || O->isDebug())
       continue;
-    addReg(MOP.getReg());
+    Register Reg = O->getReg();
+    if (!Register::isPhysicalRegister(Reg))
+      continue;
+    addReg(Reg);
   }
 }
 
 void LiveRegUnits::accumulate(const MachineInstr &MI) {
   // Add defs, uses and regmask clobbers to the set.
-  for (const MachineOperand &MOP : phys_regs_and_masks(MI)) {
-    if (MOP.isRegMask()) {
-      addRegsInMask(MOP.getRegMask());
+  for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
+    if (O->isReg()) {
+      Register Reg = O->getReg();
+      if (!Register::isPhysicalRegister(Reg))
         continue;
-    }
-    if (!MOP.isDef() && !MOP.readsReg())
+      if (!O->isDef() && !O->readsReg())
         continue;
-    addReg(MOP.getReg());
+      addReg(Reg);
+    } else if (O->isRegMask())
+      addRegsInMask(O->getRegMask());
   }
 }
 
 /// Add live-in registers of basic block \p MBB to \p LiveUnits.
 static void addBlockLiveIns(LiveRegUnits &LiveUnits,
                             const MachineBasicBlock &MBB) {
   for (const auto &LI : MBB.liveins())
     LiveUnits.addRegMasked(LI.PhysReg, LI.LaneMask);

llvm/lib/CodeGen/MachineOutliner.cpp

MachineFunction *MachineOutliner::createOutlinedFunction(
   F->setLinkage(GlobalValue::InternalLinkage);
   F->setUnnamedAddr(GlobalValue::UnnamedAddr::Global);
 
   // Set optsize/minsize, so we don't insert padding between outlined
   // functions.
   F->addFnAttr(Attribute::OptimizeForSize);
   F->addFnAttr(Attribute::MinSize);
 
+#if 1 // UBER_CUSTOMIZATION
+  AttrBuilder B;
+  B.addAttribute("outliner", "true");
+  F->removeAttributes(AttributeList::FunctionIndex, B);
+  if (F->hasFnAttribute("outliner"))
+    LLVM_DEBUG(errs() << "still has outliner\n");
+  F->addAttributes(AttributeList::FunctionIndex, B);
+#endif // end UBER_CUSTOMIZATION
+
   // Include target features from an arbitrary candidate for the outlined
   // function. This makes sure the outlined function knows what kinds of
   // instructions are going into it. This is fine, since all parent functions
   // must necessarily support the instructions that are in the outlined region.
   Candidate &FirstCand = OF.Candidates.front();
   const Function &ParentFn = FirstCand.getMF()->getFunction();
   if (ParentFn.hasFnAttribute("target-features"))
     F->addFnAttr(ParentFn.getFnAttribute("target-features"));
for (Candidate &C : OF.Candidates) {
           for (MachineOperand &MOP : MI->operands()) {
             // Skip over anything that isn't a register.
             if (!MOP.isReg())
               continue;
 
             if (MOP.isDef()) {
               // Introduce DefRegs set to skip the redundant register.
               DefRegs.insert(MOP.getReg());
-              if (UseRegs.count(MOP.getReg()))
+              if (!MOP.isDead() && UseRegs.count(MOP.getReg()))
                 // Since the regiester is modeled as defined,
                 // it is not necessary to be put in use register set.
                 UseRegs.erase(MOP.getReg());
             } else if (!MOP.isUndef()) {
               // Any register which is not undefined should
               // be put in the use register set.
               UseRegs.insert(MOP.getReg());
             }
void MachineOutliner::populateMapper(InstructionMapper &Mapper, Module &M,
   // iterating over each Function in M.
   for (Function &F : M) {
 
     // If there's nothing in F, then there's no reason to try and outline from
     // it.
     if (F.empty())
       continue;
 
+#if 1 // UBER_CUSTOMIZATION
+    if (F.getFnAttribute("outliner").getValueAsString() == "true")
+      continue;
+#endif // end UBER_CUSTOMIZATION
+
     // There's something in F. Check if it has a MachineFunction associated with
     // it.
     MachineFunction *MF = MMI.getMachineFunction(F);
 
     // If it doesn't, then there's nothing to outline from. Move to the next
     // Function.
     if (!MF)
       continue;

llvm/lib/LTO/LTOCodeGenerator.cpp

void LTOCodeGenerator::setDebugInfo(lto_debug_model Debug) {
   case LTO_DEBUG_MODEL_DWARF:
     EmitDwarfDebugInfo = true;
     return;
   }
   llvm_unreachable("Unknown debug format!");
 }
 
 void LTOCodeGenerator::setOptLevel(unsigned Level) {
+  if (Level > 3) {
+    SizeLevel = Level - 3;
+    Level = 2;
+  }
   OptLevel = Level;
   switch (OptLevel) {
   case 0:
     CGOptLevel = CodeGenOpt::None;
     return;
   case 1:
     CGOptLevel = CodeGenOpt::Less;
     return;
passes.add(
       createTargetTransformInfoWrapperPass(TargetMach->getTargetIRAnalysis()));
 
   Triple TargetTriple(TargetMach->getTargetTriple());
   PassManagerBuilder PMB;
   PMB.DisableGVNLoadPRE = DisableGVNLoadPRE;
   PMB.LoopVectorize = !DisableVectorization;
   PMB.SLPVectorize = !DisableVectorization;
   if (!DisableInline)
-    PMB.Inliner = createFunctionInliningPass();
+    PMB.Inliner = createFunctionInliningPass(OptLevel, SizeLevel, false);
   PMB.LibraryInfo = new TargetLibraryInfoImpl(TargetTriple);
   if (Freestanding)
     PMB.LibraryInfo->disableAllFunctions();
   PMB.OptLevel = OptLevel;
   PMB.VerifyInput = !DisableVerify;
   PMB.VerifyOutput = !DisableVerify;
 
   PMB.populateLTOPassManager(passes);

llvm/lib/Linker/IRMover.cpp

ConstantInt *DstBehavior =
         mdconst::extract<ConstantInt>(DstOp->getOperand(0));
     unsigned DstBehaviorValue = DstBehavior->getZExtValue();
 
     auto overrideDstValue = [&]() {
       DstModFlags->setOperand(DstIndex, SrcOp);
       Flags[ID].first = SrcOp;
     };
 
+    auto isSwiftBitCode = [&](Module &M) {
+      SmallVector<Module::ModuleFlagEntry, 8> ModuleFlags;
+      M.getModuleFlagsMetadata(ModuleFlags);
+      for (const auto &MFE : ModuleFlags) {
+        if (MFE.Behavior == Module::Require)
+          continue;
+        StringRef Key = MFE.Key->getString();
+        if (Key == "Swift Version")
+          return true;
+      }
+      return false;
+    };
+
     // If either flag has override behavior, handle it first.
     if (DstBehaviorValue == Module::Override) {
       // Diagnose inconsistent flags which both have override behavior.
       if (SrcBehaviorValue == Module::Override &&
           SrcOp->getOperand(2) != DstOp->getOperand(2))
         return stringErr("linking module flags '" + ID->getString() +
                          "': IDs have conflicting override values in '" +
                          SrcM->getModuleIdentifier() + "' and '" +
                          DstM.getModuleIdentifier() + "'");
       continue;
     } else if (SrcBehaviorValue == Module::Override) {
       // Update the destination flag to that of the source.
       overrideDstValue();
       continue;
     }
 
     // Diagnose inconsistent merge behavior types.
     if (SrcBehaviorValue != DstBehaviorValue) {
       bool MaxAndWarn = (SrcBehaviorValue == Module::Max &&
                          DstBehaviorValue == Module::Warning) ||
                         (DstBehaviorValue == Module::Max &&
                          SrcBehaviorValue == Module::Warning);
-      if (!MaxAndWarn)
+      if (!MaxAndWarn) {
+        if (SrcOp->getOperand(2) != DstOp->getOperand(2) &&
+            ID->getString().equals("Objective-C Garbage Collection")) {
+          auto Int32Ty = Type::getInt32Ty(DstM.getContext());
+          auto SrcMD = dyn_cast<ConstantAsMetadata>(SrcOp->getOperand(2));
+          auto DstMD = dyn_cast<ConstantAsMetadata>(DstOp->getOperand(2));
+          assert(SrcMD && DstMD);
+          unsigned SrcVal =
+              SrcMD->getValue()->getUniqueInteger().getZExtValue();
+          unsigned DstVal =
+              DstMD->getValue()->getUniqueInteger().getZExtValue();
+          if ((isSwiftBitCode(*SrcM) && DstVal < 64) ||
+              (isSwiftBitCode(DstM) && SrcVal < 64)) {
+            unsigned resVal = SrcVal | DstVal;
+            SrcOp->replaceOperandWith(
+                2, ConstantAsMetadata::get(ConstantInt::get(Int32Ty, resVal)));
+            DstOp->replaceOperandWith(
+                2, ConstantAsMetadata::get(ConstantInt::get(Int32Ty, resVal)));
+            continue;
+          }
+        }
         return stringErr("linking module flags '" + ID->getString() +
                          "': IDs have conflicting behaviors in '" +
                          SrcM->getModuleIdentifier() + "' and '" +
                          DstM.getModuleIdentifier() + "'");
       }
+    }
 
     auto replaceDstValue = [&](MDNode *New) {
       Metadata *FlagOps[] = {DstOp->getOperand(0), ID, New};
       MDNode *Flag = MDNode::get(DstM.getContext(), FlagOps);
       DstModFlags->setOperand(DstIndex, Flag);
       Flags[ID].first = Flag;
     };
 
Error IRLinker::run() {
   DoneLinkingBodies = true;
   Mapper.addFlags(RF_NullMapMissingGlobalValues);
 
   // Remap all of the named MDNodes in Src into the DstM module. We do this
   // after linking GlobalValues so that MDNodes that reference GlobalValues
   // are properly remapped.
   linkNamedMDNodes();
 
+  // For each global in the source module, find the corresponding global
+  // in the destination module, splice the global and append it to the end
+  // of the globals list in the destination module.
+  Module::GlobalListType &Globals = DstM.getGlobalList();
+  for (GlobalVariable &GV : SrcM->globals()) {
+    if (GV.hasAppendingLinkage())
+      continue;
+    auto NewValue = Mapper.mapValue(GV);
+    if (NewValue) {
+      auto *NewGV = dyn_cast<GlobalVariable>(NewValue->stripPointerCasts());
+      if (NewGV)
+        Globals.splice(Globals.end(), Globals, NewGV->getIterator());
+    }
+  }
   if (!IsPerformingImport && !SrcM->getModuleInlineAsm().empty()) {
     // Append the module inline asm string.
     DstM.appendModuleInlineAsm(adjustInlineAsm(SrcM->getModuleInlineAsm(),
                                                SrcTriple));
   } else if (IsPerformingImport) {
     // Import any symver directives for symbols in DstM.
     ModuleSymbolTable::CollectAsmSymvers(*SrcM,
                                          [&](StringRef Name, StringRef Alias) {

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

outliner::OutlinedFunction AArch64InstrInfo::getOutliningCandidateInfo(
 
   unsigned FrameID = MachineOutlinerDefault;
   NumBytesToCreateFrame += 4;
 
   bool HasBTI = any_of(RepeatedSequenceLocs, [](outliner::Candidate &C) {
     return C.getMF()->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement();
   });
 
+#if 1 // UBER_CUSTOMIZATION
+  bool HasOutlined = any_of(RepeatedSequenceLocs, [](outliner::Candidate &C) {
+    return C.getMF()
+               ->getFunction()
+               .getFnAttribute("outliner")
+               .getValueAsString() == "true";
+  });
+#endif // end UBER_CUSTOMIZATION
+
   // We check to see if CFI Instructions are present, and if they are
   // we find the number of CFI Instructions in the candidates.
   unsigned CFICount = 0;
   MachineBasicBlock::iterator MBBI = RepeatedSequenceLocs[0].front();
   for (unsigned Loc = RepeatedSequenceLocs[0].getStartIdx();
        Loc < RepeatedSequenceLocs[0].getEndIdx() + 1; Loc++) {
     const std::vector<MCCFIInstruction> &CFIInstructions =
         RepeatedSequenceLocs[0].getMF()->getFrameInstructions();
#endif // end UBER_CUSTOMIZATION
   // If the last instruction in any candidate is a terminator, then we should
   // tail call all of the candidates.
   if (RepeatedSequenceLocs[0].back()->isTerminator()) {
     FrameID = MachineOutlinerTailCall;
     NumBytesToCreateFrame = 0;
     SetCandidateCallInfo(MachineOutlinerTailCall, 4);
   }
 
-  else if (LastInstrOpcode == AArch64::BL ||
+  else if ((LastInstrOpcode == AArch64::BL ||
             ((LastInstrOpcode == AArch64::BLR ||
               LastInstrOpcode == AArch64::BLRNoIP) &&
-            !HasBTI)) {
+             !HasBTI)) &&
+           !HasOutlined) {
     // FIXME: Do we need to check if the code after this uses the value of LR?
     FrameID = MachineOutlinerThunk;
     NumBytesToCreateFrame = 0;
     SetCandidateCallInfo(MachineOutlinerThunk, 4);
   }
 
   else {
     // We need to decide how to emit calls + frames. We can always emit the same

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
-#include "llvm/Support/DebugCounter.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 #include <cassert>
 #include <cstdint>
-#include <functional>
 #include <iterator>
 #include <limits>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "aarch64-ldst-opt"
 
 STATISTIC(NumPairCreated, "Number of load/store pair instructions generated");
 STATISTIC(NumPostFolded, "Number of post-index updates folded");
 STATISTIC(NumPreFolded, "Number of pre-index updates folded");
 STATISTIC(NumUnscaledPairCreated,
           "Number of load/store from unscaled generated");
 STATISTIC(NumZeroStoresPromoted, "Number of narrow zero stores promoted");
 STATISTIC(NumLoadsFromStoresPromoted, "Number of loads from stores promoted");
 
-DEBUG_COUNTER(RegRenamingCounter, DEBUG_TYPE "-reg-renaming",
-              "Controls which pairs are considered for renaming");
-
 // The LdStLimit limits how far we search for load/store pairs.
 static cl::opt<unsigned> LdStLimit("aarch64-load-store-scan-limit",
                                    cl::init(20), cl::Hidden);
 
 // The UpdateLimit limits how far we search for update instructions when we form
 // pre-/post-index instructions.
 static cl::opt<unsigned> UpdateLimit("aarch64-update-scan-limit", cl::init(100),
                                      cl::Hidden);
using LdStPairFlags = struct LdStPairFlags {
   bool MergeForward = false;
 
   // SExtIdx gives the index of the result of the load pair that must be
   // extended. The value of SExtIdx assumes that the paired load produces the
   // value in this order: (I, returned iterator), i.e., -1 means no value has
   // to be extended, 0 means I, and 1 means the returned iterator.
   int SExtIdx = -1;
 
-  // If not none, RenameReg can be used to rename the result register of the
-  // first store in a pair. Currently this only works when merging stores
-  // forward.
-  Optional<MCPhysReg> RenameReg = None;
-
   LdStPairFlags() = default;
 
   void setMergeForward(bool V = true) { MergeForward = V; }
   bool getMergeForward() const { return MergeForward; }
 
   void setSExtIdx(int V) { SExtIdx = V; }
   int getSExtIdx() const { return SExtIdx; }
-
-  void setRenameReg(MCPhysReg R) { RenameReg = R; }
-  void clearRenameReg() { RenameReg = None; }
-  Optional<MCPhysReg> getRenameReg() const { return RenameReg; }
 };
 
 struct AArch64LoadStoreOpt : public MachineFunctionPass {
   static char ID;
 
   AArch64LoadStoreOpt() : MachineFunctionPass(ID) {
     initializeAArch64LoadStoreOptPass(*PassRegistry::getPassRegistry());
   }
 
   AliasAnalysis *AA;
   const AArch64InstrInfo *TII;
   const TargetRegisterInfo *TRI;
   const AArch64Subtarget *Subtarget;
 
   // Track which register units have been modified and used.
   LiveRegUnits ModifiedRegUnits, UsedRegUnits;
-  LiveRegUnits DefinedInBB;
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<AAResultsWrapperPass>();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   // Scan the instructions looking for a load/store that can be combined
   // with the current instruction into a load/store pair.
if (IsPaired) {
     MinOffset = -64;
     MaxOffset = 63;
   } else {
     MinOffset = -256;
     MaxOffset = 255;
   }
 }
 
-static MachineOperand &getLdStRegOp(MachineInstr &MI,
+static const MachineOperand &getLdStRegOp(const MachineInstr &MI,
                                           unsigned PairedRegOp = 0) {
   assert(PairedRegOp < 2 && "Unexpected register operand idx.");
   unsigned Idx = isPairedLdSt(MI) ? PairedRegOp : 0;
   return MI.getOperand(Idx);
 }
 
 static const MachineOperand &getLdStBaseOp(const MachineInstr &MI) {
   unsigned Idx = isPairedLdSt(MI) ? 2 : 1;
   return MI.getOperand(Idx);
AArch64LoadStoreOpt::mergeNarrowZeroStores(MachineBasicBlock::iterator I,
   LLVM_DEBUG(dbgs() << "\n");
 
   // Erase the old instructions.
   I->eraseFromParent();
   MergeMI->eraseFromParent();
   return NextI;
 }
 
-// Apply Fn to all instructions between MI and the beginning of the block, until
-// a def for DefReg is reached. Returns true, iff Fn returns true for all
-// visited instructions. Stop after visiting Limit iterations.
-static bool forAllMIsUntilDef(MachineInstr &MI, MCPhysReg DefReg,
-                              const TargetRegisterInfo *TRI, unsigned Limit,
-                              std::function<bool(MachineInstr &, bool)> &Fn) {
-  auto MBB = MI.getParent();
-  for (MachineInstr &I :
-       instructionsWithoutDebug(MI.getReverseIterator(), MBB->instr_rend())) {
-    if (!Limit)
-      return false;
-    --Limit;
-
-    bool isDef = any_of(I.operands(), [DefReg, TRI](MachineOperand &MOP) {
-      return MOP.isReg() && MOP.isDef() && !MOP.isDebug() && MOP.getReg() &&
-             TRI->regsOverlap(MOP.getReg(), DefReg);
-    });
-    if (!Fn(I, isDef))
-      return false;
-    if (isDef)
-      break;
-  }
-  return true;
-}
-
-static void updateDefinedRegisters(MachineInstr &MI, LiveRegUnits &Units,
-                                   const TargetRegisterInfo *TRI) {
-
-  for (const MachineOperand &MOP : phys_regs_and_masks(MI))
-    if (MOP.isReg() && MOP.isKill())
-      Units.removeReg(MOP.getReg());
-
-  for (const MachineOperand &MOP : phys_regs_and_masks(MI))
-    if (MOP.isReg() && !MOP.isKill())
-      Units.addReg(MOP.getReg());
-}
-
 MachineBasicBlock::iterator
 AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
                                       MachineBasicBlock::iterator Paired,
                                       const LdStPairFlags &Flags) {
   MachineBasicBlock::iterator E = I->getParent()->end();
   MachineBasicBlock::iterator NextI = next_nodbg(I, E);
   // If NextI is the second of the two instructions to be merged, we need
   // to skip one further. Either way we merge will invalidate the iterator,
   // and we don't need to scan the new instruction, as it's a pairwise
   // instruction, which we're not considering for further action anyway.
   if (NextI == Paired)
     NextI = next_nodbg(NextI, E);
 
   int SExtIdx = Flags.getSExtIdx();
   unsigned Opc =
       SExtIdx == -1 ? I->getOpcode() : getMatchingNonSExtOpcode(I->getOpcode());
   bool IsUnscaled = TII->isUnscaledLdSt(Opc);
   int OffsetStride = IsUnscaled ? TII->getMemScale(*I) : 1;
 
   bool MergeForward = Flags.getMergeForward();
 
-  Optional<MCPhysReg> RenameReg = Flags.getRenameReg();
-  if (MergeForward && RenameReg) {
-    MCRegister RegToRename = getLdStRegOp(*I).getReg();
-    DefinedInBB.addReg(*RenameReg);
-
-    // Return the sub/super register for RenameReg, matching the size of
-    // OriginalReg.
-    auto GetMatchingSubReg = [this,
-                              RenameReg](MCPhysReg OriginalReg) -> MCPhysReg {
-      for (MCPhysReg SubOrSuper : TRI->sub_and_superregs_inclusive(*RenameReg))
-        if (TRI->getMinimalPhysRegClass(OriginalReg) ==
-            TRI->getMinimalPhysRegClass(SubOrSuper))
-          return SubOrSuper;
-      llvm_unreachable("Should have found matching sub or super register!");
-    };
-
-    std::function<bool(MachineInstr &, bool)> UpdateMIs =
-        [this, RegToRename, GetMatchingSubReg](MachineInstr &MI, bool IsDef) {
-          if (IsDef) {
-            bool SeenDef = false;
-            for (auto &MOP : MI.operands()) {
-              // Rename the first explicit definition and all implicit
-              // definitions matching RegToRename.
-              if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
-                  (!SeenDef || (MOP.isDef() && MOP.isImplicit())) &&
-                  TRI->regsOverlap(MOP.getReg(), RegToRename)) {
-                assert((MOP.isImplicit() ||
-                        (MOP.isRenamable() && !MOP.isEarlyClobber())) &&
-                       "Need renamable operands");
-                MOP.setReg(GetMatchingSubReg(MOP.getReg()));
-                SeenDef = true;
-              }
-            }
-          } else {
-            for (auto &MOP : MI.operands()) {
-              if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
-                  TRI->regsOverlap(MOP.getReg(), RegToRename)) {
-                assert((MOP.isImplicit() ||
-                        (MOP.isRenamable() && !MOP.isEarlyClobber())) &&
-                           "Need renamable operands");
-                MOP.setReg(GetMatchingSubReg(MOP.getReg()));
-              }
-            }
-          }
-          LLVM_DEBUG(dbgs() << "Renamed " << MI << "\n");
-          return true;
-        };
-    forAllMIsUntilDef(*I, RegToRename, TRI, LdStLimit, UpdateMIs);
-
-#if !defined(NDEBUG)
-    // Make sure the register used for renaming is not used between the paired
-    // instructions. That would trash the content before the new paired
-    // instruction.
-    for (auto &MI :
-         iterator_range<MachineInstrBundleIterator<llvm::MachineInstr>>(
-             std::next(I), std::next(Paired)))
-      assert(all_of(MI.operands(),
-                    [this, &RenameReg](const MachineOperand &MOP) {
-                      return !MOP.isReg() || MOP.isDebug() || !MOP.getReg() ||
-                             !TRI->regsOverlap(MOP.getReg(), *RenameReg);
-                    }) &&
-             "Rename register used between paired instruction, trashing the "
-             "content");
-#endif
-  }
-
   // Insert our new paired instruction after whichever of the paired
   // instructions MergeForward indicates.
   MachineBasicBlock::iterator InsertionPoint = MergeForward ? Paired : I;
   // Also based on MergeForward is from where we copy the base register operand
   // so we get the flags compatible with the input code.
   const MachineOperand &BaseRegOp =
       MergeForward ? getLdStBaseOp(*Paired) : getLdStBaseOp(*I);
 
if (SExtIdx != -1) {
     (void)MIBSXTW;
     LLVM_DEBUG(dbgs() << "  Extend operand:\n    ");
     LLVM_DEBUG(((MachineInstr *)MIBSXTW)->print(dbgs()));
   } else {
     LLVM_DEBUG(((MachineInstr *)MIB)->print(dbgs()));
   }
   LLVM_DEBUG(dbgs() << "\n");
 
-  if (MergeForward)
-    for (const MachineOperand &MOP : phys_regs_and_masks(*I))
-      if (MOP.isReg() && MOP.isKill())
-        DefinedInBB.addReg(MOP.getReg());
-
   // Erase the old instructions.
   I->eraseFromParent();
   Paired->eraseFromParent();
 
   return NextI;
 }
 
 MachineBasicBlock::iterator
static bool areCandidatesToMergeOrPair(MachineInstr &FirstMI, MachineInstr &MI,
 
   // Try to match an unscaled load/store with a scaled load/store.
   return TII->isUnscaledLdSt(OpcA) != TII->isUnscaledLdSt(OpcB) &&
          getMatchingPairOpcode(OpcA) == getMatchingPairOpcode(OpcB);
 
   // FIXME: Can we also match a mixed sext/zext unscaled/scaled pair?
 }
 
-static bool
-canRenameUpToDef(MachineInstr &FirstMI, LiveRegUnits &UsedInBetween,
-                 SmallPtrSetImpl<const TargetRegisterClass *> &RequiredClasses,
-                 const TargetRegisterInfo *TRI) {
-  if (!FirstMI.mayStore())
-    return false;
-
-  // Check if we can find an unused register which we can use to rename
-  // the register used by the first load/store.
-  auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg());
-  MachineFunction &MF = *FirstMI.getParent()->getParent();
-  if (!RegClass || !MF.getRegInfo().tracksLiveness())
-    return false;
-
-  auto RegToRename = getLdStRegOp(FirstMI).getReg();
-  // For now, we only rename if the store operand gets killed at the store.
-  if (!getLdStRegOp(FirstMI).isKill() &&
-      !any_of(FirstMI.operands(),
-              [TRI, RegToRename](const MachineOperand &MOP) {
-                return MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
-                       MOP.isImplicit() && MOP.isKill() &&
-                       TRI->regsOverlap(RegToRename, MOP.getReg());
-              })) {
-    LLVM_DEBUG(dbgs() << "  Operand not killed at " << FirstMI << "\n");
-    return false;
-  }
-  auto canRenameMOP = [TRI](const MachineOperand &MOP) {
-    if (MOP.isReg()) {
-      auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg());
-      // Renaming registers with multiple disjunct sub-registers (e.g. the
-      // result of a LD3) means that all sub-registers are renamed, potentially
-      // impacting other instructions we did not check. Bail out.
-      // Note that this relies on the structure of the AArch64 register file. In
-      // particular, a subregister cannot be written without overwriting the
-      // whole register.
-      if (RegClass->HasDisjunctSubRegs) {
-        LLVM_DEBUG(
-            dbgs()
-            << "  Cannot rename operands with multiple disjunct subregisters ("
-            << MOP << ")\n");
-        return false;
-      }
-    }
-    return MOP.isImplicit() ||
-           (MOP.isRenamable() && !MOP.isEarlyClobber() && !MOP.isTied());
-  };
-
-  bool FoundDef = false;
-
-  // For each instruction between FirstMI and the previous def for RegToRename,
-  // we
-  // * check if we can rename RegToRename in this instruction
-  // * collect the registers used and required register classes for RegToRename.
-  std::function<bool(MachineInstr &, bool)> CheckMIs = [&](MachineInstr &MI,
-                                                           bool IsDef) {
-    LLVM_DEBUG(dbgs() << "Checking " << MI << "\n");
-    // Currently we do not try to rename across frame-setup instructions.
-    if (MI.getFlag(MachineInstr::FrameSetup)) {
-      LLVM_DEBUG(dbgs() << "  Cannot rename framesetup instructions currently ("
-                        << MI << ")\n");
-      return false;
-    }
-
-    UsedInBetween.accumulate(MI);
-
-    // For a definition, check that we can rename the definition and exit the
-    // loop.
-    FoundDef = IsDef;
-
-    // For defs, check if we can rename the first def of RegToRename.
-    if (FoundDef) {
-      // For some pseudo instructions, we might not generate code in the end
-      // (e.g. KILL) and we would end up without a correct def for the rename
-      // register.
-      // TODO: This might be overly conservative and we could handle those cases
-      // in multiple ways:
-      //       1. Insert an extra copy, to materialize the def.
-      //       2. Skip pseudo-defs until we find an non-pseudo def.
-      if (MI.isPseudo()) {
-        LLVM_DEBUG(dbgs() << "  Cannot rename pseudo instruction " << MI
-                          << "\n");
-        return false;
-      }
-
-      for (auto &MOP : MI.operands()) {
-        if (!MOP.isReg() || !MOP.isDef() || MOP.isDebug() || !MOP.getReg() ||
-            !TRI->regsOverlap(MOP.getReg(), RegToRename))
-          continue;
-        if (!canRenameMOP(MOP)) {
-          LLVM_DEBUG(dbgs()
-                     << "  Cannot rename " << MOP << " in " << MI << "\n");
-          return false;
-        }
-        RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg()));
-      }
-      return true;
-    } else {
-      for (auto &MOP : MI.operands()) {
-        if (!MOP.isReg() || MOP.isDebug() || !MOP.getReg() ||
-            !TRI->regsOverlap(MOP.getReg(), RegToRename))
-          continue;
-
-        if (!canRenameMOP(MOP)) {
-          LLVM_DEBUG(dbgs()
-                     << "  Cannot rename " << MOP << " in " << MI << "\n");
-          return false;
-        }
-        RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg()));
-      }
-    }
-    return true;
-  };
-
-  if (!forAllMIsUntilDef(FirstMI, RegToRename, TRI, LdStLimit, CheckMIs))
-    return false;
-
-  if (!FoundDef) {
-    LLVM_DEBUG(dbgs() << "  Did not find definition for register in BB\n");
-    return false;
-  }
-  return true;
-}
-
-// Check if we can find a physical register for renaming. This register must:
-// * not be defined up to FirstMI (checking DefinedInBB)
-// * not used between the MI and the defining instruction of the register to
-//   rename (checked using UsedInBetween).
-// * is available in all used register classes (checked using RequiredClasses).
-static Optional<MCPhysReg> tryToFindRegisterToRename(
-    MachineInstr &FirstMI, MachineInstr &MI, LiveRegUnits &DefinedInBB,
-    LiveRegUnits &UsedInBetween,
-    SmallPtrSetImpl<const TargetRegisterClass *> &RequiredClasses,
-    const TargetRegisterInfo *TRI) {
-  auto &MF = *FirstMI.getParent()->getParent();
-  MachineRegisterInfo &RegInfo = MF.getRegInfo();
-
-  // Checks if any sub- or super-register of PR is callee saved.
-  auto AnySubOrSuperRegCalleePreserved = [&MF, TRI](MCPhysReg PR) {
-    return any_of(TRI->sub_and_superregs_inclusive(PR),
-                  [&MF, TRI](MCPhysReg SubOrSuper) {
-                    return TRI->isCalleeSavedPhysReg(SubOrSuper, MF);
-                  });
-  };
-
-  // Check if PR or one of its sub- or super-registers can be used for all
-  // required register classes.
-  auto CanBeUsedForAllClasses = [&RequiredClasses, TRI](MCPhysReg PR) {
-    return all_of(RequiredClasses, [PR, TRI](const TargetRegisterClass *C) {
-      return any_of(TRI->sub_and_superregs_inclusive(PR),
-                    [C, TRI](MCPhysReg SubOrSuper) {
-                      return C == TRI->getMinimalPhysRegClass(SubOrSuper);
-                    });
-    });
-  };
-
-  auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg());
-  for (const MCPhysReg &PR : *RegClass) {
-    if (DefinedInBB.available(PR) && UsedInBetween.available(PR) &&
-        !RegInfo.isReserved(PR) && !AnySubOrSuperRegCalleePreserved(PR) &&
-        CanBeUsedForAllClasses(PR)) {
-      DefinedInBB.addReg(PR);
-      LLVM_DEBUG(dbgs() << "Found rename register " << printReg(PR, TRI)
-                        << "\n");
-      return {PR};
-    }
-  }
-  LLVM_DEBUG(dbgs() << "No rename register found from "
-                    << TRI->getRegClassName(RegClass) << "\n");
-  return None;
-}
-
 /// Scan the instructions looking for a load/store that can be combined with the
 /// current instruction into a wider equivalent or a load/store pair.
 MachineBasicBlock::iterator
 AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
                                       LdStPairFlags &Flags, unsigned Limit,
                                       bool FindNarrowMerge) {
   MachineBasicBlock::iterator E = I->getParent()->end();
   MachineBasicBlock::iterator MBBI = I;
-  MachineBasicBlock::iterator MBBIWithRenameReg;
   MachineInstr &FirstMI = *I;
   MBBI = next_nodbg(MBBI, E);
 
   bool MayLoad = FirstMI.mayLoad();
   bool IsUnscaled = TII->isUnscaledLdSt(FirstMI);
   Register Reg = getLdStRegOp(FirstMI).getReg();
   Register BaseReg = getLdStBaseOp(FirstMI).getReg();
   int Offset = getLdStOffsetOp(FirstMI).getImm();
   int OffsetStride = IsUnscaled ? TII->getMemScale(FirstMI) : 1;
   bool IsPromotableZeroStore = isPromotableZeroStoreInst(FirstMI);
 
-  Optional<bool> MaybeCanRename = None;
-  if (!EnableRenaming)
-    MaybeCanRename = {false};
-
-  SmallPtrSet<const TargetRegisterClass *, 5> RequiredClasses;
-  LiveRegUnits UsedInBetween;
-  UsedInBetween.init(*TRI);
-
-  Flags.clearRenameReg();
-
   // Track which register units have been modified and used between the first
   // insn (inclusive) and the second insn.
   ModifiedRegUnits.clear();
   UsedRegUnits.clear();
 
   // Remember any instructions that read/write memory between FirstMI and MI.
   SmallVector<MachineInstr *, 4> MemInsns;
 
   for (unsigned Count = 0; MBBI != E && Count < Limit;
        MBBI = next_nodbg(MBBI, E)) {
     MachineInstr &MI = *MBBI;
 
-    UsedInBetween.accumulate(MI);
-
     // Don't count transient instructions towards the search limit since there
     // may be different numbers of them if e.g. debug information is present.
     if (!MI.isTransient())
       ++Count;
 
     Flags.setSExtIdx(-1);
     if (areCandidatesToMergeOrPair(FirstMI, MI, Flags, TII) &&
         getLdStOffsetOp(MI).isImm()) {
if (areCandidatesToMergeOrPair(FirstMI, MI, Flags, TII) &&
         // If the Rt of the second instruction was not modified or used between
         // the two instructions and none of the instructions between the second
         // and first alias with the second, we can combine the second into the
         // first.
         if (ModifiedRegUnits.available(getLdStRegOp(MI).getReg()) &&
             !(MI.mayLoad() &&
               !UsedRegUnits.available(getLdStRegOp(MI).getReg())) &&
             !mayAlias(MI, MemInsns, AA)) {
-
           Flags.setMergeForward(false);
-          Flags.clearRenameReg();
           return MBBI;
         }
 
         // Likewise, if the Rt of the first instruction is not modified or used
         // between the two instructions and none of the instructions between the
         // first and the second alias with the first, we can combine the first
         // into the second.
-        if (!(MayLoad &&
+        if (ModifiedRegUnits.available(getLdStRegOp(FirstMI).getReg()) &&
+            !(MayLoad &&
               !UsedRegUnits.available(getLdStRegOp(FirstMI).getReg())) &&
             !mayAlias(FirstMI, MemInsns, AA)) {
-
-          if (ModifiedRegUnits.available(getLdStRegOp(FirstMI).getReg())) {
-            Flags.setMergeForward(true);
-            Flags.clearRenameReg();
-            return MBBI;
-          }
-
-          if (DebugCounter::shouldExecute(RegRenamingCounter)) {
-            if (!MaybeCanRename)
-              MaybeCanRename = {canRenameUpToDef(FirstMI, UsedInBetween,
-                                                 RequiredClasses, TRI)};
-
-            if (*MaybeCanRename) {
-              Optional<MCPhysReg> MaybeRenameReg = tryToFindRegisterToRename(
-                  FirstMI, MI, DefinedInBB, UsedInBetween, RequiredClasses,
-                  TRI);
-              if (MaybeRenameReg) {
-                Flags.setRenameReg(*MaybeRenameReg);
-                Flags.setMergeForward(true);
-                MBBIWithRenameReg = MBBI;
-              }
-            }
-          }
-        }
         // Unable to combine these instructions due to interference in between.
         // Keep looking.
       }
     }
 
-    if (Flags.getRenameReg())
-      return MBBIWithRenameReg;
-
     // If the instruction wasn't a matching load or store.  Stop searching if we
     // encounter a call instruction that might modify memory.
     if (MI.isCall())
       return E;
 
     // Update modified / uses register units.
     LiveRegUnits::accumulateUsedDefed(MI, ModifiedRegUnits, UsedRegUnits, TRI);
 
bool AArch64LoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
   MachineBasicBlock::iterator Paired =
       findMatchingInsn(MBBI, Flags, LdStLimit, /* FindNarrowMerge = */ false);
   if (Paired != E) {
     ++NumPairCreated;
     if (TII->isUnscaledLdSt(MI))
       ++NumUnscaledPairCreated;
     // Keeping the iterator straight is a pain, so we let the merge routine tell
     // us what the next instruction is after it's done mucking about.
-    auto Prev = std::prev(MBBI);
     MBBI = mergePairedInsns(MBBI, Paired, Flags);
-    // Collect liveness info for instructions between Prev and the new position
-    // MBBI.
-    for (auto I = std::next(Prev); I != MBBI; I++)
-      updateDefinedRegisters(*I, DefinedInBB, TRI);
-
     return true;
   }
   return false;
 }
 
 bool AArch64LoadStoreOpt::tryToMergeLdStUpdate
     (MachineBasicBlock::iterator &MBBI) {
   MachineInstr &MI = *MBBI;
if (Update != E) {
     return true;
   }
 
   return false;
 }
 
 bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
                                         bool EnableNarrowZeroStOpt) {
-
   bool Modified = false;
   // Four tranformations to do here:
   // 1) Find loads that directly read from stores and promote them by
   //    replacing with mov instructions. If the store is wider than the load,
   //    the load will be replaced with a bitfield extract.
   //      e.g.,
   //        str w1, [x0, #4]
   //        ldrh w2, [x0, #6]
if (EnableNarrowZeroStOpt)
     }
   // 3) Find loads and stores that can be merged into a single load or store
   //    pair instruction.
   //      e.g.,
   //        ldr x0, [x2]
   //        ldr x1, [x2, #8]
   //        ; becomes
   //        ldp x0, x1, [x2]
-
-  if (MBB.getParent()->getRegInfo().tracksLiveness()) {
-    DefinedInBB.clear();
-    DefinedInBB.addLiveIns(MBB);
-  }
-
   for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
        MBBI != E;) {
-    // Track currently live registers up to this point, to help with
-    // searching for a rename register on demand.
-    updateDefinedRegisters(*MBBI, DefinedInBB, TRI);
     if (TII->isPairableLdStInst(*MBBI) && tryToPairLdStInst(MBBI))
       Modified = true;
     else
       ++MBBI;
   }
   // 4) Find base register updates that can be merged into the load or store
   //    as a base-reg writeback.
   //      e.g.,
bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
   TRI = Subtarget->getRegisterInfo();
   AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
 
   // Resize the modified and used register unit trackers.  We do this once
   // per function and then clear the register units each time we optimize a load
   // or store.
   ModifiedRegUnits.init(*TRI);
   UsedRegUnits.init(*TRI);
-  DefinedInBB.init(*TRI);
 
   bool Modified = false;
   bool enableNarrowZeroStOpt = !Subtarget->requiresStrictAlign();
-  for (auto &MBB : Fn) {
-    auto M = optimizeBlock(MBB, enableNarrowZeroStOpt);
-    Modified |= M;
-  }
+  for (auto &MBB : Fn)
+    Modified |= optimizeBlock(MBB, enableNarrowZeroStOpt);
 
   return Modified;
 }
 
 // FIXME: Do we need/want a pre-alloc pass like ARM has to try to keep loads and
 // stores near one another?  Note: The pre-RA instruction scheduler already has
 // hooks to try and schedule pairable loads/stores together to improve pairing
 // opportunities.  Thus, pre-RA pairing pass may not be worth the effort.

llvm/lib/Transforms/IPO/PassManagerBuilder.cpp

 cl::opt<bool> EnableOrderFileInstrumentation(
     "enable-order-file-instrumentation", cl::init(false), cl::Hidden,
     cl::desc("Enable order file instrumentation (default = off)"));
 
 cl::opt<bool> EnableMatrix(
     "enable-matrix", cl::init(false), cl::Hidden,
     cl::desc("Enable lowering of the matrix intrinsics"));
 
+cl::opt<bool> EnableMergeFunc("enable-mergefunc", cl::init(false), cl::Hidden,
+                              cl::desc("Enable merge function"));
+
 cl::opt<bool> EnableConstraintElimination(
     "enable-constraint-elimination", cl::init(false), cl::Hidden,
     cl::desc(
         "Enable pass to eliminate conditions based on linear constraints."));
 
 cl::opt<AttributorRunOption> AttributorRun(
     "attributor-enable", cl::Hidden, cl::init(AttributorRunOption::NONE),
     cl::desc("Enable the attributor inter-procedural deduction pass."),
PassManagerBuilder::PassManagerBuilder() {
     RerollLoops = RunLoopRerolling;
     NewGVN = RunNewGVN;
     LicmMssaOptCap = SetLicmMssaOptCap;
     LicmMssaNoAccForPromotionCap = SetLicmMssaNoAccForPromotionCap;
     DisableGVNLoadPRE = false;
     ForgetAllSCEVInLoopUnroll = ForgetSCEVInLoopUnroll;
     VerifyInput = false;
     VerifyOutput = false;
-    MergeFunctions = false;
+    MergeFunctions = EnableMergeFunc;
     SplitColdCode = false;
     PrepareForLTO = false;
     EnablePGOInstrGen = false;
     EnablePGOCSInstrGen = false;
     EnablePGOCSInstrUse = false;
     PGOInstrGen = "";
     PGOInstrUse = "";
     PGOSampleUse = "";
void PassManagerBuilder::addLTOOptimizationPasses(legacy::PassManagerBase &PM) {
   addInitialAliasAnalysisPasses(PM);
 
   // Allow forcing function attributes as a debugging and tuning aid.
   PM.add(createForceFunctionAttrsLegacyPass());
 
   // Infer attributes about declarations if possible.
   PM.add(createInferFunctionAttrsLegacyPass());
 
-  if (OptLevel > 1) {
+  if (OptLevel > 2) {
     // Split call-site with more constrained arguments.
     PM.add(createCallSiteSplittingPass());
 
     // Indirect call promotion. This should promote all the targets that are
     // left by the earlier promotion pass that promotes intra-module targets.
     // This two-step promotion is to save the compile time. For LTO, it should
     // produce the same result as if we only do promotion here.
     PM.add(
void PassManagerBuilder::addLTOOptimizationPasses(legacy::PassManagerBase &PM) {
 
   // That's all we need at opt level 1.
   if (OptLevel == 1)
     return;
 
   // Now that we internalized some globals, see if we can hack on them!
   PM.add(createGlobalOptimizerPass());
   // Promote any localized global vars.
-  PM.add(createPromoteMemoryToRegisterPass());
+  PM.add(createSROAPass());
+  PM.add(createEarlyCSEPass());
 
   // Linking modules together can lead to duplicated global constants, only
   // keep one copy of each constant.
   PM.add(createConstantMergePass());
 
   // Remove unused arguments from functions.
   PM.add(createDeadArgEliminationPass());
 
void PassManagerBuilder::addLTOOptimizationPasses(legacy::PassManagerBase &PM) {
   // transform it to pass arguments by value instead of by reference.
   PM.add(createArgumentPromotionPass());
 
   // The IPO passes may leave cruft around.  Clean up after them.
   PM.add(createInstructionCombiningPass());
   addExtensionsToPM(EP_Peephole, PM);
   PM.add(createJumpThreadingPass(/*FreezeSelectCond*/ true));
 
-  // Break up allocas
-  PM.add(createSROAPass());
-
   // LTO provides additional opportunities for tailcall elimination due to
   // link-time inlining, and visibility of nocapture attribute.
   if (OptLevel > 1)
     PM.add(createTailCallEliminationPass());
 
   // Infer attributes on declarations, call sites, arguments, etc.
   PM.add(createPostOrderFunctionAttrsLegacyPass()); // Add nocapture.
   // Run a few AA driven optimizations here and now, to cleanup the code.

llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -aarch64-load-store-renaming=true < %s -mtriple=arm64-apple-ios7.0.0 -mcpu=cyclone -enable-misched=false | FileCheck %s
 
 ; rdar://13625505
 ; Here we have 9 fixed integer arguments the 9th argument in on stack, the
 ; varargs start right after at 8-byte alignment.
 define void @fn9(i32* %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, ...) nounwind noinline ssp {
 ; CHECK-LABEL: fn9:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #64 ; =64
 ; CHECK-NEXT:    ldr w8, [sp, #64]
 ; CHECK-NEXT:    stp w2, w1, [sp, #52]
 ; CHECK-NEXT:    stp w4, w3, [sp, #44]
 ; CHECK-NEXT:    stp w6, w5, [sp, #36]
 ; CHECK-NEXT:    str w7, [sp, #32]
 ; CHECK-NEXT:    str w8, [x0]
-; CHECK-NEXT:    ldr w9, [sp, #72]
+; CHECK-NEXT:    ldr w8, [sp, #72]
+; CHECK-NEXT:    str w8, [sp, #20]
 ; CHECK-NEXT:    ldr w8, [sp, #80]
-; CHECK-NEXT:    stp w8, w9, [sp, #16]
+; CHECK-NEXT:    str w8, [sp, #16]
 ; CHECK-NEXT:    add x8, sp, #72 ; =72
 ; CHECK-NEXT:    add x8, x8, #24 ; =24
 ; CHECK-NEXT:    str x8, [sp, #24]
 ; CHECK-NEXT:    ldr w8, [sp, #88]
 ; CHECK-NEXT:    str w8, [sp, #12]
 ; CHECK-NEXT:    add sp, sp, #64 ; =64
 ; CHECK-NEXT:    ret
   %1 = alloca i32, align 4

 
 declare void @llvm.va_start(i8*) nounwind
 
 define i32 @main() nounwind ssp {
 ; CHECK-LABEL: main:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #96 ; =96
 ; CHECK-NEXT:    stp x29, x30, [sp, #80] ; 16-byte Folded Spill
-; CHECK-NEXT:    mov w9, #1
+; CHECK-NEXT:    mov w8, #1
+; CHECK-NEXT:    str w8, [sp, #76]
 ; CHECK-NEXT:    mov w8, #2
-; CHECK-NEXT:    stp w8, w9, [sp, #72]
-; CHECK-NEXT:    mov w9, #3
+; CHECK-NEXT:    str w8, [sp, #72]
+; CHECK-NEXT:    mov w8, #3
+; CHECK-NEXT:    str w8, [sp, #68]
 ; CHECK-NEXT:    mov w8, #4
-; CHECK-NEXT:    stp w8, w9, [sp, #64]
-; CHECK-NEXT:    mov w9, #5
+; CHECK-NEXT:    str w8, [sp, #64]
+; CHECK-NEXT:    mov w8, #5
+; CHECK-NEXT:    str w8, [sp, #60]
 ; CHECK-NEXT:    mov w8, #6
-; CHECK-NEXT:    stp w8, w9, [sp, #56]
-; CHECK-NEXT:    mov w9, #7
+; CHECK-NEXT:    str w8, [sp, #56]
+; CHECK-NEXT:    mov w8, #7
+; CHECK-NEXT:    str w8, [sp, #52]
 ; CHECK-NEXT:    mov w8, #8
-; CHECK-NEXT:    stp w8, w9, [sp, #48]
+; CHECK-NEXT:    str w8, [sp, #48]
 ; CHECK-NEXT:    mov w8, #9
 ; CHECK-NEXT:    mov w9, #10
 ; CHECK-NEXT:    stp w9, w8, [sp, #40]
 ; CHECK-NEXT:    mov w10, #11
 ; CHECK-NEXT:    mov w11, #12
 ; CHECK-NEXT:    stp w11, w10, [sp, #32]
 ; CHECK-NEXT:    stp x10, x11, [sp, #16]
 ; CHECK-NEXT:    str x9, [sp, #8]

llvm/test/CodeGen/AArch64/arm64-abi_align.ll

; FAST: add {{w[0-9]+}}, w[[C]], w[[B]]
   %add4 = add i32 %add3, %conv
   %add7 = add i32 %add4, %conv6
   ret i32 %add7
 }
 
 define i32 @caller43() #3 {
 entry:
 ; CHECK-LABEL: caller43
-; CHECK-DAG: stp q1, q0, [sp, #32]
-; CHECK-DAG: stp q1, q0, [sp]
+; CHECK-DAG: str {{q[0-9]+}}, [sp, #48]
+; CHECK-DAG: str {{q[0-9]+}}, [sp, #32]
+; CHECK-DAG: str {{q[0-9]+}}, [sp, #16]
+; CHECK-DAG: str {{q[0-9]+}}, [sp]
 ; CHECK: add x1, sp, #32
 ; CHECK: mov x2, sp
 ; Space for s1 is allocated at sp+32
 ; Space for s2 is allocated at sp
 
 ; FAST-LABEL: caller43
 ; FAST: add x29, sp, #64
 ; Space for s1 is allocated at sp+32
declare i32 @f43_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6,
                        i32 %i7, i32 %i8, i32 %i9, %struct.s43* nocapture %s1,
                        %struct.s43* nocapture %s2) #2
 
 define i32 @caller43_stack() #3 {
 entry:
 ; CHECK-LABEL: caller43_stack
 ; CHECK: sub sp, sp, #112
 ; CHECK: add x29, sp, #96
-; CHECK-DAG: stp q1, q0, [x29, #-32]
-; CHECK-DAG: stp q1, q0, [sp, #32]
+; CHECK-DAG: stur {{q[0-9]+}}, [x29, #-16]
+; CHECK-DAG: stur {{q[0-9]+}}, [x29, #-32]
+; CHECK-DAG: str {{q[0-9]+}}, [sp, #48]
+; CHECK-DAG: str {{q[0-9]+}}, [sp, #32]
 ; Space for s1 is allocated at x29-32 = sp+64
 ; Space for s2 is allocated at sp+32
 ; CHECK: add x[[B:[0-9]+]], sp, #32
 ; CHECK: str x[[B]], [sp, #16]
 ; CHECK: sub x[[A:[0-9]+]], x29, #32
 ; Address of s1 is passed on stack at sp+8
 ; CHECK: str x[[A]], [sp, #8]
 ; CHECK: mov w[[C:[0-9]+]], #9

llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll

 ; CHECK-DAG: stp q0, q1, [sp]
 ; ... omit middle ones ...
 ; CHECK-DAG: stp q6, q7, [sp, #
 
 ; CHECK: str [[STACK_TOP]], [x[[VA_LIST]]]
 
 ; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]]
 ; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #56
-
+; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8]
 
 ; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp
 ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #128
-; CHECK: stp [[GR_TOP]], [[VR_TOP]], [x[[VA_LIST]], #8]
+; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16]
 
 ; CHECK: mov     [[GRVR:x[0-9]+]], #-56
 ; CHECK: movk    [[GRVR]], #65408, lsl #32
 ; CHECK: str     [[GRVR]], [x[[VA_LIST]], #24]
 
   %addr = bitcast %va_list* @var to i8*
   call void @llvm.va_start(i8* %addr)
 

 ; CHECK-DAG: stp q6, q7, [sp, #80]
 ; ... omit middle ones ...
 ; CHECK-DAG: str q1, [sp]
 
 ; CHECK: str [[STACK_TOP]], [x[[VA_LIST]]]
 
 ; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]]
 ; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #40
+; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8]
 
 ; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp
 ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #112
-; CHECK: stp [[GR_TOP]], [[VR_TOP]], [x[[VA_LIST]], #8]
+; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16]
 
 ; CHECK: mov  [[GRVR_OFFS:x[0-9]+]], #-40
 ; CHECK: movk [[GRVR_OFFS]], #65424, lsl #32
 ; CHECK: str  [[GRVR_OFFS]], [x[[VA_LIST]], #24]
 
   %addr = bitcast %va_list* @var to i8*
   call void @llvm.va_start(i8* %addr)
 

llvm/test/CodeGen/AArch64/machine-outliner-remarks.ll

 ; RUN: llc %s -enable-machine-outliner -mtriple=aarch64-unknown-unknown -pass-remarks=machine-outliner -pass-remarks-missed=machine-outliner -o /dev/null 2>&1 | FileCheck %s
 ; CHECK: <unknown>:0:0:
 ; CHECK-SAME: Did not outline 2 instructions from 2 locations.
 ; CHECK-SAME: Bytes from outlining all occurrences (16) >=
 ; CHECK-SAME: Unoutlined instruction bytes (16)
 ; CHECK-SAME: (Also found at: <UNKNOWN LOCATION>)
-; CHECK: remark: <unknown>:0:0: Saved 40 bytes by outlining 13 instructions
+; CHECK: remark: <unknown>:0:0: Saved 52 bytes by outlining 16 instructions
 ; CHECK-SAME: from 2 locations. (Found at: <UNKNOWN LOCATION>,
 ; CHECK-SAME: <UNKNOWN LOCATION>)
 ; RUN: llc %s -enable-machine-outliner -mtriple=aarch64-unknown-unknown -o /dev/null -pass-remarks-missed=machine-outliner -pass-remarks-output=%t.yaml
 ; RUN: cat %t.yaml | FileCheck %s -check-prefix=YAML
 
 ; For the YAML case, the function we pick depends on the order of the candidate
 ; list.
 ; YAML: --- !Missed

 ; YAML-NEXT:   - OtherStartLoc1:  '<UNKNOWN LOCATION>'
 ; YAML-NEXT:   - String:          ')'
 ; YAML: --- !Passed
 ; YAML-NEXT: Pass:            machine-outliner
 ; YAML-NEXT: Name:            OutlinedFunction
 ; YAML-NEXT: Function:        OUTLINED_FUNCTION_0
 ; YAML-NEXT: Args:
 ; YAML-NEXT:   - String:          'Saved '
-; YAML-NEXT:   - OutliningBenefit: '40'
+; YAML-NEXT:   - OutliningBenefit: '52'
 ; YAML-NEXT:   - String:          ' bytes by '
 ; YAML-NEXT:   - String:          'outlining '
-; YAML-NEXT:   - Length:          '13'
+; YAML-NEXT:   - Length:          '16'
 ; YAML-NEXT:   - String:          ' instructions '
 ; YAML-NEXT:   - String:          'from '
 ; YAML-NEXT:   - NumOccurrences:  '2'
 ; YAML-NEXT:   - String:          ' locations. '
 ; YAML-NEXT:   - String:          '(Found at: '
 ; YAML-NEXT:   - StartLoc0:       '<UNKNOWN LOCATION>'
 ; YAML-NEXT:   - String:          ', '
 ; YAML-NEXT:   - StartLoc1:       '<UNKNOWN LOCATION>'

llvm/test/CodeGen/AArch64/machine-outliner-side-effect-2.mir

+# RUN: llc -mtriple=aarch64 -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
+
+# The test checks whether the compiler updates the side effect of function @OUTLINED_FUNCTION_0 by adding the use of register x0.
+
+--- |
+  declare void @spam() local_unnamed_addr
+  define void @bax() optsize minsize noredzone { ret void }
+  define void @bay() optsize minsize noredzone { ret void }
+  define void @baz() optsize minsize noredzone { ret void }
+...
+---
+name:            bax
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x0, $lr
+
+    $x1 = ADDXri $sp, 16, 0
+    BL @spam, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit killed $x1, implicit-def $sp, implicit-def dead $x0
+
+    RET_ReallyLR
+
+...
+---
+name:            bay
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x0, $lr
+
+    $x1 = ADDXri $sp, 16, 0
+    BL @spam, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit killed $x1, implicit-def $sp, implicit-def dead $x0
+
+    RET_ReallyLR
+
+...
+---
+name:            baz
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x0, $lr
+
+    $x1 = ADDXri $sp, 16, 0
+    BL @spam, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit killed $x1, implicit-def $sp, implicit-def dead $x0
+
+    RET_ReallyLR
+
+...
+
+# CHECK: BL @OUTLINED_FUNCTION_0, {{.*}}, implicit $x0

llvm/test/CodeGen/AArch64/machine-outliner-throw.ll

 ; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=aarch64-arm-none-eabi < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=aarch64-arm-none-eabi -stop-after=machine-outliner < %s | FileCheck %s -check-prefix=TARGET_FEATURES
 
 ; Make sure that we haven't added nouwind.
 ; TARGET_FEATURES: define internal void @OUTLINED_FUNCTION_0()
 ; TARGET_FEATURES-SAME: #[[ATTR_NUM:[0-9]+]]
-; TARGET_FEATURES: attributes #[[ATTR_NUM]] = { minsize optsize }
+; TARGET_FEATURES: attributes #[[ATTR_NUM]] = { minsize optsize "outliner"="true" }
 
 define dso_local i32 @_Z5func1i(i32 %x) #0 {
 ; CHECK-LABEL: _Z5func1i:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    .cfi_offset w19, -8
 ; CHECK-NEXT:    .cfi_offset w30, -16

llvm/test/CodeGen/AArch64/machine-outliner.ll

-; RUN: llc -verify-machineinstrs -enable-machine-outliner -aarch64-load-store-renaming=true -mtriple=aarch64-apple-darwin < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -enable-machine-outliner -aarch64-load-store-renaming=true -mtriple=aarch64-apple-darwin -mcpu=cortex-a53 -enable-misched=false < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -enable-machine-outliner -enable-linkonceodr-outlining -mtriple=aarch64-apple-darwin < %s | FileCheck %s -check-prefix=ODR
 ; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=aarch64-apple-darwin -stop-after=machine-outliner < %s | FileCheck %s -check-prefix=TARGET_FEATURES
 
 ; Make sure that we inherit target features from functions and make sure we have
 ; the right function attributes.
 ; TARGET_FEATURES: define internal void @OUTLINED_FUNCTION_{{[0-9]+}}()
 ; TARGET_FEATURES-SAME: #[[ATTR_NUM:[0-9]+]]
 ; TARGET_FEATURES-DAG: attributes #[[ATTR_NUM]] = {

llvm/test/CodeGen/AArch64/stp-opt-with-renaming-debug.mir

 # RUN: llc -run-pass=aarch64-ldst-opt -mtriple=arm64-apple-iphoneos -aarch64-load-store-renaming=true -verify-machineinstrs -o - %s | FileCheck %s
+; XFAIL: *
 --- |
   define void @test_dbg_value1() #0 { ret void }
   define void @test_dbg_value2() #0 { ret void }
 
   !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "llvm", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
   !1 = !DIFile(filename: "dbg.ll", directory: "/tmp")
   !2 = !{}
   !5 = distinct !DISubprogram(name: "test_dbg_value", scope: !1, file: !1, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, retainedNodes: !2)

llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir

 # RUN: llc -run-pass=aarch64-ldst-opt -aarch64-load-store-renaming=true -mattr=+reserve-x10 \
 # RUN:     -mattr=+reserve-x11 -mattr=+reserve-x15 -mtriple=arm64-apple-iphoneos -verify-machineinstrs \
 # RUN:     -o - %s | FileCheck --check-prefix=CHECK --check-prefix=PRESERVED %s
 
 # RUN: llc -run-pass=aarch64-ldst-opt -aarch64-load-store-renaming=true -mtriple=arm64-apple-iphoneos \
 # RUN:     -verify-machineinstrs -o - %s | FileCheck --check-prefix=CHECK --check-prefix=NOPRES %s
-
+; XFAIL: *
 
 # Make sure we do not pick reserved registers. For test1, we would pick x10,
 # and for test2 we would pick x15, both of which are reserved.
 #
 ---
 # CHECK-LABEL: name: test1
 # CHECK:       bb.0:
 # CHECK-NEXT:     liveins: $x0, $x1

llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

 # RUN: llc -run-pass=aarch64-ldst-opt -mtriple=arm64-apple-iphoneos -verify-machineinstrs -aarch64-load-store-renaming=true -o - %s | FileCheck %s
+; XFAIL: *
 # RUN: llc -run-pass=aarch64-ldst-opt -mtriple=arm64-apple-iphoneos -verify-machineinstrs -aarch64-load-store-renaming=false -o - %s | FileCheck --check-prefix=NO-RENAME %s
+; XFAIL: *
 
 # NO-RENAME-NOT: STP
 # NO-RENAME:     test12
 # NO-RENAME:     STP
 # NO-RENAME-NOT: STP
 #
 ---
 # CHECK-LABEL: name: test1

llvm/test/LTO/ARM/link-arm-and-thumb.ll

 ; Testcase to check that functions from a Thumb module can be inlined in an
 ; ARM function.
 ;
 ; RUN: llvm-as %s -o %t1.bc
 ; RUN: llvm-as %p/Inputs/thumb.ll -o %t2.bc
-; RUN: llvm-lto -exported-symbol main \
+; RUN: llvm-lto -O3 -exported-symbol main \
 ; RUN:          -exported-symbol bar \
 ; RUN:          -filetype=asm \
 ; RUN:          -o - \
 ; RUN:          %t1.bc %t2.bc 2> %t3.out| FileCheck %s
 ; RUN: FileCheck --allow-empty --input-file %t3.out --check-prefix STDERR %s
 
 target triple = "armv7-linux-gnueabihf"
 

llvm/test/Linker/Inputs/globalorder-2.ll

+; Test the order of global variables during llvm-link
+
+; RUN: llvm-link %s -o %t.bc
+; RUN: llvm-dis  -o - %t.bc | FileCheck %s
+
+@var5 = internal global i32 0, align 4
+@var6 = internal global i32 0, align 4
+@var7 = global i32* @var5, align 4
+@var8 = global i32* @var6, align 4
+
+define i32 @foo2() {
+entry:
+  %0 = load i32*, i32** @var7, align 4
+  %1 = load i32, i32* %0, align 4
+  %2 = load i32*, i32** @var8, align 4
+  %3 = load i32, i32* %2, align 4
+  %add = add nsw i32 %3, %1
+  ret i32 %add
+}
+; CHECK: @var7 =
+; CHECK-NEXT: @var8 =

llvm/test/Linker/comdat.ll

 
 $any = comdat any
 @any = global i64 6, comdat($any)
 
 ; CHECK: $qux = comdat largest
 ; CHECK: $foo = comdat largest
 ; CHECK: $any = comdat any
 
+; CHECK: @foo = global i64 43, comdat{{$}}
 ; CHECK: @qux = global i64 12, comdat{{$}}
 ; CHECK: @any = global i64 6, comdat{{$}}
-; CHECK: @foo = global i64 43, comdat{{$}}
 ; CHECK-NOT: @in_unselected_group = global i32 13, comdat $qux
 
 ; CHECK: define i32 @baz() comdat($qux)
 ; CHECK: define i32 @bar() comdat($foo)

llvm/test/Linker/comdat14.ll

 ; RUN: llvm-link -S %s %p/Inputs/comdat14.ll -o - | FileCheck %s
 
 $c = comdat any
 
 @v = global i32 0, comdat ($c)
 
 ; CHECK: @v = global i32 0, comdat($c)
-; CHECK: @v2 = external dllexport global i32
 ; CHECK: @v3 = external global i32
+; CHECK: @v2 = external dllexport global i32

llvm/test/Linker/ctors.ll

 ; RUN: llvm-link %s %p/Inputs/ctors.ll -S -o - | \
 ; RUN:   FileCheck --check-prefix=ALL --check-prefix=CHECK1 %s
 ; RUN: llvm-link %p/Inputs/ctors.ll %s -S -o - | \
 ; RUN:   FileCheck --check-prefix=ALL --check-prefix=CHECK2 %s
 
 ; Test the bitcode writer too. It used to crash.
 ; RUN: llvm-link %s %p/Inputs/ctors.ll -o %t.bc
 
+; ALL: @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @f, i8* @v }]
 @v = weak global i8 0
 ; CHECK1: @v = weak global i8 0
 ; CHECK2: @v = weak global i8 1
 
 @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @f, i8* @v }]
-; ALL: @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @f, i8* @v }]
 
 define weak void @f() {
   ret void
 }

llvm/test/Linker/ctors2.ll

 ; RUN: llvm-link -S %s %p/Inputs/ctors2.ll -o - | FileCheck %s
 
 $foo = comdat any
 @foo = global i8 0, comdat
 
-; CHECK: @foo = global i8 0, comdat
 ; CHECK: @llvm.global_ctors = appending global [0 x { i32, void ()*, i8* }] zeroinitializer
+; CHECK: @foo = global i8 0, comdat

llvm/test/Linker/ctors3.ll

 ; RUN: llvm-link -S %s %p/Inputs/ctors3.ll -o - | FileCheck %s
 
 $foo = comdat any
 %t = type { i8 }
 @foo = global %t zeroinitializer, comdat
 
-; CHECK: @foo = global %t zeroinitializer, comdat
 ; CHECK: @llvm.global_ctors = appending global [0 x { i32, void ()*, i8* }] zeroinitializer
+; CHECK: @foo = global %t zeroinitializer, comdat

llvm/test/Linker/globalorder.ll

+; Test the order of global variables during llvm-link
+
+; RUN: llvm-link %s %S/Inputs/globalorder-2.ll -o %t.bc
+; RUN: llvm-dis  -o - %t.bc | FileCheck %s
+
+@var1 = internal global i32 0, align 4
+@var2 = internal global i32 0, align 4
+@var3 = global i32* @var1, align 4
+@var4 = global i32* @var2, align 4
+
+define i32 @foo() {
+entry:
+  %0 = load i32*, i32** @var3, align 4
+  %1 = load i32, i32* %0, align 4
+  %2 = load i32*, i32** @var4, align 4
+  %3 = load i32, i32* %2, align 4
+  %add = add nsw i32 %3, %1
+  ret i32 %add
+}
+; CHECK: @var1 =
+; CHECK-NEXT: @var2 =
+; CHECK-NEXT: @var3 =
+; CHECK-NEXT: @var4 =
+; CHECK-NEXT: @var5 =
+; CHECK-NEXT: @var6 =
+; CHECK-NEXT: @var7 =
+; CHECK-NEXT: @var8 =

llvm/test/Linker/link-flags.ll

 ; RUN: llvm-link -S %S/Inputs/linkage.b.ll %S/Inputs/linkage.c.ll | FileCheck %s -check-prefix=B -check-prefix=C -check-prefix=CU
 ; RUN: llvm-link -S -only-needed %S/Inputs/linkage.b.ll %S/Inputs/linkage.c.ll | FileCheck %s -check-prefix=B -check-prefix=C -check-prefix=CN
 ; RUN: llvm-link -S -internalize %S/Inputs/linkage.b.ll %S/Inputs/linkage.c.ll | FileCheck %s -check-prefix=B -check-prefix=CI
 ; RUN: llvm-link -S -internalize -only-needed %S/Inputs/linkage.b.ll %S/Inputs/linkage.c.ll | FileCheck %s -check-prefix=B -check-prefix=CN
 ; RUN: llvm-link -S -internalize %S/Inputs/linkage.b.ll %S/Inputs/linkage.c.ll %S/Inputs/linkage.d.ll | FileCheck %s -check-prefix=B -check-prefix=DI
 
 C-LABEL: @X = global i32 5
 CI-LABEL: @X = internal global i32 5
 CU-LABEL:@U = global i32 6
 CI-LABEL:@U = internal global i32 6
 CN-NOT:@U
-DI-LABEL: @Y = global i8 42
 DI-LABEL: @llvm.used = appending global [2 x i8*] [i8* @Y, i8* bitcast (i64 ()* @foo to i8*)], section "llvm.metadata"
+DI-LABEL: @Y = global i8 42
 
 B-LABEL: define void @bar() {
 
 C-LABEL: define i32 @foo()
 CI-LABEL: define internal i32 @foo()
 
 CU-LABEL:define i32 @unused() {
 CI-LABEL:define internal i32 @unused() {
 CN-NOT:@unused()
 
 DI-LABEL: define internal i32 @foo.6()
 DI-LABEL: define i64 @foo()

llvm/test/Linker/metadata-attach.ll

 ; RUN: llvm-link %s -S -o - | FileCheck %s
 ; RUN: llvm-link %s %S/Inputs/metadata-attach.ll -S -o - | FileCheck --check-prefix=CHECK-LINKED1 %s
 ; RUN: llvm-link %S/Inputs/metadata-attach.ll %s -S -o - | FileCheck --check-prefix=CHECK-LINKED2 %s
 
 ; CHECK: @g1 = global i32 0, !attach !0{{$}}
 ; CHECK-LINKED1: @g1 = global i32 0, !attach !0{{$}}
 @g1 = global i32 0, !attach !0
 
-; CHECK: @g3 = weak global i32 1, !attach !0{{$}}
 ; CHECK: @g2 = external global i32, !attach !0{{$}}
+; CHECK: @g3 = weak global i32 1, !attach !0{{$}}
 ; CHECK-LINKED1: @g2 = global i32 1, !attach !1{{$}}
 @g2 = external global i32, !attach !0
 
 ; CHECK-LINKED1: @g3 = global i32 2, !attach !1{{$}}
 @g3 = weak global i32 1, !attach !0
 
-; CHECK-LINKED2: @g2 = global i32 1, !attach !0{{$}}
-; CHECK-LINKED2: @g3 = global i32 2, !attach !0{{$}}
-; CHECK-LINKED2: @g1 = global i32 0, !attach !1{{$}}
+; CHECK-LINKED2: @g1 = global i32 0, !attach !0{{$}}
+; CHECK-LINKED2: @g2 = global i32 1, !attach !1{{$}}
+; CHECK-LINKED2: @g3 = global i32 2, !attach !1{{$}}
 
 ; CHECK: define void @f1() !attach !0 {
 ; CHECK-LINKED1: define void @f1() !attach !0 {
 define void @f1() !attach !0 {
   call void @f2()
   store i32 0, i32* @g2
   ret void
 }
 
 ; CHECK: declare !attach !0 void @f2()
 ; CHECK-LINKED1: define void @f2() !attach !1 {
 declare !attach !0 void @f2()
 
 ; CHECK: define weak void @f3() !attach !0 {
 ; CHECK-LINKED1: define void @f3() !attach !1 {
 define weak void @f3() !attach !0 {
   ret void
 }
 
-; CHECK-LINKED2: define void @f2() !attach !0 {
-; CHECK-LINKED2: define void @f3() !attach !0 {
-; CHECK-LINKED2: define void @f1() !attach !1 {
+; CHECK-LINKED2: define void @f2() !attach !1 {
+; CHECK-LINKED2: define void @f3() !attach !1 {
+; CHECK-LINKED2: define void @f1() !attach !0 {
 
 ; CHECK-LINKED1: !0 = !{i32 0}
 ; CHECK-LINKED1: !1 = !{i32 1}
 
-; CHECK-LINKED2: !0 = !{i32 1}
-; CHECK-LINKED2: !1 = !{i32 0}
+; CHECK-LINKED2: !0 = !{i32 0}
+; CHECK-LINKED2: !1 = !{i32 1}
 
 !0 = !{i32 0}

llvm/test/Linker/testlink.ll

 ; RUN: llvm-link %s %S/Inputs/testlink.ll -S | FileCheck %s
 
-; CHECK: %Ty2 = type { %Ty1* }
 ; CHECK: %Ty1 = type { %Ty2* }
+; CHECK: %Ty2 = type { %Ty1* }
 %Ty1 = type opaque
 %Ty2 = type { %Ty1* }
 
 ; CHECK: %intlist = type { %intlist*, i32 }
 %intlist = type { %intlist*, i32 }
 
 ; The uses of intlist in the other file should be remapped.
 ; CHECK-NOT: {{%intlist.[0-9]}}

llvm/test/ThinLTO/X86/import-constant.ll

 ; RUN:    -r=%t2.bc,val,pl \
 ; RUN:    -r=%t2.bc,outer,pl
 ; RUN: llvm-dis %t-out-norefs.1.3.import.bc -o - | FileCheck %s --check-prefix=NOREFS
 
 ; Check that variable has been promoted in the source module
 ; PROMOTE: @_ZL3Obj.llvm.{{.*}} = hidden constant %struct.S { i32 4, i32 8, i32* @val }
 
 ; @outer is a write-only variable, so it's been converted to zeroinitializer.
-; IMPORT:      @outer = internal local_unnamed_addr global %struct.Q zeroinitializer
+; IMPORT:      @val = available_externally global i32 42
 ; IMPORT-NEXT: @_ZL3Obj.llvm.{{.*}} = available_externally hidden constant %struct.S { i32 4, i32 8, i32* @val }
-; IMPORT-NEXT: @val = available_externally global i32 42
+; IMPORT-NEXT: @outer = internal local_unnamed_addr global %struct.Q zeroinitializer
 
 ; OPT: @outer = internal unnamed_addr global %struct.Q zeroinitializer
 
 ; OPT:      define dso_local i32 @main()
 ; OPT-NEXT: entry:
 ; OPT-NEXT:   store %struct.S* null, %struct.S** getelementptr inbounds (%struct.Q, %struct.Q* @outer, i64 0, i32 0)
 ; OPT-NEXT:   ret i32 12
 
-; NOREFS:      @outer = internal local_unnamed_addr global %struct.Q zeroinitializer
-; NOREFS-NEXT: @_ZL3Obj.llvm.{{.*}} = external hidden constant %struct.S
+; NOREFS:      @_ZL3Obj.llvm.{{.*}} = external hidden constant %struct.S
+; NOREFS-NEXT: @outer = internal local_unnamed_addr global %struct.Q zeroinitializer
 
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 %struct.S = type { i32, i32, i32* }
 
 define dso_local i32 @main() local_unnamed_addr {
 entry:

llvm/test/ThinLTO/X86/index-const-prop2.ll

 ; RUN:  -r=%t1.bc,gBar, \
 ; RUN:  -o %t5
 ; RUN: llvm-dis %t5.1.3.import.bc -o - | FileCheck %s --check-prefix=IMPORT-WRITEONLY
 ; RUN: llvm-dis %t5.1.5.precodegen.bc -o - | FileCheck %s --check-prefix=CODEGEN2
 ; Check that gFoo and gBar were eliminated from source module together
 ; with corresponsing stores
 ; RUN: llvm-dis %t5.2.5.precodegen.bc -o - | FileCheck %s --check-prefix=CODEGEN2-SRC
 
-; IMPORT:       @gFoo.llvm.0 = internal unnamed_addr global i32 1, align 4
-; IMPORT-NEXT:  @gBar = internal local_unnamed_addr global i32 2, align 4
+; IMPORT:  @gBar = internal local_unnamed_addr global i32 2, align 4
+; IMPORT-NEXT:       @gFoo.llvm.0 = internal unnamed_addr global i32 1, align 4
 ; IMPORT:       !DICompileUnit({{.*}})
 
 ; Write only variables are imported with a zero initializer.
-; IMPORT-WRITEONLY:  @gFoo.llvm.0 = internal unnamed_addr global i32 0
 ; IMPORT-WRITEONLY:  @gBar = internal local_unnamed_addr global i32 0
+; IMPORT-WRITEONLY:  @gFoo.llvm.0 = internal unnamed_addr global i32 0
 
 ; CODEGEN:        i32 @main()
 ; CODEGEN-NEXT:     ret i32 3
 
 ; IMPORT2: @gBar = available_externally local_unnamed_addr global i32 2, align 4
 
 ; CODEGEN2:      i32 @main2
 ; CODEGEN2-NEXT:   %1 = tail call i32 @rand()

llvm/test/ThinLTO/X86/writeonly2.ll

 ; RUN:  -r=%t1.bc,gBar, \
 ; RUN:  -o %t3
 ; RUN: llvm-dis %t3.1.3.import.bc -o - | FileCheck %s --check-prefix=IMPORT
 ; RUN: llvm-dis %t3.1.5.precodegen.bc -o - | FileCheck %s --check-prefix=CODEGEN
 ; Check that gFoo and gBar were eliminated from source module together
 ; with corresponsing stores
 ; RUN: llvm-dis %t3.2.5.precodegen.bc -o - | FileCheck %s --check-prefix=CODEGEN-SRC
 
-; IMPORT:       @gFoo.llvm.0 = internal unnamed_addr global i32 0, align 4
-; IMPORT-NEXT:  @gBar = internal local_unnamed_addr global i32 0, align 4
+; IMPORT:  @gBar = internal local_unnamed_addr global i32 0, align 4
+; IMPORT-NEXT:       @gFoo.llvm.0 = internal unnamed_addr global i32 0, align 4
 ; IMPORT:       !DICompileUnit({{.*}})
 
 ; CODEGEN-NOT:  gFoo
 ; CODEGEN-NOT:  gBar
 ; CODEGEN:      i32 @main
 ; CODEGEN-NEXT:   %1 = tail call i32 @rand()
 ; CODEGEN-NEXT:   %2 = tail call i32 @rand()
 ; CODEGEN-NEXT:   ret i32 0

llvm/tools/lto/lto.cpp

 static void lto_add_attrs(lto_code_gen_t cg) {
   LTOCodeGenerator *CG = unwrap(cg);
   auto MAttrs = codegen::getMAttrs();
   if (!MAttrs.empty()) {
     std::string attrs = join(MAttrs, ",");
     CG->setAttr(attrs);
   }
 
-  if (OptLevel < '0' || OptLevel > '3')
-    report_fatal_error("Optimization level must be between 0 and 3");
+  if (OptLevel == 's')
+    OptLevel = '4';
+  else if (OptLevel == 'z')
+    OptLevel = '5';
+  if (OptLevel < '0' || OptLevel > '5')
+    report_fatal_error(
+        "Optimization level must be between 0 and 3 or Os or Oz");
   CG->setOptLevel(OptLevel - '0');
   CG->setFreestanding(EnableFreestanding);
 }
 
 extern const char* lto_get_version() {
   return LTOCodeGenerator::getVersionString();
 }
 

 thinlto_code_gen_t thinlto_create_codegen(void) {
   lto_initialize();
   ThinLTOCodeGenerator *CodeGen = new ThinLTOCodeGenerator();
   CodeGen->setTargetOptions(
       codegen::InitTargetOptionsFromCodeGenFlags(Triple()));
   CodeGen->setFreestanding(EnableFreestanding);
 
   if (OptLevel.getNumOccurrences()) {
-    if (OptLevel < '0' || OptLevel > '3')
-      report_fatal_error("Optimization level must be between 0 and 3");
+    if (OptLevel == 's')
+      OptLevel = '4';
+    else if (OptLevel == 'z')
+      OptLevel = '5';
+    if (OptLevel < '0' || OptLevel > '5')
+      report_fatal_error(
+          "Optimization level must be between 0 and 3 or Os or Oz");
     CodeGen->setOptLevel(OptLevel - '0');
     switch (OptLevel) {
     case '0':
       CodeGen->setCodeGenOptLevel(CodeGenOpt::None);
       break;
     case '1':
       CodeGen->setCodeGenOptLevel(CodeGenOpt::Less);
       break;