- User Since
- Oct 8 2015, 3:17 PM (241 w, 6 d)
Apr 6 2020
Mar 18 2020
Testing Time: 128.22s
Expected Passes : 36105 Expected Failures : 163 Unsupported Tests : 336
I have made minor changes in test case llvm/test/CodeGen/AArch64/machine-outliner-iterative.mir.
Mar 17 2020
Mar 16 2020
Mar 13 2020
Mar 11 2020
Mar 10 2020
Thank you all for your review and suggestions!
Mar 9 2020
I have not made changes in swift side since the changes in LLVM have to go in first.
Mar 6 2020
Mar 5 2020
Mar 4 2020
All the llvm-lit tests passed without any unexpected fails.
I have updated the diffs. Now when you compare Diff 248212 with Diff 248301, you will see they are the same.
Simplified the test case.
Mar 3 2020
Mar 2 2020
Thank you Jessica for quick feedback. I have updated the test case based on your advice.
Feb 27 2020
Feb 25 2020
Feb 24 2020
Update with llvm-link test case.
Feb 21 2020
Update the test from IR file to MIR file.
Feb 20 2020
Updated test case.
Feb 14 2020
Also, I guess it would also be good to add a testcase that ensures that a register is not added as implicit when it's undefined in the range.
Feb 13 2020
The reason that the implicit defs are duplicate is because the compiler traverses the instructions in the reverse order and update the side effect of the new call instruction on the fly.
So the def reg set is introduced to avoid the redundant register.
More minor changes.
Fix typos in the comments.
I have updated the code based on reviewers' feedback and added one test case. Thanks.