[X86] Remove little support we had for MPX

[MaskRay]

Summary

GCC 9.1 removed Intel MPX support. Linux kernel removed MPX in 2019.
Our support is limited: we support assembling of bndmov but not bnd.

Just remove MPX code.

[skan]

GCC 9.1 removed Intel MPX support. Linux kernel removed MPX in 2019.

Could you provide some links by comments？

[MaskRay]

https://gcc.gnu.org/gcc-9/changes.html "Support of Intel MPX (Memory Protection Extensions) has been removed."

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ccaaaf6fe5a5e1fffca5cca0f3fc4ec84d7ae752

Mentioning the removal should be sufficient, no need to add them to the summary (commit message).

[craig.topper]

Does binutils still support MPX?

llvm/lib/Target/X86/X86InstrMPX.td

19

Should the BNDR register class from X86RegisterInfo.td be removed?

[MaskRay]

Remove the BNDR register class from X86RegisterInfo.td

[pengfei]

Seems the two fails are both related to this change.

[MaskRay]

fix tests

[pengfei]

LGTM.

[skan]

LGTM

llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp

static uint16_t name(struct InternalInstruction *insn, OperandType type,     \
     case TYPE_SEGMENTREG:                                                      \
       if ((index & 7) > 5)                                                     \
         *valid = 0;                                                            \
       return prefix##_ES + (index & 7);                                        \
     case TYPE_DEBUGREG:                                                        \
       return prefix##_DR0 + index;                                             \
     case TYPE_CONTROLREG:                                                      \
       return prefix##_CR0 + index;                                             \
-    case TYPE_BNDR:                                                            \
-      if (index > 3)                                                           \
-        *valid = 0;                                                            \
-      return prefix##_BND0 + index;                                            \
     case TYPE_MVSIBX:                                                          \
       return prefix##_XMM0 + index;                                            \
     case TYPE_MVSIBY:                                                          \
       return prefix##_YMM0 + index;                                            \
     case TYPE_MVSIBZ:                                                          \
       return prefix##_ZMM0 + index;                                            \
     }                                                                          \
   }

llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h

#define REGS_CONTROL  \
   ENTRY(CR9)          \
   ENTRY(CR10)         \
   ENTRY(CR11)         \
   ENTRY(CR12)         \
   ENTRY(CR13)         \
   ENTRY(CR14)         \
   ENTRY(CR15)
 
-#define REGS_BOUND    \
-  ENTRY(BND0)         \
-  ENTRY(BND1)         \
-  ENTRY(BND2)         \
-  ENTRY(BND3)
-
 #undef  REGS_TMM
 #define REGS_TMM  \
   ENTRY(TMM0)     \
   ENTRY(TMM1)     \
   ENTRY(TMM2)     \
   ENTRY(TMM3)     \
   ENTRY(TMM4)     \
   ENTRY(TMM5)     \
   ENTRY(TMM6)     \
   ENTRY(TMM7)
 
 #define ALL_EA_BASES  \
   EA_BASES_16BIT      \
   EA_BASES_32BIT      \
   EA_BASES_64BIT
 
 #define ALL_SIB_BASES \
   REGS_32BIT          \
   REGS_64BIT
 
 #define ALL_REGS      \
   REGS_8BIT           \
   REGS_16BIT          \
   REGS_32BIT          \
   REGS_64BIT          \
   REGS_MMX            \
   REGS_XMM            \
   REGS_YMM            \
   REGS_ZMM            \
   REGS_MASKS          \
   REGS_MASK_PAIRS     \
   REGS_SEGMENT        \
   REGS_DEBUG          \
   REGS_CONTROL        \
-  REGS_BOUND          \
   REGS_TMM            \
   ENTRY(RIP)
 
 /// All possible values of the base field for effective-address
 /// computations, a.k.a. the Mod and R/M fields of the ModR/M byte.
 /// We distinguish between bases (EA_BASE_*) and registers that just happen
 /// to be referred to when Mod == 0b11 (EA_REG_*).
 enum EABase {

llvm/lib/Target/X86/X86InstrInfo.cpp

if (X86::VR128XRegClass.hasSubClassEq(RC)) {
            HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
            HasAVX    ? X86::VMOVUPSrm :
                        X86::MOVUPSrm):
           (HasVLX    ? X86::VMOVUPSZ128mr :
            HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
            HasAVX    ? X86::VMOVUPSmr :
                        X86::MOVUPSmr);
     }
-    if (X86::BNDRRegClass.hasSubClassEq(RC)) {
-      if (STI.is64Bit())
-        return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
-      else
-        return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
-    }
     llvm_unreachable("Unknown 16-byte regclass");
   }
   case 32:
     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
     // If stack is realigned we can use aligned stores.
     if (IsStackAligned)
       return load ?
         (HasVLX    ? X86::VMOVAPSZ256rm :

llvm/lib/Target/X86/X86InstrInfo.td

 include "X86InstrXOP.td"
 
 // SSE, MMX and 3DNow! vector support.
 include "X86InstrSSE.td"
 include "X86InstrAVX512.td"
 include "X86InstrMMX.td"
 include "X86Instr3DNow.td"
 
-// MPX instructions
-include "X86InstrMPX.td"
-
 include "X86InstrVMX.td"
 include "X86InstrSVM.td"
 include "X86InstrSNP.td"
 
 include "X86InstrTSX.td"
 include "X86InstrSGX.td"
 
 include "X86InstrTDX.td"

llvm/lib/Target/X86/X86InstrMPX.td

-//===-- X86InstrMPX.td - MPX Instruction Set ---------*- tablegen -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the X86 MPX instruction set, defining the
-// instructions, and properties of the instructions which are needed for code
-// generation, machine code emission, and analysis.
-//
-//===----------------------------------------------------------------------===//
-
-// FIXME: Investigate a better scheduler class if MPX is ever used inside LLVM.
-let SchedRW = [WriteSystem] in {
-
-multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> {
-  def 32rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
-              OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
-              Requires<[Not64BitMode]>;
-  def 64rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
-              OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
-              Requires<[In64BitMode]>;
-}
-
-defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS;
-
-multiclass mpx_bound_check<bits<8> opc, string OpcodeStr> {
-  def 32rm: I<opc, MRMSrcMem, (outs), (ins  BNDR:$src1, anymem:$src2),
-              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
-              Requires<[Not64BitMode]>;
-  def 64rm: I<opc, MRMSrcMem, (outs), (ins  BNDR:$src1, anymem:$src2),
-              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
-              Requires<[In64BitMode]>;
-
-  def 32rr: I<opc, MRMSrcReg, (outs), (ins  BNDR:$src1, GR32:$src2),
-              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
-              Requires<[Not64BitMode]>;
-  def 64rr: I<opc, MRMSrcReg, (outs), (ins  BNDR:$src1, GR64:$src2),
-              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
-              Requires<[In64BitMode]>;
-}
-defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS, NotMemoryFoldable;
-defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD, NotMemoryFoldable;
-defm BNDCN : mpx_bound_check<0x1B, "bndcn">, XD, NotMemoryFoldable;
-
-def BNDMOVrr   : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src),
-                  "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
-                  NotMemoryFoldable;
-let mayLoad = 1 in {
-def BNDMOV32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
-                  "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
-                  Requires<[Not64BitMode]>, NotMemoryFoldable;
-def BNDMOV64rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src),
-                  "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
-                  Requires<[In64BitMode]>, NotMemoryFoldable;
-}
-let isCodeGenOnly = 1, ForceDisassemble = 1 in
-def BNDMOVrr_REV   : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src),
-                       "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
-                       NotMemoryFoldable;
-let mayStore = 1 in {
-def BNDMOV32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src),
-                  "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
-                  Requires<[Not64BitMode]>, NotMemoryFoldable;
-def BNDMOV64mr : I<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src),
-                  "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
-                  Requires<[In64BitMode]>, NotMemoryFoldable;
-
-def BNDSTXmr:      I<0x1B, MRMDestMem, (outs), (ins anymem:$dst, BNDR:$src),
-                    "bndstx\t{$src, $dst|$dst, $src}", []>, PS;
-}
-let mayLoad = 1 in
-def BNDLDXrm:      I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
-                    "bndldx\t{$src, $dst|$dst, $src}", []>, PS;
-} // SchedRW

llvm/lib/Target/X86/X86RegisterInfo.td

 def CR13 : X86Reg<"cr13", 13>;
 def CR14 : X86Reg<"cr14", 14>;
 def CR15 : X86Reg<"cr15", 15>;
 
 // Pseudo index registers
 def EIZ : X86Reg<"eiz", 4>;
 def RIZ : X86Reg<"riz", 4>;
 
-// Bound registers, used in MPX instructions
-def BND0 : X86Reg<"bnd0",   0>;
-def BND1 : X86Reg<"bnd1",   1>;
-def BND2 : X86Reg<"bnd2",   2>;
-def BND3 : X86Reg<"bnd3",   3>;
-
 // CET registers - Shadow Stack Pointer
 def SSP : X86Reg<"ssp", 0>;
 
 //===----------------------------------------------------------------------===//
 // Register Class Definitions... now that we have all of the pieces, define the
 // top-level register classes.  The order specified in the register list is
 // implicitly defined to be the register allocation order.
 //

 def VK1WM   : RegisterClass<"X86", [v1i1],  16,  (sub VK1, K0)> {let Size = 16;}
 def VK2WM   : RegisterClass<"X86", [v2i1],  16,  (sub VK2, K0)> {let Size = 16;}
 def VK4WM   : RegisterClass<"X86", [v4i1],  16,  (sub VK4, K0)> {let Size = 16;}
 def VK8WM   : RegisterClass<"X86", [v8i1],  16,  (sub VK8, K0)> {let Size = 16;}
 def VK16WM  : RegisterClass<"X86", [v16i1], 16, (add VK8WM)>   {let Size = 16;}
 def VK32WM  : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}
 def VK64WM  : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}
 
-// Bound registers
-def BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>;
-
 // Tiles
 let CopyCost = -1 in // Don't allow copying of tile registers
 def TILE : RegisterClass<"X86", [x86amx], 8192,
                          (sequence "TMM%u", 0, 7)> {let Size = 8192;}

llvm/test/MC/X86/mpx-encodings.s

-// RUN: llvm-mc -triple x86_64-- --show-encoding %s |\
-// RUN:   FileCheck %s --check-prefixes=CHECK,ENCODING
-
-// RUN: llvm-mc -triple x86_64-- -filetype=obj %s |\
-// RUN:   llvm-objdump -d - | FileCheck %s
-
-// CHECK: bndmk (%rax), %bnd0
-// ENCODING:  encoding: [0xf3,0x0f,0x1b,0x00]
-bndmk (%rax), %bnd0
-
-// CHECK: bndmk 1024(%rax), %bnd1
-// ENCODING:  encoding: [0xf3,0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
-bndmk 1024(%rax), %bnd1
-
-// CHECK: bndmov  %bnd2, %bnd1
-// ENCODING:  encoding: [0x66,0x0f,0x1a,0xca]
-bndmov %bnd2, %bnd1
-
-// CHECK: bndmov %bnd1, 1024(%r9)
-// ENCODING:  encoding: [0x66,0x41,0x0f,0x1b,0x89,0x00,0x04,0x00,0x00]
-bndmov %bnd1, 1024(%r9)
-
-// CHECK: bndstx %bnd1, 1024(%rax)
-// ENCODING:  encoding: [0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
-bndstx %bnd1, 1024(%rax)
-
-// CHECK: bndldx 1024(%r8), %bnd1
-// ENCODING:  encoding: [0x41,0x0f,0x1a,0x88,0x00,0x04,0x00,0x00]
-bndldx 1024(%r8), %bnd1
-
-// CHECK: bndcl 121(%r10), %bnd1
-// ENCODING:  encoding: [0xf3,0x41,0x0f,0x1a,0x4a,0x79]
-bndcl 121(%r10), %bnd1
-
-// CHECK: bndcn 121(%rcx), %bnd3
-// ENCODING:  encoding: [0xf2,0x0f,0x1b,0x59,0x79]
-bndcn 121(%rcx), %bnd3
-
-// CHECK: bndcu %rdx, %bnd3
-// ENCODING:  encoding: [0xf2,0x0f,0x1a,0xda]
-bndcu %rdx, %bnd3

llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

auto Error = Generator.generateConfigurations(
       &Instr, Configs, State.getRATC().emptyRegisters());
   ASSERT_FALSE(Error);
   ASSERT_THAT(Configs, SizeIs(1));
   const BenchmarkCode &BC = Configs[0];
   ASSERT_THAT(BC.Key.Instructions, SizeIs(1));
   ASSERT_TRUE(BC.Key.Instructions[0].getOperand(3).isImm());
 }
 
-TEST_F(X86ParallelSnippetGeneratorTest, ParallelInstruction) {
-  // - BNDCL32rr
-  // - Op0 Explicit Use RegClass(BNDR)
-  // - Op1 Explicit Use RegClass(GR32)
-  // - Var0 [Op0]
-  // - Var1 [Op1]
-  const unsigned Opcode = X86::BNDCL32rr;
-  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
-  ASSERT_THAT(CodeTemplates, SizeIs(1));
-  const auto &CT = CodeTemplates[0];
-  EXPECT_THAT(CT.Info, HasSubstr("parallel"));
-  EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
-  ASSERT_THAT(CT.Instructions, SizeIs(1));
-  const InstructionTemplate &IT = CT.Instructions[0];
-  EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
-  EXPECT_THAT(IT.getVariableValues()[0], IsInvalid());
-  EXPECT_THAT(IT.getVariableValues()[1], IsInvalid());
-}
-
 TEST_F(X86ParallelSnippetGeneratorTest, SerialInstruction) {
   // - CDQ
   // - Op0 Implicit Def Reg(EAX)
   // - Op1 Implicit Def Reg(EDX)
   // - Op2 Implicit Use Reg(EAX)
   // - hasAliasingImplicitRegisters (execution is always serial)
   // - hasAliasingRegisters
   const unsigned Opcode = X86::CDQ;