X86InstrInfo: Optimize more combinations of SUB+CMP

[MatzeB]

Summary

X86InstrInfo::optimizeCompareInstr would only optimize a SUB followed by a CMP in isRedundantFlagInstr. This extends the code to also look for other combinations like CMP+CMP, TEST+TEST, SUB x,0+TEST.

• Change isRedundantFlagInstr to run analyzeCompareInstr on the candidate instruction and compare the results. This normalizes things and gives consistent results for various comparisons (CMP x, y, SUB x, y) and immediate cases (TEST x, x, SUB x, 0, CMP x, 0...).
• Turn isRedundantFlagInstr into a member function so it can call analyzeCompare.
• We now also check isRedundantFlagInstr even if IsCmpZero is true, since we now have cases like TEST+TEST.

[pengfei]

llvm/test/CodeGen/X86/optimize-compare.mir

189

Do we have such CMP + CMP cases in reality? I think optimization should merged them already. The only case I can think is eflags are clobbered, so that we have to def them again which can't be optimizated here either.

[MatzeB]

ping

[MatzeB]

Do we have such CMP + CMP cases in reality? I think optimization should merged them already. The only case I can think is eflags are clobbered, so that we have to def them again which can't be optimizated here either.

Yes we do:

• If they are in different basic blocks, then SelectionDAG won't merge them.
• SelectionDAG has a tendency to canonicalize into different directions. My motivating sourcecode here says if (x == 1) { ... } else if (x > 1) { ... } but SeletionDAG normalizes that to x == 1 and x >= 2 so generic mechanisms like MachineCSE are not catching it.
• I've also seen several examples now, where we middleend canonicalization for i1 values leads to strange outcomes. You can for example look at https://godbolt.org/z/1T63zKqvc and see how the same comparison is repeated there (yes we should rather fix the root cause for that, but for now it's one more example of duplicated comparisons).

[pengfei]

In D110865#3062884, @MatzeB wrote:

Do we have such CMP + CMP cases in reality? I think optimization should merged them already. The only case I can think is eflags are clobbered, so that we have to def them again which can't be optimizated here either.

Yes we do:

• If they are in different basic blocks, then SelectionDAG won't merge them.
• SelectionDAG has a tendency to canonicalize into different directions. My motivating sourcecode here says if (x == 1) { ... } else if (x > 1) { ... } but SeletionDAG normalizes that to x == 1 and x >= 2 so generic mechanisms like MachineCSE are not catching it.
• I've also seen several examples now, where we middleend canonicalization for i1 values leads to strange outcomes. You can for example look at https://godbolt.org/z/1T63zKqvc and see how the same comparison is repeated there (yes we should rather fix the root cause for that, but for now it's one more example of duplicated comparisons).

Makes sense to me. Thank you!

[MatzeB]

rebase

[MatzeB]

ping

[RKSimon]

llvm/test/CodeGen/X86/optimize-compare.mir

176

Pre-commit these and rebase so the patch show the codegen diff?

[RKSimon]

llvm/lib/Target/X86/X86InstrInfo.h

637

SrcRegs -> SrcReg2 ?

638

Please describe IsSwapped as well

[MatzeB]

• Rebased on precommitted tests.
• Rewrite docu comment for isRedundantCompareInstr.

[MatzeB]

llvm/lib/Target/X86/X86InstrInfo.h

637

I previously just moved this text from the .cpp file...

I'll rewrite the whole comment from scratch.

[MatzeB]

Document new SrcReg2.isPhysical() test. (The test fixes a pre-existing bug though likely benign since nothing should actually use physical registers on CMP/SUB/TEST instructions that early in the codegen pipeline)

[RKSimon]

SGTM, does anyone else have any comments?

llvm/lib/Target/X86/X86InstrInfo.cpp

4329

worth moving this up, just after the switch()?

4498–4499

assert message?

[RKSimon]

LGTM

llvm/lib/Target/X86/X86InstrInfo.h

private:
   /// can be interpreted as a query asking to find an operand that would be
   /// commutable with the operand#1.
   ///
   /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
   bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
                                      unsigned &SrcOpIdx1,
                                      unsigned &SrcOpIdx2,
                                      bool IsIntrinsic = false) const;
+
+  /// Check whether the first instruction, whose only
+  /// purpose is to update flags, can be made redundant.
+  /// CMPrr can be made redundant by SUBrr if the operands are the same.
+  /// This function can be extended later on.
+  /// SrcReg, SrcRegs: register operands for FlagI.
+  /// ImmValue: immediate for FlagI if it takes an immediate.
+  bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg,
+                            Register SrcReg2, int64_t ImmMask, int64_t ImmValue,
+                            const MachineInstr &OI, bool *IsSwapped) const;
 };
 
 } // namespace llvm
 
 #endif

llvm/lib/Target/X86/X86InstrInfo.cpp

case X86::TEST64rr:
     SrcReg2 = 0;
     CmpMask = ~0;
     CmpValue = 0;
     return true;
   }
   return false;
 }
 
-/// Check whether the first instruction, whose only
-/// purpose is to update flags, can be made redundant.
-/// CMPrr can be made redundant by SUBrr if the operands are the same.
-/// This function can be extended later on.
-/// SrcReg, SrcRegs: register operands for FlagI.
-/// ImmValue: immediate for FlagI if it takes an immediate.
-inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
+bool X86InstrInfo::isRedundantFlagInstr(const MachineInstr &FlagI,
                                         Register SrcReg, Register SrcReg2,
                                         int64_t ImmMask, int64_t ImmValue,
-                                        const MachineInstr &OI) {
-  if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
-       (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
-       (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
-       (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
-      ((OI.getOperand(1).getReg() == SrcReg &&
-        OI.getOperand(2).getReg() == SrcReg2) ||
-       (OI.getOperand(1).getReg() == SrcReg2 &&
-        OI.getOperand(2).getReg() == SrcReg)))
-    return true;
-
-  if (ImmMask != 0 &&
-      ((FlagI.getOpcode() == X86::CMP64ri32 &&
-        OI.getOpcode() == X86::SUB64ri32) ||
-       (FlagI.getOpcode() == X86::CMP64ri8 &&
-        OI.getOpcode() == X86::SUB64ri8) ||
-       (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
-       (FlagI.getOpcode() == X86::CMP32ri8 &&
-        OI.getOpcode() == X86::SUB32ri8) ||
-       (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
-       (FlagI.getOpcode() == X86::CMP16ri8 &&
-        OI.getOpcode() == X86::SUB16ri8) ||
-       (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
-      OI.getOperand(1).getReg() == SrcReg &&
-      OI.getOperand(2).getImm() == ImmValue)
+                                        const MachineInstr &OI,
+                                        bool *IsSwapped) const {
+  switch (OI.getOpcode()) {
+  case X86::CMP64rr:
+  case X86::CMP32rr:
+  case X86::CMP16rr:
+  case X86::CMP8rr:
+  case X86::SUB64rr:
+  case X86::SUB32rr:
+  case X86::SUB16rr:
+  case X86::SUB8rr: {
+    Register OISrcReg;
+    Register OISrcReg2;
+    int64_t OIMask;
+    int64_t OIValue;
+    if (!analyzeCompare(OI, OISrcReg, OISrcReg2, OIMask, OIValue) ||
+        OIMask != ImmMask || OIValue != ImmValue)
+      return false;
+    if (SrcReg == OISrcReg && SrcReg2 == OISrcReg2) {
+      *IsSwapped = false;
+      return true;
+    }
+    if (SrcReg == OISrcReg2 && SrcReg2 == OISrcReg) {
+      *IsSwapped = true;
+      return true;
+    }
+    return false;
+  }
+  case X86::CMP64ri32:
+  case X86::CMP64ri8:
+  case X86::CMP32ri:
+  case X86::CMP32ri8:
+  case X86::CMP16ri:
+  case X86::CMP16ri8:
+  case X86::CMP8ri:
+  case X86::SUB64ri32:
+  case X86::SUB64ri8:
+  case X86::SUB32ri:
+  case X86::SUB32ri8:
+  case X86::SUB16ri:
+  case X86::SUB16ri8:
+  case X86::SUB8ri:
+  case X86::TEST64rr:
+  case X86::TEST32rr:
+  case X86::TEST16rr:
+  case X86::TEST8rr: {
+    if (ImmMask != 0) {
+      Register OISrcReg;
+      Register OISrcReg2;
+      int64_t OIMask;
+      int64_t OIValue;
+      if (analyzeCompare(OI, OISrcReg, OISrcReg2, OIMask, OIValue) &&
+          SrcReg == OISrcReg && ImmMask == OIMask && OIValue == ImmValue) {
+        assert(SrcReg2 == X86::NoRegister && OISrcReg2 == X86::NoRegister &&
+               "should not have 2nd register");
         return true;
+      }
+    }
+    return FlagI.isIdenticalTo(OI);
+  }
+  default:
     return false;
   }
+}
 
 /// Check whether the definition can be converted
 /// to remove a comparison against zero.
 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag,
                                     bool &ClearsOverflowFlag) {
   NoSignFlag = false;
   ClearsOverflowFlag = false;
 
bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
   bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
 
   MachineInstr *MI = nullptr;
   MachineInstr *Sub = nullptr;
   MachineInstr *Movr0Inst = nullptr;
   bool NoSignFlag = false;
   bool ClearsOverflowFlag = false;
   bool ShouldUpdateCC = false;
+  bool IsSwapped = false;
   X86::CondCode NewCC = X86::COND_INVALID;
 
   // Search backward from CmpInstr for the next instruction producing EFLAGS.
   const TargetRegisterInfo *TRI = &getRegisterInfo();
   MachineBasicBlock &CmpMBB = *CmpInstr.getParent();
   MachineBasicBlock::reverse_iterator From =
       std::next(MachineBasicBlock::reverse_iterator(CmpInstr));
+  if (SrcReg2.isPhysical())
+    return false;
   MachineInstr *SrcRegDef = MRI->getVRegDef(SrcReg);
   assert(SrcRegDef && "Must have a definition (SSA)");
   for (MachineBasicBlock *MBB = &CmpMBB;;) {
     for (MachineInstr &Inst : make_range(From, MBB->rend())) {
       // Can we use EFLAGS from instr defining  %SrcReg? Example:
       //     %eax = addl ...
       //     ...                // EFLAGS not changed
       //     testl %eax, %eax   // <-- can be removed
       if (&Inst == SrcRegDef) {
for (MachineInstr &Inst : make_range(From, MBB->rend())) {
             break;
           }
         }
 
         // Can we reuse results of equivalent cmp or sub? Example:
         //     sub x, y  or  cmp x, y
         //     ...           // EFLAGS not changed
         //     cmp x, y      // <-- can be removed
-        if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2,
-                                               CmpMask, CmpValue, Inst)) {
+        if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask, CmpValue,
+                                 Inst, &IsSwapped)) {
           Sub = &Inst;
           break;
         }
 
         // MOV32r0 is implemented with xor which clobbers condition code. It is
         // safe to move up, if the definition to EFLAGS is dead and earlier
         // instructions do not read or write EFLAGS.
         if (!Movr0Inst && Inst.getOpcode() == X86::MOV32r0 &&
for (MachineBasicBlock *MBB = &CmpMBB;;) {
     // Reached begin of basic block. Continue in predecessor if there is
     // exactly one.
     if (MBB->pred_size() != 1)
       return false;
     MBB = *MBB->pred_begin();
     From = MBB->rbegin();
   }
 
-  bool IsSwapped =
-      (SrcReg2 != 0 && Sub && Sub->getOperand(1).getReg() == SrcReg2 &&
-       Sub->getOperand(2).getReg() == SrcReg);
-
   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
   // If we are done with the basic block, we need to check whether EFLAGS is
   // live-out.
   bool IsSafe = false;
   SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
   MachineBasicBlock::iterator AfterCmpInstr =
       std::next(MachineBasicBlock::iterator(CmpInstr));
   for (MachineInstr &Instr : make_range(AfterCmpInstr, CmpMBB.end())) {
     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
     // We should check the usage if this instruction uses and updates EFLAGS.
     if (!UseEFLAGS && ModifyEFLAGS) {
       // It is safe to remove CmpInstr if EFLAGS is updated again.
       IsSafe = true;
       break;
     }
     if (!UseEFLAGS && !ModifyEFLAGS)
       continue;
 
     // EFLAGS is used by this instruction.
     X86::CondCode OldCC = X86::COND_INVALID;
-    if (IsCmpZero || IsSwapped) {
+    if (MI || IsSwapped) {
       // We decode the condition code from opcode.
       if (Instr.isBranch())
         OldCC = X86::getCondFromBranch(Instr);
       else {
         OldCC = X86::getCondFromSETCC(Instr);
         if (OldCC == X86::COND_INVALID)
           OldCC = X86::getCondFromCMov(Instr);
       }
       if (OldCC == X86::COND_INVALID) return false;
     }
     X86::CondCode ReplacementCC = X86::COND_INVALID;
-    if (IsCmpZero) {
+    if (MI) {
       switch (OldCC) {
       default: break;
       case X86::COND_A: case X86::COND_AE:
       case X86::COND_B: case X86::COND_BE:
         // CF is used, we can't perform this optimization.
         return false;
       case X86::COND_G: case X86::COND_GE:
       case X86::COND_L: case X86::COND_LE:
if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
       IsSafe = true;
       break;
     }
   }
 
   // If EFLAGS is not killed nor re-defined, we should check whether it is
   // live-out. If it is live-out, do not optimize.
-  if ((IsCmpZero || IsSwapped) && !IsSafe) {
+  if ((MI || IsSwapped) && !IsSafe) {
     for (MachineBasicBlock *Successor : CmpMBB.successors())
       if (Successor->isLiveIn(X86::EFLAGS))
         return false;
   }
 
   // The instruction to be updated is either Sub or MI.
-  Sub = IsCmpZero ? MI : Sub;
+  assert(MI == nullptr || Sub == nullptr);
+  Sub = MI != nullptr ? MI : Sub;
   MachineBasicBlock *SubBB = Sub->getParent();
   // Move Movr0Inst to the appropriate place before Sub.
   if (Movr0Inst) {
     // Only move within the same block so we don't accidentally move to a
     // block with higher execution frequency.
     if (&CmpMBB != SubBB)
       return false;
     // Look backwards until we find a def that doesn't use the current EFLAGS.

llvm/test/CodeGen/X86/2007-02-16-BranchFold.ll

 ; CHECK-NEXT:    movw $3, %ax
 ; CHECK-NEXT:    addl $20, %esp
 ; CHECK-NEXT:    popl %esi
 ; CHECK-NEXT:    popl %edi
 ; CHECK-NEXT:    retl
 ; CHECK-NEXT:  LBB0_6: ## %NodeBlock
 ; CHECK-NEXT:    js LBB0_9
 ; CHECK-NEXT:  ## %bb.7: ## %LeafBlock1
-; CHECK-NEXT:    testl %eax, %eax
 ; CHECK-NEXT:    jne LBB0_3
 ; CHECK-NEXT:  ## %bb.8: ## %bb12.i.i935.exitStub
 ; CHECK-NEXT:    movl %edi, (%esi)
 ; CHECK-NEXT:    movw $2, %ax
 ; CHECK-NEXT:    addl $20, %esp
 ; CHECK-NEXT:    popl %esi
 ; CHECK-NEXT:    popl %edi
 ; CHECK-NEXT:    retl

llvm/test/CodeGen/X86/optimize-compare.mir

bb.0:
     %1:gr32 = COPY $edi
     %2:gr32 = SUB32rr %0, %1, implicit-def $eflags
     ; an extra eflags reader shouldn't stop optimization.
     $cl = SETCCr 2, implicit $eflags
     $eax = COPY %2
     CMP32rr %0, %1, implicit-def $eflags
     $bl = SETCCr 2, implicit $eflags
 ...
+---
+name: opt_redundant_flags_cmp_cmp
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: opt_redundant_flags_cmp_cmp
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: $cl = SETCCr 2, implicit $eflags
+    ; CHECK-NEXT: $bl = SETCCr 7, implicit $eflags
+    %0:gr32 = COPY $esi
+    %1:gr32 = COPY $edi
+    CMP32rr %0, %1, implicit-def $eflags
+    $cl = SETCCr 2, implicit $eflags
+    ; 2nd CMP should be removed.
+    CMP32rr %1, %0, implicit-def $eflags
+    $bl = SETCCr 2, implicit $eflags
+...
+---
+name: opt_redundant_flags_cmp_cmp_2
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: opt_redundant_flags_cmp_cmp_2
+    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+    ; CHECK-NEXT: CMP64ri8 [[COPY]], 15, implicit-def $eflags
+    ; CHECK-NEXT: $cl = SETCCr 2, implicit $eflags
+    ; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
+    %0:gr64 = COPY $rsi
+    %1:gr64 = COPY $rdi
+    CMP64ri8 %0, 15, implicit-def $eflags
+    $cl = SETCCr 2, implicit $eflags
+    ; 2nd CMP should be removed.
+    CMP64ri8 %0, 15, implicit-def $eflags
+    $bl = SETCCr 2, implicit $eflags
+...
+---
+name: opt_redundant_flags_test_test
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: opt_redundant_flags_test_test
+    ; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+    ; CHECK-NEXT: TEST16rr [[COPY]], [[COPY]], implicit-def $eflags
+    ; CHECK-NEXT: $cl = SETCCr 2, implicit $eflags
+    ; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
+    %0:gr16 = COPY $ax
+    TEST16rr %0, %0, implicit-def $eflags
+    $cl = SETCCr 2, implicit $eflags
+    ; 2nd CMP should be removed.
+    TEST16rr %0, %0, implicit-def $eflags
+    $bl = SETCCr 2, implicit $eflags
+...
+---
+name: opt_redundant_flags_cmp_sub
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: opt_redundant_flags_cmp_sub
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: $cl = SETCCr 2, implicit $eflags
+    ; CHECK-NEXT: $bl = SETCCr 7, implicit $eflags
+    %0:gr32 = COPY $esi
+    %1:gr32 = COPY $edi
+    CMP32rr %0, %1, implicit-def $eflags
+    $cl = SETCCr 2, implicit $eflags
+    ; SUB should be removed.
+    dead %2:gr32 = SUB32rr %1, %0, implicit-def $eflags
+    $bl = SETCCr 2, implicit $eflags
+...
+---
+name: opt_redundant_flags_cmp_sub_2
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: opt_redundant_flags_cmp_sub_2
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: CMP32ri [[COPY]], -12345, implicit-def $eflags
+    ; CHECK-NEXT: $cl = SETCCr 2, implicit $eflags
+    ; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
+    %0:gr32 = COPY $esi
+    CMP32ri %0, -12345, implicit-def $eflags
+    $cl = SETCCr 2, implicit $eflags
+    ; SUB should be removed
+    dead %2:gr32 = SUB32ri %0, -12345, implicit-def $eflags
+    $bl = SETCCr 2, implicit $eflags
+...
+---
+name: opt_redundant_flags_cmp_sub_noopt
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: opt_redundant_flags_cmp_sub_noopt
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: $cl = SETCCr 2, implicit $eflags
+    ; CHECK-NEXT: [[SUB32rr:%[0-9]+]]:gr32 = SUB32rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: $rdx = COPY [[SUB32rr]]
+    ; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
+    %0:gr32 = COPY $esi
+    %1:gr32 = COPY $edi
+    CMP32rr %0, %1, implicit-def $eflags
+    $cl = SETCCr 2, implicit $eflags
+    ; cannot optimize the SUB because the result value is used.
+    %2:gr32 = SUB32rr %0, %1, implicit-def $eflags
+    $rdx = COPY %2
+    $bl = SETCCr 2, implicit $eflags
+...
+---
+name: opt_redundant_flags_cmp_test
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: opt_redundant_flags_cmp_test
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: CMP32ri8 [[COPY]], 0, implicit-def $eflags
+    ; CHECK-NEXT: $cl = SETCCr 2, implicit $eflags
+    ; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
+    %0:gr32 = COPY $esi
+    CMP32ri8 %0, 0, implicit-def $eflags
+    $cl = SETCCr 2, implicit $eflags
+    ; TEST should be removed
+    TEST32rr %0, %0, implicit-def $eflags
+    $bl = SETCCr 2, implicit $eflags
+...
+---
+name: opt_redundant_flags_test_cmp
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: opt_redundant_flags_test_cmp
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: TEST32rr [[COPY]], [[COPY]], implicit-def $eflags
+    ; CHECK-NEXT: $cl = SETCCr 2, implicit $eflags
+    ; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
+    %0:gr32 = COPY $esi
+    TEST32rr %0, %0, implicit-def $eflags
+    $cl = SETCCr 2, implicit $eflags
+    ; TEST should be removed
+    CMP32ri8 %0, 0, implicit-def $eflags
+    $bl = SETCCr 2, implicit $eflags
+...
+---
+name: opt_redundant_flags_cmp_addr
+stack:
+  - { id: 0, size: 4, alignment: 4 }
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: opt_redundant_flags_cmp_addr
+    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
+    ; CHECK-NEXT: CMP64ri32 [[COPY]], @opt_redundant_flags_cmp_addr + 4, implicit-def $eflags
+    ; CHECK-NEXT: $cl = SETCCr 7, implicit $eflags
+    ; CHECK-NEXT: $cl = SETCCr 3, implicit $eflags
+    %0:gr64 = COPY $rsi
+    CMP64ri32 %0, @opt_redundant_flags_cmp_addr + 4, implicit-def $eflags
+    $cl = SETCCr 7, implicit $eflags
+    ; CMP should be removed
+    CMP64ri32 %0, @opt_redundant_flags_cmp_addr + 4, implicit-def $eflags
+    $cl = SETCCr 3, implicit $eflags
+...
+---
+name: opt_redundant_flags_cmp_addr_noopt
+stack:
+  - { id: 0, size: 4, alignment: 4 }
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: opt_redundant_flags_cmp_addr_noopt
+    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
+    ; CHECK-NEXT: CMP64ri32 [[COPY]], @opt_redundant_flags_cmp_addr_noopt + 24, implicit-def $eflags
+    ; CHECK-NEXT: $cl = SETCCr 7, implicit $eflags
+    ; CHECK-NEXT: CMP64ri32 [[COPY]], 24, implicit-def $eflags
+    ; CHECK-NEXT: $cl = SETCCr 3, implicit $eflags
+    %0:gr64 = COPY $rsi
+    CMP64ri32 %0, @opt_redundant_flags_cmp_addr_noopt + 24, implicit-def $eflags
+    $cl = SETCCr 7, implicit $eflags
+    ; CMP should not be removed
+    CMP64ri32 %0, 24, implicit-def $eflags
+    $cl = SETCCr 3, implicit $eflags
+...

llvm/test/CodeGen/X86/postalloc-coalescing.ll

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB0_1: # %bb116
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    movb %al, 0
 ; CHECK-NEXT:    cmpl $-1, %eax
 ; CHECK-NEXT:    jne .LBB0_1
 ; CHECK-NEXT:  .LBB0_3: # %bb158
 ; CHECK-NEXT:    movb %al, 0
-; CHECK-NEXT:    cmpl $-1, %eax
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retl
 entry:
   br label %bb131
 
 bb116:    ; preds = %bb131
   %tmp125126 = trunc i32 %c.1 to i8   ; <i8> [#uses=1]
   store i8 %tmp125126, i8* null, align 1