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Differential D110381

[RISCV] Fix incorrect operand type of inst alias for InstR4
ClosedPublic

Authored by Jim on Sep 23 2021, 10:47 PM.

Details

Reviewers
craig.topper
jrtc27
Commits
rGed687c021161: [RISCV] Fix incorrect operand type of inst alias for InstR4

Diff Detail

Unit TestsFailed

TimeTest
700 msx64 debian > ORC-x86_64-linux.TestCases/Linux/x86-64::trivial-cxa-atexit.S
720 msx64 debian > ORC-x86_64-linux.TestCases/Linux/x86-64::trivial-static-initializer.S
710 msx64 debian > ORC-x86_64-linux.TestCases/Linux/x86-64::trivial-tls.S

Event Timeline

Jim created this revision.Sep 23 2021, 10:47 PM
Herald added subscribers: achieveartificialintelligence, jeroen.dobbelaere, vkmr and 26 others. · View Herald TranscriptSep 23 2021, 10:47 PM
Jim requested review of this revision.Sep 23 2021, 10:47 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 23 2021, 10:47 PM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
Jim added reviewers: craig.topper, jrtc27.Sep 23 2021, 10:48 PM
Jim mentioned this in D110308: [RISCV] Add invalid match case for uimm2, uimm3 and uimm7.Sep 23 2021, 10:49 PM
Jim added a child revision: D110308: [RISCV] Add invalid match case for uimm2, uimm3 and uimm7.Sep 23 2021, 11:05 PM
Harbormaster completed remote builds in B125477: Diff 374728.Sep 23 2021, 11:07 PM
craig.topper accepted this revision.Sep 24 2021, 3:13 PM

LGTM

This revision is now accepted and ready to land.Sep 24 2021, 3:13 PM
This revision was landed with ongoing or failed builds.Sep 24 2021, 10:01 PM
Closed by commit rGed687c021161: [RISCV] Fix incorrect operand type of inst alias for InstR4 (authored by Jim). · Explain Why
This revision was automatically updated to reflect the committed changes.
Jim added a commit: rGed687c021161: [RISCV] Fix incorrect operand type of inst alias for InstR4.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
8 lines

Diff 374728

llvm/lib/Target/RISCV/RISCVInstrInfo.td

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// into a mnemonic to use as the key for the tablegened asm matcher table. The // into a mnemonic to use as the key for the tablegened asm matcher table. The
// parser will take care of creating these fake mnemonics and will only do it // parser will take care of creating these fake mnemonics and will only do it
// for known formats. // for known formats.
let EmitPriority = 0 in { let EmitPriority = 0 in {
def : InstAlias<".insn_r $opcode, $funct3, $funct7, $rd, $rs1, $rs2", def : InstAlias<".insn_r $opcode, $funct3, $funct7, $rd, $rs1, $rs2",
(InsnR AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm7:$funct7, (InsnR AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm7:$funct7,
AnyReg:$rs1, AnyReg:$rs2)>; AnyReg:$rs1, AnyReg:$rs2)>;
// Accept 4 register form of ".insn r" as alias for ".insn r4". // Accept 4 register form of ".insn r" as alias for ".insn r4".
def : InstAlias<".insn_r $opcode, $funct3, $funct7, $rd, $rs1, $rs2, $rs3", def : InstAlias<".insn_r $opcode, $funct3, $funct2, $rd, $rs1, $rs2, $rs3",
(InsnR4 AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm7:$funct7, (InsnR4 AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm2:$funct2,
AnyReg:$rs1, AnyReg:$rs2, AnyReg:$rs3)>; AnyReg:$rs1, AnyReg:$rs2, AnyReg:$rs3)>;
def : InstAlias<".insn_r4 $opcode, $funct3, $funct7, $rd, $rs1, $rs2, $rs3", def : InstAlias<".insn_r4 $opcode, $funct3, $funct2, $rd, $rs1, $rs2, $rs3",
(InsnR4 AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm7:$funct7, (InsnR4 AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm2:$funct2,
AnyReg:$rs1, AnyReg:$rs2, AnyReg:$rs3)>; AnyReg:$rs1, AnyReg:$rs2, AnyReg:$rs3)>;
def : InstAlias<".insn_i $opcode, $funct3, $rd, $rs1, $imm12", def : InstAlias<".insn_i $opcode, $funct3, $rd, $rs1, $imm12",
(InsnI AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, AnyReg:$rs1, (InsnI AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, AnyReg:$rs1,
simm12:$imm12)>; simm12:$imm12)>;
def : InstAlias<".insn_i $opcode, $funct3, $rd, ${imm12}(${rs1})", def : InstAlias<".insn_i $opcode, $funct3, $rd, ${imm12}(${rs1})",
(InsnI_Mem AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, (InsnI_Mem AnyReg:$rd, uimm7:$opcode, uimm3:$funct3,
AnyReg:$rs1, simm12:$imm12)>; AnyReg:$rs1, simm12:$imm12)>;
def : InstAlias<".insn_b $opcode, $funct3, $rs1, $rs2, $imm12", def : InstAlias<".insn_b $opcode, $funct3, $rs1, $rs2, $imm12",
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