[AMDGPU] Limit promote alloca max size in functions

[rampitec]

Summary

Non-entry functions have 32 caller saved VGPRs available. If we
promote alloca to consume more registers we will have to spill
CSRs. There is no reason to eliminate scratch access to get
another scratch access instead.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp

182

Probably should be isEntryFunctionCC

[arsenm]

We could also be smarter and promote only if there isn’t an intervening call between uses

[rampitec]

In D110372#3019431, @arsenm wrote:

We could also be smarter and promote only if there isn’t an intervening call between uses

Why so? If the call does not take address it shall be fine. If address is taken promotion is impossible.

[rampitec]

llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp

182

The difference is the exclusion of AMDGPU_Gfx. What is that anyway?

[rampitec]

Switched to isEntryFunctionCC.

[rampitec]

In D110372#3019432, @rampitec wrote:

In D110372#3019431, @arsenm wrote:

We could also be smarter and promote only if there isn’t an intervening call between uses

Why so? If the call does not take address it shall be fine. If address is taken promotion is impossible.

I think I kind of got the idea, we have to spill around the call. Maybe we shall do the same: promote, but tell our limit is 32 registers.

[foad]

llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp

182

@sebastian-ne

[arsenm]

There is no reason to eliminate scratch access to get

another scratch access instead.

This can be beneficial since one pair CSR spills happen once if this helps avoid stack access inside a loop. It requires considering additional context to know this though

llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp

 #include "llvm/Analysis/CaptureTracking.h"
 #include "llvm/Analysis/ValueTracking.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/IRBuilder.h"
 #include "llvm/IR/IntrinsicsAMDGPU.h"
 #include "llvm/IR/IntrinsicsR600.h"
 #include "llvm/Pass.h"
 #include "llvm/Target/TargetMachine.h"
+#include "Utils/AMDGPUBaseInfo.h"
 
 #define DEBUG_TYPE "amdgpu-promote-alloca"
 
 using namespace llvm;
 
 namespace {
 
 static cl::opt<bool> DisablePromoteAllocaToVector(
bool AMDGPUPromoteAllocaImpl::run(Function &F) {
 
   const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(TM, F);
   if (!ST.isPromoteAllocaEnabled())
     return false;
 
   if (IsAMDGCN) {
     const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
     MaxVGPRs = ST.getMaxNumVGPRs(ST.getWavesPerEU(F).first);
+    // A non-entry function has only 32 caller preserved registers.
+    // Do not promote alloca which will force spilling.
+    if (!AMDGPU::isEntryFunctionCC(F.getCallingConv()))
+      MaxVGPRs = std::min(MaxVGPRs, 32u);
   } else {
     MaxVGPRs = 128;
   }
 
   bool SufficientLDS = hasSufficientLocalMem(F);
   bool Changed = false;
   BasicBlock &EntryBB = *F.begin();
 
bool promoteAllocasToVector(Function &F, TargetMachine &TM) {
   const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(TM, F);
   if (!ST.isPromoteAllocaEnabled())
     return false;
 
   unsigned MaxVGPRs;
   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
     const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
     MaxVGPRs = ST.getMaxNumVGPRs(ST.getWavesPerEU(F).first);
+    // A non-entry function has only 32 caller preserved registers.
+    // Do not promote alloca which will force spilling.
+    if (!AMDGPU::isEntryFunctionCC(F.getCallingConv()))
+      MaxVGPRs = std::min(MaxVGPRs, 32u);
   } else {
     MaxVGPRs = 128;
   }
 
   bool Changed = false;
   BasicBlock &EntryBB = *F.begin();
 
   SmallVector<AllocaInst *, 16> Allocas;

llvm/test/CodeGen/AMDGPU/vector-alloca-limits.ll

entry:
   %x = getelementptr [9 x i256], [9 x i256] addrspace(5)* %tmp, i32 0, i32 0
   store i256 0, i256 addrspace(5)* %x
   %tmp1 = getelementptr [9 x i256], [9 x i256] addrspace(5)* %tmp, i32 0, i32 %index
   %tmp2 = load i256, i256 addrspace(5)* %tmp1
   store i256 %tmp2, i256 addrspace(1)* %out
   ret void
 }
 
+; OPT-LABEL: @alloca_9xi64_max256(
+; OPT-NOT: alloca
+; OPT: <9 x i64>
+; LIMIT32: alloca
+; LIMIT32-NOT: <9 x i64>
+define amdgpu_kernel void @alloca_9xi64_max256(i64 addrspace(1)* %out, i32 %index) #2 {
+entry:
+  %tmp = alloca [9 x i64], addrspace(5)
+  %x = getelementptr [9 x i64], [9 x i64] addrspace(5)* %tmp, i32 0, i32 0
+  store i64 0, i64 addrspace(5)* %x
+  %tmp1 = getelementptr [9 x i64], [9 x i64] addrspace(5)* %tmp, i32 0, i32 %index
+  %tmp2 = load i64, i64 addrspace(5)* %tmp1
+  store i64 %tmp2, i64 addrspace(1)* %out
+  ret void
+}
+
+; OPT-LABEL: @func_alloca_9xi64_max256(
+; OPT: alloca
+; OPT-NOT: <9 x i64>
+; LIMIT32: alloca
+; LIMIT32-NOT: <9 x i64>
+define void @func_alloca_9xi64_max256(i64 addrspace(1)* %out, i32 %index) #2 {
+entry:
+  %tmp = alloca [9 x i64], addrspace(5)
+  %x = getelementptr [9 x i64], [9 x i64] addrspace(5)* %tmp, i32 0, i32 0
+  store i64 0, i64 addrspace(5)* %x
+  %tmp1 = getelementptr [9 x i64], [9 x i64] addrspace(5)* %tmp, i32 0, i32 %index
+  %tmp2 = load i64, i64 addrspace(5)* %tmp1
+  store i64 %tmp2, i64 addrspace(1)* %out
+  ret void
+}
+
 attributes #0 = { "amdgpu-flat-work-group-size"="1,1024" }
 attributes #1 = { "amdgpu-flat-work-group-size"="1,512" }
 attributes #2 = { "amdgpu-flat-work-group-size"="1,256" }