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Differential D110230

[InstCombine] Update InstCombine to use poison instead of undef for shufflevector's placeholder (3/3)
ClosedPublic

Authored by hyeongyukim on Sep 22 2021, 4:05 AM.

Details

Reviewers
spatel
efriedma
jdoerfert
nikic
lebedev.ri
regehr
Commits
rG98e96663f6a7: [InstCombine] Update InstCombine to use poison instead of undef for…
Summary

This patch is for fixing potential shufflevector-related bugs like D93818.
As D93818, this patch change shufflevector's default placeholder to poison.
To reduce risk, it was divided into several patches, and this patch is for InstCombineVectorOps.

Diff Detail

Unit TestsFailed

TimeTest
400 msx64 debian > Clang.CodeGen::aarch64-bf16-ldst-intrinsics.c
550 msx64 debian > Clang.CodeGen::aarch64-neon-dot-product.c
370 msx64 debian > Clang.CodeGen::arm-neon-dot-product.c
670 msx64 debian > ORC-x86_64-linux.TestCases/Linux/x86-64::trivial-cxa-atexit.S
670 msx64 debian > ORC-x86_64-linux.TestCases/Linux/x86-64::trivial-static-initializer.S
View Full Test Results (6 Failed)

Event Timeline

hyeongyukim created this revision.Sep 22 2021, 4:05 AM
Herald added a subscriber: hiraditya. · View Herald TranscriptSep 22 2021, 4:05 AM
hyeongyukim requested review of this revision.Sep 22 2021, 4:05 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 22 2021, 4:05 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
hyeongyukim retitled this revision from [InstCombine] Update InstCombine to use poison instead of undef for shufflevector's placeholder (2/3) to [InstCombine] Update InstCombine to use poison instead of undef for shufflevector's placeholder (3/3).Sep 22 2021, 4:07 AM
Harbormaster completed remote builds in B125084: Diff 374176.Sep 22 2021, 4:26 AM
hyeongyukim updated this revision to Diff 374192.Sep 22 2021, 5:33 AM

reformat code

hyeongyukim added reviewers: spatel, efriedma, jdoerfert, nikic, lebedev.ri, regehr.Sep 22 2021, 5:36 AM
Harbormaster completed remote builds in B125092: Diff 374192.Sep 22 2021, 5:46 AM
spatel accepted this revision.Sep 22 2021, 5:54 AM

LGTM

This revision is now accepted and ready to land.Sep 22 2021, 5:54 AM
This revision was landed with ongoing or failed builds.Sep 22 2021, 8:48 AM
Closed by commit rG98e96663f6a7: [InstCombine] Update InstCombine to use poison instead of undef for… (authored by hyeongyukim). · Explain Why
This revision was automatically updated to reflect the committed changes.
hyeongyukim added a commit: rG98e96663f6a7: [InstCombine] Update InstCombine to use poison instead of undef for….
Herald added a project: Restricted Project. · View Herald TranscriptSep 22 2021, 8:48 AM
Herald added a subscriber: cfe-commits. · View Herald Transcript
hyeongyukim mentioned this in D110311: [IR] Change the default value of InstertElement to poison (1/4).Sep 23 2021, 12:40 AM
aqjune mentioned this in D93817: [InstCombine] Update transformations to use poison for insertelement/shufflevector's placeholder value (2/2).Sep 25 2021, 8:12 PM
aqjune mentioned this in D94380: [InstCombine] Update transformations to use poison for insertelement/shufflevector's placeholder value (1/2).

Revision Contents

Diff 374176

llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp

Show First 20 Lines • Show All 653 Lines • ▼ Show 20 Linesstatic void replaceExtractElements(InsertElementInst *InsElt,
// TODO: This restriction matches the check in visitInsertElementInst() and // TODO: This restriction matches the check in visitInsertElementInst() and
// prevents an infinite loop caused by not turning the extract/insert pair // prevents an infinite loop caused by not turning the extract/insert pair
// into a shuffle. We really should not need either check, but we're lacking // into a shuffle. We really should not need either check, but we're lacking
// folds for shufflevectors because we're afraid to generate shuffle masks // folds for shufflevectors because we're afraid to generate shuffle masks
// that the backend can't handle. // that the backend can't handle.
if (InsElt->hasOneUse() && isa<InsertElementInst>(InsElt->user_back())) if (InsElt->hasOneUse() && isa<InsertElementInst>(InsElt->user_back()))
return; return;
auto *WideVec = auto *WideVec =
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  auto *WideVec =
-      new ShuffleVectorInst(ExtVecOp, ExtendMask);
+  auto *WideVec = new ShuffleVectorInst(ExtVecOp, ExtendMask);
Lint: Pre-merge checks: clang-format: please reformat the code ``` - auto *WideVec = - new ShuffleVectorInst…
new ShuffleVectorInst(ExtVecOp, PoisonValue::get(ExtVecType), ExtendMask); new ShuffleVectorInst(ExtVecOp, ExtendMask);
// Insert the new shuffle after the vector operand of the extract is defined // Insert the new shuffle after the vector operand of the extract is defined
// (as long as it's not a PHI) or at the start of the basic block of the // (as long as it's not a PHI) or at the start of the basic block of the
// extract, so any subsequent extracts in the same basic block can use it. // extract, so any subsequent extracts in the same basic block can use it.
// TODO: Insert before the earliest ExtractElementInst that is replaced. // TODO: Insert before the earliest ExtractElementInst that is replaced.
if (ExtVecOpInst && !isa<PHINode>(ExtVecOpInst)) if (ExtVecOpInst && !isa<PHINode>(ExtVecOpInst))
WideVec->insertAfter(ExtVecOpInst); WideVec->insertAfter(ExtVecOpInst);
else else
▲ Show 20 Lines • Show All 510 Lines • ▼ Show 20 Lines if (!cast<ConstantInt>(FirstIE->getOperand(2))->isZero())
FirstIE = InsertElementInst::Create(PoisonVec, SplatVal, Zero, "", &InsElt); FirstIE = InsertElementInst::Create(PoisonVec, SplatVal, Zero, "", &InsElt);
// Splat from element 0, but replace absent elements with undef in the mask. // Splat from element 0, but replace absent elements with undef in the mask.
SmallVector<int, 16> Mask(NumElements, 0); SmallVector<int, 16> Mask(NumElements, 0);
for (unsigned i = 0; i != NumElements; ++i) for (unsigned i = 0; i != NumElements; ++i)
if (!ElementPresent[i]) if (!ElementPresent[i])
Mask[i] = -1; Mask[i] = -1;
return new ShuffleVectorInst(FirstIE, PoisonVec, Mask); return new ShuffleVectorInst(FirstIE, Mask);
} }
/// Try to fold an insert element into an existing splat shuffle by changing /// Try to fold an insert element into an existing splat shuffle by changing
/// the shuffle's mask to include the index of this insert element. /// the shuffle's mask to include the index of this insert element.
static Instruction *foldInsEltIntoSplat(InsertElementInst &InsElt) { static Instruction *foldInsEltIntoSplat(InsertElementInst &InsElt) {
// Check if the vector operand of this insert is a canonical splat shuffle. // Check if the vector operand of this insert is a canonical splat shuffle.
auto *Shuf = dyn_cast<ShuffleVectorInst>(InsElt.getOperand(0)); auto *Shuf = dyn_cast<ShuffleVectorInst>(InsElt.getOperand(0));
if (!Shuf || !Shuf->isZeroEltSplat()) if (!Shuf || !Shuf->isZeroEltSplat())
Show All 20 Linesstatic Instruction *foldInsEltIntoSplat(InsertElementInst &InsElt) {
// inselt (shuf (inselt undef, X, 0), undef, <0,undef,0,undef>), X, 1 // inselt (shuf (inselt undef, X, 0), undef, <0,undef,0,undef>), X, 1
// --> shuf (inselt undef, X, 0), undef, <0,0,0,undef> // --> shuf (inselt undef, X, 0), undef, <0,0,0,undef>
unsigned NumMaskElts = unsigned NumMaskElts =
cast<FixedVectorType>(Shuf->getType())->getNumElements(); cast<FixedVectorType>(Shuf->getType())->getNumElements();
SmallVector<int, 16> NewMask(NumMaskElts); SmallVector<int, 16> NewMask(NumMaskElts);
for (unsigned i = 0; i != NumMaskElts; ++i) for (unsigned i = 0; i != NumMaskElts; ++i)
NewMask[i] = i == IdxC ? 0 : Shuf->getMaskValue(i); NewMask[i] = i == IdxC ? 0 : Shuf->getMaskValue(i);
return new ShuffleVectorInst(Op0, UndefValue::get(Op0->getType()), NewMask); return new ShuffleVectorInst(Op0, NewMask);
} }
/// Try to fold an extract+insert element into an existing identity shuffle by /// Try to fold an extract+insert element into an existing identity shuffle by
/// changing the shuffle's mask to include the index of this insert element. /// changing the shuffle's mask to include the index of this insert element.
static Instruction *foldInsEltIntoIdentityShuffle(InsertElementInst &InsElt) { static Instruction *foldInsEltIntoIdentityShuffle(InsertElementInst &InsElt) {
// Check if the vector operand of this insert is an identity shuffle. // Check if the vector operand of this insert is an identity shuffle.
auto *Shuf = dyn_cast<ShuffleVectorInst>(InsElt.getOperand(0)); auto *Shuf = dyn_cast<ShuffleVectorInst>(InsElt.getOperand(0));
if (!Shuf || !match(Shuf->getOperand(1), m_Undef()) || if (!Shuf || !match(Shuf->getOperand(1), m_Undef()) ||
▲ Show 20 Lines • Show All 742 Lines • ▼ Show 20 Linesstatic Instruction *canonicalizeInsertSplat(ShuffleVectorInst &Shuf,
// --> shuf (inselt undef, X, 0), undef, <0,0,undef> // --> shuf (inselt undef, X, 0), undef, <0,0,undef>
unsigned NumMaskElts = unsigned NumMaskElts =
cast<FixedVectorType>(Shuf.getType())->getNumElements(); cast<FixedVectorType>(Shuf.getType())->getNumElements();
SmallVector<int, 16> NewMask(NumMaskElts, 0); SmallVector<int, 16> NewMask(NumMaskElts, 0);
for (unsigned i = 0; i != NumMaskElts; ++i) for (unsigned i = 0; i != NumMaskElts; ++i)
if (Mask[i] == UndefMaskElem) if (Mask[i] == UndefMaskElem)
NewMask[i] = Mask[i]; NewMask[i] = Mask[i];
return new ShuffleVectorInst(NewIns, UndefVec, NewMask); return new ShuffleVectorInst(NewIns, NewMask);
} }
/// Try to fold shuffles that are the equivalent of a vector select. /// Try to fold shuffles that are the equivalent of a vector select.
static Instruction *foldSelectShuffle(ShuffleVectorInst &Shuf, static Instruction *foldSelectShuffle(ShuffleVectorInst &Shuf,
InstCombiner::BuilderTy &Builder, InstCombiner::BuilderTy &Builder,
const DataLayout &DL) { const DataLayout &DL) {
if (!Shuf.isSelect()) if (!Shuf.isSelect())
return nullptr; return nullptr;
▲ Show 20 Lines • Show All 472 Lines • ▼ Show 20 Lines if (LHS == RHS) {
SmallVector<int, 16> Elts; SmallVector<int, 16> Elts;
for (unsigned i = 0; i != VWidth; ++i) { for (unsigned i = 0; i != VWidth; ++i) {
// Propagate undef elements or force mask to LHS. // Propagate undef elements or force mask to LHS.
if (Mask[i] < 0) if (Mask[i] < 0)
Elts.push_back(UndefMaskElem); Elts.push_back(UndefMaskElem);
else else
Elts.push_back(Mask[i] % LHSWidth); Elts.push_back(Mask[i] % LHSWidth);
} }
return new ShuffleVectorInst(LHS, UndefValue::get(RHS->getType()), Elts); return new ShuffleVectorInst(LHS, Elts);
} }
// shuffle undef, x, mask --> shuffle x, undef, mask' // shuffle undef, x, mask --> shuffle x, undef, mask'
if (match(LHS, m_Undef())) { if (match(LHS, m_Undef())) {
SVI.commute(); SVI.commute();
return &SVI; return &SVI;
} }
▲ Show 20 Lines • Show All 299 Lines • Show Last 20 Lines

llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll

Show First 20 Lines • Show All 1,935 Lines • ▼ Show 20 Lines
; ;
%1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>) %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>)
ret <4 x i64> %1 ret <4 x i64> %1
} }
define <4 x i64> @identity_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) { define <4 x i64> @identity_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: @identity_test_permvar_di_256_mask( ; CHECK-LABEL: @identity_test_permvar_di_256_mask(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1> ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[A0:%.*]], <4 x i64> [[PASSTHRU:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[A0:%.*]], <4 x i64> [[PASSTHRU:%.*]]
; CHECK-NEXT: ret <4 x i64> [[TMP2]] ; CHECK-NEXT: ret <4 x i64> [[TMP2]]
; ;
%1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>) %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>)
%2 = bitcast i8 %mask to <8 x i1> %2 = bitcast i8 %mask to <8 x i1>
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru
ret <4 x i64> %3 ret <4 x i64> %3
} }
define <4 x i64> @zero_test_permvar_di_256(<4 x i64> %a0) { define <4 x i64> @zero_test_permvar_di_256(<4 x i64> %a0) {
; CHECK-LABEL: @zero_test_permvar_di_256( ; CHECK-LABEL: @zero_test_permvar_di_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: ret <4 x i64> [[TMP1]] ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
; ;
%1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> zeroinitializer) %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> zeroinitializer)
ret <4 x i64> %1 ret <4 x i64> %1
} }
define <4 x i64> @zero_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) { define <4 x i64> @zero_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: @zero_test_permvar_di_256_mask( ; CHECK-LABEL: @zero_test_permvar_di_256_mask(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[PASSTHRU:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[PASSTHRU:%.*]]
; CHECK-NEXT: ret <4 x i64> [[TMP3]] ; CHECK-NEXT: ret <4 x i64> [[TMP3]]
; ;
%1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> zeroinitializer) %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> zeroinitializer)
%2 = bitcast i8 %mask to <8 x i1> %2 = bitcast i8 %mask to <8 x i1>
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru
ret <4 x i64> %3 ret <4 x i64> %3
} }
define <4 x i64> @shuffle_test_permvar_di_256(<4 x i64> %a0) { define <4 x i64> @shuffle_test_permvar_di_256(<4 x i64> %a0) {
; CHECK-LABEL: @shuffle_test_permvar_di_256( ; CHECK-LABEL: @shuffle_test_permvar_di_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: ret <4 x i64> [[TMP1]] ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
; ;
%1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>) %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>)
ret <4 x i64> %1 ret <4 x i64> %1
} }
define <4 x i64> @shuffle_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) { define <4 x i64> @shuffle_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: @shuffle_test_permvar_di_256_mask( ; CHECK-LABEL: @shuffle_test_permvar_di_256_mask(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[PASSTHRU:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[PASSTHRU:%.*]]
; CHECK-NEXT: ret <4 x i64> [[TMP3]] ; CHECK-NEXT: ret <4 x i64> [[TMP3]]
; ;
%1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>) %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>)
%2 = bitcast i8 %mask to <8 x i1> %2 = bitcast i8 %mask to <8 x i1>
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru
ret <4 x i64> %3 ret <4 x i64> %3
} }
define <4 x i64> @undef_test_permvar_di_256(<4 x i64> %a0) { define <4 x i64> @undef_test_permvar_di_256(<4 x i64> %a0) {
; CHECK-LABEL: @undef_test_permvar_di_256( ; CHECK-LABEL: @undef_test_permvar_di_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 undef, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 undef, i32 2, i32 1, i32 0>
; CHECK-NEXT: ret <4 x i64> [[TMP1]] ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
; ;
%1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>) %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>)
ret <4 x i64> %1 ret <4 x i64> %1
} }
define <4 x i64> @undef_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) { define <4 x i64> @undef_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: @undef_test_permvar_di_256_mask( ; CHECK-LABEL: @undef_test_permvar_di_256_mask(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 undef, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 undef, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[PASSTHRU:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[PASSTHRU:%.*]]
; CHECK-NEXT: ret <4 x i64> [[TMP3]] ; CHECK-NEXT: ret <4 x i64> [[TMP3]]
; ;
%1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>) %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>)
%2 = bitcast i8 %mask to <8 x i1> %2 = bitcast i8 %mask to <8 x i1>
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru
ret <4 x i64> %3 ret <4 x i64> %3
} }
declare <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double>, <4 x i64>) declare <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double>, <4 x i64>)
define <4 x double> @identity_test_permvar_df_256(<4 x double> %a0) { define <4 x double> @identity_test_permvar_df_256(<4 x double> %a0) {
; CHECK-LABEL: @identity_test_permvar_df_256( ; CHECK-LABEL: @identity_test_permvar_df_256(
; CHECK-NEXT: ret <4 x double> [[A0:%.*]] ; CHECK-NEXT: ret <4 x double> [[A0:%.*]]
; ;
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>) %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>)
ret <4 x double> %1 ret <4 x double> %1
} }
define <4 x double> @identity_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) { define <4 x double> @identity_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) {
; CHECK-LABEL: @identity_test_permvar_df_256_mask( ; CHECK-LABEL: @identity_test_permvar_df_256_mask(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1> ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[A0:%.*]], <4 x double> [[PASSTHRU:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[A0:%.*]], <4 x double> [[PASSTHRU:%.*]]
; CHECK-NEXT: ret <4 x double> [[TMP2]] ; CHECK-NEXT: ret <4 x double> [[TMP2]]
; ;
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>) %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>)
%2 = bitcast i8 %mask to <8 x i1> %2 = bitcast i8 %mask to <8 x i1>
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru %3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru
ret <4 x double> %3 ret <4 x double> %3
} }
define <4 x double> @zero_test_permvar_df_256(<4 x double> %a0) { define <4 x double> @zero_test_permvar_df_256(<4 x double> %a0) {
; CHECK-LABEL: @zero_test_permvar_df_256( ; CHECK-LABEL: @zero_test_permvar_df_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: ret <4 x double> [[TMP1]] ; CHECK-NEXT: ret <4 x double> [[TMP1]]
; ;
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> zeroinitializer) %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> zeroinitializer)
ret <4 x double> %1 ret <4 x double> %1
} }
define <4 x double> @zero_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) { define <4 x double> @zero_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) {
; CHECK-LABEL: @zero_test_permvar_df_256_mask( ; CHECK-LABEL: @zero_test_permvar_df_256_mask(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[PASSTHRU:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[PASSTHRU:%.*]]
; CHECK-NEXT: ret <4 x double> [[TMP3]] ; CHECK-NEXT: ret <4 x double> [[TMP3]]
; ;
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> zeroinitializer) %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> zeroinitializer)
%2 = bitcast i8 %mask to <8 x i1> %2 = bitcast i8 %mask to <8 x i1>
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru %3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru
ret <4 x double> %3 ret <4 x double> %3
} }
define <4 x double> @shuffle_test_permvar_df_256(<4 x double> %a0) { define <4 x double> @shuffle_test_permvar_df_256(<4 x double> %a0) {
; CHECK-LABEL: @shuffle_test_permvar_df_256( ; CHECK-LABEL: @shuffle_test_permvar_df_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: ret <4 x double> [[TMP1]] ; CHECK-NEXT: ret <4 x double> [[TMP1]]
; ;
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>) %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>)
ret <4 x double> %1 ret <4 x double> %1
} }
define <4 x double> @shuffle_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) { define <4 x double> @shuffle_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) {
; CHECK-LABEL: @shuffle_test_permvar_df_256_mask( ; CHECK-LABEL: @shuffle_test_permvar_df_256_mask(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[PASSTHRU:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[PASSTHRU:%.*]]
; CHECK-NEXT: ret <4 x double> [[TMP3]] ; CHECK-NEXT: ret <4 x double> [[TMP3]]
; ;
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>) %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>)
%2 = bitcast i8 %mask to <8 x i1> %2 = bitcast i8 %mask to <8 x i1>
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru %3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru
ret <4 x double> %3 ret <4 x double> %3
} }
define <4 x double> @undef_test_permvar_df_256(<4 x double> %a0) { define <4 x double> @undef_test_permvar_df_256(<4 x double> %a0) {
; CHECK-LABEL: @undef_test_permvar_df_256( ; CHECK-LABEL: @undef_test_permvar_df_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 undef, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 undef, i32 2, i32 1, i32 0>
; CHECK-NEXT: ret <4 x double> [[TMP1]] ; CHECK-NEXT: ret <4 x double> [[TMP1]]
; ;
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>) %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>)
ret <4 x double> %1 ret <4 x double> %1
} }
define <4 x double> @undef_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) { define <4 x double> @undef_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) {
; CHECK-LABEL: @undef_test_permvar_df_256_mask( ; CHECK-LABEL: @undef_test_permvar_df_256_mask(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 undef, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 undef, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[PASSTHRU:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[PASSTHRU:%.*]]
; CHECK-NEXT: ret <4 x double> [[TMP3]] ; CHECK-NEXT: ret <4 x double> [[TMP3]]
; ;
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>) %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>)
%2 = bitcast i8 %mask to <8 x i1> %2 = bitcast i8 %mask to <8 x i1>
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru %3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru
ret <4 x double> %3 ret <4 x double> %3
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llvm/test/Transforms/InstCombine/X86/x86-avx512.ll

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; ;
%1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>) %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>)
ret <4 x i64> %1 ret <4 x i64> %1
} }
define <4 x i64> @identity_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) { define <4 x i64> @identity_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: @identity_test_permvar_di_256_mask( ; CHECK-LABEL: @identity_test_permvar_di_256_mask(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1> ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[A0:%.*]], <4 x i64> [[PASSTHRU:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[A0:%.*]], <4 x i64> [[PASSTHRU:%.*]]
; CHECK-NEXT: ret <4 x i64> [[TMP2]] ; CHECK-NEXT: ret <4 x i64> [[TMP2]]
; ;
%1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>) %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>)
%2 = bitcast i8 %mask to <8 x i1> %2 = bitcast i8 %mask to <8 x i1>
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru
ret <4 x i64> %3 ret <4 x i64> %3
} }
define <4 x i64> @zero_test_permvar_di_256(<4 x i64> %a0) { define <4 x i64> @zero_test_permvar_di_256(<4 x i64> %a0) {
; CHECK-LABEL: @zero_test_permvar_di_256( ; CHECK-LABEL: @zero_test_permvar_di_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: ret <4 x i64> [[TMP1]] ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
; ;
%1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> zeroinitializer) %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> zeroinitializer)
ret <4 x i64> %1 ret <4 x i64> %1
} }
define <4 x i64> @zero_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) { define <4 x i64> @zero_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: @zero_test_permvar_di_256_mask( ; CHECK-LABEL: @zero_test_permvar_di_256_mask(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[PASSTHRU:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[PASSTHRU:%.*]]
; CHECK-NEXT: ret <4 x i64> [[TMP3]] ; CHECK-NEXT: ret <4 x i64> [[TMP3]]
; ;
%1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> zeroinitializer) %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> zeroinitializer)
%2 = bitcast i8 %mask to <8 x i1> %2 = bitcast i8 %mask to <8 x i1>
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru
ret <4 x i64> %3 ret <4 x i64> %3
} }
define <4 x i64> @shuffle_test_permvar_di_256(<4 x i64> %a0) { define <4 x i64> @shuffle_test_permvar_di_256(<4 x i64> %a0) {
; CHECK-LABEL: @shuffle_test_permvar_di_256( ; CHECK-LABEL: @shuffle_test_permvar_di_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: ret <4 x i64> [[TMP1]] ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
; ;
%1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>) %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>)
ret <4 x i64> %1 ret <4 x i64> %1
} }
define <4 x i64> @shuffle_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) { define <4 x i64> @shuffle_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: @shuffle_test_permvar_di_256_mask( ; CHECK-LABEL: @shuffle_test_permvar_di_256_mask(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[PASSTHRU:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[PASSTHRU:%.*]]
; CHECK-NEXT: ret <4 x i64> [[TMP3]] ; CHECK-NEXT: ret <4 x i64> [[TMP3]]
; ;
%1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>) %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>)
%2 = bitcast i8 %mask to <8 x i1> %2 = bitcast i8 %mask to <8 x i1>
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru
ret <4 x i64> %3 ret <4 x i64> %3
} }
define <4 x i64> @undef_test_permvar_di_256(<4 x i64> %a0) { define <4 x i64> @undef_test_permvar_di_256(<4 x i64> %a0) {
; CHECK-LABEL: @undef_test_permvar_di_256( ; CHECK-LABEL: @undef_test_permvar_di_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 undef, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 undef, i32 2, i32 1, i32 0>
; CHECK-NEXT: ret <4 x i64> [[TMP1]] ; CHECK-NEXT: ret <4 x i64> [[TMP1]]
; ;
%1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>) %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>)
ret <4 x i64> %1 ret <4 x i64> %1
} }
define <4 x i64> @undef_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) { define <4 x i64> @undef_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: @undef_test_permvar_di_256_mask( ; CHECK-LABEL: @undef_test_permvar_di_256_mask(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 undef, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> poison, <4 x i32> <i32 undef, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[PASSTHRU:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[PASSTHRU:%.*]]
; CHECK-NEXT: ret <4 x i64> [[TMP3]] ; CHECK-NEXT: ret <4 x i64> [[TMP3]]
; ;
%1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>) %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>)
%2 = bitcast i8 %mask to <8 x i1> %2 = bitcast i8 %mask to <8 x i1>
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru
ret <4 x i64> %3 ret <4 x i64> %3
} }
declare <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double>, <4 x i64>) declare <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double>, <4 x i64>)
define <4 x double> @identity_test_permvar_df_256(<4 x double> %a0) { define <4 x double> @identity_test_permvar_df_256(<4 x double> %a0) {
; CHECK-LABEL: @identity_test_permvar_df_256( ; CHECK-LABEL: @identity_test_permvar_df_256(
; CHECK-NEXT: ret <4 x double> [[A0:%.*]] ; CHECK-NEXT: ret <4 x double> [[A0:%.*]]
; ;
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>) %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>)
ret <4 x double> %1 ret <4 x double> %1
} }
define <4 x double> @identity_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) { define <4 x double> @identity_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) {
; CHECK-LABEL: @identity_test_permvar_df_256_mask( ; CHECK-LABEL: @identity_test_permvar_df_256_mask(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1> ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[A0:%.*]], <4 x double> [[PASSTHRU:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[A0:%.*]], <4 x double> [[PASSTHRU:%.*]]
; CHECK-NEXT: ret <4 x double> [[TMP2]] ; CHECK-NEXT: ret <4 x double> [[TMP2]]
; ;
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>) %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>)
%2 = bitcast i8 %mask to <8 x i1> %2 = bitcast i8 %mask to <8 x i1>
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru %3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru
ret <4 x double> %3 ret <4 x double> %3
} }
define <4 x double> @zero_test_permvar_df_256(<4 x double> %a0) { define <4 x double> @zero_test_permvar_df_256(<4 x double> %a0) {
; CHECK-LABEL: @zero_test_permvar_df_256( ; CHECK-LABEL: @zero_test_permvar_df_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: ret <4 x double> [[TMP1]] ; CHECK-NEXT: ret <4 x double> [[TMP1]]
; ;
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> zeroinitializer) %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> zeroinitializer)
ret <4 x double> %1 ret <4 x double> %1
} }
define <4 x double> @zero_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) { define <4 x double> @zero_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) {
; CHECK-LABEL: @zero_test_permvar_df_256_mask( ; CHECK-LABEL: @zero_test_permvar_df_256_mask(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[PASSTHRU:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[PASSTHRU:%.*]]
; CHECK-NEXT: ret <4 x double> [[TMP3]] ; CHECK-NEXT: ret <4 x double> [[TMP3]]
; ;
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> zeroinitializer) %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> zeroinitializer)
%2 = bitcast i8 %mask to <8 x i1> %2 = bitcast i8 %mask to <8 x i1>
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru %3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru
ret <4 x double> %3 ret <4 x double> %3
} }
define <4 x double> @shuffle_test_permvar_df_256(<4 x double> %a0) { define <4 x double> @shuffle_test_permvar_df_256(<4 x double> %a0) {
; CHECK-LABEL: @shuffle_test_permvar_df_256( ; CHECK-LABEL: @shuffle_test_permvar_df_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: ret <4 x double> [[TMP1]] ; CHECK-NEXT: ret <4 x double> [[TMP1]]
; ;
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>) %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>)
ret <4 x double> %1 ret <4 x double> %1
} }
define <4 x double> @shuffle_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) { define <4 x double> @shuffle_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) {
; CHECK-LABEL: @shuffle_test_permvar_df_256_mask( ; CHECK-LABEL: @shuffle_test_permvar_df_256_mask(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[PASSTHRU:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[PASSTHRU:%.*]]
; CHECK-NEXT: ret <4 x double> [[TMP3]] ; CHECK-NEXT: ret <4 x double> [[TMP3]]
; ;
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>) %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>)
%2 = bitcast i8 %mask to <8 x i1> %2 = bitcast i8 %mask to <8 x i1>
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru %3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru
ret <4 x double> %3 ret <4 x double> %3
} }
define <4 x double> @undef_test_permvar_df_256(<4 x double> %a0) { define <4 x double> @undef_test_permvar_df_256(<4 x double> %a0) {
; CHECK-LABEL: @undef_test_permvar_df_256( ; CHECK-LABEL: @undef_test_permvar_df_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 undef, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 undef, i32 2, i32 1, i32 0>
; CHECK-NEXT: ret <4 x double> [[TMP1]] ; CHECK-NEXT: ret <4 x double> [[TMP1]]
; ;
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>) %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>)
ret <4 x double> %1 ret <4 x double> %1
} }
define <4 x double> @undef_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) { define <4 x double> @undef_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) {
; CHECK-LABEL: @undef_test_permvar_df_256_mask( ; CHECK-LABEL: @undef_test_permvar_df_256_mask(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 undef, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 undef, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[PASSTHRU:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[PASSTHRU:%.*]]
; CHECK-NEXT: ret <4 x double> [[TMP3]] ; CHECK-NEXT: ret <4 x double> [[TMP3]]
; ;
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>) %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>)
%2 = bitcast i8 %mask to <8 x i1> %2 = bitcast i8 %mask to <8 x i1>
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru %3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru
ret <4 x double> %3 ret <4 x double> %3
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llvm/test/Transforms/InstCombine/X86/x86-f16c-inseltpoison.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s ; RUN: opt < %s -instcombine -S | FileCheck %s
declare <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16>) declare <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16>)
declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>) declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>)
; ;
; Vector Demanded Elts ; Vector Demanded Elts
; ;
; Only bottom 4 elements required. ; Only bottom 4 elements required.
define <4 x float> @demand_vcvtph2ps_128(<8 x i16> %A) { define <4 x float> @demand_vcvtph2ps_128(<8 x i16> %A) {
; CHECK-LABEL: @demand_vcvtph2ps_128( ; CHECK-LABEL: @demand_vcvtph2ps_128(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[A:%.*]], <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[A:%.*]], <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <4 x half> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <4 x half>
; CHECK-NEXT: [[CVTPH2PS:%.*]] = fpext <4 x half> [[TMP2]] to <4 x float> ; CHECK-NEXT: [[CVTPH2PS:%.*]] = fpext <4 x half> [[TMP2]] to <4 x float>
; CHECK-NEXT: ret <4 x float> [[CVTPH2PS]] ; CHECK-NEXT: ret <4 x float> [[CVTPH2PS]]
; ;
%1 = shufflevector <8 x i16> %A, <8 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> %1 = shufflevector <8 x i16> %A, <8 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
%2 = tail call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %1) %2 = tail call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %1)
ret <4 x float> %2 ret <4 x float> %2
} }
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/Transforms/InstCombine/X86/x86-f16c.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s ; RUN: opt < %s -instcombine -S | FileCheck %s
declare <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16>) declare <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16>)
declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>) declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>)
; ;
; Vector Demanded Elts ; Vector Demanded Elts
; ;
; Only bottom 4 elements required. ; Only bottom 4 elements required.
define <4 x float> @demand_vcvtph2ps_128(<8 x i16> %A) { define <4 x float> @demand_vcvtph2ps_128(<8 x i16> %A) {
; CHECK-LABEL: @demand_vcvtph2ps_128( ; CHECK-LABEL: @demand_vcvtph2ps_128(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[A:%.*]], <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[A:%.*]], <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <4 x half> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <4 x half>
; CHECK-NEXT: [[CVTPH2PS:%.*]] = fpext <4 x half> [[TMP2]] to <4 x float> ; CHECK-NEXT: [[CVTPH2PS:%.*]] = fpext <4 x half> [[TMP2]] to <4 x float>
; CHECK-NEXT: ret <4 x float> [[CVTPH2PS]] ; CHECK-NEXT: ret <4 x float> [[CVTPH2PS]]
; ;
%1 = shufflevector <8 x i16> %A, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> %1 = shufflevector <8 x i16> %A, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
%2 = tail call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %1) %2 = tail call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %1)
ret <4 x float> %2 ret <4 x float> %2
} }
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llvm/test/Transforms/InstCombine/broadcast-inseltpoison.ll

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
; Multiple undef elements are ok. ; Multiple undef elements are ok.
; TODO: Multiple uses triggers the transform at %t4, but we should sink/scalarize/CSE the splats? ; TODO: Multiple uses triggers the transform at %t4, but we should sink/scalarize/CSE the splats?
define <4 x float> @splat_undef3(float %arg) { define <4 x float> @splat_undef3(float %arg) {
; CHECK-LABEL: @splat_undef3( ; CHECK-LABEL: @splat_undef3(
; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> poison, float [[ARG:%.*]], i32 0 ; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> poison, float [[ARG:%.*]], i32 0
; CHECK-NEXT: [[T4:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> <i32 0, i32 0, i32 undef, i32 undef> ; CHECK-NEXT: [[T4:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> <i32 0, i32 0, i32 undef, i32 undef>
; CHECK-NEXT: [[T6:%.*]] = shufflevector <4 x float> [[T]], <4 x float> undef, <4 x i32> zeroinitializer ; CHECK-NEXT: [[T6:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[T7:%.*]] = fadd <4 x float> [[T6]], [[T4]] ; CHECK-NEXT: [[T7:%.*]] = fadd <4 x float> [[T6]], [[T4]]
; CHECK-NEXT: ret <4 x float> [[T7]] ; CHECK-NEXT: ret <4 x float> [[T7]]
; ;
%t = insertelement <4 x float> poison, float %arg, i32 0 %t = insertelement <4 x float> poison, float %arg, i32 0
%t4 = insertelement <4 x float> %t, float %arg, i32 1 %t4 = insertelement <4 x float> %t, float %arg, i32 1
%t5 = insertelement <4 x float> %t4, float %arg, i32 2 %t5 = insertelement <4 x float> %t4, float %arg, i32 2
%t6 = insertelement <4 x float> %t5, float %arg, i32 3 %t6 = insertelement <4 x float> %t5, float %arg, i32 3
%t7 = fadd <4 x float> %t6, %t4 %t7 = fadd <4 x float> %t6, %t4
Show All 36 Lines

llvm/test/Transforms/InstCombine/broadcast.ll

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
; Multiple undef elements are ok. ; Multiple undef elements are ok.
; TODO: Multiple uses triggers the transform at %t4, but we should sink/scalarize/CSE the splats? ; TODO: Multiple uses triggers the transform at %t4, but we should sink/scalarize/CSE the splats?
define <4 x float> @splat_undef3(float %arg) { define <4 x float> @splat_undef3(float %arg) {
; CHECK-LABEL: @splat_undef3( ; CHECK-LABEL: @splat_undef3(
; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i32 0 ; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i32 0
; CHECK-NEXT: [[T4:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> <i32 0, i32 0, i32 undef, i32 undef> ; CHECK-NEXT: [[T4:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> <i32 0, i32 0, i32 undef, i32 undef>
; CHECK-NEXT: [[T6:%.*]] = shufflevector <4 x float> [[T]], <4 x float> undef, <4 x i32> zeroinitializer ; CHECK-NEXT: [[T6:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[T7:%.*]] = fadd <4 x float> [[T6]], [[T4]] ; CHECK-NEXT: [[T7:%.*]] = fadd <4 x float> [[T6]], [[T4]]
; CHECK-NEXT: ret <4 x float> [[T7]] ; CHECK-NEXT: ret <4 x float> [[T7]]
; ;
%t = insertelement <4 x float> undef, float %arg, i32 0 %t = insertelement <4 x float> undef, float %arg, i32 0
%t4 = insertelement <4 x float> %t, float %arg, i32 1 %t4 = insertelement <4 x float> %t, float %arg, i32 1
%t5 = insertelement <4 x float> %t4, float %arg, i32 2 %t5 = insertelement <4 x float> %t4, float %arg, i32 2
%t6 = insertelement <4 x float> %t5, float %arg, i32 3 %t6 = insertelement <4 x float> %t5, float %arg, i32 3
%t7 = fadd <4 x float> %t6, %t4 %t7 = fadd <4 x float> %t6, %t4
Show All 36 Lines

llvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltpoison.ll

Show First 20 Lines • Show All 422 Lines • ▼ Show 20 Lines;
%xv = insertelement <4 x float> %q, float %x, i32 2 %xv = insertelement <4 x float> %q, float %x, i32 2
%r = shufflevector <4 x float> %y, <4 x float> %xv, <5 x i32> <i32 0, i32 6, i32 2, i32 undef, i32 undef> %r = shufflevector <4 x float> %y, <4 x float> %xv, <5 x i32> <i32 0, i32 6, i32 2, i32 undef, i32 undef>
ret <5 x float> %r ret <5 x float> %r
} }
define <4 x float> @insert_nonzero_index_splat(float %x) { define <4 x float> @insert_nonzero_index_splat(float %x) {
; CHECK-LABEL: @insert_nonzero_index_splat( ; CHECK-LABEL: @insert_nonzero_index_splat(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i32 0
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
; CHECK-NEXT: ret <4 x float> [[SPLAT]] ; CHECK-NEXT: ret <4 x float> [[SPLAT]]
; ;
%xv = insertelement <4 x float> poison, float %x, i32 2 %xv = insertelement <4 x float> poison, float %x, i32 2
%splat = shufflevector <4 x float> %xv, <4 x float> poison, <4 x i32> <i32 undef, i32 2, i32 2, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> poison, <4 x i32> <i32 undef, i32 2, i32 2, i32 undef>
ret <4 x float> %splat ret <4 x float> %splat
} }
define <3 x double> @insert_nonzero_index_splat_narrow(double %x) { define <3 x double> @insert_nonzero_index_splat_narrow(double %x) {
; CHECK-LABEL: @insert_nonzero_index_splat_narrow( ; CHECK-LABEL: @insert_nonzero_index_splat_narrow(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x double> undef, double [[X:%.*]], i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x double> undef, double [[X:%.*]], i32 0
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <3 x double> [[TMP1]], <3 x double> undef, <3 x i32> <i32 0, i32 undef, i32 0> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <3 x double> [[TMP1]], <3 x double> poison, <3 x i32> <i32 0, i32 undef, i32 0>
; CHECK-NEXT: ret <3 x double> [[SPLAT]] ; CHECK-NEXT: ret <3 x double> [[SPLAT]]
; ;
%xv = insertelement <4 x double> poison, double %x, i32 3 %xv = insertelement <4 x double> poison, double %x, i32 3
%splat = shufflevector <4 x double> %xv, <4 x double> poison, <3 x i32> <i32 3, i32 undef, i32 3> %splat = shufflevector <4 x double> %xv, <4 x double> poison, <3 x i32> <i32 3, i32 undef, i32 3>
ret <3 x double> %splat ret <3 x double> %splat
} }
define <5 x i7> @insert_nonzero_index_splat_widen(i7 %x) { define <5 x i7> @insert_nonzero_index_splat_widen(i7 %x) {
; CHECK-LABEL: @insert_nonzero_index_splat_widen( ; CHECK-LABEL: @insert_nonzero_index_splat_widen(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <5 x i7> undef, i7 [[X:%.*]], i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <5 x i7> undef, i7 [[X:%.*]], i32 0
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <5 x i7> [[TMP1]], <5 x i7> undef, <5 x i32> <i32 undef, i32 0, i32 0, i32 undef, i32 0> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <5 x i7> [[TMP1]], <5 x i7> poison, <5 x i32> <i32 undef, i32 0, i32 0, i32 undef, i32 0>
; CHECK-NEXT: ret <5 x i7> [[SPLAT]] ; CHECK-NEXT: ret <5 x i7> [[SPLAT]]
; ;
%xv = insertelement <4 x i7> poison, i7 %x, i32 1 %xv = insertelement <4 x i7> poison, i7 %x, i32 1
%splat = shufflevector <4 x i7> %xv, <4 x i7> poison, <5 x i32> <i32 undef, i32 1, i32 1, i32 undef, i32 1> %splat = shufflevector <4 x i7> %xv, <4 x i7> poison, <5 x i32> <i32 undef, i32 1, i32 1, i32 undef, i32 1>
ret <5 x i7> %splat ret <5 x i7> %splat
} }
; Negative test - don't increase instruction count ; Negative test - don't increase instruction count
Show All 35 Lines;
%xv = insertelement <4 x float> poison, float %x, i32 %index %xv = insertelement <4 x float> poison, float %x, i32 %index
%splat = shufflevector <4 x float> %xv, <4 x float> poison, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> poison, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef>
ret <4 x float> %splat ret <4 x float> %splat
} }
define <4 x float> @insert_in_splat(float %x) { define <4 x float> @insert_in_splat(float %x) {
; CHECK-LABEL: @insert_in_splat( ; CHECK-LABEL: @insert_in_splat(
; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i32 0 ; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i32 0
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
; CHECK-NEXT: ret <4 x float> [[R]] ; CHECK-NEXT: ret <4 x float> [[R]]
; ;
%xv = insertelement <4 x float> poison, float %x, i32 0 %xv = insertelement <4 x float> poison, float %x, i32 0
%splat = shufflevector <4 x float> %xv, <4 x float> poison, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> poison, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
%r = insertelement <4 x float> %splat, float %x, i32 3 %r = insertelement <4 x float> %splat, float %x, i32 3
ret <4 x float> %r ret <4 x float> %r
} }
define <4 x float> @insert_in_splat_extra_uses(float %x) { define <4 x float> @insert_in_splat_extra_uses(float %x) {
; CHECK-LABEL: @insert_in_splat_extra_uses( ; CHECK-LABEL: @insert_in_splat_extra_uses(
; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i32 0 ; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i32 0
; CHECK-NEXT: call void @use(<4 x float> [[XV]]) ; CHECK-NEXT: call void @use(<4 x float> [[XV]])
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
; CHECK-NEXT: call void @use(<4 x float> [[SPLAT]]) ; CHECK-NEXT: call void @use(<4 x float> [[SPLAT]])
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
; CHECK-NEXT: ret <4 x float> [[R]] ; CHECK-NEXT: ret <4 x float> [[R]]
; ;
%xv = insertelement <4 x float> poison, float %x, i32 0 %xv = insertelement <4 x float> poison, float %x, i32 0
call void @use(<4 x float> %xv) call void @use(<4 x float> %xv)
%splat = shufflevector <4 x float> %xv, <4 x float> poison, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> poison, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
call void @use(<4 x float> %splat) call void @use(<4 x float> %splat)
%r = insertelement <4 x float> %splat, float %x, i32 3 %r = insertelement <4 x float> %splat, float %x, i32 3
ret <4 x float> %r ret <4 x float> %r
▲ Show 20 Lines • Show All 207 Lines • Show Last 20 Lines

llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll

Show First 20 Lines • Show All 422 Lines • ▼ Show 20 Lines;
%xv = insertelement <4 x float> %q, float %x, i32 2 %xv = insertelement <4 x float> %q, float %x, i32 2
%r = shufflevector <4 x float> %y, <4 x float> %xv, <5 x i32> <i32 0, i32 6, i32 2, i32 undef, i32 undef> %r = shufflevector <4 x float> %y, <4 x float> %xv, <5 x i32> <i32 0, i32 6, i32 2, i32 undef, i32 undef>
ret <5 x float> %r ret <5 x float> %r
} }
define <4 x float> @insert_nonzero_index_splat(float %x) { define <4 x float> @insert_nonzero_index_splat(float %x) {
; CHECK-LABEL: @insert_nonzero_index_splat( ; CHECK-LABEL: @insert_nonzero_index_splat(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i32 0
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
; CHECK-NEXT: ret <4 x float> [[SPLAT]] ; CHECK-NEXT: ret <4 x float> [[SPLAT]]
; ;
%xv = insertelement <4 x float> undef, float %x, i32 2 %xv = insertelement <4 x float> undef, float %x, i32 2
%splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 2, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 2, i32 undef>
ret <4 x float> %splat ret <4 x float> %splat
} }
define <3 x double> @insert_nonzero_index_splat_narrow(double %x) { define <3 x double> @insert_nonzero_index_splat_narrow(double %x) {
; CHECK-LABEL: @insert_nonzero_index_splat_narrow( ; CHECK-LABEL: @insert_nonzero_index_splat_narrow(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x double> undef, double [[X:%.*]], i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x double> undef, double [[X:%.*]], i32 0
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <3 x double> [[TMP1]], <3 x double> undef, <3 x i32> <i32 0, i32 undef, i32 0> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <3 x double> [[TMP1]], <3 x double> poison, <3 x i32> <i32 0, i32 undef, i32 0>
; CHECK-NEXT: ret <3 x double> [[SPLAT]] ; CHECK-NEXT: ret <3 x double> [[SPLAT]]
; ;
%xv = insertelement <4 x double> undef, double %x, i32 3 %xv = insertelement <4 x double> undef, double %x, i32 3
%splat = shufflevector <4 x double> %xv, <4 x double> undef, <3 x i32> <i32 3, i32 undef, i32 3> %splat = shufflevector <4 x double> %xv, <4 x double> undef, <3 x i32> <i32 3, i32 undef, i32 3>
ret <3 x double> %splat ret <3 x double> %splat
} }
define <5 x i7> @insert_nonzero_index_splat_widen(i7 %x) { define <5 x i7> @insert_nonzero_index_splat_widen(i7 %x) {
; CHECK-LABEL: @insert_nonzero_index_splat_widen( ; CHECK-LABEL: @insert_nonzero_index_splat_widen(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <5 x i7> undef, i7 [[X:%.*]], i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <5 x i7> undef, i7 [[X:%.*]], i32 0
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <5 x i7> [[TMP1]], <5 x i7> undef, <5 x i32> <i32 undef, i32 0, i32 0, i32 undef, i32 0> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <5 x i7> [[TMP1]], <5 x i7> poison, <5 x i32> <i32 undef, i32 0, i32 0, i32 undef, i32 0>
; CHECK-NEXT: ret <5 x i7> [[SPLAT]] ; CHECK-NEXT: ret <5 x i7> [[SPLAT]]
; ;
%xv = insertelement <4 x i7> undef, i7 %x, i32 1 %xv = insertelement <4 x i7> undef, i7 %x, i32 1
%splat = shufflevector <4 x i7> %xv, <4 x i7> undef, <5 x i32> <i32 undef, i32 1, i32 1, i32 undef, i32 1> %splat = shufflevector <4 x i7> %xv, <4 x i7> undef, <5 x i32> <i32 undef, i32 1, i32 1, i32 undef, i32 1>
ret <5 x i7> %splat ret <5 x i7> %splat
} }
; Negative test - don't increase instruction count ; Negative test - don't increase instruction count
Show All 35 Lines;
%xv = insertelement <4 x float> undef, float %x, i32 %index %xv = insertelement <4 x float> undef, float %x, i32 %index
%splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef>
ret <4 x float> %splat ret <4 x float> %splat
} }
define <4 x float> @insert_in_splat(float %x) { define <4 x float> @insert_in_splat(float %x) {
; CHECK-LABEL: @insert_in_splat( ; CHECK-LABEL: @insert_in_splat(
; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i32 0 ; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i32 0
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
; CHECK-NEXT: ret <4 x float> [[R]] ; CHECK-NEXT: ret <4 x float> [[R]]
; ;
%xv = insertelement <4 x float> undef, float %x, i32 0 %xv = insertelement <4 x float> undef, float %x, i32 0
%splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
%r = insertelement <4 x float> %splat, float %x, i32 3 %r = insertelement <4 x float> %splat, float %x, i32 3
ret <4 x float> %r ret <4 x float> %r
} }
define <4 x float> @insert_in_splat_extra_uses(float %x) { define <4 x float> @insert_in_splat_extra_uses(float %x) {
; CHECK-LABEL: @insert_in_splat_extra_uses( ; CHECK-LABEL: @insert_in_splat_extra_uses(
; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i32 0 ; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i32 0
; CHECK-NEXT: call void @use(<4 x float> [[XV]]) ; CHECK-NEXT: call void @use(<4 x float> [[XV]])
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
; CHECK-NEXT: call void @use(<4 x float> [[SPLAT]]) ; CHECK-NEXT: call void @use(<4 x float> [[SPLAT]])
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
; CHECK-NEXT: ret <4 x float> [[R]] ; CHECK-NEXT: ret <4 x float> [[R]]
; ;
%xv = insertelement <4 x float> undef, float %x, i32 0 %xv = insertelement <4 x float> undef, float %x, i32 0
call void @use(<4 x float> %xv) call void @use(<4 x float> %xv)
%splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
call void @use(<4 x float> %splat) call void @use(<4 x float> %splat)
%r = insertelement <4 x float> %splat, float %x, i32 3 %r = insertelement <4 x float> %splat, float %x, i32 3
ret <4 x float> %r ret <4 x float> %r
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llvm/test/Transforms/InstCombine/obfuscated_splat-inseltpoison.ll

; RUN: opt -instcombine -S < %s | FileCheck %s ; RUN: opt -instcombine -S < %s | FileCheck %s
define void @test(<4 x float> *%in_ptr, <4 x float> *%out_ptr) { define void @test(<4 x float> *%in_ptr, <4 x float> *%out_ptr) {
%A = load <4 x float>, <4 x float>* %in_ptr, align 16 %A = load <4 x float>, <4 x float>* %in_ptr, align 16
%B = shufflevector <4 x float> %A, <4 x float> poison, <4 x i32> <i32 0, i32 0, i32 undef, i32 undef> %B = shufflevector <4 x float> %A, <4 x float> poison, <4 x i32> <i32 0, i32 0, i32 undef, i32 undef>
%C = shufflevector <4 x float> %B, <4 x float> %A, <4 x i32> <i32 0, i32 1, i32 4, i32 undef> %C = shufflevector <4 x float> %B, <4 x float> %A, <4 x i32> <i32 0, i32 1, i32 4, i32 undef>
%D = shufflevector <4 x float> %C, <4 x float> %A, <4 x i32> <i32 0, i32 1, i32 2, i32 4> %D = shufflevector <4 x float> %C, <4 x float> %A, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
; CHECK: %D = shufflevector <4 x float> %A, <4 x float> undef, <4 x i32> zeroinitializer ; CHECK: %D = shufflevector <4 x float> %A, <4 x float> poison, <4 x i32> zeroinitializer
store <4 x float> %D, <4 x float> *%out_ptr store <4 x float> %D, <4 x float> *%out_ptr
ret void ret void
} }

llvm/test/Transforms/InstCombine/obfuscated_splat.ll

; RUN: opt -instcombine -S < %s | FileCheck %s ; RUN: opt -instcombine -S < %s | FileCheck %s
define void @test(<4 x float> *%in_ptr, <4 x float> *%out_ptr) { define void @test(<4 x float> *%in_ptr, <4 x float> *%out_ptr) {
%A = load <4 x float>, <4 x float>* %in_ptr, align 16 %A = load <4 x float>, <4 x float>* %in_ptr, align 16
%B = shufflevector <4 x float> %A, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 undef, i32 undef> %B = shufflevector <4 x float> %A, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 undef, i32 undef>
%C = shufflevector <4 x float> %B, <4 x float> %A, <4 x i32> <i32 0, i32 1, i32 4, i32 undef> %C = shufflevector <4 x float> %B, <4 x float> %A, <4 x i32> <i32 0, i32 1, i32 4, i32 undef>
%D = shufflevector <4 x float> %C, <4 x float> %A, <4 x i32> <i32 0, i32 1, i32 2, i32 4> %D = shufflevector <4 x float> %C, <4 x float> %A, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
; CHECK: %D = shufflevector <4 x float> %A, <4 x float> undef, <4 x i32> zeroinitializer ; CHECK: %D = shufflevector <4 x float> %A, <4 x float> poison, <4 x i32> zeroinitializer
store <4 x float> %D, <4 x float> *%out_ptr store <4 x float> %D, <4 x float> *%out_ptr
ret void ret void
} }

llvm/test/Transforms/InstCombine/reduction-shufflevector.ll

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ret float %res ret float %res
} }
; Failed cases ; Failed cases
; TODO: simplify the reductions for shuffles resulting in undef/poison elements. ; TODO: simplify the reductions for shuffles resulting in undef/poison elements.
define i32 @reduce_add_failed(<4 x i32> %x) { define i32 @reduce_add_failed(<4 x i32> %x) {
; CHECK-LABEL: @reduce_add_failed( ; CHECK-LABEL: @reduce_add_failed(
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 0> ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 0>
; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[SHUF]]) ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[SHUF]])
; CHECK-NEXT: ret i32 [[RES]] ; CHECK-NEXT: ret i32 [[RES]]
; ;
%shuf = shufflevector <4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 0, i32 1, i32 2, i32 4> %shuf = shufflevector <4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
%res = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %shuf) %res = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %shuf)
ret i32 %res ret i32 %res
} }
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; ;
%shuf = shufflevector <8 x i32> %x, <8 x i32> poison, <4 x i32> <i32 2, i32 0, i32 3, i32 1> %shuf = shufflevector <8 x i32> %x, <8 x i32> poison, <4 x i32> <i32 2, i32 0, i32 3, i32 1>
%res = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %shuf) %res = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %shuf)
ret i32 %res ret i32 %res
} }
define i32 @reduce_smin_failed(<8 x i32> %x) { define i32 @reduce_smin_failed(<8 x i32> %x) {
; CHECK-LABEL: @reduce_smin_failed( ; CHECK-LABEL: @reduce_smin_failed(
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <8 x i32> [[X:%.*]], <8 x i32> undef, <4 x i32> <i32 0, i32 3, i32 1, i32 2> ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <8 x i32> [[X:%.*]], <8 x i32> poison, <4 x i32> <i32 0, i32 3, i32 1, i32 2>
; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[SHUF]]) ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[SHUF]])
; CHECK-NEXT: ret i32 [[RES]] ; CHECK-NEXT: ret i32 [[RES]]
; ;
%shuf = shufflevector <8 x i32> %x, <8 x i32> %x, <4 x i32> <i32 0, i32 3, i32 1, i32 2> %shuf = shufflevector <8 x i32> %x, <8 x i32> %x, <4 x i32> <i32 0, i32 3, i32 1, i32 2>
%res = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %shuf) %res = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %shuf)
ret i32 %res ret i32 %res
} }
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llvm/test/Transforms/InstCombine/shuffle-cast-dist.ll

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%yb = bitcast <2 x bfloat> %y to <2 x i16> %yb = bitcast <2 x bfloat> %y to <2 x i16>
%r = shufflevector <2 x i16> %xb, <2 x i16> %yb, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %r = shufflevector <2 x i16> %xb, <2 x i16> %yb, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x i16> %r ret <4 x i16> %r
} }
define <2 x float> @bc_shuf_reuse(<4 x i32> %x){ define <2 x float> @bc_shuf_reuse(<4 x i32> %x){
; CHECK-LABEL: @bc_shuf_reuse( ; CHECK-LABEL: @bc_shuf_reuse(
; CHECK-NEXT: [[XB:%.*]] = bitcast <4 x i32> [[X:%.*]] to <4 x float> ; CHECK-NEXT: [[XB:%.*]] = bitcast <4 x i32> [[X:%.*]] to <4 x float>
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[XB]], <4 x float> undef, <2 x i32> zeroinitializer ; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[XB]], <4 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x float> [[R]] ; CHECK-NEXT: ret <2 x float> [[R]]
; ;
%xb = bitcast <4 x i32> %x to <4 x float> %xb = bitcast <4 x i32> %x to <4 x float>
%r = shufflevector <4 x float> %xb, <4 x float> %xb, <2 x i32> <i32 0, i32 4> %r = shufflevector <4 x float> %xb, <4 x float> %xb, <2 x i32> <i32 0, i32 4>
ret <2 x float> %r ret <2 x float> %r
} }
define <4 x float> @bc_shuf_y_hasoneuse(<4 x i32> %x, <4 x i32> %y){ define <4 x float> @bc_shuf_y_hasoneuse(<4 x i32> %x, <4 x i32> %y){
Show All 10 Lines;
%r = fadd <4 x float> %xb, %shuf %r = fadd <4 x float> %xb, %shuf
ret <4 x float> %r ret <4 x float> %r
} }
define <4 x float> @bc_shuf_neither_hasoneuse(<4 x i32> %x, <4 x i32> %y){ define <4 x float> @bc_shuf_neither_hasoneuse(<4 x i32> %x, <4 x i32> %y){
; CHECK-LABEL: @bc_shuf_neither_hasoneuse( ; CHECK-LABEL: @bc_shuf_neither_hasoneuse(
; CHECK-NEXT: [[XB:%.*]] = bitcast <4 x i32> [[X:%.*]] to <4 x float> ; CHECK-NEXT: [[XB:%.*]] = bitcast <4 x i32> [[X:%.*]] to <4 x float>
; CHECK-NEXT: [[YB:%.*]] = bitcast <4 x i32> [[Y:%.*]] to <4 x float> ; CHECK-NEXT: [[YB:%.*]] = bitcast <4 x i32> [[Y:%.*]] to <4 x float>
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x float> [[XB]], <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x float> [[XB]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[SUM:%.*]] = fadd <4 x float> [[XB]], [[YB]] ; CHECK-NEXT: [[SUM:%.*]] = fadd <4 x float> [[XB]], [[YB]]
; CHECK-NEXT: [[R:%.*]] = fadd <4 x float> [[SUM]], [[SHUF]] ; CHECK-NEXT: [[R:%.*]] = fadd <4 x float> [[SUM]], [[SHUF]]
; CHECK-NEXT: ret <4 x float> [[R]] ; CHECK-NEXT: ret <4 x float> [[R]]
; ;
%xb = bitcast <4 x i32> %x to <4 x float> %xb = bitcast <4 x i32> %x to <4 x float>
%yb = bitcast <4 x i32> %y to <4 x float> %yb = bitcast <4 x i32> %y to <4 x float>
%shuf = shufflevector <4 x float> %xb, <4 x float> %xb, <4 x i32> <i32 0, i32 1, i32 4, i32 5> %shuf = shufflevector <4 x float> %xb, <4 x float> %xb, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
%sum = fadd <4 x float> %xb, %yb %sum = fadd <4 x float> %xb, %yb
%r = fadd <4 x float> %sum, %shuf %r = fadd <4 x float> %sum, %shuf
ret <4 x float> %r ret <4 x float> %r
} }

llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll

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%trunc = trunc <3 x i33> %shuf to <3 x i31> %trunc = trunc <3 x i33> %shuf to <3 x i31>
ret <3 x i31> %trunc ret <3 x i31> %trunc
} }
; TODO: The shuffle extends the length of the input vector. Should we shrink this? ; TODO: The shuffle extends the length of the input vector. Should we shrink this?
define <8 x i8> @wide_lengthening_splat(<4 x i16> %v) { define <8 x i8> @wide_lengthening_splat(<4 x i16> %v) {
; CHECK-LABEL: @wide_lengthening_splat( ; CHECK-LABEL: @wide_lengthening_splat(
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i16> [[V:%.*]], <4 x i16> undef, <8 x i32> zeroinitializer ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i16> [[V:%.*]], <4 x i16> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TR:%.*]] = trunc <8 x i16> [[SHUF]] to <8 x i8> ; CHECK-NEXT: [[TR:%.*]] = trunc <8 x i16> [[SHUF]] to <8 x i8>
; CHECK-NEXT: ret <8 x i8> [[TR]] ; CHECK-NEXT: ret <8 x i8> [[TR]]
; ;
%shuf = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> zeroinitializer %shuf = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> zeroinitializer
%tr = trunc <8 x i16> %shuf to <8 x i8> %tr = trunc <8 x i16> %shuf to <8 x i8>
ret <8 x i8> %tr ret <8 x i8> %tr
} }
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llvm/test/Transforms/InstCombine/trunc.ll

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%trunc = trunc <3 x i33> %shuf to <3 x i31> %trunc = trunc <3 x i33> %shuf to <3 x i31>
ret <3 x i31> %trunc ret <3 x i31> %trunc
} }
; TODO: The shuffle extends the length of the input vector. Should we shrink this? ; TODO: The shuffle extends the length of the input vector. Should we shrink this?
define <8 x i8> @wide_lengthening_splat(<4 x i16> %v) { define <8 x i8> @wide_lengthening_splat(<4 x i16> %v) {
; CHECK-LABEL: @wide_lengthening_splat( ; CHECK-LABEL: @wide_lengthening_splat(
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i16> [[V:%.*]], <4 x i16> undef, <8 x i32> zeroinitializer ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i16> [[V:%.*]], <4 x i16> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TR:%.*]] = trunc <8 x i16> [[SHUF]] to <8 x i8> ; CHECK-NEXT: [[TR:%.*]] = trunc <8 x i16> [[SHUF]] to <8 x i8>
; CHECK-NEXT: ret <8 x i8> [[TR]] ; CHECK-NEXT: ret <8 x i8> [[TR]]
; ;
%shuf = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> zeroinitializer %shuf = shufflevector <4 x i16> %v, <4 x i16> %v, <8 x i32> zeroinitializer
%tr = trunc <8 x i16> %shuf to <8 x i8> %tr = trunc <8 x i16> %shuf to <8 x i8>
ret <8 x i8> %tr ret <8 x i8> %tr
} }
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llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Linesentry:
store <4 x float> %vecins8, <4 x float>* %a store <4 x float> %vecins8, <4 x float>* %a
ret void ret void
} }
declare i32 @fgetc(i8*) declare i32 @fgetc(i8*)
define <4 x float> @dead_shuffle_elt(<4 x float> %x, <2 x float> %y) nounwind { define <4 x float> @dead_shuffle_elt(<4 x float> %x, <2 x float> %y) nounwind {
; CHECK-LABEL: @dead_shuffle_elt( ; CHECK-LABEL: @dead_shuffle_elt(
; CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x float> [[Y:%.*]], <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ; CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x float> [[Y:%.*]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; CHECK-NEXT: [[SHUFFLE9_I:%.*]] = shufflevector <4 x float> [[SHUFFLE_I]], <4 x float> [[X:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7> ; CHECK-NEXT: [[SHUFFLE9_I:%.*]] = shufflevector <4 x float> [[SHUFFLE_I]], <4 x float> [[X:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
; CHECK-NEXT: ret <4 x float> [[SHUFFLE9_I]] ; CHECK-NEXT: ret <4 x float> [[SHUFFLE9_I]]
; ;
%shuffle.i = shufflevector <2 x float> %y, <2 x float> %y, <4 x i32> <i32 0, i32 1, i32 0, i32 1> %shuffle.i = shufflevector <2 x float> %y, <2 x float> %y, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
%shuffle9.i = shufflevector <4 x float> %x, <4 x float> %shuffle.i, <4 x i32> <i32 4, i32 5, i32 2, i32 3> %shuffle9.i = shufflevector <4 x float> %x, <4 x float> %shuffle.i, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
ret <4 x float> %shuffle9.i ret <4 x float> %shuffle9.i
} }
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%bo = frem ninf reassoc <3 x float> %x, <float 1.0, float 2.0, float 3.0> %bo = frem ninf reassoc <3 x float> %x, <float 1.0, float 2.0, float 3.0>
%r = shufflevector <3 x float> %bo, <3 x float> poison, <3 x i32> <i32 1, i32 undef, i32 2> %r = shufflevector <3 x float> %bo, <3 x float> poison, <3 x i32> <i32 1, i32 undef, i32 2>
ret <3 x float> %r ret <3 x float> %r
} }
define i32* @gep_vbase_w_s_idx(<2 x i32*> %base, i64 %index) { define i32* @gep_vbase_w_s_idx(<2 x i32*> %base, i64 %index) {
; CHECK-LABEL: @gep_vbase_w_s_idx( ; CHECK-LABEL: @gep_vbase_w_s_idx(
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32*> [[BASE:%.*]], i32 1 ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32*> [[BASE:%.*]], i32 1
; CHECK-NEXT: [[EE:%.*]] = getelementptr i32, i32* [[TMP1]], i64 %index ; CHECK-NEXT: [[EE:%.*]] = getelementptr i32, i32* [[TMP1]], i64 [[INDEX:%.*]]
; CHECK-NEXT: ret i32* [[EE]] ; CHECK-NEXT: ret i32* [[EE]]
; ;
%gep = getelementptr i32, <2 x i32*> %base, i64 %index %gep = getelementptr i32, <2 x i32*> %base, i64 %index
%ee = extractelement <2 x i32*> %gep, i32 1 %ee = extractelement <2 x i32*> %gep, i32 1
ret i32* %ee ret i32* %ee
} }
define i32* @gep_splat_base_w_s_idx(i32* %base) { define i32* @gep_splat_base_w_s_idx(i32* %base) {
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llvm/test/Transforms/InstCombine/vec_demanded_elts.ll

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Linesentry:
store <4 x float> %vecins8, <4 x float>* %a store <4 x float> %vecins8, <4 x float>* %a
ret void ret void
} }
declare i32 @fgetc(i8*) declare i32 @fgetc(i8*)
define <4 x float> @dead_shuffle_elt(<4 x float> %x, <2 x float> %y) nounwind { define <4 x float> @dead_shuffle_elt(<4 x float> %x, <2 x float> %y) nounwind {
; CHECK-LABEL: @dead_shuffle_elt( ; CHECK-LABEL: @dead_shuffle_elt(
; CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x float> [[Y:%.*]], <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ; CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x float> [[Y:%.*]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; CHECK-NEXT: [[SHUFFLE9_I:%.*]] = shufflevector <4 x float> [[SHUFFLE_I]], <4 x float> [[X:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7> ; CHECK-NEXT: [[SHUFFLE9_I:%.*]] = shufflevector <4 x float> [[SHUFFLE_I]], <4 x float> [[X:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
; CHECK-NEXT: ret <4 x float> [[SHUFFLE9_I]] ; CHECK-NEXT: ret <4 x float> [[SHUFFLE9_I]]
; ;
%shuffle.i = shufflevector <2 x float> %y, <2 x float> %y, <4 x i32> <i32 0, i32 1, i32 0, i32 1> %shuffle.i = shufflevector <2 x float> %y, <2 x float> %y, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
%shuffle9.i = shufflevector <4 x float> %x, <4 x float> %shuffle.i, <4 x i32> <i32 4, i32 5, i32 2, i32 3> %shuffle9.i = shufflevector <4 x float> %x, <4 x float> %shuffle.i, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
ret <4 x float> %shuffle9.i ret <4 x float> %shuffle9.i
} }
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%bo = frem ninf reassoc <3 x float> %x, <float 1.0, float 2.0, float 3.0> %bo = frem ninf reassoc <3 x float> %x, <float 1.0, float 2.0, float 3.0>
%r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 1, i32 undef, i32 2> %r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 1, i32 undef, i32 2>
ret <3 x float> %r ret <3 x float> %r
} }
define i32* @gep_vbase_w_s_idx(<2 x i32*> %base, i64 %index) { define i32* @gep_vbase_w_s_idx(<2 x i32*> %base, i64 %index) {
; CHECK-LABEL: @gep_vbase_w_s_idx( ; CHECK-LABEL: @gep_vbase_w_s_idx(
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32*> [[BASE:%.*]], i32 1 ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32*> [[BASE:%.*]], i32 1
; CHECK-NEXT: [[EE:%.*]] = getelementptr i32, i32* [[TMP1]], i64 %index ; CHECK-NEXT: [[EE:%.*]] = getelementptr i32, i32* [[TMP1]], i64 [[INDEX:%.*]]
; CHECK-NEXT: ret i32* [[EE]] ; CHECK-NEXT: ret i32* [[EE]]
; ;
%gep = getelementptr i32, <2 x i32*> %base, i64 %index %gep = getelementptr i32, <2 x i32*> %base, i64 %index
%ee = extractelement <2 x i32*> %gep, i32 1 %ee = extractelement <2 x i32*> %gep, i32 1
ret i32* %ee ret i32* %ee
} }
define i32* @gep_splat_base_w_s_idx(i32* %base) { define i32* @gep_splat_base_w_s_idx(i32* %base) {
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llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll

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%m1 = mul <4 x i32> %s1, %s1 %m1 = mul <4 x i32> %s1, %s1
%s2 = shufflevector <4 x i32> %m1, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %s2 = shufflevector <4 x i32> %m1, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %s2 ret <4 x i32> %s2
} }
; Do not reorder shuffle and binop if LHS of shuffles are of different size ; Do not reorder shuffle and binop if LHS of shuffles are of different size
define <2 x i32> @pr19717(<4 x i32> %in0, <2 x i32> %in1) { define <2 x i32> @pr19717(<4 x i32> %in0, <2 x i32> %in1) {
; CHECK-LABEL: @pr19717( ; CHECK-LABEL: @pr19717(
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[IN0:%.*]], <4 x i32> undef, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[IN0:%.*]], <4 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[SHUFFLE4:%.*]] = shufflevector <2 x i32> [[IN1:%.*]], <2 x i32> undef, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SHUFFLE4:%.*]] = shufflevector <2 x i32> [[IN1:%.*]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[MUL:%.*]] = mul <2 x i32> [[SHUFFLE]], [[SHUFFLE4]] ; CHECK-NEXT: [[MUL:%.*]] = mul <2 x i32> [[SHUFFLE]], [[SHUFFLE4]]
; CHECK-NEXT: ret <2 x i32> [[MUL]] ; CHECK-NEXT: ret <2 x i32> [[MUL]]
; ;
%shuffle = shufflevector <4 x i32> %in0, <4 x i32> %in0, <2 x i32> zeroinitializer %shuffle = shufflevector <4 x i32> %in0, <4 x i32> %in0, <2 x i32> zeroinitializer
%shuffle4 = shufflevector <2 x i32> %in1, <2 x i32> %in1, <2 x i32> zeroinitializer %shuffle4 = shufflevector <2 x i32> %in1, <2 x i32> %in1, <2 x i32> zeroinitializer
%mul = mul <2 x i32> %shuffle, %shuffle4 %mul = mul <2 x i32> %shuffle, %shuffle4
ret <2 x i32> %mul ret <2 x i32> %mul
} }
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%s3 = shufflevector <8 x i8> %s1, <8 x i8> %s2, <2 x i32> <i32 0, i32 8> %s3 = shufflevector <8 x i8> %s1, <8 x i8> %s2, <2 x i32> <i32 0, i32 8>
ret <2 x i8> %s3 ret <2 x i8> %s3
} }
; Similar to above, but this reduces to a widen with undefs of 'x'. ; Similar to above, but this reduces to a widen with undefs of 'x'.
define <4 x double> @insert_subvector_shuffles_identity(<2 x double> %x) { define <4 x double> @insert_subvector_shuffles_identity(<2 x double> %x) {
; CHECK-LABEL: @insert_subvector_shuffles_identity( ; CHECK-LABEL: @insert_subvector_shuffles_identity(
; CHECK-NEXT: [[S3:%.*]] = shufflevector <2 x double> [[X:%.*]], <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ; CHECK-NEXT: [[S3:%.*]] = shufflevector <2 x double> [[X:%.*]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; CHECK-NEXT: ret <4 x double> [[S3]] ; CHECK-NEXT: ret <4 x double> [[S3]]
; ;
%s1 = shufflevector <2 x double> %x, <2 x double> poison, <4 x i32> <i32 undef, i32 1, i32 undef, i32 undef> %s1 = shufflevector <2 x double> %x, <2 x double> poison, <4 x i32> <i32 undef, i32 1, i32 undef, i32 undef>
%s2 = shufflevector <2 x double> %x, <2 x double> poison, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef> %s2 = shufflevector <2 x double> %x, <2 x double> poison, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
%s3 = shufflevector <4 x double> %s2, <4 x double> %s1, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef> %s3 = shufflevector <4 x double> %s2, <4 x double> %s1, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
ret <4 x double> %s3 ret <4 x double> %s3
} }
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} }
; Demanded vector elements may not be able to simplify a shuffle mask ; Demanded vector elements may not be able to simplify a shuffle mask
; before we try to narrow it. This used to crash. ; before we try to narrow it. This used to crash.
define <4 x float> @insert_subvector_crash_invalid_mask_elt(<2 x float> %x, <4 x float>* %p) { define <4 x float> @insert_subvector_crash_invalid_mask_elt(<2 x float> %x, <4 x float>* %p) {
; CHECK-LABEL: @insert_subvector_crash_invalid_mask_elt( ; CHECK-LABEL: @insert_subvector_crash_invalid_mask_elt(
; CHECK-NEXT: [[WIDEN:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ; CHECK-NEXT: [[WIDEN:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; CHECK-NEXT: [[I:%.*]] = shufflevector <2 x float> [[X]], <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ; CHECK-NEXT: [[I:%.*]] = shufflevector <2 x float> [[X]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; CHECK-NEXT: store <4 x float> [[I]], <4 x float>* [[P:%.*]], align 16 ; CHECK-NEXT: store <4 x float> [[I]], <4 x float>* [[P:%.*]], align 16
; CHECK-NEXT: ret <4 x float> [[WIDEN]] ; CHECK-NEXT: ret <4 x float> [[WIDEN]]
; ;
%widen = shufflevector <2 x float> %x, <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %widen = shufflevector <2 x float> %x, <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%ext2 = extractelement <2 x float> %x, i32 0 %ext2 = extractelement <2 x float> %x, i32 0
%I = insertelement <4 x float> %widen, float %ext2, i16 0 %I = insertelement <4 x float> %widen, float %ext2, i16 0
store <4 x float> %I, <4 x float>* %p store <4 x float> %I, <4 x float>* %p
ret <4 x float> %widen ret <4 x float> %widen
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llvm/test/Transforms/InstCombine/vec_shuffle.ll

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%m1 = mul <4 x i32> %s1, %s1 %m1 = mul <4 x i32> %s1, %s1
%s2 = shufflevector <4 x i32> %m1, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %s2 = shufflevector <4 x i32> %m1, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %s2 ret <4 x i32> %s2
} }
; Do not reorder shuffle and binop if LHS of shuffles are of different size ; Do not reorder shuffle and binop if LHS of shuffles are of different size
define <2 x i32> @pr19717(<4 x i32> %in0, <2 x i32> %in1) { define <2 x i32> @pr19717(<4 x i32> %in0, <2 x i32> %in1) {
; CHECK-LABEL: @pr19717( ; CHECK-LABEL: @pr19717(
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[IN0:%.*]], <4 x i32> undef, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[IN0:%.*]], <4 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[SHUFFLE4:%.*]] = shufflevector <2 x i32> [[IN1:%.*]], <2 x i32> undef, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SHUFFLE4:%.*]] = shufflevector <2 x i32> [[IN1:%.*]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[MUL:%.*]] = mul <2 x i32> [[SHUFFLE]], [[SHUFFLE4]] ; CHECK-NEXT: [[MUL:%.*]] = mul <2 x i32> [[SHUFFLE]], [[SHUFFLE4]]
; CHECK-NEXT: ret <2 x i32> [[MUL]] ; CHECK-NEXT: ret <2 x i32> [[MUL]]
; ;
%shuffle = shufflevector <4 x i32> %in0, <4 x i32> %in0, <2 x i32> zeroinitializer %shuffle = shufflevector <4 x i32> %in0, <4 x i32> %in0, <2 x i32> zeroinitializer
%shuffle4 = shufflevector <2 x i32> %in1, <2 x i32> %in1, <2 x i32> zeroinitializer %shuffle4 = shufflevector <2 x i32> %in1, <2 x i32> %in1, <2 x i32> zeroinitializer
%mul = mul <2 x i32> %shuffle, %shuffle4 %mul = mul <2 x i32> %shuffle, %shuffle4
ret <2 x i32> %mul ret <2 x i32> %mul
} }
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%s3 = shufflevector <8 x i8> %s1, <8 x i8> %s2, <2 x i32> <i32 0, i32 8> %s3 = shufflevector <8 x i8> %s1, <8 x i8> %s2, <2 x i32> <i32 0, i32 8>
ret <2 x i8> %s3 ret <2 x i8> %s3
} }
; Similar to above, but this reduces to a widen with undefs of 'x'. ; Similar to above, but this reduces to a widen with undefs of 'x'.
define <4 x double> @insert_subvector_shuffles_identity(<2 x double> %x) { define <4 x double> @insert_subvector_shuffles_identity(<2 x double> %x) {
; CHECK-LABEL: @insert_subvector_shuffles_identity( ; CHECK-LABEL: @insert_subvector_shuffles_identity(
; CHECK-NEXT: [[S3:%.*]] = shufflevector <2 x double> [[X:%.*]], <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ; CHECK-NEXT: [[S3:%.*]] = shufflevector <2 x double> [[X:%.*]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; CHECK-NEXT: ret <4 x double> [[S3]] ; CHECK-NEXT: ret <4 x double> [[S3]]
; ;
%s1 = shufflevector <2 x double> %x, <2 x double> undef, <4 x i32> <i32 undef, i32 1, i32 undef, i32 undef> %s1 = shufflevector <2 x double> %x, <2 x double> undef, <4 x i32> <i32 undef, i32 1, i32 undef, i32 undef>
%s2 = shufflevector <2 x double> %x, <2 x double> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef> %s2 = shufflevector <2 x double> %x, <2 x double> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
%s3 = shufflevector <4 x double> %s2, <4 x double> %s1, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef> %s3 = shufflevector <4 x double> %s2, <4 x double> %s1, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
ret <4 x double> %s3 ret <4 x double> %s3
} }
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} }
; Demanded vector elements may not be able to simplify a shuffle mask ; Demanded vector elements may not be able to simplify a shuffle mask
; before we try to narrow it. This used to crash. ; before we try to narrow it. This used to crash.
define <4 x float> @insert_subvector_crash_invalid_mask_elt(<2 x float> %x, <4 x float>* %p) { define <4 x float> @insert_subvector_crash_invalid_mask_elt(<2 x float> %x, <4 x float>* %p) {
; CHECK-LABEL: @insert_subvector_crash_invalid_mask_elt( ; CHECK-LABEL: @insert_subvector_crash_invalid_mask_elt(
; CHECK-NEXT: [[WIDEN:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ; CHECK-NEXT: [[WIDEN:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; CHECK-NEXT: [[I:%.*]] = shufflevector <2 x float> [[X]], <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ; CHECK-NEXT: [[I:%.*]] = shufflevector <2 x float> [[X]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; CHECK-NEXT: store <4 x float> [[I]], <4 x float>* [[P:%.*]], align 16 ; CHECK-NEXT: store <4 x float> [[I]], <4 x float>* [[P:%.*]], align 16
; CHECK-NEXT: ret <4 x float> [[WIDEN]] ; CHECK-NEXT: ret <4 x float> [[WIDEN]]
; ;
%widen = shufflevector <2 x float> %x, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %widen = shufflevector <2 x float> %x, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%ext2 = extractelement <2 x float> %x, i32 0 %ext2 = extractelement <2 x float> %x, i32 0
%I = insertelement <4 x float> %widen, float %ext2, i16 0 %I = insertelement <4 x float> %widen, float %ext2, i16 0
store <4 x float> %I, <4 x float>* %p store <4 x float> %I, <4 x float>* %p
ret <4 x float> %widen ret <4 x float> %widen
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