[AMDGPU] Prefer v_fmac over v_fma only when no source modifiers are used

[foad]

Summary

v_fmac with source modifiers forces VOP3 encoding, but it is strictly
better to use the VOP3-only v_fma instead, because $dst and $src2 are
not tied so it gives the register allocator more freedom and avoids a
copy in some cases.

This is the same strategy we already use for v_mad vs v_mac and
v_fma_legacy vs v_fmac_legacy.

llvm/lib/Target/AMDGPU/SIInstructions.td

let SubtargetPredicate = NotHasMinMaxDenormModes in {
   // potentially being called from flushing kernels. Really we should
   // not be mixing code expecting different default FP modes, but mul
   // works in any FP environment.
   defm : SelectCanonicalizeAsMax<[FalsePredicate], [FP64Denormals], [FP16Denormals]>;
 } // End SubtargetPredicate = NotHasMinMaxDenormModes
 
 
 let OtherPredicates = [HasDLInsts] in {
+// Don't allow source modifiers. If there are any source modifiers then it's
+// better to select fma instead of fmac.
 def : GCNPat <
-  (fma (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)),
-       (f32 (VOP3Mods f32:$src1, i32:$src1_modifiers)),
+  (fma (f32 (VOP3NoMods f32:$src0)),
+       (f32 (VOP3NoMods f32:$src1)),
        (f32 (VOP3NoMods f32:$src2))),
-  (V_FMAC_F32_e64 $src0_modifiers, $src0, $src1_modifiers, $src1,
+  (V_FMAC_F32_e64 SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
                   SRCMODS.NONE, $src2)
 >;
 } // End OtherPredicates = [HasDLInsts]
 
 let SubtargetPredicate = isGFX10Plus in
+// Don't allow source modifiers. If there are any source modifiers then it's
+// better to select fma instead of fmac.
 def : GCNPat <
-  (fma (f16 (VOP3Mods f32:$src0, i32:$src0_modifiers)),
-       (f16 (VOP3Mods f32:$src1, i32:$src1_modifiers)),
+  (fma (f16 (VOP3NoMods f32:$src0)),
+       (f16 (VOP3NoMods f32:$src1)),
        (f16 (VOP3NoMods f32:$src2))),
-  (V_FMAC_F16_e64 $src0_modifiers, $src0, $src1_modifiers, $src1,
+  (V_FMAC_F16_e64 SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
                   SRCMODS.NONE, $src2)
 >;
 
 let SubtargetPredicate = isGFX90APlus in
+// Don't allow source modifiers. If there are any source modifiers then it's
+// better to select fma instead of fmac.
 def : GCNPat <
-  (fma (f64 (VOP3Mods0 f64:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
-       (f64 (VOP3Mods f64:$src1, i32:$src1_modifiers)),
+  (fma (f64 (VOP3NoMods f64:$src0)),
+       (f64 (VOP3NoMods f64:$src1)),
        (f64 (VOP3NoMods f64:$src2))),
-  (V_FMAC_F64_e64 $src0_modifiers, $src0, $src1_modifiers, $src1,
-                  SRCMODS.NONE, $src2, $clamp, $omod)
+  (V_FMAC_F64_e64 SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
+                  SRCMODS.NONE, $src2)
 >;
 
 // COPY is workaround tablegen bug from multiple outputs
 // from S_LSHL_B32's multiple outputs from implicit scc def.
 def : GCNPat <
   (v2i16 (build_vector (i16 0), (i16 SReg_32:$src1))),
   (S_LSHL_B32 SReg_32:$src1, (i16 16))
 >;

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll

 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v1, v1, v0
 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
 ; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
-; GFX10-IEEE-NEXT:    v_fma_f32 v6, v4, -v2, v5
+; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
-; GFX10-IEEE-NEXT:    v_fmac_f32_e64 v5, -v2, v4
-; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v5, v3, v4
+; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
+; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-FLUSH-LABEL: v_fdiv_f32:
 ; GFX10-FLUSH:       ; %bb.0:
 ; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, s4, v1, v1, v0
 ; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, vcc_lo, v0, v1, v0
 ; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 3
 ; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
 ; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
 ; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
-; GFX10-FLUSH-NEXT:    v_fma_f32 v6, v5, -v2, v4
+; GFX10-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
 ; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
-; GFX10-FLUSH-NEXT:    v_fmac_f32_e64 v4, -v2, v5
+; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 0
-; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v4, v3, v5
+; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
 ; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
 ; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
   %fdiv = fdiv float %a, %b
   ret float %fdiv
 }
 
 define float @v_fdiv_f32_afn(float %a, float %b) {
 ; GCN-LABEL: v_fdiv_f32_afn:

 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v1, v1, v0
 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
 ; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
-; GFX10-IEEE-NEXT:    v_fma_f32 v6, v4, -v2, v5
+; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
-; GFX10-IEEE-NEXT:    v_fmac_f32_e64 v5, -v2, v4
-; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v5, v3, v4
+; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
+; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-FLUSH-LABEL: v_fdiv_f32_ulp25:
 ; GFX10-FLUSH:       ; %bb.0:
 ; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-FLUSH-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|

 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v1, s4, v0, v0, 1.0
 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
 ; GFX10-IEEE-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v2, v3, v2
 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v3, v4, v2
-; GFX10-IEEE-NEXT:    v_fma_f32 v5, v3, -v1, v4
+; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v1, v3, v4
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v5, v2
-; GFX10-IEEE-NEXT:    v_fmac_f32_e64 v4, -v1, v3
-; GFX10-IEEE-NEXT:    v_div_fmas_f32 v1, v4, v2, v3
+; GFX10-IEEE-NEXT:    v_fma_f32 v1, -v1, v3, v4
+; GFX10-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v3
 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-FLUSH-LABEL: v_rcp_f32:
 ; GFX10-FLUSH:       ; %bb.0:
 ; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-FLUSH-NEXT:    v_div_scale_f32 v1, s4, v0, v0, 1.0
 ; GFX10-FLUSH-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
 ; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v2, v1
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 3
 ; GFX10-FLUSH-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
 ; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v2, v4, v2
 ; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v4, v3, v2
-; GFX10-FLUSH-NEXT:    v_fma_f32 v5, v4, -v1, v3
+; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v1, v4, v3
 ; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v4, v5, v2
-; GFX10-FLUSH-NEXT:    v_fmac_f32_e64 v3, -v1, v4
+; GFX10-FLUSH-NEXT:    v_fma_f32 v1, -v1, v4, v3
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 0
-; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v1, v3, v2, v4
+; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
 ; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
 ; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
   %fdiv = fdiv float 1.0, %x
   ret float %fdiv
 }
 
 define float @v_rcp_f32_arcp(float %x) {
 ; GFX6-IEEE-LABEL: v_rcp_f32_arcp:

 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v1, s4, v0, v0, 1.0
 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
 ; GFX10-IEEE-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v2, v3, v2
 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v3, v4, v2
-; GFX10-IEEE-NEXT:    v_fma_f32 v5, v3, -v1, v4
+; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v1, v3, v4
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v5, v2
-; GFX10-IEEE-NEXT:    v_fmac_f32_e64 v4, -v1, v3
-; GFX10-IEEE-NEXT:    v_div_fmas_f32 v1, v4, v2, v3
+; GFX10-IEEE-NEXT:    v_fma_f32 v1, -v1, v3, v4
+; GFX10-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v3
 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-FLUSH-LABEL: v_rcp_f32_arcp:
 ; GFX10-FLUSH:       ; %bb.0:
 ; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-FLUSH-NEXT:    v_div_scale_f32 v1, s4, v0, v0, 1.0
 ; GFX10-FLUSH-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
 ; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v2, v1
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 3
 ; GFX10-FLUSH-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
 ; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v2, v4, v2
 ; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v4, v3, v2
-; GFX10-FLUSH-NEXT:    v_fma_f32 v5, v4, -v1, v3
+; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v1, v4, v3
 ; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v4, v5, v2
-; GFX10-FLUSH-NEXT:    v_fmac_f32_e64 v3, -v1, v4
+; GFX10-FLUSH-NEXT:    v_fma_f32 v1, -v1, v4, v3
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 0
-; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v1, v3, v2, v4
+; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
 ; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
 ; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
   %fdiv = fdiv arcp float 1.0, %x
   ret float %fdiv
 }
 
 define float @v_rcp_f32_arcp_afn(float %x) {
 ; GCN-LABEL: v_rcp_f32_arcp_afn:

 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v1, v1, v0
 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
 ; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
-; GFX10-IEEE-NEXT:    v_fma_f32 v6, v4, -v2, v5
+; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
-; GFX10-IEEE-NEXT:    v_fmac_f32_e64 v5, -v2, v4
-; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v5, v3, v4
+; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
+; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-FLUSH-LABEL: v_fdiv_f32_arcp_ulp25:
 ; GFX10-FLUSH:       ; %bb.0:
 ; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-FLUSH-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|

 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
 ; GFX10-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
 ; GFX10-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v6, v8, v6
 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, s4, v1, v3, v1
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v9, v7
 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
-; GFX10-IEEE-NEXT:    v_fma_f32 v12, v9, -v4, v10
-; GFX10-IEEE-NEXT:    v_fma_f32 v13, v11, -v5, v8
+; GFX10-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
+; GFX10-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
-; GFX10-IEEE-NEXT:    v_fmac_f32_e64 v10, -v4, v9
-; GFX10-IEEE-NEXT:    v_fmac_f32_e64 v8, -v5, v11
-; GFX10-IEEE-NEXT:    v_div_fmas_f32 v4, v10, v6, v9
+; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
+; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
+; GFX10-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
 ; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
-; GFX10-IEEE-NEXT:    v_div_fmas_f32 v5, v8, v7, v11
+; GFX10-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-FLUSH-LABEL: v_fdiv_v2f32:
 ; GFX10-FLUSH:       ; %bb.0:
 ; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, s4, v2, v2, v0
 ; GFX10-FLUSH-NEXT:    v_div_scale_f32 v6, vcc_lo, v0, v2, v0
 ; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v5, v4
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 3
 ; GFX10-FLUSH-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
 ; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v7, v5
 ; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v7, v6, v5
-; GFX10-FLUSH-NEXT:    v_fma_f32 v8, v7, -v4, v6
+; GFX10-FLUSH-NEXT:    v_fma_f32 v8, -v4, v7, v6
 ; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v7, v8, v5
-; GFX10-FLUSH-NEXT:    v_fmac_f32_e64 v6, -v4, v7
+; GFX10-FLUSH-NEXT:    v_fma_f32 v4, -v4, v7, v6
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 0
-; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, s4, v3, v3, v1
-; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v5, v6, v5, v7
-; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v6, v4
-; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v5, v2, v0
+; GFX10-FLUSH-NEXT:    v_div_scale_f32 v6, s4, v3, v3, v1
+; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
+; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v5, v6
+; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
 ; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, vcc_lo, v1, v3, v1
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 3
-; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v4, v6, 1.0
-; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v6, v5, v6
-; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v6
-; GFX10-FLUSH-NEXT:    v_fma_f32 v7, v5, -v4, v2
-; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v7, v6
-; GFX10-FLUSH-NEXT:    v_fmac_f32_e64 v2, -v4, v5
+; GFX10-FLUSH-NEXT:    v_fma_f32 v4, -v6, v5, 1.0
+; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v4, v5
+; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v4, v2, v5
+; GFX10-FLUSH-NEXT:    v_fma_f32 v7, -v6, v4, v2
+; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v4, v7, v5
+; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v6, v4, v2
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 0
-; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v6, v5
+; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v5, v4
 ; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
 ; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
   %fdiv = fdiv <2 x float> %a, %b
   ret <2 x float> %fdiv
 }
 
 define <2 x float> @v_fdiv_v2f32_afn(<2 x float> %a, <2 x float> %b) {
 ; GCN-LABEL: v_fdiv_v2f32_afn:

 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
 ; GFX10-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
 ; GFX10-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v6, v8, v6
 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, s4, v1, v3, v1
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v9, v7
 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
-; GFX10-IEEE-NEXT:    v_fma_f32 v12, v9, -v4, v10
-; GFX10-IEEE-NEXT:    v_fma_f32 v13, v11, -v5, v8
+; GFX10-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
+; GFX10-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
-; GFX10-IEEE-NEXT:    v_fmac_f32_e64 v10, -v4, v9
-; GFX10-IEEE-NEXT:    v_fmac_f32_e64 v8, -v5, v11
-; GFX10-IEEE-NEXT:    v_div_fmas_f32 v4, v10, v6, v9
+; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
+; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
+; GFX10-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
 ; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
-; GFX10-IEEE-NEXT:    v_div_fmas_f32 v5, v8, v7, v11
+; GFX10-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-FLUSH-LABEL: v_fdiv_v2f32_ulp25:
 ; GFX10-FLUSH:       ; %bb.0:
 ; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0

 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v5, v3
 ; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
 ; GFX10-IEEE-NEXT:    v_fma_f32 v7, -v3, v5, 1.0
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v4
 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v6, s4, 1.0, v1, 1.0
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v5, v7, v5
 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v7, v8, v4
 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v6, v5
-; GFX10-IEEE-NEXT:    v_fma_f32 v10, v7, -v2, v8
-; GFX10-IEEE-NEXT:    v_fma_f32 v11, v9, -v3, v6
+; GFX10-IEEE-NEXT:    v_fma_f32 v10, -v2, v7, v8
+; GFX10-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v6
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v10, v4
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v11, v5
-; GFX10-IEEE-NEXT:    v_fmac_f32_e64 v8, -v2, v7
-; GFX10-IEEE-NEXT:    v_fmac_f32_e64 v6, -v3, v9
-; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v8, v4, v7
+; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v7, v8
+; GFX10-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v6
+; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v7
 ; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
-; GFX10-IEEE-NEXT:    v_div_fmas_f32 v3, v6, v5, v9
+; GFX10-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v9
 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-FLUSH-LABEL: v_rcp_v2f32:
 ; GFX10-FLUSH:       ; %bb.0:
 ; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, s4, v0, v0, 1.0
 ; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
 ; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 3
 ; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
 ; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
 ; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
-; GFX10-FLUSH-NEXT:    v_fma_f32 v6, v5, -v2, v4
+; GFX10-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
 ; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
-; GFX10-FLUSH-NEXT:    v_fmac_f32_e64 v4, -v2, v5
+; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 0
-; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, s4, v1, v1, 1.0
-; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v3, v4, v3, v5
-; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v4, v2
-; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v3, v0, 1.0
-; GFX10-FLUSH-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
+; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, s4, v1, v1, 1.0
+; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v4
+; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
+; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 3
-; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
-; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v4, v5, v4
-; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v3, v4
-; GFX10-FLUSH-NEXT:    v_fma_f32 v6, v5, -v2, v3
-; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v4
-; GFX10-FLUSH-NEXT:    v_fmac_f32_e64 v3, -v2, v5
+; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v4, v3, 1.0
+; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
+; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v3
+; GFX10-FLUSH-NEXT:    v_fma_f32 v6, -v4, v5, v2
+; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
+; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v4, v5, v2
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 0
-; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v3, v4, v5
+; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
 ; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
 ; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
   %fdiv = fdiv <2 x float> <float 1.0, float 1.0>, %x
   ret <2 x float> %fdiv
 }
 
 define <2 x float> @v_rcp_v2f32_arcp(<2 x float> %x) {
 ; GFX6-IEEE-LABEL: v_rcp_v2f32_arcp:

 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v5, v3
 ; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
 ; GFX10-IEEE-NEXT:    v_fma_f32 v7, -v3, v5, 1.0
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v4
 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v6, s4, 1.0, v1, 1.0
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v5, v7, v5
 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v7, v8, v4
 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v6, v5
-; GFX10-IEEE-NEXT:    v_fma_f32 v10, v7, -v2, v8
-; GFX10-IEEE-NEXT:    v_fma_f32 v11, v9, -v3, v6
+; GFX10-IEEE-NEXT:    v_fma_f32 v10, -v2, v7, v8
+; GFX10-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v6
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v10, v4
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v11, v5
-; GFX10-IEEE-NEXT:    v_fmac_f32_e64 v8, -v2, v7
-; GFX10-IEEE-NEXT:    v_fmac_f32_e64 v6, -v3, v9
-; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v8, v4, v7
+; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v7, v8
+; GFX10-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v6
+; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v7
 ; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
-; GFX10-IEEE-NEXT:    v_div_fmas_f32 v3, v6, v5, v9
+; GFX10-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v9
 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-FLUSH-LABEL: v_rcp_v2f32_arcp:
 ; GFX10-FLUSH:       ; %bb.0:
 ; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, s4, v0, v0, 1.0
 ; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
 ; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 3
 ; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
 ; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
 ; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
-; GFX10-FLUSH-NEXT:    v_fma_f32 v6, v5, -v2, v4
+; GFX10-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
 ; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
-; GFX10-FLUSH-NEXT:    v_fmac_f32_e64 v4, -v2, v5
+; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 0
-; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, s4, v1, v1, 1.0
-; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v3, v4, v3, v5
-; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v4, v2
-; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v3, v0, 1.0
-; GFX10-FLUSH-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
+; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, s4, v1, v1, 1.0
+; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v4
+; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
+; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 3
-; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
-; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v4, v5, v4
-; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v3, v4
-; GFX10-FLUSH-NEXT:    v_fma_f32 v6, v5, -v2, v3
-; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v4
-; GFX10-FLUSH-NEXT:    v_fmac_f32_e64 v3, -v2, v5
+; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v4, v3, 1.0
+; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
+; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v3
+; GFX10-FLUSH-NEXT:    v_fma_f32 v6, -v4, v5, v2
+; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
+; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v4, v5, v2
 ; GFX10-FLUSH-NEXT:    s_denorm_mode 0
-; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v3, v4, v5
+; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
 ; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
 ; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
   %fdiv = fdiv arcp <2 x float> <float 1.0, float 1.0>, %x
   ret <2 x float> %fdiv
 }
 
 define <2 x float> @v_rcp_v2f32_arcp_afn(<2 x float> %x) {
 ; GCN-LABEL: v_rcp_v2f32_arcp_afn:

 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
 ; GFX10-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
 ; GFX10-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v6, v8, v6
 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, s4, v1, v3, v1
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v9, v7
 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
-; GFX10-IEEE-NEXT:    v_fma_f32 v12, v9, -v4, v10
-; GFX10-IEEE-NEXT:    v_fma_f32 v13, v11, -v5, v8
+; GFX10-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
+; GFX10-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
-; GFX10-IEEE-NEXT:    v_fmac_f32_e64 v10, -v4, v9
-; GFX10-IEEE-NEXT:    v_fmac_f32_e64 v8, -v5, v11
-; GFX10-IEEE-NEXT:    v_div_fmas_f32 v4, v10, v6, v9
+; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
+; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
+; GFX10-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
 ; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
-; GFX10-IEEE-NEXT:    v_div_fmas_f32 v5, v8, v7, v11
+; GFX10-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25:
 ; GFX10-FLUSH:       ; %bb.0:
 ; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0

llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_fma_f32 v0, |v0|, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_fma_f32_fabs_lhs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_fma_f32 v0, v1, |v0|, v2
+; GFX10-NEXT:    v_fma_f32 v0, |v0|, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %fabs.x = call float @llvm.fabs.f32(float %x)
   %fma = call float @llvm.fma.f32(float %fabs.x, float %y, float %z)
   ret float %fma
 }
 
 define float @v_fma_f32_fabs_rhs(float %x, float %y, float %z) {
 ; GFX6-LABEL: v_fma_f32_fabs_rhs:

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_fma_f32 v0, v0, |v1|, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_fma_f32_fabs_rhs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_fma_f32 v0, |v1|, v0, v2
+; GFX10-NEXT:    v_fma_f32 v0, v0, |v1|, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %fabs.y = call float @llvm.fabs.f32(float %y)
   %fma = call float @llvm.fma.f32(float %x, float %fabs.y, float %z)
   ret float %fma
 }
 
 define float @v_fma_f32_fabs_lhs_rhs(float %x, float %y, float %z) {
 ; GFX6-LABEL: v_fma_f32_fabs_lhs_rhs:

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_fma_f32 v0, |v0|, |v1|, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_fma_f32_fabs_lhs_rhs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_fma_f32 v0, |v1|, |v0|, v2
+; GFX10-NEXT:    v_fma_f32 v0, |v0|, |v1|, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %fabs.x = call float @llvm.fabs.f32(float %x)
   %fabs.y = call float @llvm.fabs.f32(float %y)
   %fma = call float @llvm.fma.f32(float %fabs.x, float %fabs.y, float %z)
   ret float %fma
 }
 
 define amdgpu_ps float @v_fma_f32_sgpr_vgpr_vgpr(float inreg %x, float %y, float %z) {

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_fma_f32 v0, -v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_fma_f32_fneg_lhs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_fma_f32 v0, v1, -v0, v2
+; GFX10-NEXT:    v_fma_f32 v0, -v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %neg.x = fneg float %x
   %fma = call float @llvm.fma.f32(float %neg.x, float %y, float %z)
   ret float %fma
 }
 
 define float @v_fma_f32_fneg_rhs(float %x, float %y, float %z) {
 ; GFX6-LABEL: v_fma_f32_fneg_rhs:

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_fma_f32 v0, v0, -v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_fma_f32_fneg_rhs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_fma_f32 v0, -v1, v0, v2
+; GFX10-NEXT:    v_fma_f32 v0, v0, -v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %neg.y = fneg float %y
   %fma = call float @llvm.fma.f32(float %x, float %neg.y, float %z)
   ret float %fma
 }
 
 define float @v_fma_f32_fneg_z(float %x, float %y, float %z) {
 ; GFX6-LABEL: v_fma_f32_fneg_z:

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir

bb.0:
     ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
     ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
     ; GFX6-NEXT: %4:vgpr_32 = nofpexcept V_FMA_F32_e64 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
     ; GFX6-NEXT: S_ENDPGM 0, implicit %4
     ; GFX9-DL-LABEL: name: fma_f32_fneg_src0
     ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX9-DL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
     ; GFX9-DL-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-    ; GFX9-DL-NEXT: %4:vgpr_32 = nofpexcept V_FMAC_F32_e64 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
+    ; GFX9-DL-NEXT: %4:vgpr_32 = nofpexcept V_FMA_F32_e64 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
     ; GFX9-DL-NEXT: S_ENDPGM 0, implicit %4
     ; GFX10-LABEL: name: fma_f32_fneg_src0
     ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
     ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-    ; GFX10-NEXT: %4:vgpr_32 = nofpexcept V_FMAC_F32_e64 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
+    ; GFX10-NEXT: %4:vgpr_32 = nofpexcept V_FMA_F32_e64 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
     ; GFX10-NEXT: S_ENDPGM 0, implicit %4
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = COPY $vgpr1
     %2:vgpr(s32) = COPY $vgpr2
     %3:vgpr(s32) = G_FNEG %0
     %4:vgpr(s32) = G_FMA %3, %1, %2
     S_ENDPGM 0, implicit %4
 
bb.0:
     ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
     ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
     ; GFX6-NEXT: %4:vgpr_32 = nofpexcept V_FMA_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
     ; GFX6-NEXT: S_ENDPGM 0, implicit %4
     ; GFX9-DL-LABEL: name: fma_f32_fneg_src1
     ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX9-DL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
     ; GFX9-DL-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-    ; GFX9-DL-NEXT: %4:vgpr_32 = nofpexcept V_FMAC_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
+    ; GFX9-DL-NEXT: %4:vgpr_32 = nofpexcept V_FMA_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
     ; GFX9-DL-NEXT: S_ENDPGM 0, implicit %4
     ; GFX10-LABEL: name: fma_f32_fneg_src1
     ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
     ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-    ; GFX10-NEXT: %4:vgpr_32 = nofpexcept V_FMAC_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
+    ; GFX10-NEXT: %4:vgpr_32 = nofpexcept V_FMA_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
     ; GFX10-NEXT: S_ENDPGM 0, implicit %4
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = COPY $vgpr1
     %2:vgpr(s32) = COPY $vgpr2
     %3:vgpr(s32) = G_FNEG %1
     %4:vgpr(s32) = G_FMA %0, %3, %2
     S_ENDPGM 0, implicit %4
 

llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll

 ; GCN-NEXT:    s_waitcnt vmcnt(2)
 ; GCN-NEXT:    v_mad_f32 v10, s2, v6, v2
 ; GCN-NEXT:    v_mul_f32_e32 v8, s18, v2
 ; GCN-NEXT:    s_waitcnt vmcnt(1)
 ; GCN-NEXT:    v_mul_f32_e32 v3, s22, v3
 ; GCN-NEXT:    v_mac_f32_e32 v10, v7, v6
 ; GCN-NEXT:    v_mul_f32_e32 v1, v8, v6
 ; GCN-NEXT:    v_mul_f32_e32 v7, v6, v3
-; GCN-NEXT:    v_fmac_f32_e64 v9, -v6, v3
+; GCN-NEXT:    v_fma_f32 v3, -v6, v3, v9
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_add_f32_e32 v3, v4, v10
+; GCN-NEXT:    v_add_f32_e32 v4, v4, v10
 ; GCN-NEXT:    v_fma_f32 v0, v2, s26, -v1
+; GCN-NEXT:    v_fmac_f32_e32 v7, v3, v6
+; GCN-NEXT:    v_mul_f32_e32 v3, v4, v6
 ; GCN-NEXT:    v_fma_f32 v4, v5, s0, 0x3ca3d70a
-; GCN-NEXT:    v_fmac_f32_e32 v7, v9, v6
-; GCN-NEXT:    v_mul_f32_e32 v3, v3, v6
 ; GCN-NEXT:    v_fmac_f32_e32 v1, v0, v6
 ; GCN-NEXT:    v_mul_f32_e32 v0, v2, v6
 ; GCN-NEXT:    v_mul_f32_e32 v2, v7, v4
 ; GCN-NEXT:    v_mul_f32_e32 v1, v3, v1
 ; GCN-NEXT:    v_fmac_f32_e32 v1, v2, v0
 ; GCN-NEXT:    v_max_f32_e32 v0, 0, v1
 ; GCN-NEXT:    ; return to shader part epilog
 .entry:

llvm/test/CodeGen/AMDGPU/fdiv.ll

 ; PREGFX10: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]]
 ; PREGFX10-NOT: s_setreg
 
 ; GFX10-NOT: s_denorm_mode
 ; GFX10: v_fma_f32 [[A:v[0-9]+]], -[[NUM_SCALE]], [[NUM_RCP]], 1.0
 ; GFX10: v_fmac_f32_e32 [[B:v[0-9]+]], [[A]], [[NUM_RCP]]
 ; GFX10: v_div_scale_f32 [[DEN_SCALE:v[0-9]+]]
 ; GFX10: v_mul_f32_e32 [[C:v[0-9]+]], [[DEN_SCALE]], [[B]]
-; GFX10: v_fma_f32 [[D:v[0-9]+]], [[C]], -[[NUM_SCALE]], [[DEN_SCALE]]
+; GFX10: v_fma_f32 [[D:v[0-9]+]], -[[NUM_SCALE]], [[C]], [[DEN_SCALE]]
 ; GFX10: v_fmac_f32_e32 [[E:v[0-9]+]], [[D]], [[B]]
-; GFX10: v_fmac_f32_e64 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]]
+; GFX10: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]]
 ; GFX10-NOT: s_denorm_mode
 
 ; GCN: v_div_fmas_f32 [[FMAS:v[0-9]+]], [[F]], [[B]], [[E]]
 ; GCN: v_div_fixup_f32 v{{[0-9]+}}, [[FMAS]],
 define amdgpu_kernel void @fdiv_f32_denormals(float addrspace(1)* %out, float %a, float %b) #2 {
 entry:
   %fdiv = fdiv float %a, %b
   store float %fdiv, float addrspace(1)* %out

 ; PREGFX10: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]]
 ; PREGFX10-NOT: s_setreg
 
 ; GFX10-NOT: s_denorm_mode
 ; GFX10: v_fma_f32 [[A:v[0-9]+]], -[[NUM_SCALE]], [[NUM_RCP]], 1.0
 ; GFX10: v_fmac_f32_e32 [[B:v[0-9]+]], [[A]], [[NUM_RCP]]
 ; GFX10: v_div_scale_f32 [[DEN_SCALE:v[0-9]+]]
 ; GFX10: v_mul_f32_e32 [[C:v[0-9]+]], [[DEN_SCALE]], [[B]]
-; GFX10: v_fma_f32 [[D:v[0-9]+]], [[C]], -[[NUM_SCALE]], [[DEN_SCALE]]
+; GFX10: v_fma_f32 [[D:v[0-9]+]], -[[NUM_SCALE]], [[C]], [[DEN_SCALE]]
 ; GFX10: v_fmac_f32_e32 [[E:v[0-9]+]], [[D]], [[B]]
-; GFX10: v_fmac_f32_e64 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]]
+; GFX10: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]]
 ; GFX10-NOT: s_denorm_mode
 
 ; GCN: v_div_fmas_f32 [[FMAS:v[0-9]+]], [[F]], [[B]], [[E]]
 ; GCN: v_div_fixup_f32 v{{[0-9]+}}, [[FMAS]],
 define amdgpu_kernel void @fdiv_f32_denorms_correctly_rounded_divide_sqrt(float addrspace(1)* %out, float %a) #2 {
 entry:
   %fdiv = fdiv float 1.000000e+00, %a
   store float %fdiv, float addrspace(1)* %out
   ret void
 }
 
 attributes #0 = { nounwind "enable-unsafe-fp-math"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "target-features"="-flat-for-global" }
 attributes #1 = { nounwind "enable-unsafe-fp-math"="true" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "target-features"="-flat-for-global" }
 attributes #2 = { nounwind "enable-unsafe-fp-math"="false" "denormal-fp-math-f32"="ieee,ieee" "target-features"="-flat-for-global" }
 
 !0 = !{float 2.500000e+00}

llvm/test/CodeGen/AMDGPU/fma.f64.ll

-; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=gfx90a -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GFX90A -check-prefix=FUNC %s
+; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,SI %s
+; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,SI %s
+; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=gfx90a -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX90A %s
 
 declare double @llvm.fma.f64(double, double, double) nounwind readnone
 declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) nounwind readnone
 declare <4 x double> @llvm.fma.v4f64(<4 x double>, <4 x double>, <4 x double>) nounwind readnone
 declare double @llvm.fabs.f64(double) nounwind readnone
 
 ; FUNC-LABEL: {{^}}fma_f64:
 ; SI: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @fma_v4f64(<4 x double> addrspace(1)* %out, <4 x double> addrspace(1)* %in1,
    %r1 = load <4 x double>, <4 x double> addrspace(1)* %in2
    %r2 = load <4 x double>, <4 x double> addrspace(1)* %in3
    %r3 = tail call <4 x double> @llvm.fma.v4f64(<4 x double> %r0, <4 x double> %r1, <4 x double> %r2)
    store <4 x double> %r3, <4 x double> addrspace(1)* %out
    ret void
 }
 
 ; FUNC-LABEL: {{^}}fma_f64_abs_src0:
-; SI: v_fma_f64 {{v\[[0-9]+:[0-9]+\], |v\[[0-9]+:[0-9]+\]|, v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
-; GFX90A: v_fmac_f64_e64 {{v\[[0-9]+:[0-9]+\], |v\[[0-9]+:[0-9]+\]|, v\[[0-9]+:[0-9]+\]}}
+; GCN: v_fma_f64 {{v\[[0-9]+:[0-9]+\], |v\[[0-9]+:[0-9]+\]|, v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
 define amdgpu_kernel void @fma_f64_abs_src0(double addrspace(1)* %out, double addrspace(1)* %in1,
                      double addrspace(1)* %in2, double addrspace(1)* %in3) {
    %r0 = load double, double addrspace(1)* %in1
    %r1 = load double, double addrspace(1)* %in2
    %r2 = load double, double addrspace(1)* %in3
    %fabs = call double @llvm.fabs.f64(double %r0)
    %r3 = tail call double @llvm.fma.f64(double %fabs, double %r1, double %r2)
    store double %r3, double addrspace(1)* %out
    ret void
 }
 
 ; FUNC-LABEL: {{^}}fma_f64_abs_src1:
-; SI: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], \|v\[[0-9]+:[0-9]+\]\|, v\[[0-9]+:[0-9]+\]}}
-; GFX90A: v_fmac_f64_e64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], \|v\[[0-9]+:[0-9]+\]\|}}
+; GCN: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], \|v\[[0-9]+:[0-9]+\]\|, v\[[0-9]+:[0-9]+\]}}
 define amdgpu_kernel void @fma_f64_abs_src1(double addrspace(1)* %out, double addrspace(1)* %in1,
                      double addrspace(1)* %in2, double addrspace(1)* %in3) {
    %r0 = load double, double addrspace(1)* %in1
    %r1 = load double, double addrspace(1)* %in2
    %r2 = load double, double addrspace(1)* %in3
    %fabs = call double @llvm.fabs.f64(double %r1)
    %r3 = tail call double @llvm.fma.f64(double %r0, double %fabs, double %r2)
    store double %r3, double addrspace(1)* %out
define amdgpu_kernel void @fma_f64_abs_src2(double addrspace(1)* %out, double addrspace(1)* %in1,
    %r2 = load double, double addrspace(1)* %in3
    %fabs = call double @llvm.fabs.f64(double %r2)
    %r3 = tail call double @llvm.fma.f64(double %r0, double %r1, double %fabs)
    store double %r3, double addrspace(1)* %out
    ret void
 }
 
 ; FUNC-LABEL: {{^}}fma_f64_neg_src0:
-; SI: v_fma_f64 {{v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
-; GFX90A: v_fmac_f64_e64 {{v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
+; GCN: v_fma_f64 {{v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
 define amdgpu_kernel void @fma_f64_neg_src0(double addrspace(1)* %out, double addrspace(1)* %in1,
                      double addrspace(1)* %in2, double addrspace(1)* %in3) {
    %r0 = load double, double addrspace(1)* %in1
    %r1 = load double, double addrspace(1)* %in2
    %r2 = load double, double addrspace(1)* %in3
    %fsub = fsub double -0.000000e+00, %r0
    %r3 = tail call double @llvm.fma.f64(double %fsub, double %r1, double %r2)
    store double %r3, double addrspace(1)* %out
    ret void
 }
 
 ; FUNC-LABEL: {{^}}fma_f64_neg_src1:
-; SI: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
-; GFX90A: v_fmac_f64_e64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
+; GCN: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
 define amdgpu_kernel void @fma_f64_neg_src1(double addrspace(1)* %out, double addrspace(1)* %in1,
                      double addrspace(1)* %in2, double addrspace(1)* %in3) {
    %r0 = load double, double addrspace(1)* %in1
    %r1 = load double, double addrspace(1)* %in2
    %r2 = load double, double addrspace(1)* %in3
    %fsub = fsub double -0.000000e+00, %r1
    %r3 = tail call double @llvm.fma.f64(double %r0, double %fsub, double %r2)
    store double %r3, double addrspace(1)* %out
define amdgpu_kernel void @fma_f64_neg_src2(double addrspace(1)* %out, double addrspace(1)* %in1,
    %r2 = load double, double addrspace(1)* %in3
    %fsub = fsub double -0.000000e+00, %r2
    %r3 = tail call double @llvm.fma.f64(double %r0, double %r1, double %fsub)
    store double %r3, double addrspace(1)* %out
    ret void
 }
 
 ; FUNC-LABEL: {{^}}fma_f64_abs_neg_src0:
-; SI: v_fma_f64 {{v\[[0-9]+:[0-9]+\], -\|v\[[0-9]+:[0-9]+\]\|, v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
-; GFX90A: v_fmac_f64_e64 {{v\[[0-9]+:[0-9]+\], -\|v\[[0-9]+:[0-9]+\]\|, v\[[0-9]+:[0-9]+\]}}
+; GCN: v_fma_f64 {{v\[[0-9]+:[0-9]+\], -\|v\[[0-9]+:[0-9]+\]\|, v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
 define amdgpu_kernel void @fma_f64_abs_neg_src0(double addrspace(1)* %out, double addrspace(1)* %in1,
                      double addrspace(1)* %in2, double addrspace(1)* %in3) {
    %r0 = load double, double addrspace(1)* %in1
    %r1 = load double, double addrspace(1)* %in2
    %r2 = load double, double addrspace(1)* %in3
    %fabs = call double @llvm.fabs.f64(double %r0)
    %fsub = fsub double -0.000000e+00, %fabs
    %r3 = tail call double @llvm.fma.f64(double %fsub, double %r1, double %r2)
    store double %r3, double addrspace(1)* %out
    ret void
 }
 
 ; FUNC-LABEL: {{^}}fma_f64_abs_neg_src1:
-; SI: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -\|v\[[0-9]+:[0-9]+\]\|, v\[[0-9]+:[0-9]+\]}}
-; GFX90A: v_fmac_f64_e64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -\|v\[[0-9]+:[0-9]+\]\|}}
+; GCN: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -\|v\[[0-9]+:[0-9]+\]\|, v\[[0-9]+:[0-9]+\]}}
 define amdgpu_kernel void @fma_f64_abs_neg_src1(double addrspace(1)* %out, double addrspace(1)* %in1,
                      double addrspace(1)* %in2, double addrspace(1)* %in3) {
    %r0 = load double, double addrspace(1)* %in1
    %r1 = load double, double addrspace(1)* %in2
    %r2 = load double, double addrspace(1)* %in3
    %fabs = call double @llvm.fabs.f64(double %r1)
    %fsub = fsub double -0.000000e+00, %fabs
    %r3 = tail call double @llvm.fma.f64(double %r0, double %fsub, double %r2)

llvm/test/CodeGen/AMDGPU/fmad-formation-fmul-distribute-denormal-mode.ll

 ; NOFUSE-NEXT:    v_sub_f32_e32 v1, 1.0, v1
 ; NOFUSE-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; NOFUSE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; FMAGFX10-LABEL: unsafe_fmul_fsub_distribute_fast_f32:
 ; FMAGFX10:       ; %bb.0:
 ; FMAGFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; FMAGFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; FMAGFX10-NEXT:    v_fmac_f32_e64 v0, -v1, v0
+; FMAGFX10-NEXT:    v_fma_f32 v0, -v1, v0, v0
 ; FMAGFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; FMAD-LABEL: unsafe_fmul_fsub_distribute_fast_f32:
 ; FMAD:       ; %bb.0:
 ; FMAD-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; FMAD-NEXT:    v_mad_f32 v0, -v1, v0, v0
 ; FMAD-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; FMADGFX10-LABEL: unsafe_fmul_fsub_distribute_fast_f32:
 ; FMADGFX10:       ; %bb.0:
 ; FMADGFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; FMADGFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; FMADGFX10-NEXT:    v_fmac_f32_e64 v0, -v1, v0
+; FMADGFX10-NEXT:    v_fma_f32 v0, -v1, v0, v0
 ; FMADGFX10-NEXT:    s_setpc_b64 s[30:31]
   %add = fsub fast float 1.0, %arg1
   %tmp1 = fmul fast float %arg0, %add
   ret float %tmp1
 }
 
 define <2 x float> @unsafe_fmul_fadd_distribute_fast_v2f32(<2 x float> %arg0, <2 x float> %arg1) #0 {
 ; FMA-LABEL: unsafe_fmul_fadd_distribute_fast_v2f32:

 ; NOFUSE-NEXT:    v_mul_f32_e32 v0, v0, v2
 ; NOFUSE-NEXT:    v_mul_f32_e32 v1, v1, v3
 ; NOFUSE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; FMAGFX10-LABEL: unsafe_fmul_fsub_distribute_fast_v2f32:
 ; FMAGFX10:       ; %bb.0:
 ; FMAGFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; FMAGFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; FMAGFX10-NEXT:    v_fmac_f32_e64 v0, -v2, v0
-; FMAGFX10-NEXT:    v_fmac_f32_e64 v1, -v3, v1
+; FMAGFX10-NEXT:    v_fma_f32 v0, -v2, v0, v0
+; FMAGFX10-NEXT:    v_fma_f32 v1, -v3, v1, v1
 ; FMAGFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; FMAD-LABEL: unsafe_fmul_fsub_distribute_fast_v2f32:
 ; FMAD:       ; %bb.0:
 ; FMAD-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; FMAD-NEXT:    v_mad_f32 v0, -v2, v0, v0
 ; FMAD-NEXT:    v_mad_f32 v1, -v3, v1, v1
 ; FMAD-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; FMADGFX10-LABEL: unsafe_fmul_fsub_distribute_fast_v2f32:
 ; FMADGFX10:       ; %bb.0:
 ; FMADGFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; FMADGFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; FMADGFX10-NEXT:    v_fmac_f32_e64 v0, -v2, v0
-; FMADGFX10-NEXT:    v_fmac_f32_e64 v1, -v3, v1
+; FMADGFX10-NEXT:    v_fma_f32 v0, -v2, v0, v0
+; FMADGFX10-NEXT:    v_fma_f32 v1, -v3, v1, v1
 ; FMADGFX10-NEXT:    s_setpc_b64 s[30:31]
   %add = fsub  fast <2 x float> <float 1.0, float 1.0>, %arg1
   %tmp1 = fmul fast <2 x float> %arg0, %add
   ret <2 x float> %tmp1
 }
 
 define <2 x float> @unsafe_fast_fmul_fadd_distribute_post_legalize_f32(float %arg0, <2 x float> %arg1) #0 {
 ; FMA-LABEL: unsafe_fast_fmul_fadd_distribute_post_legalize_f32:

 ; NOFUSE-NEXT:    v_sub_f32_e32 v0, 1.0, v0
 ; NOFUSE-NEXT:    v_mul_f32_e32 v0, v1, v0
 ; NOFUSE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; FMAGFX10-LABEL: unsafe_fast_fmul_fsub_ditribute_post_legalize:
 ; FMAGFX10:       ; %bb.0:
 ; FMAGFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; FMAGFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; FMAGFX10-NEXT:    v_fma_f32 v0, v1, -v0, v1
+; FMAGFX10-NEXT:    v_fma_f32 v0, -v0, v1, v1
 ; FMAGFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; FMAD-LABEL: unsafe_fast_fmul_fsub_ditribute_post_legalize:
 ; FMAD:       ; %bb.0:
 ; FMAD-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; FMAD-NEXT:    v_mad_f32 v0, -v0, v1, v1
 ; FMAD-NEXT:    s_setpc_b64 s[30:31]
 ;

llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll

 }
 
 ; GCN-LABEL: {{^}}mad_sub_inv_f16:
 ; GCN: {{buffer|flat|global}}_load_ushort [[REGA:v[0-9]+]]
 ; GCN: {{buffer|flat|global}}_load_ushort [[REGB:v[0-9]+]]
 ; GCN: {{buffer|flat|global}}_load_ushort [[REGC:v[0-9]+]]
 ; VI-FLUSH: v_mad_f16 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], [[REGC]]
 
-; VI-DENORM-CONTRACT:    v_fma_f16 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], [[REGC]]
-; GFX10-DENORM-CONTRACT: v_fmac_f16_e64 [[REGC]], -[[REGA]], [[REGB]]
+; GCN-DENORM-CONTRACT: v_fma_f16 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], [[REGC]]
 
 ; GCN-DENORM-STRICT: v_mul_f16_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
 ; GCN-DENORM-STRICT: v_sub_f16_e32 [[RESULT:v[0-9]+]], [[REGC]], [[TMP]]
 
 ; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
 
 ; GFX10-FLUSH: v_mul_f16_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
 ; GFX10-FLUSH: v_sub_f16_e32 [[RESULT:v[0-9]+]], [[REGC]], [[TMP]]
-; GFX10-FLUSH:  global_store_short v{{[0-9]+}}, [[RESULT]]
-; GFX10-DENORM-STRICT: global_store_short v{{[0-9]+}}, [[RESULT]]
-; GFX10-DENORM-CONTRACT: global_store_short v{{[0-9]+}}, [[REGC]]
+; GFX10: global_store_short v{{[0-9]+}}, [[RESULT]]
 define amdgpu_kernel void @mad_sub_inv_f16(half addrspace(1)* noalias nocapture %out, half addrspace(1)* noalias nocapture readonly %ptr) #1 {
   %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
   %tid.ext = sext i32 %tid to i64
   %gep0 = getelementptr half, half addrspace(1)* %ptr, i64 %tid.ext
   %add1 = add i64 %tid.ext, 1
   %gep1 = getelementptr half, half addrspace(1)* %ptr, i64 %add1
   %add2 = add i64 %tid.ext, 2
   %gep2 = getelementptr half, half addrspace(1)* %ptr, i64 %add2

llvm/test/CodeGen/AMDGPU/frem.ll

 ; GFX10-NEXT:    v_cvt_f32_f16_e32 v3, v1
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    v_cvt_f32_f16_e32 v4, v2
 ; GFX10-NEXT:    v_rcp_f32_e32 v4, v4
 ; GFX10-NEXT:    v_mul_f32_e32 v3, v3, v4
 ; GFX10-NEXT:    v_cvt_f16_f32_e32 v3, v3
 ; GFX10-NEXT:    v_div_fixup_f16 v3, v3, v2, v1
 ; GFX10-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX10-NEXT:    v_fmac_f16_e64 v1, -v3, v2
+; GFX10-NEXT:    v_fma_f16 v1, -v3, v2, v1
 ; GFX10-NEXT:    global_store_short v0, v1, s[4:5]
 ; GFX10-NEXT:    s_endpgm
                       half addrspace(1)* %in2) #0 {
    %gep2 = getelementptr half, half addrspace(1)* %in2, i32 4
    %r0 = load half, half addrspace(1)* %in1, align 4
    %r1 = load half, half addrspace(1)* %gep2, align 4
    %r2 = frem half %r0, %r1
    store half %r2, half addrspace(1)* %out, align 4

 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    global_load_ushort v1, v0, s[6:7]
 ; GFX10-NEXT:    global_load_ushort v2, v0, s[2:3] offset:8
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    v_rcp_f16_e32 v3, v2
 ; GFX10-NEXT:    v_mul_f16_e32 v3, v1, v3
 ; GFX10-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX10-NEXT:    v_fmac_f16_e64 v1, -v3, v2
+; GFX10-NEXT:    v_fma_f16 v1, -v3, v2, v1
 ; GFX10-NEXT:    global_store_short v0, v1, s[4:5]
 ; GFX10-NEXT:    s_endpgm
                       half addrspace(1)* %in2) #0 {
    %gep2 = getelementptr half, half addrspace(1)* %in2, i32 4
    %r0 = load half, half addrspace(1)* %in1, align 4
    %r1 = load half, half addrspace(1)* %gep2, align 4
    %r2 = frem fast half %r0, %r1
    store half %r2, half addrspace(1)* %out, align 4

 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    global_load_ushort v1, v0, s[6:7]
 ; GFX10-NEXT:    global_load_ushort v2, v0, s[2:3] offset:8
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    v_rcp_f16_e32 v3, v2
 ; GFX10-NEXT:    v_mul_f16_e32 v3, v1, v3
 ; GFX10-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX10-NEXT:    v_fmac_f16_e64 v1, -v3, v2
+; GFX10-NEXT:    v_fma_f16 v1, -v3, v2, v1
 ; GFX10-NEXT:    global_store_short v0, v1, s[4:5]
 ; GFX10-NEXT:    s_endpgm
                              half addrspace(1)* %in2) #1 {
    %gep2 = getelementptr half, half addrspace(1)* %in2, i32 4
    %r0 = load half, half addrspace(1)* %in1, align 4
    %r1 = load half, half addrspace(1)* %gep2, align 4
    %r2 = frem afn half %r0, %r1
    store half %r2, half addrspace(1)* %out, align 4

 ; GFX10-NEXT:    v_mul_f32_e32 v6, v3, v5
 ; GFX10-NEXT:    v_fma_f32 v7, -v4, v6, v3
 ; GFX10-NEXT:    v_fma_f32 v6, v7, v5, v6
 ; GFX10-NEXT:    v_fma_f32 v3, -v4, v6, v3
 ; GFX10-NEXT:    s_denorm_mode 12
 ; GFX10-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
 ; GFX10-NEXT:    v_div_fixup_f32 v3, v3, v2, v1
 ; GFX10-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX10-NEXT:    v_fmac_f32_e64 v1, -v3, v2
+; GFX10-NEXT:    v_fma_f32 v1, -v3, v2, v1
 ; GFX10-NEXT:    global_store_dword v0, v1, s[4:5]
 ; GFX10-NEXT:    s_endpgm
                       float addrspace(1)* %in2) #0 {
    %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
    %r0 = load float, float addrspace(1)* %in1, align 4
    %r1 = load float, float addrspace(1)* %gep2, align 4
    %r2 = frem float %r0, %r1
    store float %r2, float addrspace(1)* %out, align 4

 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    global_load_dword v1, v0, s[6:7]
 ; GFX10-NEXT:    global_load_dword v2, v0, s[2:3] offset:16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    v_rcp_f32_e32 v3, v2
 ; GFX10-NEXT:    v_mul_f32_e32 v3, v1, v3
 ; GFX10-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX10-NEXT:    v_fmac_f32_e64 v1, -v3, v2
+; GFX10-NEXT:    v_fma_f32 v1, -v3, v2, v1
 ; GFX10-NEXT:    global_store_dword v0, v1, s[4:5]
 ; GFX10-NEXT:    s_endpgm
                       float addrspace(1)* %in2) #0 {
    %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
    %r0 = load float, float addrspace(1)* %in1, align 4
    %r1 = load float, float addrspace(1)* %gep2, align 4
    %r2 = frem fast float %r0, %r1
    store float %r2, float addrspace(1)* %out, align 4

 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    global_load_dword v1, v0, s[6:7]
 ; GFX10-NEXT:    global_load_dword v2, v0, s[2:3] offset:16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    v_rcp_f32_e32 v3, v2
 ; GFX10-NEXT:    v_mul_f32_e32 v3, v1, v3
 ; GFX10-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX10-NEXT:    v_fmac_f32_e64 v1, -v3, v2
+; GFX10-NEXT:    v_fma_f32 v1, -v3, v2, v1
 ; GFX10-NEXT:    global_store_dword v0, v1, s[4:5]
 ; GFX10-NEXT:    s_endpgm
                              float addrspace(1)* %in2) #1 {
    %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
    %r0 = load float, float addrspace(1)* %in1, align 4
    %r1 = load float, float addrspace(1)* %gep2, align 4
    %r2 = frem afn float %r0, %r1
    store float %r2, float addrspace(1)* %out, align 4

 ; GFX10-NEXT:    global_load_dword v1, v0, s[6:7]
 ; GFX10-NEXT:    global_load_dword v2, v0, s[2:3] offset:16
 ; GFX10-NEXT:    s_waitcnt vmcnt(1)
 ; GFX10-NEXT:    v_cvt_f32_f16_e32 v3, v1
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    v_cvt_f32_f16_e32 v4, v2
 ; GFX10-NEXT:    v_rcp_f32_e32 v4, v4
 ; GFX10-NEXT:    v_mul_f32_e32 v3, v3, v4
-; GFX10-NEXT:    v_mov_b32_e32 v4, v1
 ; GFX10-NEXT:    v_cvt_f16_f32_e32 v3, v3
 ; GFX10-NEXT:    v_div_fixup_f16 v3, v3, v2, v1
-; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
 ; GFX10-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX10-NEXT:    v_fmac_f16_e64 v4, -v3, v2
+; GFX10-NEXT:    v_fma_f16 v3, -v3, v2, v1
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
-; GFX10-NEXT:    v_cvt_f32_f16_e32 v3, v1
+; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
 ; GFX10-NEXT:    v_cvt_f32_f16_e32 v5, v2
+; GFX10-NEXT:    v_cvt_f32_f16_e32 v4, v1
 ; GFX10-NEXT:    v_rcp_f32_e32 v5, v5
-; GFX10-NEXT:    v_mul_f32_e32 v3, v3, v5
-; GFX10-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX10-NEXT:    v_div_fixup_f16 v3, v3, v2, v1
-; GFX10-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX10-NEXT:    v_fmac_f16_e64 v1, -v3, v2
-; GFX10-NEXT:    v_pack_b32_f16 v1, v4, v1
+; GFX10-NEXT:    v_mul_f32_e32 v4, v4, v5
+; GFX10-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; GFX10-NEXT:    v_div_fixup_f16 v4, v4, v2, v1
+; GFX10-NEXT:    v_trunc_f16_e32 v4, v4
+; GFX10-NEXT:    v_fma_f16 v1, -v4, v2, v1
+; GFX10-NEXT:    v_pack_b32_f16 v1, v3, v1
 ; GFX10-NEXT:    global_store_dword v0, v1, s[4:5]
 ; GFX10-NEXT:    s_endpgm
                         <2 x half> addrspace(1)* %in2) #0 {
    %gep2 = getelementptr <2 x half>, <2 x half> addrspace(1)* %in2, i32 4
    %r0 = load <2 x half>, <2 x half> addrspace(1)* %in1, align 8
    %r1 = load <2 x half>, <2 x half> addrspace(1)* %gep2, align 8
    %r2 = frem <2 x half> %r0, %r1
    store <2 x half> %r2, <2 x half> addrspace(1)* %out, align 8

 ; GFX10-NEXT:    global_load_dwordx2 v[0:1], v4, s[6:7]
 ; GFX10-NEXT:    global_load_dwordx2 v[2:3], v4, s[2:3] offset:32
 ; GFX10-NEXT:    s_waitcnt vmcnt(1)
 ; GFX10-NEXT:    v_cvt_f32_f16_e32 v5, v1
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    v_cvt_f32_f16_e32 v6, v3
 ; GFX10-NEXT:    v_rcp_f32_e32 v6, v6
 ; GFX10-NEXT:    v_mul_f32_e32 v5, v5, v6
-; GFX10-NEXT:    v_mov_b32_e32 v6, v1
 ; GFX10-NEXT:    v_cvt_f16_f32_e32 v5, v5
 ; GFX10-NEXT:    v_div_fixup_f16 v5, v5, v3, v1
-; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
 ; GFX10-NEXT:    v_trunc_f16_e32 v5, v5
-; GFX10-NEXT:    v_fmac_f16_e64 v6, -v5, v3
+; GFX10-NEXT:    v_fma_f16 v5, -v5, v3, v1
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GFX10-NEXT:    v_cvt_f32_f16_e32 v5, v1
+; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
 ; GFX10-NEXT:    v_cvt_f32_f16_e32 v7, v3
+; GFX10-NEXT:    v_cvt_f32_f16_e32 v6, v1
 ; GFX10-NEXT:    v_rcp_f32_e32 v7, v7
-; GFX10-NEXT:    v_mul_f32_e32 v5, v5, v7
-; GFX10-NEXT:    v_cvt_f16_f32_e32 v5, v5
-; GFX10-NEXT:    v_div_fixup_f16 v5, v5, v3, v1
-; GFX10-NEXT:    v_trunc_f16_e32 v5, v5
-; GFX10-NEXT:    v_fmac_f16_e64 v1, -v5, v3
-; GFX10-NEXT:    v_cvt_f32_f16_e32 v5, v2
+; GFX10-NEXT:    v_mul_f32_e32 v6, v6, v7
+; GFX10-NEXT:    v_cvt_f16_f32_e32 v6, v6
+; GFX10-NEXT:    v_div_fixup_f16 v6, v6, v3, v1
+; GFX10-NEXT:    v_trunc_f16_e32 v6, v6
+; GFX10-NEXT:    v_fma_f16 v1, -v6, v3, v1
 ; GFX10-NEXT:    v_cvt_f32_f16_e32 v3, v0
-; GFX10-NEXT:    v_pack_b32_f16 v1, v6, v1
+; GFX10-NEXT:    v_pack_b32_f16 v1, v5, v1
+; GFX10-NEXT:    v_cvt_f32_f16_e32 v5, v2
 ; GFX10-NEXT:    v_rcp_f32_e32 v5, v5
 ; GFX10-NEXT:    v_mul_f32_e32 v3, v3, v5
-; GFX10-NEXT:    v_mov_b32_e32 v5, v0
 ; GFX10-NEXT:    v_cvt_f16_f32_e32 v3, v3
 ; GFX10-NEXT:    v_div_fixup_f16 v3, v3, v2, v0
-; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GFX10-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX10-NEXT:    v_fmac_f16_e64 v5, -v3, v2
+; GFX10-NEXT:    v_fma_f16 v3, -v3, v2, v0
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
-; GFX10-NEXT:    v_cvt_f32_f16_e32 v3, v0
+; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GFX10-NEXT:    v_cvt_f32_f16_e32 v6, v2
+; GFX10-NEXT:    v_cvt_f32_f16_e32 v5, v0
 ; GFX10-NEXT:    v_rcp_f32_e32 v6, v6
-; GFX10-NEXT:    v_mul_f32_e32 v3, v3, v6
-; GFX10-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX10-NEXT:    v_div_fixup_f16 v3, v3, v2, v0
-; GFX10-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX10-NEXT:    v_fmac_f16_e64 v0, -v3, v2
-; GFX10-NEXT:    v_pack_b32_f16 v0, v5, v0
+; GFX10-NEXT:    v_mul_f32_e32 v5, v5, v6
+; GFX10-NEXT:    v_cvt_f16_f32_e32 v5, v5
+; GFX10-NEXT:    v_div_fixup_f16 v5, v5, v2, v0
+; GFX10-NEXT:    v_trunc_f16_e32 v5, v5
+; GFX10-NEXT:    v_fma_f16 v0, -v5, v2, v0
+; GFX10-NEXT:    v_pack_b32_f16 v0, v3, v0
 ; GFX10-NEXT:    global_store_dwordx2 v4, v[0:1], s[4:5]
 ; GFX10-NEXT:    s_endpgm
                         <4 x half> addrspace(1)* %in2) #0 {
    %gep2 = getelementptr <4 x half>, <4 x half> addrspace(1)* %in2, i32 4
    %r0 = load <4 x half>, <4 x half> addrspace(1)* %in1, align 16
    %r1 = load <4 x half>, <4 x half> addrspace(1)* %gep2, align 16
    %r2 = frem <4 x half> %r0, %r1
    store <4 x half> %r2, <4 x half> addrspace(1)* %out, align 16

 ; GFX10-NEXT:    v_mul_f32_e32 v8, v5, v7
 ; GFX10-NEXT:    v_fma_f32 v9, -v6, v8, v5
 ; GFX10-NEXT:    v_fma_f32 v8, v9, v7, v8
 ; GFX10-NEXT:    v_fma_f32 v5, -v6, v8, v5
 ; GFX10-NEXT:    s_denorm_mode 12
 ; GFX10-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
 ; GFX10-NEXT:    v_div_fixup_f32 v5, v5, v3, v1
 ; GFX10-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX10-NEXT:    v_fma_f32 v1, v3, -v5, v1
+; GFX10-NEXT:    v_fma_f32 v1, -v5, v3, v1
 ; GFX10-NEXT:    v_div_scale_f32 v5, s0, v2, v2, v0
 ; GFX10-NEXT:    v_div_scale_f32 v3, vcc_lo, v0, v2, v0
 ; GFX10-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX10-NEXT:    s_denorm_mode 15
 ; GFX10-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
 ; GFX10-NEXT:    v_fma_f32 v6, v7, v6, v6
 ; GFX10-NEXT:    v_mul_f32_e32 v7, v3, v6
 ; GFX10-NEXT:    v_fma_f32 v8, -v5, v7, v3
 ; GFX10-NEXT:    v_fma_f32 v7, v8, v6, v7
 ; GFX10-NEXT:    v_fma_f32 v3, -v5, v7, v3
 ; GFX10-NEXT:    s_denorm_mode 12
 ; GFX10-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
 ; GFX10-NEXT:    v_div_fixup_f32 v3, v3, v2, v0
 ; GFX10-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX10-NEXT:    v_fmac_f32_e64 v0, -v3, v2
+; GFX10-NEXT:    v_fma_f32 v0, -v3, v2, v0
 ; GFX10-NEXT:    global_store_dwordx2 v4, v[0:1], s[4:5]
 ; GFX10-NEXT:    s_endpgm
                         <2 x float> addrspace(1)* %in2) #0 {
    %gep2 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in2, i32 4
    %r0 = load <2 x float>, <2 x float> addrspace(1)* %in1, align 8
    %r1 = load <2 x float>, <2 x float> addrspace(1)* %gep2, align 8
    %r2 = frem <2 x float> %r0, %r1
    store <2 x float> %r2, <2 x float> addrspace(1)* %out, align 8

 ; GFX10-NEXT:    v_mul_f32_e32 v12, v9, v11
 ; GFX10-NEXT:    v_fma_f32 v13, -v10, v12, v9
 ; GFX10-NEXT:    v_fma_f32 v12, v13, v11, v12
 ; GFX10-NEXT:    v_fma_f32 v9, -v10, v12, v9
 ; GFX10-NEXT:    s_denorm_mode 12
 ; GFX10-NEXT:    v_div_fmas_f32 v9, v9, v11, v12
 ; GFX10-NEXT:    v_div_fixup_f32 v9, v9, v7, v3
 ; GFX10-NEXT:    v_trunc_f32_e32 v9, v9
-; GFX10-NEXT:    v_fma_f32 v3, v7, -v9, v3
+; GFX10-NEXT:    v_fma_f32 v3, -v9, v7, v3
 ; GFX10-NEXT:    v_div_scale_f32 v9, s0, v6, v6, v2
 ; GFX10-NEXT:    v_div_scale_f32 v7, vcc_lo, v2, v6, v2
 ; GFX10-NEXT:    v_rcp_f32_e32 v10, v9
 ; GFX10-NEXT:    s_denorm_mode 15
 ; GFX10-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
 ; GFX10-NEXT:    v_fma_f32 v10, v11, v10, v10
 ; GFX10-NEXT:    v_mul_f32_e32 v11, v7, v10
 ; GFX10-NEXT:    v_fma_f32 v12, -v9, v11, v7
 ; GFX10-NEXT:    v_fma_f32 v11, v12, v10, v11
 ; GFX10-NEXT:    v_fma_f32 v7, -v9, v11, v7
 ; GFX10-NEXT:    s_denorm_mode 12
 ; GFX10-NEXT:    v_div_fmas_f32 v7, v7, v10, v11
 ; GFX10-NEXT:    v_div_fixup_f32 v7, v7, v6, v2
 ; GFX10-NEXT:    v_trunc_f32_e32 v7, v7
-; GFX10-NEXT:    v_fma_f32 v2, v6, -v7, v2
+; GFX10-NEXT:    v_fma_f32 v2, -v7, v6, v2
 ; GFX10-NEXT:    v_div_scale_f32 v7, s0, v5, v5, v1
 ; GFX10-NEXT:    v_div_scale_f32 v6, vcc_lo, v1, v5, v1
 ; GFX10-NEXT:    v_rcp_f32_e32 v9, v7
 ; GFX10-NEXT:    s_denorm_mode 15
 ; GFX10-NEXT:    v_fma_f32 v10, -v7, v9, 1.0
 ; GFX10-NEXT:    v_fma_f32 v9, v10, v9, v9
 ; GFX10-NEXT:    v_mul_f32_e32 v10, v6, v9
 ; GFX10-NEXT:    v_fma_f32 v11, -v7, v10, v6
 ; GFX10-NEXT:    v_fma_f32 v10, v11, v9, v10
 ; GFX10-NEXT:    v_fma_f32 v6, -v7, v10, v6
 ; GFX10-NEXT:    s_denorm_mode 12
 ; GFX10-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
 ; GFX10-NEXT:    v_div_fixup_f32 v6, v6, v5, v1
 ; GFX10-NEXT:    v_trunc_f32_e32 v6, v6
-; GFX10-NEXT:    v_fma_f32 v1, v5, -v6, v1
+; GFX10-NEXT:    v_fma_f32 v1, -v6, v5, v1
 ; GFX10-NEXT:    v_div_scale_f32 v6, s0, v4, v4, v0
 ; GFX10-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v4, v0
 ; GFX10-NEXT:    v_rcp_f32_e32 v7, v6
 ; GFX10-NEXT:    s_denorm_mode 15
 ; GFX10-NEXT:    v_fma_f32 v9, -v6, v7, 1.0
 ; GFX10-NEXT:    v_fma_f32 v7, v9, v7, v7
 ; GFX10-NEXT:    v_mul_f32_e32 v9, v5, v7
 ; GFX10-NEXT:    v_fma_f32 v10, -v6, v9, v5
 ; GFX10-NEXT:    v_fma_f32 v9, v10, v7, v9
 ; GFX10-NEXT:    v_fma_f32 v5, -v6, v9, v5
 ; GFX10-NEXT:    s_denorm_mode 12
 ; GFX10-NEXT:    v_div_fmas_f32 v5, v5, v7, v9
 ; GFX10-NEXT:    v_div_fixup_f32 v5, v5, v4, v0
 ; GFX10-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX10-NEXT:    v_fmac_f32_e64 v0, -v5, v4
+; GFX10-NEXT:    v_fma_f32 v0, -v5, v4, v0
 ; GFX10-NEXT:    global_store_dwordx4 v8, v[0:3], s[4:5]
 ; GFX10-NEXT:    s_endpgm
                         <4 x float> addrspace(1)* %in2) #0 {
    %gep2 = getelementptr <4 x float>, <4 x float> addrspace(1)* %in2, i32 4
    %r0 = load <4 x float>, <4 x float> addrspace(1)* %in1, align 16
    %r1 = load <4 x float>, <4 x float> addrspace(1)* %gep2, align 16
    %r2 = frem <4 x float> %r0, %r1
    store <4 x float> %r2, <4 x float> addrspace(1)* %out, align 16

llvm/test/CodeGen/AMDGPU/mad-mix.ll

define float @no_mix_simple(float %src0, float %src1, float %src2) #0 {
   %result = call float @llvm.fmuladd.f32(float %src0, float %src1, float %src2)
   ret float %result
 }
 
 ; GCN-LABEL: no_mix_simple_fabs:
 ; GCN: s_waitcnt
 ; CIVI-NEXT: v_mad_f32 v0, |v0|, v1, v2
 ; GFX900-NEXT: v_mad_f32 v0, |v0|, v1, v2
-; GFX906-NEXT: v_fma_f32 v0, v1, |v0|, v2
+; GFX906-NEXT: v_fma_f32 v0, |v0|, v1, v2
 ; GCN-NEXT: s_setpc_b64
 define float @no_mix_simple_fabs(float %src0, float %src1, float %src2) #0 {
   %src0.fabs = call float @llvm.fabs.f32(float %src0)
   %result = call float @llvm.fmuladd.f32(float %src0.fabs, float %src1, float %src2)
   ret float %result
 }
 
 ; FIXME: Should abe able to select in thits case

llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll

 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_fma_f16 v0, -v0, -v1, v2
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_fneg:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_fmac_f16_e64 v2, -v0, -v1
-; GFX10-NEXT:    v_mov_b32_e32 v0, v2
+; GFX10-NEXT:    v_fma_f16 v0, -v0, -v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %neg.x = fneg half %x
   %neg.y = fneg half %y
   %val = call half @llvm.experimental.constrained.fma.f16(half %neg.x, half %neg.y, half %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
   ret half %val
 }
 
 define half @v_constained_fma_f16_fpexcept_strict_fabs_fabs(half %x, half %y, half %z) #0 {
 ; GCN-LABEL: v_constained_fma_f16_fpexcept_strict_fabs_fabs:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_fma_f16 v0, |v0|, |v1|, v2
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_constained_fma_f16_fpexcept_strict_fabs_fabs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_fmac_f16_e64 v2, |v0|, |v1|
-; GFX10-NEXT:    v_mov_b32_e32 v0, v2
+; GFX10-NEXT:    v_fma_f16 v0, |v0|, |v1|, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %neg.x = call half @llvm.fabs.f16(half %x)
   %neg.y = call half @llvm.fabs.f16(half %y)
   %val = call half @llvm.experimental.constrained.fma.f16(half %neg.x, half %neg.y, half %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
   ret half %val
 }
 
 define <2 x half> @v_constained_fma_v2f16_fpexcept_strict_fneg_fneg(<2 x half> %x, <2 x half> %y, <2 x half> %z) #0 {

llvm/test/CodeGen/AMDGPU/strict_fma.f32.ll

 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_fma_f32 v0, -v0, -v1, v2
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_fneg:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_fma_f32 v0, -v1, -v0, v2
+; GFX10-NEXT:    v_fma_f32 v0, -v0, -v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %neg.x = fneg float %x
   %neg.y = fneg float %y
   %val = call float @llvm.experimental.constrained.fma.f32(float %neg.x, float %neg.y, float %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
   ret float %val
 }
 
 define float @v_constained_fma_f32_fpexcept_strict_fabs_fabs(float %x, float %y, float %z) #0 {
 ; GCN-LABEL: v_constained_fma_f32_fpexcept_strict_fabs_fabs:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_fma_f32 v0, |v0|, |v1|, v2
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_constained_fma_f32_fpexcept_strict_fabs_fabs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_fma_f32 v0, |v1|, |v0|, v2
+; GFX10-NEXT:    v_fma_f32 v0, |v0|, |v1|, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %neg.x = call float @llvm.fabs.f32(float %x)
   %neg.y = call float @llvm.fabs.f32(float %y)
   %val = call float @llvm.experimental.constrained.fma.f32(float %neg.x, float %neg.y, float %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
   ret float %val
 }
 
 define <2 x float> @v_constained_fma_v2f32_fpexcept_strict_fneg_fneg(<2 x float> %x, <2 x float> %y, <2 x float> %z) #0 {
 ; GCN-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_fma_f32 v0, -v0, -v2, v4
 ; GCN-NEXT:    v_fma_f32 v1, -v1, -v3, v5
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_fma_f32 v0, -v2, -v0, v4
-; GFX10-NEXT:    v_fma_f32 v1, -v3, -v1, v5
+; GFX10-NEXT:    v_fma_f32 v0, -v0, -v2, v4
+; GFX10-NEXT:    v_fma_f32 v1, -v1, -v3, v5
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %neg.x = fneg <2 x float> %x
   %neg.y = fneg <2 x float> %y
   %val = call <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float> %neg.x, <2 x float> %neg.y, <2 x float> %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
   ret <2 x float> %val
 }
 
 declare float @llvm.fabs.f32(float) #1
 declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) #1
 declare <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float>, <2 x float>, <2 x float>, metadata, metadata) #1
 declare <3 x float> @llvm.experimental.constrained.fma.v3f32(<3 x float>, <3 x float>, <3 x float>, metadata, metadata) #1
 declare <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float>, <4 x float>, <4 x float>, metadata, metadata) #1
 
 attributes #0 = { strictfp }
 attributes #1 = { inaccessiblememonly nounwind willreturn }

llvm/test/CodeGen/AMDGPU/udiv.ll

 define amdgpu_kernel void @test_udiv_3_mulhu(i32 %p) {
    %i = udiv i32 %p, 3
    store volatile i32 %i, i32 addrspace(1)* undef
    ret void
 }
 
 ; GCN-LABEL: {{^}}fdiv_test_denormals
 ; VI: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
-; GFX1030: v_fmac_f32_e64 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}
+; GFX1030: v_fma_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
 define amdgpu_kernel void @fdiv_test_denormals(i8 addrspace(1)* nocapture readonly %arg) {
 bb:
   %tmp = load i8, i8 addrspace(1)* null, align 1
   %tmp1 = sext i8 %tmp to i32
   %tmp2 = getelementptr inbounds i8, i8 addrspace(1)* %arg, i64 undef
   %tmp3 = load i8, i8 addrspace(1)* %tmp2, align 1
   %tmp4 = sext i8 %tmp3 to i32
   %tmp5 = sdiv i32 %tmp1, %tmp4