[PowerPC] Reduce number of virtual registers used when eliminating frameindex

[lkail]

Summary

When eliminating frameindex, we don't need two virtual registers to materialize a int32 immediate. No test is changed since SRegHi is set killed and Scavenger allocates the same physical register for SReg and SRegHi.

[nemanjai]

Can you please describe why this change is desired? The description seems to indicate that this is completely unnecessary.

While I do realize that we are out of SSA form at this point, I find it a nice conceptual abstraction that code we add only defines each virtual register once. The register scavenger then allocates appropriate physical registers. Unless there is a known problem where the scavenger ends up doing a bad job or the additional virtual registers add significantly to the compilation time, I am not really in favour of this change.

[lkail]

Can you please describe why this change is desired?

When I work on https://reviews.llvm.org/D107886, I observe there are duplicated codes in PPCFrameLowering and PPCRegisterInfo to materialize immediates. I implemented a routine to get it work https://reviews.llvm.org/D107886#C2797592NL3233. I realized it also applies to virtual registers in non-SSA form. Before applying the routine mentioned above, I have to refactor this part of code a bit.

[lkail]

I just realized this was designed in purpose https://github.com/llvm/llvm-project/commit/d8a423cd71bb2a9b7666fd58fc82db16b4666d1d, though I don't know the motivation to keep it SSA, I'll abandon this patch first.

nice conceptual abstraction that code we add only defines each virtual register once

I agree with it. But in other way, we can still assert(!MRI->isSSA()) here and define virtual registers more than once.

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 
   // The offset doesn't fit into a single register, scavenge one to build the
   // offset in.
 
   bool is64Bit = TM.isPPC64();
   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
   const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
-  Register SRegHi = MF.getRegInfo().createVirtualRegister(RC),
-           SReg = MF.getRegInfo().createVirtualRegister(RC);
+  Register SReg = MF.getRegInfo().createVirtualRegister(RC);
 
   // Insert a set of rA with the full offset value before the ld, st, or add
   if (isInt<16>(Offset))
     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
       .addImm(Offset);
   else {
-    BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
+    BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg)
       .addImm(Offset >> 16);
     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
-      .addReg(SRegHi, RegState::Kill)
+      .addReg(SReg, RegState::Kill)
       .addImm(Offset);
   }
 
   // Convert into indexed form of the instruction:
   //
   //   sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
   //   addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
   unsigned OperandBase;