[PowerPC] Support huge frame size for PPC64

[lkail]

Summary

Support allocation of huge stack frame(>2g) on PPC64.

For ELFv2 ABI on Linux, quoted from the spec 2.2.3.1 General Stack Frame Requirements

There is no maximum stack frame size defined.

On AIX, XL allows such huge frame.

[nemanjai]

Do we have a practical requirement for such a thing? At the very least, I believe we will need code in FI elimination to handle these absurd frame sizes and the test case should show accesses to the stack both before and after the huge allocation.

[lkail]

Update to eliminate frameindex in huge frame.

[lkail]

I'm still testing the patch with variant workloads to insure corner cases are handled correctly.

[lkail]

Tested it with test-suite and other benchmarks on AIX and Linux, no regression found.

[lkail]

Move materialization into a routine.

[nemanjai]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

629

You remove this here but this pre-condition still holds for 32-bit mode. Why not change the condition to only trap in 32-bit mode rather than never?

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

3242

"Receiver" sounds strange. "Target" seems like a more common name.

3250

I am not suggesting we need to re-implement optimal constant materialization here, but it seems trivially easy to only emit the ORI variants only if the immediate is non-zero.

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

1553

Why is this repeated here rather than calling materializeImmPostRA() as you do in other places?

[lkail]

Address comments.

[lkail]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

1553

This is subtle, I've checked the commit https://github.com/llvm/llvm-project/commit/d8a423cd71bb2a9b7666fd58fc82db16b4666d1d of the code above. It intends to keep variables for Registers SSA-like but materializeImmPostRA violates this rule.

[lkail]

Ping.

[lkail]

Gentle ping.

[lkail]

ping.

[lkail]

Updated affected tests.

[lkail]

Gentle ping.

[lkail]

Ping.

[lkail]

Gentle ping.

[shchenz]

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

3244

Can you add the expected pattern to the FIXME for the not optimal pattern?

llvm/test/CodeGen/PowerPC/huge-frame-call.ll

24

Maybe we can avoid these cfi related instructions by adding nounwind to the function. Call frame is not a test point for this patch, right?

[lkail]

Address comments.

[shchenz]

This LGTM.

Let's wait for @nemanjai 's comments/approval since he requested change to this patch.

[nemanjai]

LGTM.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

3245

I think this is not a particularly great example since I imagine this would satisfy the isInt<16>() test (i.e. it looks like this is just -16).

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

void PPCFrameLowering::emitPrologue(MachineFunction &MF,
   // Get the ABI.
   bool isSVR4ABI = Subtarget.isSVR4ABI();
   bool isELFv2ABI = Subtarget.isELFv2ABI();
   assert((isSVR4ABI || Subtarget.isAIXABI()) && "Unsupported PPC ABI.");
 
   // Work out frame sizes.
   uint64_t FrameSize = determineFrameLayoutAndUpdate(MF);
   int64_t NegFrameSize = -FrameSize;
-  if (!isInt<32>(FrameSize) || !isInt<32>(NegFrameSize))
+  if (!isPPC64 && (!isInt<32>(FrameSize) || !isInt<32>(NegFrameSize)))
     llvm_unreachable("Unhandled stack size!");
 
   if (MFI.isFrameAddressTaken())
     replaceFPWithRealFP(MF);
 
   // Check if the link register (LR) must be saved.
   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
   bool MustSaveLR = FI->mustSaveLR();
void PPCFrameLowering::emitPrologue(MachineFunction &MF,
   const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
                                                 : PPC::MFLR );
   const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
                                                  : PPC::STW );
   const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
                                                      : PPC::STWU );
   const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
                                                         : PPC::STWUX);
-  const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
-                                                          : PPC::LIS );
-  const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
-                                                 : PPC::ORI );
   const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
                                               : PPC::OR );
   const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
                                                             : PPC::SUBFC);
   const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
                                                                : PPC::SUBFIC);
   const MCInstrDesc &MoveFromCondRegInst = TII.get(isPPC64 ? PPC::MFCR8
                                                            : PPC::MFCR);
if (HasBP && MaxAlign > 1) {
             .addImm(32 - Log2(MaxAlign))
             .addImm(31);
       if (!isLargeFrame) {
         BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
             .addReg(ScratchReg, RegState::Kill)
             .addImm(NegFrameSize);
       } else {
         assert(!SingleScratchReg && "Only a single scratch reg available");
-        BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
-            .addImm(NegFrameSize >> 16);
-        BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
-            .addReg(TempReg, RegState::Kill)
-            .addImm(NegFrameSize & 0xFFFF);
+        TII.materializeImmPostRA(MBB, MBBI, dl, TempReg, NegFrameSize);
         BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
             .addReg(ScratchReg, RegState::Kill)
             .addReg(TempReg, RegState::Kill);
       }
 
       BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
           .addReg(SPReg, RegState::Kill)
           .addReg(SPReg)
           .addReg(ScratchReg);
       HasSTUX = true;
 
     } else if (!isLargeFrame) {
       BuildMI(MBB, StackUpdateLoc, dl, StoreUpdtInst, SPReg)
           .addReg(SPReg)
           .addImm(NegFrameSize)
           .addReg(SPReg);
 
     } else {
-      BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
-          .addImm(NegFrameSize >> 16);
-      BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
-          .addReg(ScratchReg, RegState::Kill)
-          .addImm(NegFrameSize & 0xFFFF);
+      TII.materializeImmPostRA(MBB, MBBI, dl, ScratchReg, NegFrameSize);
       BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
           .addReg(SPReg, RegState::Kill)
           .addReg(SPReg)
           .addReg(ScratchReg);
       HasSTUX = true;
     }
   }
 
void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
   // restored SP. If the frame size is known and small, we can simply adjust
   // the offsets of the registers to be restored, and still use SP to restore
   // them. In such case, the final update of SP will be to add the frame
   // size to it.
   // To simplify the code, set RBReg to the base register used to restore
   // values from the stack, and set SPAdd to the value that needs to be added
   // to the SP at the end. The default values are as if red zone was present.
   unsigned RBReg = SPReg;
-  unsigned SPAdd = 0;
+  uint64_t SPAdd = 0;
 
   // Check if we can move the stack update instruction up the epilogue
   // past the callee saves. This will allow the move to LR instruction
   // to be executed before the restores of the callee saves which means
   // that the callee saves can hide the latency from the MTLR instrcution.
   MachineBasicBlock::iterator StackUpdateLoc = MBBI;
   if (stackUpdateCanBeMoved(MF)) {
     const std::vector<CalleeSavedInfo> & Info = MFI.getCalleeSavedInfo();
if (FrameSize) {
     else if (FI->hasFastCall() || MF.exposesReturnsTwice()) {
       assert(HasFP && "Expecting a valid frame pointer.");
       if (!HasRedZone)
         RBReg = FPReg;
       if (!isLargeFrame) {
         BuildMI(MBB, MBBI, dl, AddImmInst, RBReg)
           .addReg(FPReg).addImm(FrameSize);
       } else {
-        BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
-          .addImm(FrameSize >> 16);
-        BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
-          .addReg(ScratchReg, RegState::Kill)
-          .addImm(FrameSize & 0xFFFF);
+        TII.materializeImmPostRA(MBB, MBBI, dl, ScratchReg, FrameSize);
         BuildMI(MBB, MBBI, dl, AddInst)
           .addReg(RBReg)
           .addReg(FPReg)
           .addReg(ScratchReg);
       }
     } else if (!isLargeFrame && !HasBP && !MFI.hasVarSizedObjects()) {
       if (HasRedZone) {
         BuildMI(MBB, StackUpdateLoc, dl, AddImmInst, SPReg)

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

public:
 
     /// getI64Imm - Return a target constant with the specified value, of type
     /// i64.
     inline SDValue getI64Imm(uint64_t Imm, const SDLoc &dl) {
       return CurDAG->getTargetConstant(Imm, dl, MVT::i64);
     }
 
     /// getSmallIPtrImm - Return a target constant of pointer type.
-    inline SDValue getSmallIPtrImm(unsigned Imm, const SDLoc &dl) {
+    inline SDValue getSmallIPtrImm(uint64_t Imm, const SDLoc &dl) {
       return CurDAG->getTargetConstant(
           Imm, dl, PPCLowering->getPointerTy(CurDAG->getDataLayout()));
     }
 
     /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
     /// rotate and mask opcode and mask operation.
     static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
                                 unsigned &SH, unsigned &MB, unsigned &ME);
 
     /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
     /// base register.  Return the virtual register that holds this value.
     SDNode *getGlobalBaseReg();
 
-    void selectFrameIndex(SDNode *SN, SDNode *N, unsigned Offset = 0);
+    void selectFrameIndex(SDNode *SN, SDNode *N, uint64_t Offset = 0);
 
     // Select - Convert the specified operand from a target-independent to a
     // target-specific node if it hasn't already been changed.
     void Select(SDNode *N) override;
 
     bool tryBitfieldInsert(SDNode *N);
     bool tryBitPermutation(SDNode *N);
     bool tryIntCompareInGPR(SDNode *N);

 // isOpcWithIntImmediate - This method tests to see if the node is a specific
 // opcode and that it has a immediate integer right operand.
 // If so Imm will receive the 32 bit value.
 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
   return N->getOpcode() == Opc
          && isInt32Immediate(N->getOperand(1).getNode(), Imm);
 }
 
-void PPCDAGToDAGISel::selectFrameIndex(SDNode *SN, SDNode *N, unsigned Offset) {
+void PPCDAGToDAGISel::selectFrameIndex(SDNode *SN, SDNode *N, uint64_t Offset) {
   SDLoc dl(SN);
   int FI = cast<FrameIndexSDNode>(N)->getIndex();
   SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
   unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
   if (SN->hasOneUse())
     CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI,
                          getSmallIPtrImm(Offset, dl));
   else
case ISD::OR: {
     int16_t Imm;
     if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
         isIntS16Immediate(N->getOperand(1), Imm)) {
       KnownBits LHSKnown = CurDAG->computeKnownBits(N->getOperand(0));
 
       // If this is equivalent to an add, then we can fold it with the
       // FrameIndex calculation.
       if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) {
-        selectFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
+        selectFrameIndex(N, N->getOperand(0).getNode(), (int64_t)Imm);
         return;
       }
     }
 
     // If this is 'or' against an imm with consecutive ones and both sides zero,
     // try to emit rldimi
     if (tryAsSingleRLDIMI(N))
       return;
case ISD::XOR: {
     }
 
     break;
   }
   case ISD::ADD: {
     int16_t Imm;
     if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
         isIntS16Immediate(N->getOperand(1), Imm)) {
-      selectFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
+      selectFrameIndex(N, N->getOperand(0).getNode(), (int64_t)Imm);
       return;
     }
 
     break;
   }
   case ISD::SHL: {
     unsigned Imm, SH, MB, ME;
     if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&

llvm/lib/Target/PowerPC/PPCInstrInfo.h

#endif
   bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
                        bool PostRA) const;
 
   // In PostRA phase, try to find instruction defines \p Reg before \p MI.
   // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
   MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI,
                                bool &SeenIntermediateUse) const;
 
+  // Materialize immediate after RA.
+  void materializeImmPostRA(MachineBasicBlock &MBB,
+                            MachineBasicBlock::iterator MBBI,
+                            const DebugLoc &DL, Register Reg,
+                            int64_t Imm) const;
+
   /// getRegNumForOperand - some operands use different numbering schemes
   /// for the same registers. For example, a VSX instruction may have any of
   /// vs0-vs63 allocated whereas an Altivec instruction could only have
   /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
   /// register number needed for the opcode/operand number combination.
   /// The operand number argument will be useful when we need to extend this
   /// to instructions that use both Altivec and VSX numbering (for different
   /// operands).

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

for (; It != E; ++It) {
     if (It->modifiesRegister(Reg, TRI))
       return &*It;
     if (It->readsRegister(Reg, TRI))
       SeenIntermediateUse = true;
   }
   return nullptr;
 }
 
+void PPCInstrInfo::materializeImmPostRA(MachineBasicBlock &MBB,
+                                        MachineBasicBlock::iterator MBBI,
+                                        const DebugLoc &DL, Register Reg,
+                                        int64_t Imm) const {
+  assert(!MBB.getParent()->getRegInfo().isSSA() &&
+         "Register should be in non-SSA form after RA");
+  bool isPPC64 = Subtarget.isPPC64();
+  // FIXME: Materialization here is not optimal.
+  // For some special bit patterns we can use less instructions.
+  // See `selectI64ImmDirect` in PPCISelDAGToDAG.cpp.
+  if (isInt<16>(Imm)) {
+    BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::LI8 : PPC::LI), Reg).addImm(Imm);
+  } else if (isInt<32>(Imm)) {
+    BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::LIS8 : PPC::LIS), Reg)
+        .addImm(Imm >> 16);
+    if (Imm & 0xFFFF)
+      BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::ORI8 : PPC::ORI), Reg)
+          .addReg(Reg, RegState::Kill)
+          .addImm(Imm & 0xFFFF);
+  } else {
+    assert(isPPC64 && "Materializing 64-bit immediate to single register is "
+                      "only supported in PPC64");
+    BuildMI(MBB, MBBI, DL, get(PPC::LIS8), Reg).addImm(Imm >> 48);
+    if ((Imm >> 32) & 0xFFFF)
+      BuildMI(MBB, MBBI, DL, get(PPC::ORI8), Reg)
+          .addReg(Reg, RegState::Kill)
+          .addImm((Imm >> 32) & 0xFFFF);
+    BuildMI(MBB, MBBI, DL, get(PPC::RLDICR), Reg)
+        .addReg(Reg, RegState::Kill)
+        .addImm(32)
+        .addImm(31);
+    BuildMI(MBB, MBBI, DL, get(PPC::ORIS8), Reg)
+        .addReg(Reg, RegState::Kill)
+        .addImm((Imm >> 16) & 0xFFFF);
+    if (Imm & 0xFFFF)
+      BuildMI(MBB, MBBI, DL, get(PPC::ORI8), Reg)
+          .addReg(Reg, RegState::Kill)
+          .addImm(Imm & 0xFFFF);
+  }
+}
+
 MachineInstr *PPCInstrInfo::getForwardingDefMI(
   MachineInstr &MI,
   unsigned &OpNoForForwarding,
   bool &SeenIntermediateUse) const {
   OpNoForForwarding = ~0U;
   MachineInstr *DefMI = nullptr;
   MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
   const TargetRegisterInfo *TRI = &getRegisterInfo();

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

MI.getOperand(FIOperandNum).ChangeToRegister(
     FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
 
   // If the instruction is not present in ImmToIdxMap, then it has no immediate
   // form (and must be r+r).
   bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
                    OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
 
   // Now add the frame object offset to the offset from r1.
-  int Offset = MFI.getObjectOffset(FrameIndex);
+  int64_t Offset = MFI.getObjectOffset(FrameIndex);
   Offset += MI.getOperand(OffsetOperandNo).getImm();
 
   // If we're not using a Frame Pointer that has been set to the value of the
   // SP before having the stack size subtracted from it, then add the stack size
   // to Offset to get the correct offset.
   // Naked functions have stack size 0, although getStackSize may not reflect
   // that because we didn't call all the pieces that compute it for naked
   // functions.
PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
   const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
   Register SRegHi = MF.getRegInfo().createVirtualRegister(RC),
            SReg = MF.getRegInfo().createVirtualRegister(RC);
 
   // Insert a set of rA with the full offset value before the ld, st, or add
   if (isInt<16>(Offset))
     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
         .addImm(Offset);
-  else {
+  else if (isInt<32>(Offset)) {
     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
         .addImm(Offset >> 16);
     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
         .addReg(SRegHi, RegState::Kill)
         .addImm(Offset);
+  } else {
+    assert(is64Bit && "Huge stack is only supported on PPC64");
+    TII.materializeImmPostRA(MBB, II, dl, SReg, Offset);
   }
 
   // Convert into indexed form of the instruction:
   //
   //   sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
   //   addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
   unsigned OperandBase;
 
   if (noImmForm)
     OperandBase = 1;
   else if (OpC != TargetOpcode::INLINEASM &&
            OpC != TargetOpcode::INLINEASM_BR) {

llvm/test/CodeGen/PowerPC/huge-frame-call.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu < %s \
+; RUN:   2>&1 | FileCheck --check-prefix=CHECK-LE %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s \
+; RUN:   2>&1 | FileCheck --check-prefix=CHECK-BE %s
+
+%0 = type <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, [8 x i8] }>
+@global.1 = internal global %0 <{ i32 129, i32 2, i32 118, i32 0, i32 5, i32 0, i32 0, i32 0, i32 120, i32 0, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @global.2, i32 0, i32 0), [8 x i8] c"\00\00\00\00\00\00\00\03" }>, align 4
+@global.2 = internal constant [3 x i8] c"x.c"
+@alias = dso_local alias i32 (), i32 ()* @main
+
+define dso_local signext i32 @main() nounwind {
+; CHECK-LE-LABEL: main:
+; CHECK-LE:       # %bb.0: # %bb
+; CHECK-LE-NEXT:    mflr 0
+; CHECK-LE-NEXT:    std 0, 16(1)
+; CHECK-LE-NEXT:    lis 0, -1
+; CHECK-LE-NEXT:    ori 0, 0, 65535
+; CHECK-LE-NEXT:    sldi 0, 0, 32
+; CHECK-LE-NEXT:    oris 0, 0, 32767
+; CHECK-LE-NEXT:    ori 0, 0, 65120
+; CHECK-LE-NEXT:    stdux 1, 1, 0
+; CHECK-LE-NEXT:    lis 3, 0
+; CHECK-LE-NEXT:    sldi 3, 3, 32
+; CHECK-LE-NEXT:    oris 3, 3, 32768
+; CHECK-LE-NEXT:    ori 3, 3, 400
+; CHECK-LE-NEXT:    stdx 30, 1, 3 # 8-byte Folded Spill
+; CHECK-LE-NEXT:    bl pluto
+; CHECK-LE-NEXT:    nop
+; CHECK-LE-NEXT:    addis 3, 2, global.1@toc@ha
+; CHECK-LE-NEXT:    li 4, 0
+; CHECK-LE-NEXT:    li 7, 0
+; CHECK-LE-NEXT:    li 8, 0
+; CHECK-LE-NEXT:    li 9, 0
+; CHECK-LE-NEXT:    addi 5, 3, global.1@toc@l
+; CHECK-LE-NEXT:    ori 6, 4, 32768
+; CHECK-LE-NEXT:    li 3, 6
+; CHECK-LE-NEXT:    li 4, 257
+; CHECK-LE-NEXT:    bl snork
+; CHECK-LE-NEXT:    nop
+; CHECK-LE-NEXT:    mr 30, 3
+; CHECK-LE-NEXT:    li 3, 344
+; CHECK-LE-NEXT:    addi 4, 1, 48
+; CHECK-LE-NEXT:    li 5, 8
+; CHECK-LE-NEXT:    li 6, 8
+; CHECK-LE-NEXT:    oris 3, 3, 32768
+; CHECK-LE-NEXT:    add 4, 4, 3
+; CHECK-LE-NEXT:    mr 3, 30
+; CHECK-LE-NEXT:    bl zot
+; CHECK-LE-NEXT:    nop
+; CHECK-LE-NEXT:    mr 3, 30
+; CHECK-LE-NEXT:    bl wibble
+; CHECK-LE-NEXT:    nop
+; CHECK-LE-NEXT:    li 3, 0
+; CHECK-LE-NEXT:    bl snork.3
+; CHECK-LE-NEXT:    nop
+;
+; CHECK-BE-LABEL: main:
+; CHECK-BE:       # %bb.0: # %bb
+; CHECK-BE-NEXT:    mflr 0
+; CHECK-BE-NEXT:    std 0, 16(1)
+; CHECK-BE-NEXT:    lis 0, -1
+; CHECK-BE-NEXT:    ori 0, 0, 65535
+; CHECK-BE-NEXT:    sldi 0, 0, 32
+; CHECK-BE-NEXT:    oris 0, 0, 32767
+; CHECK-BE-NEXT:    ori 0, 0, 65056
+; CHECK-BE-NEXT:    stdux 1, 1, 0
+; CHECK-BE-NEXT:    lis 3, 0
+; CHECK-BE-NEXT:    sldi 3, 3, 32
+; CHECK-BE-NEXT:    oris 3, 3, 32768
+; CHECK-BE-NEXT:    ori 3, 3, 472
+; CHECK-BE-NEXT:    stdx 31, 1, 3 # 8-byte Folded Spill
+; CHECK-BE-NEXT:    bl .pluto[PR]
+; CHECK-BE-NEXT:    nop
+; CHECK-BE-NEXT:    ld 5, L..C0(2) # @global.1
+; CHECK-BE-NEXT:    li 3, 0
+; CHECK-BE-NEXT:    ori 6, 3, 32768
+; CHECK-BE-NEXT:    li 3, 6
+; CHECK-BE-NEXT:    li 4, 257
+; CHECK-BE-NEXT:    li 7, 0
+; CHECK-BE-NEXT:    li 8, 0
+; CHECK-BE-NEXT:    li 9, 0
+; CHECK-BE-NEXT:    bl .snork[PR]
+; CHECK-BE-NEXT:    nop
+; CHECK-BE-NEXT:    mr 31, 3
+; CHECK-BE-NEXT:    li 3, 344
+; CHECK-BE-NEXT:    oris 3, 3, 32768
+; CHECK-BE-NEXT:    addi 4, 1, 120
+; CHECK-BE-NEXT:    add 4, 4, 3
+; CHECK-BE-NEXT:    mr 3, 31
+; CHECK-BE-NEXT:    li 5, 8
+; CHECK-BE-NEXT:    li 6, 8
+; CHECK-BE-NEXT:    bl .zot[PR]
+; CHECK-BE-NEXT:    nop
+; CHECK-BE-NEXT:    mr 3, 31
+; CHECK-BE-NEXT:    bl .wibble[PR]
+; CHECK-BE-NEXT:    nop
+; CHECK-BE-NEXT:    li 3, 0
+; CHECK-BE-NEXT:    bl .snork.3[PR]
+; CHECK-BE-NEXT:    nop
+bb:
+  %tmp = alloca [2147484000 x i8], align 8
+  tail call void @pluto()
+  %tmp6 = tail call i64 @snork(i64 6, i32 257, %0* nonnull @global.1, i64 32768, i8* null, i64 0, i8* null)
+  %tmp7 = getelementptr inbounds [2147484000 x i8], [2147484000 x i8]* %tmp, i64 0, i64 2147483992
+  %tmp8 = bitcast i8* %tmp7 to double*
+  %tmp9 = call i64 @zot(i64 %tmp6, double* nonnull %tmp8, i64 8, i64 8)
+  %tmp10 = call i64 @wibble(i64 %tmp6)
+  call void @snork.3(i64 0)
+  unreachable
+}
+
+declare void @pluto()
+
+declare signext i64 @snork(i64, i32, %0*, i64, i8*, i64, i8*)
+
+declare signext i64 @zot(i64, double*, i64, i64)
+
+declare signext i64 @wibble(i64)
+
+declare void @snork.3(i64)

llvm/test/CodeGen/PowerPC/huge-frame-size.ll

-; REQUIRES: asserts
-; RUN: not --crash llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu < %s \
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu < %s \
 ; RUN:   2>&1 | FileCheck --check-prefix=CHECK-LE %s
-; RUN: not --crash llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s \
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s \
 ; RUN:   2>&1 | FileCheck --check-prefix=CHECK-BE %s
 
 declare void @bar(i8*)
 
 define void @foo(i8 %x) {
-; CHECK-LE: Unhandled stack size
-; CHECK-BE: Unhandled stack size
+; CHECK-LE-LABEL: foo:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    lis 0, -1
+; CHECK-LE-NEXT:    ori 0, 0, 65534
+; CHECK-LE-NEXT:    sldi 0, 0, 32
+; CHECK-LE-NEXT:    oris 0, 0, 65535
+; CHECK-LE-NEXT:    ori 0, 0, 65504
+; CHECK-LE-NEXT:    stdux 1, 1, 0
+; CHECK-LE-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-LE-NEXT:    li 4, 1
+; CHECK-LE-NEXT:    li 5, -1
+; CHECK-LE-NEXT:    addi 6, 1, 32
+; CHECK-LE-NEXT:    stb 3, 32(1)
+; CHECK-LE-NEXT:    rldic 4, 4, 31, 32
+; CHECK-LE-NEXT:    rldic 5, 5, 0, 32
+; CHECK-LE-NEXT:    stbx 3, 6, 4
+; CHECK-LE-NEXT:    stbx 3, 6, 5
+; CHECK-LE-NEXT:    ld 1, 0(1)
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: foo:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    lis 0, -1
+; CHECK-BE-NEXT:    ori 0, 0, 65534
+; CHECK-BE-NEXT:    sldi 0, 0, 32
+; CHECK-BE-NEXT:    oris 0, 0, 65535
+; CHECK-BE-NEXT:    ori 0, 0, 65488
+; CHECK-BE-NEXT:    stdux 1, 1, 0
+; CHECK-BE-NEXT:    li 4, 1
+; CHECK-BE-NEXT:    addi 5, 1, 48
+; CHECK-BE-NEXT:    rldic 4, 4, 31, 32
+; CHECK-BE-NEXT:    stb 3, 48(1)
+; CHECK-BE-NEXT:    stbx 3, 5, 4
+; CHECK-BE-NEXT:    li 4, -1
+; CHECK-BE-NEXT:    rldic 4, 4, 0, 32
+; CHECK-BE-NEXT:    stbx 3, 5, 4
+; CHECK-BE-NEXT:    ld 1, 0(1)
+; CHECK-BE-NEXT:    blr
 entry:
   %a = alloca i8, i64 4294967296, align 16
   %b = getelementptr i8, i8* %a, i64 0
+  %c = getelementptr i8, i8* %a, i64 2147483648
+  %d = getelementptr i8, i8* %a, i64 4294967295
   store volatile i8 %x, i8* %b
+  store volatile i8 %x, i8* %c
+  store volatile i8 %x, i8* %d
   ret void
 }

llvm/test/CodeGen/PowerPC/huge-frame-unsupported.ll

+; REQUIRES: asserts
+; RUN: not --crash llc -verify-machineinstrs -mtriple=powerpc-unknown-unknown < %s \
+; RUN:   2>&1 | FileCheck %s
+
+declare void @bar(i8*)
+
+define void @foo(i8 %x) {
+; CHECK: Unhandled stack size
+entry:
+  %a = alloca i8, i64 4294967296, align 16
+  %b = getelementptr i8, i8* %a, i64 0
+  store volatile i8 %x, i8* %b
+  ret void
+}

llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll

return:                                           ; preds = %entry, %if.end
   %retval.0 = phi i32 [ %add, %if.end ], [ 0, %entry ]
   ret i32 %retval.0
 }
 
 define dso_local zeroext i32 @aligned(i32* nocapture readonly %in) #0 {
 ; BE-P10-LABEL: aligned:
 ; BE-P10:       # %bb.0: # %entry
 ; BE-P10-NEXT:    mflr r0
-; BE-P10-NEXT:    lis r12, -1
 ; BE-P10-NEXT:    std r30, -16(r1)
+; BE-P10-NEXT:    lis r12, -1
 ; BE-P10-NEXT:    mr r30, r1
 ; BE-P10-NEXT:    std r0, 16(r1)
 ; BE-P10-NEXT:    hashst r0, -24(r1)
 ; BE-P10-NEXT:    clrldi r0, r1, 49
-; BE-P10-NEXT:    ori r12, r12, 0
 ; BE-P10-NEXT:    subc r0, r12, r0
 ; BE-P10-NEXT:    stdux r1, r1, r0
 ; BE-P10-NEXT:    std r31, -8(r30) # 8-byte Folded Spill
 ; BE-P10-NEXT:    mr r31, r3
 ; BE-P10-NEXT:    lwz r3, 4(r3)
 ; BE-P10-NEXT:    lis r4, 0
 ; BE-P10-NEXT:    addi r5, r1, 32764
 ; BE-P10-NEXT:    ori r4, r4, 65508

 ; BE-P10-NEXT:    ld r30, -16(r1)
 ; BE-P10-NEXT:    mtlr r0
 ; BE-P10-NEXT:    hashchk r0, -24(r1)
 ; BE-P10-NEXT:    blr
 ;
 ; BE-P9-LABEL: aligned:
 ; BE-P9:       # %bb.0: # %entry
 ; BE-P9-NEXT:    mflr r0
-; BE-P9-NEXT:    lis r12, -1
 ; BE-P9-NEXT:    std r30, -16(r1)
+; BE-P9-NEXT:    lis r12, -1
 ; BE-P9-NEXT:    mr r30, r1
-; BE-P9-NEXT:    ori r12, r12, 0
 ; BE-P9-NEXT:    std r0, 16(r1)
 ; BE-P9-NEXT:    hashst r0, -24(r1)
 ; BE-P9-NEXT:    clrldi r0, r1, 49
 ; BE-P9-NEXT:    subc r0, r12, r0
 ; BE-P9-NEXT:    stdux r1, r1, r0
 ; BE-P9-NEXT:    std r31, -8(r30) # 8-byte Folded Spill
 ; BE-P9-NEXT:    mr r31, r3
 ; BE-P9-NEXT:    lwz r3, 4(r3)

 ; BE-P9-NEXT:    ld r30, -16(r1)
 ; BE-P9-NEXT:    mtlr r0
 ; BE-P9-NEXT:    hashchk r0, -24(r1)
 ; BE-P9-NEXT:    blr
 ;
 ; BE-P8-LABEL: aligned:
 ; BE-P8:       # %bb.0: # %entry
 ; BE-P8-NEXT:    mflr r0
-; BE-P8-NEXT:    lis r12, -1
 ; BE-P8-NEXT:    std r30, -16(r1)
+; BE-P8-NEXT:    lis r12, -1
 ; BE-P8-NEXT:    mr r30, r1
 ; BE-P8-NEXT:    std r0, 16(r1)
 ; BE-P8-NEXT:    hashst r0, -24(r1)
 ; BE-P8-NEXT:    clrldi r0, r1, 49
-; BE-P8-NEXT:    ori r12, r12, 0
 ; BE-P8-NEXT:    subc r0, r12, r0
 ; BE-P8-NEXT:    stdux r1, r1, r0
 ; BE-P8-NEXT:    std r31, -8(r30) # 8-byte Folded Spill
 ; BE-P8-NEXT:    mr r31, r3
 ; BE-P8-NEXT:    lwz r3, 4(r3)
 ; BE-P8-NEXT:    lis r6, 0
 ; BE-P8-NEXT:    ori r6, r6, 65508
 ; BE-P8-NEXT:    lwz r4, 12(r31)

 ; BE-P8-NEXT:    ld r30, -16(r1)
 ; BE-P8-NEXT:    hashchk r0, -24(r1)
 ; BE-P8-NEXT:    mtlr r0
 ; BE-P8-NEXT:    blr
 ;
 ; BE-32BIT-P10-LABEL: aligned:
 ; BE-32BIT-P10:       # %bb.0: # %entry
 ; BE-32BIT-P10-NEXT:    mflr r0
-; BE-32BIT-P10-NEXT:    lis r12, -1
 ; BE-32BIT-P10-NEXT:    stw r30, -8(r1)
+; BE-32BIT-P10-NEXT:    lis r12, -1
 ; BE-32BIT-P10-NEXT:    mr r30, r1
 ; BE-32BIT-P10-NEXT:    stw r0, 8(r1)
 ; BE-32BIT-P10-NEXT:    hashst r0, -16(r1)
 ; BE-32BIT-P10-NEXT:    clrlwi r0, r1, 17
-; BE-32BIT-P10-NEXT:    ori r12, r12, 0
 ; BE-32BIT-P10-NEXT:    subc r0, r12, r0
 ; BE-32BIT-P10-NEXT:    stwux r1, r1, r0
 ; BE-32BIT-P10-NEXT:    stw r31, -4(r30) # 4-byte Folded Spill
 ; BE-32BIT-P10-NEXT:    mr r31, r3
 ; BE-32BIT-P10-NEXT:    lwz r3, 4(r3)
 ; BE-32BIT-P10-NEXT:    lis r4, 0
 ; BE-32BIT-P10-NEXT:    addi r5, r1, 32764
 ; BE-32BIT-P10-NEXT:    ori r4, r4, 65516

 ; BE-32BIT-P10-NEXT:    lwz r30, -8(r1)
 ; BE-32BIT-P10-NEXT:    mtlr r0
 ; BE-32BIT-P10-NEXT:    hashchk r0, -16(r1)
 ; BE-32BIT-P10-NEXT:    blr
 ;
 ; BE-32BIT-P9-LABEL: aligned:
 ; BE-32BIT-P9:       # %bb.0: # %entry
 ; BE-32BIT-P9-NEXT:    mflr r0
-; BE-32BIT-P9-NEXT:    lis r12, -1
 ; BE-32BIT-P9-NEXT:    stw r30, -8(r1)
+; BE-32BIT-P9-NEXT:    lis r12, -1
 ; BE-32BIT-P9-NEXT:    mr r30, r1
-; BE-32BIT-P9-NEXT:    ori r12, r12, 0
 ; BE-32BIT-P9-NEXT:    stw r0, 8(r1)
 ; BE-32BIT-P9-NEXT:    hashst r0, -16(r1)
 ; BE-32BIT-P9-NEXT:    clrlwi r0, r1, 17
 ; BE-32BIT-P9-NEXT:    subc r0, r12, r0
 ; BE-32BIT-P9-NEXT:    stwux r1, r1, r0
 ; BE-32BIT-P9-NEXT:    stw r31, -4(r30) # 4-byte Folded Spill
 ; BE-32BIT-P9-NEXT:    mr r31, r3
 ; BE-32BIT-P9-NEXT:    lwz r3, 4(r3)

 ; BE-32BIT-P9-NEXT:    lwz r30, -8(r1)
 ; BE-32BIT-P9-NEXT:    mtlr r0
 ; BE-32BIT-P9-NEXT:    hashchk r0, -16(r1)
 ; BE-32BIT-P9-NEXT:    blr
 ;
 ; BE-32BIT-P8-LABEL: aligned:
 ; BE-32BIT-P8:       # %bb.0: # %entry
 ; BE-32BIT-P8-NEXT:    mflr r0
-; BE-32BIT-P8-NEXT:    lis r12, -1
 ; BE-32BIT-P8-NEXT:    stw r30, -8(r1)
+; BE-32BIT-P8-NEXT:    lis r12, -1
 ; BE-32BIT-P8-NEXT:    mr r30, r1
 ; BE-32BIT-P8-NEXT:    stw r0, 8(r1)
 ; BE-32BIT-P8-NEXT:    hashst r0, -16(r1)
 ; BE-32BIT-P8-NEXT:    clrlwi r0, r1, 17
-; BE-32BIT-P8-NEXT:    ori r12, r12, 0
 ; BE-32BIT-P8-NEXT:    subc r0, r12, r0
 ; BE-32BIT-P8-NEXT:    stwux r1, r1, r0
 ; BE-32BIT-P8-NEXT:    stw r31, -4(r30) # 4-byte Folded Spill
 ; BE-32BIT-P8-NEXT:    mr r31, r3
 ; BE-32BIT-P8-NEXT:    lwz r3, 4(r3)
 ; BE-32BIT-P8-NEXT:    lis r6, 0
 ; BE-32BIT-P8-NEXT:    ori r6, r6, 65516
 ; BE-32BIT-P8-NEXT:    lwz r4, 12(r31)

 ; BE-32BIT-P8-NEXT:    lwz r30, -8(r1)
 ; BE-32BIT-P8-NEXT:    hashchk r0, -16(r1)
 ; BE-32BIT-P8-NEXT:    mtlr r0
 ; BE-32BIT-P8-NEXT:    blr
 ;
 ; BE-P10-PRIV-LABEL: aligned:
 ; BE-P10-PRIV:       # %bb.0: # %entry
 ; BE-P10-PRIV-NEXT:    mflr r0
-; BE-P10-PRIV-NEXT:    lis r12, -1
 ; BE-P10-PRIV-NEXT:    std r30, -16(r1)
+; BE-P10-PRIV-NEXT:    lis r12, -1
 ; BE-P10-PRIV-NEXT:    mr r30, r1
 ; BE-P10-PRIV-NEXT:    std r0, 16(r1)
 ; BE-P10-PRIV-NEXT:    hashstp r0, -24(r1)
 ; BE-P10-PRIV-NEXT:    clrldi r0, r1, 49
-; BE-P10-PRIV-NEXT:    ori r12, r12, 0
 ; BE-P10-PRIV-NEXT:    subc r0, r12, r0
 ; BE-P10-PRIV-NEXT:    stdux r1, r1, r0
 ; BE-P10-PRIV-NEXT:    std r31, -8(r30) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    mr r31, r3
 ; BE-P10-PRIV-NEXT:    lwz r3, 4(r3)
 ; BE-P10-PRIV-NEXT:    lis r4, 0
 ; BE-P10-PRIV-NEXT:    addi r5, r1, 32764
 ; BE-P10-PRIV-NEXT:    ori r4, r4, 65508

 ; BE-P10-PRIV-NEXT:    ld r30, -16(r1)
 ; BE-P10-PRIV-NEXT:    mtlr r0
 ; BE-P10-PRIV-NEXT:    hashchkp r0, -24(r1)
 ; BE-P10-PRIV-NEXT:    blr
 ;
 ; BE-P9-PRIV-LABEL: aligned:
 ; BE-P9-PRIV:       # %bb.0: # %entry
 ; BE-P9-PRIV-NEXT:    mflr r0
-; BE-P9-PRIV-NEXT:    lis r12, -1
 ; BE-P9-PRIV-NEXT:    std r30, -16(r1)
+; BE-P9-PRIV-NEXT:    lis r12, -1
 ; BE-P9-PRIV-NEXT:    mr r30, r1
-; BE-P9-PRIV-NEXT:    ori r12, r12, 0
 ; BE-P9-PRIV-NEXT:    std r0, 16(r1)
 ; BE-P9-PRIV-NEXT:    hashstp r0, -24(r1)
 ; BE-P9-PRIV-NEXT:    clrldi r0, r1, 49
 ; BE-P9-PRIV-NEXT:    subc r0, r12, r0
 ; BE-P9-PRIV-NEXT:    stdux r1, r1, r0
 ; BE-P9-PRIV-NEXT:    std r31, -8(r30) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    mr r31, r3
 ; BE-P9-PRIV-NEXT:    lwz r3, 4(r3)

 ; BE-P9-PRIV-NEXT:    ld r30, -16(r1)
 ; BE-P9-PRIV-NEXT:    mtlr r0
 ; BE-P9-PRIV-NEXT:    hashchkp r0, -24(r1)
 ; BE-P9-PRIV-NEXT:    blr
 ;
 ; BE-P8-PRIV-LABEL: aligned:
 ; BE-P8-PRIV:       # %bb.0: # %entry
 ; BE-P8-PRIV-NEXT:    mflr r0
-; BE-P8-PRIV-NEXT:    lis r12, -1
 ; BE-P8-PRIV-NEXT:    std r30, -16(r1)
+; BE-P8-PRIV-NEXT:    lis r12, -1
 ; BE-P8-PRIV-NEXT:    mr r30, r1
 ; BE-P8-PRIV-NEXT:    std r0, 16(r1)
 ; BE-P8-PRIV-NEXT:    hashstp r0, -24(r1)
 ; BE-P8-PRIV-NEXT:    clrldi r0, r1, 49
-; BE-P8-PRIV-NEXT:    ori r12, r12, 0
 ; BE-P8-PRIV-NEXT:    subc r0, r12, r0
 ; BE-P8-PRIV-NEXT:    stdux r1, r1, r0
 ; BE-P8-PRIV-NEXT:    std r31, -8(r30) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    mr r31, r3
 ; BE-P8-PRIV-NEXT:    lwz r3, 4(r3)
 ; BE-P8-PRIV-NEXT:    lis r6, 0
 ; BE-P8-PRIV-NEXT:    ori r6, r6, 65508
 ; BE-P8-PRIV-NEXT:    lwz r4, 12(r31)

 ; BE-P8-PRIV-NEXT:    ld r30, -16(r1)
 ; BE-P8-PRIV-NEXT:    hashchkp r0, -24(r1)
 ; BE-P8-PRIV-NEXT:    mtlr r0
 ; BE-P8-PRIV-NEXT:    blr
 ;
 ; BE-32BIT-P10-PRIV-LABEL: aligned:
 ; BE-32BIT-P10-PRIV:       # %bb.0: # %entry
 ; BE-32BIT-P10-PRIV-NEXT:    mflr r0
-; BE-32BIT-P10-PRIV-NEXT:    lis r12, -1
 ; BE-32BIT-P10-PRIV-NEXT:    stw r30, -8(r1)
+; BE-32BIT-P10-PRIV-NEXT:    lis r12, -1
 ; BE-32BIT-P10-PRIV-NEXT:    mr r30, r1
 ; BE-32BIT-P10-PRIV-NEXT:    stw r0, 8(r1)
 ; BE-32BIT-P10-PRIV-NEXT:    hashstp r0, -16(r1)
 ; BE-32BIT-P10-PRIV-NEXT:    clrlwi r0, r1, 17
-; BE-32BIT-P10-PRIV-NEXT:    ori r12, r12, 0
 ; BE-32BIT-P10-PRIV-NEXT:    subc r0, r12, r0
 ; BE-32BIT-P10-PRIV-NEXT:    stwux r1, r1, r0
 ; BE-32BIT-P10-PRIV-NEXT:    stw r31, -4(r30) # 4-byte Folded Spill
 ; BE-32BIT-P10-PRIV-NEXT:    mr r31, r3
 ; BE-32BIT-P10-PRIV-NEXT:    lwz r3, 4(r3)
 ; BE-32BIT-P10-PRIV-NEXT:    lis r4, 0
 ; BE-32BIT-P10-PRIV-NEXT:    addi r5, r1, 32764
 ; BE-32BIT-P10-PRIV-NEXT:    ori r4, r4, 65516

 ; BE-32BIT-P10-PRIV-NEXT:    lwz r30, -8(r1)
 ; BE-32BIT-P10-PRIV-NEXT:    mtlr r0
 ; BE-32BIT-P10-PRIV-NEXT:    hashchkp r0, -16(r1)
 ; BE-32BIT-P10-PRIV-NEXT:    blr
 ;
 ; BE-32BIT-P9-PRIV-LABEL: aligned:
 ; BE-32BIT-P9-PRIV:       # %bb.0: # %entry
 ; BE-32BIT-P9-PRIV-NEXT:    mflr r0
-; BE-32BIT-P9-PRIV-NEXT:    lis r12, -1
 ; BE-32BIT-P9-PRIV-NEXT:    stw r30, -8(r1)
+; BE-32BIT-P9-PRIV-NEXT:    lis r12, -1
 ; BE-32BIT-P9-PRIV-NEXT:    mr r30, r1
-; BE-32BIT-P9-PRIV-NEXT:    ori r12, r12, 0
 ; BE-32BIT-P9-PRIV-NEXT:    stw r0, 8(r1)
 ; BE-32BIT-P9-PRIV-NEXT:    hashstp r0, -16(r1)
 ; BE-32BIT-P9-PRIV-NEXT:    clrlwi r0, r1, 17
 ; BE-32BIT-P9-PRIV-NEXT:    subc r0, r12, r0
 ; BE-32BIT-P9-PRIV-NEXT:    stwux r1, r1, r0
 ; BE-32BIT-P9-PRIV-NEXT:    stw r31, -4(r30) # 4-byte Folded Spill
 ; BE-32BIT-P9-PRIV-NEXT:    mr r31, r3
 ; BE-32BIT-P9-PRIV-NEXT:    lwz r3, 4(r3)

 ; BE-32BIT-P9-PRIV-NEXT:    lwz r30, -8(r1)
 ; BE-32BIT-P9-PRIV-NEXT:    mtlr r0
 ; BE-32BIT-P9-PRIV-NEXT:    hashchkp r0, -16(r1)
 ; BE-32BIT-P9-PRIV-NEXT:    blr
 ;
 ; BE-32BIT-P8-PRIV-LABEL: aligned:
 ; BE-32BIT-P8-PRIV:       # %bb.0: # %entry
 ; BE-32BIT-P8-PRIV-NEXT:    mflr r0
-; BE-32BIT-P8-PRIV-NEXT:    lis r12, -1
 ; BE-32BIT-P8-PRIV-NEXT:    stw r30, -8(r1)
+; BE-32BIT-P8-PRIV-NEXT:    lis r12, -1
 ; BE-32BIT-P8-PRIV-NEXT:    mr r30, r1
 ; BE-32BIT-P8-PRIV-NEXT:    stw r0, 8(r1)
 ; BE-32BIT-P8-PRIV-NEXT:    hashstp r0, -16(r1)
 ; BE-32BIT-P8-PRIV-NEXT:    clrlwi r0, r1, 17
-; BE-32BIT-P8-PRIV-NEXT:    ori r12, r12, 0
 ; BE-32BIT-P8-PRIV-NEXT:    subc r0, r12, r0
 ; BE-32BIT-P8-PRIV-NEXT:    stwux r1, r1, r0
 ; BE-32BIT-P8-PRIV-NEXT:    stw r31, -4(r30) # 4-byte Folded Spill
 ; BE-32BIT-P8-PRIV-NEXT:    mr r31, r3
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r3, 4(r3)
 ; BE-32BIT-P8-PRIV-NEXT:    lis r6, 0
 ; BE-32BIT-P8-PRIV-NEXT:    ori r6, r6, 65516
 ; BE-32BIT-P8-PRIV-NEXT:    lwz r4, 12(r31)

llvm/test/CodeGen/PowerPC/ppc64-rop-protection.ll

return:                                           ; preds = %entry, %if.end
   %retval.0 = phi i32 [ %add, %if.end ], [ 0, %entry ]
   ret i32 %retval.0
 }
 
 define dso_local zeroext i32 @aligned(i32* nocapture readonly %in) #0 {
 ; LE-P10-LABEL: aligned:
 ; LE-P10:       # %bb.0: # %entry
 ; LE-P10-NEXT:    mflr r0
-; LE-P10-NEXT:    lis r12, -1
 ; LE-P10-NEXT:    std r30, -16(r1)
+; LE-P10-NEXT:    lis r12, -1
 ; LE-P10-NEXT:    mr r30, r1
 ; LE-P10-NEXT:    std r0, 16(r1)
 ; LE-P10-NEXT:    hashst r0, -32(r1)
 ; LE-P10-NEXT:    clrldi r0, r1, 49
-; LE-P10-NEXT:    ori r12, r12, 0
 ; LE-P10-NEXT:    subc r0, r12, r0
 ; LE-P10-NEXT:    stdux r1, r1, r0
 ; LE-P10-NEXT:    std r29, -24(r30) # 8-byte Folded Spill
 ; LE-P10-NEXT:    mr r29, r3
 ; LE-P10-NEXT:    lwz r3, 4(r3)
 ; LE-P10-NEXT:    lis r4, 0
 ; LE-P10-NEXT:    addi r5, r1, 32764
 ; LE-P10-NEXT:    ori r4, r4, 65500

 ; LE-P10-NEXT:    ld r30, -16(r1)
 ; LE-P10-NEXT:    mtlr r0
 ; LE-P10-NEXT:    hashchk r0, -32(r1)
 ; LE-P10-NEXT:    blr
 ;
 ; LE-P9-LABEL: aligned:
 ; LE-P9:       # %bb.0: # %entry
 ; LE-P9-NEXT:    mflr r0
-; LE-P9-NEXT:    lis r12, -1
 ; LE-P9-NEXT:    std r30, -16(r1)
+; LE-P9-NEXT:    lis r12, -1
 ; LE-P9-NEXT:    mr r30, r1
-; LE-P9-NEXT:    ori r12, r12, 0
 ; LE-P9-NEXT:    std r0, 16(r1)
 ; LE-P9-NEXT:    hashst r0, -32(r1)
 ; LE-P9-NEXT:    clrldi r0, r1, 49
 ; LE-P9-NEXT:    subc r0, r12, r0
 ; LE-P9-NEXT:    stdux r1, r1, r0
 ; LE-P9-NEXT:    std r29, -24(r30) # 8-byte Folded Spill
 ; LE-P9-NEXT:    mr r29, r3
 ; LE-P9-NEXT:    lwz r3, 4(r3)

 ; LE-P9-NEXT:    ld r30, -16(r1)
 ; LE-P9-NEXT:    mtlr r0
 ; LE-P9-NEXT:    hashchk r0, -32(r1)
 ; LE-P9-NEXT:    blr
 ;
 ; LE-P8-LABEL: aligned:
 ; LE-P8:       # %bb.0: # %entry
 ; LE-P8-NEXT:    mflr r0
-; LE-P8-NEXT:    lis r12, -1
 ; LE-P8-NEXT:    std r30, -16(r1)
+; LE-P8-NEXT:    lis r12, -1
 ; LE-P8-NEXT:    mr r30, r1
 ; LE-P8-NEXT:    std r0, 16(r1)
 ; LE-P8-NEXT:    hashst r0, -32(r1)
 ; LE-P8-NEXT:    clrldi r0, r1, 49
-; LE-P8-NEXT:    ori r12, r12, 0
 ; LE-P8-NEXT:    subc r0, r12, r0
 ; LE-P8-NEXT:    stdux r1, r1, r0
 ; LE-P8-NEXT:    std r29, -24(r30) # 8-byte Folded Spill
 ; LE-P8-NEXT:    mr r29, r3
 ; LE-P8-NEXT:    lwz r3, 4(r3)
 ; LE-P8-NEXT:    lis r6, 0
 ; LE-P8-NEXT:    ori r6, r6, 65500
 ; LE-P8-NEXT:    lwz r4, 12(r29)

 ; LE-P10-O0:       # %bb.0: # %entry
 ; LE-P10-O0-NEXT:    mflr r0
 ; LE-P10-O0-NEXT:    std r30, -16(r1)
 ; LE-P10-O0-NEXT:    std r0, 16(r1)
 ; LE-P10-O0-NEXT:    hashst r0, -24(r1)
 ; LE-P10-O0-NEXT:    mr r30, r1
 ; LE-P10-O0-NEXT:    clrldi r0, r1, 49
 ; LE-P10-O0-NEXT:    lis r12, -1
-; LE-P10-O0-NEXT:    ori r12, r12, 0
 ; LE-P10-O0-NEXT:    subc r0, r12, r0
 ; LE-P10-O0-NEXT:    stdux r1, r1, r0
 ; LE-P10-O0-NEXT:    std r3, 32752(r1) # 8-byte Folded Spill
 ; LE-P10-O0-NEXT:    lwz r4, 4(r3)
 ; LE-P10-O0-NEXT:    lis r5, 0
 ; LE-P10-O0-NEXT:    ori r5, r5, 65508
 ; LE-P10-O0-NEXT:    stwx r4, r1, r5
 ; LE-P10-O0-NEXT:    lwz r4, 12(r3)

 ; LE-P9-O0:       # %bb.0: # %entry
 ; LE-P9-O0-NEXT:    mflr r0
 ; LE-P9-O0-NEXT:    std r30, -16(r1)
 ; LE-P9-O0-NEXT:    std r0, 16(r1)
 ; LE-P9-O0-NEXT:    hashst r0, -24(r1)
 ; LE-P9-O0-NEXT:    mr r30, r1
 ; LE-P9-O0-NEXT:    clrldi r0, r1, 49
 ; LE-P9-O0-NEXT:    lis r12, -1
-; LE-P9-O0-NEXT:    ori r12, r12, 0
 ; LE-P9-O0-NEXT:    subc r0, r12, r0
 ; LE-P9-O0-NEXT:    stdux r1, r1, r0
 ; LE-P9-O0-NEXT:    std r3, 32752(r1) # 8-byte Folded Spill
 ; LE-P9-O0-NEXT:    lwz r4, 4(r3)
 ; LE-P9-O0-NEXT:    lis r5, 0
 ; LE-P9-O0-NEXT:    ori r5, r5, 65508
 ; LE-P9-O0-NEXT:    stwx r4, r1, r5
 ; LE-P9-O0-NEXT:    lwz r4, 12(r3)

 ; LE-P8-O0:       # %bb.0: # %entry
 ; LE-P8-O0-NEXT:    mflr r0
 ; LE-P8-O0-NEXT:    std r30, -16(r1)
 ; LE-P8-O0-NEXT:    std r0, 16(r1)
 ; LE-P8-O0-NEXT:    hashst r0, -24(r1)
 ; LE-P8-O0-NEXT:    mr r30, r1
 ; LE-P8-O0-NEXT:    clrldi r0, r1, 49
 ; LE-P8-O0-NEXT:    lis r12, -1
-; LE-P8-O0-NEXT:    ori r12, r12, 0
 ; LE-P8-O0-NEXT:    subc r0, r12, r0
 ; LE-P8-O0-NEXT:    stdux r1, r1, r0
 ; LE-P8-O0-NEXT:    std r3, 32752(r1) # 8-byte Folded Spill
 ; LE-P8-O0-NEXT:    lwz r4, 4(r3)
 ; LE-P8-O0-NEXT:    lis r5, 0
 ; LE-P8-O0-NEXT:    ori r5, r5, 65508
 ; LE-P8-O0-NEXT:    stwx r4, r1, r5
 ; LE-P8-O0-NEXT:    lwz r4, 12(r3)

 ; LE-P8-O0-NEXT:    ld r30, -16(r1)
 ; LE-P8-O0-NEXT:    hashchk r0, -24(r1)
 ; LE-P8-O0-NEXT:    mtlr r0
 ; LE-P8-O0-NEXT:    blr
 ;
 ; BE-P10-LABEL: aligned:
 ; BE-P10:       # %bb.0: # %entry
 ; BE-P10-NEXT:    mflr r0
-; BE-P10-NEXT:    lis r12, -1
 ; BE-P10-NEXT:    std r30, -16(r1)
+; BE-P10-NEXT:    lis r12, -1
 ; BE-P10-NEXT:    mr r30, r1
 ; BE-P10-NEXT:    std r0, 16(r1)
 ; BE-P10-NEXT:    hashst r0, -32(r1)
 ; BE-P10-NEXT:    clrldi r0, r1, 49
-; BE-P10-NEXT:    ori r12, r12, 0
 ; BE-P10-NEXT:    subc r0, r12, r0
 ; BE-P10-NEXT:    stdux r1, r1, r0
 ; BE-P10-NEXT:    std r29, -24(r30) # 8-byte Folded Spill
 ; BE-P10-NEXT:    mr r29, r3
 ; BE-P10-NEXT:    lwz r3, 4(r3)
 ; BE-P10-NEXT:    lis r4, 0
 ; BE-P10-NEXT:    addi r5, r1, 32764
 ; BE-P10-NEXT:    ori r4, r4, 65500

 ; BE-P10-NEXT:    ld r30, -16(r1)
 ; BE-P10-NEXT:    mtlr r0
 ; BE-P10-NEXT:    hashchk r0, -32(r1)
 ; BE-P10-NEXT:    blr
 ;
 ; BE-P9-LABEL: aligned:
 ; BE-P9:       # %bb.0: # %entry
 ; BE-P9-NEXT:    mflr r0
-; BE-P9-NEXT:    lis r12, -1
 ; BE-P9-NEXT:    std r30, -16(r1)
+; BE-P9-NEXT:    lis r12, -1
 ; BE-P9-NEXT:    mr r30, r1
-; BE-P9-NEXT:    ori r12, r12, 0
 ; BE-P9-NEXT:    std r0, 16(r1)
 ; BE-P9-NEXT:    hashst r0, -32(r1)
 ; BE-P9-NEXT:    clrldi r0, r1, 49
 ; BE-P9-NEXT:    subc r0, r12, r0
 ; BE-P9-NEXT:    stdux r1, r1, r0
 ; BE-P9-NEXT:    std r29, -24(r30) # 8-byte Folded Spill
 ; BE-P9-NEXT:    mr r29, r3
 ; BE-P9-NEXT:    lwz r3, 4(r3)

 ; BE-P9-NEXT:    ld r30, -16(r1)
 ; BE-P9-NEXT:    mtlr r0
 ; BE-P9-NEXT:    hashchk r0, -32(r1)
 ; BE-P9-NEXT:    blr
 ;
 ; BE-P8-LABEL: aligned:
 ; BE-P8:       # %bb.0: # %entry
 ; BE-P8-NEXT:    mflr r0
-; BE-P8-NEXT:    lis r12, -1
 ; BE-P8-NEXT:    std r30, -16(r1)
+; BE-P8-NEXT:    lis r12, -1
 ; BE-P8-NEXT:    mr r30, r1
 ; BE-P8-NEXT:    std r0, 16(r1)
 ; BE-P8-NEXT:    hashst r0, -32(r1)
 ; BE-P8-NEXT:    clrldi r0, r1, 49
-; BE-P8-NEXT:    ori r12, r12, 0
 ; BE-P8-NEXT:    subc r0, r12, r0
 ; BE-P8-NEXT:    stdux r1, r1, r0
 ; BE-P8-NEXT:    std r29, -24(r30) # 8-byte Folded Spill
 ; BE-P8-NEXT:    mr r29, r3
 ; BE-P8-NEXT:    lwz r3, 4(r3)
 ; BE-P8-NEXT:    lis r6, 0
 ; BE-P8-NEXT:    ori r6, r6, 65500
 ; BE-P8-NEXT:    lwz r4, 12(r29)

 ;
 ; BE-32BIT-P10-LABEL: aligned:
 ; BE-32BIT-P10:       # %bb.0: # %entry
 ; BE-32BIT-P10-NEXT:    mflr r0
 ; BE-32BIT-P10-NEXT:    lis r12, -1
 ; BE-32BIT-P10-NEXT:    stw r0, 4(r1)
 ; BE-32BIT-P10-NEXT:    hashst r0, -24(r1)
 ; BE-32BIT-P10-NEXT:    clrlwi r0, r1, 17
-; BE-32BIT-P10-NEXT:    ori r12, r12, 0
 ; BE-32BIT-P10-NEXT:    subc r0, r12, r0
 ; BE-32BIT-P10-NEXT:    stwux r1, r1, r0
 ; BE-32BIT-P10-NEXT:    sub r0, r1, r0
 ; BE-32BIT-P10-NEXT:    lis r4, 0
 ; BE-32BIT-P10-NEXT:    addi r5, r1, 32764
 ; BE-32BIT-P10-NEXT:    addic r0, r0, -8
 ; BE-32BIT-P10-NEXT:    ori r4, r4, 65508
 ; BE-32BIT-P10-NEXT:    stwx r30, 0, r0

 ; BE-32BIT-P10-NEXT:    hashchk r0, -24(r1)
 ; BE-32BIT-P10-NEXT:    mtlr r0
 ; BE-32BIT-P10-NEXT:    blr
 ;
 ; BE-32BIT-P9-LABEL: aligned:
 ; BE-32BIT-P9:       # %bb.0: # %entry
 ; BE-32BIT-P9-NEXT:    mflr r0
 ; BE-32BIT-P9-NEXT:    lis r12, -1
-; BE-32BIT-P9-NEXT:    ori r12, r12, 0
 ; BE-32BIT-P9-NEXT:    stw r0, 4(r1)
 ; BE-32BIT-P9-NEXT:    hashst r0, -24(r1)
 ; BE-32BIT-P9-NEXT:    clrlwi r0, r1, 17
 ; BE-32BIT-P9-NEXT:    subc r0, r12, r0
 ; BE-32BIT-P9-NEXT:    stwux r1, r1, r0
 ; BE-32BIT-P9-NEXT:    sub r0, r1, r0
 ; BE-32BIT-P9-NEXT:    lis r4, 0
 ; BE-32BIT-P9-NEXT:    addi r5, r1, 32764

 ;
 ; BE-32BIT-P8-LABEL: aligned:
 ; BE-32BIT-P8:       # %bb.0: # %entry
 ; BE-32BIT-P8-NEXT:    mflr r0
 ; BE-32BIT-P8-NEXT:    lis r12, -1
 ; BE-32BIT-P8-NEXT:    stw r0, 4(r1)
 ; BE-32BIT-P8-NEXT:    hashst r0, -24(r1)
 ; BE-32BIT-P8-NEXT:    clrlwi r0, r1, 17
-; BE-32BIT-P8-NEXT:    ori r12, r12, 0
 ; BE-32BIT-P8-NEXT:    subc r0, r12, r0
 ; BE-32BIT-P8-NEXT:    stwux r1, r1, r0
 ; BE-32BIT-P8-NEXT:    sub r0, r1, r0
 ; BE-32BIT-P8-NEXT:    lis r6, 0
 ; BE-32BIT-P8-NEXT:    addic r0, r0, -8
 ; BE-32BIT-P8-NEXT:    ori r6, r6, 65508
 ; BE-32BIT-P8-NEXT:    stwx r30, 0, r0
 ; BE-32BIT-P8-NEXT:    addic r30, r0, 8

 ; BE-32BIT-P8-NEXT:    lwz r0, 4(r1)
 ; BE-32BIT-P8-NEXT:    hashchk r0, -24(r1)
 ; BE-32BIT-P8-NEXT:    mtlr r0
 ; BE-32BIT-P8-NEXT:    blr
 ;
 ; LE-P10-PRIV-LABEL: aligned:
 ; LE-P10-PRIV:       # %bb.0: # %entry
 ; LE-P10-PRIV-NEXT:    mflr r0
-; LE-P10-PRIV-NEXT:    lis r12, -1
 ; LE-P10-PRIV-NEXT:    std r30, -16(r1)
+; LE-P10-PRIV-NEXT:    lis r12, -1
 ; LE-P10-PRIV-NEXT:    mr r30, r1
 ; LE-P10-PRIV-NEXT:    std r0, 16(r1)
 ; LE-P10-PRIV-NEXT:    hashstp r0, -32(r1)
 ; LE-P10-PRIV-NEXT:    clrldi r0, r1, 49
-; LE-P10-PRIV-NEXT:    ori r12, r12, 0
 ; LE-P10-PRIV-NEXT:    subc r0, r12, r0
 ; LE-P10-PRIV-NEXT:    stdux r1, r1, r0
 ; LE-P10-PRIV-NEXT:    std r29, -24(r30) # 8-byte Folded Spill
 ; LE-P10-PRIV-NEXT:    mr r29, r3
 ; LE-P10-PRIV-NEXT:    lwz r3, 4(r3)
 ; LE-P10-PRIV-NEXT:    lis r4, 0
 ; LE-P10-PRIV-NEXT:    addi r5, r1, 32764
 ; LE-P10-PRIV-NEXT:    ori r4, r4, 65500

 ; LE-P10-PRIV-NEXT:    ld r30, -16(r1)
 ; LE-P10-PRIV-NEXT:    mtlr r0
 ; LE-P10-PRIV-NEXT:    hashchkp r0, -32(r1)
 ; LE-P10-PRIV-NEXT:    blr
 ;
 ; LE-P9-PRIV-LABEL: aligned:
 ; LE-P9-PRIV:       # %bb.0: # %entry
 ; LE-P9-PRIV-NEXT:    mflr r0
-; LE-P9-PRIV-NEXT:    lis r12, -1
 ; LE-P9-PRIV-NEXT:    std r30, -16(r1)
+; LE-P9-PRIV-NEXT:    lis r12, -1
 ; LE-P9-PRIV-NEXT:    mr r30, r1
-; LE-P9-PRIV-NEXT:    ori r12, r12, 0
 ; LE-P9-PRIV-NEXT:    std r0, 16(r1)
 ; LE-P9-PRIV-NEXT:    hashstp r0, -32(r1)
 ; LE-P9-PRIV-NEXT:    clrldi r0, r1, 49
 ; LE-P9-PRIV-NEXT:    subc r0, r12, r0
 ; LE-P9-PRIV-NEXT:    stdux r1, r1, r0
 ; LE-P9-PRIV-NEXT:    std r29, -24(r30) # 8-byte Folded Spill
 ; LE-P9-PRIV-NEXT:    mr r29, r3
 ; LE-P9-PRIV-NEXT:    lwz r3, 4(r3)

 ; LE-P9-PRIV-NEXT:    ld r30, -16(r1)
 ; LE-P9-PRIV-NEXT:    mtlr r0
 ; LE-P9-PRIV-NEXT:    hashchkp r0, -32(r1)
 ; LE-P9-PRIV-NEXT:    blr
 ;
 ; LE-P8-PRIV-LABEL: aligned:
 ; LE-P8-PRIV:       # %bb.0: # %entry
 ; LE-P8-PRIV-NEXT:    mflr r0
-; LE-P8-PRIV-NEXT:    lis r12, -1
 ; LE-P8-PRIV-NEXT:    std r30, -16(r1)
+; LE-P8-PRIV-NEXT:    lis r12, -1
 ; LE-P8-PRIV-NEXT:    mr r30, r1
 ; LE-P8-PRIV-NEXT:    std r0, 16(r1)
 ; LE-P8-PRIV-NEXT:    hashstp r0, -32(r1)
 ; LE-P8-PRIV-NEXT:    clrldi r0, r1, 49
-; LE-P8-PRIV-NEXT:    ori r12, r12, 0
 ; LE-P8-PRIV-NEXT:    subc r0, r12, r0
 ; LE-P8-PRIV-NEXT:    stdux r1, r1, r0
 ; LE-P8-PRIV-NEXT:    std r29, -24(r30) # 8-byte Folded Spill
 ; LE-P8-PRIV-NEXT:    mr r29, r3
 ; LE-P8-PRIV-NEXT:    lwz r3, 4(r3)
 ; LE-P8-PRIV-NEXT:    lis r6, 0
 ; LE-P8-PRIV-NEXT:    ori r6, r6, 65500
 ; LE-P8-PRIV-NEXT:    lwz r4, 12(r29)

 ; LE-P8-PRIV-NEXT:    ld r30, -16(r1)
 ; LE-P8-PRIV-NEXT:    hashchkp r0, -32(r1)
 ; LE-P8-PRIV-NEXT:    mtlr r0
 ; LE-P8-PRIV-NEXT:    blr
 ;
 ; BE-P10-PRIV-LABEL: aligned:
 ; BE-P10-PRIV:       # %bb.0: # %entry
 ; BE-P10-PRIV-NEXT:    mflr r0
-; BE-P10-PRIV-NEXT:    lis r12, -1
 ; BE-P10-PRIV-NEXT:    std r30, -16(r1)
+; BE-P10-PRIV-NEXT:    lis r12, -1
 ; BE-P10-PRIV-NEXT:    mr r30, r1
 ; BE-P10-PRIV-NEXT:    std r0, 16(r1)
 ; BE-P10-PRIV-NEXT:    hashstp r0, -32(r1)
 ; BE-P10-PRIV-NEXT:    clrldi r0, r1, 49
-; BE-P10-PRIV-NEXT:    ori r12, r12, 0
 ; BE-P10-PRIV-NEXT:    subc r0, r12, r0
 ; BE-P10-PRIV-NEXT:    stdux r1, r1, r0
 ; BE-P10-PRIV-NEXT:    std r29, -24(r30) # 8-byte Folded Spill
 ; BE-P10-PRIV-NEXT:    mr r29, r3
 ; BE-P10-PRIV-NEXT:    lwz r3, 4(r3)
 ; BE-P10-PRIV-NEXT:    lis r4, 0
 ; BE-P10-PRIV-NEXT:    addi r5, r1, 32764
 ; BE-P10-PRIV-NEXT:    ori r4, r4, 65500

 ; BE-P10-PRIV-NEXT:    ld r30, -16(r1)
 ; BE-P10-PRIV-NEXT:    mtlr r0
 ; BE-P10-PRIV-NEXT:    hashchkp r0, -32(r1)
 ; BE-P10-PRIV-NEXT:    blr
 ;
 ; BE-P9-PRIV-LABEL: aligned:
 ; BE-P9-PRIV:       # %bb.0: # %entry
 ; BE-P9-PRIV-NEXT:    mflr r0
-; BE-P9-PRIV-NEXT:    lis r12, -1
 ; BE-P9-PRIV-NEXT:    std r30, -16(r1)
+; BE-P9-PRIV-NEXT:    lis r12, -1
 ; BE-P9-PRIV-NEXT:    mr r30, r1
-; BE-P9-PRIV-NEXT:    ori r12, r12, 0
 ; BE-P9-PRIV-NEXT:    std r0, 16(r1)
 ; BE-P9-PRIV-NEXT:    hashstp r0, -32(r1)
 ; BE-P9-PRIV-NEXT:    clrldi r0, r1, 49
 ; BE-P9-PRIV-NEXT:    subc r0, r12, r0
 ; BE-P9-PRIV-NEXT:    stdux r1, r1, r0
 ; BE-P9-PRIV-NEXT:    std r29, -24(r30) # 8-byte Folded Spill
 ; BE-P9-PRIV-NEXT:    mr r29, r3
 ; BE-P9-PRIV-NEXT:    lwz r3, 4(r3)

 ; BE-P9-PRIV-NEXT:    ld r30, -16(r1)
 ; BE-P9-PRIV-NEXT:    mtlr r0
 ; BE-P9-PRIV-NEXT:    hashchkp r0, -32(r1)
 ; BE-P9-PRIV-NEXT:    blr
 ;
 ; BE-P8-PRIV-LABEL: aligned:
 ; BE-P8-PRIV:       # %bb.0: # %entry
 ; BE-P8-PRIV-NEXT:    mflr r0
-; BE-P8-PRIV-NEXT:    lis r12, -1
 ; BE-P8-PRIV-NEXT:    std r30, -16(r1)
+; BE-P8-PRIV-NEXT:    lis r12, -1
 ; BE-P8-PRIV-NEXT:    mr r30, r1
 ; BE-P8-PRIV-NEXT:    std r0, 16(r1)
 ; BE-P8-PRIV-NEXT:    hashstp r0, -32(r1)
 ; BE-P8-PRIV-NEXT:    clrldi r0, r1, 49
-; BE-P8-PRIV-NEXT:    ori r12, r12, 0
 ; BE-P8-PRIV-NEXT:    subc r0, r12, r0
 ; BE-P8-PRIV-NEXT:    stdux r1, r1, r0
 ; BE-P8-PRIV-NEXT:    std r29, -24(r30) # 8-byte Folded Spill
 ; BE-P8-PRIV-NEXT:    mr r29, r3
 ; BE-P8-PRIV-NEXT:    lwz r3, 4(r3)
 ; BE-P8-PRIV-NEXT:    lis r6, 0
 ; BE-P8-PRIV-NEXT:    ori r6, r6, 65500
 ; BE-P8-PRIV-NEXT:    lwz r4, 12(r29)