[PowerPC] [NFC] Add Big-Endian checks for existing MMA tests

[saghir]

Summary

This patch adds Big-Endian checks for the existing MMA test cases.
It also changes the target for these test cases to pwr10.

[qiucf]

clang/test/CodeGen/builtins-ppc-pair-mma.c

5

Seems just adding %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 -emit-llvm %s -o - | FileCheck %s also makes the test pass. CHECK and CHECK-BE contents are the same.

[nemanjai]

LGTM. Please update the description and commit message as to why this is being added.

clang/test/CodeGen/builtins-ppc-pair-mma.c

5

The existing builtins produce the same IR but I think this is done in preparation for https://reviews.llvm.org/D107647 which will add builtins very similar to these but that produce different IR on LE and BE. The description of the patch should probably mention that.

[lei]

Is it really necessary to add the BE checks in this patch if they are the same as LE checks? Why not just add it later when there is a diff seen?

[saghir]

Addressed review comments.

[saghir]

clang/test/CodeGen/builtins-ppc-pair-mma.c

5

Since all the builtins in this file produce the same output for LE and BE, it's probably better to add checks for the new builtins (having different output for LE/BE) in a separate file.

[saghir]

Rebased.

[saghir]

Rebased before commit.

clang/test/CodeGen/builtins-ppc-pair-mma.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:  -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
 
 // CHECK-LABEL: @test1(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], <16 x i8> [[VC]], <16 x i8> [[VC]])
 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
 // CHECK-NEXT:    store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2:![0-9]+]]
 // CHECK-NEXT:    ret void
 //

clang/test/Sema/ppc-pair-mma-types.c

 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -target-cpu future %s -verify
+// RUN:   -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -target-cpu pwr10 %s -verify
 
 // The use of PPC MMA types is strongly restricted. Non-pointer MMA variables
 // can only be declared in functions and a limited number of operations are
 // supported on these types. This test case checks that invalid uses of MMA
 // types are correctly prevented.
 
 // vector quad
 

clang/test/SemaCXX/ppc-pair-mma-types.cpp

 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -fcxx-exceptions -target-cpu future %s -verify
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN:   -fcxx-exceptions -target-cpu pwr10 %s -verify
 
 // vector quad
 
 // alias
 using vq_t = __vector_quad;
 void testVQAlias(int *inp, int *outp) {
   vq_t *vqin = (vq_t *)inp;
   vq_t *vqout = (vq_t *)outp;