[RISCV] Implement CSR mseccfg for spec Smepmp

[QuarticCat]

Summary

This revision implements CSR mseccfg for RISCV according to the specification of version 0.9.4.

[jrtc27]

Commit message is missing an m from mseccfg.

The name also concerns me, "security config" is extremely broad, so it's not clear it applies specifically to PMP things and it could get confused with other security-related extensions.

llvm/lib/Target/RISCV/RISCVSystemOperands.td

254

The definitions here are grouped in the same way that they are in the privileged spec. Is the intent that these CSRs will be part of the same group as the existing PMP registers in the table in the CSR Listings section of the spec (table 2.5 in my build from earlier this year)?

[QuarticCat]

llvm/lib/Target/RISCV/RISCVSystemOperands.td

254

I emailed Nick Kossifidis, here is the response:

Initialy mseccfg was in the same group with the rest of PMP registers (pmpcfg/pmpaddr) but later on, during review, the address was re-assigned and since it's a single allocation it doesn't belong to any of the groups on that table. I don't know if there is a plan to introduce a new group for small allocations in the future but I can ask if you want.

[asb]

Only minor comment is that if the CSR isn't in the mainline privileged specification, it would be worth adding a comment in RISCVSystemOperands.td explaining where it's defined.

llvm/lib/Target/RISCV/RISCVSystemOperands.td

 def : SysReg<"pmpaddr9", 0x3B9>;
 def : SysReg<"pmpaddr10", 0x3BA>;
 def : SysReg<"pmpaddr11", 0x3BB>;
 def : SysReg<"pmpaddr12", 0x3BC>;
 def : SysReg<"pmpaddr13", 0x3BD>;
 def : SysReg<"pmpaddr14", 0x3BE>;
 def : SysReg<"pmpaddr15", 0x3BF>;
 
+def : SysReg<"mseccfg", 0x747>;
+let isRV32Only = 1 in
+def : SysReg<"mseccfgh", 0x757>;
 
 //===--------------------------
 // Machine Counter and Timers
 //===--------------------------
 def : SysReg<"mcycle", 0xB00>;
 def : SysReg<"minstret", 0xB02>;
 
 def : SysReg<"mhpmcounter3", 0xB03>;

llvm/test/MC/RISCV/machine-csr-names.s

 # CHECK-INST: csrrs t2, pmpcfg2, zero
 # CHECK-ENC: encoding: [0xf3,0x23,0x20,0x3a]
 # CHECK-INST-ALIAS: csrr t2, pmpcfg2
 # name
 csrrs t1, pmpcfg2, zero
 # uimm12
 csrrs t2, 0x3A2, zero
 
+# mseccfg
+# name
+# CHECK-INST: csrrs t1, mseccfg, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x70,0x74]
+# CHECK-INST-ALIAS: csrr t1, mseccfg
+# uimm12
+# CHECK-INST: csrrs t2, mseccfg, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x70,0x74]
+# CHECK-INST-ALIAS: csrr t2, mseccfg
+# name
+csrrs t1, mseccfg, zero
+# uimm12
+csrrs t2, 0x747, zero
 
 ######################################
 # Machine Counter and Timers
 ######################################
 # mcycle
 # name
 # CHECK-INST: csrrs t1, mcycle, zero
 # CHECK-ENC: encoding: [0x73,0x23,0x00,0xb0]

llvm/test/MC/RISCV/rv32-machine-csr-names.s

 # CHECK-INST: csrrs t2, pmpcfg3, zero
 # CHECK-ENC: encoding: [0xf3,0x23,0x30,0x3a]
 # CHECK-INST-ALIAS: csrr t2, pmpcfg3
 # name
 csrrs t1, pmpcfg3, zero
 # uimm12
 csrrs t2, 0x3A3, zero
 
+# mseccfgh
+# name
+# CHECK-INST: csrrs t1, mseccfgh, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x70,0x75]
+# CHECK-INST-ALIAS: csrr t1, mseccfgh
+# uimm12
+# CHECK-INST: csrrs t2, mseccfgh, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x70,0x75]
+# CHECK-INST-ALIAS: csrr t2, mseccfgh
+# name
+csrrs t1, mseccfgh, zero
+# uimm12
+csrrs t2, 0x757, zero
+
 ######################################
 # Machine Counter and Timers
 ######################################
 # mcycleh
 # name
 # CHECK-INST: csrrs t1, mcycleh, zero
 # CHECK-ENC: encoding: [0x73,0x23,0x00,0xb8]
 # CHECK-INST-ALIAS: csrr t1, mcycleh

llvm/test/MC/RISCV/rv64-machine-csr-names.s

 
 # pmpcfg3
 # uimm12
 # CHECK-INST: csrrs t2, 931, zero
 # CHECK-ENC: encoding: [0xf3,0x23,0x30,0x3a]
 # CHECK-INST-ALIAS: csrr t2, 931
 csrrs t2, 0x3A3, zero
 
+# mseccfgh
+# uimm12
+# CHECK-INST: csrrs t2, 1879, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x70,0x75]
+# CHECK-INST-ALIAS: csrr t2, 1879
+csrrs t2, 0x757, zero
+
 ######################################
 # Machine Counter and Timers
 ######################################
 # mcycleh
 # uimm12
 # CHECK-INST: csrrs t2, 2944, zero
 # CHECK-ENC: encoding: [0xf3,0x23,0x00,0xb8]
 # CHECK-INST-ALIAS: csrr t2, 2944