[X86][SchedModels] Fix missing ReadAdvance for MULX and ADCX/ADOX (PR51494)

[andreadb]

Summary

Before this patch, instructions MULX32rm and MULX64rm were missing a ReadAdvance for the implicit read of register EDX/RDX.
This patch fixes the issue, and it also adds a ReadAdvance for the implicit read of EFLAGS in ADCX/ADOX.

This patch also introduces a new SchedWrite for the MULX variants. By using those writes, we can get rid of most InstRW in the Zen models. The only exception is the Zen3 model, for which an InstRW is still required to override the RM variants of MULX.
Another minor advantage of using these new SchedWrites is that we can now correctly mark MULX as unsupported on models used by targets that don't feature BMI2.

While doing this minor refactoring, I noticed (and fixed) an inconsistency in the throughput numbers reported by zen1 models for MULX64. Specifically, the MULX64 variant didn't correctly declare resources, and it had an unrealistic throughput. That issue also affected the zen2 model (I suspect a copy-paste mistake; most definitions in zen2 seems copied straight from zen1 modulo a small rename of substring Zn to Zn2).
The new values now correctly match what is reported in the AMD SOG official document for family 17th.

[RKSimon]

@lebedev.ri Are you OK with the znver changes?

llvm/lib/Target/X86/X86ScheduleZnver3.td

631

its weird that the rm variant uses the Zn3Multiplier pipe for an extra cycle......

[lebedev.ri]

Just checking: we don't have this problem with SBB?

In D108372#2957412, @RKSimon wrote:

@lebedev.ri Are you OK with the znver changes?

znver3 seems fine, thanks.

llvm/lib/Target/X86/X86ScheduleZnver3.td

631

Yes, but i'm pretty sure this is not a typo.
There might be modelling problems in mca/exegesis, so it might be spurious.

[andreadb]

llvm/lib/Target/X86/X86ScheduleZnver3.td

631

Yeah. That is basically the reason why I couldn't remove the InstRW from the znver3 model.

I also wonder why there is an extra Zn3Multiplier cycle only for the RM variants. Normally, you would expect the RM variants to semantically behave like a Load+RR sequence.

Maybe it was done intentionally, to artificially decrease the throughput of the MULX RM variants only (in order to better match the exegesis report).

[lebedev.ri]

llvm/lib/Target/X86/X86ScheduleZnver3.td

631

Maybe it was done intentionally, to artificially decrease the throughput of the MULX RM variants only (in order to better match the exegesis report).

Yep, that was my comment precisely.

[andreadb]

In D108372#2957430, @lebedev.ri wrote:

Just checking: we don't have this problem with SBB?

Sorry. I missed that first question.

SBB was already fixed by this commit: https://reviews.llvm.org/rG7a1a35a1d1ae2e69769505c9f39910067c53d53b
That was the commit that fixed PR51318 and PR51322.

[lebedev.ri]

In D108372#2957460, @andreadb wrote:

In D108372#2957430, @lebedev.ri wrote:

Just checking: we don't have this problem with SBB?

Sorry. I missed that first question.

SBB was already fixed by this commit: https://reviews.llvm.org/rG7a1a35a1d1ae2e69769505c9f39910067c53d53b
That was the commit that fixed PR51318 and PR51322.

Aha, i thought it was.

LG to me, thank you.

@RKSimon ?

[RKSimon]

LGTM - cheers!

llvm/lib/Target/X86/X86InstrArithmetic.td

 let hasSideEffects = 0 in {
   def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src),
              !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
              []>, T8XD, VEX_4V, Sched<[sched, WriteIMulH]>;
 
   let mayLoad = 1 in
   def rm : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src),
              !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
-
-             []>, T8XD, VEX_4V, Sched<[sched.Folded, WriteIMulH]>;
+             []>, T8XD, VEX_4V,
+             Sched<[sched.Folded, WriteIMulH,
+                    // Memory operand.
+                    ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
+                    // Implicit read of EDX/RDX
+                    sched.ReadAfterFold]>;
 
   // Pseudo instructions to be used when the low result isn't used. The
   // instruction is defined to keep the high if both destinations are the same.
   def Hrr : PseudoI<(outs RC:$dst), (ins RC:$src),
                     []>, Sched<[sched]>;
 
   let mayLoad = 1 in
   def Hrm : PseudoI<(outs RC:$dst), (ins x86memop:$src),
                     []>, Sched<[sched.Folded]>;
 }
 }
 
 let Predicates = [HasBMI2] in {
   let Uses = [EDX] in
-    defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem, WriteIMul32>;
+    defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem, WriteMULX32>;
   let Uses = [RDX] in
-    defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem, WriteIMul64>, VEX_W;
+    defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem, WriteMULX64>, VEX_W;
 }
 
 //===----------------------------------------------------------------------===//
 // ADCX and ADOX Instructions
 //
 // We don't have patterns for these as there is no advantage over ADC for
 // most code.
 let Predicates = [HasADX], Defs = [EFLAGS], Uses = [EFLAGS],
def ADOX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst),
                    (ins GR32:$src1, GR32:$src2),
                    "adox{l}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
 
   def ADOX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst),
                     (ins GR64:$src1, GR64:$src2),
                     "adox{q}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
   } // SchedRW
 
-  let mayLoad = 1, SchedRW = [WriteADC.Folded, WriteADC.ReadAfterFold] in {
+  let mayLoad = 1,
+      SchedRW = [WriteADC.Folded, WriteADC.ReadAfterFold,
+                 // Memory operand.
+                 ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
+                 // Implicit read of EFLAGS
+                 WriteADC.ReadAfterFold] in {
   def ADCX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst),
                    (ins GR32:$src1, i32mem:$src2),
                    "adcx{l}\t{$src2, $dst|$dst, $src2}", []>, T8PD;
 
   def ADCX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst),
                     (ins GR64:$src1, i64mem:$src2),
                     "adcx{q}\t{$src2, $dst|$dst, $src2}", []>, T8PD;
 

llvm/lib/Target/X86/X86SchedBroadwell.td

 
 // Integer multiplication.
 defm : BWWriteResPair<WriteIMul8,     [BWPort1],   3>;
 defm : BWWriteResPair<WriteIMul16,    [BWPort1,BWPort06,BWPort0156], 4, [1,1,2], 4>;
 defm : X86WriteRes<WriteIMul16Imm,    [BWPort1,BWPort0156], 4, [1,1], 2>;
 defm : X86WriteRes<WriteIMul16ImmLd,  [BWPort1,BWPort0156,BWPort23], 8, [1,1,1], 3>;
 defm : BWWriteResPair<WriteIMul16Reg, [BWPort1],   3>;
 defm : BWWriteResPair<WriteIMul32,    [BWPort1,BWPort06,BWPort0156], 4, [1,1,1], 3>;
+defm : BWWriteResPair<WriteMULX32,    [BWPort1,BWPort06,BWPort0156], 4, [1,1,1], 3>;
 defm : BWWriteResPair<WriteIMul32Imm, [BWPort1],   3>;
 defm : BWWriteResPair<WriteIMul32Reg, [BWPort1],   3>;
 defm : BWWriteResPair<WriteIMul64,    [BWPort1,BWPort5], 4, [1,1], 2>;
+defm : BWWriteResPair<WriteMULX64,    [BWPort1,BWPort5], 4, [1,1], 2>;
 defm : BWWriteResPair<WriteIMul64Imm, [BWPort1],   3>;
 defm : BWWriteResPair<WriteIMul64Reg, [BWPort1],   3>;
 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
 
 // TODO: Why isn't the BWDivider used consistently?
 defm : X86WriteRes<WriteDiv8,      [BWPort0, BWDivider], 25, [1, 10], 1>;
 defm : X86WriteRes<WriteDiv16,     [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;
 defm : X86WriteRes<WriteDiv32,     [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;

llvm/lib/Target/X86/X86SchedHaswell.td

 
 // Integer multiplication.
 defm : HWWriteResPair<WriteIMul8,     [HWPort1],   3>;
 defm : HWWriteResPair<WriteIMul16,    [HWPort1,HWPort06,HWPort0156], 4, [1,1,2], 4>;
 defm : X86WriteRes<WriteIMul16Imm,    [HWPort1,HWPort0156], 4, [1,1], 2>;
 defm : X86WriteRes<WriteIMul16ImmLd,  [HWPort1,HWPort0156,HWPort23], 8, [1,1,1], 3>;
 defm : HWWriteResPair<WriteIMul16Reg, [HWPort1],   3>;
 defm : HWWriteResPair<WriteIMul32,    [HWPort1,HWPort06,HWPort0156], 4, [1,1,1], 3>;
+defm : HWWriteResPair<WriteMULX32,    [HWPort1,HWPort06,HWPort0156], 4, [1,1,1], 3>;
 defm : HWWriteResPair<WriteIMul32Imm, [HWPort1],   3>;
 defm : HWWriteResPair<WriteIMul32Reg, [HWPort1],   3>;
 defm : HWWriteResPair<WriteIMul64,    [HWPort1,HWPort6], 4, [1,1], 2>;
+defm : HWWriteResPair<WriteMULX64,    [HWPort1,HWPort6], 4, [1,1], 2>;
 defm : HWWriteResPair<WriteIMul64Imm, [HWPort1],   3>;
 defm : HWWriteResPair<WriteIMul64Reg, [HWPort1],   3>;
 def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
 
 defm : X86WriteRes<WriteBSWAP32,   [HWPort15], 1, [1], 1>;
 defm : X86WriteRes<WriteBSWAP64,   [HWPort06, HWPort15], 2, [1,1], 2>;
 defm : X86WriteRes<WriteCMPXCHG,[HWPort06, HWPort0156], 5, [2,3], 5>;
 defm : X86WriteRes<WriteCMPXCHGRMW,[HWPort23,HWPort06,HWPort0156,HWPort237,HWPort4], 9, [1,2,1,1,1], 6>;

llvm/lib/Target/X86/X86SchedSandyBridge.td

 defm : SBWriteResPair<WriteADC,    [SBPort05,SBPort015], 2, [1,1], 2>;
 
 defm : SBWriteResPair<WriteIMul8,     [SBPort1],   3>;
 defm : SBWriteResPair<WriteIMul16,    [SBPort1,SBPort05,SBPort015], 4, [1,1,2], 4>;
 defm : X86WriteRes<WriteIMul16Imm,    [SBPort1,SBPort015], 4, [1,1], 2>;
 defm : X86WriteRes<WriteIMul16ImmLd,  [SBPort1,SBPort015,SBPort23], 8, [1,1,1], 3>;
 defm : SBWriteResPair<WriteIMul16Reg, [SBPort1],   3>;
 defm : SBWriteResPair<WriteIMul32,    [SBPort1,SBPort05,SBPort015], 4, [1,1,1], 3>;
+defm : SBWriteResPair<WriteMULX32,    [SBPort1,SBPort05,SBPort015], 4, [1,1,1], 3>;
 defm : SBWriteResPair<WriteIMul32Imm, [SBPort1],   3>;
 defm : SBWriteResPair<WriteIMul32Reg, [SBPort1],   3>;
 defm : SBWriteResPair<WriteIMul64,    [SBPort1,SBPort0], 4, [1,1], 2>;
+defm : SBWriteResPair<WriteMULX64,    [SBPort1,SBPort0], 4, [1,1], 2>;
 defm : SBWriteResPair<WriteIMul64Imm, [SBPort1],   3>;
 defm : SBWriteResPair<WriteIMul64Reg, [SBPort1],   3>;
 def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
 
 defm : X86WriteRes<WriteXCHG,      [SBPort015], 2, [3], 3>;
 defm : X86WriteRes<WriteBSWAP32,   [SBPort1], 1, [1], 1>;
 defm : X86WriteRes<WriteBSWAP64,   [SBPort1, SBPort05], 2, [1,1], 2>;
 defm : X86WriteRes<WriteCMPXCHG,   [SBPort05, SBPort015], 5, [1,3], 4>;

llvm/lib/Target/X86/X86SchedSkylakeClient.td

 
 // Integer multiplication.
 defm : SKLWriteResPair<WriteIMul8,     [SKLPort1],   3>;
 defm : SKLWriteResPair<WriteIMul16,    [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,2], 4>;
 defm : X86WriteRes<WriteIMul16Imm,     [SKLPort1,SKLPort0156], 4, [1,1], 2>;
 defm : X86WriteRes<WriteIMul16ImmLd,   [SKLPort1,SKLPort0156,SKLPort23], 8, [1,1,1], 3>;
 defm : SKLWriteResPair<WriteIMul16Reg, [SKLPort1],   3>;
 defm : SKLWriteResPair<WriteIMul32,    [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>;
+defm : SKLWriteResPair<WriteMULX32,    [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>;
 defm : SKLWriteResPair<WriteIMul32Imm, [SKLPort1],   3>;
 defm : SKLWriteResPair<WriteIMul32Reg, [SKLPort1],   3>;
 defm : SKLWriteResPair<WriteIMul64,    [SKLPort1,SKLPort5], 4, [1,1], 2>;
+defm : SKLWriteResPair<WriteMULX64,    [SKLPort1,SKLPort5], 4, [1,1], 2>;
 defm : SKLWriteResPair<WriteIMul64Imm, [SKLPort1],   3>;
 defm : SKLWriteResPair<WriteIMul64Reg, [SKLPort1],   3>;
 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
 
 defm : X86WriteRes<WriteBSWAP32,    [SKLPort15], 1, [1], 1>;
 defm : X86WriteRes<WriteBSWAP64,    [SKLPort06, SKLPort15], 2, [1,1], 2>;
 defm : X86WriteRes<WriteCMPXCHG,[SKLPort06, SKLPort0156], 5, [2,3], 5>;
 defm : X86WriteRes<WriteCMPXCHGRMW,[SKLPort23,SKLPort06,SKLPort0156,SKLPort237,SKLPort4], 8, [1,2,1,1,1], 6>;

llvm/lib/Target/X86/X86SchedSkylakeServer.td

 // Integer multiplication.
 defm : SKXWriteResPair<WriteIMul8,     [SKXPort1],   3>;
 defm : SKXWriteResPair<WriteIMul16,    [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,2], 4>;
 defm : X86WriteRes<WriteIMul16Imm,     [SKXPort1,SKXPort0156], 4, [1,1], 2>;
 defm : X86WriteRes<WriteIMul16ImmLd,   [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;
 defm : X86WriteRes<WriteIMul16Reg,     [SKXPort1],   3, [1], 1>;
 defm : X86WriteRes<WriteIMul16RegLd,   [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;
 defm : SKXWriteResPair<WriteIMul32,    [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,1], 3>;
+defm : SKXWriteResPair<WriteMULX32,    [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,1], 3>;
 defm : SKXWriteResPair<WriteIMul32Imm, [SKXPort1],   3>;
 defm : SKXWriteResPair<WriteIMul32Reg, [SKXPort1],   3>;
 defm : SKXWriteResPair<WriteIMul64,    [SKXPort1,SKXPort5], 4, [1,1], 2>;
+defm : SKXWriteResPair<WriteMULX64,    [SKXPort1,SKXPort5], 4, [1,1], 2>;
 defm : SKXWriteResPair<WriteIMul64Imm, [SKXPort1],   3>;
 defm : SKXWriteResPair<WriteIMul64Reg, [SKXPort1],   3>;
 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
 
 defm : X86WriteRes<WriteBSWAP32, [SKXPort15], 1, [1], 1>;
 defm : X86WriteRes<WriteBSWAP64, [SKXPort06, SKXPort15], 2, [1,1], 2>;
 defm : X86WriteRes<WriteCMPXCHG,[SKXPort06, SKXPort0156], 5, [2,3], 5>;
 defm : X86WriteRes<WriteCMPXCHGRMW,[SKXPort23,SKXPort06,SKXPort0156,SKXPort237,SKXPort4], 8, [1,2,1,1,1], 6>;

llvm/lib/Target/X86/X86Schedule.td

 defm WriteIMul16Imm : X86SchedWritePair; // Integer 16-bit multiplication by immediate.
 defm WriteIMul16Reg : X86SchedWritePair; // Integer 16-bit multiplication by register.
 defm WriteIMul32    : X86SchedWritePair; // Integer 32-bit multiplication.
 defm WriteIMul32Imm : X86SchedWritePair; // Integer 32-bit multiplication by immediate.
 defm WriteIMul32Reg : X86SchedWritePair; // Integer 32-bit multiplication by register.
 defm WriteIMul64    : X86SchedWritePair; // Integer 64-bit multiplication.
 defm WriteIMul64Imm : X86SchedWritePair; // Integer 64-bit multiplication by immediate.
 defm WriteIMul64Reg : X86SchedWritePair; // Integer 64-bit multiplication by register.
-def  WriteIMulH     : SchedWrite;        // Integer multiplication, high part.
+defm WriteMULX32    : X86SchedWritePair; // Integer 32-bit Multiplication without affecting flags.
+defm WriteMULX64    : X86SchedWritePair; // Integer 64-bit Multiplication without affecting flags.
+def  WriteIMulH     : SchedWrite;        // Integer multiplication, high part (only used by MULX).
 
 def  WriteBSWAP32 : SchedWrite; // Byte Order (Endianness) 32-bit Swap.
 def  WriteBSWAP64 : SchedWrite; // Byte Order (Endianness) 64-bit Swap.
 defm WriteCMPXCHG : X86SchedWritePair; // Compare and set, compare and swap.
 def  WriteCMPXCHGRMW : SchedWrite;     // Compare and set, compare and swap.
 def  WriteXCHG    : SchedWrite;        // Compare+Exchange - TODO RMW support.
 
 // Integer division.

llvm/lib/Target/X86/X86ScheduleAtom.td

 defm : AtomWriteResPair<WriteIMul16Reg, [AtomPort01], [AtomPort01],  6,  7,  [6],  [7]>;
 defm : AtomWriteResPair<WriteIMul32,    [AtomPort01], [AtomPort01],  6,  7,  [6],  [7]>;
 defm : AtomWriteResPair<WriteIMul32Imm, [AtomPort0],  [AtomPort0],   5,  5,  [5],  [5]>;
 defm : AtomWriteResPair<WriteIMul32Reg, [AtomPort0],  [AtomPort0],   5,  5,  [5],  [5]>;
 defm : AtomWriteResPair<WriteIMul64,    [AtomPort01], [AtomPort01], 12, 12, [12], [12]>;
 defm : AtomWriteResPair<WriteIMul64Imm, [AtomPort01], [AtomPort01], 14, 14, [14], [14]>;
 defm : AtomWriteResPair<WriteIMul64Reg, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>;
 defm : X86WriteResUnsupported<WriteIMulH>;
+defm : X86WriteResPairUnsupported<WriteMULX32>;
+defm : X86WriteResPairUnsupported<WriteMULX64>;
 
 defm : X86WriteRes<WriteXCHG,        [AtomPort01], 2, [2], 1>;
 defm : X86WriteRes<WriteBSWAP32,     [AtomPort0], 1, [1], 1>;
 defm : X86WriteRes<WriteBSWAP64,     [AtomPort0], 1, [1], 1>;
 defm : AtomWriteResPair<WriteCMPXCHG, [AtomPort01], [AtomPort01], 15, 15, [15]>;
 defm : X86WriteRes<WriteCMPXCHGRMW,   [AtomPort01, AtomPort0], 1, [1, 1], 1>;
 
 defm : AtomWriteResPair<WriteDiv8,   [AtomPort01], [AtomPort01], 50, 68, [50], [68]>;

llvm/lib/Target/X86/X86ScheduleBdVer2.td

 defm : PdWriteResExPair<WriteIMul16Imm, [PdEX1, PdMul],          5,  [1, 5],    2>;
 defm : PdWriteResExPair<WriteIMul16Reg, [PdEX1, PdMul],          4,  [1, 2]>;
 defm : PdWriteResExPair<WriteIMul32,    [PdEX1, PdMul],          4,  [1, 4]>;
 defm : PdWriteResExPair<WriteIMul32Imm, [PdEX1, PdMul],          4,  [1, 2],    1, 1>;
 defm : PdWriteResExPair<WriteIMul32Reg, [PdEX1, PdMul],          4,  [1, 2]>;
 defm : PdWriteResExPair<WriteIMul64,    [PdEX1, PdMul],          6,  [1, 6]>;
 defm : PdWriteResExPair<WriteIMul64Imm, [PdEX1, PdMul],          6,  [1, 4],1, 1>;
 defm : PdWriteResExPair<WriteIMul64Reg, [PdEX1, PdMul],          6,  [1, 4]>;
-defm : X86WriteResUnsupported<WriteIMulH>; // BMI2 MULX
+
+// BMI2 MULX
+defm : X86WriteResUnsupported<WriteIMulH>;
+defm : X86WriteResPairUnsupported<WriteMULX32>;
+defm : X86WriteResPairUnsupported<WriteMULX64>;
 
 defm : PdWriteResExPair<WriteDiv8,    [PdEX1, PdDiv],           12,  [1, 12]>;
 defm : PdWriteResExPair<WriteDiv16,   [PdEX1, PdDiv],           15,  [1, 15],   2>;
 defm : PdWriteResExPair<WriteDiv32,   [PdEX1, PdDiv],           14,  [1, 14],   2>;
 defm : PdWriteResExPair<WriteDiv64,   [PdEX1, PdDiv],           14,  [1, 14],   2>;
 
 defm : PdWriteResExPair<WriteIDiv8,   [PdEX1, PdDiv],           12,  [1, 12]>;
 defm : PdWriteResExPair<WriteIDiv16,  [PdEX1, PdDiv],           15,  [1, 17],   2>;

llvm/lib/Target/X86/X86ScheduleBtVer2.td

 defm : JWriteResIntPair<WriteIMul16Imm, [JALU1, JMul], 4, [1, 2], 2>;
 defm : JWriteResIntPair<WriteIMul16Reg, [JALU1, JMul], 3, [1, 1], 1>;
 defm : JWriteResIntPair<WriteIMul32,    [JALU1, JMul], 3, [1, 2], 2>;
 defm : JWriteResIntPair<WriteIMul32Imm, [JALU1, JMul], 3, [1, 1], 1>;
 defm : JWriteResIntPair<WriteIMul32Reg, [JALU1, JMul], 3, [1, 1], 1>;
 defm : JWriteResIntPair<WriteIMul64,    [JALU1, JMul], 6, [1, 4], 2>;  
 defm : JWriteResIntPair<WriteIMul64Imm, [JALU1, JMul], 6, [1, 4], 1>;
 defm : JWriteResIntPair<WriteIMul64Reg, [JALU1, JMul], 6, [1, 4], 1>;
-defm : X86WriteRes<WriteIMulH,          [JALU1], 6, [4], 1>;
+defm : X86WriteResUnsupported<WriteIMulH>;
+defm : X86WriteResPairUnsupported<WriteMULX32>;
+defm : X86WriteResPairUnsupported<WriteMULX64>;
 
 defm : JWriteResIntPair<WriteDiv8,   [JALU1, JDiv], 12, [1, 12], 1>;
 defm : JWriteResIntPair<WriteDiv16,  [JALU1, JDiv], 17, [1, 17], 2>;
 defm : JWriteResIntPair<WriteDiv32,  [JALU1, JDiv], 25, [1, 25], 2>;
 defm : JWriteResIntPair<WriteDiv64,  [JALU1, JDiv], 41, [1, 41], 2>;
 defm : JWriteResIntPair<WriteIDiv8,  [JALU1, JDiv], 12, [1, 12], 1>;
 defm : JWriteResIntPair<WriteIDiv16, [JALU1, JDiv], 17, [1, 17], 2>;
 defm : JWriteResIntPair<WriteIDiv32, [JALU1, JDiv], 25, [1, 25], 2>;

llvm/lib/Target/X86/X86ScheduleSLM.td

 defm : SLMWriteResPair<WriteIMul16Imm, [SLM_IEC_RSV1],  3>;
 defm : SLMWriteResPair<WriteIMul16Reg, [SLM_IEC_RSV1],  3>;
 defm : SLMWriteResPair<WriteIMul32,    [SLM_IEC_RSV1],  3>;
 defm : SLMWriteResPair<WriteIMul32Imm, [SLM_IEC_RSV1],  3>;
 defm : SLMWriteResPair<WriteIMul32Reg, [SLM_IEC_RSV1],  3>;
 defm : SLMWriteResPair<WriteIMul64,    [SLM_IEC_RSV1],  3>;
 defm : SLMWriteResPair<WriteIMul64Imm, [SLM_IEC_RSV1],  3>;
 defm : SLMWriteResPair<WriteIMul64Reg, [SLM_IEC_RSV1],  3>;
-def  : WriteRes<WriteIMulH, [SLM_FPC_RSV0]>;
+defm : X86WriteResUnsupported<WriteIMulH>;
+defm : X86WriteResPairUnsupported<WriteMULX32>;
+defm : X86WriteResPairUnsupported<WriteMULX64>;
 
 defm : X86WriteRes<WriteBSWAP32, [SLM_IEC_RSV01], 1, [1], 1>;
 defm : X86WriteRes<WriteBSWAP64, [SLM_IEC_RSV01], 1, [1], 1>;
 defm : X86WriteRes<WriteCMPXCHG, [SLM_IEC_RSV01], 1, [1], 1>;
 defm : X86WriteRes<WriteCMPXCHGRMW, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1, 2], 2>;
 defm : X86WriteRes<WriteXCHG,      [SLM_IEC_RSV01], 1, [1], 1>;
 
 defm : SLMWriteResPair<WriteShift,    [SLM_IEC_RSV0],  1>;

llvm/lib/Target/X86/X86ScheduleZnver1.td

 defm : ZnWriteResPair<WriteDiv32,  [ZnALU2, ZnDivider], 25, [1,25], 2>;
 defm : ZnWriteResPair<WriteDiv64,  [ZnALU2, ZnDivider], 41, [1,41], 2>;
 defm : ZnWriteResPair<WriteIDiv8,  [ZnALU2, ZnDivider], 15, [1,15], 1>;
 defm : ZnWriteResPair<WriteIDiv16, [ZnALU2, ZnDivider], 17, [1,17], 2>;
 defm : ZnWriteResPair<WriteIDiv32, [ZnALU2, ZnDivider], 25, [1,25], 2>;
 defm : ZnWriteResPair<WriteIDiv64, [ZnALU2, ZnDivider], 41, [1,41], 2>;
 
 // IMULH
-def  : WriteRes<WriteIMulH, [ZnALU1, ZnMultiplier]>{
-  let Latency = 4;
+def  : WriteRes<WriteIMulH, [ZnMultiplier]>{
+  let Latency = 3;
+  let NumMicroOps = 0;
 }
 
 // Floating point operations
 defm : X86WriteRes<WriteFLoad,         [ZnAGU], 8, [1], 1>;
 defm : X86WriteRes<WriteFLoadX,        [ZnAGU], 8, [1], 1>;
 defm : X86WriteRes<WriteFLoadY,        [ZnAGU], 8, [1], 1>;
 defm : X86WriteRes<WriteFMaskedLoad,   [ZnAGU,ZnFPU01], 8, [1,1], 1>;
 defm : X86WriteRes<WriteFMaskedLoadY,  [ZnAGU,ZnFPU01], 8, [1,2], 2>;

 
 // m64.
 def ZnWriteMul64Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> {
   let Latency = 9;
   let NumMicroOps = 2;
 }
 def : SchedAlias<WriteIMul64Ld, ZnWriteMul64Ld>;
 
-// MULX.
-// r32,r32,r32.
-def ZnWriteMulX32 : SchedWriteRes<[ZnALU1, ZnMultiplier]> {
-  let Latency = 3;
-  let ResourceCycles = [1, 2];
-}
-def : InstRW<[ZnWriteMulX32], (instrs MULX32rr)>;
-
-// r32,r32,m32.
-def ZnWriteMulX32Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> {
-  let Latency = 8;
-  let ResourceCycles = [1, 2, 2];
-}
-def : InstRW<[ZnWriteMulX32Ld, ReadAfterLd], (instrs MULX32rm)>;
-
-// r64,r64,r64.
-def ZnWriteMulX64 : SchedWriteRes<[ZnALU1]> {
-  let Latency = 3;
-}
-def : InstRW<[ZnWriteMulX64], (instrs MULX64rr)>;
-
-// r64,r64,m64.
-def ZnWriteMulX64Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> {
-  let Latency = 8;
-}
-def : InstRW<[ZnWriteMulX64Ld, ReadAfterLd], (instrs MULX64rm)>;
+// MULX
+// Numbers are based on the AMD SOG for Family 17h - Instruction Latencies.
+defm : ZnWriteResPair<WriteMULX32, [ZnALU1, ZnMultiplier], 3, [1, 1], 1, 5, 0>;
+defm : ZnWriteResPair<WriteMULX64, [ZnALU1, ZnMultiplier], 3, [1, 1], 1, 5, 0>;
 
 //-- Control transfer instructions --//
 
 // J(E|R)CXZ.
 def ZnWriteJCXZ : SchedWriteRes<[ZnALU03]>;
 def : InstRW<[ZnWriteJCXZ], (instrs JCXZ, JECXZ, JRCXZ)>;
 
 // INTO

llvm/lib/Target/X86/X86ScheduleZnver2.td

 defm : Zn2WriteResPair<WriteDiv32,  [Zn2ALU2, Zn2Divider], 25, [1,25], 2>;
 defm : Zn2WriteResPair<WriteDiv64,  [Zn2ALU2, Zn2Divider], 41, [1,41], 2>;
 defm : Zn2WriteResPair<WriteIDiv8,  [Zn2ALU2, Zn2Divider], 15, [1,15], 1>;
 defm : Zn2WriteResPair<WriteIDiv16, [Zn2ALU2, Zn2Divider], 17, [1,17], 2>;
 defm : Zn2WriteResPair<WriteIDiv32, [Zn2ALU2, Zn2Divider], 25, [1,25], 2>;
 defm : Zn2WriteResPair<WriteIDiv64, [Zn2ALU2, Zn2Divider], 41, [1,41], 2>;
 
 // IMULH
-def  : WriteRes<WriteIMulH, [Zn2ALU1, Zn2Multiplier]>{
-  let Latency = 4;
+def  : WriteRes<WriteIMulH, [Zn2Multiplier]>{
+  let Latency = 3;
+  let NumMicroOps = 0;
 }
 
 // Floating point operations
 defm : X86WriteRes<WriteFLoad,         [Zn2AGU], 8, [1], 1>;
 defm : X86WriteRes<WriteFLoadX,        [Zn2AGU], 8, [1], 1>;
 defm : X86WriteRes<WriteFLoadY,        [Zn2AGU], 8, [1], 1>;
 defm : X86WriteRes<WriteFMaskedLoad,   [Zn2AGU,Zn2FPU01], 8, [1,1], 1>;
 defm : X86WriteRes<WriteFMaskedLoadY,  [Zn2AGU,Zn2FPU01], 8, [1,1], 2>;
def Zn2WriteMul64Ld : SchedWriteRes<[Zn2AGU, Zn2ALU1, Zn2Multiplier]> {
   let Latency = 8;
   let NumMicroOps = 2;
 }
 def : SchedAlias<WriteIMul64Ld, Zn2WriteMul64Ld>;
 def : SchedAlias<WriteIMul64ImmLd, Zn2WriteMul64Ld>;
 def : SchedAlias<WriteIMul64RegLd, Zn2WriteMul64Ld>;
 
 // MULX.
-// r32,r32,r32.
-def Zn2WriteMulX32 : SchedWriteRes<[Zn2ALU1, Zn2Multiplier]> {
-  let Latency = 3;
-  let ResourceCycles = [1, 2];
-}
-def : InstRW<[Zn2WriteMulX32], (instrs MULX32rr)>;
-
-// r32,r32,m32.
-def Zn2WriteMulX32Ld : SchedWriteRes<[Zn2AGU, Zn2ALU1, Zn2Multiplier]> {
-  let Latency = 7;
-  let ResourceCycles = [1, 2, 2];
-}
-def : InstRW<[Zn2WriteMulX32Ld, ReadAfterLd], (instrs MULX32rm)>;
-
-// r64,r64,r64.
-def Zn2WriteMulX64 : SchedWriteRes<[Zn2ALU1]> {
-  let Latency = 3;
-}
-def : InstRW<[Zn2WriteMulX64], (instrs MULX64rr)>;
-
-// r64,r64,m64.
-def Zn2WriteMulX64Ld : SchedWriteRes<[Zn2AGU, Zn2ALU1, Zn2Multiplier]> {
-  let Latency = 7;
-}
-def : InstRW<[Zn2WriteMulX64Ld, ReadAfterLd], (instrs MULX64rm)>;
+// Numbers are based on the AMD SOG for Family 17h - Instruction Latencies.
+defm : Zn2WriteResPair<WriteMULX32, [Zn2ALU1, Zn2Multiplier], 3, [1, 1], 1, 4, 0>;
+defm : Zn2WriteResPair<WriteMULX64, [Zn2ALU1, Zn2Multiplier], 3, [1, 1], 1, 4, 0>;
 
 //-- Control transfer instructions --//
 
 // J(E|R)CXZ.
 def Zn2WriteJCXZ : SchedWriteRes<[Zn2ALU03]>;
 def : InstRW<[Zn2WriteJCXZ], (instrs JCXZ, JECXZ, JRCXZ)>;
 
 // INTO

llvm/lib/Target/X86/X86ScheduleZnver3.td

 def : InstRW<[Zn3SlowLEA16r], (instrs LEA16r)>;
 
 // Integer multiplication
 defm : Zn3WriteResIntPair<WriteIMul8, [Zn3Multiplier], 3, [3], 1>; // Integer 8-bit multiplication.
 defm : Zn3WriteResIntPair<WriteIMul16, [Zn3Multiplier], 3, [3], 3, /*LoadUOps=*/1>; // Integer 16-bit multiplication.
 defm : Zn3WriteResIntPair<WriteIMul16Imm, [Zn3Multiplier], 4, [4], 2>; // Integer 16-bit multiplication by immediate.
 defm : Zn3WriteResIntPair<WriteIMul16Reg, [Zn3Multiplier], 3, [1], 1>; // Integer 16-bit multiplication by register.
 defm : Zn3WriteResIntPair<WriteIMul32, [Zn3Multiplier], 3, [3], 2>;    // Integer 32-bit multiplication.
+defm : Zn3WriteResIntPair<WriteMULX32, [Zn3Multiplier], 4, [1], 2>;    // Integer 32-bit Unsigned Multiply Without Affecting Flags.
 
 def Zn3MULX32rr : SchedWriteRes<[Zn3Multiplier]> {
   let Latency = 4;
   let ResourceCycles = [1];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3MULX32rr, WriteIMulH], (instrs MULX32rr)>;
 
 def Zn3MULX32rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3Multiplier]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3MULX32rr.Latency);
   let ResourceCycles = [1, 1, 2];
   let NumMicroOps = Zn3MULX32rr.NumMicroOps;
 }
-def : InstRW<[Zn3MULX32rm, WriteIMulH], (instrs MULX32rm)>;
+def : InstRW<[Zn3MULX32rm, WriteIMulH,
+              ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
+              ReadAfterLd], (instrs MULX32rm)>;
 
 defm : Zn3WriteResIntPair<WriteIMul32Imm, [Zn3Multiplier], 3, [1], 1>; // Integer 32-bit multiplication by immediate.
 defm : Zn3WriteResIntPair<WriteIMul32Reg, [Zn3Multiplier], 3, [1], 1>; // Integer 32-bit multiplication by register.
 defm : Zn3WriteResIntPair<WriteIMul64, [Zn3Multiplier], 3, [3], 2>;    // Integer 64-bit multiplication.
+defm : Zn3WriteResIntPair<WriteMULX64, [Zn3Multiplier], 4, [1], 2>;    // Integer 32-bit Unsigned Multiply Without Affecting Flags.
 
 def Zn3MULX64rr : SchedWriteRes<[Zn3Multiplier]> {
   let Latency = 4;
   let ResourceCycles = [1];
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn3MULX64rr, WriteIMulH], (instrs MULX64rr)>;
 
 def Zn3MULX64rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3Multiplier]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3MULX64rr.Latency);
   let ResourceCycles = [1, 1, 2];
   let NumMicroOps = Zn3MULX64rr.NumMicroOps;
 }
-def : InstRW<[Zn3MULX64rm, WriteIMulH], (instrs MULX64rm)>;
+def : InstRW<[Zn3MULX64rm, WriteIMulH,
+              ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
+              ReadAfterLd], (instrs MULX64rm)>;
 
 defm : Zn3WriteResIntPair<WriteIMul64Imm, [Zn3Multiplier], 3, [1], 1>; // Integer 64-bit multiplication by immediate.
 defm : Zn3WriteResIntPair<WriteIMul64Reg, [Zn3Multiplier], 3, [1], 1>; // Integer 64-bit multiplication by register.
 defm : Zn3WriteResInt<WriteIMulH, [], 4, [], 0>;         // Integer multiplication, high part.
 
 defm : Zn3WriteResInt<WriteBSWAP32, [Zn3ALU0123], 1, [1], 1>; // Byte Order (Endianness) 32-bit Swap.
 defm : Zn3WriteResInt<WriteBSWAP64, [Zn3ALU0123], 1, [1], 1>; // Byte Order (Endianness) 64-bit Swap.
 

llvm/test/tools/llvm-mca/X86/Haswell/adcx-adox-read-advance.s

 # LLVM-MCA-BEGIN
 adox (%rdi), %rcx
 # LLVM-MCA-END
 
 # CHECK:      [0] Code Region
 
 # CHECK:      Iterations:        2
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      17
+# CHECK-NEXT: Total Cycles:      12
 # CHECK-NEXT: Total uOps:        6
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.35
-# CHECK-NEXT: IPC:               0.12
+# CHECK-NEXT: uOps Per Cycle:    0.50
+# CHECK-NEXT: IPC:               0.17
 # CHECK-NEXT: Block RThroughput: 0.8
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]
 # CHECK-NEXT:  -      -     0.50   0.50   0.50   0.50    -     0.50   0.50    -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    Instructions:
 # CHECK-NEXT:  -      -     0.50   0.50   0.50   0.50    -     0.50   0.50    -     adcxq (%rdi), %rcx
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456
+# CHECK-NEXT:                     01
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeeeER.    ..   adcxq (%rdi), %rcx
-# CHECK-NEXT: [1,0]     .D======eeeeeeeER   adcxq (%rdi), %rcx
+# CHECK:      [0,0]     DeeeeeeeER..   adcxq  (%rdi), %rcx
+# CHECK-NEXT: [1,0]     .D=eeeeeeeER   adcxq  (%rdi), %rcx
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     2     4.0    0.5    0.0       adcxq  (%rdi), %rcx
+# CHECK-NEXT: 0.     2     1.5    0.5    0.0       adcxq  (%rdi), %rcx
 
 # CHECK:      [1] Code Region
 
 # CHECK:      Iterations:        2
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      17
+# CHECK-NEXT: Total Cycles:      12
 # CHECK-NEXT: Total uOps:        6
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.35
-# CHECK-NEXT: IPC:               0.12
+# CHECK-NEXT: uOps Per Cycle:    0.50
+# CHECK-NEXT: IPC:               0.17
 # CHECK-NEXT: Block RThroughput: 0.8
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]
 # CHECK-NEXT:  -      -     0.50   0.50   0.50   0.50    -     0.50   0.50    -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    Instructions:
 # CHECK-NEXT:  -      -     0.50   0.50   0.50   0.50    -     0.50   0.50    -     adoxq (%rdi), %rcx
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456
+# CHECK-NEXT:                     01
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeeeER.    ..   adoxq (%rdi), %rcx
-# CHECK-NEXT: [1,0]     .D======eeeeeeeER   adoxq (%rdi), %rcx
+# CHECK:      [0,0]     DeeeeeeeER..   adoxq  (%rdi), %rcx
+# CHECK-NEXT: [1,0]     .D=eeeeeeeER   adoxq  (%rdi), %rcx
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     2     4.0    0.5    0.0       adoxq  (%rdi), %rcx
+# CHECK-NEXT: 0.     2     1.5    0.5    0.0       adoxq  (%rdi), %rcx

llvm/test/tools/llvm-mca/X86/Haswell/mulx-read-advance.s

 # LLVM-MCA-BEGIN
 mulxq (%rdi), %rax, %rdx
 # LLVM-MCA-END
 
 # CHECK:      [0] Code Region
 
 # CHECK:      Iterations:        2
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      21
+# CHECK-NEXT: Total Cycles:      16
 # CHECK-NEXT: Total uOps:        10
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.48
-# CHECK-NEXT: IPC:               0.10
+# CHECK-NEXT: uOps Per Cycle:    0.63
+# CHECK-NEXT: IPC:               0.13
 # CHECK-NEXT: Block RThroughput: 1.3
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]
 # CHECK-NEXT:  -      -     0.50   1.00   0.50   0.50    -     0.50   1.00    -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    Instructions:
 # CHECK-NEXT:  -      -     0.50   1.00   0.50   0.50    -     0.50   1.00    -     mulxl (%rdi), %eax, %edx
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456789
-# CHECK-NEXT: Index     0123456789          0
+# CHECK-NEXT:                     012345
+# CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeeeeeER   .    .   mulxl (%rdi), %eax, %edx
-# CHECK-NEXT: [1,0]     . D=======eeeeeeeeeER   mulxl (%rdi), %eax, %edx
+# CHECK:      [0,0]     DeeeeeeeeeER   .   mulxl  (%rdi), %eax, %edx
+# CHECK-NEXT: [1,0]     . D==eeeeeeeeeER   mulxl  (%rdi), %eax, %edx
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     2     4.5    0.5    0.0       mulxl  (%rdi), %eax, %edx
+# CHECK-NEXT: 0.     2     2.0    0.5    0.0       mulxl  (%rdi), %eax, %edx
 
 # CHECK:      [1] Code Region
 
 # CHECK:      Iterations:        2
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      21
+# CHECK-NEXT: Total Cycles:      16
 # CHECK-NEXT: Total uOps:        8
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.38
-# CHECK-NEXT: IPC:               0.10
+# CHECK-NEXT: uOps Per Cycle:    0.50
+# CHECK-NEXT: IPC:               0.13
 # CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]
 # CHECK-NEXT:  -      -      -     1.00   0.50   0.50    -      -     1.00    -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    Instructions:
 # CHECK-NEXT:  -      -      -     1.00   0.50   0.50    -      -     1.00    -     mulxq (%rdi), %rax, %rdx
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456789
-# CHECK-NEXT: Index     0123456789          0
+# CHECK-NEXT:                     012345
+# CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeeeeeER   .    .   mulxq (%rdi), %rax, %rdx
-# CHECK-NEXT: [1,0]     .D========eeeeeeeeeER   mulxq (%rdi), %rax, %rdx
+# CHECK:      [0,0]     DeeeeeeeeeER   .   mulxq  (%rdi), %rax, %rdx
+# CHECK-NEXT: [1,0]     .D===eeeeeeeeeER   mulxq  (%rdi), %rax, %rdx
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     2     5.0    0.5    0.0       mulxq  (%rdi), %rax, %rdx
+# CHECK-NEXT: 0.     2     2.5    0.5    0.0       mulxq  (%rdi), %rax, %rdx

llvm/test/tools/llvm-mca/X86/Znver1/resources-bmi2.s

 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      1     0.25                        bzhil %eax, %ebx, %ecx
 # CHECK-NEXT:  2      5     0.50    *                   bzhil %eax, (%rbx), %ecx
 # CHECK-NEXT:  1      1     0.25                        bzhiq %rax, %rbx, %rcx
 # CHECK-NEXT:  2      5     0.50    *                   bzhiq %rax, (%rbx), %rcx
 # CHECK-NEXT:  1      3     2.00                        mulxl %eax, %ebx, %ecx
 # CHECK-NEXT:  1      8     2.00    *                   mulxl (%rax), %ebx, %ecx
-# CHECK-NEXT:  1      3     1.00                        mulxq %rax, %rbx, %rcx
-# CHECK-NEXT:  1      8     1.00    *                   mulxq (%rax), %rbx, %rcx
+# CHECK-NEXT:  1      3     2.00                        mulxq %rax, %rbx, %rcx
+# CHECK-NEXT:  1      8     2.00    *                   mulxq (%rax), %rbx, %rcx
 # CHECK-NEXT:  1      100   0.25                        pdepl %eax, %ebx, %ecx
 # CHECK-NEXT:  1      100   0.25    *                   pdepl (%rax), %ebx, %ecx
 # CHECK-NEXT:  1      100   0.25                        pdepq %rax, %rbx, %rcx
 # CHECK-NEXT:  1      100   0.25    *                   pdepq (%rax), %rbx, %rcx
 # CHECK-NEXT:  1      100   0.25                        pextl %eax, %ebx, %ecx
 # CHECK-NEXT:  1      100   0.25    *                   pextl (%rax), %ebx, %ecx
 # CHECK-NEXT:  1      100   0.25                        pextq %rax, %rbx, %rcx
 # CHECK-NEXT:  1      100   0.25    *                   pextq (%rax), %rbx, %rcx

 # CHECK-NEXT: [7]   - ZnFPU0
 # CHECK-NEXT: [8]   - ZnFPU1
 # CHECK-NEXT: [9]   - ZnFPU2
 # CHECK-NEXT: [10]  - ZnFPU3
 # CHECK-NEXT: [11]  - ZnMultiplier
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]
-# CHECK-NEXT: 6.00   6.00   5.00   10.00  5.00   5.00    -      -      -      -      -     5.00
+# CHECK-NEXT: 6.00   6.00   5.00   9.00   5.00   5.00    -      -      -      -      -     8.00
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   Instructions:
 # CHECK-NEXT:  -      -     0.25   0.25   0.25   0.25    -      -      -      -      -      -     bzhil %eax, %ebx, %ecx
 # CHECK-NEXT: 0.50   0.50   0.25   0.25   0.25   0.25    -      -      -      -      -      -     bzhil %eax, (%rbx), %ecx
 # CHECK-NEXT:  -      -     0.25   0.25   0.25   0.25    -      -      -      -      -      -     bzhiq %rax, %rbx, %rcx
 # CHECK-NEXT: 0.50   0.50   0.25   0.25   0.25   0.25    -      -      -      -      -      -     bzhiq %rax, (%rbx), %rcx
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -      -      -      -     2.00   mulxl %eax, %ebx, %ecx
-# CHECK-NEXT: 0.50   0.50    -     2.00    -      -      -      -      -      -      -     2.00   mulxl (%rax), %ebx, %ecx
-# CHECK-NEXT:  -      -      -     1.00    -      -      -      -      -      -      -      -     mulxq %rax, %rbx, %rcx
-# CHECK-NEXT: 0.50   0.50    -     1.00    -      -      -      -      -      -      -     1.00   mulxq (%rax), %rbx, %rcx
+# CHECK-NEXT: 0.50   0.50    -     1.00    -      -      -      -      -      -      -     2.00   mulxl (%rax), %ebx, %ecx
+# CHECK-NEXT:  -      -      -     1.00    -      -      -      -      -      -      -     2.00   mulxq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.50   0.50    -     1.00    -      -      -      -      -      -      -     2.00   mulxq (%rax), %rbx, %rcx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -     pdepl %eax, %ebx, %ecx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -     pdepl (%rax), %ebx, %ecx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -     pdepq %rax, %rbx, %rcx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -     pdepq (%rax), %rbx, %rcx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -     pextl %eax, %ebx, %ecx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -     pextl (%rax), %ebx, %ecx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -     pextq %rax, %rbx, %rcx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -     pextq (%rax), %rbx, %rcx

llvm/test/tools/llvm-mca/X86/Znver2/adcx-adox-read-advance.s

 # LLVM-MCA-BEGIN
 adox (%rdi), %rcx
 # LLVM-MCA-END
 
 # CHECK:      [0] Code Region
 
 # CHECK:      Iterations:        2
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      13
+# CHECK-NEXT: Total Cycles:      9
 # CHECK-NEXT: Total uOps:        4
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.31
-# CHECK-NEXT: IPC:               0.15
+# CHECK-NEXT: uOps Per Cycle:    0.44
+# CHECK-NEXT: IPC:               0.22
 # CHECK-NEXT: Block RThroughput: 0.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]
 # CHECK-NEXT:  -     0.50   0.50    -      -     0.50   0.50    -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   Instructions:
 # CHECK-NEXT:  -     0.50   0.50    -      -     0.50   0.50    -      -      -      -      -      -     adcxq  (%rdi), %rcx
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     012
-# CHECK-NEXT: Index     0123456789
+# CHECK-NEXT: Index     012345678
 
-# CHECK:      [0,0]     DeeeeeER  . .   adcxq (%rdi), %rcx
-# CHECK-NEXT: [1,0]     D=====eeeeeER   adcxq (%rdi), %rcx
+# CHECK:      [0,0]     DeeeeeER.   adcxq (%rdi), %rcx
+# CHECK-NEXT: [1,0]     D=eeeeeER   adcxq (%rdi), %rcx
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     2     3.5    0.5    0.0       adcxq  (%rdi), %rcx
+# CHECK-NEXT: 0.     2     1.5    0.5    0.0       adcxq  (%rdi), %rcx
 
 # CHECK:      [1] Code Region
 
 # CHECK:      Iterations:        2
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      13
+# CHECK-NEXT: Total Cycles:      9
 # CHECK-NEXT: Total uOps:        4
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.31
-# CHECK-NEXT: IPC:               0.15
+# CHECK-NEXT: uOps Per Cycle:    0.44
+# CHECK-NEXT: IPC:               0.22
 # CHECK-NEXT: Block RThroughput: 0.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]
 # CHECK-NEXT:  -     0.50   0.50    -      -     0.50   0.50    -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   Instructions:
 # CHECK-NEXT:  -     0.50   0.50    -      -     0.50   0.50    -      -      -      -      -      -     adoxq  (%rdi), %rcx
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     012
-# CHECK-NEXT: Index     0123456789
+# CHECK-NEXT: Index     012345678
 
-# CHECK:      [0,0]     DeeeeeER  . .   adoxq (%rdi), %rcx
-# CHECK-NEXT: [1,0]     D=====eeeeeER   adoxq (%rdi), %rcx
+# CHECK:      [0,0]     DeeeeeER.   adoxq (%rdi), %rcx
+# CHECK-NEXT: [1,0]     D=eeeeeER   adoxq (%rdi), %rcx
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     2     3.5    0.5    0.0       adoxq  (%rdi), %rcx
+# CHECK-NEXT: 0.     2     1.5    0.5    0.0       adoxq  (%rdi), %rcx

llvm/test/tools/llvm-mca/X86/Znver2/mulx-read-advance.s

 # LLVM-MCA-BEGIN
 mulxq (%rdi), %rax, %rdx
 # LLVM-MCA-END
 
 # CHECK:      [0] Code Region
 
 # CHECK:      Iterations:        2
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      17
+# CHECK-NEXT: Total Cycles:      13
 # CHECK-NEXT: Total uOps:        2
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.12
-# CHECK-NEXT: IPC:               0.12
+# CHECK-NEXT: uOps Per Cycle:    0.15
+# CHECK-NEXT: IPC:               0.15
 # CHECK-NEXT: Block RThroughput: 2.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK-NEXT: [8]   - Zn2FPU0
 # CHECK-NEXT: [9]   - Zn2FPU1
 # CHECK-NEXT: [10]  - Zn2FPU2
 # CHECK-NEXT: [11]  - Zn2FPU3
 # CHECK-NEXT: [12]  - Zn2Multiplier
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]
-# CHECK-NEXT:  -     0.50   0.50    -     2.00    -      -      -      -      -      -      -     2.00
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     2.00
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   Instructions:
-# CHECK-NEXT:  -     0.50   0.50    -     2.00    -      -      -      -      -      -      -     2.00   mulxl  (%rdi), %eax, %edx
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     2.00   mulxl  (%rdi), %eax, %edx
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456
+# CHECK-NEXT:                     012
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeeeER.    ..   mulxl (%rdi), %eax, %edx
-# CHECK-NEXT: [1,0]     D=======eeeeeeeER   mulxl (%rdi), %eax, %edx
+# CHECK:      [0,0]     DeeeeeeeER. .   mulxl (%rdi), %eax, %edx
+# CHECK-NEXT: [1,0]     D===eeeeeeeER   mulxl (%rdi), %eax, %edx
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     2     4.5    0.5    0.0       mulxl  (%rdi), %eax, %edx
+# CHECK-NEXT: 0.     2     2.5    0.5    0.0       mulxl  (%rdi), %eax, %edx
 
 # CHECK:      [1] Code Region
 
 # CHECK:      Iterations:        2
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      17
+# CHECK-NEXT: Total Cycles:      13
 # CHECK-NEXT: Total uOps:        2
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.12
-# CHECK-NEXT: IPC:               0.12
-# CHECK-NEXT: Block RThroughput: 1.0
+# CHECK-NEXT: uOps Per Cycle:    0.15
+# CHECK-NEXT: IPC:               0.15
+# CHECK-NEXT: Block RThroughput: 2.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  1      7     1.00    *                   mulxq (%rdi), %rax, %rdx
+# CHECK-NEXT:  1      7     2.00    *                   mulxq (%rdi), %rax, %rdx
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - Zn2AGU0
 # CHECK-NEXT: [1]   - Zn2AGU1
 # CHECK-NEXT: [2]   - Zn2AGU2
 # CHECK-NEXT: [3]   - Zn2ALU0
 # CHECK-NEXT: [4]   - Zn2ALU1
 # CHECK-NEXT: [5]   - Zn2ALU2
 # CHECK-NEXT: [6]   - Zn2ALU3
 # CHECK-NEXT: [7]   - Zn2Divider
 # CHECK-NEXT: [8]   - Zn2FPU0
 # CHECK-NEXT: [9]   - Zn2FPU1
 # CHECK-NEXT: [10]  - Zn2FPU2
 # CHECK-NEXT: [11]  - Zn2FPU3
 # CHECK-NEXT: [12]  - Zn2Multiplier
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]
-# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     1.00
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     2.00
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   Instructions:
-# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     1.00   mulxq  (%rdi), %rax, %rdx
+# CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     2.00   mulxq  (%rdi), %rax, %rdx
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456
+# CHECK-NEXT:                     012
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeeeER.    ..   mulxq (%rdi), %rax, %rdx
-# CHECK-NEXT: [1,0]     D=======eeeeeeeER   mulxq (%rdi), %rax, %rdx
+# CHECK:      [0,0]     DeeeeeeeER. .   mulxq (%rdi), %rax, %rdx
+# CHECK-NEXT: [1,0]     D===eeeeeeeER   mulxq (%rdi), %rax, %rdx
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     2     4.5    0.5    0.0       mulxq  (%rdi), %rax, %rdx
+# CHECK-NEXT: 0.     2     2.5    0.5    0.0       mulxq  (%rdi), %rax, %rdx

llvm/test/tools/llvm-mca/X86/Znver2/resources-bmi2.s

 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      1     0.25                        bzhil %eax, %ebx, %ecx
 # CHECK-NEXT:  2      5     0.33    *                   bzhil %eax, (%rbx), %ecx
 # CHECK-NEXT:  1      1     0.25                        bzhiq %rax, %rbx, %rcx
 # CHECK-NEXT:  2      5     0.33    *                   bzhiq %rax, (%rbx), %rcx
 # CHECK-NEXT:  1      3     2.00                        mulxl %eax, %ebx, %ecx
 # CHECK-NEXT:  1      7     2.00    *                   mulxl (%rax), %ebx, %ecx
-# CHECK-NEXT:  1      3     1.00                        mulxq %rax, %rbx, %rcx
-# CHECK-NEXT:  1      7     1.00    *                   mulxq (%rax), %rbx, %rcx
+# CHECK-NEXT:  1      3     2.00                        mulxq %rax, %rbx, %rcx
+# CHECK-NEXT:  1      7     2.00    *                   mulxq (%rax), %rbx, %rcx
 # CHECK-NEXT:  1      100   0.25                        pdepl %eax, %ebx, %ecx
 # CHECK-NEXT:  1      100   0.25    *                   pdepl (%rax), %ebx, %ecx
 # CHECK-NEXT:  1      100   0.25                        pdepq %rax, %rbx, %rcx
 # CHECK-NEXT:  1      100   0.25    *                   pdepq (%rax), %rbx, %rcx
 # CHECK-NEXT:  1      100   0.25                        pextl %eax, %ebx, %ecx
 # CHECK-NEXT:  1      100   0.25    *                   pextl (%rax), %ebx, %ecx
 # CHECK-NEXT:  1      100   0.25                        pextq %rax, %rbx, %rcx
 # CHECK-NEXT:  1      100   0.25    *                   pextq (%rax), %rbx, %rcx

 # CHECK-NEXT: [8]   - Zn2FPU0
 # CHECK-NEXT: [9]   - Zn2FPU1
 # CHECK-NEXT: [10]  - Zn2FPU2
 # CHECK-NEXT: [11]  - Zn2FPU3
 # CHECK-NEXT: [12]  - Zn2Multiplier
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]
-# CHECK-NEXT: 4.00   4.00   4.00   5.00   10.00  5.00   5.00    -      -      -      -      -     5.00
+# CHECK-NEXT: 4.00   4.00   4.00   5.00   9.00   5.00   5.00    -      -      -      -      -     8.00
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   Instructions:
 # CHECK-NEXT:  -      -      -     0.25   0.25   0.25   0.25    -      -      -      -      -      -     bzhil  %eax, %ebx, %ecx
 # CHECK-NEXT: 0.33   0.33   0.33   0.25   0.25   0.25   0.25    -      -      -      -      -      -     bzhil  %eax, (%rbx), %ecx
 # CHECK-NEXT:  -      -      -     0.25   0.25   0.25   0.25    -      -      -      -      -      -     bzhiq  %rax, %rbx, %rcx
 # CHECK-NEXT: 0.33   0.33   0.33   0.25   0.25   0.25   0.25    -      -      -      -      -      -     bzhiq  %rax, (%rbx), %rcx
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -      -      -      -     2.00   mulxl  %eax, %ebx, %ecx
-# CHECK-NEXT: 0.33   0.33   0.33    -     2.00    -      -      -      -      -      -      -     2.00   mulxl  (%rax), %ebx, %ecx
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -      -      -      -      -     mulxq  %rax, %rbx, %rcx
-# CHECK-NEXT: 0.33   0.33   0.33    -     1.00    -      -      -      -      -      -      -     1.00   mulxq  (%rax), %rbx, %rcx
+# CHECK-NEXT: 0.33   0.33   0.33    -     1.00    -      -      -      -      -      -      -     2.00   mulxl  (%rax), %ebx, %ecx
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -      -      -      -     2.00   mulxq  %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33   0.33   0.33    -     1.00    -      -      -      -      -      -      -     2.00   mulxq  (%rax), %rbx, %rcx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -     pdepl  %eax, %ebx, %ecx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -     pdepl  (%rax), %ebx, %ecx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -     pdepq  %rax, %rbx, %rcx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -     pdepq  (%rax), %rbx, %rcx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -     pextl  %eax, %ebx, %ecx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -     pextl  (%rax), %ebx, %ecx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -     pextq  %rax, %rbx, %rcx
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -     pextq  (%rax), %rbx, %rcx