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Differential D108287

[AArch64] Correct store ReadAdrBase operand
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Authored by dmgreen on Aug 18 2021, 3:58 AM.

Details

Reviewers
NickGuy
SjoerdMeijer
fhahn
t.p.northover
andreadb
Commits
rG50f4ae58eb13: [AArch64] Correct store ReadAdrBase operand
Summary

It appears that the Read operand for stores was being placed on the first operand (the stored value) not the address base. This adds a ReadST for the stored value operand, allowing the ReadAdrBase to correctly act upon the address.

Diff Detail

Event Timeline

dmgreen created this revision.Aug 18 2021, 3:58 AM
Herald added a reviewer: andreadb. · View Herald TranscriptAug 18 2021, 3:58 AM
Herald added subscribers: gbedwell, hiraditya, kristof.beyls. · View Herald Transcript
dmgreen requested review of this revision.Aug 18 2021, 3:58 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 18 2021, 3:58 AM
Harbormaster completed remote builds in B120092: Diff 367163.Aug 18 2021, 3:58 AM
NickGuy accepted this revision.Aug 23 2021, 2:39 AM
This revision is now accepted and ready to land.Aug 23 2021, 2:39 AM
This revision was landed with ongoing or failed builds.Aug 23 2021, 1:08 PM
Closed by commit rG50f4ae58eb13: [AArch64] Correct store ReadAdrBase operand (authored by dmgreen). · Explain Why
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rG50f4ae58eb13: [AArch64] Correct store ReadAdrBase operand.

Revision Contents

Diff 367163

llvm/lib/Target/AArch64/AArch64InstrFormats.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype, multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
string asm, ValueType Ty, SDPatternOperator storeop> { string asm, ValueType Ty, SDPatternOperator storeop> {
let AddedComplexity = 10 in let AddedComplexity = 10 in
def roW : LoadStore8RO<sz, V, opc, regtype, asm, (outs), def roW : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
(ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend), (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
[(storeop (Ty regtype:$Rt), [(storeop (Ty regtype:$Rt),
(ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm, (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
ro_Wextend8:$extend))]>, ro_Wextend8:$extend))]>,
Sched<[WriteSTIdx, ReadAdrBase]> { Sched<[WriteSTIdx, ReadST, ReadAdrBase]> {
let Inst{13} = 0b0; let Inst{13} = 0b0;
} }
let AddedComplexity = 10 in let AddedComplexity = 10 in
def roX : LoadStore8RO<sz, V, opc, regtype, asm, (outs), def roX : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
(ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend), (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
[(storeop (Ty regtype:$Rt), [(storeop (Ty regtype:$Rt),
(ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm, (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
ro_Xextend8:$extend))]>, ro_Xextend8:$extend))]>,
Sched<[WriteSTIdx, ReadAdrBase]> { Sched<[WriteSTIdx, ReadST, ReadAdrBase]> {
let Inst{13} = 0b1; let Inst{13} = 0b1;
} }
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>; def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
} }
class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype, class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
string asm, dag ins, dag outs, list<dag> pat> string asm, dag ins, dag outs, list<dag> pat>
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multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype, multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
string asm, ValueType Ty, SDPatternOperator storeop> { string asm, ValueType Ty, SDPatternOperator storeop> {
let AddedComplexity = 10 in let AddedComplexity = 10 in
def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs), def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
(ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend), (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
[(storeop (Ty regtype:$Rt), [(storeop (Ty regtype:$Rt),
(ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm, (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
ro_Wextend16:$extend))]>, ro_Wextend16:$extend))]>,
Sched<[WriteSTIdx, ReadAdrBase]> { Sched<[WriteSTIdx, ReadST, ReadAdrBase]> {
let Inst{13} = 0b0; let Inst{13} = 0b0;
} }
let AddedComplexity = 10 in let AddedComplexity = 10 in
def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs), def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
(ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend), (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
[(storeop (Ty regtype:$Rt), [(storeop (Ty regtype:$Rt),
(ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm, (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
ro_Xextend16:$extend))]>, ro_Xextend16:$extend))]>,
Sched<[WriteSTIdx, ReadAdrBase]> { Sched<[WriteSTIdx, ReadST, ReadAdrBase]> {
let Inst{13} = 0b1; let Inst{13} = 0b1;
} }
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>; def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
} }
class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype, class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
string asm, dag ins, dag outs, list<dag> pat> string asm, dag ins, dag outs, list<dag> pat>
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multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype, multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
string asm, ValueType Ty, SDPatternOperator storeop> { string asm, ValueType Ty, SDPatternOperator storeop> {
let AddedComplexity = 10 in let AddedComplexity = 10 in
def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs), def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
(ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend), (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
[(storeop (Ty regtype:$Rt), [(storeop (Ty regtype:$Rt),
(ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm, (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
ro_Wextend32:$extend))]>, ro_Wextend32:$extend))]>,
Sched<[WriteSTIdx, ReadAdrBase]> { Sched<[WriteSTIdx, ReadST, ReadAdrBase]> {
let Inst{13} = 0b0; let Inst{13} = 0b0;
} }
let AddedComplexity = 10 in let AddedComplexity = 10 in
def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs), def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
(ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend), (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
[(storeop (Ty regtype:$Rt), [(storeop (Ty regtype:$Rt),
(ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm, (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
ro_Xextend32:$extend))]>, ro_Xextend32:$extend))]>,
Sched<[WriteSTIdx, ReadAdrBase]> { Sched<[WriteSTIdx, ReadST, ReadAdrBase]> {
let Inst{13} = 0b1; let Inst{13} = 0b1;
} }
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>; def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
} }
class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype, class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
string asm, dag ins, dag outs, list<dag> pat> string asm, dag ins, dag outs, list<dag> pat>
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multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype, multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
string asm, ValueType Ty, SDPatternOperator storeop> { string asm, ValueType Ty, SDPatternOperator storeop> {
let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs), def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
(ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend), (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
[(storeop (Ty regtype:$Rt), [(storeop (Ty regtype:$Rt),
(ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm, (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
ro_Wextend64:$extend))]>, ro_Wextend64:$extend))]>,
Sched<[WriteSTIdx, ReadAdrBase]> { Sched<[WriteSTIdx, ReadST, ReadAdrBase]> {
let Inst{13} = 0b0; let Inst{13} = 0b0;
} }
let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs), def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
(ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend), (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
[(storeop (Ty regtype:$Rt), [(storeop (Ty regtype:$Rt),
(ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm, (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
ro_Xextend64:$extend))]>, ro_Xextend64:$extend))]>,
Sched<[WriteSTIdx, ReadAdrBase]> { Sched<[WriteSTIdx, ReadST, ReadAdrBase]> {
let Inst{13} = 0b1; let Inst{13} = 0b1;
} }
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>; def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
} }
class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype, class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
string asm, dag ins, dag outs, list<dag> pat> string asm, dag ins, dag outs, list<dag> pat>
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} }
multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype, multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
string asm, ValueType Ty, SDPatternOperator storeop> { string asm, ValueType Ty, SDPatternOperator storeop> {
let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs), def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
(ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend), (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
[]>, []>,
Sched<[WriteSTIdx, ReadAdrBase]> { Sched<[WriteSTIdx, ReadST, ReadAdrBase]> {
let Inst{13} = 0b0; let Inst{13} = 0b0;
} }
let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs), def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
(ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend), (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
[]>, []>,
Sched<[WriteSTIdx, ReadAdrBase]> { Sched<[WriteSTIdx, ReadST, ReadAdrBase]> {
let Inst{13} = 0b1; let Inst{13} = 0b1;
} }
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>; def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
} }
let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
class BasePrefetchRO<bits<2> sz, bit V, bits<2> opc, dag outs, dag ins, class BasePrefetchRO<bits<2> sz, bit V, bits<2> opc, dag outs, dag ins,
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llvm/lib/Target/AArch64/AArch64SchedA53.td

Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Linesdef A53WriteFSqrtDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 32;
let ResourceCycles = [28]; } let ResourceCycles = [28]; }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Subtarget-specific SchedRead types. // Subtarget-specific SchedRead types.
// No forwarding for these reads. // No forwarding for these reads.
def : ReadAdvance<ReadExtrHi, 0>; def : ReadAdvance<ReadExtrHi, 0>;
def : ReadAdvance<ReadAdrBase, 0>; def : ReadAdvance<ReadAdrBase, 0>;
def : ReadAdvance<ReadST, 0>;
def : ReadAdvance<ReadVLD, 0>; def : ReadAdvance<ReadVLD, 0>;
// ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
// operands are needed one cycle later if and only if they are to be // operands are needed one cycle later if and only if they are to be
// shifted. Otherwise, they too are needed two cycles later. This same // shifted. Otherwise, they too are needed two cycles later. This same
// ReadAdvance applies to Extended registers as well, even though there is // ReadAdvance applies to Extended registers as well, even though there is
// a separate SchedPredicate for them. // a separate SchedPredicate for them.
def : ReadAdvance<ReadI, 2, [WriteImm,WriteI, def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
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llvm/lib/Target/AArch64/AArch64SchedA55.td

Show First 20 Lines • Show All 176 Lines • ▼ Show 20 Linesdef CortexA55WriteFSqrtDP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 22;
let ResourceCycles = [19]; } let ResourceCycles = [19]; }
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Subtarget-specific SchedRead types. // Subtarget-specific SchedRead types.
def : ReadAdvance<ReadVLD, 0>; def : ReadAdvance<ReadVLD, 0>;
def : ReadAdvance<ReadExtrHi, 1>; def : ReadAdvance<ReadExtrHi, 1>;
def : ReadAdvance<ReadAdrBase, 1>; def : ReadAdvance<ReadAdrBase, 1>;
def : ReadAdvance<ReadST, 1>;
// ALU - ALU input operands are generally needed in EX1. An operand produced in // ALU - ALU input operands are generally needed in EX1. An operand produced in
// in say EX2 can be forwarded for consumption to ALU in EX1, thereby // in say EX2 can be forwarded for consumption to ALU in EX1, thereby
// allowing back-to-back ALU operations such as add. If an operand requires // allowing back-to-back ALU operations such as add. If an operand requires
// a shift, it will, however, be required in ISS stage. // a shift, it will, however, be required in ISS stage.
def : ReadAdvance<ReadI, 2, [WriteImm,WriteI, def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
WriteISReg, WriteIEReg,WriteIS, WriteISReg, WriteIEReg,WriteIS,
WriteID32,WriteID64, WriteID32,WriteID64,
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llvm/lib/Target/AArch64/AArch64SchedA57.td

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// Forwarding logic is only modeled for multiply and accumulate // Forwarding logic is only modeled for multiply and accumulate
def : ReadAdvance<ReadI, 0>; def : ReadAdvance<ReadI, 0>;
def : ReadAdvance<ReadISReg, 0>; def : ReadAdvance<ReadISReg, 0>;
def : ReadAdvance<ReadIEReg, 0>; def : ReadAdvance<ReadIEReg, 0>;
def : ReadAdvance<ReadIM, 0>; def : ReadAdvance<ReadIM, 0>;
def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>; def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
def : ReadAdvance<ReadID, 0>; def : ReadAdvance<ReadID, 0>;
def : ReadAdvance<ReadExtrHi, 0>; def : ReadAdvance<ReadExtrHi, 0>;
def : ReadAdvance<ReadST, 0>;
def : ReadAdvance<ReadAdrBase, 0>; def : ReadAdvance<ReadAdrBase, 0>;
def : ReadAdvance<ReadVLD, 0>; def : ReadAdvance<ReadVLD, 0>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Specialize the coarse model by associating instruction groups with the // Specialize the coarse model by associating instruction groups with the
// subtarget-defined types. As the modeled is refined, this will override most // subtarget-defined types. As the modeled is refined, this will override most
// of the above ShchedAlias mappings. // of the above ShchedAlias mappings.
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llvm/lib/Target/AArch64/AArch64SchedA64FX.td

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def : ReadAdvance<ReadI, 0>; def : ReadAdvance<ReadI, 0>;
def : ReadAdvance<ReadISReg, 0>; def : ReadAdvance<ReadISReg, 0>;
def : ReadAdvance<ReadIEReg, 0>; def : ReadAdvance<ReadIEReg, 0>;
def : ReadAdvance<ReadIM, 0>; def : ReadAdvance<ReadIM, 0>;
def : ReadAdvance<ReadIMA, 0>; def : ReadAdvance<ReadIMA, 0>;
def : ReadAdvance<ReadID, 0>; def : ReadAdvance<ReadID, 0>;
def : ReadAdvance<ReadExtrHi, 0>; def : ReadAdvance<ReadExtrHi, 0>;
def : ReadAdvance<ReadAdrBase, 0>; def : ReadAdvance<ReadAdrBase, 0>;
def : ReadAdvance<ReadST, 0>;
def : ReadAdvance<ReadVLD, 0>; def : ReadAdvance<ReadVLD, 0>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 3. Instruction Tables. // 3. Instruction Tables.
//--- //---
// 3.1 Branch Instructions // 3.1 Branch Instructions
//--- //---
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llvm/lib/Target/AArch64/AArch64SchedCyclone.td

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// Read the (unshifted) base register Xn in the second micro-op one cycle later. // Read the (unshifted) base register Xn in the second micro-op one cycle later.
// EXAMPLE: LDR Xn, Xm [, lsl 3] // EXAMPLE: LDR Xn, Xm [, lsl 3]
def ReadBaseRS : SchedReadAdvance<1>; def ReadBaseRS : SchedReadAdvance<1>;
def CyReadAdrBase : SchedReadVariant<[ def CyReadAdrBase : SchedReadVariant<[
SchedVar<ScaledIdxPred, [ReadBaseRS]>, // Read base reg after shifting offset. SchedVar<ScaledIdxPred, [ReadBaseRS]>, // Read base reg after shifting offset.
SchedVar<NoSchedPred, [ReadDefault]>]>; // Read base reg with no shift. SchedVar<NoSchedPred, [ReadDefault]>]>; // Read base reg with no shift.
def : SchedAlias<ReadAdrBase, CyReadAdrBase>; // Map AArch64->Cyclone type. def : SchedAlias<ReadAdrBase, CyReadAdrBase>; // Map AArch64->Cyclone type.
def : ReadAdvance<ReadST, 0>;
//--- //---
// 7.8.9,7.8.11. Load/Store, paired // 7.8.9,7.8.11. Load/Store, paired
//--- //---
// Address pre/post increment is a simple ALU op with one cycle latency. // Address pre/post increment is a simple ALU op with one cycle latency.
def : WriteRes<WriteAdr, [CyUnitI]>; def : WriteRes<WriteAdr, [CyUnitI]>;
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llvm/lib/Target/AArch64/AArch64SchedExynosM3.td

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def : ReadAdvance<ReadIEReg, 0>; def : ReadAdvance<ReadIEReg, 0>;
def : ReadAdvance<ReadIM, 0>; def : ReadAdvance<ReadIM, 0>;
// TODO: The forwarding for 32 bits actually saves 2 cycles. // TODO: The forwarding for 32 bits actually saves 2 cycles.
def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
def : ReadAdvance<ReadID, 0>; def : ReadAdvance<ReadID, 0>;
def : ReadAdvance<ReadExtrHi, 0>; def : ReadAdvance<ReadExtrHi, 0>;
def : ReadAdvance<ReadAdrBase, 0>; def : ReadAdvance<ReadAdrBase, 0>;
def : ReadAdvance<ReadVLD, 0>; def : ReadAdvance<ReadVLD, 0>;
def : ReadAdvance<ReadST, 0>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Finer scheduling model. // Finer scheduling model.
def M3WriteNEONA : SchedWriteRes<[M3UnitNSHF, def M3WriteNEONA : SchedWriteRes<[M3UnitNSHF,
M3UnitFADD]> { let Latency = 3; M3UnitFADD]> { let Latency = 3;
let NumMicroOps = 2; } let NumMicroOps = 2; }
def M3WriteNEONB : SchedWriteRes<[M3UnitNALU, def M3WriteNEONB : SchedWriteRes<[M3UnitNALU,
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llvm/lib/Target/AArch64/AArch64SchedExynosM4.td

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def : ReadAdvance<ReadIEReg, 0>; def : ReadAdvance<ReadIEReg, 0>;
def : ReadAdvance<ReadIM, 0>; def : ReadAdvance<ReadIM, 0>;
// TODO: The forwarding for 32 bits actually saves 2 cycles. // TODO: The forwarding for 32 bits actually saves 2 cycles.
def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
def : ReadAdvance<ReadID, 0>; def : ReadAdvance<ReadID, 0>;
def : ReadAdvance<ReadExtrHi, 0>; def : ReadAdvance<ReadExtrHi, 0>;
def : ReadAdvance<ReadAdrBase, 0>; def : ReadAdvance<ReadAdrBase, 0>;
def : ReadAdvance<ReadVLD, 0>; def : ReadAdvance<ReadVLD, 0>;
def : ReadAdvance<ReadST, 0>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Finer scheduling model. // Finer scheduling model.
// Branch instructions // Branch instructions
def : InstRW<[M4WriteB1], (instrs Bcc)>; def : InstRW<[M4WriteB1], (instrs Bcc)>;
def : InstRW<[M4WriteAF], (instrs BL)>; def : InstRW<[M4WriteAF], (instrs BL)>;
def : InstRW<[M4WriteBX], (instrs BLR)>; def : InstRW<[M4WriteBX], (instrs BLR)>;
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llvm/lib/Target/AArch64/AArch64SchedExynosM5.td

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def : ReadAdvance<ReadIEReg, 0>; def : ReadAdvance<ReadIEReg, 0>;
def : ReadAdvance<ReadIM, 0>; def : ReadAdvance<ReadIM, 0>;
// TODO: The forwarding for 32 bits actually saves 2 cycles. // TODO: The forwarding for 32 bits actually saves 2 cycles.
def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
def : ReadAdvance<ReadID, 0>; def : ReadAdvance<ReadID, 0>;
def : ReadAdvance<ReadExtrHi, 0>; def : ReadAdvance<ReadExtrHi, 0>;
def : ReadAdvance<ReadAdrBase, 0>; def : ReadAdvance<ReadAdrBase, 0>;
def : ReadAdvance<ReadVLD, 0>; def : ReadAdvance<ReadVLD, 0>;
def : ReadAdvance<ReadST, 0>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Finer scheduling model. // Finer scheduling model.
// Branch instructions // Branch instructions
def : InstRW<[M5WriteB1], (instrs Bcc)>; def : InstRW<[M5WriteB1], (instrs Bcc)>;
def : InstRW<[M5WriteAFX], (instrs BL)>; def : InstRW<[M5WriteAFX], (instrs BL)>;
def : InstRW<[M5WriteBX], (instrs BLR)>; def : InstRW<[M5WriteBX], (instrs BLR)>;
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llvm/lib/Target/AArch64/AArch64SchedFalkor.td

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def : ReadAdvance<ReadISReg, 0>; def : ReadAdvance<ReadISReg, 0>;
def : ReadAdvance<ReadIEReg, 0>; def : ReadAdvance<ReadIEReg, 0>;
def : ReadAdvance<ReadIM, 0>; def : ReadAdvance<ReadIM, 0>;
def : ReadAdvance<ReadIMA, 0>; def : ReadAdvance<ReadIMA, 0>;
def : ReadAdvance<ReadID, 0>; def : ReadAdvance<ReadID, 0>;
def : ReadAdvance<ReadExtrHi, 0>; def : ReadAdvance<ReadExtrHi, 0>;
def : ReadAdvance<ReadAdrBase, 0>; def : ReadAdvance<ReadAdrBase, 0>;
def : ReadAdvance<ReadVLD, 0>; def : ReadAdvance<ReadVLD, 0>;
def : ReadAdvance<ReadST, 0>;
// Detailed Refinements // Detailed Refinements
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
include "AArch64SchedFalkorDetails.td" include "AArch64SchedFalkorDetails.td"
} }

llvm/lib/Target/AArch64/AArch64SchedKryo.td

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def : ReadAdvance<ReadISReg, 0>; def : ReadAdvance<ReadISReg, 0>;
def : ReadAdvance<ReadIEReg, 0>; def : ReadAdvance<ReadIEReg, 0>;
def : ReadAdvance<ReadIM, 0>; def : ReadAdvance<ReadIM, 0>;
def : ReadAdvance<ReadIMA, 0>; def : ReadAdvance<ReadIMA, 0>;
def : ReadAdvance<ReadID, 0>; def : ReadAdvance<ReadID, 0>;
def : ReadAdvance<ReadExtrHi, 0>; def : ReadAdvance<ReadExtrHi, 0>;
def : ReadAdvance<ReadAdrBase, 0>; def : ReadAdvance<ReadAdrBase, 0>;
def : ReadAdvance<ReadVLD, 0>; def : ReadAdvance<ReadVLD, 0>;
def : ReadAdvance<ReadST, 0>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Specialize the coarse model by associating instruction groups with the // Specialize the coarse model by associating instruction groups with the
// subtarget-defined types. As the modeled is refined, this will override most // subtarget-defined types. As the modeled is refined, this will override most
// of the above SchedWriteRes and SchedAlias mappings. // of the above SchedWriteRes and SchedAlias mappings.
// Miscellaneous // Miscellaneous
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llvm/lib/Target/AArch64/AArch64SchedTSV110.td

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def : ReadAdvance<ReadISReg, 0>; def : ReadAdvance<ReadISReg, 0>;
def : ReadAdvance<ReadIEReg, 0>; def : ReadAdvance<ReadIEReg, 0>;
def : ReadAdvance<ReadIM, 0>; def : ReadAdvance<ReadIM, 0>;
def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>; def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
def : ReadAdvance<ReadID, 0>; def : ReadAdvance<ReadID, 0>;
def : ReadAdvance<ReadExtrHi, 0>; def : ReadAdvance<ReadExtrHi, 0>;
def : ReadAdvance<ReadAdrBase, 0>; def : ReadAdvance<ReadAdrBase, 0>;
def : ReadAdvance<ReadVLD, 0>; def : ReadAdvance<ReadVLD, 0>;
def : ReadAdvance<ReadST, 0>;
def : InstRW<[WriteI], (instrs COPY)>; def : InstRW<[WriteI], (instrs COPY)>;
// Detailed Refinements // Detailed Refinements
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Contains all of the TSV110 specific SchedWriteRes types. The approach // Contains all of the TSV110 specific SchedWriteRes types. The approach
// below is to define a generic SchedWriteRes for every combination of // below is to define a generic SchedWriteRes for every combination of
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llvm/lib/Target/AArch64/AArch64SchedThunderX.td

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//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Subtarget-specific SchedRead types. // Subtarget-specific SchedRead types.
// No forwarding for these reads. // No forwarding for these reads.
def : ReadAdvance<ReadExtrHi, 1>; def : ReadAdvance<ReadExtrHi, 1>;
def : ReadAdvance<ReadAdrBase, 2>; def : ReadAdvance<ReadAdrBase, 2>;
def : ReadAdvance<ReadVLD, 2>; def : ReadAdvance<ReadVLD, 2>;
def : ReadAdvance<ReadST, 2>;
// FIXME: This needs more targeted benchmarking. // FIXME: This needs more targeted benchmarking.
// ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
// operands are needed one cycle later if and only if they are to be // operands are needed one cycle later if and only if they are to be
// shifted. Otherwise, they too are needed two cycles later. This same // shifted. Otherwise, they too are needed two cycles later. This same
// ReadAdvance applies to Extended registers as well, even though there is // ReadAdvance applies to Extended registers as well, even though there is
// a separate SchedPredicate for them. // a separate SchedPredicate for them.
def : ReadAdvance<ReadI, 2, [WriteImm, WriteI, def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
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llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td

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def : ReadAdvance<ReadISReg, 0>; def : ReadAdvance<ReadISReg, 0>;
def : ReadAdvance<ReadIEReg, 0>; def : ReadAdvance<ReadIEReg, 0>;
def : ReadAdvance<ReadIM, 0>; def : ReadAdvance<ReadIM, 0>;
def : ReadAdvance<ReadIMA, 0>; def : ReadAdvance<ReadIMA, 0>;
def : ReadAdvance<ReadID, 0>; def : ReadAdvance<ReadID, 0>;
def : ReadAdvance<ReadExtrHi, 0>; def : ReadAdvance<ReadExtrHi, 0>;
def : ReadAdvance<ReadAdrBase, 0>; def : ReadAdvance<ReadAdrBase, 0>;
def : ReadAdvance<ReadVLD, 0>; def : ReadAdvance<ReadVLD, 0>;
def : ReadAdvance<ReadST, 0>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 3. Instruction Tables. // 3. Instruction Tables.
//--- //---
// 3.1 Branch Instructions // 3.1 Branch Instructions
//--- //---
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llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td

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def : ReadAdvance<ReadISReg, 0>; def : ReadAdvance<ReadISReg, 0>;
def : ReadAdvance<ReadIEReg, 0>; def : ReadAdvance<ReadIEReg, 0>;
def : ReadAdvance<ReadIM, 0>; def : ReadAdvance<ReadIM, 0>;
def : ReadAdvance<ReadIMA, 0>; def : ReadAdvance<ReadIMA, 0>;
def : ReadAdvance<ReadID, 0>; def : ReadAdvance<ReadID, 0>;
def : ReadAdvance<ReadExtrHi, 0>; def : ReadAdvance<ReadExtrHi, 0>;
def : ReadAdvance<ReadAdrBase, 0>; def : ReadAdvance<ReadAdrBase, 0>;
def : ReadAdvance<ReadVLD, 0>; def : ReadAdvance<ReadVLD, 0>;
def : ReadAdvance<ReadST, 0>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 3. Instruction Tables. // 3. Instruction Tables.
//--- //---
// 3.1 Branch Instructions // 3.1 Branch Instructions
//--- //---
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llvm/lib/Target/AArch64/AArch64Schedule.td

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def WriteLD : SchedWrite; // Load from base addr plus immediate offset def WriteLD : SchedWrite; // Load from base addr plus immediate offset
def WriteST : SchedWrite; // Store to base addr plus immediate offset def WriteST : SchedWrite; // Store to base addr plus immediate offset
def WriteSTP : SchedWrite; // Store a register pair. def WriteSTP : SchedWrite; // Store a register pair.
def WriteAdr : SchedWrite; // Address pre/post increment. def WriteAdr : SchedWrite; // Address pre/post increment.
def WriteLDIdx : SchedWrite; // Load from a register index (maybe scaled). def WriteLDIdx : SchedWrite; // Load from a register index (maybe scaled).
def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled). def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled).
def ReadST : SchedRead; // Read the stored value.
def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST. def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.
// Serialized two-level address load. // Serialized two-level address load.
// EXAMPLE: LOADGot // EXAMPLE: LOADGot
def WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>; def WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>;
// Serialized two-level address lookup. // Serialized two-level address lookup.
// EXAMPLE: MOVaddr... // EXAMPLE: MOVaddr...
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llvm/test/tools/llvm-mca/AArch64/Cortex/A55-store-readadv.s

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stp x0, x1, [x2, #16] stp x0, x1, [x2, #16]
add x2, x3, #1 add x2, x3, #1
stp x0, x1, [x2, #16]! stp x0, x1, [x2, #16]!
add x2, x3, #1 add x2, x3, #1
stp x0, x1, [x2], #16 stp x0, x1, [x2], #16
# CHECK: Iterations: 100 # CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 11800 # CHECK-NEXT: Instructions: 11800
# CHECK-NEXT: Total Cycles: 20301 # CHECK-NEXT: Total Cycles: 19801
# CHECK-NEXT: Total uOps: 14400 # CHECK-NEXT: Total uOps: 14400
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.71 # CHECK-NEXT: uOps Per Cycle: 0.73
# CHECK-NEXT: IPC: 0.58 # CHECK-NEXT: IPC: 0.60
# CHECK-NEXT: Block RThroughput: 72.0 # CHECK-NEXT: Block RThroughput: 72.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add x2, x3, #1 # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add x2, x3, #1
# CHECK-NEXT: - - - - - - - - - - - 1.00 stp x0, x1, [x2, #16] # CHECK-NEXT: - - - - - - - - - - - 1.00 stp x0, x1, [x2, #16]
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add x2, x3, #1 # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add x2, x3, #1
# CHECK-NEXT: - - - - - - - - - - - 1.00 stp x0, x1, [x2, #16]! # CHECK-NEXT: - - - - - - - - - - - 1.00 stp x0, x1, [x2, #16]!
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add x2, x3, #1 # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add x2, x3, #1
# CHECK-NEXT: - - - - - - - - - - - 1.00 stp x0, x1, [x2], #16 # CHECK-NEXT: - - - - - - - - - - - 1.00 stp x0, x1, [x2], #16
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 # CHECK-NEXT: 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 012345678
# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123 # CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789
# CHECK: [0,0] DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK: [0,0] DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,1] . DE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str b0, [x2, #16] # CHECK-NEXT: [0,1] . DE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str b0, [x2, #16]
# CHECK-NEXT: [0,2] . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,2] . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,3] . .DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str b0, [x2, #16]! # CHECK-NEXT: [0,3] . .DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str b0, [x2, #16]!
# CHECK-NEXT: [0,4] . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,4] . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,5] . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str b0, [x2], #16 # CHECK-NEXT: [0,5] . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str b0, [x2], #16
# CHECK-NEXT: [0,6] . . .DeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,6] . . .DeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,7] . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str d0, [x2], #16 # CHECK-NEXT: [0,7] . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str d0, [x2], #16
# CHECK-NEXT: [0,8] . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,8] . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,9] . . . . DE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str d0, [x2, #16]! # CHECK-NEXT: [0,9] . . . . DE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str d0, [x2, #16]!
# CHECK-NEXT: [0,10] . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,10] . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,11] . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str d0, [x2, #16] # CHECK-NEXT: [0,11] . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str d0, [x2, #16]
# CHECK-NEXT: [0,12] . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,12] . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,13] . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str h0, [x2], #16 # CHECK-NEXT: [0,13] . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str h0, [x2], #16
# CHECK-NEXT: [0,14] . . . . . .DeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,14] . . . . . .DeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,15] . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str h0, [x2, #16]! # CHECK-NEXT: [0,15] . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str h0, [x2, #16]!
# CHECK-NEXT: [0,16] . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,16] . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,17] . . . . . . . DE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str h0, [x2, #16] # CHECK-NEXT: [0,17] . . . . . . . DE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str h0, [x2, #16]
# CHECK-NEXT: [0,18] . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,18] . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,19] . . . . . . . .DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str q0, [x2], #16 # CHECK-NEXT: [0,19] . . . . . . . .DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str q0, [x2], #16
# CHECK-NEXT: [0,20] . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,20] . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,21] . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str q0, [x2, #16]! # CHECK-NEXT: [0,21] . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str q0, [x2, #16]!
# CHECK-NEXT: [0,22] . . . . . . . . .DeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,22] . . . . . . . . .DeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,23] . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str q0, [x2, #16] # CHECK-NEXT: [0,23] . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str q0, [x2, #16]
# CHECK-NEXT: [0,24] . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,24] . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,25] . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str s0, [x2], #16 # CHECK-NEXT: [0,25] . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str s0, [x2], #16
# CHECK-NEXT: [0,26] . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,26] . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,27] . . . . . . . . . . .DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str s0, [x2, #16]! # CHECK-NEXT: [0,27] . . . . . . . . . . .DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str s0, [x2, #16]!
# CHECK-NEXT: [0,28] . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,28] . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,29] . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str s0, [x2, #16] # CHECK-NEXT: [0,29] . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str s0, [x2, #16]
# CHECK-NEXT: [0,30] . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,30] . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,31] . . . . . . . . . . . . DE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str w0, [x2], #16 # CHECK-NEXT: [0,31] . . . . . . . . . . . . DE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . str w0, [x2], #16
# CHECK-NEXT: [0,32] . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,32] . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,33] . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . str w0, [x2, #16]! # CHECK-NEXT: [0,33] . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . str w0, [x2, #16]!
# CHECK-NEXT: [0,34] . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,34] . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,35] . . . . . . . . . . . . . .DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . str w0, [x2, #16] # CHECK-NEXT: [0,35] . . . . . . . . . . . . . .DE . . . . . . . . . . . . . . . . . . . . . . . . . . . str w0, [x2, #16]
# CHECK-NEXT: [0,36] . . . . . . . . . . . . . .DeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,36] . . . . . . . . . . . . . .DeeE. . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,37] . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . . str x0, [x2], #16 # CHECK-NEXT: [0,37] . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . str x0, [x2], #16
# CHECK-NEXT: [0,38] . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,38] . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,39] . . . . . . . . . . . . . . . DE. . . . . . . . . . . . . . . . . . . . . . . . . . . str x0, [x2, #16]! # CHECK-NEXT: [0,39] . . . . . . . . . . . . . . . DE. . . . . . . . . . . . . . . . . . . . . . . . . . str x0, [x2, #16]!
# CHECK-NEXT: [0,40] . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,40] . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,41] . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . . str x0, [x2, #16] # CHECK-NEXT: [0,41] . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . str x0, [x2, #16]
# CHECK-NEXT: [0,42] . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,42] . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,43] . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . . strb w0, [x2], #16 # CHECK-NEXT: [0,43] . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . strb w0, [x2], #16
# CHECK-NEXT: [0,44] . . . . . . . . . . . . . . . . .DeeE. . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,44] . . . . . . . . . . . . . . . . .DeeE. . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,45] . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . . strb w0, [x2, #16]! # CHECK-NEXT: [0,45] . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . . strb w0, [x2, #16]!
# CHECK-NEXT: [0,46] . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,46] . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,47] . . . . . . . . . . . . . . . . . . DE. . . . . . . . . . . . . . . . . . . . . . . . strb w0, [x2, #16] # CHECK-NEXT: [0,47] . . . . . . . . . . . . . . . . . . DE. . . . . . . . . . . . . . . . . . . . . . . strb w0, [x2, #16]
# CHECK-NEXT: [0,48] . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,48] . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,49] . . . . . . . . . . . . . . . . . . .DE . . . . . . . . . . . . . . . . . . . . . . . strh w0, [x2], #16 # CHECK-NEXT: [0,49] . . . . . . . . . . . . . . . . . . .DE . . . . . . . . . . . . . . . . . . . . . . strh w0, [x2], #16
# CHECK-NEXT: [0,50] . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,50] . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,51] . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . . strh w0, [x2, #16]! # CHECK-NEXT: [0,51] . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . strh w0, [x2, #16]!
# CHECK-NEXT: [0,52] . . . . . . . . . . . . . . . . . . . .DeeE. . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,52] . . . . . . . . . . . . . . . . . . . .DeeE. . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,53] . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . strh w0, [x2, #16] # CHECK-NEXT: [0,53] . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . strh w0, [x2, #16]
# CHECK-NEXT: [0,54] . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,54] . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,55] . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . . str d0, [x2, x2, lsl #3] # CHECK-NEXT: [0,55] . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . str d0, [x2, x2, lsl #3]
# CHECK-NEXT: [0,56] . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,56] . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,57] . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . . str q0, [x2, w0, sxtw] # CHECK-NEXT: [0,57] . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . . str q0, [x2, w0, sxtw]
# CHECK-NEXT: [0,58] . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,58] . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,59] . . . . . . . . . . . . . . . . . . . . . . DE. . . . . . . . . . . . . . . . . . . . str w0, [x2, w0, sxtw] # CHECK-NEXT: [0,59] . . . . . . . . . . . . . . . . . . . . . .DE . . . . . . . . . . . . . . . . . . . str w0, [x2, w0, sxtw]
# CHECK-NEXT: [0,60] . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,60] . . . . . . . . . . . . . . . . . . . . . .DeeE. . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,61] . . . . . . . . . . . . . . . . . . . . . . .DE . . . . . . . . . . . . . . . . . . . str x0, [x2, w0, sxtw] # CHECK-NEXT: [0,61] . . . . . . . . . . . . . . . . . . . . . . DE. . . . . . . . . . . . . . . . . . . str x0, [x2, w0, sxtw]
# CHECK-NEXT: [0,62] . . . . . . . . . . . . . . . . . . . . . . .DeeE. . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,62] . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,63] . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . strb w0, [x2, w0, sxtw] # CHECK-NEXT: [0,63] . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . strb w0, [x2, w0, sxtw]
# CHECK-NEXT: [0,64] . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,64] . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,65] . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . strh w0, [x2, w0, sxtw] # CHECK-NEXT: [0,65] . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . . strh w0, [x2, w0, sxtw]
# CHECK-NEXT: [0,66] . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,66] . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,67] . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . stur b0, [x2, #255] # CHECK-NEXT: [0,67] . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . . . stur b0, [x2, #255]
# CHECK-NEXT: [0,68] . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,68] . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,69] . . . . . . . . . . . . . . . . . . . . . . . . . DE. . . . . . . . . . . . . . . . . stur d0, [x2, #255] # CHECK-NEXT: [0,69] . . . . . . . . . . . . . . . . . . . . . . . . DE. . . . . . . . . . . . . . . . . stur d0, [x2, #255]
# CHECK-NEXT: [0,70] . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,70] . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,71] . . . . . . . . . . . . . . . . . . . . . . . . . .DE . . . . . . . . . . . . . . . . stur h0, [x2, #255] # CHECK-NEXT: [0,71] . . . . . . . . . . . . . . . . . . . . . . . . .DE . . . . . . . . . . . . . . . . stur h0, [x2, #255]
# CHECK-NEXT: [0,72] . . . . . . . . . . . . . . . . . . . . . . . . . .DeeE. . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,72] . . . . . . . . . . . . . . . . . . . . . . . . .DeeE. . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,73] . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . stur q0, [x2, #255] # CHECK-NEXT: [0,73] . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . stur q0, [x2, #255]
# CHECK-NEXT: [0,74] . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,74] . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,75] . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . stur s0, [x2, #255] # CHECK-NEXT: [0,75] . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . . stur s0, [x2, #255]
# CHECK-NEXT: [0,76] . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,76] . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,77] . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . stur w0, [x2, #255] # CHECK-NEXT: [0,77] . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . . . stur w0, [x2, #255]
# CHECK-NEXT: [0,78] . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,78] . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,79] . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE. . . . . . . . . . . . . . sturb w0, [x2, #255] # CHECK-NEXT: [0,79] . . . . . . . . . . . . . . . . . . . . . . . . . . . DE. . . . . . . . . . . . . . sturb w0, [x2, #255]
# CHECK-NEXT: [0,80] . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,80] . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,81] . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DE . . . . . . . . . . . . . sturh w0, [x2, #255] # CHECK-NEXT: [0,81] . . . . . . . . . . . . . . . . . . . . . . . . . . . .DE . . . . . . . . . . . . . sturh w0, [x2, #255]
# CHECK-NEXT: [0,82] . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DeeE. . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,82] . . . . . . . . . . . . . . . . . . . . . . . . . . . .DeeE. . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,83] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . stnp d0, d1, [x2, #16] # CHECK-NEXT: [0,83] . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . stnp d0, d1, [x2, #16]
# CHECK-NEXT: [0,84] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,84] . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,85] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . stnp q0, q1, [x2, #16] # CHECK-NEXT: [0,85] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . . stnp q0, q1, [x2, #16]
# CHECK-NEXT: [0,86] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,86] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,87] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . stnp s0, s1, [x2, #16] # CHECK-NEXT: [0,87] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . . . stnp s0, s1, [x2, #16]
# CHECK-NEXT: [0,88] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,88] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,89] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE. . . . . . . . . . . stnp s0, s1, [x2, #16] # CHECK-NEXT: [0,89] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE. . . . . . . . . . . stnp s0, s1, [x2, #16]
# CHECK-NEXT: [0,90] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,90] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,91] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DE . . . . . . . . . . stnp w0, w1, [x2, #16] # CHECK-NEXT: [0,91] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DE . . . . . . . . . . stnp w0, w1, [x2, #16]
# CHECK-NEXT: [0,92] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DeeE. . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,92] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DeeE. . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,93] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . stnp x0, x1, [x2, #16] # CHECK-NEXT: [0,93] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . stnp x0, x1, [x2, #16]
# CHECK-NEXT: [0,94] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,94] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,95] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . stp d0, d1, [x2, #16] # CHECK-NEXT: [0,95] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . . stp d0, d1, [x2, #16]
# CHECK-NEXT: [0,96] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,96] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,97] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . stp d0, d1, [x2, #16]! # CHECK-NEXT: [0,97] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . . stp d0, d1, [x2, #16]!
# CHECK-NEXT: [0,98] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DeeE. . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,98] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DeeE. . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,99] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . stp d0, d1, [x2], #16 # CHECK-NEXT: [0,99] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . . . stp d0, d1, [x2], #16
# CHECK-NEXT: [0,100] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,100] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,101] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE. . . . . . . stp q0, q1, [x2, #16] # CHECK-NEXT: [0,101] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE. . . . . . . stp q0, q1, [x2, #16]
# CHECK-NEXT: [0,102] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . add x2, x3, #1 # CHECK-NEXT: [0,102] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . . add x2, x3, #1
# CHECK-NEXT: [0,103] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DE . . . . . . stp q0, q1, [x2, #16]! # CHECK-NEXT: [0,103] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DE . . . . . . stp q0, q1, [x2, #16]!
# CHECK-NEXT: [0,104] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . add x2, x3, #1 # CHECK-NEXT: [0,104] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . . add x2, x3, #1
# CHECK-NEXT: [0,105] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . stp q0, q1, [x2], #16 # CHECK-NEXT: [0,105] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . . stp q0, q1, [x2], #16
# CHECK-NEXT: [0,106] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DeeE. . . . . add x2, x3, #1 # CHECK-NEXT: [0,106] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DeeE. . . . . add x2, x3, #1
# CHECK-NEXT: [0,107] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . stp s0, s1, [x2, #16] # CHECK-NEXT: [0,107] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . stp s0, s1, [x2, #16]
# CHECK-NEXT: [0,108] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . add x2, x3, #1 # CHECK-NEXT: [0,108] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . . add x2, x3, #1
# CHECK-NEXT: [0,109] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . stp s0, s1, [x2, #16]! # CHECK-NEXT: [0,109] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . . . stp s0, s1, [x2, #16]!
# CHECK-NEXT: [0,110] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . add x2, x3, #1 # CHECK-NEXT: [0,110] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . . add x2, x3, #1
# CHECK-NEXT: [0,111] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DE . . . stp s0, s1, [x2], #16 # CHECK-NEXT: [0,111] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DE . . . stp s0, s1, [x2], #16
# CHECK-NEXT: [0,112] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . add x2, x3, #1 # CHECK-NEXT: [0,112] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . add x2, x3, #1
# CHECK-NEXT: [0,113] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . stp x0, x1, [x2, #16] # CHECK-NEXT: [0,113] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE . . stp x0, x1, [x2, #16]
# CHECK-NEXT: [0,114] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . add x2, x3, #1 # CHECK-NEXT: [0,114] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE . . add x2, x3, #1
# CHECK-NEXT: [0,115] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE. . stp x0, x1, [x2, #16]! # CHECK-NEXT: [0,115] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE. . stp x0, x1, [x2, #16]!
# CHECK-NEXT: [0,116] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE. add x2, x3, #1 # CHECK-NEXT: [0,116] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DeeE. add x2, x3, #1
# CHECK-NEXT: [0,117] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE stp x0, x1, [x2], #16 # CHECK-NEXT: [0,117] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DE stp x0, x1, [x2], #16
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
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