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Differential D107710

[RISCV][test] Improve tests for (add (mul x, c1), c2)
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Authored by benshi001 on Aug 8 2021, 3:01 AM.

Details

Reviewers
craig.topper
luismarques
asb
Commits
rGb10e74389e1e: [RISCV][test] Improve tests for (add (mul x, c1), c2)

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Event Timeline

benshi001 created this revision.Aug 8 2021, 3:01 AM
Herald added subscribers: vkmr, frasercrmck, evandro and 22 others. · View Herald TranscriptAug 8 2021, 3:01 AM
benshi001 requested review of this revision.Aug 8 2021, 3:01 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 8 2021, 3:01 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B118543: Diff 365010.Aug 8 2021, 3:01 AM
benshi001 added a child revision: D107711: [DAGCombiner] Add target hook function to decide folding (mul (add x, c1), c2).Aug 8 2021, 3:05 AM
benshi001 updated this revision to Diff 365020.Aug 8 2021, 7:24 AM
Harbormaster completed remote builds in B118551: Diff 365020.Aug 8 2021, 7:25 AM
benshi001 updated this revision to Diff 365021.Aug 8 2021, 7:25 AM
benshi001 set the repository for this revision to rG LLVM Github Monorepo.
Harbormaster completed remote builds in B118552: Diff 365021.Aug 8 2021, 7:25 AM
benshi001 updated this revision to Diff 365025.Aug 8 2021, 8:01 AM
Harbormaster completed remote builds in B118556: Diff 365025.Aug 8 2021, 8:29 AM
benshi001 updated this revision to Diff 365072.Aug 8 2021, 9:41 PM
Harbormaster completed remote builds in B118597: Diff 365072.Aug 8 2021, 10:15 PM
benshi001 updated this revision to Diff 365403.Aug 10 2021, 3:05 AM
benshi001 retitled this revision from [RISCV][test] Improve tests for (add (mul x, c0), c1) to [RISCV][test] Improve tests for (add (mul x, c1), c2).
benshi001 edited the summary of this revision. (Show Details)
Harbormaster completed remote builds in B118834: Diff 365403.Aug 10 2021, 3:35 AM
benshi001 updated this revision to Diff 365469.Aug 10 2021, 7:12 AM
Harbormaster completed remote builds in B118881: Diff 365469.Aug 10 2021, 7:56 AM
benshi001 added a comment.Aug 18 2021, 2:39 AM

Can this also be approved? Its child revision https://reviews.llvm.org/D107711 has been approved.

luismarques accepted this revision.Aug 19 2021, 2:08 AM

LGTM.

This revision is now accepted and ready to land.Aug 19 2021, 2:08 AM
Closed by commit rGb10e74389e1e: [RISCV][test] Improve tests for (add (mul x, c1), c2) (authored by benshi001). · Explain WhyAug 19 2021, 6:04 AM
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rGb10e74389e1e: [RISCV][test] Improve tests for (add (mul x, c1), c2).

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
165 lines

Diff 365010

llvm/test/CodeGen/RISCV/addimm-mulimm.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;; Test that (mul (add x, c1), c2) can be transformed to ;; Test that (mul (add x, c1), c2) can be transformed to
;; (add (mul x, c2), c1*c2) if profitable. ;; (add (mul x, c2), c1*c2) if profitable.
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IM %s ; RUN: | FileCheck -check-prefix=RV32IM %s
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IM %s ; RUN: | FileCheck -check-prefix=RV64IM %s
define signext i32 @add_mul_trans_accept_1(i32 %x) { define i32 @add_mul_trans_reject_a0(i32 %x) {
; RV32IM-LABEL: add_mul_trans_accept_1 ; RV32IM-LABEL: add_mul_trans_reject_a0:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a1, zero, 11 ; RV32IM-NEXT: addi a1, zero, 11
; RV32IM-NEXT: mul a0, a0, a1 ; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: addi a0, a0, 407 ; RV32IM-NEXT: addi a0, a0, 407
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64IM-LABEL: add_mul_trans_accept_1 ; RV64IM-LABEL: add_mul_trans_reject_a0:
; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, 11
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: addi a0, a0, 407
; RV64IM-NEXT: ret
%tmp0 = add i32 %x, 37
%tmp1 = mul i32 %tmp0, 11
ret i32 %tmp1
}
define signext i32 @add_mul_trans_reject_a1(i32 signext %x) {
; RV32IM-LABEL: add_mul_trans_reject_a1:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a1, zero, 11
; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: addi a0, a0, 407
; RV32IM-NEXT: ret
;
; RV64IM-LABEL: add_mul_trans_reject_a1:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, 11 ; RV64IM-NEXT: addi a1, zero, 11
; RV64IM-NEXT: mul a0, a0, a1 ; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: addiw a0, a0, 407 ; RV64IM-NEXT: addiw a0, a0, 407
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%tmp0 = add i32 %x, 37 %tmp0 = add i32 %x, 37
%tmp1 = mul i32 %tmp0, 11 %tmp1 = mul i32 %tmp0, 11
ret i32 %tmp1 ret i32 %tmp1
} }
define signext i32 @add_mul_trans_accept_2(i32 %x) { define i64 @add_mul_trans_reject_a2(i64 %x) {
; RV32IM-LABEL: add_mul_trans_accept_2 ; RV32IM-LABEL: add_mul_trans_reject_a2:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a2, zero, 11
; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: mulhu a3, a0, a2
; RV32IM-NEXT: add a1, a3, a1
; RV32IM-NEXT: mul a2, a0, a2
; RV32IM-NEXT: addi a0, a2, 407
; RV32IM-NEXT: sltu a2, a0, a2
; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: ret
;
; RV64IM-LABEL: add_mul_trans_reject_a2:
; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, 11
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: addi a0, a0, 407
; RV64IM-NEXT: ret
%tmp0 = add i64 %x, 37
%tmp1 = mul i64 %tmp0, 11
ret i64 %tmp1
}
define i32 @add_mul_trans_reject_b0(i32 %x) {
; RV32IM-LABEL: add_mul_trans_reject_b0:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a1, zero, 13
; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: lui a1, 28
; RV32IM-NEXT: addi a1, a1, 1701
; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: ret
;
; RV64IM-LABEL: add_mul_trans_reject_b0:
; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, 13
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: lui a1, 28
; RV64IM-NEXT: addiw a1, a1, 1701
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: ret
%tmp0 = add i32 %x, 8953
%tmp1 = mul i32 %tmp0, 13
ret i32 %tmp1
}
define signext i32 @add_mul_trans_reject_b1(i32 signext %x) {
; RV32IM-LABEL: add_mul_trans_reject_b1:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a1, zero, 13 ; RV32IM-NEXT: addi a1, zero, 13
; RV32IM-NEXT: mul a0, a0, a1 ; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: lui a1, 28 ; RV32IM-NEXT: lui a1, 28
; RV32IM-NEXT: addi a1, a1, 1701 ; RV32IM-NEXT: addi a1, a1, 1701
; RV32IM-NEXT: add a0, a0, a1 ; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64IM-LABEL: add_mul_trans_accept_2 ; RV64IM-LABEL: add_mul_trans_reject_b1:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, 13 ; RV64IM-NEXT: addi a1, zero, 13
; RV64IM-NEXT: mul a0, a0, a1 ; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: lui a1, 28 ; RV64IM-NEXT: lui a1, 28
; RV64IM-NEXT: addiw a1, a1, 1701 ; RV64IM-NEXT: addiw a1, a1, 1701
; RV64IM-NEXT: addw a0, a0, a1 ; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%tmp0 = add i32 %x, 8953 %tmp0 = add i32 %x, 8953
%tmp1 = mul i32 %tmp0, 13 %tmp1 = mul i32 %tmp0, 13
ret i32 %tmp1 ret i32 %tmp1
} }
define signext i32 @add_mul_trans_reject_1(i32 %x) { define i64 @add_mul_trans_reject_b2(i64 %x) {
; RV32IM-LABEL: add_mul_trans_reject_1 ; RV32IM-LABEL: add_mul_trans_reject_b2:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a2, zero, 13
; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: mulhu a3, a0, a2
; RV32IM-NEXT: add a1, a3, a1
; RV32IM-NEXT: mul a2, a0, a2
; RV32IM-NEXT: lui a0, 28
; RV32IM-NEXT: addi a0, a0, 1701
; RV32IM-NEXT: add a0, a2, a0
; RV32IM-NEXT: sltu a2, a0, a2
; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: ret
;
; RV64IM-LABEL: add_mul_trans_reject_b2:
; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, 13
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: lui a1, 28
; RV64IM-NEXT: addiw a1, a1, 1701
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: ret
%tmp0 = add i64 %x, 8953
%tmp1 = mul i64 %tmp0, 13
ret i64 %tmp1
}
define i32 @add_mul_trans_accept_a0(i32 %x) {
; RV32IM-LABEL: add_mul_trans_accept_a0:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a1, zero, 19 ; RV32IM-NEXT: addi a1, zero, 19
; RV32IM-NEXT: mul a0, a0, a1 ; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: lui a1, 9 ; RV32IM-NEXT: lui a1, 9
; RV32IM-NEXT: addi a1, a1, 585 ; RV32IM-NEXT: addi a1, a1, 585
; RV32IM-NEXT: add a0, a0, a1 ; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64IM-LABEL: add_mul_trans_reject_1 ; RV64IM-LABEL: add_mul_trans_accept_a0:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, 19 ; RV64IM-NEXT: addi a1, zero, 19
; RV64IM-NEXT: mul a0, a0, a1 ; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: lui a1, 9 ; RV64IM-NEXT: lui a1, 9
; RV64IM-NEXT: addiw a1, a1, 585 ; RV64IM-NEXT: addiw a1, a1, 585
; RV64IM-NEXT: addw a0, a0, a1 ; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%tmp0 = add i32 %x, 1971 %tmp0 = add i32 %x, 1971
%tmp1 = mul i32 %tmp0, 19 %tmp1 = mul i32 %tmp0, 19
ret i32 %tmp1 ret i32 %tmp1
} }
define signext i32 @add_mul_trans_reject_2(i32 %x) { define signext i32 @add_mul_trans_accept_a1(i32 signext %x) {
; RV32IM-LABEL: add_mul_trans_accept_a1:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 792 ; RV32IM-NEXT: addi a1, zero, 19
; RV32IM-NEXT: addi a1, a1, -1709
; RV32IM-NEXT: mul a0, a0, a1 ; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: lui a1, 1014660 ; RV32IM-NEXT: lui a1, 9
; RV32IM-NEXT: addi a1, a1, -1891 ; RV32IM-NEXT: addi a1, a1, 585
; RV32IM-NEXT: add a0, a0, a1 ; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64IM-LABEL: add_mul_trans_accept_a1:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a1, 792 ; RV64IM-NEXT: addi a1, zero, 19
; RV64IM-NEXT: addiw a1, a1, -1709
; RV64IM-NEXT: mul a0, a0, a1 ; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: lui a1, 1014660 ; RV64IM-NEXT: lui a1, 9
; RV64IM-NEXT: addiw a1, a1, -1891 ; RV64IM-NEXT: addiw a1, a1, 585
; RV64IM-NEXT: addw a0, a0, a1 ; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%tmp0 = add i32 %x, 1841231 %tmp0 = add i32 %x, 1971
%tmp1 = mul i32 %tmp0, 3242323 %tmp1 = mul i32 %tmp0, 19
ret i32 %tmp1 ret i32 %tmp1
} }
define i64 @add_mul_trans_accept_a2(i64 %x) {
; RV32IM-LABEL: add_mul_trans_accept_a2:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a2, zero, 19
; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: mulhu a3, a0, a2
; RV32IM-NEXT: add a1, a3, a1
; RV32IM-NEXT: mul a2, a0, a2
; RV32IM-NEXT: lui a0, 9
; RV32IM-NEXT: addi a0, a0, 585
; RV32IM-NEXT: add a0, a2, a0
; RV32IM-NEXT: sltu a2, a0, a2
; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: ret
;
; RV64IM-LABEL: add_mul_trans_accept_a2:
; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, 19
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: lui a1, 9
; RV64IM-NEXT: addiw a1, a1, 585
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: ret
%tmp0 = add i64 %x, 1971
%tmp1 = mul i64 %tmp0, 19
ret i64 %tmp1
}