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Differential D107213

Disassemble AArch64 pc-relative address calculations & symbolicate
ClosedPublic

Authored by jasonmolenda on Jul 31 2021, 12:53 AM.

Details

Reviewers
DavidSpickett
Commits
rG7150b562081f: Symbolicate aarch64 adrp+add pc-relative addr in disass
Summary

lldb's disassembler for arm64 / aarch64 doesn't recognize the ADRP+ADD instruction pair often used to calculate pc-relative addresses, and symbolicate what is being pointed to, making it hard to understand the assembly; doing the computation manually is annoying. This patch adds a bit of arm64-specific knowledge to the disassembly symbolicator to remember the state and compute the address being specified when the target is aarch64.

I'm fixing the other thing that I dislike the most about lldb's arm64 disassembly in the llvm aarch64 instruction printer, via https://reviews.llvm.org/D107196 .

Diff Detail

Event Timeline

jasonmolenda created this revision.Jul 31 2021, 12:53 AM
Herald added subscribers: omjavaid, danielkiss, JDevlieghere, kristof.beyls. · View Herald TranscriptJul 31 2021, 12:53 AM
jasonmolenda requested review of this revision.Jul 31 2021, 12:53 AM
Harbormaster completed remote builds in B117307: Diff 363274.Jul 31 2021, 1:25 AM
DavidSpickett added a subscriber: DavidSpickett.Aug 2 2021, 2:24 AM

The test is with MachO but I assume this would apply to ELF, COFF etc, since it's a general disassembly feature?

lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
1315

Add aarch64_be here.

Triple does have a isAArch64 which does this but I think you just get the ArchType enum here so you can't use it which is a shame.

1325

There is a 32 bit variant of ADD with W registers, I assume LLVMDisassembler_ReferenceType_In_ARM64_ADDXri is specific to the X version though, correct?

Which saves you checking the "sf" field later. (plus I don't know that any compiler would bother using the W version for this sort of thing anyway)

1328

Add comments to these two lines saying what they're checking for.

(looks correct from what the ARMARM says)

1332–1335

Comments here too. The second one is sign extension, correct?

1339

"sh" is a single bit field so you could just:

if ((addrxi_inst >> 22) & 1)
1342

ditto on the comments, but the math seems fine.

1347

This method is pretty long as it is, does it make sense to make the aarch64 specific part of it another private method?

lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.h
77

Just to check I understand, these are member vars because SymbolLookup will first be called on the adrp. So you write these values, then it's called again for the add, which is where you use them?

If so I would add a comment along those lines.

lldb/test/API/functionalities/disassemble/aarch64-adrp-add/TestAArch64AdrpAdd.py
36

You could break after finding it.

37

if not found_hi_string and...

42

A message would help here, like "Did not find \"HI\" string in disassembly.".

Of course if you want to debug it the logging is actually going to help but just for anyone seeing it as a random failure in a general test suite run.

jasonmolenda added a comment.Aug 4 2021, 12:42 AM

Thanks so much for taking the time to read the patch over and make suggestions David. I cribbed the bit masking / manip from MachODump.cpp's SymbolizerSymbolLookUp but you're right about it being better with at least a little bit of comments about what is going on there.

Yeah, this is a very aarch64 specific thing in the generic symbolizer, but it's not an especially large function so I didn't feel too bad about it. If we started needing to handle multi-instruction sequences like this in the symbolizer (where we save state from previous instructions to determine a result), then this definitely would not scale well.

I've written it so that I only recognize the pattern with ADRP is immediately followed by an ADD, that was maybe a choice I could have gone either way on. I clear the saved ADRP instruction when it's not followed by that ADD in the same instruction. I didn't want to mis-calculate an address if the instruction pair using the same register were in two different basic blocks or something.

lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
1325

Ah, good point. I did a quick check and clang currently generates the same adrp+add with an x register, and then ANDs the result with 0xffffffff for our "arm64_32" target (ILP32 codegen that executes in the lower 4GB of virtual address space but uses the aarch64 ISA), so it works out.

DavidSpickett added a comment.Aug 4 2021, 2:42 AM

Yeah, this is a very aarch64 specific thing in the generic symbolizer, but it's not an especially large function so I didn't feel too bad about it. If we started needing to handle multi-instruction sequences like this in the symbolizer (where we save state from previous instructions to determine a result), then this definitely would not scale well.

Yeah I mainly mentioned it because of vague memories of some other function that grew a whole bunch of these. Fine for now.

(And in general I like the change, we get this sort of request for the disassembly tools a lot but haven't really thought about it for lldb)

I've written it so that I only recognize the pattern with ADRP is immediately followed by an ADD, that was maybe a choice I could have gone either way on.

That bit makes sense to me. I suppose instruction scheduling might separate them but this probably hits 99% of them.

jasonmolenda updated this revision to Diff 364361.Aug 4 2021, 11:36 PM
jasonmolenda added a reviewer: DavidSpickett.

Update patch to address David's suggestion that the bit masking & testing needed some comments to make it possible to follow. In the process of doing that, I noticed that MachODump.cpp's SymbolizerSymbolLookUp, where I cribbed the bit stuff from, doesn't handle an ADRP referring to a 4k block before $pc; it doesn't sign extend the page imm value correctly from the ADRP. I updated the test case to have a symbol 4k earlier than $pc so lldb has to compute this correctly to symbolicate the address, and added both an arm64 and arm64_32 yaml encoded copy of the binary.

jasonmolenda updated this revision to Diff 364363.Aug 4 2021, 11:42 PM

Ah, add one more comment that David suggested.

jasonmolenda added inline comments.Aug 4 2021, 11:48 PM
lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
1328

There's a comment right before the conditional expr which says what it's checking. The check that m_adrp_insn is actually an adrp instruction is unnecessary; I cribbed that from the MachODump file, but the only way I set the ivar to the instruction is if we had type_ptr==LLVMDisassembler_ReferenceType_In_ARM64_ADRP in the previous instruction.

1332–1335

Yeah, it was being done incorrectly.

1339

Yeah, I rewrote it the way you suggest. I don't know why it was written that way in MachODump.cpp (incorrectly), but also why would the sh bit be set on the ADD when that just shifts the value up 12 bits like the ADRP instruction did already. It's like a less rangey version of ADRP as soon as the sh bit is set.

Harbormaster completed remote builds in B118088: Diff 364363.Aug 5 2021, 12:13 AM
DavidSpickett added inline comments.Aug 6 2021, 5:46 AM
lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
1328

The check that m_adrp_insn is actually an adrp instruction is unnecessary

In that we could have an Optional<uint32_t> and assume if set, it's an adrp. But this is functionally the same.

Comment bikeshedding, put the conditions in the same order as the text? So readers know that 0x1f is the register?
(though if you were questioning this code the first port of call would be the arm manuals but regardless)

// If previous instruction was ADRP and this is ADD, and it's to
// the same register, this is pc-relative address calculation.
if (m_adrp_address == pc - 4 &&
    (m_adrp_insn & 0x9f000000) == 0x90000000 && 
    *type_ptr == LLVMDisassembler_ReferenceType_In_ARM64_ADDXri &&
    (m_adrp_insn & 0x1f) == ((value >> 5) & 0x1f)) {
lldb/test/API/functionalities/disassemble/aarch64-adrp-add/TestAArch64AdrpAdd.py
16–28

Could move most of this into a utility fn too.

30

no_debug_info_test here?

61

Shouldn't this be within the if Trace?

lldb/test/API/functionalities/disassemble/aarch64-adrp-add/main.c
261

I admit a bit of a "wat" moment here, but I assume this is setting things up so that foo is some distance behind (at a lower address) than main?
So we have foo, which is before main and HI which is after for a negative, positive offset.

Could do with a comment for how many instructions this is. Maybe you could #define something for maybe 64 nops at a time just to make it a little less verbose.

Matt added a subscriber: Matt.Aug 10 2021, 1:26 PM
jasonmolenda updated this revision to Diff 365925.Aug 12 2021, 12:44 AM

Address David's second review comments -- explained the unusual formatting of the main.c in the test case, change the m_adrp_insn to be an Optional instead of using 0 as a "not-set" value. I'll prob land this tomorrow unless someone has additional feedback, I think it's in reasonable shape.

Harbormaster completed remote builds in B119204: Diff 365925.Aug 12 2021, 1:07 AM
DavidSpickett accepted this revision.Aug 12 2021, 1:13 AM

LGTM

This revision is now accepted and ready to land.Aug 12 2021, 1:13 AM
This revision was landed with ongoing or failed builds.Aug 12 2021, 2:44 PM
Closed by commit rG7150b562081f: Symbolicate aarch64 adrp+add pc-relative addr in disass (authored by jasonmolenda). · Explain Why
This revision was automatically updated to reflect the committed changes.
jasonmolenda added a commit: rG7150b562081f: Symbolicate aarch64 adrp+add pc-relative addr in disass.

Revision Contents

PathSize
lldb/
source/
Plugins/
Disassembler/
LLVMC/
2 lines
49 lines
test/
API/
functionalities/
disassemble/
aarch64-adrp-add/
67 lines
397 lines
379 lines
267 lines

Diff 364361

lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.h

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines static const char *SymbolLookupCallback(void *DisInfo,
uint64_t *ReferenceType, uint64_t *ReferenceType,
uint64_t ReferencePC, uint64_t ReferencePC,
const char **ReferenceName); const char **ReferenceName);
const lldb_private::ExecutionContext *m_exe_ctx; const lldb_private::ExecutionContext *m_exe_ctx;
InstructionLLVMC *m_inst; InstructionLLVMC *m_inst;
std::mutex m_mutex; std::mutex m_mutex;
bool m_data_from_file; bool m_data_from_file;
lldb::addr_t m_adrp_address;
uint32_t m_adrp_insn;
DavidSpickettUnsubmitted
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Just to check I understand, these are member vars because SymbolLookup will first be called on the adrp. So you write these values, then it's called again for the add, which is where you use them?

If so I would add a comment along those lines.

DavidSpickett: Just to check I understand, these are member vars because SymbolLookup will first be called on…
// Since we need to make two actual MC Disassemblers for ARM (ARM & THUMB), // Since we need to make two actual MC Disassemblers for ARM (ARM & THUMB),
// and there's a bit of goo to set up and own in the MC disassembler world, // and there's a bit of goo to set up and own in the MC disassembler world,
// this class was added to manage the actual disassemblers. // this class was added to manage the actual disassemblers.
class MCDisasmInstance; class MCDisasmInstance;
std::unique_ptr<MCDisasmInstance> m_disasm_up; std::unique_ptr<MCDisasmInstance> m_disasm_up;
std::unique_ptr<MCDisasmInstance> m_alternate_disasm_up; std::unique_ptr<MCDisasmInstance> m_alternate_disasm_up;
}; };
#endif // LLDB_SOURCE_PLUGINS_DISASSEMBLER_LLVMC_DISASSEMBLERLLVMC_H #endif // LLDB_SOURCE_PLUGINS_DISASSEMBLER_LLVMC_DISASSEMBLERLLVMC_H

lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp

Show First 20 Lines • Show All 192 Lines • ▼ Show 20 Lines
bool DisassemblerLLVMC::MCDisasmInstance::IsCall(llvm::MCInst &mc_inst) const { bool DisassemblerLLVMC::MCDisasmInstance::IsCall(llvm::MCInst &mc_inst) const {
return m_instr_info_up->get(mc_inst.getOpcode()).isCall(); return m_instr_info_up->get(mc_inst.getOpcode()).isCall();
} }
DisassemblerLLVMC::DisassemblerLLVMC(const ArchSpec &arch, DisassemblerLLVMC::DisassemblerLLVMC(const ArchSpec &arch,
const char *flavor_string) const char *flavor_string)
: Disassembler(arch, flavor_string), m_exe_ctx(nullptr), m_inst(nullptr), : Disassembler(arch, flavor_string), m_exe_ctx(nullptr), m_inst(nullptr),
m_data_from_file(false) { m_data_from_file(false), m_adrp_address(LLDB_INVALID_ADDRESS),
m_adrp_insn(0) {
if (!FlavorValidForArchSpec(arch, m_flavor.c_str())) { if (!FlavorValidForArchSpec(arch, m_flavor.c_str())) {
m_flavor.assign("default"); m_flavor.assign("default");
} }
unsigned flavor = ~0U; unsigned flavor = ~0U;
llvm::Triple triple = arch.GetTriple(); llvm::Triple triple = arch.GetTriple();
// So far the only supported flavor is "intel" on x86. The base class will // So far the only supported flavor is "intel" on x86. The base class will
▲ Show 20 Lines • Show All 263 Lines • ▼ Show 20 Lines
const char *DisassemblerLLVMC::SymbolLookup(uint64_t value, uint64_t *type_ptr, const char *DisassemblerLLVMC::SymbolLookup(uint64_t value, uint64_t *type_ptr,
uint64_t pc, const char **name) { uint64_t pc, const char **name) {
if (*type_ptr) { if (*type_ptr) {
if (m_exe_ctx && m_inst) { if (m_exe_ctx && m_inst) {
// std::string remove_this_prior_to_checkin; // std::string remove_this_prior_to_checkin;
Target *target = m_exe_ctx ? m_exe_ctx->GetTargetPtr() : nullptr; Target *target = m_exe_ctx ? m_exe_ctx->GetTargetPtr() : nullptr;
Address value_so_addr; Address value_so_addr;
Address pc_so_addr; Address pc_so_addr;
if (target->GetArchitecture().GetMachine() == llvm::Triple::aarch64 ||
target->GetArchitecture().GetMachine() == llvm::Triple::aarch64_be ||
DavidSpickettUnsubmitted
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Add aarch64_be here.

Triple does have a isAArch64 which does this but I think you just get the ArchType enum here so you can't use it which is a shame.

DavidSpickett: Add `aarch64_be` here. Triple does have a `isAArch64` which does this but I think you just get…
target->GetArchitecture().GetMachine() == llvm::Triple::aarch64_32) {
if (*type_ptr == LLVMDisassembler_ReferenceType_In_ARM64_ADRP) {
m_adrp_address = pc;
m_adrp_insn = value;
*name = nullptr;
*type_ptr = LLVMDisassembler_ReferenceType_InOut_None;
return nullptr;
}
// If previous instruction was ADRP and this is ADD, and it's to
// the same register, this is pc-relative address calculation.
DavidSpickettUnsubmitted
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There is a 32 bit variant of ADD with W registers, I assume LLVMDisassembler_ReferenceType_In_ARM64_ADDXri is specific to the X version though, correct?

Which saves you checking the "sf" field later. (plus I don't know that any compiler would bother using the W version for this sort of thing anyway)

DavidSpickett: There is a 32 bit variant of ADD with W registers, I assume…
jasonmolendaAuthorUnsubmitted
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Ah, good point. I did a quick check and clang currently generates the same adrp+add with an x register, and then ANDs the result with 0xffffffff for our "arm64_32" target (ILP32 codegen that executes in the lower 4GB of virtual address space but uses the aarch64 ISA), so it works out.

jasonmolenda: Ah, good point. I did a quick check and clang currently generates the same adrp+add with an x…
if (*type_ptr == LLVMDisassembler_ReferenceType_In_ARM64_ADDXri &&
m_adrp_address == pc - 4 &&
(m_adrp_insn & 0x9f000000) == 0x90000000 &&
DavidSpickettUnsubmitted
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Add comments to these two lines saying what they're checking for.

(looks correct from what the ARMARM says)

DavidSpickett: Add comments to these two lines saying what they're checking for. (looks correct from what the…
jasonmolendaAuthorUnsubmitted
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There's a comment right before the conditional expr which says what it's checking. The check that m_adrp_insn is actually an adrp instruction is unnecessary; I cribbed that from the MachODump file, but the only way I set the ivar to the instruction is if we had type_ptr==LLVMDisassembler_ReferenceType_In_ARM64_ADRP in the previous instruction.

jasonmolenda: There's a comment right before the conditional expr which says what it's checking. The check…
DavidSpickettUnsubmitted
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The check that m_adrp_insn is actually an adrp instruction is unnecessary

In that we could have an Optional<uint32_t> and assume if set, it's an adrp. But this is functionally the same.

Comment bikeshedding, put the conditions in the same order as the text? So readers know that 0x1f is the register?
(though if you were questioning this code the first port of call would be the arm manuals but regardless)

// If previous instruction was ADRP and this is ADD, and it's to
// the same register, this is pc-relative address calculation.
if (m_adrp_address == pc - 4 &&
    (m_adrp_insn & 0x9f000000) == 0x90000000 && 
    *type_ptr == LLVMDisassembler_ReferenceType_In_ARM64_ADDXri &&
    (m_adrp_insn & 0x1f) == ((value >> 5) & 0x1f)) {
DavidSpickett: > The check that m_adrp_insn is actually an adrp instruction is unnecessary In that we could…
(m_adrp_insn & 0x1f) == ((value >> 5) & 0x1f)) {
// Bitmasking lifted from MachODump.cpp's SymbolizerSymbolLookUp.
uint32_t addxri_inst;
uint64_t adrp_imm, addxri_imm;
// Get immlo and immhi bits, OR them together to get the ADRP imm
// value.
adrp_imm =
DavidSpickettUnsubmitted
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Comments here too. The second one is sign extension, correct?

DavidSpickett: Comments here too. The second one is sign extension, correct?
jasonmolendaAuthorUnsubmitted
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Yeah, it was being done incorrectly.

jasonmolenda: Yeah, it was being done incorrectly.
((m_adrp_insn & 0x00ffffe0) >> 3) | ((m_adrp_insn >> 29) & 0x3);
// if high bit of immhi after right-shifting set, sign extend
if (adrp_imm & (1ULL << 20))
adrp_imm |= ~((1ULL << 21) - 1);
DavidSpickettUnsubmitted
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"sh" is a single bit field so you could just:

if ((addrxi_inst >> 22) & 1)
DavidSpickett: "sh" is a single bit field so you could just: ``` if ((addrxi_inst >> 22) & 1) ```
jasonmolendaAuthorUnsubmitted
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Yeah, I rewrote it the way you suggest. I don't know why it was written that way in MachODump.cpp (incorrectly), but also why would the sh bit be set on the ADD when that just shifts the value up 12 bits like the ADRP instruction did already. It's like a less rangey version of ADRP as soon as the sh bit is set.

jasonmolenda: Yeah, I rewrote it the way you suggest. I don't know why it was written that way in MachODump.
addxri_inst = value;
addxri_imm = (addxri_inst >> 10) & 0xfff;
DavidSpickettUnsubmitted
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ditto on the comments, but the math seems fine.

DavidSpickett: ditto on the comments, but the math seems fine.
// check if 'sh' bit is set, shift imm value up if so
// (this would make no sense, ADRP already gave us this part)
if ((addxri_inst >> (12 + 5 + 5)) & 1)
addxri_imm <<= 12;
value = (m_adrp_address & 0xfffffffffffff000LL) + (adrp_imm << 12) +
DavidSpickettUnsubmitted
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This method is pretty long as it is, does it make sense to make the aarch64 specific part of it another private method?

DavidSpickett: This method is pretty long as it is, does it make sense to make the aarch64 specific part of it…
addxri_imm;
}
m_adrp_address = LLDB_INVALID_ADDRESS;
m_adrp_insn = 0;
}
if (m_inst->UsingFileAddress()) { if (m_inst->UsingFileAddress()) {
ModuleSP module_sp(m_inst->GetAddress().GetModule()); ModuleSP module_sp(m_inst->GetAddress().GetModule());
if (module_sp) { if (module_sp) {
module_sp->ResolveFileAddress(value, value_so_addr); module_sp->ResolveFileAddress(value, value_so_addr);
module_sp->ResolveFileAddress(pc, pc_so_addr); module_sp->ResolveFileAddress(pc, pc_so_addr);
} }
} else if (target && !target->GetSectionLoadList().IsEmpty()) { } else if (target && !target->GetSectionLoadList().IsEmpty()) {
target->GetSectionLoadList().ResolveLoadAddress(value, value_so_addr); target->GetSectionLoadList().ResolveLoadAddress(value, value_so_addr);
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
str.erase(first_eol_char); str.erase(first_eol_char);
} }
m_inst->AppendComment(str); m_inst->AppendComment(str);
} }
} }
} }
} }
// TODO: llvm-objdump sets the type_ptr to the
// LLVMDisassembler_ReferenceType_Out_* values
// based on where value_so_addr is pointing, with
// Mach-O specific augmentations in MachODump.cpp. e.g.
// see what AArch64ExternalSymbolizer::tryAddingSymbolicOperand
// handles.
*type_ptr = LLVMDisassembler_ReferenceType_InOut_None; *type_ptr = LLVMDisassembler_ReferenceType_InOut_None;
*name = nullptr; *name = nullptr;
return nullptr; return nullptr;
} }
// PluginInterface protocol // PluginInterface protocol
ConstString DisassemblerLLVMC::GetPluginName() { return GetPluginNameStatic(); } ConstString DisassemblerLLVMC::GetPluginName() { return GetPluginNameStatic(); }
uint32_t DisassemblerLLVMC::GetPluginVersion() { return 1; } uint32_t DisassemblerLLVMC::GetPluginVersion() { return 1; }
Context not available.

lldb/test/API/functionalities/disassemble/aarch64-adrp-add/TestAArch64AdrpAdd.py

  • This file was added.
"""
Test that the arm64 ADRP + ADD pc-relative addressing pair is symbolicated.
"""
from lldbsuite.test.decorators import *
from lldbsuite.test.lldbtest import *
from lldbsuite.test import lldbutil
class TestAArch64AdrpAdd(TestBase):
mydir = TestBase.compute_mydir(__file__)
@no_debug_info_test
def test_arm64(self):
src_dir = self.getSourceDir()
yaml_path = os.path.join(src_dir, "a.out-arm64.yaml")
obj_path = self.getBuildArtifact("a.out-arm64")
self.yaml2obj(yaml_path, obj_path)
target = self.dbg.CreateTarget(obj_path)
self.assertTrue(target, VALID_TARGET)
mains = target.FindFunctions("main")
for f in mains.symbols:
binaryname = f.GetStartAddress().GetModule().GetFileSpec().GetFilename()
if binaryname == "a.out-arm64":
self.disassemble_check_for_hi_and_foo(target, f, binaryname)
DavidSpickettUnsubmitted
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Could move most of this into a utility fn too.

DavidSpickett: Could move most of this into a utility fn too.
def test_arm64_32(self):
src_dir = self.getSourceDir()
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no_debug_info_test here?

DavidSpickett: `no_debug_info_test` here?
yaml_path = os.path.join(src_dir, "a.out-arm64_32.yaml")
obj_path = self.getBuildArtifact("a.out-arm64_32")
self.yaml2obj(yaml_path, obj_path)
target = self.dbg.CreateTarget(obj_path)
self.assertTrue(target, VALID_TARGET)
DavidSpickettUnsubmitted
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You could break after finding it.

DavidSpickett: You could `break` after finding it.
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if not found_hi_string and...

DavidSpickett: `if not found_hi_string and...`
mains = target.FindFunctions("main")
for f in mains.symbols:
binaryname = f.GetStartAddress().GetModule().GetFileSpec().GetFilename()
if binaryname == "a.out-arm64_32":
self.disassemble_check_for_hi_and_foo(target, f, binaryname)
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A message would help here, like "Did not find \"HI\" string in disassembly.".

Of course if you want to debug it the logging is actually going to help but just for anyone seeing it as a random failure in a general test suite run.

DavidSpickett: A message would help here, like `"Did not find \"HI\" string in disassembly."`. Of course if…
def disassemble_check_for_hi_and_foo(self, target, func, binaryname):
insns = func.GetInstructions(target)
found_hi_string = False
found_foo = False
# The binary has an ADRP + ADD instruction pair which load
# the pc-relative address of a c-string, and loads the address
# of a function into a function pointer. lldb should show
# that c-string and the name of that function in the disassembly
# comment field.
for i in insns:
if "HI" in i.GetComment(target):
found_hi_string = True
if "foo" in i.GetComment(target):
found_foo = True
if found_hi_string == False or found_foo == False:
print('Did not find "HI" string or "foo" in disassembly symbolication in %s' % binaryname)
if self.TraceOn():
DavidSpickettUnsubmitted
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Shouldn't this be within the if Trace?

DavidSpickett: Shouldn't this be within the if Trace?
strm = lldb.SBStream()
insns.GetDescription(strm)
print('Disassembly of main(), looking for "HI" and "foo" in comments:')
print(strm.GetData())
self.assertTrue(found_hi_string)
self.assertTrue(found_foo)

lldb/test/API/functionalities/disassemble/aarch64-adrp-add/a.out-arm64.yaml

  • This file was added.
--- !mach-o
FileHeader:
magic: 0xFEEDFACF
cputype: 0x100000C
cpusubtype: 0x0
filetype: 0x2
ncmds: 17
sizeofcmds: 1384
flags: 0x200085
reserved: 0x0
LoadCommands:
- cmd: LC_SEGMENT_64
cmdsize: 72
segname: __PAGEZERO
vmaddr: 0
vmsize: 4294967296
fileoff: 0
filesize: 0
maxprot: 0
initprot: 0
nsects: 0
flags: 0
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ImportName: ''
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Other: 0x0
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n_desc: 16
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...

lldb/test/API/functionalities/disassemble/aarch64-adrp-add/a.out-arm64_32.yaml

  • This file was added.
--- !mach-o
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reserved3: 0x0
content: FF8300D1FD7B01A9FD430091080000B008B13E910900009029713D91BFC31FB8E90B00B9007D409210040094EA0B40B9E8030AAAE00700B900013FD6FD7B41A9FF830091C0035FD6FD7BBFA9FD0300910400009400140011FD7BC1A8C0035FD61F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D51F2003D5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- sectname: __stubs
segname: __TEXT
addr: 0xBF7C
size: 12
offset: 0x7F7C
align: 2
reloff: 0x0
nreloc: 0
flags: 0x80000408
reserved1: 0x0
reserved2: 0xC
reserved3: 0x0
content: 1F2003D51004021800021FD6
- sectname: __stub_helper
segname: __TEXT
addr: 0xBF88
size: 36
offset: 0x7F88
align: 2
reloff: 0x0
nreloc: 0
flags: 0x80000400
reserved1: 0x0
reserved2: 0x0
reserved3: 0x0
content: F10302101F2003D5F047BFA91F2003D55003001800021FD650000018F9FFFF1700000000
- sectname: __cstring
segname: __TEXT
addr: 0xBFAC
size: 3
offset: 0x7FAC
align: 0
reloff: 0x0
nreloc: 0
flags: 0x2
reserved1: 0x0
reserved2: 0x0
reserved3: 0x0
content: '484900'
- sectname: __unwind_info
segname: __TEXT
addr: 0xBFB0
size: 80
offset: 0x7FB0
align: 2
reloff: 0x0
nreloc: 0
flags: 0x0
reserved1: 0x0
reserved2: 0x0
reserved3: 0x0
content: 010000001C000000000000001C000000000000001C00000002000000146F000034000000340000007D7F00000000000034000000030000000C0002001400020000000001600000000000000200000004
- cmd: LC_SEGMENT
cmdsize: 124
segname: __DATA_CONST
vmaddr: 49152
vmsize: 16384
fileoff: 32768
filesize: 16384
maxprot: 3
initprot: 3
nsects: 1
flags: 16
Sections:
- sectname: __got
segname: __DATA_CONST
addr: 0xC000
size: 4
offset: 0x8000
align: 2
reloff: 0x0
nreloc: 0
flags: 0x6
reserved1: 0x1
reserved2: 0x0
reserved3: 0x0
content: '00000000'
- cmd: LC_SEGMENT
cmdsize: 192
segname: __DATA
vmaddr: 65536
vmsize: 16384
fileoff: 49152
filesize: 16384
maxprot: 3
initprot: 3
nsects: 2
flags: 0
Sections:
- sectname: __la_symbol_ptr
segname: __DATA
addr: 0x10000
size: 4
offset: 0xC000
align: 2
reloff: 0x0
nreloc: 0
flags: 0x7
reserved1: 0x2
reserved2: 0x0
reserved3: 0x0
content: A0BF0000
- sectname: __data
segname: __DATA
addr: 0x10004
size: 4
offset: 0xC004
align: 2
reloff: 0x0
nreloc: 0
flags: 0x0
reserved1: 0x0
reserved2: 0x0
reserved3: 0x0
content: '00000000'
- cmd: LC_SEGMENT
cmdsize: 56
segname: __LINKEDIT
vmaddr: 81920
vmsize: 16384
fileoff: 65536
filesize: 264
maxprot: 1
initprot: 1
nsects: 0
flags: 0
- cmd: LC_DYLD_INFO_ONLY
cmdsize: 48
rebase_off: 65536
rebase_size: 4
bind_off: 65540
bind_size: 24
weak_bind_off: 0
weak_bind_size: 0
lazy_bind_off: 65564
lazy_bind_size: 12
export_off: 65576
export_size: 44
- cmd: LC_SYMTAB
cmdsize: 24
symoff: 65628
nsyms: 7
stroff: 65724
strsize: 76
- cmd: LC_DYSYMTAB
cmdsize: 80
ilocalsym: 0
nlocalsym: 3
iextdefsym: 3
nextdefsym: 2
iundefsym: 5
nundefsym: 2
tocoff: 0
ntoc: 0
modtaboff: 0
nmodtab: 0
extrefsymoff: 0
nextrefsyms: 0
indirectsymoff: 65712
nindirectsyms: 3
extreloff: 0
nextrel: 0
locreloff: 0
nlocrel: 0
- cmd: LC_LOAD_DYLINKER
cmdsize: 28
name: 12
Content: '/usr/lib/dyld'
ZeroPadBytes: 3
- cmd: LC_UUID
cmdsize: 24
uuid: 4050A0D9-F607-3ED9-B154-8C9BDDA61736
- cmd: LC_BUILD_VERSION
cmdsize: 32
platform: 4
minos: 459776
sdk: 459776
ntools: 1
Tools:
- tool: 3
version: 42599936
- cmd: LC_SOURCE_VERSION
cmdsize: 16
version: 0
- cmd: LC_MAIN
cmdsize: 24
entryoff: 28436
stacksize: 0
- cmd: LC_ENCRYPTION_INFO
cmdsize: 20
cryptoff: 16384
cryptsize: 16384
cryptid: 0
- cmd: LC_LOAD_DYLIB
cmdsize: 52
dylib:
name: 24
timestamp: 2
current_version: 84698117
compatibility_version: 65536
Content: '/usr/lib/libSystem.B.dylib'
ZeroPadBytes: 2
- cmd: LC_FUNCTION_STARTS
cmdsize: 16
dataoff: 65620
datasize: 8
- cmd: LC_DATA_IN_CODE
cmdsize: 16
dataoff: 65628
datasize: 0
LinkEditData:
RebaseOpcodes:
- Opcode: REBASE_OPCODE_SET_TYPE_IMM
Imm: 1
- Opcode: REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
Imm: 3
ExtraData: [ 0x0 ]
- Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES
Imm: 1
BindOpcodes:
- Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
Imm: 1
Symbol: ''
- Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
Imm: 0
Symbol: dyld_stub_binder
- Opcode: BIND_OPCODE_SET_TYPE_IMM
Imm: 1
Symbol: ''
- Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
Imm: 2
ULEBExtraData: [ 0x0 ]
Symbol: ''
- Opcode: BIND_OPCODE_DO_BIND
Imm: 0
Symbol: ''
- Opcode: BIND_OPCODE_DONE
Imm: 0
Symbol: ''
LazyBindOpcodes:
- Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
Imm: 3
ULEBExtraData: [ 0x0 ]
Symbol: ''
- Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
Imm: 1
Symbol: ''
- Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
Imm: 0
Symbol: _puts
- Opcode: BIND_OPCODE_DO_BIND
Imm: 0
Symbol: ''
- Opcode: BIND_OPCODE_DONE
Imm: 0
Symbol: ''
ExportTrie:
TerminalSize: 0
NodeOffset: 0
Name: ''
Flags: 0x0
Address: 0x0
Other: 0x0
ImportName: ''
Children:
- TerminalSize: 0
NodeOffset: 5
Name: _
Flags: 0x0
Address: 0x0
Other: 0x0
ImportName: ''
Children:
- TerminalSize: 2
NodeOffset: 33
Name: _mh_execute_header
Flags: 0x0
Address: 0x0
Other: 0x0
ImportName: ''
- TerminalSize: 4
NodeOffset: 37
Name: main
Flags: 0x0
Address: 0x6F14
Other: 0x0
ImportName: ''
NameList:
- n_strx: 51
n_type: 0xE
n_sect: 1
n_desc: 0
n_value: 44892
- n_strx: 56
n_type: 0xE
n_sect: 1
n_desc: 0
n_value: 44916
- n_strx: 61
n_type: 0xE
n_sect: 8
n_desc: 0
n_value: 65540
- n_strx: 2
n_type: 0xF
n_sect: 1
n_desc: 16
n_value: 16384
- n_strx: 22
n_type: 0xF
n_sect: 1
n_desc: 0
n_value: 44820
- n_strx: 28
n_type: 0x1
n_sect: 0
n_desc: 256
n_value: 0
- n_strx: 34
n_type: 0x1
n_sect: 0
n_desc: 256
n_value: 0
StringTable:
- ' '
- __mh_execute_header
- _main
- _puts
- dyld_stub_binder
- _foo
- _bar
- __dyld_private
...

lldb/test/API/functionalities/disassemble/aarch64-adrp-add/main.c

  • This file was added.
#include <stdio.h>
static int bar();
static int foo () { return 5 + bar(); }
static int bar() {
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
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asm("nop");asm("nop");asm("nop");asm("nop");
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asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
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asm("nop");asm("nop");asm("nop");asm("nop");
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asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
asm("nop");asm("nop");asm("nop");asm("nop");
return 5;
DavidSpickettUnsubmitted
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ReplyInline Actions

I admit a bit of a "wat" moment here, but I assume this is setting things up so that foo is some distance behind (at a lower address) than main?
So we have foo, which is before main and HI which is after for a negative, positive offset.

Could do with a comment for how many instructions this is. Maybe you could #define something for maybe 64 nops at a time just to make it a little less verbose.

DavidSpickett: I admit a bit of a "wat" moment here, but I assume this is setting things up so that foo is…
}
int main () {
int (*f)(void) = foo;
puts("HI");
return f();
}