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Differential D107196

[AArch64InstPrinter] Change printAddSubImm to only add imm value comment when shifted
ClosedPublic

Authored by jasonmolenda on Jul 30 2021, 2:48 PM.

Details

Reviewers
t.p.northover
jhenderson
MaskRay
Commits
rG0d8cd4e2d5d4: [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
Summary

AArch64InstPrinter::printAddSubImm adds an immediate value to the comment stream when both are available. This is helpful when the imm value is shifted, e.g.

add x9, x0, #291, lsl #12 ; =1191936

but most of the time it looks like

subs x9, x0, #256 ; =256

where the comment adds nothing useful.

This patch changes printAddSubImm so it only appends the immediate value to the comment stream when it has a shift. The majority of the patchset is updating the tests to match the new output style.

Diff Detail

Event Timeline

jasonmolenda created this revision.Jul 30 2021, 2:48 PM
Herald added a reviewer: jhenderson. · View Herald TranscriptJul 30 2021, 2:48 PM
Herald added a reviewer: MaskRay. · View Herald Transcript
Herald added subscribers: danielkiss, asbirlea, rupprecht and 5 others. · View Herald Transcript
jasonmolenda requested review of this revision.Jul 30 2021, 2:48 PM
Harbormaster completed remote builds in B117261: Diff 363206.Jul 30 2021, 3:25 PM
MaskRay accepted this revision.Jul 30 2021, 3:38 PM

Thanks for the patch! I have wanted this for some time.

This revision is now accepted and ready to land.Jul 30 2021, 3:38 PM
MaskRay added a comment.EditedJul 30 2021, 3:38 PM

Consider committing the test update separately from the code patch, so that the functional change has very few lines of update.

jasonmolenda mentioned this in D107213: Disassemble AArch64 pc-relative address calculations & symbolicate.Jul 31 2021, 12:53 AM
jasonmolenda added a comment.Jul 31 2021, 12:58 PM

An interesting side question as long as we're talking about this printer,

add x9, x0, #291, lsl #12 ; =1191936

once we have a shifted imm value, adding the value in base10 to the comment stream is maybe not the best choice. This could be printed as,

add x9, x0, #291, lsl #12 ; =0x123000

Anyone have an opinion one way or the other?

MaskRay added a comment.Jul 31 2021, 2:11 PM

Currently --print-imm-hex can change ; =1191936 to the hexadecimal form.

I do feel unconditionally hex comments are better and think an option for decimal comment may unlikely be needed.

So LGTM as a follow-up.

llvm/test/tools/llvm-objdump/ELF/AArch64/disassemble-align.s
6

Perhaps append {{$}} to ensure there is no comment.

t.p.northover added a comment.Aug 3 2021, 1:21 AM
In D107196#2917773, @MaskRay wrote:

Consider committing the test update separately from the code patch, so that the functional change has very few lines of update.

Wouldn't that mean a revision with lots of tests failing? I think a single large commit would be better. People can grep out changes in llvm/test if they're not interested in that.

jasonmolenda added a comment.Aug 3 2021, 1:24 AM
In D107196#2921590, @t.p.northover wrote:
In D107196#2917773, @MaskRay wrote:

Consider committing the test update separately from the code patch, so that the functional change has very few lines of update.

Wouldn't that mean a revision with lots of tests failing? I think a single large commit would be better. People can grep out changes in llvm/test if they're not interested in that.

I figured I would do commits locally and push them at the same time. I'm doing a final testsuite run right now and was hoping to land it if you think this might be a poor idea.

jhenderson added a comment.Aug 3 2021, 1:39 AM
In D107196#2921591, @jasonmolenda wrote:
In D107196#2921590, @t.p.northover wrote:
In D107196#2917773, @MaskRay wrote:

Consider committing the test update separately from the code patch, so that the functional change has very few lines of update.

Wouldn't that mean a revision with lots of tests failing? I think a single large commit would be better. People can grep out changes in llvm/test if they're not interested in that.

I figured I would do commits locally and push them at the same time. I'm doing a final testsuite run right now and was hoping to land it if you think this might be a poor idea.

I wouldn't land them as two separate commits - even though the build bots might be fine, it'll mean that for at least one commit, LLVM as a whole is in a broken state, which can cause various issues e.g. when bisecting, or if a system does a commit-by-commit build and test cycle.

llvm/test/tools/llvm-objdump/ELF/AArch64/disassemble-align.s
6

+1

jasonmolenda added a comment.Aug 3 2021, 1:41 AM
In D107196#2921607, @jhenderson wrote:
In D107196#2921591, @jasonmolenda wrote:
In D107196#2921590, @t.p.northover wrote:
In D107196#2917773, @MaskRay wrote:

Consider committing the test update separately from the code patch, so that the functional change has very few lines of update.

Wouldn't that mean a revision with lots of tests failing? I think a single large commit would be better. People can grep out changes in llvm/test if they're not interested in that.

I figured I would do commits locally and push them at the same time. I'm doing a final testsuite run right now and was hoping to land it if you think this might be a poor idea.

I wouldn't land them as two separate commits - even though the build bots might be fine, it'll mean that for at least one commit, LLVM as a whole is in a broken state, which can cause various issues e.g. when bisecting, or if a system does a commit-by-commit build and test cycle.

Ah of course, good point.

I added the {{$}} in my WIP patch.

Closed by commit rG0d8cd4e2d5d4: [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted (authored by jasonmolenda). · Explain WhyAug 3 2021, 2:29 AM
This revision was automatically updated to reflect the committed changes.
jasonmolenda added a commit: rG0d8cd4e2d5d4: [AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted.
MaskRay added a comment.Aug 3 2021, 8:42 PM
In D107196#2921590, @t.p.northover wrote:
In D107196#2917773, @MaskRay wrote:

Consider committing the test update separately from the code patch, so that the functional change has very few lines of update.

Wouldn't that mean a revision with lots of tests failing? I think a single large commit would be better. People can grep out changes in llvm/test if they're not interested in that.

I am referring to // =16 removal. Deleting the part will not make the test fail.

Revision Contents

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Diff 363661

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

Show First 20 Lines • Show All 1,020 Lines • ▼ Show 20 Linesvoid AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
raw_ostream &O) { raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNum); const MCOperand &MO = MI->getOperand(OpNum);
if (MO.isImm()) { if (MO.isImm()) {
unsigned Val = (MO.getImm() & 0xfff); unsigned Val = (MO.getImm() & 0xfff);
assert(Val == MO.getImm() && "Add/sub immediate out of range!"); assert(Val == MO.getImm() && "Add/sub immediate out of range!");
unsigned Shift = unsigned Shift =
AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm()); AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
O << '#' << formatImm(Val); O << '#' << formatImm(Val);
if (Shift != 0) if (Shift != 0) {
printShifter(MI, OpNum + 1, STI, O); printShifter(MI, OpNum + 1, STI, O);
if (CommentStream) if (CommentStream)
*CommentStream << '=' << formatImm(Val << Shift) << '\n'; *CommentStream << '=' << formatImm(Val << Shift) << '\n';
}
} else { } else {
assert(MO.isExpr() && "Unexpected operand type!"); assert(MO.isExpr() && "Unexpected operand type!");
MO.getExpr()->print(O, &MAI); MO.getExpr()->print(O, &MAI);
printShifter(MI, OpNum + 1, STI, O); printShifter(MI, OpNum + 1, STI, O);
} }
} }
template <typename T> template <typename T>
▲ Show 20 Lines • Show All 714 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; CHECK-LLSC-O0-NEXT: // implicit-def: $q0 ; CHECK-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-LLSC-O0-NEXT: mov v0.d[0], x9 ; CHECK-LLSC-O0-NEXT: mov v0.d[0], x9
; CHECK-LLSC-O0-NEXT: mov v0.d[1], x8 ; CHECK-LLSC-O0-NEXT: mov v0.d[1], x8
; CHECK-LLSC-O0-NEXT: str q0, [x0] ; CHECK-LLSC-O0-NEXT: str q0, [x0]
; CHECK-LLSC-O0-NEXT: ret ; CHECK-LLSC-O0-NEXT: ret
; ;
; CHECK-CAS-O0-LABEL: val_compare_and_swap: ; CHECK-CAS-O0-LABEL: val_compare_and_swap:
; CHECK-CAS-O0: // %bb.0: ; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16 // =16 ; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16 ; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill ; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
; CHECK-CAS-O0-NEXT: mov x1, x5 ; CHECK-CAS-O0-NEXT: mov x1, x5
; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload ; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3 ; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5 ; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5 ; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
; CHECK-CAS-O0-NEXT: mov x5, x1 ; CHECK-CAS-O0-NEXT: mov x5, x1
; CHECK-CAS-O0-NEXT: caspa x2, x3, x4, x5, [x0] ; CHECK-CAS-O0-NEXT: caspa x2, x3, x4, x5, [x0]
; CHECK-CAS-O0-NEXT: mov x9, x2 ; CHECK-CAS-O0-NEXT: mov x9, x2
; CHECK-CAS-O0-NEXT: mov x8, x3 ; CHECK-CAS-O0-NEXT: mov x8, x3
; CHECK-CAS-O0-NEXT: // implicit-def: $q0 ; CHECK-CAS-O0-NEXT: // implicit-def: $q0
; CHECK-CAS-O0-NEXT: mov v0.d[0], x9 ; CHECK-CAS-O0-NEXT: mov v0.d[0], x9
; CHECK-CAS-O0-NEXT: mov v0.d[1], x8 ; CHECK-CAS-O0-NEXT: mov v0.d[1], x8
; CHECK-CAS-O0-NEXT: str q0, [x0] ; CHECK-CAS-O0-NEXT: str q0, [x0]
; CHECK-CAS-O0-NEXT: add sp, sp, #16 // =16 ; CHECK-CAS-O0-NEXT: add sp, sp, #16
; CHECK-CAS-O0-NEXT: ret ; CHECK-CAS-O0-NEXT: ret
%pair = cmpxchg i128* %p, i128 %oldval, i128 %newval acquire acquire %pair = cmpxchg i128* %p, i128 %oldval, i128 %newval acquire acquire
%val = extractvalue { i128, i1 } %pair, 0 %val = extractvalue { i128, i1 } %pair, 0
store i128 %val, i128* %p store i128 %val, i128* %p
ret void ret void
} }
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; CHECK-LLSC-O0-NEXT: // implicit-def: $q0 ; CHECK-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-LLSC-O0-NEXT: mov v0.d[0], x9 ; CHECK-LLSC-O0-NEXT: mov v0.d[0], x9
; CHECK-LLSC-O0-NEXT: mov v0.d[1], x8 ; CHECK-LLSC-O0-NEXT: mov v0.d[1], x8
; CHECK-LLSC-O0-NEXT: str q0, [x0] ; CHECK-LLSC-O0-NEXT: str q0, [x0]
; CHECK-LLSC-O0-NEXT: ret ; CHECK-LLSC-O0-NEXT: ret
; ;
; CHECK-CAS-O0-LABEL: val_compare_and_swap_monotonic_seqcst: ; CHECK-CAS-O0-LABEL: val_compare_and_swap_monotonic_seqcst:
; CHECK-CAS-O0: // %bb.0: ; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16 // =16 ; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16 ; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill ; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
; CHECK-CAS-O0-NEXT: mov x1, x5 ; CHECK-CAS-O0-NEXT: mov x1, x5
; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload ; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3 ; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5 ; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5 ; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
; CHECK-CAS-O0-NEXT: mov x5, x1 ; CHECK-CAS-O0-NEXT: mov x5, x1
; CHECK-CAS-O0-NEXT: caspal x2, x3, x4, x5, [x0] ; CHECK-CAS-O0-NEXT: caspal x2, x3, x4, x5, [x0]
; CHECK-CAS-O0-NEXT: mov x9, x2 ; CHECK-CAS-O0-NEXT: mov x9, x2
; CHECK-CAS-O0-NEXT: mov x8, x3 ; CHECK-CAS-O0-NEXT: mov x8, x3
; CHECK-CAS-O0-NEXT: // implicit-def: $q0 ; CHECK-CAS-O0-NEXT: // implicit-def: $q0
; CHECK-CAS-O0-NEXT: mov v0.d[0], x9 ; CHECK-CAS-O0-NEXT: mov v0.d[0], x9
; CHECK-CAS-O0-NEXT: mov v0.d[1], x8 ; CHECK-CAS-O0-NEXT: mov v0.d[1], x8
; CHECK-CAS-O0-NEXT: str q0, [x0] ; CHECK-CAS-O0-NEXT: str q0, [x0]
; CHECK-CAS-O0-NEXT: add sp, sp, #16 // =16 ; CHECK-CAS-O0-NEXT: add sp, sp, #16
; CHECK-CAS-O0-NEXT: ret ; CHECK-CAS-O0-NEXT: ret
%pair = cmpxchg i128* %p, i128 %oldval, i128 %newval monotonic seq_cst %pair = cmpxchg i128* %p, i128 %oldval, i128 %newval monotonic seq_cst
%val = extractvalue { i128, i1 } %pair, 0 %val = extractvalue { i128, i1 } %pair, 0
store i128 %val, i128* %p store i128 %val, i128* %p
ret void ret void
} }
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; CHECK-LLSC-O0-NEXT: // implicit-def: $q0 ; CHECK-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-LLSC-O0-NEXT: mov v0.d[0], x9 ; CHECK-LLSC-O0-NEXT: mov v0.d[0], x9
; CHECK-LLSC-O0-NEXT: mov v0.d[1], x8 ; CHECK-LLSC-O0-NEXT: mov v0.d[1], x8
; CHECK-LLSC-O0-NEXT: str q0, [x0] ; CHECK-LLSC-O0-NEXT: str q0, [x0]
; CHECK-LLSC-O0-NEXT: ret ; CHECK-LLSC-O0-NEXT: ret
; ;
; CHECK-CAS-O0-LABEL: val_compare_and_swap_release_acquire: ; CHECK-CAS-O0-LABEL: val_compare_and_swap_release_acquire:
; CHECK-CAS-O0: // %bb.0: ; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16 // =16 ; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16 ; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill ; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
; CHECK-CAS-O0-NEXT: mov x1, x5 ; CHECK-CAS-O0-NEXT: mov x1, x5
; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload ; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3 ; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5 ; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5 ; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
; CHECK-CAS-O0-NEXT: mov x5, x1 ; CHECK-CAS-O0-NEXT: mov x5, x1
; CHECK-CAS-O0-NEXT: caspal x2, x3, x4, x5, [x0] ; CHECK-CAS-O0-NEXT: caspal x2, x3, x4, x5, [x0]
; CHECK-CAS-O0-NEXT: mov x9, x2 ; CHECK-CAS-O0-NEXT: mov x9, x2
; CHECK-CAS-O0-NEXT: mov x8, x3 ; CHECK-CAS-O0-NEXT: mov x8, x3
; CHECK-CAS-O0-NEXT: // implicit-def: $q0 ; CHECK-CAS-O0-NEXT: // implicit-def: $q0
; CHECK-CAS-O0-NEXT: mov v0.d[0], x9 ; CHECK-CAS-O0-NEXT: mov v0.d[0], x9
; CHECK-CAS-O0-NEXT: mov v0.d[1], x8 ; CHECK-CAS-O0-NEXT: mov v0.d[1], x8
; CHECK-CAS-O0-NEXT: str q0, [x0] ; CHECK-CAS-O0-NEXT: str q0, [x0]
; CHECK-CAS-O0-NEXT: add sp, sp, #16 // =16 ; CHECK-CAS-O0-NEXT: add sp, sp, #16
; CHECK-CAS-O0-NEXT: ret ; CHECK-CAS-O0-NEXT: ret
%pair = cmpxchg i128* %p, i128 %oldval, i128 %newval release acquire %pair = cmpxchg i128* %p, i128 %oldval, i128 %newval release acquire
%val = extractvalue { i128, i1 } %pair, 0 %val = extractvalue { i128, i1 } %pair, 0
store i128 %val, i128* %p store i128 %val, i128* %p
ret void ret void
} }
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; CHECK-LLSC-O0-NEXT: // implicit-def: $q0 ; CHECK-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-LLSC-O0-NEXT: mov v0.d[0], x9 ; CHECK-LLSC-O0-NEXT: mov v0.d[0], x9
; CHECK-LLSC-O0-NEXT: mov v0.d[1], x8 ; CHECK-LLSC-O0-NEXT: mov v0.d[1], x8
; CHECK-LLSC-O0-NEXT: str q0, [x0] ; CHECK-LLSC-O0-NEXT: str q0, [x0]
; CHECK-LLSC-O0-NEXT: ret ; CHECK-LLSC-O0-NEXT: ret
; ;
; CHECK-CAS-O0-LABEL: val_compare_and_swap_monotonic: ; CHECK-CAS-O0-LABEL: val_compare_and_swap_monotonic:
; CHECK-CAS-O0: // %bb.0: ; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16 // =16 ; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16 ; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill ; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
; CHECK-CAS-O0-NEXT: mov x1, x5 ; CHECK-CAS-O0-NEXT: mov x1, x5
; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload ; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3 ; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5 ; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5 ; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
; CHECK-CAS-O0-NEXT: mov x5, x1 ; CHECK-CAS-O0-NEXT: mov x5, x1
; CHECK-CAS-O0-NEXT: caspal x2, x3, x4, x5, [x0] ; CHECK-CAS-O0-NEXT: caspal x2, x3, x4, x5, [x0]
; CHECK-CAS-O0-NEXT: mov x9, x2 ; CHECK-CAS-O0-NEXT: mov x9, x2
; CHECK-CAS-O0-NEXT: mov x8, x3 ; CHECK-CAS-O0-NEXT: mov x8, x3
; CHECK-CAS-O0-NEXT: // implicit-def: $q0 ; CHECK-CAS-O0-NEXT: // implicit-def: $q0
; CHECK-CAS-O0-NEXT: mov v0.d[0], x9 ; CHECK-CAS-O0-NEXT: mov v0.d[0], x9
; CHECK-CAS-O0-NEXT: mov v0.d[1], x8 ; CHECK-CAS-O0-NEXT: mov v0.d[1], x8
; CHECK-CAS-O0-NEXT: str q0, [x0] ; CHECK-CAS-O0-NEXT: str q0, [x0]
; CHECK-CAS-O0-NEXT: add sp, sp, #16 // =16 ; CHECK-CAS-O0-NEXT: add sp, sp, #16
; CHECK-CAS-O0-NEXT: ret ; CHECK-CAS-O0-NEXT: ret
%pair = cmpxchg i128* %p, i128 %oldval, i128 %newval release acquire %pair = cmpxchg i128* %p, i128 %oldval, i128 %newval release acquire
%val = extractvalue { i128, i1 } %pair, 0 %val = extractvalue { i128, i1 } %pair, 0
store i128 %val, i128* %p store i128 %val, i128* %p
ret void ret void
} }
define void @atomic_load_relaxed(i64, i64, i128* %p, i128* %p2) { define void @atomic_load_relaxed(i64, i64, i128* %p, i128* %p2) {
Show All 20 Lines
; CHECK-CAS-O1-NEXT: // %bb.2: // %atomicrmw.end ; CHECK-CAS-O1-NEXT: // %bb.2: // %atomicrmw.end
; CHECK-CAS-O1-NEXT: mov v0.d[0], x9 ; CHECK-CAS-O1-NEXT: mov v0.d[0], x9
; CHECK-CAS-O1-NEXT: mov v0.d[1], x8 ; CHECK-CAS-O1-NEXT: mov v0.d[1], x8
; CHECK-CAS-O1-NEXT: str q0, [x3] ; CHECK-CAS-O1-NEXT: str q0, [x3]
; CHECK-CAS-O1-NEXT: ret ; CHECK-CAS-O1-NEXT: ret
; ;
; CHECK-LLSC-O0-LABEL: atomic_load_relaxed: ; CHECK-LLSC-O0-LABEL: atomic_load_relaxed:
; CHECK-LLSC-O0: // %bb.0: ; CHECK-LLSC-O0: // %bb.0:
; CHECK-LLSC-O0-NEXT: sub sp, sp, #64 // =64 ; CHECK-LLSC-O0-NEXT: sub sp, sp, #64
; CHECK-LLSC-O0-NEXT: .cfi_def_cfa_offset 64 ; CHECK-LLSC-O0-NEXT: .cfi_def_cfa_offset 64
; CHECK-LLSC-O0-NEXT: str x2, [sp, #48] // 8-byte Folded Spill ; CHECK-LLSC-O0-NEXT: str x2, [sp, #48] // 8-byte Folded Spill
; CHECK-LLSC-O0-NEXT: str x3, [sp, #56] // 8-byte Folded Spill ; CHECK-LLSC-O0-NEXT: str x3, [sp, #56] // 8-byte Folded Spill
; CHECK-LLSC-O0-NEXT: b .LBB4_1 ; CHECK-LLSC-O0-NEXT: b .LBB4_1
; CHECK-LLSC-O0-NEXT: .LBB4_1: // %atomicrmw.start ; CHECK-LLSC-O0-NEXT: .LBB4_1: // %atomicrmw.start
; CHECK-LLSC-O0-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-LLSC-O0-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-LLSC-O0-NEXT: ldr x11, [sp, #48] // 8-byte Folded Reload ; CHECK-LLSC-O0-NEXT: ldr x11, [sp, #48] // 8-byte Folded Reload
; CHECK-LLSC-O0-NEXT: ldxp x9, x15, [x11] ; CHECK-LLSC-O0-NEXT: ldxp x9, x15, [x11]
; CHECK-LLSC-O0-NEXT: mov x12, xzr ; CHECK-LLSC-O0-NEXT: mov x12, xzr
; CHECK-LLSC-O0-NEXT: mov w8, #64 ; CHECK-LLSC-O0-NEXT: mov w8, #64
; CHECK-LLSC-O0-NEXT: // kill: def $x8 killed $w8 ; CHECK-LLSC-O0-NEXT: // kill: def $x8 killed $w8
; CHECK-LLSC-O0-NEXT: mov w10, #64 ; CHECK-LLSC-O0-NEXT: mov w10, #64
; CHECK-LLSC-O0-NEXT: // kill: def $x10 killed $w10 ; CHECK-LLSC-O0-NEXT: // kill: def $x10 killed $w10
; CHECK-LLSC-O0-NEXT: str x10, [sp, #8] // 8-byte Folded Spill ; CHECK-LLSC-O0-NEXT: str x10, [sp, #8] // 8-byte Folded Spill
; CHECK-LLSC-O0-NEXT: subs x16, x10, #64 // =64 ; CHECK-LLSC-O0-NEXT: subs x16, x10, #64
; CHECK-LLSC-O0-NEXT: subs x13, x8, #64 // =64 ; CHECK-LLSC-O0-NEXT: subs x13, x8, #64
; CHECK-LLSC-O0-NEXT: lsl x14, x15, x10 ; CHECK-LLSC-O0-NEXT: lsl x14, x15, x10
; CHECK-LLSC-O0-NEXT: lsr x13, x15, x13 ; CHECK-LLSC-O0-NEXT: lsr x13, x15, x13
; CHECK-LLSC-O0-NEXT: orr x13, x13, x12 ; CHECK-LLSC-O0-NEXT: orr x13, x13, x12
; CHECK-LLSC-O0-NEXT: lsl x15, x15, x16 ; CHECK-LLSC-O0-NEXT: lsl x15, x15, x16
; CHECK-LLSC-O0-NEXT: subs x16, x10, #64 // =64 ; CHECK-LLSC-O0-NEXT: subs x16, x10, #64
; CHECK-LLSC-O0-NEXT: csel x14, x14, x12, lo ; CHECK-LLSC-O0-NEXT: csel x14, x14, x12, lo
; CHECK-LLSC-O0-NEXT: subs x16, x10, #64 // =64 ; CHECK-LLSC-O0-NEXT: subs x16, x10, #64
; CHECK-LLSC-O0-NEXT: csel x13, x13, x15, lo ; CHECK-LLSC-O0-NEXT: csel x13, x13, x15, lo
; CHECK-LLSC-O0-NEXT: subs x15, x10, #0 // =0 ; CHECK-LLSC-O0-NEXT: subs x15, x10, #0
; CHECK-LLSC-O0-NEXT: csel x13, x12, x13, eq ; CHECK-LLSC-O0-NEXT: csel x13, x12, x13, eq
; CHECK-LLSC-O0-NEXT: orr x9, x9, x14 ; CHECK-LLSC-O0-NEXT: orr x9, x9, x14
; CHECK-LLSC-O0-NEXT: orr x12, x12, x13 ; CHECK-LLSC-O0-NEXT: orr x12, x12, x13
; CHECK-LLSC-O0-NEXT: // implicit-def: $q0 ; CHECK-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-LLSC-O0-NEXT: mov v0.d[0], x9 ; CHECK-LLSC-O0-NEXT: mov v0.d[0], x9
; CHECK-LLSC-O0-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-LLSC-O0-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-LLSC-O0-NEXT: mov v0.d[1], x12 ; CHECK-LLSC-O0-NEXT: mov v0.d[1], x12
; CHECK-LLSC-O0-NEXT: str q0, [sp, #32] // 16-byte Folded Spill ; CHECK-LLSC-O0-NEXT: str q0, [sp, #32] // 16-byte Folded Spill
; CHECK-LLSC-O0-NEXT: subs x13, x10, #64 // =64 ; CHECK-LLSC-O0-NEXT: subs x13, x10, #64
; CHECK-LLSC-O0-NEXT: subs x8, x8, #64 // =64 ; CHECK-LLSC-O0-NEXT: subs x8, x8, #64
; CHECK-LLSC-O0-NEXT: lsl x8, x12, x8 ; CHECK-LLSC-O0-NEXT: lsl x8, x12, x8
; CHECK-LLSC-O0-NEXT: orr x8, x8, x9, lsr #0 ; CHECK-LLSC-O0-NEXT: orr x8, x8, x9, lsr #0
; CHECK-LLSC-O0-NEXT: lsr x12, x12, x13 ; CHECK-LLSC-O0-NEXT: lsr x12, x12, x13
; CHECK-LLSC-O0-NEXT: subs x13, x10, #64 // =64 ; CHECK-LLSC-O0-NEXT: subs x13, x10, #64
; CHECK-LLSC-O0-NEXT: csel x8, x8, x12, lo ; CHECK-LLSC-O0-NEXT: csel x8, x8, x12, lo
; CHECK-LLSC-O0-NEXT: subs x10, x10, #0 // =0 ; CHECK-LLSC-O0-NEXT: subs x10, x10, #0
; CHECK-LLSC-O0-NEXT: csel x10, x9, x8, eq ; CHECK-LLSC-O0-NEXT: csel x10, x9, x8, eq
; CHECK-LLSC-O0-NEXT: stxp w8, x9, x10, [x11] ; CHECK-LLSC-O0-NEXT: stxp w8, x9, x10, [x11]
; CHECK-LLSC-O0-NEXT: cbnz w8, .LBB4_1 ; CHECK-LLSC-O0-NEXT: cbnz w8, .LBB4_1
; CHECK-LLSC-O0-NEXT: b .LBB4_2 ; CHECK-LLSC-O0-NEXT: b .LBB4_2
; CHECK-LLSC-O0-NEXT: .LBB4_2: // %atomicrmw.end ; CHECK-LLSC-O0-NEXT: .LBB4_2: // %atomicrmw.end
; CHECK-LLSC-O0-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-LLSC-O0-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-LLSC-O0-NEXT: ldr x8, [sp, #56] // 8-byte Folded Reload ; CHECK-LLSC-O0-NEXT: ldr x8, [sp, #56] // 8-byte Folded Reload
; CHECK-LLSC-O0-NEXT: str q0, [x8] ; CHECK-LLSC-O0-NEXT: str q0, [x8]
; CHECK-LLSC-O0-NEXT: add sp, sp, #64 // =64 ; CHECK-LLSC-O0-NEXT: add sp, sp, #64
; CHECK-LLSC-O0-NEXT: ret ; CHECK-LLSC-O0-NEXT: ret
; ;
; CHECK-CAS-O0-LABEL: atomic_load_relaxed: ; CHECK-CAS-O0-LABEL: atomic_load_relaxed:
; CHECK-CAS-O0: // %bb.0: ; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #64 // =64 ; CHECK-CAS-O0-NEXT: sub sp, sp, #64
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 64 ; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 64
; CHECK-CAS-O0-NEXT: str x2, [sp, #48] // 8-byte Folded Spill ; CHECK-CAS-O0-NEXT: str x2, [sp, #48] // 8-byte Folded Spill
; CHECK-CAS-O0-NEXT: str x3, [sp, #56] // 8-byte Folded Spill ; CHECK-CAS-O0-NEXT: str x3, [sp, #56] // 8-byte Folded Spill
; CHECK-CAS-O0-NEXT: b .LBB4_1 ; CHECK-CAS-O0-NEXT: b .LBB4_1
; CHECK-CAS-O0-NEXT: .LBB4_1: // %atomicrmw.start ; CHECK-CAS-O0-NEXT: .LBB4_1: // %atomicrmw.start
; CHECK-CAS-O0-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-CAS-O0-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-CAS-O0-NEXT: ldr x11, [sp, #48] // 8-byte Folded Reload ; CHECK-CAS-O0-NEXT: ldr x11, [sp, #48] // 8-byte Folded Reload
; CHECK-CAS-O0-NEXT: ldxp x9, x15, [x11] ; CHECK-CAS-O0-NEXT: ldxp x9, x15, [x11]
; CHECK-CAS-O0-NEXT: mov x12, #0 ; CHECK-CAS-O0-NEXT: mov x12, #0
; CHECK-CAS-O0-NEXT: mov w8, #64 ; CHECK-CAS-O0-NEXT: mov w8, #64
; CHECK-CAS-O0-NEXT: // kill: def $x8 killed $w8 ; CHECK-CAS-O0-NEXT: // kill: def $x8 killed $w8
; CHECK-CAS-O0-NEXT: mov w10, #64 ; CHECK-CAS-O0-NEXT: mov w10, #64
; CHECK-CAS-O0-NEXT: // kill: def $x10 killed $w10 ; CHECK-CAS-O0-NEXT: // kill: def $x10 killed $w10
; CHECK-CAS-O0-NEXT: str x10, [sp, #8] // 8-byte Folded Spill ; CHECK-CAS-O0-NEXT: str x10, [sp, #8] // 8-byte Folded Spill
; CHECK-CAS-O0-NEXT: subs x16, x10, #64 // =64 ; CHECK-CAS-O0-NEXT: subs x16, x10, #64
; CHECK-CAS-O0-NEXT: subs x13, x8, #64 // =64 ; CHECK-CAS-O0-NEXT: subs x13, x8, #64
; CHECK-CAS-O0-NEXT: lsl x14, x15, x10 ; CHECK-CAS-O0-NEXT: lsl x14, x15, x10
; CHECK-CAS-O0-NEXT: lsr x13, x15, x13 ; CHECK-CAS-O0-NEXT: lsr x13, x15, x13
; CHECK-CAS-O0-NEXT: orr x13, x13, x12 ; CHECK-CAS-O0-NEXT: orr x13, x13, x12
; CHECK-CAS-O0-NEXT: lsl x15, x15, x16 ; CHECK-CAS-O0-NEXT: lsl x15, x15, x16
; CHECK-CAS-O0-NEXT: subs x16, x10, #64 // =64 ; CHECK-CAS-O0-NEXT: subs x16, x10, #64
; CHECK-CAS-O0-NEXT: csel x14, x14, x12, lo ; CHECK-CAS-O0-NEXT: csel x14, x14, x12, lo
; CHECK-CAS-O0-NEXT: subs x16, x10, #64 // =64 ; CHECK-CAS-O0-NEXT: subs x16, x10, #64
; CHECK-CAS-O0-NEXT: csel x13, x13, x15, lo ; CHECK-CAS-O0-NEXT: csel x13, x13, x15, lo
; CHECK-CAS-O0-NEXT: subs x15, x10, #0 // =0 ; CHECK-CAS-O0-NEXT: subs x15, x10, #0
; CHECK-CAS-O0-NEXT: csel x13, x12, x13, eq ; CHECK-CAS-O0-NEXT: csel x13, x12, x13, eq
; CHECK-CAS-O0-NEXT: orr x9, x9, x14 ; CHECK-CAS-O0-NEXT: orr x9, x9, x14
; CHECK-CAS-O0-NEXT: orr x12, x12, x13 ; CHECK-CAS-O0-NEXT: orr x12, x12, x13
; CHECK-CAS-O0-NEXT: // implicit-def: $q0 ; CHECK-CAS-O0-NEXT: // implicit-def: $q0
; CHECK-CAS-O0-NEXT: mov v0.d[0], x9 ; CHECK-CAS-O0-NEXT: mov v0.d[0], x9
; CHECK-CAS-O0-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-CAS-O0-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-CAS-O0-NEXT: mov v0.d[1], x12 ; CHECK-CAS-O0-NEXT: mov v0.d[1], x12
; CHECK-CAS-O0-NEXT: str q0, [sp, #32] // 16-byte Folded Spill ; CHECK-CAS-O0-NEXT: str q0, [sp, #32] // 16-byte Folded Spill
; CHECK-CAS-O0-NEXT: subs x13, x10, #64 // =64 ; CHECK-CAS-O0-NEXT: subs x13, x10, #64
; CHECK-CAS-O0-NEXT: subs x8, x8, #64 // =64 ; CHECK-CAS-O0-NEXT: subs x8, x8, #64
; CHECK-CAS-O0-NEXT: lsl x8, x12, x8 ; CHECK-CAS-O0-NEXT: lsl x8, x12, x8
; CHECK-CAS-O0-NEXT: orr x8, x8, x9, lsr #0 ; CHECK-CAS-O0-NEXT: orr x8, x8, x9, lsr #0
; CHECK-CAS-O0-NEXT: lsr x12, x12, x13 ; CHECK-CAS-O0-NEXT: lsr x12, x12, x13
; CHECK-CAS-O0-NEXT: subs x13, x10, #64 // =64 ; CHECK-CAS-O0-NEXT: subs x13, x10, #64
; CHECK-CAS-O0-NEXT: csel x8, x8, x12, lo ; CHECK-CAS-O0-NEXT: csel x8, x8, x12, lo
; CHECK-CAS-O0-NEXT: subs x10, x10, #0 // =0 ; CHECK-CAS-O0-NEXT: subs x10, x10, #0
; CHECK-CAS-O0-NEXT: csel x10, x9, x8, eq ; CHECK-CAS-O0-NEXT: csel x10, x9, x8, eq
; CHECK-CAS-O0-NEXT: stxp w8, x9, x10, [x11] ; CHECK-CAS-O0-NEXT: stxp w8, x9, x10, [x11]
; CHECK-CAS-O0-NEXT: cbnz w8, .LBB4_1 ; CHECK-CAS-O0-NEXT: cbnz w8, .LBB4_1
; CHECK-CAS-O0-NEXT: b .LBB4_2 ; CHECK-CAS-O0-NEXT: b .LBB4_2
; CHECK-CAS-O0-NEXT: .LBB4_2: // %atomicrmw.end ; CHECK-CAS-O0-NEXT: .LBB4_2: // %atomicrmw.end
; CHECK-CAS-O0-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-CAS-O0-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-CAS-O0-NEXT: ldr x8, [sp, #56] // 8-byte Folded Reload ; CHECK-CAS-O0-NEXT: ldr x8, [sp, #56] // 8-byte Folded Reload
; CHECK-CAS-O0-NEXT: str q0, [x8] ; CHECK-CAS-O0-NEXT: str q0, [x8]
; CHECK-CAS-O0-NEXT: add sp, sp, #64 // =64 ; CHECK-CAS-O0-NEXT: add sp, sp, #64
; CHECK-CAS-O0-NEXT: ret ; CHECK-CAS-O0-NEXT: ret
%r = load atomic i128, i128* %p monotonic, align 16 %r = load atomic i128, i128* %p monotonic, align 16
store i128 %r, i128* %p2 store i128 %r, i128* %p2
ret void ret void
} }

llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll

Show First 20 Lines • Show All 319 Lines • ▼ Show 20 Lines
; CHECK-NOLSE-O1-NEXT: stlxr w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stlxr w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB6_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB6_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: fetch_and_nand: ; CHECK-NOLSE-O0-LABEL: fetch_and_nand:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB6_1 ; CHECK-NOLSE-O0-NEXT: b LBB6_1
; CHECK-NOLSE-O0-NEXT: LBB6_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB6_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB6_2 Depth 2 ; CHECK-NOLSE-O0-NEXT: ; Child Loop BB6_2 Depth 2
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Folded Reload
Show All 15 Lines
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #12] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #12] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: subs w8, w9, w8 ; CHECK-NOLSE-O0-NEXT: subs w8, w9, w8
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB6_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB6_1
; CHECK-NOLSE-O0-NEXT: b LBB6_5 ; CHECK-NOLSE-O0-NEXT: b LBB6_5
; CHECK-NOLSE-O0-NEXT: LBB6_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB6_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: fetch_and_nand: ; CHECK-LSE-O1-LABEL: fetch_and_nand:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: LBB6_1: ; %atomicrmw.start ; CHECK-LSE-O1-NEXT: LBB6_1: ; %atomicrmw.start
; CHECK-LSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-LSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-LSE-O1-NEXT: ldxr w8, [x0] ; CHECK-LSE-O1-NEXT: ldxr w8, [x0]
; CHECK-LSE-O1-NEXT: and w9, w8, #0x7 ; CHECK-LSE-O1-NEXT: and w9, w8, #0x7
; CHECK-LSE-O1-NEXT: mvn w9, w9 ; CHECK-LSE-O1-NEXT: mvn w9, w9
; CHECK-LSE-O1-NEXT: stlxr w10, w9, [x0] ; CHECK-LSE-O1-NEXT: stlxr w10, w9, [x0]
; CHECK-LSE-O1-NEXT: cbnz w10, LBB6_1 ; CHECK-LSE-O1-NEXT: cbnz w10, LBB6_1
; CHECK-LSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-LSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-LSE-O1-NEXT: mov x0, x8 ; CHECK-LSE-O1-NEXT: mov x0, x8
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: fetch_and_nand: ; CHECK-LSE-O0-LABEL: fetch_and_nand:
; CHECK-LSE-O0: ; %bb.0: ; CHECK-LSE-O0: ; %bb.0:
; CHECK-LSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-LSE-O0-NEXT: sub sp, sp, #32
; CHECK-LSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-LSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-LSE-O0-NEXT: ldr w8, [x0] ; CHECK-LSE-O0-NEXT: ldr w8, [x0]
; CHECK-LSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-LSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-LSE-O0-NEXT: b LBB6_1 ; CHECK-LSE-O0-NEXT: b LBB6_1
; CHECK-LSE-O0-NEXT: LBB6_1: ; %atomicrmw.start ; CHECK-LSE-O0-NEXT: LBB6_1: ; %atomicrmw.start
; CHECK-LSE-O0-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-LSE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-LSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Folded Reload ; CHECK-LSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Folded Reload
; CHECK-LSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload ; CHECK-LSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-LSE-O0-NEXT: and w9, w8, #0x7 ; CHECK-LSE-O0-NEXT: and w9, w8, #0x7
; CHECK-LSE-O0-NEXT: mvn w10, w9 ; CHECK-LSE-O0-NEXT: mvn w10, w9
; CHECK-LSE-O0-NEXT: mov x9, x8 ; CHECK-LSE-O0-NEXT: mov x9, x8
; CHECK-LSE-O0-NEXT: casl w9, w10, [x11] ; CHECK-LSE-O0-NEXT: casl w9, w10, [x11]
; CHECK-LSE-O0-NEXT: str w9, [sp, #12] ; 4-byte Folded Spill ; CHECK-LSE-O0-NEXT: str w9, [sp, #12] ; 4-byte Folded Spill
; CHECK-LSE-O0-NEXT: subs w8, w9, w8 ; CHECK-LSE-O0-NEXT: subs w8, w9, w8
; CHECK-LSE-O0-NEXT: cset w8, eq ; CHECK-LSE-O0-NEXT: cset w8, eq
; CHECK-LSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-LSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-LSE-O0-NEXT: tbz w8, #0, LBB6_1 ; CHECK-LSE-O0-NEXT: tbz w8, #0, LBB6_1
; CHECK-LSE-O0-NEXT: b LBB6_2 ; CHECK-LSE-O0-NEXT: b LBB6_2
; CHECK-LSE-O0-NEXT: LBB6_2: ; %atomicrmw.end ; CHECK-LSE-O0-NEXT: LBB6_2: ; %atomicrmw.end
; CHECK-LSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-LSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-LSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-LSE-O0-NEXT: add sp, sp, #32
; CHECK-LSE-O0-NEXT: ret ; CHECK-LSE-O0-NEXT: ret
%val = atomicrmw nand i32* %p, i32 7 release %val = atomicrmw nand i32* %p, i32 7 release
ret i32 %val ret i32 %val
} }
define i64 @fetch_and_nand_64(i64* %p) #0 { define i64 @fetch_and_nand_64(i64* %p) #0 {
; CHECK-NOLSE-O1-LABEL: fetch_and_nand_64: ; CHECK-NOLSE-O1-LABEL: fetch_and_nand_64:
; CHECK-NOLSE-O1: ; %bb.0: ; CHECK-NOLSE-O1: ; %bb.0:
; CHECK-NOLSE-O1-NEXT: LBB7_1: ; %atomicrmw.start ; CHECK-NOLSE-O1-NEXT: LBB7_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O1-NEXT: ldaxr x8, [x0] ; CHECK-NOLSE-O1-NEXT: ldaxr x8, [x0]
; CHECK-NOLSE-O1-NEXT: and x9, x8, #0x7 ; CHECK-NOLSE-O1-NEXT: and x9, x8, #0x7
; CHECK-NOLSE-O1-NEXT: mvn x9, x9 ; CHECK-NOLSE-O1-NEXT: mvn x9, x9
; CHECK-NOLSE-O1-NEXT: stlxr w10, x9, [x0] ; CHECK-NOLSE-O1-NEXT: stlxr w10, x9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB7_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB7_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov x0, x8 ; CHECK-NOLSE-O1-NEXT: mov x0, x8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: fetch_and_nand_64: ; CHECK-NOLSE-O0-LABEL: fetch_and_nand_64:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldr x8, [x0] ; CHECK-NOLSE-O0-NEXT: ldr x8, [x0]
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB7_1 ; CHECK-NOLSE-O0-NEXT: b LBB7_1
; CHECK-NOLSE-O0-NEXT: LBB7_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB7_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB7_2 Depth 2 ; CHECK-NOLSE-O0-NEXT: ; Child Loop BB7_2 Depth 2
; CHECK-NOLSE-O0-NEXT: ldr x8, [sp, #24] ; 8-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr x8, [sp, #24] ; 8-byte Folded Reload
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; CHECK-NOLSE-O0-NEXT: str x9, [sp, #8] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x9, [sp, #8] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: subs x8, x9, x8 ; CHECK-NOLSE-O0-NEXT: subs x8, x9, x8
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str x9, [sp, #24] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x9, [sp, #24] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB7_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB7_1
; CHECK-NOLSE-O0-NEXT: b LBB7_5 ; CHECK-NOLSE-O0-NEXT: b LBB7_5
; CHECK-NOLSE-O0-NEXT: LBB7_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB7_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr x0, [sp, #8] ; 8-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr x0, [sp, #8] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: fetch_and_nand_64: ; CHECK-LSE-O1-LABEL: fetch_and_nand_64:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: LBB7_1: ; %atomicrmw.start ; CHECK-LSE-O1-NEXT: LBB7_1: ; %atomicrmw.start
; CHECK-LSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-LSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-LSE-O1-NEXT: ldaxr x8, [x0] ; CHECK-LSE-O1-NEXT: ldaxr x8, [x0]
; CHECK-LSE-O1-NEXT: and x9, x8, #0x7 ; CHECK-LSE-O1-NEXT: and x9, x8, #0x7
; CHECK-LSE-O1-NEXT: mvn x9, x9 ; CHECK-LSE-O1-NEXT: mvn x9, x9
; CHECK-LSE-O1-NEXT: stlxr w10, x9, [x0] ; CHECK-LSE-O1-NEXT: stlxr w10, x9, [x0]
; CHECK-LSE-O1-NEXT: cbnz w10, LBB7_1 ; CHECK-LSE-O1-NEXT: cbnz w10, LBB7_1
; CHECK-LSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-LSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-LSE-O1-NEXT: mov x0, x8 ; CHECK-LSE-O1-NEXT: mov x0, x8
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: fetch_and_nand_64: ; CHECK-LSE-O0-LABEL: fetch_and_nand_64:
; CHECK-LSE-O0: ; %bb.0: ; CHECK-LSE-O0: ; %bb.0:
; CHECK-LSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-LSE-O0-NEXT: sub sp, sp, #32
; CHECK-LSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-LSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-LSE-O0-NEXT: ldr x8, [x0] ; CHECK-LSE-O0-NEXT: ldr x8, [x0]
; CHECK-LSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Folded Spill ; CHECK-LSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Folded Spill
; CHECK-LSE-O0-NEXT: b LBB7_1 ; CHECK-LSE-O0-NEXT: b LBB7_1
; CHECK-LSE-O0-NEXT: LBB7_1: ; %atomicrmw.start ; CHECK-LSE-O0-NEXT: LBB7_1: ; %atomicrmw.start
; CHECK-LSE-O0-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-LSE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-LSE-O0-NEXT: ldr x8, [sp, #24] ; 8-byte Folded Reload ; CHECK-LSE-O0-NEXT: ldr x8, [sp, #24] ; 8-byte Folded Reload
; CHECK-LSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload ; CHECK-LSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-LSE-O0-NEXT: and x9, x8, #0x7 ; CHECK-LSE-O0-NEXT: and x9, x8, #0x7
; CHECK-LSE-O0-NEXT: mvn x10, x9 ; CHECK-LSE-O0-NEXT: mvn x10, x9
; CHECK-LSE-O0-NEXT: mov x9, x8 ; CHECK-LSE-O0-NEXT: mov x9, x8
; CHECK-LSE-O0-NEXT: casal x9, x10, [x11] ; CHECK-LSE-O0-NEXT: casal x9, x10, [x11]
; CHECK-LSE-O0-NEXT: str x9, [sp, #8] ; 8-byte Folded Spill ; CHECK-LSE-O0-NEXT: str x9, [sp, #8] ; 8-byte Folded Spill
; CHECK-LSE-O0-NEXT: subs x8, x9, x8 ; CHECK-LSE-O0-NEXT: subs x8, x9, x8
; CHECK-LSE-O0-NEXT: cset w8, eq ; CHECK-LSE-O0-NEXT: cset w8, eq
; CHECK-LSE-O0-NEXT: str x9, [sp, #24] ; 8-byte Folded Spill ; CHECK-LSE-O0-NEXT: str x9, [sp, #24] ; 8-byte Folded Spill
; CHECK-LSE-O0-NEXT: tbz w8, #0, LBB7_1 ; CHECK-LSE-O0-NEXT: tbz w8, #0, LBB7_1
; CHECK-LSE-O0-NEXT: b LBB7_2 ; CHECK-LSE-O0-NEXT: b LBB7_2
; CHECK-LSE-O0-NEXT: LBB7_2: ; %atomicrmw.end ; CHECK-LSE-O0-NEXT: LBB7_2: ; %atomicrmw.end
; CHECK-LSE-O0-NEXT: ldr x0, [sp, #8] ; 8-byte Folded Reload ; CHECK-LSE-O0-NEXT: ldr x0, [sp, #8] ; 8-byte Folded Reload
; CHECK-LSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-LSE-O0-NEXT: add sp, sp, #32
; CHECK-LSE-O0-NEXT: ret ; CHECK-LSE-O0-NEXT: ret
%val = atomicrmw nand i64* %p, i64 7 acq_rel %val = atomicrmw nand i64* %p, i64 7 acq_rel
ret i64 %val ret i64 %val
} }
define i32 @fetch_and_or(i32* %p) #0 { define i32 @fetch_and_or(i32* %p) #0 {
; CHECK-NOLSE-O1-LABEL: fetch_and_or: ; CHECK-NOLSE-O1-LABEL: fetch_and_or:
; CHECK-NOLSE-O1: ; %bb.0: ; CHECK-NOLSE-O1: ; %bb.0:
; CHECK-NOLSE-O1-NEXT: mov w9, #5 ; CHECK-NOLSE-O1-NEXT: mov w9, #5
; CHECK-NOLSE-O1-NEXT: LBB8_1: ; %atomicrmw.start ; CHECK-NOLSE-O1-NEXT: LBB8_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O1-NEXT: ldaxr w8, [x0] ; CHECK-NOLSE-O1-NEXT: ldaxr w8, [x0]
; CHECK-NOLSE-O1-NEXT: orr w10, w8, w9 ; CHECK-NOLSE-O1-NEXT: orr w10, w8, w9
; CHECK-NOLSE-O1-NEXT: stlxr w11, w10, [x0] ; CHECK-NOLSE-O1-NEXT: stlxr w11, w10, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB8_1 ; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB8_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: fetch_and_or: ; CHECK-NOLSE-O0-LABEL: fetch_and_or:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB8_1 ; CHECK-NOLSE-O0-NEXT: b LBB8_1
; CHECK-NOLSE-O0-NEXT: LBB8_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB8_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB8_2 Depth 2 ; CHECK-NOLSE-O0-NEXT: ; Child Loop BB8_2 Depth 2
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Folded Reload
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; CHECK-NOLSE-O0-NEXT: str w9, [sp, #12] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #12] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: subs w8, w9, w8 ; CHECK-NOLSE-O0-NEXT: subs w8, w9, w8
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB8_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB8_1
; CHECK-NOLSE-O0-NEXT: LBB8_5 ; CHECK-NOLSE-O0-NEXT: LBB8_5
; CHECK-NOLSE-O0-NEXT: LBB8_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB8_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: fetch_and_or: ; CHECK-LSE-O1-LABEL: fetch_and_or:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: mov w8, #5 ; CHECK-LSE-O1-NEXT: mov w8, #5
; CHECK-LSE-O1-NEXT: ldsetal w8, w0, [x0] ; CHECK-LSE-O1-NEXT: ldsetal w8, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
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; CHECK-NOLSE-O1-NEXT: stxr w10, x9, [x0] ; CHECK-NOLSE-O1-NEXT: stxr w10, x9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB9_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB9_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov x0, x8 ; CHECK-NOLSE-O1-NEXT: mov x0, x8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: fetch_and_or_64: ; CHECK-NOLSE-O0-LABEL: fetch_and_or_64:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldr x8, [x0] ; CHECK-NOLSE-O0-NEXT: ldr x8, [x0]
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB9_1 ; CHECK-NOLSE-O0-NEXT: b LBB9_1
; CHECK-NOLSE-O0-NEXT: LBB9_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB9_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB9_2 Depth 2 ; CHECK-NOLSE-O0-NEXT: ; Child Loop BB9_2 Depth 2
; CHECK-NOLSE-O0-NEXT: ldr x8, [sp, #24] ; 8-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr x8, [sp, #24] ; 8-byte Folded Reload
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; CHECK-NOLSE-O0-NEXT: str x9, [sp, #8] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x9, [sp, #8] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: subs x8, x9, x8 ; CHECK-NOLSE-O0-NEXT: subs x8, x9, x8
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str x9, [sp, #24] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x9, [sp, #24] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB9_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB9_1
; CHECK-NOLSE-O0-NEXT: b LBB9_5 ; CHECK-NOLSE-O0-NEXT: b LBB9_5
; CHECK-NOLSE-O0-NEXT: LBB9_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB9_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr x0, [sp, #8] ; 8-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr x0, [sp, #8] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: fetch_and_or_64: ; CHECK-LSE-O1-LABEL: fetch_and_or_64:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: mov w8, #7 ; CHECK-LSE-O1-NEXT: mov w8, #7
; CHECK-LSE-O1-NEXT: ldset x8, x0, [x0] ; CHECK-LSE-O1-NEXT: ldset x8, x0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
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; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomic_load_relaxed_8: ; CHECK-NOLSE-O0-LABEL: atomic_load_relaxed_8:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: ldrb w9, [x0, #4095] ; CHECK-NOLSE-O0-NEXT: ldrb w9, [x0, #4095]
; CHECK-NOLSE-O0-NEXT: add x8, x0, w1, sxtw ; CHECK-NOLSE-O0-NEXT: add x8, x0, w1, sxtw
; CHECK-NOLSE-O0-NEXT: ldrb w8, [x8] ; CHECK-NOLSE-O0-NEXT: ldrb w8, [x8]
; CHECK-NOLSE-O0-NEXT: add w8, w8, w9, uxtb ; CHECK-NOLSE-O0-NEXT: add w8, w8, w9, uxtb
; CHECK-NOLSE-O0-NEXT: subs x9, x0, #256 ; =256 ; CHECK-NOLSE-O0-NEXT: subs x9, x0, #256
; CHECK-NOLSE-O0-NEXT: ldrb w9, [x9] ; CHECK-NOLSE-O0-NEXT: ldrb w9, [x9]
; CHECK-NOLSE-O0-NEXT: add w8, w8, w9, uxtb ; CHECK-NOLSE-O0-NEXT: add w8, w8, w9, uxtb
; CHECK-NOLSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936 ; CHECK-NOLSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936
; CHECK-NOLSE-O0-NEXT: ldrb w9, [x9] ; CHECK-NOLSE-O0-NEXT: ldrb w9, [x9]
; CHECK-NOLSE-O0-NEXT: add w0, w8, w9, uxtb ; CHECK-NOLSE-O0-NEXT: add w0, w8, w9, uxtb
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomic_load_relaxed_8: ; CHECK-LSE-O1-LABEL: atomic_load_relaxed_8:
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; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomic_load_relaxed_8: ; CHECK-LSE-O0-LABEL: atomic_load_relaxed_8:
; CHECK-LSE-O0: ; %bb.0: ; CHECK-LSE-O0: ; %bb.0:
; CHECK-LSE-O0-NEXT: ldrb w9, [x0, #4095] ; CHECK-LSE-O0-NEXT: ldrb w9, [x0, #4095]
; CHECK-LSE-O0-NEXT: add x8, x0, w1, sxtw ; CHECK-LSE-O0-NEXT: add x8, x0, w1, sxtw
; CHECK-LSE-O0-NEXT: ldrb w8, [x8] ; CHECK-LSE-O0-NEXT: ldrb w8, [x8]
; CHECK-LSE-O0-NEXT: add w8, w8, w9, uxtb ; CHECK-LSE-O0-NEXT: add w8, w8, w9, uxtb
; CHECK-LSE-O0-NEXT: subs x9, x0, #256 ; =256 ; CHECK-LSE-O0-NEXT: subs x9, x0, #256
; CHECK-LSE-O0-NEXT: ldrb w9, [x9] ; CHECK-LSE-O0-NEXT: ldrb w9, [x9]
; CHECK-LSE-O0-NEXT: add w8, w8, w9, uxtb ; CHECK-LSE-O0-NEXT: add w8, w8, w9, uxtb
; CHECK-LSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936 ; CHECK-LSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936
; CHECK-LSE-O0-NEXT: ldrb w9, [x9] ; CHECK-LSE-O0-NEXT: ldrb w9, [x9]
; CHECK-LSE-O0-NEXT: add w0, w8, w9, uxtb ; CHECK-LSE-O0-NEXT: add w0, w8, w9, uxtb
; CHECK-LSE-O0-NEXT: ret ; CHECK-LSE-O0-NEXT: ret
%ptr_unsigned = getelementptr i8, i8* %p, i32 4095 %ptr_unsigned = getelementptr i8, i8* %p, i32 4095
%val_unsigned = load atomic i8, i8* %ptr_unsigned monotonic, align 1 %val_unsigned = load atomic i8, i8* %ptr_unsigned monotonic, align 1
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; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomic_load_relaxed_16: ; CHECK-NOLSE-O0-LABEL: atomic_load_relaxed_16:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: ldrh w9, [x0, #8190] ; CHECK-NOLSE-O0-NEXT: ldrh w9, [x0, #8190]
; CHECK-NOLSE-O0-NEXT: add x8, x0, w1, sxtw #1 ; CHECK-NOLSE-O0-NEXT: add x8, x0, w1, sxtw #1
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x8] ; CHECK-NOLSE-O0-NEXT: ldrh w8, [x8]
; CHECK-NOLSE-O0-NEXT: add w8, w8, w9, uxth ; CHECK-NOLSE-O0-NEXT: add w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: subs x9, x0, #256 ; =256 ; CHECK-NOLSE-O0-NEXT: subs x9, x0, #256
; CHECK-NOLSE-O0-NEXT: ldrh w9, [x9] ; CHECK-NOLSE-O0-NEXT: ldrh w9, [x9]
; CHECK-NOLSE-O0-NEXT: add w8, w8, w9, uxth ; CHECK-NOLSE-O0-NEXT: add w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936 ; CHECK-NOLSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936
; CHECK-NOLSE-O0-NEXT: ldrh w9, [x9] ; CHECK-NOLSE-O0-NEXT: ldrh w9, [x9]
; CHECK-NOLSE-O0-NEXT: add w0, w8, w9, uxth ; CHECK-NOLSE-O0-NEXT: add w0, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomic_load_relaxed_16: ; CHECK-LSE-O1-LABEL: atomic_load_relaxed_16:
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; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomic_load_relaxed_16: ; CHECK-LSE-O0-LABEL: atomic_load_relaxed_16:
; CHECK-LSE-O0: ; %bb.0: ; CHECK-LSE-O0: ; %bb.0:
; CHECK-LSE-O0-NEXT: ldrh w9, [x0, #8190] ; CHECK-LSE-O0-NEXT: ldrh w9, [x0, #8190]
; CHECK-LSE-O0-NEXT: add x8, x0, w1, sxtw #1 ; CHECK-LSE-O0-NEXT: add x8, x0, w1, sxtw #1
; CHECK-LSE-O0-NEXT: ldrh w8, [x8] ; CHECK-LSE-O0-NEXT: ldrh w8, [x8]
; CHECK-LSE-O0-NEXT: add w8, w8, w9, uxth ; CHECK-LSE-O0-NEXT: add w8, w8, w9, uxth
; CHECK-LSE-O0-NEXT: subs x9, x0, #256 ; =256 ; CHECK-LSE-O0-NEXT: subs x9, x0, #256
; CHECK-LSE-O0-NEXT: ldrh w9, [x9] ; CHECK-LSE-O0-NEXT: ldrh w9, [x9]
; CHECK-LSE-O0-NEXT: add w8, w8, w9, uxth ; CHECK-LSE-O0-NEXT: add w8, w8, w9, uxth
; CHECK-LSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936 ; CHECK-LSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936
; CHECK-LSE-O0-NEXT: ldrh w9, [x9] ; CHECK-LSE-O0-NEXT: ldrh w9, [x9]
; CHECK-LSE-O0-NEXT: add w0, w8, w9, uxth ; CHECK-LSE-O0-NEXT: add w0, w8, w9, uxth
; CHECK-LSE-O0-NEXT: ret ; CHECK-LSE-O0-NEXT: ret
%ptr_unsigned = getelementptr i16, i16* %p, i32 4095 %ptr_unsigned = getelementptr i16, i16* %p, i32 4095
%val_unsigned = load atomic i16, i16* %ptr_unsigned monotonic, align 2 %val_unsigned = load atomic i16, i16* %ptr_unsigned monotonic, align 2
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; CHECK-NOLSE-O1-NEXT: stlxrb w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stlxrb w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB27_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB27_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_add_i8: ; CHECK-NOLSE-O0-LABEL: atomicrmw_add_i8:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB27_1 ; CHECK-NOLSE-O0-NEXT: b LBB27_1
; CHECK-NOLSE-O0-NEXT: LBB27_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB27_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
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; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff ; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB27_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB27_1
; CHECK-NOLSE-O0-NEXT: b LBB27_5 ; CHECK-NOLSE-O0-NEXT: b LBB27_5
; CHECK-NOLSE-O0-NEXT: LBB27_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB27_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_add_i8: ; CHECK-LSE-O1-LABEL: atomicrmw_add_i8:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: ldaddalb w1, w0, [x0] ; CHECK-LSE-O1-NEXT: ldaddalb w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomicrmw_add_i8: ; CHECK-LSE-O0-LABEL: atomicrmw_add_i8:
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; CHECK-NOLSE-O1-NEXT: stxrb w9, w1, [x0] ; CHECK-NOLSE-O1-NEXT: stxrb w9, w1, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w9, LBB28_1 ; CHECK-NOLSE-O1-NEXT: cbnz w9, LBB28_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_xchg_i8: ; CHECK-NOLSE-O0-LABEL: atomicrmw_xchg_i8:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB28_1 ; CHECK-NOLSE-O0-NEXT: b LBB28_1
; CHECK-NOLSE-O0-NEXT: LBB28_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB28_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
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; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff ; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB28_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB28_1
; CHECK-NOLSE-O0-NEXT: b LBB28_5 ; CHECK-NOLSE-O0-NEXT: b LBB28_5
; CHECK-NOLSE-O0-NEXT: LBB28_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB28_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_xchg_i8: ; CHECK-LSE-O1-LABEL: atomicrmw_xchg_i8:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: swpb w1, w0, [x0] ; CHECK-LSE-O1-NEXT: swpb w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomicrmw_xchg_i8: ; CHECK-LSE-O0-LABEL: atomicrmw_xchg_i8:
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; CHECK-NOLSE-O1-NEXT: stxrb w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stxrb w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB29_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB29_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_sub_i8: ; CHECK-NOLSE-O0-LABEL: atomicrmw_sub_i8:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB29_1 ; CHECK-NOLSE-O0-NEXT: b LBB29_1
; CHECK-NOLSE-O0-NEXT: LBB29_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB29_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
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; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff ; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB29_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB29_1
; CHECK-NOLSE-O0-NEXT: b LBB29_5 ; CHECK-NOLSE-O0-NEXT: b LBB29_5
; CHECK-NOLSE-O0-NEXT: LBB29_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB29_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_sub_i8: ; CHECK-LSE-O1-LABEL: atomicrmw_sub_i8:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: neg w8, w1 ; CHECK-LSE-O1-NEXT: neg w8, w1
; CHECK-LSE-O1-NEXT: ldaddab w8, w0, [x0] ; CHECK-LSE-O1-NEXT: ldaddab w8, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
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; CHECK-NOLSE-O1-NEXT: stlxrb w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stlxrb w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB30_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB30_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_and_i8: ; CHECK-NOLSE-O0-LABEL: atomicrmw_and_i8:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB30_1 ; CHECK-NOLSE-O0-NEXT: b LBB30_1
; CHECK-NOLSE-O0-NEXT: LBB30_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB30_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
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; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff ; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB30_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB30_1
; CHECK-NOLSE-O0-NEXT: b LBB30_5 ; CHECK-NOLSE-O0-NEXT: b LBB30_5
; CHECK-NOLSE-O0-NEXT: LBB30_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB30_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_and_i8: ; CHECK-LSE-O1-LABEL: atomicrmw_and_i8:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: mvn w8, w1 ; CHECK-LSE-O1-NEXT: mvn w8, w1
; CHECK-LSE-O1-NEXT: ldclrlb w8, w0, [x0] ; CHECK-LSE-O1-NEXT: ldclrlb w8, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
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; CHECK-NOLSE-O1-NEXT: stlxrb w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stlxrb w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB31_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB31_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_or_i8: ; CHECK-NOLSE-O0-LABEL: atomicrmw_or_i8:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB31_1 ; CHECK-NOLSE-O0-NEXT: b LBB31_1
; CHECK-NOLSE-O0-NEXT: LBB31_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB31_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
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; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff ; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB31_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB31_1
; CHECK-NOLSE-O0-NEXT: b LBB31_5 ; CHECK-NOLSE-O0-NEXT: b LBB31_5
; CHECK-NOLSE-O0-NEXT: LBB31_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB31_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_or_i8: ; CHECK-LSE-O1-LABEL: atomicrmw_or_i8:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: ldsetalb w1, w0, [x0] ; CHECK-LSE-O1-NEXT: ldsetalb w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomicrmw_or_i8: ; CHECK-LSE-O0-LABEL: atomicrmw_or_i8:
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; CHECK-NOLSE-O1-NEXT: stxrb w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stxrb w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB32_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB32_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_xor_i8: ; CHECK-NOLSE-O0-LABEL: atomicrmw_xor_i8:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB32_1 ; CHECK-NOLSE-O0-NEXT: b LBB32_1
; CHECK-NOLSE-O0-NEXT: LBB32_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB32_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
Show All 18 Lines
; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff ; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB32_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB32_1
; CHECK-NOLSE-O0-NEXT: b LBB32_5 ; CHECK-NOLSE-O0-NEXT: b LBB32_5
; CHECK-NOLSE-O0-NEXT: LBB32_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB32_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_xor_i8: ; CHECK-LSE-O1-LABEL: atomicrmw_xor_i8:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: ldeorb w1, w0, [x0] ; CHECK-LSE-O1-NEXT: ldeorb w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomicrmw_xor_i8: ; CHECK-LSE-O0-LABEL: atomicrmw_xor_i8:
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; CHECK-NOLSE-O1-NEXT: stxrb w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stxrb w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB33_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB33_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_min_i8: ; CHECK-NOLSE-O0-LABEL: atomicrmw_min_i8:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB33_1 ; CHECK-NOLSE-O0-NEXT: b LBB33_1
; CHECK-NOLSE-O0-NEXT: LBB33_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB33_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
Show All 21 Lines
; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff ; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB33_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB33_1
; CHECK-NOLSE-O0-NEXT: b LBB33_5 ; CHECK-NOLSE-O0-NEXT: b LBB33_5
; CHECK-NOLSE-O0-NEXT: LBB33_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB33_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_min_i8: ; CHECK-LSE-O1-LABEL: atomicrmw_min_i8:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: ldsminab w1, w0, [x0] ; CHECK-LSE-O1-NEXT: ldsminab w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomicrmw_min_i8: ; CHECK-LSE-O0-LABEL: atomicrmw_min_i8:
Show All 16 Lines
; CHECK-NOLSE-O1-NEXT: stlxrb w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stlxrb w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB34_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB34_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_max_i8: ; CHECK-NOLSE-O0-LABEL: atomicrmw_max_i8:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB34_1 ; CHECK-NOLSE-O0-NEXT: b LBB34_1
; CHECK-NOLSE-O0-NEXT: LBB34_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB34_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
Show All 21 Lines
; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff ; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB34_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB34_1
; CHECK-NOLSE-O0-NEXT: b LBB34_5 ; CHECK-NOLSE-O0-NEXT: b LBB34_5
; CHECK-NOLSE-O0-NEXT: LBB34_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB34_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_max_i8: ; CHECK-LSE-O1-LABEL: atomicrmw_max_i8:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: ldsmaxlb w1, w0, [x0] ; CHECK-LSE-O1-NEXT: ldsmaxlb w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomicrmw_max_i8: ; CHECK-LSE-O0-LABEL: atomicrmw_max_i8:
Show All 16 Lines
; CHECK-NOLSE-O1-NEXT: stlxrb w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stlxrb w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB35_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB35_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_umin_i8: ; CHECK-NOLSE-O0-LABEL: atomicrmw_umin_i8:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB35_1 ; CHECK-NOLSE-O0-NEXT: b LBB35_1
; CHECK-NOLSE-O0-NEXT: LBB35_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB35_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
Show All 21 Lines
; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff ; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB35_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB35_1
; CHECK-NOLSE-O0-NEXT: b LBB35_5 ; CHECK-NOLSE-O0-NEXT: b LBB35_5
; CHECK-NOLSE-O0-NEXT: LBB35_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB35_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_umin_i8: ; CHECK-LSE-O1-LABEL: atomicrmw_umin_i8:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: lduminalb w1, w0, [x0] ; CHECK-LSE-O1-NEXT: lduminalb w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomicrmw_umin_i8: ; CHECK-LSE-O0-LABEL: atomicrmw_umin_i8:
Show All 16 Lines
; CHECK-NOLSE-O1-NEXT: stxrb w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stxrb w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB36_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB36_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_umax_i8: ; CHECK-NOLSE-O0-LABEL: atomicrmw_umax_i8:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrb w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB36_1 ; CHECK-NOLSE-O0-NEXT: b LBB36_1
; CHECK-NOLSE-O0-NEXT: LBB36_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB36_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
Show All 21 Lines
; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff ; CHECK-NOLSE-O0-NEXT: and w8, w9, #0xff
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w10, uxtb
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB36_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB36_1
; CHECK-NOLSE-O0-NEXT: b LBB36_5 ; CHECK-NOLSE-O0-NEXT: b LBB36_5
; CHECK-NOLSE-O0-NEXT: LBB36_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB36_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_umax_i8: ; CHECK-LSE-O1-LABEL: atomicrmw_umax_i8:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: ldumaxb w1, w0, [x0] ; CHECK-LSE-O1-NEXT: ldumaxb w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomicrmw_umax_i8: ; CHECK-LSE-O0-LABEL: atomicrmw_umax_i8:
Show All 14 Lines
; CHECK-NOLSE-O1-NEXT: stlxrh w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stlxrh w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB37_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB37_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_add_i16: ; CHECK-NOLSE-O0-LABEL: atomicrmw_add_i16:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB37_1 ; CHECK-NOLSE-O0-NEXT: b LBB37_1
; CHECK-NOLSE-O0-NEXT: LBB37_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB37_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
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; CHECK-NOLSE-O0-NEXT: uxth w8, w8 ; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB37_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB37_1
; CHECK-NOLSE-O0-NEXT: b LBB37_5 ; CHECK-NOLSE-O0-NEXT: b LBB37_5
; CHECK-NOLSE-O0-NEXT: LBB37_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB37_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_add_i16: ; CHECK-LSE-O1-LABEL: atomicrmw_add_i16:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: ldaddalh w1, w0, [x0] ; CHECK-LSE-O1-NEXT: ldaddalh w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomicrmw_add_i16: ; CHECK-LSE-O0-LABEL: atomicrmw_add_i16:
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; CHECK-NOLSE-O1-NEXT: stxrh w9, w1, [x0] ; CHECK-NOLSE-O1-NEXT: stxrh w9, w1, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w9, LBB38_1 ; CHECK-NOLSE-O1-NEXT: cbnz w9, LBB38_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_xchg_i16: ; CHECK-NOLSE-O0-LABEL: atomicrmw_xchg_i16:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB38_1 ; CHECK-NOLSE-O0-NEXT: b LBB38_1
; CHECK-NOLSE-O0-NEXT: LBB38_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB38_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
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; CHECK-NOLSE-O0-NEXT: uxth w8, w8 ; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB38_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB38_1
; CHECK-NOLSE-O0-NEXT: b LBB38_5 ; CHECK-NOLSE-O0-NEXT: b LBB38_5
; CHECK-NOLSE-O0-NEXT: LBB38_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB38_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_xchg_i16: ; CHECK-LSE-O1-LABEL: atomicrmw_xchg_i16:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: swph w1, w0, [x0] ; CHECK-LSE-O1-NEXT: swph w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomicrmw_xchg_i16: ; CHECK-LSE-O0-LABEL: atomicrmw_xchg_i16:
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; CHECK-NOLSE-O1-NEXT: stxrh w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stxrh w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB39_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB39_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_sub_i16: ; CHECK-NOLSE-O0-LABEL: atomicrmw_sub_i16:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB39_1 ; CHECK-NOLSE-O0-NEXT: b LBB39_1
; CHECK-NOLSE-O0-NEXT: LBB39_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB39_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
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; CHECK-NOLSE-O0-NEXT: uxth w8, w8 ; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB39_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB39_1
; CHECK-NOLSE-O0-NEXT: b LBB39_5 ; CHECK-NOLSE-O0-NEXT: b LBB39_5
; CHECK-NOLSE-O0-NEXT: LBB39_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB39_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_sub_i16: ; CHECK-LSE-O1-LABEL: atomicrmw_sub_i16:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: neg w8, w1 ; CHECK-LSE-O1-NEXT: neg w8, w1
; CHECK-LSE-O1-NEXT: ldaddah w8, w0, [x0] ; CHECK-LSE-O1-NEXT: ldaddah w8, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
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; CHECK-NOLSE-O1-NEXT: stlxrh w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stlxrh w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB40_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB40_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_and_i16: ; CHECK-NOLSE-O0-LABEL: atomicrmw_and_i16:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB40_1 ; CHECK-NOLSE-O0-NEXT: b LBB40_1
; CHECK-NOLSE-O0-NEXT: LBB40_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB40_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
Show All 18 Lines
; CHECK-NOLSE-O0-NEXT: uxth w8, w8 ; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB40_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB40_1
; CHECK-NOLSE-O0-NEXT: b LBB40_5 ; CHECK-NOLSE-O0-NEXT: b LBB40_5
; CHECK-NOLSE-O0-NEXT: LBB40_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB40_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_and_i16: ; CHECK-LSE-O1-LABEL: atomicrmw_and_i16:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: mvn w8, w1 ; CHECK-LSE-O1-NEXT: mvn w8, w1
; CHECK-LSE-O1-NEXT: ldclrlh w8, w0, [x0] ; CHECK-LSE-O1-NEXT: ldclrlh w8, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
Show All 16 Lines
; CHECK-NOLSE-O1-NEXT: stlxrh w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stlxrh w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB41_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB41_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_or_i16: ; CHECK-NOLSE-O0-LABEL: atomicrmw_or_i16:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB41_1 ; CHECK-NOLSE-O0-NEXT: b LBB41_1
; CHECK-NOLSE-O0-NEXT: LBB41_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB41_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
Show All 18 Lines
; CHECK-NOLSE-O0-NEXT: uxth w8, w8 ; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB41_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB41_1
; CHECK-NOLSE-O0-NEXT: b LBB41_5 ; CHECK-NOLSE-O0-NEXT: b LBB41_5
; CHECK-NOLSE-O0-NEXT: LBB41_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB41_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_or_i16: ; CHECK-LSE-O1-LABEL: atomicrmw_or_i16:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: ldsetalh w1, w0, [x0] ; CHECK-LSE-O1-NEXT: ldsetalh w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomicrmw_or_i16: ; CHECK-LSE-O0-LABEL: atomicrmw_or_i16:
Show All 14 Lines
; CHECK-NOLSE-O1-NEXT: stxrh w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stxrh w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB42_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB42_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_xor_i16: ; CHECK-NOLSE-O0-LABEL: atomicrmw_xor_i16:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB42_1 ; CHECK-NOLSE-O0-NEXT: b LBB42_1
; CHECK-NOLSE-O0-NEXT: LBB42_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB42_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
Show All 18 Lines
; CHECK-NOLSE-O0-NEXT: uxth w8, w8 ; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB42_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB42_1
; CHECK-NOLSE-O0-NEXT: b LBB42_5 ; CHECK-NOLSE-O0-NEXT: b LBB42_5
; CHECK-NOLSE-O0-NEXT: LBB42_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB42_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_xor_i16: ; CHECK-LSE-O1-LABEL: atomicrmw_xor_i16:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: ldeorh w1, w0, [x0] ; CHECK-LSE-O1-NEXT: ldeorh w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomicrmw_xor_i16: ; CHECK-LSE-O0-LABEL: atomicrmw_xor_i16:
Show All 16 Lines
; CHECK-NOLSE-O1-NEXT: stxrh w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stxrh w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB43_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB43_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_min_i16: ; CHECK-NOLSE-O0-LABEL: atomicrmw_min_i16:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB43_1 ; CHECK-NOLSE-O0-NEXT: b LBB43_1
; CHECK-NOLSE-O0-NEXT: LBB43_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB43_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
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; CHECK-NOLSE-O0-NEXT: uxth w8, w8 ; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB43_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB43_1
; CHECK-NOLSE-O0-NEXT: b LBB43_5 ; CHECK-NOLSE-O0-NEXT: b LBB43_5
; CHECK-NOLSE-O0-NEXT: LBB43_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB43_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_min_i16: ; CHECK-LSE-O1-LABEL: atomicrmw_min_i16:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: ldsminah w1, w0, [x0] ; CHECK-LSE-O1-NEXT: ldsminah w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomicrmw_min_i16: ; CHECK-LSE-O0-LABEL: atomicrmw_min_i16:
Show All 16 Lines
; CHECK-NOLSE-O1-NEXT: stlxrh w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stlxrh w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB44_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB44_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_max_i16: ; CHECK-NOLSE-O0-LABEL: atomicrmw_max_i16:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB44_1 ; CHECK-NOLSE-O0-NEXT: b LBB44_1
; CHECK-NOLSE-O0-NEXT: LBB44_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB44_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
Show All 21 Lines
; CHECK-NOLSE-O0-NEXT: uxth w8, w8 ; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB44_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB44_1
; CHECK-NOLSE-O0-NEXT: b LBB44_5 ; CHECK-NOLSE-O0-NEXT: b LBB44_5
; CHECK-NOLSE-O0-NEXT: LBB44_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB44_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_max_i16: ; CHECK-LSE-O1-LABEL: atomicrmw_max_i16:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: ldsmaxlh w1, w0, [x0] ; CHECK-LSE-O1-NEXT: ldsmaxlh w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomicrmw_max_i16: ; CHECK-LSE-O0-LABEL: atomicrmw_max_i16:
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; CHECK-NOLSE-O1-NEXT: stlxrh w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stlxrh w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB45_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB45_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_umin_i16: ; CHECK-NOLSE-O0-LABEL: atomicrmw_umin_i16:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB45_1 ; CHECK-NOLSE-O0-NEXT: b LBB45_1
; CHECK-NOLSE-O0-NEXT: LBB45_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB45_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
Show All 21 Lines
; CHECK-NOLSE-O0-NEXT: uxth w8, w8 ; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB45_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB45_1
; CHECK-NOLSE-O0-NEXT: b LBB45_5 ; CHECK-NOLSE-O0-NEXT: b LBB45_5
; CHECK-NOLSE-O0-NEXT: LBB45_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB45_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_umin_i16: ; CHECK-LSE-O1-LABEL: atomicrmw_umin_i16:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: lduminalh w1, w0, [x0] ; CHECK-LSE-O1-NEXT: lduminalh w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomicrmw_umin_i16: ; CHECK-LSE-O0-LABEL: atomicrmw_umin_i16:
Show All 16 Lines
; CHECK-NOLSE-O1-NEXT: stxrh w10, w9, [x0] ; CHECK-NOLSE-O1-NEXT: stxrh w10, w9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB46_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB46_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8 ; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: atomicrmw_umax_i16: ; CHECK-NOLSE-O0-LABEL: atomicrmw_umax_i16:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0] ; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB46_1 ; CHECK-NOLSE-O0-NEXT: b LBB46_1
; CHECK-NOLSE-O0-NEXT: LBB46_1: ; %atomicrmw.start ; CHECK-NOLSE-O0-NEXT: LBB46_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
Show All 21 Lines
; CHECK-NOLSE-O0-NEXT: uxth w8, w8 ; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth ; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq ; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill ; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB46_1 ; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB46_1
; CHECK-NOLSE-O0-NEXT: b LBB46_5 ; CHECK-NOLSE-O0-NEXT: b LBB46_5
; CHECK-NOLSE-O0-NEXT: LBB46_5: ; %atomicrmw.end ; CHECK-NOLSE-O0-NEXT: LBB46_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload ; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32 ; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret ; CHECK-NOLSE-O0-NEXT: ret
; ;
; CHECK-LSE-O1-LABEL: atomicrmw_umax_i16: ; CHECK-LSE-O1-LABEL: atomicrmw_umax_i16:
; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: ldumaxh w1, w0, [x0] ; CHECK-LSE-O1-NEXT: ldumaxh w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret ; CHECK-LSE-O1-NEXT: ret
; ;
; CHECK-LSE-O0-LABEL: atomicrmw_umax_i16: ; CHECK-LSE-O0-LABEL: atomicrmw_umax_i16:
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llvm/test/CodeGen/AArch64/GlobalISel/byval-call.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -global-isel -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
declare void @byval_i32(i32* byval(i32) %ptr) declare void @byval_i32(i32* byval(i32) %ptr)
define void @call_byval_i32(i32* %incoming) { define void @call_byval_i32(i32* %incoming) {
; CHECK-LABEL: call_byval_i32: ; CHECK-LABEL: call_byval_i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: ldr w8, [x0] ; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: str w8, [sp] ; CHECK-NEXT: str w8, [sp]
; CHECK-NEXT: bl byval_i32 ; CHECK-NEXT: bl byval_i32
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @byval_i32(i32* byval(i32) %incoming) call void @byval_i32(i32* byval(i32) %incoming)
ret void ret void
} }
declare void @byval_a64i32([64 x i32]* byval([64 x i32]) %ptr) declare void @byval_a64i32([64 x i32]* byval([64 x i32]) %ptr)
define void @call_byval_a64i32([64 x i32]* %incoming) { define void @call_byval_a64i32([64 x i32]* %incoming) {
; CHECK-LABEL: call_byval_a64i32: ; CHECK-LABEL: call_byval_a64i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #288 // =288 ; CHECK-NEXT: sub sp, sp, #288
; CHECK-NEXT: stp x29, x30, [sp, #256] // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #256] // 16-byte Folded Spill
; CHECK-NEXT: str x28, [sp, #272] // 8-byte Folded Spill ; CHECK-NEXT: str x28, [sp, #272] // 8-byte Folded Spill
; CHECK-NEXT: add x29, sp, #256 // =256 ; CHECK-NEXT: add x29, sp, #256
; CHECK-NEXT: .cfi_def_cfa w29, 32 ; CHECK-NEXT: .cfi_def_cfa w29, 32
; CHECK-NEXT: .cfi_offset w28, -16 ; CHECK-NEXT: .cfi_offset w28, -16
; CHECK-NEXT: .cfi_offset w30, -24 ; CHECK-NEXT: .cfi_offset w30, -24
; CHECK-NEXT: .cfi_offset w29, -32 ; CHECK-NEXT: .cfi_offset w29, -32
; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: str q0, [sp] ; CHECK-NEXT: str q0, [sp]
; CHECK-NEXT: ldr q0, [x0, #16] ; CHECK-NEXT: ldr q0, [x0, #16]
; CHECK-NEXT: str q0, [sp, #16] ; CHECK-NEXT: str q0, [sp, #16]
Show All 23 Lines
; CHECK-NEXT: str q0, [sp, #208] ; CHECK-NEXT: str q0, [sp, #208]
; CHECK-NEXT: ldr q0, [x0, #224] ; CHECK-NEXT: ldr q0, [x0, #224]
; CHECK-NEXT: str q0, [sp, #224] ; CHECK-NEXT: str q0, [sp, #224]
; CHECK-NEXT: ldr q0, [x0, #240] ; CHECK-NEXT: ldr q0, [x0, #240]
; CHECK-NEXT: str q0, [sp, #240] ; CHECK-NEXT: str q0, [sp, #240]
; CHECK-NEXT: bl byval_a64i32 ; CHECK-NEXT: bl byval_a64i32
; CHECK-NEXT: ldr x28, [sp, #272] // 8-byte Folded Reload ; CHECK-NEXT: ldr x28, [sp, #272] // 8-byte Folded Reload
; CHECK-NEXT: ldp x29, x30, [sp, #256] // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp, #256] // 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #288 // =288 ; CHECK-NEXT: add sp, sp, #288
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @byval_a64i32([64 x i32]* byval([64 x i32]) %incoming) call void @byval_a64i32([64 x i32]* byval([64 x i32]) %incoming)
ret void ret void
} }

llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll

Show All 24 Lines
; Test musttailing with a normal call in the block. Test that we spill and ; Test musttailing with a normal call in the block. Test that we spill and
; restore, as a normal call will clobber all argument registers. ; restore, as a normal call will clobber all argument registers.
@asdf = internal constant [4 x i8] c"asdf" @asdf = internal constant [4 x i8] c"asdf"
declare void @puts(i8*) declare void @puts(i8*)
define i32 @test_musttail_variadic_spill(i32 %arg0, ...) { define i32 @test_musttail_variadic_spill(i32 %arg0, ...) {
; CHECK-LABEL: test_musttail_variadic_spill: ; CHECK-LABEL: test_musttail_variadic_spill:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: sub sp, sp, #224 ; =224 ; CHECK-NEXT: sub sp, sp, #224
; CHECK-NEXT: stp x28, x27, [sp, #128] ; 16-byte Folded Spill ; CHECK-NEXT: stp x28, x27, [sp, #128] ; 16-byte Folded Spill
; CHECK-NEXT: stp x26, x25, [sp, #144] ; 16-byte Folded Spill ; CHECK-NEXT: stp x26, x25, [sp, #144] ; 16-byte Folded Spill
; CHECK-NEXT: stp x24, x23, [sp, #160] ; 16-byte Folded Spill ; CHECK-NEXT: stp x24, x23, [sp, #160] ; 16-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #176] ; 16-byte Folded Spill ; CHECK-NEXT: stp x22, x21, [sp, #176] ; 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #192] ; 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #192] ; 16-byte Folded Spill
; CHECK-NEXT: stp x29, x30, [sp, #208] ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #208] ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 224 ; CHECK-NEXT: .cfi_def_cfa_offset 224
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
Show All 40 Lines
; CHECK-NEXT: mov x7, x26 ; CHECK-NEXT: mov x7, x26
; CHECK-NEXT: mov x8, x27 ; CHECK-NEXT: mov x8, x27
; CHECK-NEXT: ldp x29, x30, [sp, #208] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp, #208] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x20, x19, [sp, #192] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #192] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #176] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #176] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x24, x23, [sp, #160] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x24, x23, [sp, #160] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x26, x25, [sp, #144] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x26, x25, [sp, #144] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x28, x27, [sp, #128] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x28, x27, [sp, #128] ; 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #224 ; =224 ; CHECK-NEXT: add sp, sp, #224
; CHECK-NEXT: b _musttail_variadic_callee ; CHECK-NEXT: b _musttail_variadic_callee
; CHECK-NEXT: .loh AdrpAdd Lloh0, Lloh1 ; CHECK-NEXT: .loh AdrpAdd Lloh0, Lloh1
call void @puts(i8* getelementptr ([4 x i8], [4 x i8]* @asdf, i32 0, i32 0)) call void @puts(i8* getelementptr ([4 x i8], [4 x i8]* @asdf, i32 0, i32 0))
%r = musttail call i32 (i32, ...) @musttail_variadic_callee(i32 %arg0, ...) %r = musttail call i32 (i32, ...) @musttail_variadic_callee(i32 %arg0, ...)
ret i32 %r ret i32 %r
} }
; Test musttailing with a varargs call in the block. Test that we spill and ; Test musttailing with a varargs call in the block. Test that we spill and
; reload all arguments in the variadic argument pack. ; reload all arguments in the variadic argument pack.
declare void @llvm.va_start(i8*) nounwind declare void @llvm.va_start(i8*) nounwind
declare void(i8*, ...)* @get_f(i8* %this) declare void(i8*, ...)* @get_f(i8* %this)
define void @f_thunk(i8* %this, ...) { define void @f_thunk(i8* %this, ...) {
; CHECK-LABEL: f_thunk: ; CHECK-LABEL: f_thunk:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: sub sp, sp, #256 ; =256 ; CHECK-NEXT: sub sp, sp, #256
; CHECK-NEXT: stp x28, x27, [sp, #160] ; 16-byte Folded Spill ; CHECK-NEXT: stp x28, x27, [sp, #160] ; 16-byte Folded Spill
; CHECK-NEXT: stp x26, x25, [sp, #176] ; 16-byte Folded Spill ; CHECK-NEXT: stp x26, x25, [sp, #176] ; 16-byte Folded Spill
; CHECK-NEXT: stp x24, x23, [sp, #192] ; 16-byte Folded Spill ; CHECK-NEXT: stp x24, x23, [sp, #192] ; 16-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #208] ; 16-byte Folded Spill ; CHECK-NEXT: stp x22, x21, [sp, #208] ; 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #224] ; 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #224] ; 16-byte Folded Spill
; CHECK-NEXT: stp x29, x30, [sp, #240] ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #240] ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 256 ; CHECK-NEXT: .cfi_def_cfa_offset 256
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: .cfi_offset w19, -24 ; CHECK-NEXT: .cfi_offset w19, -24
; CHECK-NEXT: .cfi_offset w20, -32 ; CHECK-NEXT: .cfi_offset w20, -32
; CHECK-NEXT: .cfi_offset w21, -40 ; CHECK-NEXT: .cfi_offset w21, -40
; CHECK-NEXT: .cfi_offset w22, -48 ; CHECK-NEXT: .cfi_offset w22, -48
; CHECK-NEXT: .cfi_offset w23, -56 ; CHECK-NEXT: .cfi_offset w23, -56
; CHECK-NEXT: .cfi_offset w24, -64 ; CHECK-NEXT: .cfi_offset w24, -64
; CHECK-NEXT: .cfi_offset w25, -72 ; CHECK-NEXT: .cfi_offset w25, -72
; CHECK-NEXT: .cfi_offset w26, -80 ; CHECK-NEXT: .cfi_offset w26, -80
; CHECK-NEXT: .cfi_offset w27, -88 ; CHECK-NEXT: .cfi_offset w27, -88
; CHECK-NEXT: .cfi_offset w28, -96 ; CHECK-NEXT: .cfi_offset w28, -96
; CHECK-NEXT: mov x27, x8 ; CHECK-NEXT: mov x27, x8
; CHECK-NEXT: add x8, sp, #128 ; =128 ; CHECK-NEXT: add x8, sp, #128
; CHECK-NEXT: add x9, sp, #256 ; =256 ; CHECK-NEXT: add x9, sp, #256
; CHECK-NEXT: mov x19, x0 ; CHECK-NEXT: mov x19, x0
; CHECK-NEXT: mov x20, x1 ; CHECK-NEXT: mov x20, x1
; CHECK-NEXT: mov x21, x2 ; CHECK-NEXT: mov x21, x2
; CHECK-NEXT: mov x22, x3 ; CHECK-NEXT: mov x22, x3
; CHECK-NEXT: mov x23, x4 ; CHECK-NEXT: mov x23, x4
; CHECK-NEXT: mov x24, x5 ; CHECK-NEXT: mov x24, x5
; CHECK-NEXT: mov x25, x6 ; CHECK-NEXT: mov x25, x6
; CHECK-NEXT: mov x26, x7 ; CHECK-NEXT: mov x26, x7
Show All 18 Lines
; CHECK-NEXT: mov x7, x26 ; CHECK-NEXT: mov x7, x26
; CHECK-NEXT: mov x8, x27 ; CHECK-NEXT: mov x8, x27
; CHECK-NEXT: ldp x29, x30, [sp, #240] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp, #240] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x20, x19, [sp, #224] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #224] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #208] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #208] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x24, x23, [sp, #192] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x24, x23, [sp, #192] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x26, x25, [sp, #176] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x26, x25, [sp, #176] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x28, x27, [sp, #160] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x28, x27, [sp, #160] ; 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #256 ; =256 ; CHECK-NEXT: add sp, sp, #256
; CHECK-NEXT: br x9 ; CHECK-NEXT: br x9
%ap = alloca [4 x i8*], align 16 %ap = alloca [4 x i8*], align 16
%ap_i8 = bitcast [4 x i8*]* %ap to i8* %ap_i8 = bitcast [4 x i8*]* %ap to i8*
call void @llvm.va_start(i8* %ap_i8) call void @llvm.va_start(i8* %ap_i8)
%fptr = call void(i8*, ...)*(i8*) @get_f(i8* %this) %fptr = call void(i8*, ...)*(i8*) @get_f(i8* %this)
musttail call void (i8*, ...) %fptr(i8* %this, ...) musttail call void (i8*, ...) %fptr(i8* %this, ...)
ret void ret void
} }
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llvm/test/CodeGen/AArch64/GlobalISel/freeze.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines; GISEL-NEXT: ret
%y1 = freeze <2 x i32> undef %y1 = freeze <2 x i32> undef
%t1 = add <2 x i32> %y1, %y1 %t1 = add <2 x i32> %y1, %y1
ret <2 x i32> %t1 ret <2 x i32> %t1
} }
define i8* @freeze_ptr() { define i8* @freeze_ptr() {
; CHECK-LABEL: freeze_ptr: ; CHECK-LABEL: freeze_ptr:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x0, x8, #4 // =4 ; CHECK-NEXT: add x0, x8, #4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: freeze_ptr: ; GISEL-LABEL: freeze_ptr:
; GISEL: // %bb.0: ; GISEL: // %bb.0:
; GISEL-NEXT: add x0, x8, #4 // =4 ; GISEL-NEXT: add x0, x8, #4
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%y1 = freeze i8* undef %y1 = freeze i8* undef
%t1 = getelementptr i8, i8* %y1, i64 4 %t1 = getelementptr i8, i8* %y1, i64 4
ret i8* %t1 ret i8* %t1
} }
define i32 @freeze_struct() { define i32 @freeze_struct() {
; CHECK-LABEL: freeze_struct: ; CHECK-LABEL: freeze_struct:
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llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll

Show First 20 Lines • Show All 148 Lines • ▼ Show 20 Linesentry:
%conv = fptosi double %d10 to i32 %conv = fptosi double %d10 to i32
%add = add nsw i32 %conv, %i10 %add = add nsw i32 %conv, %i10
%l1.0.l1.0. = load volatile i32, i32* %l1, align 4 %l1.0.l1.0. = load volatile i32, i32* %l1, align 4
%add1 = add nsw i32 %add, %l1.0.l1.0. %add1 = add nsw i32 %add, %l1.0.l1.0.
ret i32 %add1 ret i32 %add1
} }
; CHECK-LABEL: novla_nodynamicrealign_nocall ; CHECK-LABEL: novla_nodynamicrealign_nocall
; Check that space is reserved for one local variable on the stack. ; Check that space is reserved for one local variable on the stack.
; CHECK: sub sp, sp, #16 // =16 ; CHECK: sub sp, sp, #16
; Check correct access to arguments passed on the stack, through stack pointer ; Check correct access to arguments passed on the stack, through stack pointer
; CHECK: ldr d[[DARG:[0-9]+]], [sp, #40] ; CHECK: ldr d[[DARG:[0-9]+]], [sp, #40]
; CHECK: ldr w[[IARG:[0-9]+]], [sp, #24] ; CHECK: ldr w[[IARG:[0-9]+]], [sp, #24]
; Check correct access to local variable on the stack, through stack pointer ; Check correct access to local variable on the stack, through stack pointer
; CHECK: ldr w[[ILOC:[0-9]+]], [sp, #12] ; CHECK: ldr w[[ILOC:[0-9]+]], [sp, #12]
; Check epilogue: ; Check epilogue:
; CHECK: add sp, sp, #16 // =16 ; CHECK: add sp, sp, #16
; CHECK: ret ; CHECK: ret
define i32 @novla_dynamicrealign_call(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 { define i32 @novla_dynamicrealign_call(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 {
entry: entry:
%l1 = alloca i32, align 128 %l1 = alloca i32, align 128
%conv = fptosi double %d10 to i32 %conv = fptosi double %d10 to i32
%add = add nsw i32 %conv, %i10 %add = add nsw i32 %conv, %i10
▲ Show 20 Lines • Show All 216 Lines • ▼ Show 20 Lines
; CHECK: str x21, [sp, #16] ; CHECK: str x21, [sp, #16]
; CHECK: stp x20, x19, [sp, #32] ; CHECK: stp x20, x19, [sp, #32]
; Check that the frame pointer is created: ; Check that the frame pointer is created:
; CHECK: mov x29, sp ; CHECK: mov x29, sp
; Check that the stack pointer gets re-aligned to 128 ; Check that the stack pointer gets re-aligned to 128
; bytes & the base pointer (x19) gets initialized to ; bytes & the base pointer (x19) gets initialized to
; this 128-byte aligned area for local variables & ; this 128-byte aligned area for local variables &
; spill slots ; spill slots
; CHECK: sub x9, sp, #80 // =80 ; CHECK: sub x9, sp, #80
; CHECK: and sp, x9, #0xffffffffffffff80 ; CHECK: and sp, x9, #0xffffffffffffff80
; CHECK: mov x19, sp ; CHECK: mov x19, sp
; Check correctness of cfi pseudo-instructions ; Check correctness of cfi pseudo-instructions
; CHECK: .cfi_def_cfa w29, 48 ; CHECK: .cfi_def_cfa w29, 48
; CHECK: .cfi_offset w19, -8 ; CHECK: .cfi_offset w19, -8
; CHECK: .cfi_offset w20, -16 ; CHECK: .cfi_offset w20, -16
; CHECK: .cfi_offset w21, -32 ; CHECK: .cfi_offset w21, -32
; CHECK: .cfi_offset w30, -40 ; CHECK: .cfi_offset w30, -40
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bb1: bb1:
ret void ret void
} }
; CHECK-LABEL: realign_conditional2 ; CHECK-LABEL: realign_conditional2
; Extra realignment in the prologue (performance issue). ; Extra realignment in the prologue (performance issue).
; CHECK: tbz {{.*}} .[[LABEL:.*]] ; CHECK: tbz {{.*}} .[[LABEL:.*]]
; CHECK: sub x9, sp, #32 // =32 ; CHECK: sub x9, sp, #32
; CHECK: and sp, x9, #0xffffffffffffffe0 ; CHECK: and sp, x9, #0xffffffffffffffe0
; CHECK: mov x19, sp ; CHECK: mov x19, sp
; Stack is realigned in a non-entry BB. ; Stack is realigned in a non-entry BB.
; CHECK: sub [[REG:x[01-9]+]], sp, #64 ; CHECK: sub [[REG:x[01-9]+]], sp, #64
; CHECK: and sp, [[REG]], #0xffffffffffffffe0 ; CHECK: and sp, [[REG]], #0xffffffffffffffe0
; CHECK: .[[LABEL]]: ; CHECK: .[[LABEL]]:
; CHECK: ret ; CHECK: ret
attributes #0 = { "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0} !2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0} !3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"} !4 = !{!"Simple C/C++ TBAA"}

llvm/test/CodeGen/AArch64/aarch64-load-ext.ll

Show All 17 Lines; CHECK-BE-NEXT: ret
%v0 = insertelement <2 x i16> undef, i16 %i_0, i32 0 %v0 = insertelement <2 x i16> undef, i16 %i_0, i32 0
ret <2 x i16> %v0 ret <2 x i16> %v0
} }
define <2 x i16> @test1(<2 x i16>* %v2i16_ptr) { define <2 x i16> @test1(<2 x i16>* %v2i16_ptr) {
; CHECK-LE-LABEL: test1: ; CHECK-LE-LABEL: test1:
; CHECK-LE: // %bb.0: ; CHECK-LE: // %bb.0:
; CHECK-LE-NEXT: ld1 { v0.h }[0], [x0] ; CHECK-LE-NEXT: ld1 { v0.h }[0], [x0]
; CHECK-LE-NEXT: add x8, x0, #2 // =2 ; CHECK-LE-NEXT: add x8, x0, #2
; CHECK-LE-NEXT: ld1 { v0.h }[2], [x8] ; CHECK-LE-NEXT: ld1 { v0.h }[2], [x8]
; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-LE-NEXT: ret ; CHECK-LE-NEXT: ret
; ;
; CHECK-BE-LABEL: test1: ; CHECK-BE-LABEL: test1:
; CHECK-BE: // %bb.0: ; CHECK-BE: // %bb.0:
; CHECK-BE-NEXT: ld1 { v0.h }[0], [x0] ; CHECK-BE-NEXT: ld1 { v0.h }[0], [x0]
; CHECK-BE-NEXT: add x8, x0, #2 // =2 ; CHECK-BE-NEXT: add x8, x0, #2
; CHECK-BE-NEXT: ld1 { v0.h }[2], [x8] ; CHECK-BE-NEXT: ld1 { v0.h }[2], [x8]
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s ; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
%v2i16 = load <2 x i16>, <2 x i16>* %v2i16_ptr %v2i16 = load <2 x i16>, <2 x i16>* %v2i16_ptr
ret <2 x i16> %v2i16 ret <2 x i16> %v2i16
} }
define <2 x i16> @test2(i16* %i16_ptr, i64 %inc) { define <2 x i16> @test2(i16* %i16_ptr, i64 %inc) {
Show All 19 Lines; CHECK-BE-NEXT: ret
%v1 = insertelement <2 x i16> %v0, i16 %i_1, i32 1 %v1 = insertelement <2 x i16> %v0, i16 %i_1, i32 1
ret <2 x i16> %v1 ret <2 x i16> %v1
} }
define <2 x i8> @test3(<2 x i8>* %v2i8_ptr) { define <2 x i8> @test3(<2 x i8>* %v2i8_ptr) {
; CHECK-LE-LABEL: test3: ; CHECK-LE-LABEL: test3:
; CHECK-LE: // %bb.0: ; CHECK-LE: // %bb.0:
; CHECK-LE-NEXT: ld1 { v0.b }[0], [x0] ; CHECK-LE-NEXT: ld1 { v0.b }[0], [x0]
; CHECK-LE-NEXT: add x8, x0, #1 // =1 ; CHECK-LE-NEXT: add x8, x0, #1
; CHECK-LE-NEXT: ld1 { v0.b }[4], [x8] ; CHECK-LE-NEXT: ld1 { v0.b }[4], [x8]
; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-LE-NEXT: ret ; CHECK-LE-NEXT: ret
; ;
; CHECK-BE-LABEL: test3: ; CHECK-BE-LABEL: test3:
; CHECK-BE: // %bb.0: ; CHECK-BE: // %bb.0:
; CHECK-BE-NEXT: ld1 { v0.b }[0], [x0] ; CHECK-BE-NEXT: ld1 { v0.b }[0], [x0]
; CHECK-BE-NEXT: add x8, x0, #1 // =1 ; CHECK-BE-NEXT: add x8, x0, #1
; CHECK-BE-NEXT: ld1 { v0.b }[4], [x8] ; CHECK-BE-NEXT: ld1 { v0.b }[4], [x8]
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s ; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
%v2i8 = load <2 x i8>, <2 x i8>* %v2i8_ptr %v2i8 = load <2 x i8>, <2 x i8>* %v2i8_ptr
ret <2 x i8> %v2i8 ret <2 x i8> %v2i8
} }
define <4 x i8> @test4(<4 x i8>* %v4i8_ptr) { define <4 x i8> @test4(<4 x i8>* %v4i8_ptr) {
▲ Show 20 Lines • Show All 354 Lines • ▼ Show 20 Lines; CHECK-BE-NEXT: ret
%z = add <4 x i8> %x, %y %z = add <4 x i8> %x, %y
%s = sext <4 x i8> %z to <4 x i32> %s = sext <4 x i8> %z to <4 x i32>
ret <4 x i32> %s ret <4 x i32> %s
} }
define <4 x i8> @bitcast(i32 %0) { define <4 x i8> @bitcast(i32 %0) {
; CHECK-LE-LABEL: bitcast: ; CHECK-LE-LABEL: bitcast:
; CHECK-LE: // %bb.0: ; CHECK-LE: // %bb.0:
; CHECK-LE-NEXT: sub sp, sp, #16 // =16 ; CHECK-LE-NEXT: sub sp, sp, #16
; CHECK-LE-NEXT: .cfi_def_cfa_offset 16 ; CHECK-LE-NEXT: .cfi_def_cfa_offset 16
; CHECK-LE-NEXT: str w0, [sp, #12] ; CHECK-LE-NEXT: str w0, [sp, #12]
; CHECK-LE-NEXT: ldr s0, [sp, #12] ; CHECK-LE-NEXT: ldr s0, [sp, #12]
; CHECK-LE-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-LE-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-LE-NEXT: add sp, sp, #16 // =16 ; CHECK-LE-NEXT: add sp, sp, #16
; CHECK-LE-NEXT: ret ; CHECK-LE-NEXT: ret
; ;
; CHECK-BE-LABEL: bitcast: ; CHECK-BE-LABEL: bitcast:
; CHECK-BE: // %bb.0: ; CHECK-BE: // %bb.0:
; CHECK-BE-NEXT: sub sp, sp, #16 // =16 ; CHECK-BE-NEXT: sub sp, sp, #16
; CHECK-BE-NEXT: .cfi_def_cfa_offset 16 ; CHECK-BE-NEXT: .cfi_def_cfa_offset 16
; CHECK-BE-NEXT: str w0, [sp, #12] ; CHECK-BE-NEXT: str w0, [sp, #12]
; CHECK-BE-NEXT: ldr s0, [sp, #12] ; CHECK-BE-NEXT: ldr s0, [sp, #12]
; CHECK-BE-NEXT: rev32 v0.8b, v0.8b ; CHECK-BE-NEXT: rev32 v0.8b, v0.8b
; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-BE-NEXT: rev64 v0.4h, v0.4h ; CHECK-BE-NEXT: rev64 v0.4h, v0.4h
; CHECK-BE-NEXT: add sp, sp, #16 // =16 ; CHECK-BE-NEXT: add sp, sp, #16
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
%2 = bitcast i32 %0 to <4 x i8> %2 = bitcast i32 %0 to <4 x i8>
ret <4 x i8> %2 ret <4 x i8> %2
} }

llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -o -| FileCheck %s ; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -o -| FileCheck %s
define void @matrix_mul_unsigned(i32 %N, i32* nocapture %C, i16* nocapture readonly %A, i16 %val) { define void @matrix_mul_unsigned(i32 %N, i32* nocapture %C, i16* nocapture readonly %A, i16 %val) {
; CHECK-LABEL: matrix_mul_unsigned: ; CHECK-LABEL: matrix_mul_unsigned:
; CHECK: // %bb.0: // %vector.header ; CHECK: // %bb.0: // %vector.header
; CHECK-NEXT: and w9, w3, #0xffff ; CHECK-NEXT: and w9, w3, #0xffff
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 ; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: and x8, x0, #0xfffffff8 ; CHECK-NEXT: and x8, x0, #0xfffffff8
; CHECK-NEXT: dup v0.4h, w9 ; CHECK-NEXT: dup v0.4h, w9
; CHECK-NEXT: .LBB0_1: // %vector.body ; CHECK-NEXT: .LBB0_1: // %vector.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: add x9, x2, w0, uxtw #1 ; CHECK-NEXT: add x9, x2, w0, uxtw #1
; CHECK-NEXT: ldp d1, d2, [x9] ; CHECK-NEXT: ldp d1, d2, [x9]
; CHECK-NEXT: add x9, x1, w0, uxtw #2 ; CHECK-NEXT: add x9, x1, w0, uxtw #2
; CHECK-NEXT: subs x8, x8, #8 // =8 ; CHECK-NEXT: subs x8, x8, #8
; CHECK-NEXT: add w0, w0, #8 // =8 ; CHECK-NEXT: add w0, w0, #8
; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h ; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h
; CHECK-NEXT: umull v2.4s, v0.4h, v2.4h ; CHECK-NEXT: umull v2.4s, v0.4h, v2.4h
; CHECK-NEXT: stp q1, q2, [x9] ; CHECK-NEXT: stp q1, q2, [x9]
; CHECK-NEXT: b.ne .LBB0_1 ; CHECK-NEXT: b.ne .LBB0_1
; CHECK-NEXT: // %bb.2: // %for.end12 ; CHECK-NEXT: // %bb.2: // %for.end12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
vector.header: vector.header:
%conv4 = zext i16 %val to i32 %conv4 = zext i16 %val to i32
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 ; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: and x8, x0, #0xfffffff8 ; CHECK-NEXT: and x8, x0, #0xfffffff8
; CHECK-NEXT: dup v0.4h, w9 ; CHECK-NEXT: dup v0.4h, w9
; CHECK-NEXT: .LBB1_1: // %vector.body ; CHECK-NEXT: .LBB1_1: // %vector.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: add x9, x2, w0, sxtw #1 ; CHECK-NEXT: add x9, x2, w0, sxtw #1
; CHECK-NEXT: ldp d1, d2, [x9] ; CHECK-NEXT: ldp d1, d2, [x9]
; CHECK-NEXT: add x9, x1, w0, sxtw #2 ; CHECK-NEXT: add x9, x1, w0, sxtw #2
; CHECK-NEXT: subs x8, x8, #8 // =8 ; CHECK-NEXT: subs x8, x8, #8
; CHECK-NEXT: add w0, w0, #8 // =8 ; CHECK-NEXT: add w0, w0, #8
; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h ; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-NEXT: smull v2.4s, v0.4h, v2.4h ; CHECK-NEXT: smull v2.4s, v0.4h, v2.4h
; CHECK-NEXT: stp q1, q2, [x9] ; CHECK-NEXT: stp q1, q2, [x9]
; CHECK-NEXT: b.ne .LBB1_1 ; CHECK-NEXT: b.ne .LBB1_1
; CHECK-NEXT: // %bb.2: // %for.end12 ; CHECK-NEXT: // %bb.2: // %for.end12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
vector.header: vector.header:
%conv4 = sext i16 %val to i32 %conv4 = sext i16 %val to i32
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; CHECK-NEXT: and w9, w3, #0xffff ; CHECK-NEXT: and w9, w3, #0xffff
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 ; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: and x8, x0, #0xfffffff8 ; CHECK-NEXT: and x8, x0, #0xfffffff8
; CHECK-NEXT: dup v0.4h, w9 ; CHECK-NEXT: dup v0.4h, w9
; CHECK-NEXT: .LBB2_1: // %vector.body ; CHECK-NEXT: .LBB2_1: // %vector.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrh w9, [x2], #16 ; CHECK-NEXT: ldrh w9, [x2], #16
; CHECK-NEXT: mov w10, w0 ; CHECK-NEXT: mov w10, w0
; CHECK-NEXT: subs x8, x8, #8 // =8 ; CHECK-NEXT: subs x8, x8, #8
; CHECK-NEXT: lsl x10, x10, #2 ; CHECK-NEXT: lsl x10, x10, #2
; CHECK-NEXT: dup v1.4h, w9 ; CHECK-NEXT: dup v1.4h, w9
; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h ; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h
; CHECK-NEXT: add w0, w0, #8 // =8 ; CHECK-NEXT: add w0, w0, #8
; CHECK-NEXT: str q1, [x1, x10] ; CHECK-NEXT: str q1, [x1, x10]
; CHECK-NEXT: b.ne .LBB2_1 ; CHECK-NEXT: b.ne .LBB2_1
; CHECK-NEXT: // %bb.2: // %for.end12 ; CHECK-NEXT: // %bb.2: // %for.end12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
vector.header: vector.header:
%conv4 = zext i16 %val to i32 %conv4 = zext i16 %val to i32
%wide.trip.count = zext i32 %N to i64 %wide.trip.count = zext i32 %N to i64
%0 = add nsw i64 %wide.trip.count, -1 %0 = add nsw i64 %wide.trip.count, -1
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llvm/test/CodeGen/AArch64/aarch64-tail-dup-size.ll

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; CHECK-O2-NEXT: str x9, [x0] ; CHECK-O2-NEXT: str x9, [x0]
; CHECK-O2-NEXT: ldr x8, [x8, :lo12:global_ptr] ; CHECK-O2-NEXT: ldr x8, [x8, :lo12:global_ptr]
; CHECK-O2-NEXT: b .LBB0_3 ; CHECK-O2-NEXT: b .LBB0_3
; CHECK-O2-NEXT: .LBB0_2: ; CHECK-O2-NEXT: .LBB0_2:
; CHECK-O2-NEXT: mov x8, xzr ; CHECK-O2-NEXT: mov x8, xzr
; CHECK-O2-NEXT: .LBB0_3: // %if.end ; CHECK-O2-NEXT: .LBB0_3: // %if.end
; CHECK-O2-NEXT: adrp x9, global_int ; CHECK-O2-NEXT: adrp x9, global_int
; CHECK-O2-NEXT: ldr w1, [x9, :lo12:global_int] ; CHECK-O2-NEXT: ldr w1, [x9, :lo12:global_int]
; CHECK-O2-NEXT: add x2, x8, #16 // =16 ; CHECK-O2-NEXT: add x2, x8, #16
; CHECK-O2-NEXT: mov w0, #10 ; CHECK-O2-NEXT: mov w0, #10
; CHECK-O2-NEXT: b externalfunc ; CHECK-O2-NEXT: b externalfunc
; ;
; CHECK-O3-LABEL: testcase: ; CHECK-O3-LABEL: testcase:
; CHECK-O3: // %bb.0: // %entry ; CHECK-O3: // %bb.0: // %entry
; CHECK-O3-NEXT: adrp x8, global_ptr ; CHECK-O3-NEXT: adrp x8, global_ptr
; CHECK-O3-NEXT: ldr x9, [x8, :lo12:global_ptr] ; CHECK-O3-NEXT: ldr x9, [x8, :lo12:global_ptr]
; CHECK-O3-NEXT: cbz x9, .LBB0_2 ; CHECK-O3-NEXT: cbz x9, .LBB0_2
; CHECK-O3-NEXT: // %bb.1: // %if.then ; CHECK-O3-NEXT: // %bb.1: // %if.then
; CHECK-O3-NEXT: ldr x9, [x9] ; CHECK-O3-NEXT: ldr x9, [x9]
; CHECK-O3-NEXT: str x9, [x0] ; CHECK-O3-NEXT: str x9, [x0]
; CHECK-O3-NEXT: ldr x8, [x8, :lo12:global_ptr] ; CHECK-O3-NEXT: ldr x8, [x8, :lo12:global_ptr]
; CHECK-O3-NEXT: adrp x9, global_int ; CHECK-O3-NEXT: adrp x9, global_int
; CHECK-O3-NEXT: ldr w1, [x9, :lo12:global_int] ; CHECK-O3-NEXT: ldr w1, [x9, :lo12:global_int]
; CHECK-O3-NEXT: add x2, x8, #16 // =16 ; CHECK-O3-NEXT: add x2, x8, #16
; CHECK-O3-NEXT: mov w0, #10 ; CHECK-O3-NEXT: mov w0, #10
; CHECK-O3-NEXT: b externalfunc ; CHECK-O3-NEXT: b externalfunc
; CHECK-O3-NEXT: .LBB0_2: ; CHECK-O3-NEXT: .LBB0_2:
; CHECK-O3-NEXT: mov x8, xzr ; CHECK-O3-NEXT: mov x8, xzr
; CHECK-O3-NEXT: adrp x9, global_int ; CHECK-O3-NEXT: adrp x9, global_int
; CHECK-O3-NEXT: ldr w1, [x9, :lo12:global_int] ; CHECK-O3-NEXT: ldr w1, [x9, :lo12:global_int]
; CHECK-O3-NEXT: add x2, x8, #16 // =16 ; CHECK-O3-NEXT: add x2, x8, #16
; CHECK-O3-NEXT: mov w0, #10 ; CHECK-O3-NEXT: mov w0, #10
; CHECK-O3-NEXT: b externalfunc ; CHECK-O3-NEXT: b externalfunc
entry: entry:
%0 = load %a*, %a** @global_ptr, align 8 %0 = load %a*, %a** @global_ptr, align 8
%cmp.not = icmp eq %a* %0, null %cmp.not = icmp eq %a* %0, null
br i1 %cmp.not, label %if.end, label %if.then br i1 %cmp.not, label %if.end, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
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llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
define win64cc void @pass_va(i32 %count, ...) nounwind { define win64cc void @pass_va(i32 %count, ...) nounwind {
; CHECK-LABEL: pass_va: ; CHECK-LABEL: pass_va:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #96 // =96 ; CHECK-NEXT: sub sp, sp, #96
; CHECK-NEXT: add x8, sp, #40 // =40 ; CHECK-NEXT: add x8, sp, #40
; CHECK-NEXT: add x0, sp, #40 // =40 ; CHECK-NEXT: add x0, sp, #40
; CHECK-NEXT: stp x30, x18, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x18, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: stp x1, x2, [sp, #40] ; CHECK-NEXT: stp x1, x2, [sp, #40]
; CHECK-NEXT: stp x3, x4, [sp, #56] ; CHECK-NEXT: stp x3, x4, [sp, #56]
; CHECK-NEXT: stp x5, x6, [sp, #72] ; CHECK-NEXT: stp x5, x6, [sp, #72]
; CHECK-NEXT: str x7, [sp, #88] ; CHECK-NEXT: str x7, [sp, #88]
; CHECK-NEXT: str x8, [sp, #8] ; CHECK-NEXT: str x8, [sp, #8]
; CHECK-NEXT: bl other_func ; CHECK-NEXT: bl other_func
; CHECK-NEXT: ldp x30, x18, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x18, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #96 // =96 ; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%ap1 = bitcast i8** %ap to i8* %ap1 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap1) call void @llvm.va_start(i8* %ap1)
%ap2 = load i8*, i8** %ap, align 8 %ap2 = load i8*, i8** %ap, align 8
call void @other_func(i8* %ap2) call void @other_func(i8* %ap2)
ret void ret void
} }
declare void @other_func(i8*) local_unnamed_addr declare void @other_func(i8*) local_unnamed_addr
declare void @llvm.va_start(i8*) nounwind declare void @llvm.va_start(i8*) nounwind
declare void @llvm.va_copy(i8*, i8*) nounwind declare void @llvm.va_copy(i8*, i8*) nounwind
define win64cc i8* @f9(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, i64 %a7, i64 %a8, ...) nounwind { define win64cc i8* @f9(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, i64 %a7, i64 %a8, ...) nounwind {
; CHECK-LABEL: f9: ; CHECK-LABEL: f9:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x18, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x18, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: add x8, sp, #24 // =24 ; CHECK-NEXT: add x8, sp, #24
; CHECK-NEXT: add x0, sp, #24 // =24 ; CHECK-NEXT: add x0, sp, #24
; CHECK-NEXT: str x8, [sp, #8] ; CHECK-NEXT: str x8, [sp, #8]
; CHECK-NEXT: ldr x18, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x18, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%ap1 = bitcast i8** %ap to i8* %ap1 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap1) call void @llvm.va_start(i8* %ap1)
%ap2 = load i8*, i8** %ap, align 8 %ap2 = load i8*, i8** %ap, align 8
ret i8* %ap2 ret i8* %ap2
} }
define win64cc i8* @f8(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, i64 %a7, ...) nounwind { define win64cc i8* @f8(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, i64 %a7, ...) nounwind {
; CHECK-LABEL: f8: ; CHECK-LABEL: f8:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x18, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x18, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: add x8, sp, #16 // =16 ; CHECK-NEXT: add x8, sp, #16
; CHECK-NEXT: add x0, sp, #16 // =16 ; CHECK-NEXT: add x0, sp, #16
; CHECK-NEXT: str x8, [sp, #8] ; CHECK-NEXT: str x8, [sp, #8]
; CHECK-NEXT: ldr x18, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x18, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%ap1 = bitcast i8** %ap to i8* %ap1 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap1) call void @llvm.va_start(i8* %ap1)
%ap2 = load i8*, i8** %ap, align 8 %ap2 = load i8*, i8** %ap, align 8
ret i8* %ap2 ret i8* %ap2
} }
define win64cc i8* @f7(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, ...) nounwind { define win64cc i8* @f7(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, ...) nounwind {
; CHECK-LABEL: f7: ; CHECK-LABEL: f7:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x18, [sp, #-32]! // 8-byte Folded Spill ; CHECK-NEXT: str x18, [sp, #-32]! // 8-byte Folded Spill
; CHECK-NEXT: add x8, sp, #24 // =24 ; CHECK-NEXT: add x8, sp, #24
; CHECK-NEXT: str x7, [sp, #24] ; CHECK-NEXT: str x7, [sp, #24]
; CHECK-NEXT: add x0, sp, #24 // =24 ; CHECK-NEXT: add x0, sp, #24
; CHECK-NEXT: str x8, [sp, #8] ; CHECK-NEXT: str x8, [sp, #8]
; CHECK-NEXT: ldr x18, [sp], #32 // 8-byte Folded Reload ; CHECK-NEXT: ldr x18, [sp], #32 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%ap1 = bitcast i8** %ap to i8* %ap1 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap1) call void @llvm.va_start(i8* %ap1)
%ap2 = load i8*, i8** %ap, align 8 %ap2 = load i8*, i8** %ap, align 8
ret i8* %ap2 ret i8* %ap2
} }

llvm/test/CodeGen/AArch64/addsub-constant-folding.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
declare void @use(i32 %arg) declare void @use(i32 %arg)
declare void @vec_use(<4 x i32> %arg) declare void @vec_use(<4 x i32> %arg)
; (x+c1)+c2 ; (x+c1)+c2
define i32 @add_const_add_const(i32 %arg) { define i32 @add_const_add_const(i32 %arg) {
; CHECK-LABEL: add_const_add_const: ; CHECK-LABEL: add_const_add_const:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w0, w0, #10 // =10 ; CHECK-NEXT: add w0, w0, #10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add i32 %arg, 8 %t0 = add i32 %arg, 8
%t1 = add i32 %t0, 2 %t1 = add i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define i32 @add_const_add_const_extrause(i32 %arg) { define i32 @add_const_add_const_extrause(i32 %arg) {
; CHECK-LABEL: add_const_add_const_extrause: ; CHECK-LABEL: add_const_add_const_extrause:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: add w0, w0, #8 // =8 ; CHECK-NEXT: add w0, w0, #8
; CHECK-NEXT: bl use ; CHECK-NEXT: bl use
; CHECK-NEXT: add w0, w19, #10 // =10 ; CHECK-NEXT: add w0, w19, #10
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add i32 %arg, 8 %t0 = add i32 %arg, 8
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = add i32 %t0, 2 %t1 = add i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_add_const_add_const(<4 x i32> %arg) { define <4 x i32> @vec_add_const_add_const(<4 x i32> %arg) {
; CHECK-LABEL: vec_add_const_add_const: ; CHECK-LABEL: vec_add_const_add_const:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #10 ; CHECK-NEXT: movi v1.4s, #10
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
%t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_add_const_add_const_extrause(<4 x i32> %arg) { define <4 x i32> @vec_add_const_add_const_extrause(<4 x i32> %arg) {
; CHECK-LABEL: vec_add_const_add_const_extrause: ; CHECK-LABEL: vec_add_const_add_const_extrause:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #10 ; CHECK-NEXT: movi v0.4s, #10
; CHECK-NEXT: add v0.4s, v1.4s, v0.4s ; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_add_const_add_const_nonsplat(<4 x i32> %arg) { define <4 x i32> @vec_add_const_add_const_nonsplat(<4 x i32> %arg) {
; CHECK-LABEL: vec_add_const_add_const_nonsplat: ; CHECK-LABEL: vec_add_const_add_const_nonsplat:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI4_0 ; CHECK-NEXT: adrp x8, .LCPI4_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>
%t1 = add <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
; (x+c1)-c2 ; (x+c1)-c2
define i32 @add_const_sub_const(i32 %arg) { define i32 @add_const_sub_const(i32 %arg) {
; CHECK-LABEL: add_const_sub_const: ; CHECK-LABEL: add_const_sub_const:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w0, w0, #6 // =6 ; CHECK-NEXT: add w0, w0, #6
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add i32 %arg, 8 %t0 = add i32 %arg, 8
%t1 = sub i32 %t0, 2 %t1 = sub i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define i32 @add_const_sub_const_extrause(i32 %arg) { define i32 @add_const_sub_const_extrause(i32 %arg) {
; CHECK-LABEL: add_const_sub_const_extrause: ; CHECK-LABEL: add_const_sub_const_extrause:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: add w0, w0, #8 // =8 ; CHECK-NEXT: add w0, w0, #8
; CHECK-NEXT: bl use ; CHECK-NEXT: bl use
; CHECK-NEXT: add w0, w19, #6 // =6 ; CHECK-NEXT: add w0, w19, #6
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add i32 %arg, 8 %t0 = add i32 %arg, 8
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = sub i32 %t0, 2 %t1 = sub i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_add_const_sub_const(<4 x i32> %arg) { define <4 x i32> @vec_add_const_sub_const(<4 x i32> %arg) {
; CHECK-LABEL: vec_add_const_sub_const: ; CHECK-LABEL: vec_add_const_sub_const:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #6 ; CHECK-NEXT: movi v1.4s, #6
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_add_const_sub_const_extrause(<4 x i32> %arg) { define <4 x i32> @vec_add_const_sub_const_extrause(<4 x i32> %arg) {
; CHECK-LABEL: vec_add_const_sub_const_extrause: ; CHECK-LABEL: vec_add_const_sub_const_extrause:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #6 ; CHECK-NEXT: movi v0.4s, #6
; CHECK-NEXT: add v0.4s, v1.4s, v0.4s ; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_add_const_sub_const_nonsplat(<4 x i32> %arg) { define <4 x i32> @vec_add_const_sub_const_nonsplat(<4 x i32> %arg) {
Show All 24 Lines
define i32 @add_const_const_sub_extrause(i32 %arg) { define i32 @add_const_const_sub_extrause(i32 %arg) {
; CHECK-LABEL: add_const_const_sub_extrause: ; CHECK-LABEL: add_const_const_sub_extrause:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: add w0, w0, #8 // =8 ; CHECK-NEXT: add w0, w0, #8
; CHECK-NEXT: bl use ; CHECK-NEXT: bl use
; CHECK-NEXT: mov w8, #-6 ; CHECK-NEXT: mov w8, #-6
; CHECK-NEXT: sub w0, w8, w19 ; CHECK-NEXT: sub w0, w8, w19
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add i32 %arg, 8 %t0 = add i32 %arg, 8
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = sub i32 2, %t0 %t1 = sub i32 2, %t0
Show All 9 Lines; CHECK-NEXT: ret
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
%t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_add_const_const_sub_extrause(<4 x i32> %arg) { define <4 x i32> @vec_add_const_const_sub_extrause(<4 x i32> %arg) {
; CHECK-LABEL: vec_add_const_const_sub_extrause: ; CHECK-LABEL: vec_add_const_const_sub_extrause:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: mvni v0.4s, #5 ; CHECK-NEXT: mvni v0.4s, #5
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_add_const_const_sub_nonsplat(<4 x i32> %arg) { define <4 x i32> @vec_add_const_const_sub_nonsplat(<4 x i32> %arg) {
; CHECK-LABEL: vec_add_const_const_sub_nonsplat: ; CHECK-LABEL: vec_add_const_const_sub_nonsplat:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI14_0 ; CHECK-NEXT: adrp x8, .LCPI14_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>
%t1 = sub <4 x i32> <i32 2, i32 3, i32 undef, i32 2>, %t0 %t1 = sub <4 x i32> <i32 2, i32 3, i32 undef, i32 2>, %t0
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
; (x-c1)+c2 ; (x-c1)+c2
define i32 @sub_const_add_const(i32 %arg) { define i32 @sub_const_add_const(i32 %arg) {
; CHECK-LABEL: sub_const_add_const: ; CHECK-LABEL: sub_const_add_const:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub w0, w0, #6 // =6 ; CHECK-NEXT: sub w0, w0, #6
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 %arg, 8 %t0 = sub i32 %arg, 8
%t1 = add i32 %t0, 2 %t1 = add i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define i32 @sub_const_add_const_extrause(i32 %arg) { define i32 @sub_const_add_const_extrause(i32 %arg) {
; CHECK-LABEL: sub_const_add_const_extrause: ; CHECK-LABEL: sub_const_add_const_extrause:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: sub w0, w0, #8 // =8 ; CHECK-NEXT: sub w0, w0, #8
; CHECK-NEXT: bl use ; CHECK-NEXT: bl use
; CHECK-NEXT: sub w0, w19, #6 // =6 ; CHECK-NEXT: sub w0, w19, #6
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 %arg, 8 %t0 = sub i32 %arg, 8
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = add i32 %t0, 2 %t1 = add i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_sub_const_add_const(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_add_const(<4 x i32> %arg) {
; CHECK-LABEL: vec_sub_const_add_const: ; CHECK-LABEL: vec_sub_const_add_const:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mvni v1.4s, #5 ; CHECK-NEXT: mvni v1.4s, #5
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
%t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_sub_const_add_const_extrause(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_add_const_extrause(<4 x i32> %arg) {
; CHECK-LABEL: vec_sub_const_add_const_extrause: ; CHECK-LABEL: vec_sub_const_add_const_extrause:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: mvni v0.4s, #5 ; CHECK-NEXT: mvni v0.4s, #5
; CHECK-NEXT: add v0.4s, v1.4s, v0.4s ; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_sub_const_add_const_nonsplat(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_add_const_nonsplat(<4 x i32> %arg) {
; CHECK-LABEL: vec_sub_const_add_const_nonsplat: ; CHECK-LABEL: vec_sub_const_add_const_nonsplat:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI19_0 ; CHECK-NEXT: adrp x8, .LCPI19_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI19_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI19_0]
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8> %t0 = sub <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>
%t1 = add <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
; (x-c1)-c2 ; (x-c1)-c2
define i32 @sub_const_sub_const(i32 %arg) { define i32 @sub_const_sub_const(i32 %arg) {
; CHECK-LABEL: sub_const_sub_const: ; CHECK-LABEL: sub_const_sub_const:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub w0, w0, #10 // =10 ; CHECK-NEXT: sub w0, w0, #10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 %arg, 8 %t0 = sub i32 %arg, 8
%t1 = sub i32 %t0, 2 %t1 = sub i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define i32 @sub_const_sub_const_extrause(i32 %arg) { define i32 @sub_const_sub_const_extrause(i32 %arg) {
; CHECK-LABEL: sub_const_sub_const_extrause: ; CHECK-LABEL: sub_const_sub_const_extrause:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: sub w0, w0, #8 // =8 ; CHECK-NEXT: sub w0, w0, #8
; CHECK-NEXT: bl use ; CHECK-NEXT: bl use
; CHECK-NEXT: sub w0, w19, #10 // =10 ; CHECK-NEXT: sub w0, w19, #10
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 %arg, 8 %t0 = sub i32 %arg, 8
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = sub i32 %t0, 2 %t1 = sub i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_sub_const_sub_const(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_sub_const(<4 x i32> %arg) {
; CHECK-LABEL: vec_sub_const_sub_const: ; CHECK-LABEL: vec_sub_const_sub_const:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #10 ; CHECK-NEXT: movi v1.4s, #10
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_sub_const_sub_const_extrause(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_sub_const_extrause(<4 x i32> %arg) {
; CHECK-LABEL: vec_sub_const_sub_const_extrause: ; CHECK-LABEL: vec_sub_const_sub_const_extrause:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #10 ; CHECK-NEXT: movi v0.4s, #10
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_sub_const_sub_const_nonsplat(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_sub_const_nonsplat(<4 x i32> %arg) {
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define i32 @sub_const_const_sub_extrause(i32 %arg) { define i32 @sub_const_const_sub_extrause(i32 %arg) {
; CHECK-LABEL: sub_const_const_sub_extrause: ; CHECK-LABEL: sub_const_const_sub_extrause:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: sub w0, w0, #8 // =8 ; CHECK-NEXT: sub w0, w0, #8
; CHECK-NEXT: bl use ; CHECK-NEXT: bl use
; CHECK-NEXT: mov w8, #10 ; CHECK-NEXT: mov w8, #10
; CHECK-NEXT: sub w0, w8, w19 ; CHECK-NEXT: sub w0, w8, w19
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 %arg, 8 %t0 = sub i32 %arg, 8
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = sub i32 2, %t0 %t1 = sub i32 2, %t0
Show All 9 Lines; CHECK-NEXT: ret
%t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
%t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_sub_const_const_sub_extrause(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_const_sub_extrause(<4 x i32> %arg) {
; CHECK-LABEL: vec_sub_const_const_sub_extrause: ; CHECK-LABEL: vec_sub_const_const_sub_extrause:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #2 ; CHECK-NEXT: movi v0.4s, #2
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_sub_const_const_sub_nonsplat(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_const_sub_nonsplat(<4 x i32> %arg) {
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg
%t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_const_sub_add_const_extrause(<4 x i32> %arg) { define <4 x i32> @vec_const_sub_add_const_extrause(<4 x i32> %arg) {
; CHECK-LABEL: vec_const_sub_add_const_extrause: ; CHECK-LABEL: vec_const_sub_add_const_extrause:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #10 ; CHECK-NEXT: movi v0.4s, #10
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_const_sub_add_const_nonsplat(<4 x i32> %arg) { define <4 x i32> @vec_const_sub_add_const_nonsplat(<4 x i32> %arg) {
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_const_sub_sub_const_extrause(<4 x i32> %arg) { define <4 x i32> @vec_const_sub_sub_const_extrause(<4 x i32> %arg) {
; CHECK-LABEL: vec_const_sub_sub_const_extrause: ; CHECK-LABEL: vec_const_sub_sub_const_extrause:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #6 ; CHECK-NEXT: movi v0.4s, #6
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_const_sub_sub_const_nonsplat(<4 x i32> %arg) { define <4 x i32> @vec_const_sub_sub_const_nonsplat(<4 x i32> %arg) {
; CHECK-LABEL: vec_const_sub_sub_const_nonsplat: ; CHECK-LABEL: vec_const_sub_sub_const_nonsplat:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI39_0 ; CHECK-NEXT: adrp x8, .LCPI39_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI39_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI39_0]
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> <i32 21, i32 undef, i32 8, i32 8>, %arg %t0 = sub <4 x i32> <i32 21, i32 undef, i32 8, i32 8>, %arg
%t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
; c2-(c1-x) ; c2-(c1-x)
define i32 @const_sub_const_sub(i32 %arg) { define i32 @const_sub_const_sub(i32 %arg) {
; CHECK-LABEL: const_sub_const_sub: ; CHECK-LABEL: const_sub_const_sub:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub w0, w0, #6 // =6 ; CHECK-NEXT: sub w0, w0, #6
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 8, %arg %t0 = sub i32 8, %arg
%t1 = sub i32 2, %t0 %t1 = sub i32 2, %t0
ret i32 %t1 ret i32 %t1
} }
define i32 @const_sub_const_sub_extrause(i32 %arg) { define i32 @const_sub_const_sub_extrause(i32 %arg) {
; CHECK-LABEL: const_sub_const_sub_extrause: ; CHECK-LABEL: const_sub_const_sub_extrause:
Show All 25 Lines; CHECK-NEXT: ret
%t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg
%t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_const_sub_const_sub_extrause(<4 x i32> %arg) { define <4 x i32> @vec_const_sub_const_sub_extrause(<4 x i32> %arg) {
; CHECK-LABEL: vec_const_sub_const_sub_extrause: ; CHECK-LABEL: vec_const_sub_const_sub_extrause:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #2 ; CHECK-NEXT: movi v0.4s, #2
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_const_sub_const_sub_nonsplat(<4 x i32> %arg) { define <4 x i32> @vec_const_sub_const_sub_nonsplat(<4 x i32> %arg) {
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llvm/test/CodeGen/AArch64/addsub.ll

Show All 13 Lines
; CHECK-LABEL: add_small: ; CHECK-LABEL: add_small:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, :got:var_i32 ; CHECK-NEXT: adrp x8, :got:var_i32
; CHECK-NEXT: adrp x9, :got:var_i64 ; CHECK-NEXT: adrp x9, :got:var_i64
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var_i32] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:var_i32]
; CHECK-NEXT: ldr x9, [x9, :got_lo12:var_i64] ; CHECK-NEXT: ldr x9, [x9, :got_lo12:var_i64]
; CHECK-NEXT: ldr w10, [x8] ; CHECK-NEXT: ldr w10, [x8]
; CHECK-NEXT: ldr x11, [x9] ; CHECK-NEXT: ldr x11, [x9]
; CHECK-NEXT: add w10, w10, #4095 // =4095 ; CHECK-NEXT: add w10, w10, #4095
; CHECK-NEXT: add x11, x11, #52 // =52 ; CHECK-NEXT: add x11, x11, #52
; CHECK-NEXT: str w10, [x8] ; CHECK-NEXT: str w10, [x8]
; CHECK-NEXT: str x11, [x9] ; CHECK-NEXT: str x11, [x9]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val32 = load i32, i32* @var_i32 %val32 = load i32, i32* @var_i32
%newval32 = add i32 %val32, 4095 %newval32 = add i32 %val32, 4095
store i32 %newval32, i32* @var_i32 store i32 %newval32, i32* @var_i32
Show All 13 Lines
; whereas this can be achieved with: ; whereas this can be achieved with:
; wA = ldrb ; wA = ldrb
; xC = add xA, #12 ; <- xA implicitly zero extend wA. ; xC = add xA, #12 ; <- xA implicitly zero extend wA.
define void @add_small_imm(i8* %p, i64* %q, i32 %b, i32* %addr) { define void @add_small_imm(i8* %p, i64* %q, i32 %b, i32* %addr) {
; CHECK-LABEL: add_small_imm: ; CHECK-LABEL: add_small_imm:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldrb w8, [x0] ; CHECK-NEXT: ldrb w8, [x0]
; CHECK-NEXT: add w9, w8, w2 ; CHECK-NEXT: add w9, w8, w2
; CHECK-NEXT: add x8, x8, #12 // =12 ; CHECK-NEXT: add x8, x8, #12
; CHECK-NEXT: str w9, [x3] ; CHECK-NEXT: str w9, [x3]
; CHECK-NEXT: str x8, [x1] ; CHECK-NEXT: str x8, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%t = load i8, i8* %p %t = load i8, i8* %p
%promoted = zext i8 %t to i64 %promoted = zext i8 %t to i64
%zextt = zext i8 %t to i32 %zextt = zext i8 %t to i32
Show All 38 Lines
; CHECK-LABEL: sub_small: ; CHECK-LABEL: sub_small:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, :got:var_i32 ; CHECK-NEXT: adrp x8, :got:var_i32
; CHECK-NEXT: adrp x9, :got:var_i64 ; CHECK-NEXT: adrp x9, :got:var_i64
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var_i32] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:var_i32]
; CHECK-NEXT: ldr x9, [x9, :got_lo12:var_i64] ; CHECK-NEXT: ldr x9, [x9, :got_lo12:var_i64]
; CHECK-NEXT: ldr w10, [x8] ; CHECK-NEXT: ldr w10, [x8]
; CHECK-NEXT: ldr x11, [x9] ; CHECK-NEXT: ldr x11, [x9]
; CHECK-NEXT: sub w10, w10, #4095 // =4095 ; CHECK-NEXT: sub w10, w10, #4095
; CHECK-NEXT: sub x11, x11, #52 // =52 ; CHECK-NEXT: sub x11, x11, #52
; CHECK-NEXT: str w10, [x8] ; CHECK-NEXT: str w10, [x8]
; CHECK-NEXT: str x11, [x9] ; CHECK-NEXT: str x11, [x9]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val32 = load i32, i32* @var_i32 %val32 = load i32, i32* @var_i32
%newval32 = sub i32 %val32, 4095 %newval32 = sub i32 %val32, 4095
store i32 %newval32, i32* @var_i32 store i32 %newval32, i32* @var_i32
Show All 32 Lines
} }
define void @testing() { define void @testing() {
; CHECK-LABEL: testing: ; CHECK-LABEL: testing:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, :got:var_i32 ; CHECK-NEXT: adrp x8, :got:var_i32
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var_i32] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:var_i32]
; CHECK-NEXT: ldr w9, [x8] ; CHECK-NEXT: ldr w9, [x8]
; CHECK-NEXT: cmp w9, #4095 // =4095 ; CHECK-NEXT: cmp w9, #4095
; CHECK-NEXT: b.ne .LBB5_6 ; CHECK-NEXT: b.ne .LBB5_6
; CHECK-NEXT: // %bb.1: // %test2 ; CHECK-NEXT: // %bb.1: // %test2
; CHECK-NEXT: adrp x10, :got:var2_i32 ; CHECK-NEXT: adrp x10, :got:var2_i32
; CHECK-NEXT: ldr x10, [x10, :got_lo12:var2_i32] ; CHECK-NEXT: ldr x10, [x10, :got_lo12:var2_i32]
; CHECK-NEXT: add w11, w9, #1 // =1 ; CHECK-NEXT: add w11, w9, #1
; CHECK-NEXT: str w11, [x8] ; CHECK-NEXT: str w11, [x8]
; CHECK-NEXT: ldr w10, [x10] ; CHECK-NEXT: ldr w10, [x10]
; CHECK-NEXT: cmp w10, #3567, lsl #12 // =14610432 ; CHECK-NEXT: cmp w10, #3567, lsl #12 // =14610432
; CHECK-NEXT: b.lo .LBB5_6 ; CHECK-NEXT: b.lo .LBB5_6
; CHECK-NEXT: // %bb.2: // %test3 ; CHECK-NEXT: // %bb.2: // %test3
; CHECK-NEXT: add w11, w9, #2 // =2 ; CHECK-NEXT: add w11, w9, #2
; CHECK-NEXT: cmp w9, #123 // =123 ; CHECK-NEXT: cmp w9, #123
; CHECK-NEXT: str w11, [x8] ; CHECK-NEXT: str w11, [x8]
; CHECK-NEXT: b.lt .LBB5_6 ; CHECK-NEXT: b.lt .LBB5_6
; CHECK-NEXT: // %bb.3: // %test4 ; CHECK-NEXT: // %bb.3: // %test4
; CHECK-NEXT: add w11, w9, #3 // =3 ; CHECK-NEXT: add w11, w9, #3
; CHECK-NEXT: cmp w10, #321 // =321 ; CHECK-NEXT: cmp w10, #321
; CHECK-NEXT: str w11, [x8] ; CHECK-NEXT: str w11, [x8]
; CHECK-NEXT: b.gt .LBB5_6 ; CHECK-NEXT: b.gt .LBB5_6
; CHECK-NEXT: // %bb.4: // %test5 ; CHECK-NEXT: // %bb.4: // %test5
; CHECK-NEXT: add w11, w9, #4 // =4 ; CHECK-NEXT: add w11, w9, #4
; CHECK-NEXT: cmn w10, #443 // =443 ; CHECK-NEXT: cmn w10, #443
; CHECK-NEXT: str w11, [x8] ; CHECK-NEXT: str w11, [x8]
; CHECK-NEXT: b.ge .LBB5_6 ; CHECK-NEXT: b.ge .LBB5_6
; CHECK-NEXT: // %bb.5: // %test6 ; CHECK-NEXT: // %bb.5: // %test6
; CHECK-NEXT: add w9, w9, #5 // =5 ; CHECK-NEXT: add w9, w9, #5
; CHECK-NEXT: str w9, [x8] ; CHECK-NEXT: str w9, [x8]
; CHECK-NEXT: .LBB5_6: // %common.ret ; CHECK-NEXT: .LBB5_6: // %common.ret
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val = load i32, i32* @var_i32 %val = load i32, i32* @var_i32
%val2 = load i32, i32* @var2_i32 %val2 = load i32, i32* @var2_i32
%cmp_pos_small = icmp ne i32 %val, 4095 %cmp_pos_small = icmp ne i32 %val, 4095
br i1 %cmp_pos_small, label %ret, label %test2 br i1 %cmp_pos_small, label %ret, label %test2
Show All 34 Lines
declare {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) declare {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
define i1 @sadd_add(i32 %a, i32 %b, i32* %p) { define i1 @sadd_add(i32 %a, i32 %b, i32* %p) {
; CHECK-LABEL: sadd_add: ; CHECK-LABEL: sadd_add:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mvn w8, w0 ; CHECK-NEXT: mvn w8, w0
; CHECK-NEXT: adds w8, w8, w1 ; CHECK-NEXT: adds w8, w8, w1
; CHECK-NEXT: cset w0, vs ; CHECK-NEXT: cset w0, vs
; CHECK-NEXT: add w8, w8, #1 // =1 ; CHECK-NEXT: add w8, w8, #1
; CHECK-NEXT: str w8, [x2] ; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%nota = xor i32 %a, -1 %nota = xor i32 %a, -1
%a0 = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %nota, i32 %b) %a0 = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %nota, i32 %b)
%e0 = extractvalue {i32, i1} %a0, 0 %e0 = extractvalue {i32, i1} %a0, 0
%e1 = extractvalue {i32, i1} %a0, 1 %e1 = extractvalue {i32, i1} %a0, 1
%res = add i32 %e0, 1 %res = add i32 %e0, 1
store i32 %res, i32* %p store i32 %res, i32* %p
ret i1 %e1 ret i1 %e1
} }
declare {i8, i1} @llvm.uadd.with.overflow.i8(i8 %a, i8 %b) declare {i8, i1} @llvm.uadd.with.overflow.i8(i8 %a, i8 %b)
define i1 @uadd_add(i8 %a, i8 %b, i8* %p) { define i1 @uadd_add(i8 %a, i8 %b, i8* %p) {
; CHECK-LABEL: uadd_add: ; CHECK-LABEL: uadd_add:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mvn w8, w0 ; CHECK-NEXT: mvn w8, w0
; CHECK-NEXT: and w8, w8, #0xff ; CHECK-NEXT: and w8, w8, #0xff
; CHECK-NEXT: add w8, w8, w1, uxtb ; CHECK-NEXT: add w8, w8, w1, uxtb
; CHECK-NEXT: lsr w0, w8, #8 ; CHECK-NEXT: lsr w0, w8, #8
; CHECK-NEXT: add w8, w8, #1 // =1 ; CHECK-NEXT: add w8, w8, #1
; CHECK-NEXT: strb w8, [x2] ; CHECK-NEXT: strb w8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%nota = xor i8 %a, -1 %nota = xor i8 %a, -1
%a0 = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 %nota, i8 %b) %a0 = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 %nota, i8 %b)
%e0 = extractvalue {i8, i1} %a0, 0 %e0 = extractvalue {i8, i1} %a0, 0
%e1 = extractvalue {i8, i1} %a0, 1 %e1 = extractvalue {i8, i1} %a0, 1
%res = add i8 %e0, 1 %res = add i8 %e0, 1
store i8 %res, i8* %p store i8 %res, i8* %p
ret i1 %e1 ret i1 %e1
} }
; TODO: adds/subs ; TODO: adds/subs

llvm/test/CodeGen/AArch64/align-down.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
} }
; Extra use tests ; Extra use tests
define i32 @t3_extrause0(i32 %ptr, i32 %alignment, i32* %mask_storage) nounwind { define i32 @t3_extrause0(i32 %ptr, i32 %alignment, i32* %mask_storage) nounwind {
; CHECK-LABEL: t3_extrause0: ; CHECK-LABEL: t3_extrause0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: neg w9, w1 ; CHECK-NEXT: neg w9, w1
; CHECK-NEXT: sub w8, w1, #1 // =1 ; CHECK-NEXT: sub w8, w1, #1
; CHECK-NEXT: and w0, w0, w9 ; CHECK-NEXT: and w0, w0, w9
; CHECK-NEXT: str w8, [x2] ; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = add i32 %alignment, -1 %mask = add i32 %alignment, -1
store i32 %mask, i32* %mask_storage store i32 %mask, i32* %mask_storage
%bias = and i32 %ptr, %mask %bias = and i32 %ptr, %mask
%r = sub i32 %ptr, %bias %r = sub i32 %ptr, %bias
ret i32 %r ret i32 %r
} }
define i32 @n4_extrause1(i32 %ptr, i32 %alignment, i32* %bias_storage) nounwind { define i32 @n4_extrause1(i32 %ptr, i32 %alignment, i32* %bias_storage) nounwind {
; CHECK-LABEL: n4_extrause1: ; CHECK-LABEL: n4_extrause1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, #1 // =1 ; CHECK-NEXT: sub w8, w1, #1
; CHECK-NEXT: and w8, w0, w8 ; CHECK-NEXT: and w8, w0, w8
; CHECK-NEXT: sub w0, w0, w8 ; CHECK-NEXT: sub w0, w0, w8
; CHECK-NEXT: str w8, [x2] ; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = add i32 %alignment, -1 %mask = add i32 %alignment, -1
%bias = and i32 %ptr, %mask ; has extra uses, can't fold %bias = and i32 %ptr, %mask ; has extra uses, can't fold
store i32 %bias, i32* %bias_storage store i32 %bias, i32* %bias_storage
%r = sub i32 %ptr, %bias %r = sub i32 %ptr, %bias
ret i32 %r ret i32 %r
} }
define i32 @n5_extrause2(i32 %ptr, i32 %alignment, i32* %mask_storage, i32* %bias_storage) nounwind { define i32 @n5_extrause2(i32 %ptr, i32 %alignment, i32* %mask_storage, i32* %bias_storage) nounwind {
; CHECK-LABEL: n5_extrause2: ; CHECK-LABEL: n5_extrause2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, #1 // =1 ; CHECK-NEXT: sub w8, w1, #1
; CHECK-NEXT: str w8, [x2] ; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: and w8, w0, w8 ; CHECK-NEXT: and w8, w0, w8
; CHECK-NEXT: sub w0, w0, w8 ; CHECK-NEXT: sub w0, w0, w8
; CHECK-NEXT: str w8, [x3] ; CHECK-NEXT: str w8, [x3]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = add i32 %alignment, -1 %mask = add i32 %alignment, -1
store i32 %mask, i32* %mask_storage store i32 %mask, i32* %mask_storage
%bias = and i32 %ptr, %mask ; has extra uses, can't fold %bias = and i32 %ptr, %mask ; has extra uses, can't fold
store i32 %bias, i32* %bias_storage store i32 %bias, i32* %bias_storage
%r = sub i32 %ptr, %bias %r = sub i32 %ptr, %bias
ret i32 %r ret i32 %r
} }
; Negative tests ; Negative tests
define i32 @n6_different_ptrs(i32 %ptr0, i32 %ptr1, i32 %alignment) nounwind { define i32 @n6_different_ptrs(i32 %ptr0, i32 %ptr1, i32 %alignment) nounwind {
; CHECK-LABEL: n6_different_ptrs: ; CHECK-LABEL: n6_different_ptrs:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w2, #1 // =1 ; CHECK-NEXT: sub w8, w2, #1
; CHECK-NEXT: and w8, w1, w8 ; CHECK-NEXT: and w8, w1, w8
; CHECK-NEXT: sub w0, w0, w8 ; CHECK-NEXT: sub w0, w0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = add i32 %alignment, -1 %mask = add i32 %alignment, -1
%bias = and i32 %ptr1, %mask ; not %ptr0 %bias = and i32 %ptr1, %mask ; not %ptr0
%r = sub i32 %ptr0, %bias ; not %ptr1 %r = sub i32 %ptr0, %bias ; not %ptr1
ret i32 %r ret i32 %r
} }
define i32 @n7_different_ptrs_commutative(i32 %ptr0, i32 %ptr1, i32 %alignment) nounwind { define i32 @n7_different_ptrs_commutative(i32 %ptr0, i32 %ptr1, i32 %alignment) nounwind {
; CHECK-LABEL: n7_different_ptrs_commutative: ; CHECK-LABEL: n7_different_ptrs_commutative:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w2, #1 // =1 ; CHECK-NEXT: sub w8, w2, #1
; CHECK-NEXT: and w8, w8, w1 ; CHECK-NEXT: and w8, w8, w1
; CHECK-NEXT: sub w0, w0, w8 ; CHECK-NEXT: sub w0, w0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = add i32 %alignment, -1 %mask = add i32 %alignment, -1
%bias = and i32 %mask, %ptr1 ; swapped, not %ptr0 %bias = and i32 %mask, %ptr1 ; swapped, not %ptr0
%r = sub i32 %ptr0, %bias ; not %ptr1 %r = sub i32 %ptr0, %bias ; not %ptr1
ret i32 %r ret i32 %r
} }
define i32 @n8_not_lowbit_mask(i32 %ptr, i32 %alignment) nounwind { define i32 @n8_not_lowbit_mask(i32 %ptr, i32 %alignment) nounwind {
; CHECK-LABEL: n8_not_lowbit_mask: ; CHECK-LABEL: n8_not_lowbit_mask:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w1, #1 // =1 ; CHECK-NEXT: add w8, w1, #1
; CHECK-NEXT: bic w0, w0, w8 ; CHECK-NEXT: bic w0, w0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = add i32 %alignment, 1 ; not -1 %mask = add i32 %alignment, 1 ; not -1
%bias = and i32 %ptr, %mask %bias = and i32 %ptr, %mask
%r = sub i32 %ptr, %bias %r = sub i32 %ptr, %bias
ret i32 %r ret i32 %r
} }
define i32 @n9_sub_is_not_commutative(i32 %ptr, i32 %alignment) nounwind { define i32 @n9_sub_is_not_commutative(i32 %ptr, i32 %alignment) nounwind {
; CHECK-LABEL: n9_sub_is_not_commutative: ; CHECK-LABEL: n9_sub_is_not_commutative:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, #1 // =1 ; CHECK-NEXT: sub w8, w1, #1
; CHECK-NEXT: and w8, w0, w8 ; CHECK-NEXT: and w8, w0, w8
; CHECK-NEXT: sub w0, w8, w0 ; CHECK-NEXT: sub w0, w8, w0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = add i32 %alignment, -1 %mask = add i32 %alignment, -1
%bias = and i32 %ptr, %mask %bias = and i32 %ptr, %mask
%r = sub i32 %bias, %ptr ; wrong order %r = sub i32 %bias, %ptr ; wrong order
ret i32 %r ret i32 %r
} }

llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -aarch64-load-store-renaming=true < %s -mtriple=arm64-apple-ios7.0.0 -mcpu=cyclone -enable-misched=false | FileCheck %s ; RUN: llc -aarch64-load-store-renaming=true < %s -mtriple=arm64-apple-ios7.0.0 -mcpu=cyclone -enable-misched=false | FileCheck %s
; rdar://13625505 ; rdar://13625505
; Here we have 9 fixed integer arguments the 9th argument in on stack, the ; Here we have 9 fixed integer arguments the 9th argument in on stack, the
; varargs start right after at 8-byte alignment. ; varargs start right after at 8-byte alignment.
define void @fn9(i32* %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, ...) nounwind noinline ssp { define void @fn9(i32* %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, ...) nounwind noinline ssp {
; CHECK-LABEL: fn9: ; CHECK-LABEL: fn9:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: sub sp, sp, #64 ; =64 ; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: ldr w8, [sp, #64] ; CHECK-NEXT: ldr w8, [sp, #64]
; CHECK-NEXT: stp w2, w1, [sp, #52] ; CHECK-NEXT: stp w2, w1, [sp, #52]
; CHECK-NEXT: stp w4, w3, [sp, #44] ; CHECK-NEXT: stp w4, w3, [sp, #44]
; CHECK-NEXT: stp w6, w5, [sp, #36] ; CHECK-NEXT: stp w6, w5, [sp, #36]
; CHECK-NEXT: str w7, [sp, #32] ; CHECK-NEXT: str w7, [sp, #32]
; CHECK-NEXT: str w8, [x0] ; CHECK-NEXT: str w8, [x0]
; CHECK-NEXT: ldr w9, [sp, #72] ; CHECK-NEXT: ldr w9, [sp, #72]
; CHECK-NEXT: ldr w8, [sp, #80] ; CHECK-NEXT: ldr w8, [sp, #80]
; CHECK-NEXT: stp w8, w9, [sp, #16] ; CHECK-NEXT: stp w8, w9, [sp, #16]
; CHECK-NEXT: add x8, sp, #72 ; =72 ; CHECK-NEXT: add x8, sp, #72
; CHECK-NEXT: add x8, x8, #24 ; =24 ; CHECK-NEXT: add x8, x8, #24
; CHECK-NEXT: str x8, [sp, #24] ; CHECK-NEXT: str x8, [sp, #24]
; CHECK-NEXT: ldr w8, [sp, #88] ; CHECK-NEXT: ldr w8, [sp, #88]
; CHECK-NEXT: str w8, [sp, #12] ; CHECK-NEXT: str w8, [sp, #12]
; CHECK-NEXT: add sp, sp, #64 ; =64 ; CHECK-NEXT: add sp, sp, #64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = alloca i32, align 4 %1 = alloca i32, align 4
%2 = alloca i32, align 4 %2 = alloca i32, align 4
%3 = alloca i32, align 4 %3 = alloca i32, align 4
%4 = alloca i32, align 4 %4 = alloca i32, align 4
%5 = alloca i32, align 4 %5 = alloca i32, align 4
%6 = alloca i32, align 4 %6 = alloca i32, align 4
%7 = alloca i32, align 4 %7 = alloca i32, align 4
Show All 23 Lines; CHECK-NEXT: ret
ret void ret void
} }
declare void @llvm.va_start(i8*) nounwind declare void @llvm.va_start(i8*) nounwind
define i32 @main() nounwind ssp { define i32 @main() nounwind ssp {
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: sub sp, sp, #96 ; =96 ; CHECK-NEXT: sub sp, sp, #96
; CHECK-NEXT: stp x29, x30, [sp, #80] ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #80] ; 16-byte Folded Spill
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: mov w8, #2 ; CHECK-NEXT: mov w8, #2
; CHECK-NEXT: stp w8, w9, [sp, #72] ; CHECK-NEXT: stp w8, w9, [sp, #72]
; CHECK-NEXT: mov w9, #3 ; CHECK-NEXT: mov w9, #3
; CHECK-NEXT: mov w8, #4 ; CHECK-NEXT: mov w8, #4
; CHECK-NEXT: stp w8, w9, [sp, #64] ; CHECK-NEXT: stp w8, w9, [sp, #64]
; CHECK-NEXT: mov w9, #5 ; CHECK-NEXT: mov w9, #5
; CHECK-NEXT: mov w8, #6 ; CHECK-NEXT: mov w8, #6
; CHECK-NEXT: stp w8, w9, [sp, #56] ; CHECK-NEXT: stp w8, w9, [sp, #56]
; CHECK-NEXT: mov w9, #7 ; CHECK-NEXT: mov w9, #7
; CHECK-NEXT: mov w8, #8 ; CHECK-NEXT: mov w8, #8
; CHECK-NEXT: stp w8, w9, [sp, #48] ; CHECK-NEXT: stp w8, w9, [sp, #48]
; CHECK-NEXT: mov w8, #9 ; CHECK-NEXT: mov w8, #9
; CHECK-NEXT: mov w9, #10 ; CHECK-NEXT: mov w9, #10
; CHECK-NEXT: stp w9, w8, [sp, #40] ; CHECK-NEXT: stp w9, w8, [sp, #40]
; CHECK-NEXT: mov w10, #11 ; CHECK-NEXT: mov w10, #11
; CHECK-NEXT: mov w11, #12 ; CHECK-NEXT: mov w11, #12
; CHECK-NEXT: stp w11, w10, [sp, #32] ; CHECK-NEXT: stp w11, w10, [sp, #32]
; CHECK-NEXT: stp x10, x11, [sp, #16] ; CHECK-NEXT: stp x10, x11, [sp, #16]
; CHECK-NEXT: str x9, [sp, #8] ; CHECK-NEXT: str x9, [sp, #8]
; CHECK-NEXT: str w8, [sp] ; CHECK-NEXT: str w8, [sp]
; CHECK-NEXT: add x0, sp, #76 ; =76 ; CHECK-NEXT: add x0, sp, #76
; CHECK-NEXT: mov w1, #2 ; CHECK-NEXT: mov w1, #2
; CHECK-NEXT: mov w2, #3 ; CHECK-NEXT: mov w2, #3
; CHECK-NEXT: mov w3, #4 ; CHECK-NEXT: mov w3, #4
; CHECK-NEXT: mov w4, #5 ; CHECK-NEXT: mov w4, #5
; CHECK-NEXT: mov w5, #6 ; CHECK-NEXT: mov w5, #6
; CHECK-NEXT: mov w6, #7 ; CHECK-NEXT: mov w6, #7
; CHECK-NEXT: mov w7, #8 ; CHECK-NEXT: mov w7, #8
; CHECK-NEXT: bl _fn9 ; CHECK-NEXT: bl _fn9
; CHECK-NEXT: mov w0, #0 ; CHECK-NEXT: mov w0, #0
; CHECK-NEXT: ldp x29, x30, [sp, #80] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp, #80] ; 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #96 ; =96 ; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a1 = alloca i32, align 4 %a1 = alloca i32, align 4
%a2 = alloca i32, align 4 %a2 = alloca i32, align 4
%a3 = alloca i32, align 4 %a3 = alloca i32, align 4
%a4 = alloca i32, align 4 %a4 = alloca i32, align 4
%a5 = alloca i32, align 4 %a5 = alloca i32, align 4
%a6 = alloca i32, align 4 %a6 = alloca i32, align 4
%a7 = alloca i32, align 4 %a7 = alloca i32, align 4
Show All 30 Lines; CHECK-NEXT: ret
ret i32 0 ret i32 0
} }
;rdar://13668483 ;rdar://13668483
@.str = private unnamed_addr constant [4 x i8] c"fmt\00", align 1 @.str = private unnamed_addr constant [4 x i8] c"fmt\00", align 1
define void @foo(i8* %fmt, ...) nounwind { define void @foo(i8* %fmt, ...) nounwind {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: sub sp, sp, #48 ; =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: ldr w8, [sp, #48] ; CHECK-NEXT: ldr w8, [sp, #48]
; CHECK-NEXT: str w8, [sp, #28] ; CHECK-NEXT: str w8, [sp, #28]
; CHECK-NEXT: add x8, sp, #48 ; =48 ; CHECK-NEXT: add x8, sp, #48
; CHECK-NEXT: add x8, x8, #23 ; =23 ; CHECK-NEXT: add x8, x8, #23
; CHECK-NEXT: and x8, x8, #0xfffffffffffffff0 ; CHECK-NEXT: and x8, x8, #0xfffffffffffffff0
; CHECK-NEXT: add x9, x8, #16 ; =16 ; CHECK-NEXT: add x9, x8, #16
; CHECK-NEXT: stp x9, x0, [sp, #32] ; CHECK-NEXT: stp x9, x0, [sp, #32]
; CHECK-NEXT: ldr q0, [x8] ; CHECK-NEXT: ldr q0, [x8]
; CHECK-NEXT: str q0, [sp], #48 ; CHECK-NEXT: str q0, [sp], #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%fmt.addr = alloca i8*, align 8 %fmt.addr = alloca i8*, align 8
%args = alloca i8*, align 8 %args = alloca i8*, align 8
%vc = alloca i32, align 4 %vc = alloca i32, align 4
%vv = alloca <4 x i32>, align 16 %vv = alloca <4 x i32>, align 16
store i8* %fmt, i8** %fmt.addr, align 8 store i8* %fmt, i8** %fmt.addr, align 8
%args1 = bitcast i8** %args to i8* %args1 = bitcast i8** %args to i8*
call void @llvm.va_start(i8* %args1) call void @llvm.va_start(i8* %args1)
%0 = va_arg i8** %args, i32 %0 = va_arg i8** %args, i32
store i32 %0, i32* %vc, align 4 store i32 %0, i32* %vc, align 4
%1 = va_arg i8** %args, <4 x i32> %1 = va_arg i8** %args, <4 x i32>
store <4 x i32> %1, <4 x i32>* %vv, align 16 store <4 x i32> %1, <4 x i32>* %vv, align 16
ret void ret void
} }
define void @bar(i32 %x, <4 x i32> %y) nounwind { define void @bar(i32 %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: bar: ; CHECK-LABEL: bar:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: sub sp, sp, #80 ; =80 ; CHECK-NEXT: sub sp, sp, #80
; CHECK-NEXT: stp x29, x30, [sp, #64] ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #64] ; 16-byte Folded Spill
; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0 ; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: str w0, [sp, #60] ; CHECK-NEXT: str w0, [sp, #60]
; CHECK-NEXT: stp q0, q0, [sp, #16] ; CHECK-NEXT: stp q0, q0, [sp, #16]
; CHECK-NEXT: str x0, [sp] ; CHECK-NEXT: str x0, [sp]
; CHECK-NEXT: Lloh0: ; CHECK-NEXT: Lloh0:
; CHECK-NEXT: adrp x0, l_.str@PAGE ; CHECK-NEXT: adrp x0, l_.str@PAGE
; CHECK-NEXT: Lloh1: ; CHECK-NEXT: Lloh1:
; CHECK-NEXT: add x0, x0, l_.str@PAGEOFF ; CHECK-NEXT: add x0, x0, l_.str@PAGEOFF
; CHECK-NEXT: bl _foo ; CHECK-NEXT: bl _foo
; CHECK-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #80 ; =80 ; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpAdd Lloh0, Lloh1 ; CHECK-NEXT: .loh AdrpAdd Lloh0, Lloh1
entry: entry:
%x.addr = alloca i32, align 4 %x.addr = alloca i32, align 4
%y.addr = alloca <4 x i32>, align 16 %y.addr = alloca <4 x i32>, align 16
store i32 %x, i32* %x.addr, align 4 store i32 %x, i32* %x.addr, align 4
store <4 x i32> %y, <4 x i32>* %y.addr, align 16 store <4 x i32> %y, <4 x i32>* %y.addr, align 16
%0 = load i32, i32* %x.addr, align 4 %0 = load i32, i32* %x.addr, align 4
%1 = load <4 x i32>, <4 x i32>* %y.addr, align 16 %1 = load <4 x i32>, <4 x i32>* %y.addr, align 16
call void (i8*, ...) @foo(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %0, <4 x i32> %1) call void (i8*, ...) @foo(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %0, <4 x i32> %1)
ret void ret void
} }
; rdar://13668927 ; rdar://13668927
; When passing 16-byte aligned small structs as vararg, make sure the caller ; When passing 16-byte aligned small structs as vararg, make sure the caller
; side is 16-byte aligned on stack. ; side is 16-byte aligned on stack.
%struct.s41 = type { i32, i16, i32, i16 } %struct.s41 = type { i32, i16, i32, i16 }
define void @foo2(i8* %fmt, ...) nounwind { define void @foo2(i8* %fmt, ...) nounwind {
; CHECK-LABEL: foo2: ; CHECK-LABEL: foo2:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: sub sp, sp, #48 ; =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: ldr w8, [sp, #48] ; CHECK-NEXT: ldr w8, [sp, #48]
; CHECK-NEXT: str w8, [sp, #28] ; CHECK-NEXT: str w8, [sp, #28]
; CHECK-NEXT: add x8, sp, #48 ; =48 ; CHECK-NEXT: add x8, sp, #48
; CHECK-NEXT: add x8, x8, #23 ; =23 ; CHECK-NEXT: add x8, x8, #23
; CHECK-NEXT: and x8, x8, #0xfffffffffffffff0 ; CHECK-NEXT: and x8, x8, #0xfffffffffffffff0
; CHECK-NEXT: add x9, x8, #16 ; =16 ; CHECK-NEXT: add x9, x8, #16
; CHECK-NEXT: stp x9, x0, [sp, #32] ; CHECK-NEXT: stp x9, x0, [sp, #32]
; CHECK-NEXT: ldr q0, [x8] ; CHECK-NEXT: ldr q0, [x8]
; CHECK-NEXT: str q0, [sp], #48 ; CHECK-NEXT: str q0, [sp], #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%fmt.addr = alloca i8*, align 8 %fmt.addr = alloca i8*, align 8
%args = alloca i8*, align 8 %args = alloca i8*, align 8
%vc = alloca i32, align 4 %vc = alloca i32, align 4
Show All 16 Linesentry:
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %5, i8* align 16 %6, i64 16, i1 false) call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %5, i8* align 16 %6, i64 16, i1 false)
ret void ret void
} }
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind
define void @bar2(i32 %x, i128 %s41.coerce) nounwind { define void @bar2(i32 %x, i128 %s41.coerce) nounwind {
; CHECK-LABEL: bar2: ; CHECK-LABEL: bar2:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: sub sp, sp, #80 ; =80 ; CHECK-NEXT: sub sp, sp, #80
; CHECK-NEXT: stp x29, x30, [sp, #64] ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #64] ; 16-byte Folded Spill
; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0 ; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: str w0, [sp, #60] ; CHECK-NEXT: str w0, [sp, #60]
; CHECK-NEXT: stp x1, x2, [sp, #32] ; CHECK-NEXT: stp x1, x2, [sp, #32]
; CHECK-NEXT: stp x1, x2, [sp, #16] ; CHECK-NEXT: stp x1, x2, [sp, #16]
; CHECK-NEXT: str x0, [sp] ; CHECK-NEXT: str x0, [sp]
; CHECK-NEXT: Lloh2: ; CHECK-NEXT: Lloh2:
; CHECK-NEXT: adrp x0, l_.str@PAGE ; CHECK-NEXT: adrp x0, l_.str@PAGE
; CHECK-NEXT: Lloh3: ; CHECK-NEXT: Lloh3:
; CHECK-NEXT: add x0, x0, l_.str@PAGEOFF ; CHECK-NEXT: add x0, x0, l_.str@PAGEOFF
; CHECK-NEXT: bl _foo2 ; CHECK-NEXT: bl _foo2
; CHECK-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #80 ; =80 ; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpAdd Lloh2, Lloh3 ; CHECK-NEXT: .loh AdrpAdd Lloh2, Lloh3
entry: entry:
%x.addr = alloca i32, align 4 %x.addr = alloca i32, align 4
%s41 = alloca %struct.s41, align 16 %s41 = alloca %struct.s41, align 16
store i32 %x, i32* %x.addr, align 4 store i32 %x, i32* %x.addr, align 4
%0 = bitcast %struct.s41* %s41 to i128* %0 = bitcast %struct.s41* %s41 to i128*
store i128 %s41.coerce, i128* %0, align 1 store i128 %s41.coerce, i128* %0, align 1
%1 = load i32, i32* %x.addr, align 4 %1 = load i32, i32* %x.addr, align 4
%2 = bitcast %struct.s41* %s41 to i128* %2 = bitcast %struct.s41* %s41 to i128*
%3 = load i128, i128* %2, align 1 %3 = load i128, i128* %2, align 1
call void (i8*, ...) @foo2(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %1, i128 %3) call void (i8*, ...) @foo2(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %1, i128 %3)
ret void ret void
} }

llvm/test/CodeGen/AArch64/arm64-atomic-128.ll

Show First 20 Lines • Show All 300 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .LBB8_1: // %atomicrmw.start ; CHECK-NEXT: .LBB8_1: // %atomicrmw.start
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldaxp x9, x8, [x0] ; CHECK-NEXT: ldaxp x9, x8, [x0]
; CHECK-NEXT: cmp x9, x2 ; CHECK-NEXT: cmp x9, x2
; CHECK-NEXT: cset w10, ls ; CHECK-NEXT: cset w10, ls
; CHECK-NEXT: cmp x8, x3 ; CHECK-NEXT: cmp x8, x3
; CHECK-NEXT: cset w11, le ; CHECK-NEXT: cset w11, le
; CHECK-NEXT: csel w10, w10, w11, eq ; CHECK-NEXT: csel w10, w10, w11, eq
; CHECK-NEXT: cmp w10, #0 // =0 ; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: csel x10, x8, x3, ne ; CHECK-NEXT: csel x10, x8, x3, ne
; CHECK-NEXT: csel x11, x9, x2, ne ; CHECK-NEXT: csel x11, x9, x2, ne
; CHECK-NEXT: stlxp w12, x11, x10, [x0] ; CHECK-NEXT: stlxp w12, x11, x10, [x0]
; CHECK-NEXT: cbnz w12, .LBB8_1 ; CHECK-NEXT: cbnz w12, .LBB8_1
; CHECK-NEXT: // %bb.2: // %atomicrmw.end ; CHECK-NEXT: // %bb.2: // %atomicrmw.end
; CHECK-NEXT: adrp x10, :got:var ; CHECK-NEXT: adrp x10, :got:var
; CHECK-NEXT: ldr x10, [x10, :got_lo12:var] ; CHECK-NEXT: ldr x10, [x10, :got_lo12:var]
; CHECK-NEXT: stp x9, x8, [x10] ; CHECK-NEXT: stp x9, x8, [x10]
Show All 10 Lines
; CHECK-NEXT: .LBB9_1: // %atomicrmw.start ; CHECK-NEXT: .LBB9_1: // %atomicrmw.start
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldaxp x9, x8, [x0] ; CHECK-NEXT: ldaxp x9, x8, [x0]
; CHECK-NEXT: cmp x9, x2 ; CHECK-NEXT: cmp x9, x2
; CHECK-NEXT: cset w10, hi ; CHECK-NEXT: cset w10, hi
; CHECK-NEXT: cmp x8, x3 ; CHECK-NEXT: cmp x8, x3
; CHECK-NEXT: cset w11, gt ; CHECK-NEXT: cset w11, gt
; CHECK-NEXT: csel w10, w10, w11, eq ; CHECK-NEXT: csel w10, w10, w11, eq
; CHECK-NEXT: cmp w10, #0 // =0 ; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: csel x10, x8, x3, ne ; CHECK-NEXT: csel x10, x8, x3, ne
; CHECK-NEXT: csel x11, x9, x2, ne ; CHECK-NEXT: csel x11, x9, x2, ne
; CHECK-NEXT: stlxp w12, x11, x10, [x0] ; CHECK-NEXT: stlxp w12, x11, x10, [x0]
; CHECK-NEXT: cbnz w12, .LBB9_1 ; CHECK-NEXT: cbnz w12, .LBB9_1
; CHECK-NEXT: // %bb.2: // %atomicrmw.end ; CHECK-NEXT: // %bb.2: // %atomicrmw.end
; CHECK-NEXT: adrp x10, :got:var ; CHECK-NEXT: adrp x10, :got:var
; CHECK-NEXT: ldr x10, [x10, :got_lo12:var] ; CHECK-NEXT: ldr x10, [x10, :got_lo12:var]
; CHECK-NEXT: stp x9, x8, [x10] ; CHECK-NEXT: stp x9, x8, [x10]
Show All 10 Lines
; CHECK-NEXT: .LBB10_1: // %atomicrmw.start ; CHECK-NEXT: .LBB10_1: // %atomicrmw.start
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldaxp x9, x8, [x0] ; CHECK-NEXT: ldaxp x9, x8, [x0]
; CHECK-NEXT: cmp x9, x2 ; CHECK-NEXT: cmp x9, x2
; CHECK-NEXT: cset w10, ls ; CHECK-NEXT: cset w10, ls
; CHECK-NEXT: cmp x8, x3 ; CHECK-NEXT: cmp x8, x3
; CHECK-NEXT: cset w11, ls ; CHECK-NEXT: cset w11, ls
; CHECK-NEXT: csel w10, w10, w11, eq ; CHECK-NEXT: csel w10, w10, w11, eq
; CHECK-NEXT: cmp w10, #0 // =0 ; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: csel x10, x8, x3, ne ; CHECK-NEXT: csel x10, x8, x3, ne
; CHECK-NEXT: csel x11, x9, x2, ne ; CHECK-NEXT: csel x11, x9, x2, ne
; CHECK-NEXT: stlxp w12, x11, x10, [x0] ; CHECK-NEXT: stlxp w12, x11, x10, [x0]
; CHECK-NEXT: cbnz w12, .LBB10_1 ; CHECK-NEXT: cbnz w12, .LBB10_1
; CHECK-NEXT: // %bb.2: // %atomicrmw.end ; CHECK-NEXT: // %bb.2: // %atomicrmw.end
; CHECK-NEXT: adrp x10, :got:var ; CHECK-NEXT: adrp x10, :got:var
; CHECK-NEXT: ldr x10, [x10, :got_lo12:var] ; CHECK-NEXT: ldr x10, [x10, :got_lo12:var]
; CHECK-NEXT: stp x9, x8, [x10] ; CHECK-NEXT: stp x9, x8, [x10]
Show All 10 Lines
; CHECK-NEXT: .LBB11_1: // %atomicrmw.start ; CHECK-NEXT: .LBB11_1: // %atomicrmw.start
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldaxp x9, x8, [x0] ; CHECK-NEXT: ldaxp x9, x8, [x0]
; CHECK-NEXT: cmp x9, x2 ; CHECK-NEXT: cmp x9, x2
; CHECK-NEXT: cset w10, hi ; CHECK-NEXT: cset w10, hi
; CHECK-NEXT: cmp x8, x3 ; CHECK-NEXT: cmp x8, x3
; CHECK-NEXT: cset w11, hi ; CHECK-NEXT: cset w11, hi
; CHECK-NEXT: csel w10, w10, w11, eq ; CHECK-NEXT: csel w10, w10, w11, eq
; CHECK-NEXT: cmp w10, #0 // =0 ; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: csel x10, x8, x3, ne ; CHECK-NEXT: csel x10, x8, x3, ne
; CHECK-NEXT: csel x11, x9, x2, ne ; CHECK-NEXT: csel x11, x9, x2, ne
; CHECK-NEXT: stlxp w12, x11, x10, [x0] ; CHECK-NEXT: stlxp w12, x11, x10, [x0]
; CHECK-NEXT: cbnz w12, .LBB11_1 ; CHECK-NEXT: cbnz w12, .LBB11_1
; CHECK-NEXT: // %bb.2: // %atomicrmw.end ; CHECK-NEXT: // %bb.2: // %atomicrmw.end
; CHECK-NEXT: adrp x10, :got:var ; CHECK-NEXT: adrp x10, :got:var
; CHECK-NEXT: ldr x10, [x10, :got_lo12:var] ; CHECK-NEXT: ldr x10, [x10, :got_lo12:var]
; CHECK-NEXT: stp x9, x8, [x10] ; CHECK-NEXT: stp x9, x8, [x10]
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llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll

Show First 20 Lines • Show All 807 Lines • ▼ Show 20 Lines
; LLC-NEXT: ret ; LLC-NEXT: ret
; LLC-NEXT: .LBB26_2: // %if.end ; LLC-NEXT: .LBB26_2: // %if.end
; LLC-NEXT: ubfx x8, x0, #32, #16 ; LLC-NEXT: ubfx x8, x0, #32, #16
; LLC-NEXT: cbz w8, .LBB26_4 ; LLC-NEXT: cbz w8, .LBB26_4
; LLC-NEXT: // %bb.3: // %if.then7 ; LLC-NEXT: // %bb.3: // %if.then7
; LLC-NEXT: adrp x9, first_ones ; LLC-NEXT: adrp x9, first_ones
; LLC-NEXT: add x9, x9, :lo12:first_ones ; LLC-NEXT: add x9, x9, :lo12:first_ones
; LLC-NEXT: ldrb w8, [x9, x8] ; LLC-NEXT: ldrb w8, [x9, x8]
; LLC-NEXT: add w0, w8, #16 // =16 ; LLC-NEXT: add w0, w8, #16
; LLC-NEXT: ret ; LLC-NEXT: ret
; LLC-NEXT: .LBB26_4: // %if.end13 ; LLC-NEXT: .LBB26_4: // %if.end13
; LLC-NEXT: ubfx x8, x0, #16, #16 ; LLC-NEXT: ubfx x8, x0, #16, #16
; LLC-NEXT: cbz w8, .LBB26_6 ; LLC-NEXT: cbz w8, .LBB26_6
; LLC-NEXT: // %bb.5: // %if.then17 ; LLC-NEXT: // %bb.5: // %if.then17
; LLC-NEXT: adrp x9, first_ones ; LLC-NEXT: adrp x9, first_ones
; LLC-NEXT: add x9, x9, :lo12:first_ones ; LLC-NEXT: add x9, x9, :lo12:first_ones
; LLC-NEXT: ldrb w8, [x9, x8] ; LLC-NEXT: ldrb w8, [x9, x8]
; LLC-NEXT: add w0, w8, #32 // =32 ; LLC-NEXT: add w0, w8, #32
; LLC-NEXT: ret ; LLC-NEXT: ret
; LLC-NEXT: .LBB26_6: ; LLC-NEXT: .LBB26_6:
; LLC-NEXT: mov w0, #64 ; LLC-NEXT: mov w0, #64
; LLC-NEXT: ret ; LLC-NEXT: ret
; OPT-LABEL: @fct19( ; OPT-LABEL: @fct19(
; OPT-NEXT: entry: ; OPT-NEXT: entry:
; OPT-NEXT: [[X_SROA_1_0_EXTRACT_SHIFT:%.*]] = lshr i64 [[ARG1:%.*]], 16 ; OPT-NEXT: [[X_SROA_1_0_EXTRACT_SHIFT:%.*]] = lshr i64 [[ARG1:%.*]], 16
; OPT-NEXT: [[X_SROA_1_0_EXTRACT_TRUNC:%.*]] = trunc i64 [[X_SROA_1_0_EXTRACT_SHIFT]] to i16 ; OPT-NEXT: [[X_SROA_1_0_EXTRACT_TRUNC:%.*]] = trunc i64 [[X_SROA_1_0_EXTRACT_SHIFT]] to i16
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; LLC-NEXT: movk x12, #11077, lsl #32 ; LLC-NEXT: movk x12, #11077, lsl #32
; LLC-NEXT: extr x8, x1, x0, #18 ; LLC-NEXT: extr x8, x1, x0, #18
; LLC-NEXT: lsr x9, x1, #18 ; LLC-NEXT: lsr x9, x1, #18
; LLC-NEXT: orr x10, x2, x3 ; LLC-NEXT: orr x10, x2, x3
; LLC-NEXT: mov w11, #26220 ; LLC-NEXT: mov w11, #26220
; LLC-NEXT: movk x12, #45, lsl #48 ; LLC-NEXT: movk x12, #45, lsl #48
; LLC-NEXT: and x11, x9, x11 ; LLC-NEXT: and x11, x9, x11
; LLC-NEXT: and x12, x8, x12 ; LLC-NEXT: and x12, x8, x12
; LLC-NEXT: cmp x10, #0 // =0 ; LLC-NEXT: cmp x10, #0
; LLC-NEXT: csel x0, x12, x8, eq ; LLC-NEXT: csel x0, x12, x8, eq
; LLC-NEXT: csel x1, x11, x9, eq ; LLC-NEXT: csel x1, x11, x9, eq
; LLC-NEXT: ret ; LLC-NEXT: ret
; OPT-LABEL: @fct20( ; OPT-LABEL: @fct20(
; OPT-NEXT: entry: ; OPT-NEXT: entry:
; OPT-NEXT: [[SHR:%.*]] = lshr i128 [[A:%.*]], 18 ; OPT-NEXT: [[SHR:%.*]] = lshr i128 [[A:%.*]], 18
; OPT-NEXT: [[CONV:%.*]] = trunc i128 [[SHR]] to i80 ; OPT-NEXT: [[CONV:%.*]] = trunc i128 [[SHR]] to i80
; OPT-NEXT: [[TOBOOL:%.*]] = icmp eq i128 [[B:%.*]], 0 ; OPT-NEXT: [[TOBOOL:%.*]] = icmp eq i128 [[B:%.*]], 0
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llvm/test/CodeGen/AArch64/arm64-ccmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -debugify-and-strip-all-safe -mcpu=cyclone -verify-machineinstrs -aarch64-enable-ccmp -aarch64-stress-ccmp | FileCheck %s ; RUN: llc < %s -debugify-and-strip-all-safe -mcpu=cyclone -verify-machineinstrs -aarch64-enable-ccmp -aarch64-stress-ccmp | FileCheck %s
target triple = "arm64-apple-ios" target triple = "arm64-apple-ios"
define i32 @single_same(i32 %a, i32 %b) nounwind ssp { define i32 @single_same(i32 %a, i32 %b) nounwind ssp {
; CHECK-LABEL: single_same: ; CHECK-LABEL: single_same:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cmp w0, #5 ; =5 ; CHECK-NEXT: cmp w0, #5
; CHECK-NEXT: ccmp w1, #17, #4, ne ; CHECK-NEXT: ccmp w1, #17, #4, ne
; CHECK-NEXT: b.ne LBB0_2 ; CHECK-NEXT: b.ne LBB0_2
; CHECK-NEXT: ; %bb.1: ; %if.then ; CHECK-NEXT: ; %bb.1: ; %if.then
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: bl _foo ; CHECK-NEXT: bl _foo
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: LBB0_2: ; %if.end ; CHECK-NEXT: LBB0_2: ; %if.end
; CHECK-NEXT: mov w0, #7 ; CHECK-NEXT: mov w0, #7
Show All 11 Lines
if.end: if.end:
ret i32 7 ret i32 7
} }
; Different condition codes for the two compares. ; Different condition codes for the two compares.
define i32 @single_different(i32 %a, i32 %b) nounwind ssp { define i32 @single_different(i32 %a, i32 %b) nounwind ssp {
; CHECK-LABEL: single_different: ; CHECK-LABEL: single_different:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cmp w0, #6 ; =6 ; CHECK-NEXT: cmp w0, #6
; CHECK-NEXT: ccmp w1, #17, #0, ge ; CHECK-NEXT: ccmp w1, #17, #0, ge
; CHECK-NEXT: b.eq LBB1_2 ; CHECK-NEXT: b.eq LBB1_2
; CHECK-NEXT: ; %bb.1: ; %if.then ; CHECK-NEXT: ; %bb.1: ; %if.then
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: bl _foo ; CHECK-NEXT: bl _foo
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: LBB1_2: ; %if.end ; CHECK-NEXT: LBB1_2: ; %if.end
; CHECK-NEXT: mov w0, #7 ; CHECK-NEXT: mov w0, #7
Show All 11 Lines
if.end: if.end:
ret i32 7 ret i32 7
} }
; Second block clobbers the flags, can't convert (easily). ; Second block clobbers the flags, can't convert (easily).
define i32 @single_flagclobber(i32 %a, i32 %b) nounwind ssp { define i32 @single_flagclobber(i32 %a, i32 %b) nounwind ssp {
; CHECK-LABEL: single_flagclobber: ; CHECK-LABEL: single_flagclobber:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cmp w0, #5 ; =5 ; CHECK-NEXT: cmp w0, #5
; CHECK-NEXT: b.eq LBB2_2 ; CHECK-NEXT: b.eq LBB2_2
; CHECK-NEXT: ; %bb.1: ; %lor.lhs.false ; CHECK-NEXT: ; %bb.1: ; %lor.lhs.false
; CHECK-NEXT: lsl w8, w1, #1 ; CHECK-NEXT: lsl w8, w1, #1
; CHECK-NEXT: cmp w1, #7 ; =7 ; CHECK-NEXT: cmp w1, #7
; CHECK-NEXT: csinc w8, w8, w1, lt ; CHECK-NEXT: csinc w8, w8, w1, lt
; CHECK-NEXT: cmp w8, #16 ; =16 ; CHECK-NEXT: cmp w8, #16
; CHECK-NEXT: b.gt LBB2_3 ; CHECK-NEXT: b.gt LBB2_3
; CHECK-NEXT: LBB2_2: ; %if.then ; CHECK-NEXT: LBB2_2: ; %if.then
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: bl _foo ; CHECK-NEXT: bl _foo
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: LBB2_3: ; %if.end ; CHECK-NEXT: LBB2_3: ; %if.end
; CHECK-NEXT: mov w0, #7 ; CHECK-NEXT: mov w0, #7
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Show All 16 Lines
if.end: ; preds = %if.then, %lor.lhs.false if.end: ; preds = %if.then, %lor.lhs.false
ret i32 7 ret i32 7
} }
; Second block clobbers the flags and ends with a tbz terminator. ; Second block clobbers the flags and ends with a tbz terminator.
define i32 @single_flagclobber_tbz(i32 %a, i32 %b) nounwind ssp { define i32 @single_flagclobber_tbz(i32 %a, i32 %b) nounwind ssp {
; CHECK-LABEL: single_flagclobber_tbz: ; CHECK-LABEL: single_flagclobber_tbz:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cmp w0, #5 ; =5 ; CHECK-NEXT: cmp w0, #5
; CHECK-NEXT: b.eq LBB3_2 ; CHECK-NEXT: b.eq LBB3_2
; CHECK-NEXT: ; %bb.1: ; %lor.lhs.false ; CHECK-NEXT: ; %bb.1: ; %lor.lhs.false
; CHECK-NEXT: lsl w8, w1, #1 ; CHECK-NEXT: lsl w8, w1, #1
; CHECK-NEXT: cmp w1, #7 ; =7 ; CHECK-NEXT: cmp w1, #7
; CHECK-NEXT: csinc w8, w8, w1, lt ; CHECK-NEXT: csinc w8, w8, w1, lt
; CHECK-NEXT: tbz w8, #3, LBB3_3 ; CHECK-NEXT: tbz w8, #3, LBB3_3
; CHECK-NEXT: LBB3_2: ; %if.then ; CHECK-NEXT: LBB3_2: ; %if.then
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: bl _foo ; CHECK-NEXT: bl _foo
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: LBB3_3: ; %if.end ; CHECK-NEXT: LBB3_3: ; %if.end
; CHECK-NEXT: mov w0, #7 ; CHECK-NEXT: mov w0, #7
Show All 20 Lines
} }
; Speculatively execute division by zero. ; Speculatively execute division by zero.
; The sdiv/udiv instructions do not trap when the divisor is zero, so they are ; The sdiv/udiv instructions do not trap when the divisor is zero, so they are
; safe to speculate. ; safe to speculate.
define i32 @speculate_division(i32 %a, i32 %b) nounwind ssp { define i32 @speculate_division(i32 %a, i32 %b) nounwind ssp {
; CHECK-LABEL: speculate_division: ; CHECK-LABEL: speculate_division:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cmp w0, #1 ; =1 ; CHECK-NEXT: cmp w0, #1
; CHECK-NEXT: sdiv w8, w1, w0 ; CHECK-NEXT: sdiv w8, w1, w0
; CHECK-NEXT: ccmp w8, #16, #0, ge ; CHECK-NEXT: ccmp w8, #16, #0, ge
; CHECK-NEXT: b.le LBB4_2 ; CHECK-NEXT: b.le LBB4_2
; CHECK-NEXT: ; %bb.1: ; %if.end ; CHECK-NEXT: ; %bb.1: ; %if.end
; CHECK-NEXT: mov w0, #7 ; CHECK-NEXT: mov w0, #7
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: LBB4_2: ; %if.then ; CHECK-NEXT: LBB4_2: ; %if.then
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
Show All 17 Lines
if.end: if.end:
ret i32 7 ret i32 7
} }
; Floating point compare. ; Floating point compare.
define i32 @single_fcmp(i32 %a, float %b) nounwind ssp { define i32 @single_fcmp(i32 %a, float %b) nounwind ssp {
; CHECK-LABEL: single_fcmp: ; CHECK-LABEL: single_fcmp:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cmp w0, #1 ; =1 ; CHECK-NEXT: cmp w0, #1
; CHECK-NEXT: scvtf s1, w0 ; CHECK-NEXT: scvtf s1, w0
; CHECK-NEXT: fdiv s0, s0, s1 ; CHECK-NEXT: fdiv s0, s0, s1
; CHECK-NEXT: fmov s1, #17.00000000 ; CHECK-NEXT: fmov s1, #17.00000000
; CHECK-NEXT: fccmp s0, s1, #8, ge ; CHECK-NEXT: fccmp s0, s1, #8, ge
; CHECK-NEXT: b.ge LBB5_2 ; CHECK-NEXT: b.ge LBB5_2
; CHECK-NEXT: ; %bb.1: ; %if.end ; CHECK-NEXT: ; %bb.1: ; %if.end
; CHECK-NEXT: mov w0, #7 ; CHECK-NEXT: mov w0, #7
; CHECK-NEXT: ret ; CHECK-NEXT: ret
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
if.end: if.end:
ret void ret void
} }
; Convert a cbz in the head block. ; Convert a cbz in the head block.
define i32 @cbz_head(i32 %a, i32 %b) nounwind ssp { define i32 @cbz_head(i32 %a, i32 %b) nounwind ssp {
; CHECK-LABEL: cbz_head: ; CHECK-LABEL: cbz_head:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cmp w0, #0 ; =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: ccmp w1, #17, #0, ne ; CHECK-NEXT: ccmp w1, #17, #0, ne
; CHECK-NEXT: b.eq LBB7_2 ; CHECK-NEXT: b.eq LBB7_2
; CHECK-NEXT: ; %bb.1: ; %if.then ; CHECK-NEXT: ; %bb.1: ; %if.then
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: bl _foo ; CHECK-NEXT: bl _foo
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: LBB7_2: ; %if.end ; CHECK-NEXT: LBB7_2: ; %if.end
; CHECK-NEXT: mov w0, #7 ; CHECK-NEXT: mov w0, #7
Show All 13 Lines
} }
; Check that the immediate operand is in range. The ccmp instruction encodes a ; Check that the immediate operand is in range. The ccmp instruction encodes a
; smaller range of immediates than subs/adds. ; smaller range of immediates than subs/adds.
; The ccmp immediates must be in the range 0-31. ; The ccmp immediates must be in the range 0-31.
define i32 @immediate_range(i32 %a, i32 %b) nounwind ssp { define i32 @immediate_range(i32 %a, i32 %b) nounwind ssp {
; CHECK-LABEL: immediate_range: ; CHECK-LABEL: immediate_range:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cmp w0, #5 ; =5 ; CHECK-NEXT: cmp w0, #5
; CHECK-NEXT: b.eq LBB8_3 ; CHECK-NEXT: b.eq LBB8_3
; CHECK-NEXT: ; %bb.1: ; %entry ; CHECK-NEXT: ; %bb.1: ; %entry
; CHECK-NEXT: cmp w1, #32 ; =32 ; CHECK-NEXT: cmp w1, #32
; CHECK-NEXT: b.eq LBB8_3 ; CHECK-NEXT: b.eq LBB8_3
; CHECK-NEXT: ; %bb.2: ; %if.end ; CHECK-NEXT: ; %bb.2: ; %if.end
; CHECK-NEXT: mov w0, #7 ; CHECK-NEXT: mov w0, #7
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: LBB8_3: ; %if.then ; CHECK-NEXT: LBB8_3: ; %if.then
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: bl _foo ; CHECK-NEXT: bl _foo
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
Show All 12 Lines
if.end: if.end:
ret i32 7 ret i32 7
} }
; Convert a cbz in the second block. ; Convert a cbz in the second block.
define i32 @cbz_second(i32 %a, i32 %b) nounwind ssp { define i32 @cbz_second(i32 %a, i32 %b) nounwind ssp {
; CHECK-LABEL: cbz_second: ; CHECK-LABEL: cbz_second:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cmp w0, #0 ; =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: ccmp w1, #0, #0, ne ; CHECK-NEXT: ccmp w1, #0, #0, ne
; CHECK-NEXT: b.eq LBB9_2 ; CHECK-NEXT: b.eq LBB9_2
; CHECK-NEXT: ; %bb.1: ; %if.then ; CHECK-NEXT: ; %bb.1: ; %if.then
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: bl _foo ; CHECK-NEXT: bl _foo
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: LBB9_2: ; %if.end ; CHECK-NEXT: LBB9_2: ; %if.end
; CHECK-NEXT: mov w0, #7 ; CHECK-NEXT: mov w0, #7
Show All 11 Lines
if.end: if.end:
ret i32 7 ret i32 7
} }
; Convert a cbnz in the second block. ; Convert a cbnz in the second block.
define i32 @cbnz_second(i32 %a, i32 %b) nounwind ssp { define i32 @cbnz_second(i32 %a, i32 %b) nounwind ssp {
; CHECK-LABEL: cbnz_second: ; CHECK-LABEL: cbnz_second:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cmp w0, #0 ; =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: ccmp w1, #0, #4, ne ; CHECK-NEXT: ccmp w1, #0, #4, ne
; CHECK-NEXT: b.ne LBB10_2 ; CHECK-NEXT: b.ne LBB10_2
; CHECK-NEXT: ; %bb.1: ; %if.then ; CHECK-NEXT: ; %bb.1: ; %if.then
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: bl _foo ; CHECK-NEXT: bl _foo
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: LBB10_2: ; %if.end ; CHECK-NEXT: LBB10_2: ; %if.end
; CHECK-NEXT: mov w0, #7 ; CHECK-NEXT: mov w0, #7
Show All 16 Lines
%str1 = type { %str2 } %str1 = type { %str2 }
%str2 = type { [24 x i8], i8*, i32, %str1*, i32, [4 x i8], %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, i8*, i8, i8*, %str1*, i8* } %str2 = type { [24 x i8], i8*, i32, %str1*, i32, [4 x i8], %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, i8*, i8, i8*, %str1*, i8* }
; Test case distilled from 126.gcc. ; Test case distilled from 126.gcc.
; The phi in sw.bb.i.i gets multiple operands for the %entry predecessor. ; The phi in sw.bb.i.i gets multiple operands for the %entry predecessor.
define void @build_modify_expr() nounwind ssp { define void @build_modify_expr() nounwind ssp {
; CHECK-LABEL: build_modify_expr: ; CHECK-LABEL: build_modify_expr:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cmp w8, #37 ; =37 ; CHECK-NEXT: cmp w8, #37
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsl x8, x8, xzr ; CHECK-NEXT: lsl x8, x8, xzr
; CHECK-NEXT: mov x9, #31 ; CHECK-NEXT: mov x9, #31
; CHECK-NEXT: movk x9, #48, lsl #32 ; CHECK-NEXT: movk x9, #48, lsl #32
; CHECK-NEXT: and x8, x8, x9 ; CHECK-NEXT: and x8, x8, x9
; CHECK-NEXT: ccmp x8, #0, #4, ls ; CHECK-NEXT: ccmp x8, #0, #4, ls
; CHECK-NEXT: b.eq LBB11_2 ; CHECK-NEXT: b.eq LBB11_2
; CHECK-NEXT: ; %bb.1: ; %if.end85 ; CHECK-NEXT: ; %bb.1: ; %if.end85
Show All 25 Linessw.bb.i.i:
%0 = load %str1*, %str1** %arrayidx.i.i, align 8 %0 = load %str1*, %str1** %arrayidx.i.i, align 8
%code1.i.i.phi.trans.insert = getelementptr inbounds %str1, %str1* %0, i64 0, i32 0, i32 0, i64 16 %code1.i.i.phi.trans.insert = getelementptr inbounds %str1, %str1* %0, i64 0, i32 0, i32 0, i64 16
br label %sw.bb.i.i br label %sw.bb.i.i
} }
define i64 @select_and(i32 %w0, i32 %w1, i64 %x2, i64 %x3) { define i64 @select_and(i32 %w0, i32 %w1, i64 %x2, i64 %x3) {
; CHECK-LABEL: select_and: ; CHECK-LABEL: select_and:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: cmp w1, #5 ; =5 ; CHECK-NEXT: cmp w1, #5
; CHECK-NEXT: ccmp w0, w1, #0, ne ; CHECK-NEXT: ccmp w0, w1, #0, ne
; CHECK-NEXT: csel x0, x2, x3, lt ; CHECK-NEXT: csel x0, x2, x3, lt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = icmp slt i32 %w0, %w1 %1 = icmp slt i32 %w0, %w1
%2 = icmp ne i32 5, %w1 %2 = icmp ne i32 5, %w1
%3 = and i1 %1, %2 %3 = and i1 %1, %2
%sel = select i1 %3, i64 %x2, i64 %x3 %sel = select i1 %3, i64 %x2, i64 %x3
ret i64 %sel ret i64 %sel
} }
define i64 @select_or(i32 %w0, i32 %w1, i64 %x2, i64 %x3) { define i64 @select_or(i32 %w0, i32 %w1, i64 %x2, i64 %x3) {
; CHECK-LABEL: select_or: ; CHECK-LABEL: select_or:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: cmp w1, #5 ; =5 ; CHECK-NEXT: cmp w1, #5
; CHECK-NEXT: ccmp w0, w1, #8, eq ; CHECK-NEXT: ccmp w0, w1, #8, eq
; CHECK-NEXT: csel x0, x2, x3, lt ; CHECK-NEXT: csel x0, x2, x3, lt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = icmp slt i32 %w0, %w1 %1 = icmp slt i32 %w0, %w1
%2 = icmp ne i32 5, %w1 %2 = icmp ne i32 5, %w1
%3 = or i1 %1, %2 %3 = or i1 %1, %2
%sel = select i1 %3, i64 %x2, i64 %x3 %sel = select i1 %3, i64 %x2, i64 %x3
ret i64 %sel ret i64 %sel
} }
define i64 @gccbug(i64 %x0, i64 %x1) { define i64 @gccbug(i64 %x0, i64 %x1) {
; CHECK-LABEL: gccbug: ; CHECK-LABEL: gccbug:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: cmp x0, #2 ; =2 ; CHECK-NEXT: cmp x0, #2
; CHECK-NEXT: ccmp x0, #4, #4, ne ; CHECK-NEXT: ccmp x0, #4, #4, ne
; CHECK-NEXT: ccmp x1, #0, #0, eq ; CHECK-NEXT: ccmp x1, #0, #0, eq
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: cinc x0, x8, eq ; CHECK-NEXT: cinc x0, x8, eq
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%cmp0 = icmp eq i64 %x1, 0 %cmp0 = icmp eq i64 %x1, 0
%cmp1 = icmp eq i64 %x0, 2 %cmp1 = icmp eq i64 %x0, 2
%cmp2 = icmp eq i64 %x0, 4 %cmp2 = icmp eq i64 %x0, 4
%or = or i1 %cmp2, %cmp1 %or = or i1 %cmp2, %cmp1
%and = and i1 %or, %cmp0 %and = and i1 %or, %cmp0
%sel = select i1 %and, i64 2, i64 1 %sel = select i1 %and, i64 2, i64 1
ret i64 %sel ret i64 %sel
} }
define i32 @select_ororand(i32 %w0, i32 %w1, i32 %w2, i32 %w3) { define i32 @select_ororand(i32 %w0, i32 %w1, i32 %w2, i32 %w3) {
; CHECK-LABEL: select_ororand: ; CHECK-LABEL: select_ororand:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: cmp w3, #4 ; =4 ; CHECK-NEXT: cmp w3, #4
; CHECK-NEXT: ccmp w2, #2, #0, gt ; CHECK-NEXT: ccmp w2, #2, #0, gt
; CHECK-NEXT: ccmp w1, #13, #2, ge ; CHECK-NEXT: ccmp w1, #13, #2, ge
; CHECK-NEXT: ccmp w0, #0, #4, ls ; CHECK-NEXT: ccmp w0, #0, #4, ls
; CHECK-NEXT: csel w0, w3, wzr, eq ; CHECK-NEXT: csel w0, w3, wzr, eq
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c0 = icmp eq i32 %w0, 0 %c0 = icmp eq i32 %w0, 0
%c1 = icmp ugt i32 %w1, 13 %c1 = icmp ugt i32 %w1, 13
%c2 = icmp slt i32 %w2, 2 %c2 = icmp slt i32 %w2, 2
Show All 20 Lines; CHECK-NEXT: ret
%and = and i1 %or, %c0 %and = and i1 %or, %c0
%sel = select i1 %and, i32 %v1, i32 %v2 %sel = select i1 %and, i32 %v1, i32 %v2
ret i32 %sel ret i32 %sel
} }
define i64 @select_noccmp1(i64 %v1, i64 %v2, i64 %v3, i64 %r) { define i64 @select_noccmp1(i64 %v1, i64 %v2, i64 %v3, i64 %r) {
; CHECK-LABEL: select_noccmp1: ; CHECK-LABEL: select_noccmp1:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: cmp x0, #0 ; =0 ; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: cset w8, lt ; CHECK-NEXT: cset w8, lt
; CHECK-NEXT: cmp x0, #13 ; =13 ; CHECK-NEXT: cmp x0, #13
; CHECK-NEXT: cset w9, gt ; CHECK-NEXT: cset w9, gt
; CHECK-NEXT: cmp x2, #2 ; =2 ; CHECK-NEXT: cmp x2, #2
; CHECK-NEXT: cset w10, lt ; CHECK-NEXT: cset w10, lt
; CHECK-NEXT: cmp x2, #4 ; =4 ; CHECK-NEXT: cmp x2, #4
; CHECK-NEXT: cset w11, gt ; CHECK-NEXT: cset w11, gt
; CHECK-NEXT: and w8, w8, w9 ; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: and w9, w10, w11 ; CHECK-NEXT: and w9, w10, w11
; CHECK-NEXT: orr w8, w8, w9 ; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: cmp w8, #0 ; =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: csel x0, xzr, x3, ne ; CHECK-NEXT: csel x0, xzr, x3, ne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c0 = icmp slt i64 %v1, 0 %c0 = icmp slt i64 %v1, 0
%c1 = icmp sgt i64 %v1, 13 %c1 = icmp sgt i64 %v1, 13
%c2 = icmp slt i64 %v3, 2 %c2 = icmp slt i64 %v3, 2
%c4 = icmp sgt i64 %v3, 4 %c4 = icmp sgt i64 %v3, 4
%and0 = and i1 %c0, %c1 %and0 = and i1 %c0, %c1
%and1 = and i1 %c2, %c4 %and1 = and i1 %c2, %c4
%or = or i1 %and0, %and1 %or = or i1 %and0, %and1
%sel = select i1 %or, i64 0, i64 %r %sel = select i1 %or, i64 0, i64 %r
ret i64 %sel ret i64 %sel
} }
@g = global i32 0 @g = global i32 0
; Should not use ccmp if we have to compute the or expression in an integer ; Should not use ccmp if we have to compute the or expression in an integer
; register anyway because of other users. ; register anyway because of other users.
define i64 @select_noccmp2(i64 %v1, i64 %v2, i64 %v3, i64 %r) { define i64 @select_noccmp2(i64 %v1, i64 %v2, i64 %v3, i64 %r) {
; CHECK-LABEL: select_noccmp2: ; CHECK-LABEL: select_noccmp2:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: cmp x0, #0 ; =0 ; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: cset w8, lt ; CHECK-NEXT: cset w8, lt
; CHECK-NEXT: cmp x0, #13 ; =13 ; CHECK-NEXT: cmp x0, #13
; CHECK-NEXT: cset w9, gt ; CHECK-NEXT: cset w9, gt
; CHECK-NEXT: orr w8, w8, w9 ; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: cmp w8, #0 ; =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: csel x0, xzr, x3, ne ; CHECK-NEXT: csel x0, xzr, x3, ne
; CHECK-NEXT: sbfx w8, w8, #0, #1 ; CHECK-NEXT: sbfx w8, w8, #0, #1
; CHECK-NEXT: adrp x9, _g@PAGE ; CHECK-NEXT: adrp x9, _g@PAGE
; CHECK-NEXT: str w8, [x9, _g@PAGEOFF] ; CHECK-NEXT: str w8, [x9, _g@PAGEOFF]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c0 = icmp slt i64 %v1, 0 %c0 = icmp slt i64 %v1, 0
%c1 = icmp sgt i64 %v1, 13 %c1 = icmp sgt i64 %v1, 13
%or = or i1 %c0, %c1 %or = or i1 %c0, %c1
%sel = select i1 %or, i64 0, i64 %r %sel = select i1 %or, i64 0, i64 %r
%ext = sext i1 %or to i32 %ext = sext i1 %or to i32
store volatile i32 %ext, i32* @g store volatile i32 %ext, i32* @g
ret i64 %sel ret i64 %sel
} }
; The following is not possible to implement with a single cmp;ccmp;csel ; The following is not possible to implement with a single cmp;ccmp;csel
; sequence. ; sequence.
define i32 @select_noccmp3(i32 %v0, i32 %v1, i32 %v2) { define i32 @select_noccmp3(i32 %v0, i32 %v1, i32 %v2) {
; CHECK-LABEL: select_noccmp3: ; CHECK-LABEL: select_noccmp3:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: cmp w0, #0 ; =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: cset w8, lt ; CHECK-NEXT: cset w8, lt
; CHECK-NEXT: cmp w0, #13 ; =13 ; CHECK-NEXT: cmp w0, #13
; CHECK-NEXT: cset w9, gt ; CHECK-NEXT: cset w9, gt
; CHECK-NEXT: cmp w0, #22 ; =22 ; CHECK-NEXT: cmp w0, #22
; CHECK-NEXT: cset w10, lt ; CHECK-NEXT: cset w10, lt
; CHECK-NEXT: cmp w0, #44 ; =44 ; CHECK-NEXT: cmp w0, #44
; CHECK-NEXT: cset w11, gt ; CHECK-NEXT: cset w11, gt
; CHECK-NEXT: cmp w0, #99 ; =99 ; CHECK-NEXT: cmp w0, #99
; CHECK-NEXT: cset w12, eq ; CHECK-NEXT: cset w12, eq
; CHECK-NEXT: cmp w0, #77 ; =77 ; CHECK-NEXT: cmp w0, #77
; CHECK-NEXT: cset w13, eq ; CHECK-NEXT: cset w13, eq
; CHECK-NEXT: orr w8, w8, w9 ; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: orr w9, w10, w11 ; CHECK-NEXT: orr w9, w10, w11
; CHECK-NEXT: and w8, w8, w9 ; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: orr w9, w12, w13 ; CHECK-NEXT: orr w9, w12, w13
; CHECK-NEXT: tst w8, w9 ; CHECK-NEXT: tst w8, w9
; CHECK-NEXT: csel w0, w1, w2, ne ; CHECK-NEXT: csel w0, w1, w2, ne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
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ret i32 %sel ret i32 %sel
} }
; Also verify that we don't try to generate f128 FCCMPs, using RT calls instead. ; Also verify that we don't try to generate f128 FCCMPs, using RT calls instead.
define i32 @f128_select_and_olt_oge(fp128 %v0, fp128 %v1, fp128 %v2, fp128 %v3, i32 %a, i32 %b) #0 { define i32 @f128_select_and_olt_oge(fp128 %v0, fp128 %v1, fp128 %v2, fp128 %v3, i32 %a, i32 %b) #0 {
; CHECK-LABEL: f128_select_and_olt_oge: ; CHECK-LABEL: f128_select_and_olt_oge:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: sub sp, sp, #80 ; =80 ; CHECK-NEXT: sub sp, sp, #80
; CHECK-NEXT: stp x22, x21, [sp, #32] ; 16-byte Folded Spill ; CHECK-NEXT: stp x22, x21, [sp, #32] ; 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #48] ; 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #48] ; 16-byte Folded Spill
; CHECK-NEXT: stp x29, x30, [sp, #64] ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #64] ; 16-byte Folded Spill
; CHECK-NEXT: mov x19, x1 ; CHECK-NEXT: mov x19, x1
; CHECK-NEXT: mov x20, x0 ; CHECK-NEXT: mov x20, x0
; CHECK-NEXT: stp q2, q3, [sp] ; 32-byte Folded Spill ; CHECK-NEXT: stp q2, q3, [sp] ; 32-byte Folded Spill
; CHECK-NEXT: bl ___lttf2 ; CHECK-NEXT: bl ___lttf2
; CHECK-NEXT: cmp w0, #0 ; =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: cset w21, lt ; CHECK-NEXT: cset w21, lt
; CHECK-NEXT: ldp q0, q1, [sp] ; 32-byte Folded Reload ; CHECK-NEXT: ldp q0, q1, [sp] ; 32-byte Folded Reload
; CHECK-NEXT: bl ___getf2 ; CHECK-NEXT: bl ___getf2
; CHECK-NEXT: cmp w0, #0 ; =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: cset w8, ge ; CHECK-NEXT: cset w8, ge
; CHECK-NEXT: tst w8, w21 ; CHECK-NEXT: tst w8, w21
; CHECK-NEXT: csel w0, w20, w19, ne ; CHECK-NEXT: csel w0, w20, w19, ne
; CHECK-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x20, x19, [sp, #48] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #48] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #32] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #32] ; 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #80 ; =80 ; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c0 = fcmp olt fp128 %v0, %v1 %c0 = fcmp olt fp128 %v0, %v1
%c1 = fcmp oge fp128 %v2, %v3 %c1 = fcmp oge fp128 %v2, %v3
%cr = and i1 %c1, %c0 %cr = and i1 %c1, %c0
%sel = select i1 %cr, i32 %a, i32 %b %sel = select i1 %cr, i32 %a, i32 %b
ret i32 %sel ret i32 %sel
} }
; This testcase resembles the core problem of http://llvm.org/PR39550 ; This testcase resembles the core problem of http://llvm.org/PR39550
; (an OR operation is 2 levels deep but needs to be implemented first) ; (an OR operation is 2 levels deep but needs to be implemented first)
define i32 @deep_or(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %x, i32 %y) { define i32 @deep_or(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %x, i32 %y) {
; CHECK-LABEL: deep_or: ; CHECK-LABEL: deep_or:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: cmp w2, #20 ; =20 ; CHECK-NEXT: cmp w2, #20
; CHECK-NEXT: ccmp w2, #15, #4, ne ; CHECK-NEXT: ccmp w2, #15, #4, ne
; CHECK-NEXT: ccmp w1, #0, #4, eq ; CHECK-NEXT: ccmp w1, #0, #4, eq
; CHECK-NEXT: ccmp w0, #0, #4, ne ; CHECK-NEXT: ccmp w0, #0, #4, ne
; CHECK-NEXT: csel w0, w4, w5, ne ; CHECK-NEXT: csel w0, w4, w5, ne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c0 = icmp ne i32 %a0, 0 %c0 = icmp ne i32 %a0, 0
%c1 = icmp ne i32 %a1, 0 %c1 = icmp ne i32 %a1, 0
%c2 = icmp eq i32 %a2, 15 %c2 = icmp eq i32 %a2, 15
%c3 = icmp eq i32 %a2, 20 %c3 = icmp eq i32 %a2, 20
%or = or i1 %c2, %c3 %or = or i1 %c2, %c3
%and0 = and i1 %or, %c1 %and0 = and i1 %or, %c1
%and1 = and i1 %and0, %c0 %and1 = and i1 %and0, %c0
%sel = select i1 %and1, i32 %x, i32 %y %sel = select i1 %and1, i32 %x, i32 %y
ret i32 %sel ret i32 %sel
} }
; Variation of deep_or, we still need to implement the OR first though. ; Variation of deep_or, we still need to implement the OR first though.
define i32 @deep_or1(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %x, i32 %y) { define i32 @deep_or1(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %x, i32 %y) {
; CHECK-LABEL: deep_or1: ; CHECK-LABEL: deep_or1:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: cmp w2, #20 ; =20 ; CHECK-NEXT: cmp w2, #20
; CHECK-NEXT: ccmp w2, #15, #4, ne ; CHECK-NEXT: ccmp w2, #15, #4, ne
; CHECK-NEXT: ccmp w0, #0, #4, eq ; CHECK-NEXT: ccmp w0, #0, #4, eq
; CHECK-NEXT: ccmp w1, #0, #4, ne ; CHECK-NEXT: ccmp w1, #0, #4, ne
; CHECK-NEXT: csel w0, w4, w5, ne ; CHECK-NEXT: csel w0, w4, w5, ne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c0 = icmp ne i32 %a0, 0 %c0 = icmp ne i32 %a0, 0
%c1 = icmp ne i32 %a1, 0 %c1 = icmp ne i32 %a1, 0
%c2 = icmp eq i32 %a2, 15 %c2 = icmp eq i32 %a2, 15
%c3 = icmp eq i32 %a2, 20 %c3 = icmp eq i32 %a2, 20
%or = or i1 %c2, %c3 %or = or i1 %c2, %c3
%and0 = and i1 %c0, %or %and0 = and i1 %c0, %or
%and1 = and i1 %and0, %c1 %and1 = and i1 %and0, %c1
%sel = select i1 %and1, i32 %x, i32 %y %sel = select i1 %and1, i32 %x, i32 %y
ret i32 %sel ret i32 %sel
} }
; Variation of deep_or, we still need to implement the OR first though. ; Variation of deep_or, we still need to implement the OR first though.
define i32 @deep_or2(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %x, i32 %y) { define i32 @deep_or2(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %x, i32 %y) {
; CHECK-LABEL: deep_or2: ; CHECK-LABEL: deep_or2:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: cmp w2, #20 ; =20 ; CHECK-NEXT: cmp w2, #20
; CHECK-NEXT: ccmp w2, #15, #4, ne ; CHECK-NEXT: ccmp w2, #15, #4, ne
; CHECK-NEXT: ccmp w1, #0, #4, eq ; CHECK-NEXT: ccmp w1, #0, #4, eq
; CHECK-NEXT: ccmp w0, #0, #4, ne ; CHECK-NEXT: ccmp w0, #0, #4, ne
; CHECK-NEXT: csel w0, w4, w5, ne ; CHECK-NEXT: csel w0, w4, w5, ne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c0 = icmp ne i32 %a0, 0 %c0 = icmp ne i32 %a0, 0
%c1 = icmp ne i32 %a1, 0 %c1 = icmp ne i32 %a1, 0
%c2 = icmp eq i32 %a2, 15 %c2 = icmp eq i32 %a2, 15
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llvm/test/CodeGen/AArch64/arm64-fp128.ll

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} }
@var32 = dso_local global i32 0 @var32 = dso_local global i32 0
@var64 = dso_local global i64 0 @var64 = dso_local global i64 0
define dso_local void @test_fptosi() { define dso_local void @test_fptosi() {
; CHECK-LABEL: test_fptosi: ; CHECK-LABEL: test_fptosi:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: adrp x8, lhs ; CHECK-NEXT: adrp x8, lhs
; CHECK-NEXT: ldr q0, [x8, :lo12:lhs] ; CHECK-NEXT: ldr q0, [x8, :lo12:lhs]
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl __fixtfsi ; CHECK-NEXT: bl __fixtfsi
; CHECK-NEXT: adrp x8, var32 ; CHECK-NEXT: adrp x8, var32
; CHECK-NEXT: str w0, [x8, :lo12:var32] ; CHECK-NEXT: str w0, [x8, :lo12:var32]
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: bl __fixtfdi ; CHECK-NEXT: bl __fixtfdi
; CHECK-NEXT: adrp x8, var64 ; CHECK-NEXT: adrp x8, var64
; CHECK-NEXT: str x0, [x8, :lo12:var64] ; CHECK-NEXT: str x0, [x8, :lo12:var64]
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val = load fp128, fp128* @lhs, align 16 %val = load fp128, fp128* @lhs, align 16
%val32 = fptosi fp128 %val to i32 %val32 = fptosi fp128 %val to i32
store i32 %val32, i32* @var32 store i32 %val32, i32* @var32
%val64 = fptosi fp128 %val to i64 %val64 = fptosi fp128 %val to i64
store i64 %val64, i64* @var64 store i64 %val64, i64* @var64
ret void ret void
} }
define dso_local void @test_fptoui() { define dso_local void @test_fptoui() {
; CHECK-LABEL: test_fptoui: ; CHECK-LABEL: test_fptoui:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: adrp x8, lhs ; CHECK-NEXT: adrp x8, lhs
; CHECK-NEXT: ldr q0, [x8, :lo12:lhs] ; CHECK-NEXT: ldr q0, [x8, :lo12:lhs]
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl __fixunstfsi ; CHECK-NEXT: bl __fixunstfsi
; CHECK-NEXT: adrp x8, var32 ; CHECK-NEXT: adrp x8, var32
; CHECK-NEXT: str w0, [x8, :lo12:var32] ; CHECK-NEXT: str w0, [x8, :lo12:var32]
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: bl __fixunstfdi ; CHECK-NEXT: bl __fixunstfdi
; CHECK-NEXT: adrp x8, var64 ; CHECK-NEXT: adrp x8, var64
; CHECK-NEXT: str x0, [x8, :lo12:var64] ; CHECK-NEXT: str x0, [x8, :lo12:var64]
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val = load fp128, fp128* @lhs, align 16 %val = load fp128, fp128* @lhs, align 16
%val32 = fptoui fp128 %val to i32 %val32 = fptoui fp128 %val to i32
store i32 %val32, i32* @var32 store i32 %val32, i32* @var32
%val64 = fptoui fp128 %val to i64 %val64 = fptoui fp128 %val to i64
store i64 %val64, i64* @var64 store i64 %val64, i64* @var64
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; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: adrp x8, lhs ; CHECK-NEXT: adrp x8, lhs
; CHECK-NEXT: ldr q0, [x8, :lo12:lhs] ; CHECK-NEXT: ldr q0, [x8, :lo12:lhs]
; CHECK-NEXT: adrp x8, rhs ; CHECK-NEXT: adrp x8, rhs
; CHECK-NEXT: ldr q1, [x8, :lo12:rhs] ; CHECK-NEXT: ldr q1, [x8, :lo12:rhs]
; CHECK-NEXT: bl __letf2 ; CHECK-NEXT: bl __letf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: cset w0, le ; CHECK-NEXT: cset w0, le
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%lhs = load fp128, fp128* @lhs, align 16 %lhs = load fp128, fp128* @lhs, align 16
%rhs = load fp128, fp128* @rhs, align 16 %rhs = load fp128, fp128* @rhs, align 16
; Technically, everything after the call to __letf2 is redundant, but we'll let ; Technically, everything after the call to __letf2 is redundant, but we'll let
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; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: adrp x8, lhs ; CHECK-NEXT: adrp x8, lhs
; CHECK-NEXT: ldr q0, [x8, :lo12:lhs] ; CHECK-NEXT: ldr q0, [x8, :lo12:lhs]
; CHECK-NEXT: adrp x8, rhs ; CHECK-NEXT: adrp x8, rhs
; CHECK-NEXT: ldr q1, [x8, :lo12:rhs] ; CHECK-NEXT: ldr q1, [x8, :lo12:rhs]
; CHECK-NEXT: bl __letf2 ; CHECK-NEXT: bl __letf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: cset w0, gt ; CHECK-NEXT: cset w0, gt
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%lhs = load fp128, fp128* @lhs, align 16 %lhs = load fp128, fp128* @lhs, align 16
%rhs = load fp128, fp128* @rhs, align 16 %rhs = load fp128, fp128* @rhs, align 16
%val = fcmp ugt fp128 %lhs, %rhs %val = fcmp ugt fp128 %lhs, %rhs
ret i1 %val ret i1 %val
} }
define dso_local i1 @test_setcc3() { define dso_local i1 @test_setcc3() {
; CHECK-LABEL: test_setcc3: ; CHECK-LABEL: test_setcc3:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: stp x30, x19, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x19, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: adrp x8, lhs ; CHECK-NEXT: adrp x8, lhs
; CHECK-NEXT: ldr q0, [x8, :lo12:lhs] ; CHECK-NEXT: ldr q0, [x8, :lo12:lhs]
; CHECK-NEXT: adrp x8, rhs ; CHECK-NEXT: adrp x8, rhs
; CHECK-NEXT: ldr q1, [x8, :lo12:rhs] ; CHECK-NEXT: ldr q1, [x8, :lo12:rhs]
; CHECK-NEXT: stp q1, q0, [sp] // 32-byte Folded Spill ; CHECK-NEXT: stp q1, q0, [sp] // 32-byte Folded Spill
; CHECK-NEXT: bl __eqtf2 ; CHECK-NEXT: bl __eqtf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: cset w19, eq ; CHECK-NEXT: cset w19, eq
; CHECK-NEXT: ldp q1, q0, [sp] // 32-byte Folded Reload ; CHECK-NEXT: ldp q1, q0, [sp] // 32-byte Folded Reload
; CHECK-NEXT: bl __unordtf2 ; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: cset w8, ne ; CHECK-NEXT: cset w8, ne
; CHECK-NEXT: orr w0, w8, w19 ; CHECK-NEXT: orr w0, w8, w19
; CHECK-NEXT: ldp x30, x19, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #48 // =48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%lhs = load fp128, fp128* @lhs, align 16 %lhs = load fp128, fp128* @lhs, align 16
%rhs = load fp128, fp128* @rhs, align 16 %rhs = load fp128, fp128* @rhs, align 16
%val = fcmp ueq fp128 %lhs, %rhs %val = fcmp ueq fp128 %lhs, %rhs
ret i1 %val ret i1 %val
} }
define dso_local i32 @test_br_cc() { define dso_local i32 @test_br_cc() {
; CHECK-LABEL: test_br_cc: ; CHECK-LABEL: test_br_cc:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: adrp x8, lhs ; CHECK-NEXT: adrp x8, lhs
; CHECK-NEXT: ldr q0, [x8, :lo12:lhs] ; CHECK-NEXT: ldr q0, [x8, :lo12:lhs]
; CHECK-NEXT: adrp x8, rhs ; CHECK-NEXT: adrp x8, rhs
; CHECK-NEXT: ldr q1, [x8, :lo12:rhs] ; CHECK-NEXT: ldr q1, [x8, :lo12:rhs]
; CHECK-NEXT: bl __lttf2 ; CHECK-NEXT: bl __lttf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: b.ge .LBB11_2 ; CHECK-NEXT: b.ge .LBB11_2
; CHECK-NEXT: // %bb.1: // %iftrue ; CHECK-NEXT: // %bb.1: // %iftrue
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB11_2: // %iffalse ; CHECK-NEXT: .LBB11_2: // %iffalse
; CHECK-NEXT: mov w0, #29 ; CHECK-NEXT: mov w0, #29
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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@varhalf = dso_local global half 0.0, align 2 @varhalf = dso_local global half 0.0, align 2
@varfloat = dso_local global float 0.0, align 4 @varfloat = dso_local global float 0.0, align 4
@vardouble = dso_local global double 0.0, align 8 @vardouble = dso_local global double 0.0, align 8
define dso_local void @test_round() { define dso_local void @test_round() {
; CHECK-LABEL: test_round: ; CHECK-LABEL: test_round:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: adrp x8, lhs ; CHECK-NEXT: adrp x8, lhs
; CHECK-NEXT: ldr q0, [x8, :lo12:lhs] ; CHECK-NEXT: ldr q0, [x8, :lo12:lhs]
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl __trunctfhf2 ; CHECK-NEXT: bl __trunctfhf2
; CHECK-NEXT: adrp x8, varhalf ; CHECK-NEXT: adrp x8, varhalf
; CHECK-NEXT: str h0, [x8, :lo12:varhalf] ; CHECK-NEXT: str h0, [x8, :lo12:varhalf]
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: bl __trunctfsf2 ; CHECK-NEXT: bl __trunctfsf2
; CHECK-NEXT: adrp x8, varfloat ; CHECK-NEXT: adrp x8, varfloat
; CHECK-NEXT: str s0, [x8, :lo12:varfloat] ; CHECK-NEXT: str s0, [x8, :lo12:varfloat]
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: bl __trunctfdf2 ; CHECK-NEXT: bl __trunctfdf2
; CHECK-NEXT: adrp x8, vardouble ; CHECK-NEXT: adrp x8, vardouble
; CHECK-NEXT: str d0, [x8, :lo12:vardouble] ; CHECK-NEXT: str d0, [x8, :lo12:vardouble]
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val = load fp128, fp128* @lhs, align 16 %val = load fp128, fp128* @lhs, align 16
%half = fptrunc fp128 %val to half %half = fptrunc fp128 %val to half
store half %half, half* @varhalf, align 2 store half %half, half* @varhalf, align 2
%float = fptrunc fp128 %val to float %float = fptrunc fp128 %val to float
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llvm/test/CodeGen/AArch64/arm64-memset-inline.ll

Show First 20 Lines • Show All 227 Lines • ▼ Show 20 Lines; CHECK-NEXT: bl something
call void @something(i8* %cast) call void @something(i8* %cast)
ret void ret void
} }
define void @memset_8_stack() { define void @memset_8_stack() {
; CHECK-LABEL: memset_8_stack: ; CHECK-LABEL: memset_8_stack:
; CHECK: mov x8, #-6148914691236517206 ; CHECK: mov x8, #-6148914691236517206
; CHECK-NEXT: stp x30, x8, [sp, #-16]! ; CHECK-NEXT: stp x30, x8, [sp, #-16]!
; CHECK-NEXT: add x0, sp, #8 // =8 ; CHECK-NEXT: add x0, sp, #8
; CHECK-NEXT: bl something ; CHECK-NEXT: bl something
%buf = alloca [8 x i8], align 1 %buf = alloca [8 x i8], align 1
%cast = bitcast [8 x i8]* %buf to i8* %cast = bitcast [8 x i8]* %buf to i8*
call void @llvm.memset.p0i8.i32(i8* %cast, i8 -86, i32 8, i1 false) call void @llvm.memset.p0i8.i32(i8* %cast, i8 -86, i32 8, i1 false)
call void @something(i8* %cast) call void @something(i8* %cast)
ret void ret void
} }
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llvm/test/CodeGen/AArch64/arm64-neon-copy.ll

Show First 20 Lines • Show All 1,231 Lines • ▼ Show 20 Lines
; CHECK-NEXT: and x8, x0, #0x7 ; CHECK-NEXT: and x8, x0, #0x7
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: bfi x9, x8, #1, #3 ; CHECK-NEXT: bfi x9, x8, #1, #3
; CHECK-NEXT: ldr h1, [x9] ; CHECK-NEXT: ldr h1, [x9]
; CHECK-NEXT: mov v1.h[1], v0.h[1] ; CHECK-NEXT: mov v1.h[1], v0.h[1]
; CHECK-NEXT: mov v1.h[2], v0.h[2] ; CHECK-NEXT: mov v1.h[2], v0.h[2]
; CHECK-NEXT: mov v1.h[3], v0.h[3] ; CHECK-NEXT: mov v1.h[3], v0.h[3]
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #16 // =16 ; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = extractelement <8 x i16> %x, i32 %idx %tmp = extractelement <8 x i16> %x, i32 %idx
%tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 0 %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 0
%tmp3 = extractelement <8 x i16> %x, i32 1 %tmp3 = extractelement <8 x i16> %x, i32 1
%tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 1 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 1
%tmp5 = extractelement <8 x i16> %x, i32 2 %tmp5 = extractelement <8 x i16> %x, i32 2
%tmp6 = insertelement <4 x i16> %tmp4, i16 %tmp5, i32 2 %tmp6 = insertelement <4 x i16> %tmp4, i16 %tmp5, i32 2
%tmp7 = extractelement <8 x i16> %x, i32 3 %tmp7 = extractelement <8 x i16> %x, i32 3
%tmp8 = insertelement <4 x i16> %tmp6, i16 %tmp7, i32 3 %tmp8 = insertelement <4 x i16> %tmp6, i16 %tmp7, i32 3
ret <4 x i16> %tmp8 ret <4 x i16> %tmp8
} }
define <4 x i16> @test_extracts_inserts_varidx_insert(<8 x i16> %x, i32 %idx) { define <4 x i16> @test_extracts_inserts_varidx_insert(<8 x i16> %x, i32 %idx) {
; CHECK-LABEL: test_extracts_inserts_varidx_insert: ; CHECK-LABEL: test_extracts_inserts_varidx_insert:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #16 // =16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 ; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: and x8, x0, #0x3 ; CHECK-NEXT: and x8, x0, #0x3
; CHECK-NEXT: add x9, sp, #8 // =8 ; CHECK-NEXT: add x9, sp, #8
; CHECK-NEXT: bfi x9, x8, #1, #2 ; CHECK-NEXT: bfi x9, x8, #1, #2
; CHECK-NEXT: str h0, [x9] ; CHECK-NEXT: str h0, [x9]
; CHECK-NEXT: ldr d1, [sp, #8] ; CHECK-NEXT: ldr d1, [sp, #8]
; CHECK-NEXT: mov v1.h[1], v0.h[1] ; CHECK-NEXT: mov v1.h[1], v0.h[1]
; CHECK-NEXT: mov v1.h[2], v0.h[2] ; CHECK-NEXT: mov v1.h[2], v0.h[2]
; CHECK-NEXT: mov v1.h[3], v0.h[3] ; CHECK-NEXT: mov v1.h[3], v0.h[3]
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #16 // =16 ; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = extractelement <8 x i16> %x, i32 0 %tmp = extractelement <8 x i16> %x, i32 0
%tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 %idx %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 %idx
%tmp3 = extractelement <8 x i16> %x, i32 1 %tmp3 = extractelement <8 x i16> %x, i32 1
%tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 1 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 1
%tmp5 = extractelement <8 x i16> %x, i32 2 %tmp5 = extractelement <8 x i16> %x, i32 2
%tmp6 = insertelement <4 x i16> %tmp4, i16 %tmp5, i32 2 %tmp6 = insertelement <4 x i16> %tmp4, i16 %tmp5, i32 2
%tmp7 = extractelement <8 x i16> %x, i32 3 %tmp7 = extractelement <8 x i16> %x, i32 3
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llvm/test/CodeGen/AArch64/arm64-nvcast.ll

; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
define void @test(float * %p1, i32 %v1) { define void @test(float * %p1, i32 %v1) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: sub sp, sp, #16 ; =16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1 ; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: fmov.2d v0, #2.00000000 ; CHECK-NEXT: fmov.2d v0, #2.00000000
; CHECK-NEXT: and x8, x1, #0x3 ; CHECK-NEXT: and x8, x1, #0x3
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: str q0, [sp] ; CHECK-NEXT: str q0, [sp]
; CHECK-NEXT: bfi x9, x8, #2, #2 ; CHECK-NEXT: bfi x9, x8, #2, #2
; CHECK-NEXT: ldr s0, [x9] ; CHECK-NEXT: ldr s0, [x9]
; CHECK-NEXT: str s0, [x0] ; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: add sp, sp, #16 ; =16 ; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%v2 = extractelement <3 x float> <float 0.000000e+00, float 2.000000e+00, float 0.000000e+00>, i32 %v1 %v2 = extractelement <3 x float> <float 0.000000e+00, float 2.000000e+00, float 0.000000e+00>, i32 %v1
store float %v2, float* %p1, align 4 store float %v2, float* %p1, align 4
ret void ret void
} }
define void @test2(float * %p1, i32 %v1) { define void @test2(float * %p1, i32 %v1) {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: sub sp, sp, #16 ; =16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1 ; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: movi.16b v0, #63 ; CHECK-NEXT: movi.16b v0, #63
; CHECK-NEXT: and x8, x1, #0x3 ; CHECK-NEXT: and x8, x1, #0x3
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: str q0, [sp] ; CHECK-NEXT: str q0, [sp]
; CHECK-NEXT: bfi x9, x8, #2, #2 ; CHECK-NEXT: bfi x9, x8, #2, #2
; CHECK-NEXT: ldr s0, [x9] ; CHECK-NEXT: ldr s0, [x9]
; CHECK-NEXT: str s0, [x0] ; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: add sp, sp, #16 ; =16 ; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%v2 = extractelement <3 x float> <float 0.7470588088035583, float 0.7470588088035583, float 0.7470588088035583>, i32 %v1 %v2 = extractelement <3 x float> <float 0.7470588088035583, float 0.7470588088035583, float 0.7470588088035583>, i32 %v1
store float %v2, float* %p1, align 4 store float %v2, float* %p1, align 4
ret void ret void
} }
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llvm/test/CodeGen/AArch64/arm64-popcnt.ll

Show First 20 Lines • Show All 166 Lines • ▼ Show 20 Lines
define i32 @ctpop_eq_one(i64 %x) nounwind readnone { define i32 @ctpop_eq_one(i64 %x) nounwind readnone {
; CHECK-LABEL: ctpop_eq_one: ; CHECK-LABEL: ctpop_eq_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fmov d0, x0 ; CHECK-NEXT: fmov d0, x0
; CHECK-NEXT: cnt.8b v0, v0 ; CHECK-NEXT: cnt.8b v0, v0
; CHECK-NEXT: uaddlv.8b h0, v0 ; CHECK-NEXT: uaddlv.8b h0, v0
; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: cmp x8, #1 // =1 ; CHECK-NEXT: cmp x8, #1
; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECK-NONEON-LABEL: ctpop_eq_one: ; CHECK-NONEON-LABEL: ctpop_eq_one:
; CHECK-NONEON: // %bb.0: ; CHECK-NONEON: // %bb.0:
; CHECK-NONEON-NEXT: lsr x8, x0, #1 ; CHECK-NONEON-NEXT: lsr x8, x0, #1
; CHECK-NONEON-NEXT: and x8, x8, #0x5555555555555555 ; CHECK-NONEON-NEXT: and x8, x8, #0x5555555555555555
; CHECK-NONEON-NEXT: sub x8, x0, x8 ; CHECK-NONEON-NEXT: sub x8, x0, x8
; CHECK-NONEON-NEXT: and x9, x8, #0x3333333333333333 ; CHECK-NONEON-NEXT: and x9, x8, #0x3333333333333333
; CHECK-NONEON-NEXT: lsr x8, x8, #2 ; CHECK-NONEON-NEXT: lsr x8, x8, #2
; CHECK-NONEON-NEXT: and x8, x8, #0x3333333333333333 ; CHECK-NONEON-NEXT: and x8, x8, #0x3333333333333333
; CHECK-NONEON-NEXT: add x8, x9, x8 ; CHECK-NONEON-NEXT: add x8, x9, x8
; CHECK-NONEON-NEXT: add x8, x8, x8, lsr #4 ; CHECK-NONEON-NEXT: add x8, x8, x8, lsr #4
; CHECK-NONEON-NEXT: and x8, x8, #0xf0f0f0f0f0f0f0f ; CHECK-NONEON-NEXT: and x8, x8, #0xf0f0f0f0f0f0f0f
; CHECK-NONEON-NEXT: mov x9, #72340172838076673 ; CHECK-NONEON-NEXT: mov x9, #72340172838076673
; CHECK-NONEON-NEXT: mul x8, x8, x9 ; CHECK-NONEON-NEXT: mul x8, x8, x9
; CHECK-NONEON-NEXT: lsr x8, x8, #56 ; CHECK-NONEON-NEXT: lsr x8, x8, #56
; CHECK-NONEON-NEXT: cmp x8, #1 // =1 ; CHECK-NONEON-NEXT: cmp x8, #1
; CHECK-NONEON-NEXT: cset w0, eq ; CHECK-NONEON-NEXT: cset w0, eq
; CHECK-NONEON-NEXT: ret ; CHECK-NONEON-NEXT: ret
%count = tail call i64 @llvm.ctpop.i64(i64 %x) %count = tail call i64 @llvm.ctpop.i64(i64 %x)
%cmp = icmp eq i64 %count, 1 %cmp = icmp eq i64 %count, 1
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @ctpop_ne_one(i64 %x) nounwind readnone { define i32 @ctpop_ne_one(i64 %x) nounwind readnone {
; CHECK-LABEL: ctpop_ne_one: ; CHECK-LABEL: ctpop_ne_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fmov d0, x0 ; CHECK-NEXT: fmov d0, x0
; CHECK-NEXT: cnt.8b v0, v0 ; CHECK-NEXT: cnt.8b v0, v0
; CHECK-NEXT: uaddlv.8b h0, v0 ; CHECK-NEXT: uaddlv.8b h0, v0
; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: cmp x8, #1 // =1 ; CHECK-NEXT: cmp x8, #1
; CHECK-NEXT: cset w0, ne ; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECK-NONEON-LABEL: ctpop_ne_one: ; CHECK-NONEON-LABEL: ctpop_ne_one:
; CHECK-NONEON: // %bb.0: ; CHECK-NONEON: // %bb.0:
; CHECK-NONEON-NEXT: lsr x8, x0, #1 ; CHECK-NONEON-NEXT: lsr x8, x0, #1
; CHECK-NONEON-NEXT: and x8, x8, #0x5555555555555555 ; CHECK-NONEON-NEXT: and x8, x8, #0x5555555555555555
; CHECK-NONEON-NEXT: sub x8, x0, x8 ; CHECK-NONEON-NEXT: sub x8, x0, x8
; CHECK-NONEON-NEXT: and x9, x8, #0x3333333333333333 ; CHECK-NONEON-NEXT: and x9, x8, #0x3333333333333333
; CHECK-NONEON-NEXT: lsr x8, x8, #2 ; CHECK-NONEON-NEXT: lsr x8, x8, #2
; CHECK-NONEON-NEXT: and x8, x8, #0x3333333333333333 ; CHECK-NONEON-NEXT: and x8, x8, #0x3333333333333333
; CHECK-NONEON-NEXT: add x8, x9, x8 ; CHECK-NONEON-NEXT: add x8, x9, x8
; CHECK-NONEON-NEXT: add x8, x8, x8, lsr #4 ; CHECK-NONEON-NEXT: add x8, x8, x8, lsr #4
; CHECK-NONEON-NEXT: and x8, x8, #0xf0f0f0f0f0f0f0f ; CHECK-NONEON-NEXT: and x8, x8, #0xf0f0f0f0f0f0f0f
; CHECK-NONEON-NEXT: mov x9, #72340172838076673 ; CHECK-NONEON-NEXT: mov x9, #72340172838076673
; CHECK-NONEON-NEXT: mul x8, x8, x9 ; CHECK-NONEON-NEXT: mul x8, x8, x9
; CHECK-NONEON-NEXT: lsr x8, x8, #56 ; CHECK-NONEON-NEXT: lsr x8, x8, #56
; CHECK-NONEON-NEXT: cmp x8, #1 // =1 ; CHECK-NONEON-NEXT: cmp x8, #1
; CHECK-NONEON-NEXT: cset w0, ne ; CHECK-NONEON-NEXT: cset w0, ne
; CHECK-NONEON-NEXT: ret ; CHECK-NONEON-NEXT: ret
%count = tail call i64 @llvm.ctpop.i64(i64 %x) %count = tail call i64 @llvm.ctpop.i64(i64 %x)
%cmp = icmp ne i64 %count, 1 %cmp = icmp ne i64 %count, 1
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
declare i32 @llvm.ctpop.i32(i32) nounwind readnone declare i32 @llvm.ctpop.i32(i32) nounwind readnone
declare i64 @llvm.ctpop.i64(i64) nounwind readnone declare i64 @llvm.ctpop.i64(i64) nounwind readnone

llvm/test/CodeGen/AArch64/arm64-rev.ll

Show First 20 Lines • Show All 529 Lines • ▼ Show 20 Lines; GISEL-NEXT: ret
ret <8 x i16> %tmp2 ret <8 x i16> %tmp2
} }
; vrev <4 x i16> should use REV32 and not REV64 ; vrev <4 x i16> should use REV32 and not REV64
define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp { define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
; CHECK-LABEL: test_vrev64: ; CHECK-LABEL: test_vrev64:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: add x8, x1, #2 // =2 ; CHECK-NEXT: add x8, x1, #2
; CHECK-NEXT: st1.h { v0 }[5], [x8] ; CHECK-NEXT: st1.h { v0 }[5], [x8]
; CHECK-NEXT: st1.h { v0 }[6], [x1] ; CHECK-NEXT: st1.h { v0 }[6], [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: test_vrev64: ; GISEL-LABEL: test_vrev64:
; GISEL: // %bb.0: // %entry ; GISEL: // %bb.0: // %entry
; GISEL-NEXT: ldr q0, [x0] ; GISEL-NEXT: ldr q0, [x0]
; GISEL-NEXT: add x8, x1, #2 // =2 ; GISEL-NEXT: add x8, x1, #2
; GISEL-NEXT: st1.h { v0 }[6], [x1] ; GISEL-NEXT: st1.h { v0 }[6], [x1]
; GISEL-NEXT: st1.h { v0 }[5], [x8] ; GISEL-NEXT: st1.h { v0 }[5], [x8]
; GISEL-NEXT: ret ; GISEL-NEXT: ret
entry: entry:
%0 = bitcast <4 x i16>* %source to <8 x i16>* %0 = bitcast <4 x i16>* %source to <8 x i16>*
%tmp2 = load <8 x i16>, <8 x i16>* %0, align 4 %tmp2 = load <8 x i16>, <8 x i16>* %0, align 4
%tmp3 = extractelement <8 x i16> %tmp2, i32 6 %tmp3 = extractelement <8 x i16> %tmp2, i32 6
%tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0 %tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -debugify-and-strip-all-safe %s -o - -mtriple=arm64-apple-ios -enable-shrink-wrap=true -disable-post-ra -frame-pointer=non-leaf | FileCheck %s --check-prefix=ENABLE ; RUN: llc -debugify-and-strip-all-safe %s -o - -mtriple=arm64-apple-ios -enable-shrink-wrap=true -disable-post-ra -frame-pointer=non-leaf | FileCheck %s --check-prefix=ENABLE
; RUN: llc -debugify-and-strip-all-safe %s -o - -enable-shrink-wrap=false -disable-post-ra -frame-pointer=non-leaf | FileCheck %s --check-prefix=DISABLE ; RUN: llc -debugify-and-strip-all-safe %s -o - -enable-shrink-wrap=false -disable-post-ra -frame-pointer=non-leaf | FileCheck %s --check-prefix=DISABLE
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios" target triple = "arm64-apple-ios"
; Initial motivating example: Simple diamond with a call just on one side. ; Initial motivating example: Simple diamond with a call just on one side.
define i32 @foo(i32 %a, i32 %b) { define i32 @foo(i32 %a, i32 %b) {
; ENABLE-LABEL: foo: ; ENABLE-LABEL: foo:
; ENABLE: ; %bb.0: ; ENABLE: ; %bb.0:
; ENABLE-NEXT: cmp w0, w1 ; ENABLE-NEXT: cmp w0, w1
; ENABLE-NEXT: b.ge LBB0_2 ; ENABLE-NEXT: b.ge LBB0_2
; ENABLE-NEXT: ; %bb.1: ; %true ; ENABLE-NEXT: ; %bb.1: ; %true
; ENABLE-NEXT: sub sp, sp, #32 ; =32 ; ENABLE-NEXT: sub sp, sp, #32
; ENABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill ; ENABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; ENABLE-NEXT: add x29, sp, #16 ; =16 ; ENABLE-NEXT: add x29, sp, #16
; ENABLE-NEXT: .cfi_def_cfa w29, 16 ; ENABLE-NEXT: .cfi_def_cfa w29, 16
; ENABLE-NEXT: .cfi_offset w30, -8 ; ENABLE-NEXT: .cfi_offset w30, -8
; ENABLE-NEXT: .cfi_offset w29, -16 ; ENABLE-NEXT: .cfi_offset w29, -16
; ENABLE-NEXT: stur w0, [x29, #-4] ; ENABLE-NEXT: stur w0, [x29, #-4]
; ENABLE-NEXT: sub x1, x29, #4 ; =4 ; ENABLE-NEXT: sub x1, x29, #4
; ENABLE-NEXT: mov w0, wzr ; ENABLE-NEXT: mov w0, wzr
; ENABLE-NEXT: bl _doSomething ; ENABLE-NEXT: bl _doSomething
; ENABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; ENABLE-NEXT: add sp, sp, #32 ; =32 ; ENABLE-NEXT: add sp, sp, #32
; ENABLE-NEXT: LBB0_2: ; %false ; ENABLE-NEXT: LBB0_2: ; %false
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ;
; DISABLE-LABEL: foo: ; DISABLE-LABEL: foo:
; DISABLE: ; %bb.0: ; DISABLE: ; %bb.0:
; DISABLE-NEXT: sub sp, sp, #32 ; =32 ; DISABLE-NEXT: sub sp, sp, #32
; DISABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill ; DISABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; DISABLE-NEXT: add x29, sp, #16 ; =16 ; DISABLE-NEXT: add x29, sp, #16
; DISABLE-NEXT: .cfi_def_cfa w29, 16 ; DISABLE-NEXT: .cfi_def_cfa w29, 16
; DISABLE-NEXT: .cfi_offset w30, -8 ; DISABLE-NEXT: .cfi_offset w30, -8
; DISABLE-NEXT: .cfi_offset w29, -16 ; DISABLE-NEXT: .cfi_offset w29, -16
; DISABLE-NEXT: cmp w0, w1 ; DISABLE-NEXT: cmp w0, w1
; DISABLE-NEXT: b.ge LBB0_2 ; DISABLE-NEXT: b.ge LBB0_2
; DISABLE-NEXT: ; %bb.1: ; %true ; DISABLE-NEXT: ; %bb.1: ; %true
; DISABLE-NEXT: stur w0, [x29, #-4] ; DISABLE-NEXT: stur w0, [x29, #-4]
; DISABLE-NEXT: sub x1, x29, #4 ; =4 ; DISABLE-NEXT: sub x1, x29, #4
; DISABLE-NEXT: mov w0, wzr ; DISABLE-NEXT: mov w0, wzr
; DISABLE-NEXT: bl _doSomething ; DISABLE-NEXT: bl _doSomething
; DISABLE-NEXT: LBB0_2: ; %false ; DISABLE-NEXT: LBB0_2: ; %false
; DISABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload ; DISABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; DISABLE-NEXT: add sp, sp, #32 ; =32 ; DISABLE-NEXT: add sp, sp, #32
; DISABLE-NEXT: ret ; DISABLE-NEXT: ret
%tmp = alloca i32, align 4 %tmp = alloca i32, align 4
%tmp2 = icmp slt i32 %a, %b %tmp2 = icmp slt i32 %a, %b
br i1 %tmp2, label %true, label %false br i1 %tmp2, label %true, label %false
true: true:
store i32 %a, i32* %tmp, align 4 store i32 %a, i32* %tmp, align 4
%tmp4 = call i32 @doSomething(i32 0, i32* %tmp) %tmp4 = call i32 @doSomething(i32 0, i32* %tmp)
Show All 12 Lines
; is outside. ; is outside.
define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) { define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) {
; ENABLE-LABEL: freqSaveAndRestoreOutsideLoop: ; ENABLE-LABEL: freqSaveAndRestoreOutsideLoop:
; ENABLE: ; %bb.0: ; %entry ; ENABLE: ; %bb.0: ; %entry
; ENABLE-NEXT: cbz w0, LBB1_4 ; ENABLE-NEXT: cbz w0, LBB1_4
; ENABLE-NEXT: ; %bb.1: ; %for.body.preheader ; ENABLE-NEXT: ; %bb.1: ; %for.body.preheader
; ENABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill ; ENABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
; ENABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill ; ENABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; ENABLE-NEXT: add x29, sp, #16 ; =16 ; ENABLE-NEXT: add x29, sp, #16
; ENABLE-NEXT: .cfi_def_cfa w29, 16 ; ENABLE-NEXT: .cfi_def_cfa w29, 16
; ENABLE-NEXT: .cfi_offset w30, -8 ; ENABLE-NEXT: .cfi_offset w30, -8
; ENABLE-NEXT: .cfi_offset w29, -16 ; ENABLE-NEXT: .cfi_offset w29, -16
; ENABLE-NEXT: .cfi_offset w19, -24 ; ENABLE-NEXT: .cfi_offset w19, -24
; ENABLE-NEXT: .cfi_offset w20, -32 ; ENABLE-NEXT: .cfi_offset w20, -32
; ENABLE-NEXT: mov w19, wzr ; ENABLE-NEXT: mov w19, wzr
; ENABLE-NEXT: mov w20, #10 ; ENABLE-NEXT: mov w20, #10
; ENABLE-NEXT: LBB1_2: ; %for.body ; ENABLE-NEXT: LBB1_2: ; %for.body
; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1 ; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1
; ENABLE-NEXT: bl _something ; ENABLE-NEXT: bl _something
; ENABLE-NEXT: subs w20, w20, #1 ; =1 ; ENABLE-NEXT: subs w20, w20, #1
; ENABLE-NEXT: add w19, w0, w19 ; ENABLE-NEXT: add w19, w0, w19
; ENABLE-NEXT: b.ne LBB1_2 ; ENABLE-NEXT: b.ne LBB1_2
; ENABLE-NEXT: ; %bb.3: ; %for.end ; ENABLE-NEXT: ; %bb.3: ; %for.end
; ENABLE-NEXT: lsl w0, w19, #3 ; ENABLE-NEXT: lsl w0, w19, #3
; ENABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; ENABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ENABLE-NEXT: LBB1_4: ; %if.else ; ENABLE-NEXT: LBB1_4: ; %if.else
; ENABLE-NEXT: lsl w0, w1, #1 ; ENABLE-NEXT: lsl w0, w1, #1
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ;
; DISABLE-LABEL: freqSaveAndRestoreOutsideLoop: ; DISABLE-LABEL: freqSaveAndRestoreOutsideLoop:
; DISABLE: ; %bb.0: ; %entry ; DISABLE: ; %bb.0: ; %entry
; DISABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill ; DISABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
; DISABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill ; DISABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; DISABLE-NEXT: add x29, sp, #16 ; =16 ; DISABLE-NEXT: add x29, sp, #16
; DISABLE-NEXT: .cfi_def_cfa w29, 16 ; DISABLE-NEXT: .cfi_def_cfa w29, 16
; DISABLE-NEXT: .cfi_offset w30, -8 ; DISABLE-NEXT: .cfi_offset w30, -8
; DISABLE-NEXT: .cfi_offset w29, -16 ; DISABLE-NEXT: .cfi_offset w29, -16
; DISABLE-NEXT: .cfi_offset w19, -24 ; DISABLE-NEXT: .cfi_offset w19, -24
; DISABLE-NEXT: .cfi_offset w20, -32 ; DISABLE-NEXT: .cfi_offset w20, -32
; DISABLE-NEXT: cbz w0, LBB1_4 ; DISABLE-NEXT: cbz w0, LBB1_4
; DISABLE-NEXT: ; %bb.1: ; %for.body.preheader ; DISABLE-NEXT: ; %bb.1: ; %for.body.preheader
; DISABLE-NEXT: mov w19, wzr ; DISABLE-NEXT: mov w19, wzr
; DISABLE-NEXT: mov w20, #10 ; DISABLE-NEXT: mov w20, #10
; DISABLE-NEXT: LBB1_2: ; %for.body ; DISABLE-NEXT: LBB1_2: ; %for.body
; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1 ; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1
; DISABLE-NEXT: bl _something ; DISABLE-NEXT: bl _something
; DISABLE-NEXT: subs w20, w20, #1 ; =1 ; DISABLE-NEXT: subs w20, w20, #1
; DISABLE-NEXT: add w19, w0, w19 ; DISABLE-NEXT: add w19, w0, w19
; DISABLE-NEXT: b.ne LBB1_2 ; DISABLE-NEXT: b.ne LBB1_2
; DISABLE-NEXT: ; %bb.3: ; %for.end ; DISABLE-NEXT: ; %bb.3: ; %for.end
; DISABLE-NEXT: lsl w0, w19, #3 ; DISABLE-NEXT: lsl w0, w19, #3
; DISABLE-NEXT: b LBB1_5 ; DISABLE-NEXT: b LBB1_5
; DISABLE-NEXT: LBB1_4: ; %if.else ; DISABLE-NEXT: LBB1_4: ; %if.else
; DISABLE-NEXT: lsl w0, w1, #1 ; DISABLE-NEXT: lsl w0, w1, #1
; DISABLE-NEXT: LBB1_5: ; %if.end ; DISABLE-NEXT: LBB1_5: ; %if.end
Show All 30 Lines
; Check that we do not perform the shrink-wrapping inside the loop even ; Check that we do not perform the shrink-wrapping inside the loop even
; though that would be legal. The cost model must prevent that. ; though that would be legal. The cost model must prevent that.
define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) { define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {
; ENABLE-LABEL: freqSaveAndRestoreOutsideLoop2: ; ENABLE-LABEL: freqSaveAndRestoreOutsideLoop2:
; ENABLE: ; %bb.0: ; %entry ; ENABLE: ; %bb.0: ; %entry
; ENABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill ; ENABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
; ENABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill ; ENABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; ENABLE-NEXT: add x29, sp, #16 ; =16 ; ENABLE-NEXT: add x29, sp, #16
; ENABLE-NEXT: .cfi_def_cfa w29, 16 ; ENABLE-NEXT: .cfi_def_cfa w29, 16
; ENABLE-NEXT: .cfi_offset w30, -8 ; ENABLE-NEXT: .cfi_offset w30, -8
; ENABLE-NEXT: .cfi_offset w29, -16 ; ENABLE-NEXT: .cfi_offset w29, -16
; ENABLE-NEXT: .cfi_offset w19, -24 ; ENABLE-NEXT: .cfi_offset w19, -24
; ENABLE-NEXT: .cfi_offset w20, -32 ; ENABLE-NEXT: .cfi_offset w20, -32
; ENABLE-NEXT: mov w19, wzr ; ENABLE-NEXT: mov w19, wzr
; ENABLE-NEXT: mov w20, #10 ; ENABLE-NEXT: mov w20, #10
; ENABLE-NEXT: LBB2_1: ; %for.body ; ENABLE-NEXT: LBB2_1: ; %for.body
; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1 ; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1
; ENABLE-NEXT: bl _something ; ENABLE-NEXT: bl _something
; ENABLE-NEXT: subs w20, w20, #1 ; =1 ; ENABLE-NEXT: subs w20, w20, #1
; ENABLE-NEXT: add w19, w0, w19 ; ENABLE-NEXT: add w19, w0, w19
; ENABLE-NEXT: b.ne LBB2_1 ; ENABLE-NEXT: b.ne LBB2_1
; ENABLE-NEXT: ; %bb.2: ; %for.end ; ENABLE-NEXT: ; %bb.2: ; %for.end
; ENABLE-NEXT: mov w0, w19 ; ENABLE-NEXT: mov w0, w19
; ENABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; ENABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ;
; DISABLE-LABEL: freqSaveAndRestoreOutsideLoop2: ; DISABLE-LABEL: freqSaveAndRestoreOutsideLoop2:
; DISABLE: ; %bb.0: ; %entry ; DISABLE: ; %bb.0: ; %entry
; DISABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill ; DISABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
; DISABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill ; DISABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; DISABLE-NEXT: add x29, sp, #16 ; =16 ; DISABLE-NEXT: add x29, sp, #16
; DISABLE-NEXT: .cfi_def_cfa w29, 16 ; DISABLE-NEXT: .cfi_def_cfa w29, 16
; DISABLE-NEXT: .cfi_offset w30, -8 ; DISABLE-NEXT: .cfi_offset w30, -8
; DISABLE-NEXT: .cfi_offset w29, -16 ; DISABLE-NEXT: .cfi_offset w29, -16
; DISABLE-NEXT: .cfi_offset w19, -24 ; DISABLE-NEXT: .cfi_offset w19, -24
; DISABLE-NEXT: .cfi_offset w20, -32 ; DISABLE-NEXT: .cfi_offset w20, -32
; DISABLE-NEXT: mov w19, wzr ; DISABLE-NEXT: mov w19, wzr
; DISABLE-NEXT: mov w20, #10 ; DISABLE-NEXT: mov w20, #10
; DISABLE-NEXT: LBB2_1: ; %for.body ; DISABLE-NEXT: LBB2_1: ; %for.body
; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1 ; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1
; DISABLE-NEXT: bl _something ; DISABLE-NEXT: bl _something
; DISABLE-NEXT: subs w20, w20, #1 ; =1 ; DISABLE-NEXT: subs w20, w20, #1
; DISABLE-NEXT: add w19, w0, w19 ; DISABLE-NEXT: add w19, w0, w19
; DISABLE-NEXT: b.ne LBB2_1 ; DISABLE-NEXT: b.ne LBB2_1
; DISABLE-NEXT: ; %bb.2: ; %for.end ; DISABLE-NEXT: ; %bb.2: ; %for.end
; DISABLE-NEXT: mov w0, w19 ; DISABLE-NEXT: mov w0, w19
; DISABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload ; DISABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; DISABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload ; DISABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
; DISABLE-NEXT: ret ; DISABLE-NEXT: ret
entry: entry:
Show All 16 Lines
; restore outside. ; restore outside.
define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) { define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) {
; ENABLE-LABEL: loopInfoSaveOutsideLoop: ; ENABLE-LABEL: loopInfoSaveOutsideLoop:
; ENABLE: ; %bb.0: ; %entry ; ENABLE: ; %bb.0: ; %entry
; ENABLE-NEXT: cbz w0, LBB3_4 ; ENABLE-NEXT: cbz w0, LBB3_4
; ENABLE-NEXT: ; %bb.1: ; %for.body.preheader ; ENABLE-NEXT: ; %bb.1: ; %for.body.preheader
; ENABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill ; ENABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
; ENABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill ; ENABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; ENABLE-NEXT: add x29, sp, #16 ; =16 ; ENABLE-NEXT: add x29, sp, #16
; ENABLE-NEXT: .cfi_def_cfa w29, 16 ; ENABLE-NEXT: .cfi_def_cfa w29, 16
; ENABLE-NEXT: .cfi_offset w30, -8 ; ENABLE-NEXT: .cfi_offset w30, -8
; ENABLE-NEXT: .cfi_offset w29, -16 ; ENABLE-NEXT: .cfi_offset w29, -16
; ENABLE-NEXT: .cfi_offset w19, -24 ; ENABLE-NEXT: .cfi_offset w19, -24
; ENABLE-NEXT: .cfi_offset w20, -32 ; ENABLE-NEXT: .cfi_offset w20, -32
; ENABLE-NEXT: mov w19, wzr ; ENABLE-NEXT: mov w19, wzr
; ENABLE-NEXT: mov w20, #10 ; ENABLE-NEXT: mov w20, #10
; ENABLE-NEXT: LBB3_2: ; %for.body ; ENABLE-NEXT: LBB3_2: ; %for.body
; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1 ; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1
; ENABLE-NEXT: bl _something ; ENABLE-NEXT: bl _something
; ENABLE-NEXT: subs w20, w20, #1 ; =1 ; ENABLE-NEXT: subs w20, w20, #1
; ENABLE-NEXT: add w19, w0, w19 ; ENABLE-NEXT: add w19, w0, w19
; ENABLE-NEXT: b.ne LBB3_2 ; ENABLE-NEXT: b.ne LBB3_2
; ENABLE-NEXT: ; %bb.3: ; %for.end ; ENABLE-NEXT: ; %bb.3: ; %for.end
; ENABLE-NEXT: bl _somethingElse ; ENABLE-NEXT: bl _somethingElse
; ENABLE-NEXT: lsl w0, w19, #3 ; ENABLE-NEXT: lsl w0, w19, #3
; ENABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; ENABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ENABLE-NEXT: LBB3_4: ; %if.else ; ENABLE-NEXT: LBB3_4: ; %if.else
; ENABLE-NEXT: lsl w0, w1, #1 ; ENABLE-NEXT: lsl w0, w1, #1
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ;
; DISABLE-LABEL: loopInfoSaveOutsideLoop: ; DISABLE-LABEL: loopInfoSaveOutsideLoop:
; DISABLE: ; %bb.0: ; %entry ; DISABLE: ; %bb.0: ; %entry
; DISABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill ; DISABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
; DISABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill ; DISABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; DISABLE-NEXT: add x29, sp, #16 ; =16 ; DISABLE-NEXT: add x29, sp, #16
; DISABLE-NEXT: .cfi_def_cfa w29, 16 ; DISABLE-NEXT: .cfi_def_cfa w29, 16
; DISABLE-NEXT: .cfi_offset w30, -8 ; DISABLE-NEXT: .cfi_offset w30, -8
; DISABLE-NEXT: .cfi_offset w29, -16 ; DISABLE-NEXT: .cfi_offset w29, -16
; DISABLE-NEXT: .cfi_offset w19, -24 ; DISABLE-NEXT: .cfi_offset w19, -24
; DISABLE-NEXT: .cfi_offset w20, -32 ; DISABLE-NEXT: .cfi_offset w20, -32
; DISABLE-NEXT: cbz w0, LBB3_4 ; DISABLE-NEXT: cbz w0, LBB3_4
; DISABLE-NEXT: ; %bb.1: ; %for.body.preheader ; DISABLE-NEXT: ; %bb.1: ; %for.body.preheader
; DISABLE-NEXT: mov w19, wzr ; DISABLE-NEXT: mov w19, wzr
; DISABLE-NEXT: mov w20, #10 ; DISABLE-NEXT: mov w20, #10
; DISABLE-NEXT: LBB3_2: ; %for.body ; DISABLE-NEXT: LBB3_2: ; %for.body
; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1 ; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1
; DISABLE-NEXT: bl _something ; DISABLE-NEXT: bl _something
; DISABLE-NEXT: subs w20, w20, #1 ; =1 ; DISABLE-NEXT: subs w20, w20, #1
; DISABLE-NEXT: add w19, w0, w19 ; DISABLE-NEXT: add w19, w0, w19
; DISABLE-NEXT: b.ne LBB3_2 ; DISABLE-NEXT: b.ne LBB3_2
; DISABLE-NEXT: ; %bb.3: ; %for.end ; DISABLE-NEXT: ; %bb.3: ; %for.end
; DISABLE-NEXT: bl _somethingElse ; DISABLE-NEXT: bl _somethingElse
; DISABLE-NEXT: lsl w0, w19, #3 ; DISABLE-NEXT: lsl w0, w19, #3
; DISABLE-NEXT: b LBB3_5 ; DISABLE-NEXT: b LBB3_5
; DISABLE-NEXT: LBB3_4: ; %if.else ; DISABLE-NEXT: LBB3_4: ; %if.else
; DISABLE-NEXT: lsl w0, w1, #1 ; DISABLE-NEXT: lsl w0, w1, #1
Show All 34 Lines
; save outside. ; save outside.
define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) nounwind { define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) nounwind {
; ENABLE-LABEL: loopInfoRestoreOutsideLoop: ; ENABLE-LABEL: loopInfoRestoreOutsideLoop:
; ENABLE: ; %bb.0: ; %entry ; ENABLE: ; %bb.0: ; %entry
; ENABLE-NEXT: cbz w0, LBB4_4 ; ENABLE-NEXT: cbz w0, LBB4_4
; ENABLE-NEXT: ; %bb.1: ; %if.then ; ENABLE-NEXT: ; %bb.1: ; %if.then
; ENABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill ; ENABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
; ENABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill ; ENABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; ENABLE-NEXT: add x29, sp, #16 ; =16 ; ENABLE-NEXT: add x29, sp, #16
; ENABLE-NEXT: bl _somethingElse ; ENABLE-NEXT: bl _somethingElse
; ENABLE-NEXT: mov w19, wzr ; ENABLE-NEXT: mov w19, wzr
; ENABLE-NEXT: mov w20, #10 ; ENABLE-NEXT: mov w20, #10
; ENABLE-NEXT: LBB4_2: ; %for.body ; ENABLE-NEXT: LBB4_2: ; %for.body
; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1 ; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1
; ENABLE-NEXT: bl _something ; ENABLE-NEXT: bl _something
; ENABLE-NEXT: subs w20, w20, #1 ; =1 ; ENABLE-NEXT: subs w20, w20, #1
; ENABLE-NEXT: add w19, w0, w19 ; ENABLE-NEXT: add w19, w0, w19
; ENABLE-NEXT: b.ne LBB4_2 ; ENABLE-NEXT: b.ne LBB4_2
; ENABLE-NEXT: ; %bb.3: ; %for.end ; ENABLE-NEXT: ; %bb.3: ; %for.end
; ENABLE-NEXT: lsl w0, w19, #3 ; ENABLE-NEXT: lsl w0, w19, #3
; ENABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; ENABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ENABLE-NEXT: LBB4_4: ; %if.else ; ENABLE-NEXT: LBB4_4: ; %if.else
; ENABLE-NEXT: lsl w0, w1, #1 ; ENABLE-NEXT: lsl w0, w1, #1
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ;
; DISABLE-LABEL: loopInfoRestoreOutsideLoop: ; DISABLE-LABEL: loopInfoRestoreOutsideLoop:
; DISABLE: ; %bb.0: ; %entry ; DISABLE: ; %bb.0: ; %entry
; DISABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill ; DISABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
; DISABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill ; DISABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; DISABLE-NEXT: add x29, sp, #16 ; =16 ; DISABLE-NEXT: add x29, sp, #16
; DISABLE-NEXT: cbz w0, LBB4_4 ; DISABLE-NEXT: cbz w0, LBB4_4
; DISABLE-NEXT: ; %bb.1: ; %if.then ; DISABLE-NEXT: ; %bb.1: ; %if.then
; DISABLE-NEXT: bl _somethingElse ; DISABLE-NEXT: bl _somethingElse
; DISABLE-NEXT: mov w19, wzr ; DISABLE-NEXT: mov w19, wzr
; DISABLE-NEXT: mov w20, #10 ; DISABLE-NEXT: mov w20, #10
; DISABLE-NEXT: LBB4_2: ; %for.body ; DISABLE-NEXT: LBB4_2: ; %for.body
; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1 ; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1
; DISABLE-NEXT: bl _something ; DISABLE-NEXT: bl _something
; DISABLE-NEXT: subs w20, w20, #1 ; =1 ; DISABLE-NEXT: subs w20, w20, #1
; DISABLE-NEXT: add w19, w0, w19 ; DISABLE-NEXT: add w19, w0, w19
; DISABLE-NEXT: b.ne LBB4_2 ; DISABLE-NEXT: b.ne LBB4_2
; DISABLE-NEXT: ; %bb.3: ; %for.end ; DISABLE-NEXT: ; %bb.3: ; %for.end
; DISABLE-NEXT: lsl w0, w19, #3 ; DISABLE-NEXT: lsl w0, w19, #3
; DISABLE-NEXT: b LBB4_5 ; DISABLE-NEXT: b LBB4_5
; DISABLE-NEXT: LBB4_4: ; %if.else ; DISABLE-NEXT: LBB4_4: ; %if.else
; DISABLE-NEXT: lsl w0, w1, #1 ; DISABLE-NEXT: lsl w0, w1, #1
; DISABLE-NEXT: LBB4_5: ; %if.end ; DISABLE-NEXT: LBB4_5: ; %if.end
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
} }
; Check that we handle variadic function correctly. ; Check that we handle variadic function correctly.
define i32 @variadicFunc(i32 %cond, i32 %count, ...) nounwind { define i32 @variadicFunc(i32 %cond, i32 %count, ...) nounwind {
; ENABLE-LABEL: variadicFunc: ; ENABLE-LABEL: variadicFunc:
; ENABLE: ; %bb.0: ; %entry ; ENABLE: ; %bb.0: ; %entry
; ENABLE-NEXT: cbz w0, LBB6_4 ; ENABLE-NEXT: cbz w0, LBB6_4
; ENABLE-NEXT: ; %bb.1: ; %if.then ; ENABLE-NEXT: ; %bb.1: ; %if.then
; ENABLE-NEXT: sub sp, sp, #16 ; =16 ; ENABLE-NEXT: sub sp, sp, #16
; ENABLE-NEXT: add x8, sp, #16 ; =16 ; ENABLE-NEXT: add x8, sp, #16
; ENABLE-NEXT: cmp w1, #1 ; =1 ; ENABLE-NEXT: cmp w1, #1
; ENABLE-NEXT: str x8, [sp, #8] ; ENABLE-NEXT: str x8, [sp, #8]
; ENABLE-NEXT: mov w0, wzr ; ENABLE-NEXT: mov w0, wzr
; ENABLE-NEXT: b.lt LBB6_3 ; ENABLE-NEXT: b.lt LBB6_3
; ENABLE-NEXT: LBB6_2: ; %for.body ; ENABLE-NEXT: LBB6_2: ; %for.body
; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1 ; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1
; ENABLE-NEXT: ldr x8, [sp, #8] ; ENABLE-NEXT: ldr x8, [sp, #8]
; ENABLE-NEXT: add x9, x8, #8 ; =8 ; ENABLE-NEXT: add x9, x8, #8
; ENABLE-NEXT: str x9, [sp, #8] ; ENABLE-NEXT: str x9, [sp, #8]
; ENABLE-NEXT: ldr w8, [x8] ; ENABLE-NEXT: ldr w8, [x8]
; ENABLE-NEXT: subs w1, w1, #1 ; =1 ; ENABLE-NEXT: subs w1, w1, #1
; ENABLE-NEXT: add w0, w0, w8 ; ENABLE-NEXT: add w0, w0, w8
; ENABLE-NEXT: b.ne LBB6_2 ; ENABLE-NEXT: b.ne LBB6_2
; ENABLE-NEXT: LBB6_3: ; %for.end ; ENABLE-NEXT: LBB6_3: ; %for.end
; ENABLE-NEXT: add sp, sp, #16 ; =16 ; ENABLE-NEXT: add sp, sp, #16
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ENABLE-NEXT: LBB6_4: ; %if.else ; ENABLE-NEXT: LBB6_4: ; %if.else
; ENABLE-NEXT: lsl w0, w1, #1 ; ENABLE-NEXT: lsl w0, w1, #1
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ;
; DISABLE-LABEL: variadicFunc: ; DISABLE-LABEL: variadicFunc:
; DISABLE: ; %bb.0: ; %entry ; DISABLE: ; %bb.0: ; %entry
; DISABLE-NEXT: sub sp, sp, #16 ; =16 ; DISABLE-NEXT: sub sp, sp, #16
; DISABLE-NEXT: cbz w0, LBB6_4 ; DISABLE-NEXT: cbz w0, LBB6_4
; DISABLE-NEXT: ; %bb.1: ; %if.then ; DISABLE-NEXT: ; %bb.1: ; %if.then
; DISABLE-NEXT: add x8, sp, #16 ; =16 ; DISABLE-NEXT: add x8, sp, #16
; DISABLE-NEXT: cmp w1, #1 ; =1 ; DISABLE-NEXT: cmp w1, #1
; DISABLE-NEXT: str x8, [sp, #8] ; DISABLE-NEXT: str x8, [sp, #8]
; DISABLE-NEXT: mov w0, wzr ; DISABLE-NEXT: mov w0, wzr
; DISABLE-NEXT: b.lt LBB6_3 ; DISABLE-NEXT: b.lt LBB6_3
; DISABLE-NEXT: LBB6_2: ; %for.body ; DISABLE-NEXT: LBB6_2: ; %for.body
; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1 ; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1
; DISABLE-NEXT: ldr x8, [sp, #8] ; DISABLE-NEXT: ldr x8, [sp, #8]
; DISABLE-NEXT: add x9, x8, #8 ; =8 ; DISABLE-NEXT: add x9, x8, #8
; DISABLE-NEXT: str x9, [sp, #8] ; DISABLE-NEXT: str x9, [sp, #8]
; DISABLE-NEXT: ldr w8, [x8] ; DISABLE-NEXT: ldr w8, [x8]
; DISABLE-NEXT: subs w1, w1, #1 ; =1 ; DISABLE-NEXT: subs w1, w1, #1
; DISABLE-NEXT: add w0, w0, w8 ; DISABLE-NEXT: add w0, w0, w8
; DISABLE-NEXT: b.ne LBB6_2 ; DISABLE-NEXT: b.ne LBB6_2
; DISABLE-NEXT: LBB6_3: ; %if.end ; DISABLE-NEXT: LBB6_3: ; %if.end
; DISABLE-NEXT: add sp, sp, #16 ; =16 ; DISABLE-NEXT: add sp, sp, #16
; DISABLE-NEXT: ret ; DISABLE-NEXT: ret
; DISABLE-NEXT: LBB6_4: ; %if.else ; DISABLE-NEXT: LBB6_4: ; %if.else
; DISABLE-NEXT: lsl w0, w1, #1 ; DISABLE-NEXT: lsl w0, w1, #1
; DISABLE-NEXT: add sp, sp, #16 ; =16 ; DISABLE-NEXT: add sp, sp, #16
; DISABLE-NEXT: ret ; DISABLE-NEXT: ret
entry: entry:
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%tobool = icmp eq i32 %cond, 0 %tobool = icmp eq i32 %cond, 0
br i1 %tobool, label %if.else, label %if.then br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
%ap1 = bitcast i8** %ap to i8* %ap1 = bitcast i8** %ap to i8*
Show All 36 Lines
; ENABLE-NEXT: ; %bb.1: ; %for.body.preheader ; ENABLE-NEXT: ; %bb.1: ; %for.body.preheader
; ENABLE-NEXT: stp x20, x19, [sp, #-16]! ; 16-byte Folded Spill ; ENABLE-NEXT: stp x20, x19, [sp, #-16]! ; 16-byte Folded Spill
; ENABLE-NEXT: .cfi_def_cfa_offset 16 ; ENABLE-NEXT: .cfi_def_cfa_offset 16
; ENABLE-NEXT: .cfi_offset w19, -8 ; ENABLE-NEXT: .cfi_offset w19, -8
; ENABLE-NEXT: .cfi_offset w20, -16 ; ENABLE-NEXT: .cfi_offset w20, -16
; ENABLE-NEXT: mov w8, #10 ; ENABLE-NEXT: mov w8, #10
; ENABLE-NEXT: LBB7_2: ; %for.body ; ENABLE-NEXT: LBB7_2: ; %for.body
; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1 ; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1
; ENABLE-NEXT: subs w8, w8, #1 ; =1 ; ENABLE-NEXT: subs w8, w8, #1
; ENABLE-NEXT: ; InlineAsm Start ; ENABLE-NEXT: ; InlineAsm Start
; ENABLE-NEXT: add x19, x19, #1 ; =1 ; ENABLE-NEXT: add x19, x19, #1
; ENABLE-NEXT: ; InlineAsm End ; ENABLE-NEXT: ; InlineAsm End
; ENABLE-NEXT: b.ne LBB7_2 ; ENABLE-NEXT: b.ne LBB7_2
; ENABLE-NEXT: ; %bb.3: ; ENABLE-NEXT: ; %bb.3:
; ENABLE-NEXT: mov w0, wzr ; ENABLE-NEXT: mov w0, wzr
; ENABLE-NEXT: ldp x20, x19, [sp], #16 ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x20, x19, [sp], #16 ; 16-byte Folded Reload
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ENABLE-NEXT: LBB7_4: ; %if.else ; ENABLE-NEXT: LBB7_4: ; %if.else
; ENABLE-NEXT: lsl w0, w1, #1 ; ENABLE-NEXT: lsl w0, w1, #1
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ;
; DISABLE-LABEL: inlineAsm: ; DISABLE-LABEL: inlineAsm:
; DISABLE: ; %bb.0: ; %entry ; DISABLE: ; %bb.0: ; %entry
; DISABLE-NEXT: stp x20, x19, [sp, #-16]! ; 16-byte Folded Spill ; DISABLE-NEXT: stp x20, x19, [sp, #-16]! ; 16-byte Folded Spill
; DISABLE-NEXT: .cfi_def_cfa_offset 16 ; DISABLE-NEXT: .cfi_def_cfa_offset 16
; DISABLE-NEXT: .cfi_offset w19, -8 ; DISABLE-NEXT: .cfi_offset w19, -8
; DISABLE-NEXT: .cfi_offset w20, -16 ; DISABLE-NEXT: .cfi_offset w20, -16
; DISABLE-NEXT: cbz w0, LBB7_4 ; DISABLE-NEXT: cbz w0, LBB7_4
; DISABLE-NEXT: ; %bb.1: ; %for.body.preheader ; DISABLE-NEXT: ; %bb.1: ; %for.body.preheader
; DISABLE-NEXT: mov w8, #10 ; DISABLE-NEXT: mov w8, #10
; DISABLE-NEXT: LBB7_2: ; %for.body ; DISABLE-NEXT: LBB7_2: ; %for.body
; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1 ; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1
; DISABLE-NEXT: subs w8, w8, #1 ; =1 ; DISABLE-NEXT: subs w8, w8, #1
; DISABLE-NEXT: ; InlineAsm Start ; DISABLE-NEXT: ; InlineAsm Start
; DISABLE-NEXT: add x19, x19, #1 ; =1 ; DISABLE-NEXT: add x19, x19, #1
; DISABLE-NEXT: ; InlineAsm End ; DISABLE-NEXT: ; InlineAsm End
; DISABLE-NEXT: b.ne LBB7_2 ; DISABLE-NEXT: b.ne LBB7_2
; DISABLE-NEXT: ; %bb.3: ; DISABLE-NEXT: ; %bb.3:
; DISABLE-NEXT: mov w0, wzr ; DISABLE-NEXT: mov w0, wzr
; DISABLE-NEXT: ldp x20, x19, [sp], #16 ; 16-byte Folded Reload ; DISABLE-NEXT: ldp x20, x19, [sp], #16 ; 16-byte Folded Reload
; DISABLE-NEXT: ret ; DISABLE-NEXT: ret
; DISABLE-NEXT: LBB7_4: ; %if.else ; DISABLE-NEXT: LBB7_4: ; %if.else
; DISABLE-NEXT: lsl w0, w1, #1 ; DISABLE-NEXT: lsl w0, w1, #1
Show All 21 Lines
; Check that we handle calls to variadic functions correctly. ; Check that we handle calls to variadic functions correctly.
define i32 @callVariadicFunc(i32 %cond, i32 %N) { define i32 @callVariadicFunc(i32 %cond, i32 %N) {
; ENABLE-LABEL: callVariadicFunc: ; ENABLE-LABEL: callVariadicFunc:
; ENABLE: ; %bb.0: ; %entry ; ENABLE: ; %bb.0: ; %entry
; ENABLE-NEXT: ; kill: def $w1 killed $w1 def $x1 ; ENABLE-NEXT: ; kill: def $w1 killed $w1 def $x1
; ENABLE-NEXT: cbz w0, LBB8_2 ; ENABLE-NEXT: cbz w0, LBB8_2
; ENABLE-NEXT: ; %bb.1: ; %if.then ; ENABLE-NEXT: ; %bb.1: ; %if.then
; ENABLE-NEXT: sub sp, sp, #64 ; =64 ; ENABLE-NEXT: sub sp, sp, #64
; ENABLE-NEXT: stp x29, x30, [sp, #48] ; 16-byte Folded Spill ; ENABLE-NEXT: stp x29, x30, [sp, #48] ; 16-byte Folded Spill
; ENABLE-NEXT: add x29, sp, #48 ; =48 ; ENABLE-NEXT: add x29, sp, #48
; ENABLE-NEXT: .cfi_def_cfa w29, 16 ; ENABLE-NEXT: .cfi_def_cfa w29, 16
; ENABLE-NEXT: .cfi_offset w30, -8 ; ENABLE-NEXT: .cfi_offset w30, -8
; ENABLE-NEXT: .cfi_offset w29, -16 ; ENABLE-NEXT: .cfi_offset w29, -16
; ENABLE-NEXT: stp x1, x1, [sp, #32] ; ENABLE-NEXT: stp x1, x1, [sp, #32]
; ENABLE-NEXT: stp x1, x1, [sp, #16] ; ENABLE-NEXT: stp x1, x1, [sp, #16]
; ENABLE-NEXT: stp x1, x1, [sp] ; ENABLE-NEXT: stp x1, x1, [sp]
; ENABLE-NEXT: mov w0, w1 ; ENABLE-NEXT: mov w0, w1
; ENABLE-NEXT: bl _someVariadicFunc ; ENABLE-NEXT: bl _someVariadicFunc
; ENABLE-NEXT: lsl w0, w0, #3 ; ENABLE-NEXT: lsl w0, w0, #3
; ENABLE-NEXT: ldp x29, x30, [sp, #48] ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x29, x30, [sp, #48] ; 16-byte Folded Reload
; ENABLE-NEXT: add sp, sp, #64 ; =64 ; ENABLE-NEXT: add sp, sp, #64
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ENABLE-NEXT: LBB8_2: ; %if.else ; ENABLE-NEXT: LBB8_2: ; %if.else
; ENABLE-NEXT: lsl w0, w1, #1 ; ENABLE-NEXT: lsl w0, w1, #1
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ;
; DISABLE-LABEL: callVariadicFunc: ; DISABLE-LABEL: callVariadicFunc:
; DISABLE: ; %bb.0: ; %entry ; DISABLE: ; %bb.0: ; %entry
; DISABLE-NEXT: sub sp, sp, #64 ; =64 ; DISABLE-NEXT: sub sp, sp, #64
; DISABLE-NEXT: stp x29, x30, [sp, #48] ; 16-byte Folded Spill ; DISABLE-NEXT: stp x29, x30, [sp, #48] ; 16-byte Folded Spill
; DISABLE-NEXT: add x29, sp, #48 ; =48 ; DISABLE-NEXT: add x29, sp, #48
; DISABLE-NEXT: .cfi_def_cfa w29, 16 ; DISABLE-NEXT: .cfi_def_cfa w29, 16
; DISABLE-NEXT: .cfi_offset w30, -8 ; DISABLE-NEXT: .cfi_offset w30, -8
; DISABLE-NEXT: .cfi_offset w29, -16 ; DISABLE-NEXT: .cfi_offset w29, -16
; DISABLE-NEXT: ; kill: def $w1 killed $w1 def $x1 ; DISABLE-NEXT: ; kill: def $w1 killed $w1 def $x1
; DISABLE-NEXT: cbz w0, LBB8_2 ; DISABLE-NEXT: cbz w0, LBB8_2
; DISABLE-NEXT: ; %bb.1: ; %if.then ; DISABLE-NEXT: ; %bb.1: ; %if.then
; DISABLE-NEXT: stp x1, x1, [sp, #32] ; DISABLE-NEXT: stp x1, x1, [sp, #32]
; DISABLE-NEXT: stp x1, x1, [sp, #16] ; DISABLE-NEXT: stp x1, x1, [sp, #16]
; DISABLE-NEXT: stp x1, x1, [sp] ; DISABLE-NEXT: stp x1, x1, [sp]
; DISABLE-NEXT: mov w0, w1 ; DISABLE-NEXT: mov w0, w1
; DISABLE-NEXT: bl _someVariadicFunc ; DISABLE-NEXT: bl _someVariadicFunc
; DISABLE-NEXT: lsl w0, w0, #3 ; DISABLE-NEXT: lsl w0, w0, #3
; DISABLE-NEXT: b LBB8_3 ; DISABLE-NEXT: b LBB8_3
; DISABLE-NEXT: LBB8_2: ; %if.else ; DISABLE-NEXT: LBB8_2: ; %if.else
; DISABLE-NEXT: lsl w0, w1, #1 ; DISABLE-NEXT: lsl w0, w1, #1
; DISABLE-NEXT: LBB8_3: ; %if.end ; DISABLE-NEXT: LBB8_3: ; %if.end
; DISABLE-NEXT: ldp x29, x30, [sp, #48] ; 16-byte Folded Reload ; DISABLE-NEXT: ldp x29, x30, [sp, #48] ; 16-byte Folded Reload
; DISABLE-NEXT: add sp, sp, #64 ; =64 ; DISABLE-NEXT: add sp, sp, #64
; DISABLE-NEXT: ret ; DISABLE-NEXT: ret
entry: entry:
%tobool = icmp eq i32 %cond, 0 %tobool = icmp eq i32 %cond, 0
br i1 %tobool, label %if.else, label %if.then br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
%call = tail call i32 (i32, ...) @someVariadicFunc(i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N) %call = tail call i32 (i32, ...) @someVariadicFunc(i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N)
%shl = shl i32 %call, 3 %shl = shl i32 %call, 3
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; should return gracefully and continue compilation. ; should return gracefully and continue compilation.
; The only condition for this test is the compilation finishes correctly. ; The only condition for this test is the compilation finishes correctly.
; ;
define void @infiniteloop() { define void @infiniteloop() {
; ENABLE-LABEL: infiniteloop: ; ENABLE-LABEL: infiniteloop:
; ENABLE: ; %bb.0: ; %entry ; ENABLE: ; %bb.0: ; %entry
; ENABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill ; ENABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
; ENABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill ; ENABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; ENABLE-NEXT: add x29, sp, #16 ; =16 ; ENABLE-NEXT: add x29, sp, #16
; ENABLE-NEXT: .cfi_def_cfa w29, 16 ; ENABLE-NEXT: .cfi_def_cfa w29, 16
; ENABLE-NEXT: .cfi_offset w30, -8 ; ENABLE-NEXT: .cfi_offset w30, -8
; ENABLE-NEXT: .cfi_offset w29, -16 ; ENABLE-NEXT: .cfi_offset w29, -16
; ENABLE-NEXT: .cfi_offset w19, -24 ; ENABLE-NEXT: .cfi_offset w19, -24
; ENABLE-NEXT: .cfi_offset w20, -32 ; ENABLE-NEXT: .cfi_offset w20, -32
; ENABLE-NEXT: cbnz wzr, LBB10_3 ; ENABLE-NEXT: cbnz wzr, LBB10_3
; ENABLE-NEXT: ; %bb.1: ; %if.then ; ENABLE-NEXT: ; %bb.1: ; %if.then
; ENABLE-NEXT: sub x19, sp, #16 ; =16 ; ENABLE-NEXT: sub x19, sp, #16
; ENABLE-NEXT: mov sp, x19 ; ENABLE-NEXT: mov sp, x19
; ENABLE-NEXT: mov w20, wzr ; ENABLE-NEXT: mov w20, wzr
; ENABLE-NEXT: LBB10_2: ; %for.body ; ENABLE-NEXT: LBB10_2: ; %for.body
; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1 ; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1
; ENABLE-NEXT: bl _something ; ENABLE-NEXT: bl _something
; ENABLE-NEXT: add w20, w0, w20 ; ENABLE-NEXT: add w20, w0, w20
; ENABLE-NEXT: str w20, [x19] ; ENABLE-NEXT: str w20, [x19]
; ENABLE-NEXT: b LBB10_2 ; ENABLE-NEXT: b LBB10_2
; ENABLE-NEXT: LBB10_3: ; %if.end ; ENABLE-NEXT: LBB10_3: ; %if.end
; ENABLE-NEXT: sub sp, x29, #16 ; =16 ; ENABLE-NEXT: sub sp, x29, #16
; ENABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; ENABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ;
; DISABLE-LABEL: infiniteloop: ; DISABLE-LABEL: infiniteloop:
; DISABLE: ; %bb.0: ; %entry ; DISABLE: ; %bb.0: ; %entry
; DISABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill ; DISABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
; DISABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill ; DISABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; DISABLE-NEXT: add x29, sp, #16 ; =16 ; DISABLE-NEXT: add x29, sp, #16
; DISABLE-NEXT: .cfi_def_cfa w29, 16 ; DISABLE-NEXT: .cfi_def_cfa w29, 16
; DISABLE-NEXT: .cfi_offset w30, -8 ; DISABLE-NEXT: .cfi_offset w30, -8
; DISABLE-NEXT: .cfi_offset w29, -16 ; DISABLE-NEXT: .cfi_offset w29, -16
; DISABLE-NEXT: .cfi_offset w19, -24 ; DISABLE-NEXT: .cfi_offset w19, -24
; DISABLE-NEXT: .cfi_offset w20, -32 ; DISABLE-NEXT: .cfi_offset w20, -32
; DISABLE-NEXT: cbnz wzr, LBB10_3 ; DISABLE-NEXT: cbnz wzr, LBB10_3
; DISABLE-NEXT: ; %bb.1: ; %if.then ; DISABLE-NEXT: ; %bb.1: ; %if.then
; DISABLE-NEXT: sub x19, sp, #16 ; =16 ; DISABLE-NEXT: sub x19, sp, #16
; DISABLE-NEXT: mov sp, x19 ; DISABLE-NEXT: mov sp, x19
; DISABLE-NEXT: mov w20, wzr ; DISABLE-NEXT: mov w20, wzr
; DISABLE-NEXT: LBB10_2: ; %for.body ; DISABLE-NEXT: LBB10_2: ; %for.body
; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1 ; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1
; DISABLE-NEXT: bl _something ; DISABLE-NEXT: bl _something
; DISABLE-NEXT: add w20, w0, w20 ; DISABLE-NEXT: add w20, w0, w20
; DISABLE-NEXT: str w20, [x19] ; DISABLE-NEXT: str w20, [x19]
; DISABLE-NEXT: b LBB10_2 ; DISABLE-NEXT: b LBB10_2
; DISABLE-NEXT: LBB10_3: ; %if.end ; DISABLE-NEXT: LBB10_3: ; %if.end
; DISABLE-NEXT: sub sp, x29, #16 ; =16 ; DISABLE-NEXT: sub sp, x29, #16
; DISABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload ; DISABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; DISABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload ; DISABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
; DISABLE-NEXT: ret ; DISABLE-NEXT: ret
entry: entry:
br i1 undef, label %if.then, label %if.end br i1 undef, label %if.then, label %if.end
if.then: if.then:
%ptr = alloca i32, i32 4 %ptr = alloca i32, i32 4
Show All 11 Lines
} }
; Another infinite loop test this time with a body bigger than just one block. ; Another infinite loop test this time with a body bigger than just one block.
define void @infiniteloop2() { define void @infiniteloop2() {
; ENABLE-LABEL: infiniteloop2: ; ENABLE-LABEL: infiniteloop2:
; ENABLE: ; %bb.0: ; %entry ; ENABLE: ; %bb.0: ; %entry
; ENABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill ; ENABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
; ENABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill ; ENABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; ENABLE-NEXT: add x29, sp, #16 ; =16 ; ENABLE-NEXT: add x29, sp, #16
; ENABLE-NEXT: .cfi_def_cfa w29, 16 ; ENABLE-NEXT: .cfi_def_cfa w29, 16
; ENABLE-NEXT: .cfi_offset w30, -8 ; ENABLE-NEXT: .cfi_offset w30, -8
; ENABLE-NEXT: .cfi_offset w29, -16 ; ENABLE-NEXT: .cfi_offset w29, -16
; ENABLE-NEXT: .cfi_offset w19, -24 ; ENABLE-NEXT: .cfi_offset w19, -24
; ENABLE-NEXT: .cfi_offset w20, -32 ; ENABLE-NEXT: .cfi_offset w20, -32
; ENABLE-NEXT: cbnz wzr, LBB11_3 ; ENABLE-NEXT: cbnz wzr, LBB11_3
; ENABLE-NEXT: ; %bb.1: ; %if.then ; ENABLE-NEXT: ; %bb.1: ; %if.then
; ENABLE-NEXT: sub x8, sp, #16 ; =16 ; ENABLE-NEXT: sub x8, sp, #16
; ENABLE-NEXT: mov sp, x8 ; ENABLE-NEXT: mov sp, x8
; ENABLE-NEXT: mov w9, wzr ; ENABLE-NEXT: mov w9, wzr
; ENABLE-NEXT: ; InlineAsm Start ; ENABLE-NEXT: ; InlineAsm Start
; ENABLE-NEXT: mov x10, #0 ; ENABLE-NEXT: mov x10, #0
; ENABLE-NEXT: ; InlineAsm End ; ENABLE-NEXT: ; InlineAsm End
; ENABLE-NEXT: LBB11_2: ; %for.body ; ENABLE-NEXT: LBB11_2: ; %for.body
; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1 ; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1
; ENABLE-NEXT: add w9, w10, w9 ; ENABLE-NEXT: add w9, w10, w9
; ENABLE-NEXT: str w9, [x8] ; ENABLE-NEXT: str w9, [x8]
; ENABLE-NEXT: ; InlineAsm Start ; ENABLE-NEXT: ; InlineAsm Start
; ENABLE-NEXT: nop ; ENABLE-NEXT: nop
; ENABLE-NEXT: ; InlineAsm End ; ENABLE-NEXT: ; InlineAsm End
; ENABLE-NEXT: mov w9, #1 ; ENABLE-NEXT: mov w9, #1
; ENABLE-NEXT: b LBB11_2 ; ENABLE-NEXT: b LBB11_2
; ENABLE-NEXT: LBB11_3: ; %if.end ; ENABLE-NEXT: LBB11_3: ; %if.end
; ENABLE-NEXT: sub sp, x29, #16 ; =16 ; ENABLE-NEXT: sub sp, x29, #16
; ENABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; ENABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ;
; DISABLE-LABEL: infiniteloop2: ; DISABLE-LABEL: infiniteloop2:
; DISABLE: ; %bb.0: ; %entry ; DISABLE: ; %bb.0: ; %entry
; DISABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill ; DISABLE-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
; DISABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill ; DISABLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; DISABLE-NEXT: add x29, sp, #16 ; =16 ; DISABLE-NEXT: add x29, sp, #16
; DISABLE-NEXT: .cfi_def_cfa w29, 16 ; DISABLE-NEXT: .cfi_def_cfa w29, 16
; DISABLE-NEXT: .cfi_offset w30, -8 ; DISABLE-NEXT: .cfi_offset w30, -8
; DISABLE-NEXT: .cfi_offset w29, -16 ; DISABLE-NEXT: .cfi_offset w29, -16
; DISABLE-NEXT: .cfi_offset w19, -24 ; DISABLE-NEXT: .cfi_offset w19, -24
; DISABLE-NEXT: .cfi_offset w20, -32 ; DISABLE-NEXT: .cfi_offset w20, -32
; DISABLE-NEXT: cbnz wzr, LBB11_3 ; DISABLE-NEXT: cbnz wzr, LBB11_3
; DISABLE-NEXT: ; %bb.1: ; %if.then ; DISABLE-NEXT: ; %bb.1: ; %if.then
; DISABLE-NEXT: sub x8, sp, #16 ; =16 ; DISABLE-NEXT: sub x8, sp, #16
; DISABLE-NEXT: mov sp, x8 ; DISABLE-NEXT: mov sp, x8
; DISABLE-NEXT: mov w9, wzr ; DISABLE-NEXT: mov w9, wzr
; DISABLE-NEXT: ; InlineAsm Start ; DISABLE-NEXT: ; InlineAsm Start
; DISABLE-NEXT: mov x10, #0 ; DISABLE-NEXT: mov x10, #0
; DISABLE-NEXT: ; InlineAsm End ; DISABLE-NEXT: ; InlineAsm End
; DISABLE-NEXT: LBB11_2: ; %for.body ; DISABLE-NEXT: LBB11_2: ; %for.body
; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1 ; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1
; DISABLE-NEXT: add w9, w10, w9 ; DISABLE-NEXT: add w9, w10, w9
; DISABLE-NEXT: str w9, [x8] ; DISABLE-NEXT: str w9, [x8]
; DISABLE-NEXT: ; InlineAsm Start ; DISABLE-NEXT: ; InlineAsm Start
; DISABLE-NEXT: nop ; DISABLE-NEXT: nop
; DISABLE-NEXT: ; InlineAsm End ; DISABLE-NEXT: ; InlineAsm End
; DISABLE-NEXT: mov w9, #1 ; DISABLE-NEXT: mov w9, #1
; DISABLE-NEXT: b LBB11_2 ; DISABLE-NEXT: b LBB11_2
; DISABLE-NEXT: LBB11_3: ; %if.end ; DISABLE-NEXT: LBB11_3: ; %if.end
; DISABLE-NEXT: sub sp, x29, #16 ; =16 ; DISABLE-NEXT: sub sp, x29, #16
; DISABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload ; DISABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; DISABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload ; DISABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
; DISABLE-NEXT: ret ; DISABLE-NEXT: ret
entry: entry:
br i1 undef, label %if.then, label %if.end br i1 undef, label %if.then, label %if.end
if.then: if.then:
%ptr = alloca i32, i32 4 %ptr = alloca i32, i32 4
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; Re-aligned stack pointer. See bug 26642. Avoid clobbering live ; Re-aligned stack pointer. See bug 26642. Avoid clobbering live
; values in the prologue when re-aligning the stack pointer. ; values in the prologue when re-aligning the stack pointer.
define i32 @stack_realign(i32 %a, i32 %b, i32* %ptr1, i32* %ptr2) { define i32 @stack_realign(i32 %a, i32 %b, i32* %ptr1, i32* %ptr2) {
; ENABLE-LABEL: stack_realign: ; ENABLE-LABEL: stack_realign:
; ENABLE: ; %bb.0: ; ENABLE: ; %bb.0:
; ENABLE-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; ENABLE-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; ENABLE-NEXT: mov x29, sp ; ENABLE-NEXT: mov x29, sp
; ENABLE-NEXT: sub x9, sp, #16 ; =16 ; ENABLE-NEXT: sub x9, sp, #16
; ENABLE-NEXT: and sp, x9, #0xffffffffffffffe0 ; ENABLE-NEXT: and sp, x9, #0xffffffffffffffe0
; ENABLE-NEXT: .cfi_def_cfa w29, 16 ; ENABLE-NEXT: .cfi_def_cfa w29, 16
; ENABLE-NEXT: .cfi_offset w30, -8 ; ENABLE-NEXT: .cfi_offset w30, -8
; ENABLE-NEXT: .cfi_offset w29, -16 ; ENABLE-NEXT: .cfi_offset w29, -16
; ENABLE-NEXT: lsl w8, w0, w1 ; ENABLE-NEXT: lsl w8, w0, w1
; ENABLE-NEXT: cmp w0, w1 ; ENABLE-NEXT: cmp w0, w1
; ENABLE-NEXT: lsl w9, w1, w0 ; ENABLE-NEXT: lsl w9, w1, w0
; ENABLE-NEXT: b.ge LBB13_2 ; ENABLE-NEXT: b.ge LBB13_2
; ENABLE-NEXT: ; %bb.1: ; %true ; ENABLE-NEXT: ; %bb.1: ; %true
; ENABLE-NEXT: str w0, [sp] ; ENABLE-NEXT: str w0, [sp]
; ENABLE-NEXT: LBB13_2: ; %false ; ENABLE-NEXT: LBB13_2: ; %false
; ENABLE-NEXT: str w8, [x2] ; ENABLE-NEXT: str w8, [x2]
; ENABLE-NEXT: str w9, [x3] ; ENABLE-NEXT: str w9, [x3]
; ENABLE-NEXT: mov sp, x29 ; ENABLE-NEXT: mov sp, x29
; ENABLE-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ;
; DISABLE-LABEL: stack_realign: ; DISABLE-LABEL: stack_realign:
; DISABLE: ; %bb.0: ; DISABLE: ; %bb.0:
; DISABLE-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; DISABLE-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; DISABLE-NEXT: mov x29, sp ; DISABLE-NEXT: mov x29, sp
; DISABLE-NEXT: sub x9, sp, #16 ; =16 ; DISABLE-NEXT: sub x9, sp, #16
; DISABLE-NEXT: and sp, x9, #0xffffffffffffffe0 ; DISABLE-NEXT: and sp, x9, #0xffffffffffffffe0
; DISABLE-NEXT: .cfi_def_cfa w29, 16 ; DISABLE-NEXT: .cfi_def_cfa w29, 16
; DISABLE-NEXT: .cfi_offset w30, -8 ; DISABLE-NEXT: .cfi_offset w30, -8
; DISABLE-NEXT: .cfi_offset w29, -16 ; DISABLE-NEXT: .cfi_offset w29, -16
; DISABLE-NEXT: lsl w8, w0, w1 ; DISABLE-NEXT: lsl w8, w0, w1
; DISABLE-NEXT: cmp w0, w1 ; DISABLE-NEXT: cmp w0, w1
; DISABLE-NEXT: lsl w9, w1, w0 ; DISABLE-NEXT: lsl w9, w1, w0
; DISABLE-NEXT: b.ge LBB13_2 ; DISABLE-NEXT: b.ge LBB13_2
Show All 32 Lines
; ENABLE-LABEL: stack_realign2: ; ENABLE-LABEL: stack_realign2:
; ENABLE: ; %bb.0: ; ENABLE: ; %bb.0:
; ENABLE-NEXT: stp x28, x27, [sp, #-96]! ; 16-byte Folded Spill ; ENABLE-NEXT: stp x28, x27, [sp, #-96]! ; 16-byte Folded Spill
; ENABLE-NEXT: stp x26, x25, [sp, #16] ; 16-byte Folded Spill ; ENABLE-NEXT: stp x26, x25, [sp, #16] ; 16-byte Folded Spill
; ENABLE-NEXT: stp x24, x23, [sp, #32] ; 16-byte Folded Spill ; ENABLE-NEXT: stp x24, x23, [sp, #32] ; 16-byte Folded Spill
; ENABLE-NEXT: stp x22, x21, [sp, #48] ; 16-byte Folded Spill ; ENABLE-NEXT: stp x22, x21, [sp, #48] ; 16-byte Folded Spill
; ENABLE-NEXT: stp x20, x19, [sp, #64] ; 16-byte Folded Spill ; ENABLE-NEXT: stp x20, x19, [sp, #64] ; 16-byte Folded Spill
; ENABLE-NEXT: stp x29, x30, [sp, #80] ; 16-byte Folded Spill ; ENABLE-NEXT: stp x29, x30, [sp, #80] ; 16-byte Folded Spill
; ENABLE-NEXT: add x29, sp, #80 ; =80 ; ENABLE-NEXT: add x29, sp, #80
; ENABLE-NEXT: sub x9, sp, #32 ; =32 ; ENABLE-NEXT: sub x9, sp, #32
; ENABLE-NEXT: and sp, x9, #0xffffffffffffffe0 ; ENABLE-NEXT: and sp, x9, #0xffffffffffffffe0
; ENABLE-NEXT: .cfi_def_cfa w29, 16 ; ENABLE-NEXT: .cfi_def_cfa w29, 16
; ENABLE-NEXT: .cfi_offset w30, -8 ; ENABLE-NEXT: .cfi_offset w30, -8
; ENABLE-NEXT: .cfi_offset w29, -16 ; ENABLE-NEXT: .cfi_offset w29, -16
; ENABLE-NEXT: .cfi_offset w19, -24 ; ENABLE-NEXT: .cfi_offset w19, -24
; ENABLE-NEXT: .cfi_offset w20, -32 ; ENABLE-NEXT: .cfi_offset w20, -32
; ENABLE-NEXT: .cfi_offset w21, -40 ; ENABLE-NEXT: .cfi_offset w21, -40
; ENABLE-NEXT: .cfi_offset w22, -48 ; ENABLE-NEXT: .cfi_offset w22, -48
Show All 24 Lines
; ENABLE-NEXT: str w9, [x3] ; ENABLE-NEXT: str w9, [x3]
; ENABLE-NEXT: str w10, [x4] ; ENABLE-NEXT: str w10, [x4]
; ENABLE-NEXT: str w12, [x5] ; ENABLE-NEXT: str w12, [x5]
; ENABLE-NEXT: str w15, [x6] ; ENABLE-NEXT: str w15, [x6]
; ENABLE-NEXT: str w17, [x7] ; ENABLE-NEXT: str w17, [x7]
; ENABLE-NEXT: stp w0, w1, [x2, #4] ; ENABLE-NEXT: stp w0, w1, [x2, #4]
; ENABLE-NEXT: stp w16, w11, [x2, #12] ; ENABLE-NEXT: stp w16, w11, [x2, #12]
; ENABLE-NEXT: stp w13, w14, [x2, #20] ; ENABLE-NEXT: stp w13, w14, [x2, #20]
; ENABLE-NEXT: sub sp, x29, #80 ; =80 ; ENABLE-NEXT: sub sp, x29, #80
; ENABLE-NEXT: ldp x29, x30, [sp, #80] ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x29, x30, [sp, #80] ; 16-byte Folded Reload
; ENABLE-NEXT: ldp x20, x19, [sp, #64] ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x20, x19, [sp, #64] ; 16-byte Folded Reload
; ENABLE-NEXT: ldp x22, x21, [sp, #48] ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x22, x21, [sp, #48] ; 16-byte Folded Reload
; ENABLE-NEXT: ldp x24, x23, [sp, #32] ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x24, x23, [sp, #32] ; 16-byte Folded Reload
; ENABLE-NEXT: ldp x26, x25, [sp, #16] ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x26, x25, [sp, #16] ; 16-byte Folded Reload
; ENABLE-NEXT: ldp x28, x27, [sp], #96 ; 16-byte Folded Reload ; ENABLE-NEXT: ldp x28, x27, [sp], #96 ; 16-byte Folded Reload
; ENABLE-NEXT: ret ; ENABLE-NEXT: ret
; ;
; DISABLE-LABEL: stack_realign2: ; DISABLE-LABEL: stack_realign2:
; DISABLE: ; %bb.0: ; DISABLE: ; %bb.0:
; DISABLE-NEXT: stp x28, x27, [sp, #-96]! ; 16-byte Folded Spill ; DISABLE-NEXT: stp x28, x27, [sp, #-96]! ; 16-byte Folded Spill
; DISABLE-NEXT: stp x26, x25, [sp, #16] ; 16-byte Folded Spill ; DISABLE-NEXT: stp x26, x25, [sp, #16] ; 16-byte Folded Spill
; DISABLE-NEXT: stp x24, x23, [sp, #32] ; 16-byte Folded Spill ; DISABLE-NEXT: stp x24, x23, [sp, #32] ; 16-byte Folded Spill
; DISABLE-NEXT: stp x22, x21, [sp, #48] ; 16-byte Folded Spill ; DISABLE-NEXT: stp x22, x21, [sp, #48] ; 16-byte Folded Spill
; DISABLE-NEXT: stp x20, x19, [sp, #64] ; 16-byte Folded Spill ; DISABLE-NEXT: stp x20, x19, [sp, #64] ; 16-byte Folded Spill
; DISABLE-NEXT: stp x29, x30, [sp, #80] ; 16-byte Folded Spill ; DISABLE-NEXT: stp x29, x30, [sp, #80] ; 16-byte Folded Spill
; DISABLE-NEXT: add x29, sp, #80 ; =80 ; DISABLE-NEXT: add x29, sp, #80
; DISABLE-NEXT: sub x9, sp, #32 ; =32 ; DISABLE-NEXT: sub x9, sp, #32
; DISABLE-NEXT: and sp, x9, #0xffffffffffffffe0 ; DISABLE-NEXT: and sp, x9, #0xffffffffffffffe0
; DISABLE-NEXT: .cfi_def_cfa w29, 16 ; DISABLE-NEXT: .cfi_def_cfa w29, 16
; DISABLE-NEXT: .cfi_offset w30, -8 ; DISABLE-NEXT: .cfi_offset w30, -8
; DISABLE-NEXT: .cfi_offset w29, -16 ; DISABLE-NEXT: .cfi_offset w29, -16
; DISABLE-NEXT: .cfi_offset w19, -24 ; DISABLE-NEXT: .cfi_offset w19, -24
; DISABLE-NEXT: .cfi_offset w20, -32 ; DISABLE-NEXT: .cfi_offset w20, -32
; DISABLE-NEXT: .cfi_offset w21, -40 ; DISABLE-NEXT: .cfi_offset w21, -40
; DISABLE-NEXT: .cfi_offset w22, -48 ; DISABLE-NEXT: .cfi_offset w22, -48
Show All 24 Lines
; DISABLE-NEXT: str w9, [x3] ; DISABLE-NEXT: str w9, [x3]
; DISABLE-NEXT: str w10, [x4] ; DISABLE-NEXT: str w10, [x4]
; DISABLE-NEXT: str w12, [x5] ; DISABLE-NEXT: str w12, [x5]
; DISABLE-NEXT: str w15, [x6] ; DISABLE-NEXT: str w15, [x6]
; DISABLE-NEXT: str w17, [x7] ; DISABLE-NEXT: str w17, [x7]
; DISABLE-NEXT: stp w0, w1, [x2, #4] ; DISABLE-NEXT: stp w0, w1, [x2, #4]
; DISABLE-NEXT: stp w16, w11, [x2, #12] ; DISABLE-NEXT: stp w16, w11, [x2, #12]
; DISABLE-NEXT: stp w13, w14, [x2, #20] ; DISABLE-NEXT: stp w13, w14, [x2, #20]
; DISABLE-NEXT: sub sp, x29, #80 ; =80 ; DISABLE-NEXT: sub sp, x29, #80
; DISABLE-NEXT: ldp x29, x30, [sp, #80] ; 16-byte Folded Reload ; DISABLE-NEXT: ldp x29, x30, [sp, #80] ; 16-byte Folded Reload
; DISABLE-NEXT: ldp x20, x19, [sp, #64] ; 16-byte Folded Reload ; DISABLE-NEXT: ldp x20, x19, [sp, #64] ; 16-byte Folded Reload
; DISABLE-NEXT: ldp x22, x21, [sp, #48] ; 16-byte Folded Reload ; DISABLE-NEXT: ldp x22, x21, [sp, #48] ; 16-byte Folded Reload
; DISABLE-NEXT: ldp x24, x23, [sp, #32] ; 16-byte Folded Reload ; DISABLE-NEXT: ldp x24, x23, [sp, #32] ; 16-byte Folded Reload
; DISABLE-NEXT: ldp x26, x25, [sp, #16] ; 16-byte Folded Reload ; DISABLE-NEXT: ldp x26, x25, [sp, #16] ; 16-byte Folded Reload
; DISABLE-NEXT: ldp x28, x27, [sp], #96 ; 16-byte Folded Reload ; DISABLE-NEXT: ldp x28, x27, [sp], #96 ; 16-byte Folded Reload
; DISABLE-NEXT: ret ; DISABLE-NEXT: ret
%tmp = alloca i32, align 32 %tmp = alloca i32, align 32
Show All 40 Lines

llvm/test/CodeGen/AArch64/arm64-vabs.ll

Show First 20 Lines • Show All 1,622 Lines • ▼ Show 20 Lines
; CHECK-NEXT: mov.d x11, v1[1] ; CHECK-NEXT: mov.d x11, v1[1]
; CHECK-NEXT: sbcs x10, x10, x13 ; CHECK-NEXT: sbcs x10, x10, x13
; CHECK-NEXT: asr x12, x8, #63 ; CHECK-NEXT: asr x12, x8, #63
; CHECK-NEXT: asr x14, x11, #63 ; CHECK-NEXT: asr x14, x11, #63
; CHECK-NEXT: subs x8, x8, x11 ; CHECK-NEXT: subs x8, x8, x11
; CHECK-NEXT: sbcs x11, x12, x14 ; CHECK-NEXT: sbcs x11, x12, x14
; CHECK-NEXT: negs x12, x8 ; CHECK-NEXT: negs x12, x8
; CHECK-NEXT: ngcs x13, x11 ; CHECK-NEXT: ngcs x13, x11
; CHECK-NEXT: cmp x11, #0 // =0 ; CHECK-NEXT: cmp x11, #0
; CHECK-NEXT: csel x2, x12, x8, lt ; CHECK-NEXT: csel x2, x12, x8, lt
; CHECK-NEXT: csel x3, x13, x11, lt ; CHECK-NEXT: csel x3, x13, x11, lt
; CHECK-NEXT: negs x8, x9 ; CHECK-NEXT: negs x8, x9
; CHECK-NEXT: ngcs x11, x10 ; CHECK-NEXT: ngcs x11, x10
; CHECK-NEXT: cmp x10, #0 // =0 ; CHECK-NEXT: cmp x10, #0
; CHECK-NEXT: csel x8, x8, x9, lt ; CHECK-NEXT: csel x8, x8, x9, lt
; CHECK-NEXT: csel x1, x11, x10, lt ; CHECK-NEXT: csel x1, x11, x10, lt
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: mov.d v0[1], x1 ; CHECK-NEXT: mov.d v0[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%aext = sext <2 x i64> %a to <2 x i128> %aext = sext <2 x i64> %a to <2 x i128>
%bext = sext <2 x i64> %b to <2 x i128> %bext = sext <2 x i64> %b to <2 x i128>
%abdiff = sub nsw <2 x i128> %aext, %bext %abdiff = sub nsw <2 x i128> %aext, %bext
%abcmp = icmp slt <2 x i128> %abdiff, zeroinitializer %abcmp = icmp slt <2 x i128> %abdiff, zeroinitializer
%ababs = sub nsw <2 x i128> zeroinitializer, %abdiff %ababs = sub nsw <2 x i128> zeroinitializer, %abdiff
%absel = select <2 x i1> %abcmp, <2 x i128> %ababs, <2 x i128> %abdiff %absel = select <2 x i1> %abcmp, <2 x i128> %ababs, <2 x i128> %abdiff
ret <2 x i128> %absel ret <2 x i128> %absel
} }

llvm/test/CodeGen/AArch64/atomicrmw-O0.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=aarch64-- -O0 -fast-isel=0 -global-isel=false %s -o - | FileCheck %s -check-prefix=NOLSE ; RUN: llc -verify-machineinstrs -mtriple=aarch64-- -O0 -fast-isel=0 -global-isel=false %s -o - | FileCheck %s -check-prefix=NOLSE
; RUN: llc -verify-machineinstrs -mtriple=aarch64-- -mattr=+lse -O0 -fast-isel=0 -global-isel=false %s -o - | FileCheck %s -check-prefix=LSE ; RUN: llc -verify-machineinstrs -mtriple=aarch64-- -mattr=+lse -O0 -fast-isel=0 -global-isel=false %s -o - | FileCheck %s -check-prefix=LSE
; Ensure there's no stack spill in between ldxr/stxr pairs. ; Ensure there's no stack spill in between ldxr/stxr pairs.
define i8 @test_rmw_add_8(i8* %dst) { define i8 @test_rmw_add_8(i8* %dst) {
; NOLSE-LABEL: test_rmw_add_8: ; NOLSE-LABEL: test_rmw_add_8:
; NOLSE: // %bb.0: // %entry ; NOLSE: // %bb.0: // %entry
; NOLSE-NEXT: sub sp, sp, #32 // =32 ; NOLSE-NEXT: sub sp, sp, #32
; NOLSE-NEXT: .cfi_def_cfa_offset 32 ; NOLSE-NEXT: .cfi_def_cfa_offset 32
; NOLSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill ; NOLSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill
; NOLSE-NEXT: ldrb w8, [x0] ; NOLSE-NEXT: ldrb w8, [x0]
; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; NOLSE-NEXT: b .LBB0_1 ; NOLSE-NEXT: b .LBB0_1
; NOLSE-NEXT: .LBB0_1: // %atomicrmw.start ; NOLSE-NEXT: .LBB0_1: // %atomicrmw.start
; NOLSE-NEXT: // =>This Loop Header: Depth=1 ; NOLSE-NEXT: // =>This Loop Header: Depth=1
; NOLSE-NEXT: // Child Loop BB0_2 Depth 2 ; NOLSE-NEXT: // Child Loop BB0_2 Depth 2
; NOLSE-NEXT: ldr w9, [sp, #28] // 4-byte Folded Reload ; NOLSE-NEXT: ldr w9, [sp, #28] // 4-byte Folded Reload
; NOLSE-NEXT: ldr x11, [sp, #16] // 8-byte Folded Reload ; NOLSE-NEXT: ldr x11, [sp, #16] // 8-byte Folded Reload
; NOLSE-NEXT: add w12, w9, #1 // =1 ; NOLSE-NEXT: add w12, w9, #1
; NOLSE-NEXT: .LBB0_2: // %atomicrmw.start ; NOLSE-NEXT: .LBB0_2: // %atomicrmw.start
; NOLSE-NEXT: // Parent Loop BB0_1 Depth=1 ; NOLSE-NEXT: // Parent Loop BB0_1 Depth=1
; NOLSE-NEXT: // => This Inner Loop Header: Depth=2 ; NOLSE-NEXT: // => This Inner Loop Header: Depth=2
; NOLSE-NEXT: ldaxrb w8, [x11] ; NOLSE-NEXT: ldaxrb w8, [x11]
; NOLSE-NEXT: cmp w8, w9, uxtb ; NOLSE-NEXT: cmp w8, w9, uxtb
; NOLSE-NEXT: b.ne .LBB0_4 ; NOLSE-NEXT: b.ne .LBB0_4
; NOLSE-NEXT: // %bb.3: // %atomicrmw.start ; NOLSE-NEXT: // %bb.3: // %atomicrmw.start
; NOLSE-NEXT: // in Loop: Header=BB0_2 Depth=2 ; NOLSE-NEXT: // in Loop: Header=BB0_2 Depth=2
; NOLSE-NEXT: stlxrb w10, w12, [x11] ; NOLSE-NEXT: stlxrb w10, w12, [x11]
; NOLSE-NEXT: cbnz w10, .LBB0_2 ; NOLSE-NEXT: cbnz w10, .LBB0_2
; NOLSE-NEXT: .LBB0_4: // %atomicrmw.start ; NOLSE-NEXT: .LBB0_4: // %atomicrmw.start
; NOLSE-NEXT: // in Loop: Header=BB0_1 Depth=1 ; NOLSE-NEXT: // in Loop: Header=BB0_1 Depth=1
; NOLSE-NEXT: subs w9, w8, w9, uxtb ; NOLSE-NEXT: subs w9, w8, w9, uxtb
; NOLSE-NEXT: cset w9, eq ; NOLSE-NEXT: cset w9, eq
; NOLSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill
; NOLSE-NEXT: subs w9, w9, #1 // =1 ; NOLSE-NEXT: subs w9, w9, #1
; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; NOLSE-NEXT: b.ne .LBB0_1 ; NOLSE-NEXT: b.ne .LBB0_1
; NOLSE-NEXT: b .LBB0_5 ; NOLSE-NEXT: b .LBB0_5
; NOLSE-NEXT: .LBB0_5: // %atomicrmw.end ; NOLSE-NEXT: .LBB0_5: // %atomicrmw.end
; NOLSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload ; NOLSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload
; NOLSE-NEXT: add sp, sp, #32 // =32 ; NOLSE-NEXT: add sp, sp, #32
; NOLSE-NEXT: ret ; NOLSE-NEXT: ret
; ;
; LSE-LABEL: test_rmw_add_8: ; LSE-LABEL: test_rmw_add_8:
; LSE: // %bb.0: // %entry ; LSE: // %bb.0: // %entry
; LSE-NEXT: mov w8, #1 ; LSE-NEXT: mov w8, #1
; LSE-NEXT: ldaddalb w8, w0, [x0] ; LSE-NEXT: ldaddalb w8, w0, [x0]
; LSE-NEXT: ret ; LSE-NEXT: ret
entry: entry:
%res = atomicrmw add i8* %dst, i8 1 seq_cst %res = atomicrmw add i8* %dst, i8 1 seq_cst
ret i8 %res ret i8 %res
} }
define i16 @test_rmw_add_16(i16* %dst) { define i16 @test_rmw_add_16(i16* %dst) {
; NOLSE-LABEL: test_rmw_add_16: ; NOLSE-LABEL: test_rmw_add_16:
; NOLSE: // %bb.0: // %entry ; NOLSE: // %bb.0: // %entry
; NOLSE-NEXT: sub sp, sp, #32 // =32 ; NOLSE-NEXT: sub sp, sp, #32
; NOLSE-NEXT: .cfi_def_cfa_offset 32 ; NOLSE-NEXT: .cfi_def_cfa_offset 32
; NOLSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill ; NOLSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill
; NOLSE-NEXT: ldrh w8, [x0] ; NOLSE-NEXT: ldrh w8, [x0]
; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; NOLSE-NEXT: b .LBB1_1 ; NOLSE-NEXT: b .LBB1_1
; NOLSE-NEXT: .LBB1_1: // %atomicrmw.start ; NOLSE-NEXT: .LBB1_1: // %atomicrmw.start
; NOLSE-NEXT: // =>This Loop Header: Depth=1 ; NOLSE-NEXT: // =>This Loop Header: Depth=1
; NOLSE-NEXT: // Child Loop BB1_2 Depth 2 ; NOLSE-NEXT: // Child Loop BB1_2 Depth 2
; NOLSE-NEXT: ldr w9, [sp, #28] // 4-byte Folded Reload ; NOLSE-NEXT: ldr w9, [sp, #28] // 4-byte Folded Reload
; NOLSE-NEXT: ldr x11, [sp, #16] // 8-byte Folded Reload ; NOLSE-NEXT: ldr x11, [sp, #16] // 8-byte Folded Reload
; NOLSE-NEXT: add w12, w9, #1 // =1 ; NOLSE-NEXT: add w12, w9, #1
; NOLSE-NEXT: .LBB1_2: // %atomicrmw.start ; NOLSE-NEXT: .LBB1_2: // %atomicrmw.start
; NOLSE-NEXT: // Parent Loop BB1_1 Depth=1 ; NOLSE-NEXT: // Parent Loop BB1_1 Depth=1
; NOLSE-NEXT: // => This Inner Loop Header: Depth=2 ; NOLSE-NEXT: // => This Inner Loop Header: Depth=2
; NOLSE-NEXT: ldaxrh w8, [x11] ; NOLSE-NEXT: ldaxrh w8, [x11]
; NOLSE-NEXT: cmp w8, w9, uxth ; NOLSE-NEXT: cmp w8, w9, uxth
; NOLSE-NEXT: b.ne .LBB1_4 ; NOLSE-NEXT: b.ne .LBB1_4
; NOLSE-NEXT: // %bb.3: // %atomicrmw.start ; NOLSE-NEXT: // %bb.3: // %atomicrmw.start
; NOLSE-NEXT: // in Loop: Header=BB1_2 Depth=2 ; NOLSE-NEXT: // in Loop: Header=BB1_2 Depth=2
; NOLSE-NEXT: stlxrh w10, w12, [x11] ; NOLSE-NEXT: stlxrh w10, w12, [x11]
; NOLSE-NEXT: cbnz w10, .LBB1_2 ; NOLSE-NEXT: cbnz w10, .LBB1_2
; NOLSE-NEXT: .LBB1_4: // %atomicrmw.start ; NOLSE-NEXT: .LBB1_4: // %atomicrmw.start
; NOLSE-NEXT: // in Loop: Header=BB1_1 Depth=1 ; NOLSE-NEXT: // in Loop: Header=BB1_1 Depth=1
; NOLSE-NEXT: subs w9, w8, w9, uxth ; NOLSE-NEXT: subs w9, w8, w9, uxth
; NOLSE-NEXT: cset w9, eq ; NOLSE-NEXT: cset w9, eq
; NOLSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill
; NOLSE-NEXT: subs w9, w9, #1 // =1 ; NOLSE-NEXT: subs w9, w9, #1
; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; NOLSE-NEXT: b.ne .LBB1_1 ; NOLSE-NEXT: b.ne .LBB1_1
; NOLSE-NEXT: b .LBB1_5 ; NOLSE-NEXT: b .LBB1_5
; NOLSE-NEXT: .LBB1_5: // %atomicrmw.end ; NOLSE-NEXT: .LBB1_5: // %atomicrmw.end
; NOLSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload ; NOLSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload
; NOLSE-NEXT: add sp, sp, #32 // =32 ; NOLSE-NEXT: add sp, sp, #32
; NOLSE-NEXT: ret ; NOLSE-NEXT: ret
; ;
; LSE-LABEL: test_rmw_add_16: ; LSE-LABEL: test_rmw_add_16:
; LSE: // %bb.0: // %entry ; LSE: // %bb.0: // %entry
; LSE-NEXT: mov w8, #1 ; LSE-NEXT: mov w8, #1
; LSE-NEXT: ldaddalh w8, w0, [x0] ; LSE-NEXT: ldaddalh w8, w0, [x0]
; LSE-NEXT: ret ; LSE-NEXT: ret
entry: entry:
%res = atomicrmw add i16* %dst, i16 1 seq_cst %res = atomicrmw add i16* %dst, i16 1 seq_cst
ret i16 %res ret i16 %res
} }
define i32 @test_rmw_add_32(i32* %dst) { define i32 @test_rmw_add_32(i32* %dst) {
; NOLSE-LABEL: test_rmw_add_32: ; NOLSE-LABEL: test_rmw_add_32:
; NOLSE: // %bb.0: // %entry ; NOLSE: // %bb.0: // %entry
; NOLSE-NEXT: sub sp, sp, #32 // =32 ; NOLSE-NEXT: sub sp, sp, #32
; NOLSE-NEXT: .cfi_def_cfa_offset 32 ; NOLSE-NEXT: .cfi_def_cfa_offset 32
; NOLSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill ; NOLSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill
; NOLSE-NEXT: ldr w8, [x0] ; NOLSE-NEXT: ldr w8, [x0]
; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; NOLSE-NEXT: b .LBB2_1 ; NOLSE-NEXT: b .LBB2_1
; NOLSE-NEXT: .LBB2_1: // %atomicrmw.start ; NOLSE-NEXT: .LBB2_1: // %atomicrmw.start
; NOLSE-NEXT: // =>This Loop Header: Depth=1 ; NOLSE-NEXT: // =>This Loop Header: Depth=1
; NOLSE-NEXT: // Child Loop BB2_2 Depth 2 ; NOLSE-NEXT: // Child Loop BB2_2 Depth 2
; NOLSE-NEXT: ldr w9, [sp, #28] // 4-byte Folded Reload ; NOLSE-NEXT: ldr w9, [sp, #28] // 4-byte Folded Reload
; NOLSE-NEXT: ldr x11, [sp, #16] // 8-byte Folded Reload ; NOLSE-NEXT: ldr x11, [sp, #16] // 8-byte Folded Reload
; NOLSE-NEXT: add w12, w9, #1 // =1 ; NOLSE-NEXT: add w12, w9, #1
; NOLSE-NEXT: .LBB2_2: // %atomicrmw.start ; NOLSE-NEXT: .LBB2_2: // %atomicrmw.start
; NOLSE-NEXT: // Parent Loop BB2_1 Depth=1 ; NOLSE-NEXT: // Parent Loop BB2_1 Depth=1
; NOLSE-NEXT: // => This Inner Loop Header: Depth=2 ; NOLSE-NEXT: // => This Inner Loop Header: Depth=2
; NOLSE-NEXT: ldaxr w8, [x11] ; NOLSE-NEXT: ldaxr w8, [x11]
; NOLSE-NEXT: cmp w8, w9 ; NOLSE-NEXT: cmp w8, w9
; NOLSE-NEXT: b.ne .LBB2_4 ; NOLSE-NEXT: b.ne .LBB2_4
; NOLSE-NEXT: // %bb.3: // %atomicrmw.start ; NOLSE-NEXT: // %bb.3: // %atomicrmw.start
; NOLSE-NEXT: // in Loop: Header=BB2_2 Depth=2 ; NOLSE-NEXT: // in Loop: Header=BB2_2 Depth=2
; NOLSE-NEXT: stlxr w10, w12, [x11] ; NOLSE-NEXT: stlxr w10, w12, [x11]
; NOLSE-NEXT: cbnz w10, .LBB2_2 ; NOLSE-NEXT: cbnz w10, .LBB2_2
; NOLSE-NEXT: .LBB2_4: // %atomicrmw.start ; NOLSE-NEXT: .LBB2_4: // %atomicrmw.start
; NOLSE-NEXT: // in Loop: Header=BB2_1 Depth=1 ; NOLSE-NEXT: // in Loop: Header=BB2_1 Depth=1
; NOLSE-NEXT: subs w9, w8, w9 ; NOLSE-NEXT: subs w9, w8, w9
; NOLSE-NEXT: cset w9, eq ; NOLSE-NEXT: cset w9, eq
; NOLSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill
; NOLSE-NEXT: subs w9, w9, #1 // =1 ; NOLSE-NEXT: subs w9, w9, #1
; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; NOLSE-NEXT: b.ne .LBB2_1 ; NOLSE-NEXT: b.ne .LBB2_1
; NOLSE-NEXT: b .LBB2_5 ; NOLSE-NEXT: b .LBB2_5
; NOLSE-NEXT: .LBB2_5: // %atomicrmw.end ; NOLSE-NEXT: .LBB2_5: // %atomicrmw.end
; NOLSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload ; NOLSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload
; NOLSE-NEXT: add sp, sp, #32 // =32 ; NOLSE-NEXT: add sp, sp, #32
; NOLSE-NEXT: ret ; NOLSE-NEXT: ret
; ;
; LSE-LABEL: test_rmw_add_32: ; LSE-LABEL: test_rmw_add_32:
; LSE: // %bb.0: // %entry ; LSE: // %bb.0: // %entry
; LSE-NEXT: mov w8, #1 ; LSE-NEXT: mov w8, #1
; LSE-NEXT: ldaddal w8, w0, [x0] ; LSE-NEXT: ldaddal w8, w0, [x0]
; LSE-NEXT: ret ; LSE-NEXT: ret
entry: entry:
%res = atomicrmw add i32* %dst, i32 1 seq_cst %res = atomicrmw add i32* %dst, i32 1 seq_cst
ret i32 %res ret i32 %res
} }
define i64 @test_rmw_add_64(i64* %dst) { define i64 @test_rmw_add_64(i64* %dst) {
; NOLSE-LABEL: test_rmw_add_64: ; NOLSE-LABEL: test_rmw_add_64:
; NOLSE: // %bb.0: // %entry ; NOLSE: // %bb.0: // %entry
; NOLSE-NEXT: sub sp, sp, #32 // =32 ; NOLSE-NEXT: sub sp, sp, #32
; NOLSE-NEXT: .cfi_def_cfa_offset 32 ; NOLSE-NEXT: .cfi_def_cfa_offset 32
; NOLSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill ; NOLSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill
; NOLSE-NEXT: ldr x8, [x0] ; NOLSE-NEXT: ldr x8, [x0]
; NOLSE-NEXT: str x8, [sp, #24] // 8-byte Folded Spill ; NOLSE-NEXT: str x8, [sp, #24] // 8-byte Folded Spill
; NOLSE-NEXT: b .LBB3_1 ; NOLSE-NEXT: b .LBB3_1
; NOLSE-NEXT: .LBB3_1: // %atomicrmw.start ; NOLSE-NEXT: .LBB3_1: // %atomicrmw.start
; NOLSE-NEXT: // =>This Loop Header: Depth=1 ; NOLSE-NEXT: // =>This Loop Header: Depth=1
; NOLSE-NEXT: // Child Loop BB3_2 Depth 2 ; NOLSE-NEXT: // Child Loop BB3_2 Depth 2
; NOLSE-NEXT: ldr x9, [sp, #24] // 8-byte Folded Reload ; NOLSE-NEXT: ldr x9, [sp, #24] // 8-byte Folded Reload
; NOLSE-NEXT: ldr x11, [sp, #16] // 8-byte Folded Reload ; NOLSE-NEXT: ldr x11, [sp, #16] // 8-byte Folded Reload
; NOLSE-NEXT: add x12, x9, #1 // =1 ; NOLSE-NEXT: add x12, x9, #1
; NOLSE-NEXT: .LBB3_2: // %atomicrmw.start ; NOLSE-NEXT: .LBB3_2: // %atomicrmw.start
; NOLSE-NEXT: // Parent Loop BB3_1 Depth=1 ; NOLSE-NEXT: // Parent Loop BB3_1 Depth=1
; NOLSE-NEXT: // => This Inner Loop Header: Depth=2 ; NOLSE-NEXT: // => This Inner Loop Header: Depth=2
; NOLSE-NEXT: ldaxr x8, [x11] ; NOLSE-NEXT: ldaxr x8, [x11]
; NOLSE-NEXT: cmp x8, x9 ; NOLSE-NEXT: cmp x8, x9
; NOLSE-NEXT: b.ne .LBB3_4 ; NOLSE-NEXT: b.ne .LBB3_4
; NOLSE-NEXT: // %bb.3: // %atomicrmw.start ; NOLSE-NEXT: // %bb.3: // %atomicrmw.start
; NOLSE-NEXT: // in Loop: Header=BB3_2 Depth=2 ; NOLSE-NEXT: // in Loop: Header=BB3_2 Depth=2
; NOLSE-NEXT: stlxr w10, x12, [x11] ; NOLSE-NEXT: stlxr w10, x12, [x11]
; NOLSE-NEXT: cbnz w10, .LBB3_2 ; NOLSE-NEXT: cbnz w10, .LBB3_2
; NOLSE-NEXT: .LBB3_4: // %atomicrmw.start ; NOLSE-NEXT: .LBB3_4: // %atomicrmw.start
; NOLSE-NEXT: // in Loop: Header=BB3_1 Depth=1 ; NOLSE-NEXT: // in Loop: Header=BB3_1 Depth=1
; NOLSE-NEXT: subs x9, x8, x9 ; NOLSE-NEXT: subs x9, x8, x9
; NOLSE-NEXT: cset w9, eq ; NOLSE-NEXT: cset w9, eq
; NOLSE-NEXT: str x8, [sp, #8] // 8-byte Folded Spill ; NOLSE-NEXT: str x8, [sp, #8] // 8-byte Folded Spill
; NOLSE-NEXT: subs w9, w9, #1 // =1 ; NOLSE-NEXT: subs w9, w9, #1
; NOLSE-NEXT: str x8, [sp, #24] // 8-byte Folded Spill ; NOLSE-NEXT: str x8, [sp, #24] // 8-byte Folded Spill
; NOLSE-NEXT: b.ne .LBB3_1 ; NOLSE-NEXT: b.ne .LBB3_1
; NOLSE-NEXT: b .LBB3_5 ; NOLSE-NEXT: b .LBB3_5
; NOLSE-NEXT: .LBB3_5: // %atomicrmw.end ; NOLSE-NEXT: .LBB3_5: // %atomicrmw.end
; NOLSE-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload ; NOLSE-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
; NOLSE-NEXT: add sp, sp, #32 // =32 ; NOLSE-NEXT: add sp, sp, #32
; NOLSE-NEXT: ret ; NOLSE-NEXT: ret
; ;
; LSE-LABEL: test_rmw_add_64: ; LSE-LABEL: test_rmw_add_64:
; LSE: // %bb.0: // %entry ; LSE: // %bb.0: // %entry
; LSE-NEXT: mov w8, #1 ; LSE-NEXT: mov w8, #1
; LSE-NEXT: // kill: def $x8 killed $w8 ; LSE-NEXT: // kill: def $x8 killed $w8
; LSE-NEXT: ldaddal x8, x0, [x0] ; LSE-NEXT: ldaddal x8, x0, [x0]
; LSE-NEXT: ret ; LSE-NEXT: ret
entry: entry:
%res = atomicrmw add i64* %dst, i64 1 seq_cst %res = atomicrmw add i64* %dst, i64 1 seq_cst
ret i64 %res ret i64 %res
} }
define i128 @test_rmw_add_128(i128* %dst) { define i128 @test_rmw_add_128(i128* %dst) {
; NOLSE-LABEL: test_rmw_add_128: ; NOLSE-LABEL: test_rmw_add_128:
; NOLSE: // %bb.0: // %entry ; NOLSE: // %bb.0: // %entry
; NOLSE-NEXT: sub sp, sp, #48 // =48 ; NOLSE-NEXT: sub sp, sp, #48
; NOLSE-NEXT: .cfi_def_cfa_offset 48 ; NOLSE-NEXT: .cfi_def_cfa_offset 48
; NOLSE-NEXT: str x0, [sp, #24] // 8-byte Folded Spill ; NOLSE-NEXT: str x0, [sp, #24] // 8-byte Folded Spill
; NOLSE-NEXT: ldr x8, [x0, #8] ; NOLSE-NEXT: ldr x8, [x0, #8]
; NOLSE-NEXT: ldr x9, [x0] ; NOLSE-NEXT: ldr x9, [x0]
; NOLSE-NEXT: str x9, [sp, #32] // 8-byte Folded Spill ; NOLSE-NEXT: str x9, [sp, #32] // 8-byte Folded Spill
; NOLSE-NEXT: str x8, [sp, #40] // 8-byte Folded Spill ; NOLSE-NEXT: str x8, [sp, #40] // 8-byte Folded Spill
; NOLSE-NEXT: b .LBB4_1 ; NOLSE-NEXT: b .LBB4_1
; NOLSE-NEXT: .LBB4_1: // %atomicrmw.start ; NOLSE-NEXT: .LBB4_1: // %atomicrmw.start
; NOLSE-NEXT: // =>This Loop Header: Depth=1 ; NOLSE-NEXT: // =>This Loop Header: Depth=1
; NOLSE-NEXT: // Child Loop BB4_2 Depth 2 ; NOLSE-NEXT: // Child Loop BB4_2 Depth 2
; NOLSE-NEXT: ldr x11, [sp, #40] // 8-byte Folded Reload ; NOLSE-NEXT: ldr x11, [sp, #40] // 8-byte Folded Reload
; NOLSE-NEXT: ldr x8, [sp, #32] // 8-byte Folded Reload ; NOLSE-NEXT: ldr x8, [sp, #32] // 8-byte Folded Reload
; NOLSE-NEXT: ldr x13, [sp, #24] // 8-byte Folded Reload ; NOLSE-NEXT: ldr x13, [sp, #24] // 8-byte Folded Reload
; NOLSE-NEXT: adds x14, x8, #1 // =1 ; NOLSE-NEXT: adds x14, x8, #1
; NOLSE-NEXT: mov x9, xzr ; NOLSE-NEXT: mov x9, xzr
; NOLSE-NEXT: adcs x15, x11, x9 ; NOLSE-NEXT: adcs x15, x11, x9
; NOLSE-NEXT: .LBB4_2: // %atomicrmw.start ; NOLSE-NEXT: .LBB4_2: // %atomicrmw.start
; NOLSE-NEXT: // Parent Loop BB4_1 Depth=1 ; NOLSE-NEXT: // Parent Loop BB4_1 Depth=1
; NOLSE-NEXT: // => This Inner Loop Header: Depth=2 ; NOLSE-NEXT: // => This Inner Loop Header: Depth=2
; NOLSE-NEXT: ldaxp x10, x9, [x13] ; NOLSE-NEXT: ldaxp x10, x9, [x13]
; NOLSE-NEXT: cmp x10, x8 ; NOLSE-NEXT: cmp x10, x8
; NOLSE-NEXT: cset w12, ne ; NOLSE-NEXT: cset w12, ne
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; NOLSE-NEXT: str x10, [sp, #16] // 8-byte Folded Spill ; NOLSE-NEXT: str x10, [sp, #16] // 8-byte Folded Spill
; NOLSE-NEXT: str x10, [sp, #32] // 8-byte Folded Spill ; NOLSE-NEXT: str x10, [sp, #32] // 8-byte Folded Spill
; NOLSE-NEXT: str x9, [sp, #40] // 8-byte Folded Spill ; NOLSE-NEXT: str x9, [sp, #40] // 8-byte Folded Spill
; NOLSE-NEXT: cbnz x8, .LBB4_1 ; NOLSE-NEXT: cbnz x8, .LBB4_1
; NOLSE-NEXT: b .LBB4_6 ; NOLSE-NEXT: b .LBB4_6
; NOLSE-NEXT: .LBB4_6: // %atomicrmw.end ; NOLSE-NEXT: .LBB4_6: // %atomicrmw.end
; NOLSE-NEXT: ldr x1, [sp, #8] // 8-byte Folded Reload ; NOLSE-NEXT: ldr x1, [sp, #8] // 8-byte Folded Reload
; NOLSE-NEXT: ldr x0, [sp, #16] // 8-byte Folded Reload ; NOLSE-NEXT: ldr x0, [sp, #16] // 8-byte Folded Reload
; NOLSE-NEXT: add sp, sp, #48 // =48 ; NOLSE-NEXT: add sp, sp, #48
; NOLSE-NEXT: ret ; NOLSE-NEXT: ret
; ;
; LSE-LABEL: test_rmw_add_128: ; LSE-LABEL: test_rmw_add_128:
; LSE: // %bb.0: // %entry ; LSE: // %bb.0: // %entry
; LSE-NEXT: sub sp, sp, #80 // =80 ; LSE-NEXT: sub sp, sp, #80
; LSE-NEXT: .cfi_def_cfa_offset 80 ; LSE-NEXT: .cfi_def_cfa_offset 80
; LSE-NEXT: str x0, [sp, #56] // 8-byte Folded Spill ; LSE-NEXT: str x0, [sp, #56] // 8-byte Folded Spill
; LSE-NEXT: ldr x8, [x0, #8] ; LSE-NEXT: ldr x8, [x0, #8]
; LSE-NEXT: ldr x9, [x0] ; LSE-NEXT: ldr x9, [x0]
; LSE-NEXT: str x9, [sp, #64] // 8-byte Folded Spill ; LSE-NEXT: str x9, [sp, #64] // 8-byte Folded Spill
; LSE-NEXT: str x8, [sp, #72] // 8-byte Folded Spill ; LSE-NEXT: str x8, [sp, #72] // 8-byte Folded Spill
; LSE-NEXT: b .LBB4_1 ; LSE-NEXT: b .LBB4_1
; LSE-NEXT: .LBB4_1: // %atomicrmw.start ; LSE-NEXT: .LBB4_1: // %atomicrmw.start
; LSE-NEXT: // =>This Inner Loop Header: Depth=1 ; LSE-NEXT: // =>This Inner Loop Header: Depth=1
; LSE-NEXT: ldr x10, [sp, #72] // 8-byte Folded Reload ; LSE-NEXT: ldr x10, [sp, #72] // 8-byte Folded Reload
; LSE-NEXT: ldr x8, [sp, #64] // 8-byte Folded Reload ; LSE-NEXT: ldr x8, [sp, #64] // 8-byte Folded Reload
; LSE-NEXT: ldr x9, [sp, #56] // 8-byte Folded Reload ; LSE-NEXT: ldr x9, [sp, #56] // 8-byte Folded Reload
; LSE-NEXT: adds x2, x8, #1 // =1 ; LSE-NEXT: adds x2, x8, #1
; LSE-NEXT: mov x11, xzr ; LSE-NEXT: mov x11, xzr
; LSE-NEXT: adcs x11, x10, x11 ; LSE-NEXT: adcs x11, x10, x11
; LSE-NEXT: // kill: def $x2 killed $x2 def $x2_x3 ; LSE-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; LSE-NEXT: mov x3, x11 ; LSE-NEXT: mov x3, x11
; LSE-NEXT: mov x0, x8 ; LSE-NEXT: mov x0, x8
; LSE-NEXT: mov x1, x10 ; LSE-NEXT: mov x1, x10
; LSE-NEXT: stp x0, x1, [sp, #8] // 16-byte Folded Spill ; LSE-NEXT: stp x0, x1, [sp, #8] // 16-byte Folded Spill
; LSE-NEXT: caspal x0, x1, x2, x3, [x9] ; LSE-NEXT: caspal x0, x1, x2, x3, [x9]
; LSE-NEXT: stp x0, x1, [sp, #24] // 16-byte Folded Spill ; LSE-NEXT: stp x0, x1, [sp, #24] // 16-byte Folded Spill
; LSE-NEXT: mov x9, x1 ; LSE-NEXT: mov x9, x1
; LSE-NEXT: str x9, [sp, #40] // 8-byte Folded Spill ; LSE-NEXT: str x9, [sp, #40] // 8-byte Folded Spill
; LSE-NEXT: eor x11, x9, x10 ; LSE-NEXT: eor x11, x9, x10
; LSE-NEXT: mov x10, x0 ; LSE-NEXT: mov x10, x0
; LSE-NEXT: str x10, [sp, #48] // 8-byte Folded Spill ; LSE-NEXT: str x10, [sp, #48] // 8-byte Folded Spill
; LSE-NEXT: eor x8, x10, x8 ; LSE-NEXT: eor x8, x10, x8
; LSE-NEXT: orr x8, x8, x11 ; LSE-NEXT: orr x8, x8, x11
; LSE-NEXT: str x10, [sp, #64] // 8-byte Folded Spill ; LSE-NEXT: str x10, [sp, #64] // 8-byte Folded Spill
; LSE-NEXT: str x9, [sp, #72] // 8-byte Folded Spill ; LSE-NEXT: str x9, [sp, #72] // 8-byte Folded Spill
; LSE-NEXT: cbnz x8, .LBB4_1 ; LSE-NEXT: cbnz x8, .LBB4_1
; LSE-NEXT: b .LBB4_2 ; LSE-NEXT: b .LBB4_2
; LSE-NEXT: .LBB4_2: // %atomicrmw.end ; LSE-NEXT: .LBB4_2: // %atomicrmw.end
; LSE-NEXT: ldr x1, [sp, #40] // 8-byte Folded Reload ; LSE-NEXT: ldr x1, [sp, #40] // 8-byte Folded Reload
; LSE-NEXT: ldr x0, [sp, #48] // 8-byte Folded Reload ; LSE-NEXT: ldr x0, [sp, #48] // 8-byte Folded Reload
; LSE-NEXT: add sp, sp, #80 // =80 ; LSE-NEXT: add sp, sp, #80
; LSE-NEXT: ret ; LSE-NEXT: ret
entry: entry:
%res = atomicrmw add i128* %dst, i128 1 seq_cst %res = atomicrmw add i128* %dst, i128 1 seq_cst
ret i128 %res ret i128 %res
} }
define i8 @test_rmw_nand_8(i8* %dst) { define i8 @test_rmw_nand_8(i8* %dst) {
; NOLSE-LABEL: test_rmw_nand_8: ; NOLSE-LABEL: test_rmw_nand_8:
; NOLSE: // %bb.0: // %entry ; NOLSE: // %bb.0: // %entry
; NOLSE-NEXT: sub sp, sp, #32 // =32 ; NOLSE-NEXT: sub sp, sp, #32
; NOLSE-NEXT: .cfi_def_cfa_offset 32 ; NOLSE-NEXT: .cfi_def_cfa_offset 32
; NOLSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill ; NOLSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill
; NOLSE-NEXT: ldrb w8, [x0] ; NOLSE-NEXT: ldrb w8, [x0]
; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; NOLSE-NEXT: b .LBB5_1 ; NOLSE-NEXT: b .LBB5_1
; NOLSE-NEXT: .LBB5_1: // %atomicrmw.start ; NOLSE-NEXT: .LBB5_1: // %atomicrmw.start
; NOLSE-NEXT: // =>This Loop Header: Depth=1 ; NOLSE-NEXT: // =>This Loop Header: Depth=1
; NOLSE-NEXT: // Child Loop BB5_2 Depth 2 ; NOLSE-NEXT: // Child Loop BB5_2 Depth 2
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; NOLSE-NEXT: // in Loop: Header=BB5_2 Depth=2 ; NOLSE-NEXT: // in Loop: Header=BB5_2 Depth=2
; NOLSE-NEXT: stlxrb w10, w12, [x11] ; NOLSE-NEXT: stlxrb w10, w12, [x11]
; NOLSE-NEXT: cbnz w10, .LBB5_2 ; NOLSE-NEXT: cbnz w10, .LBB5_2
; NOLSE-NEXT: .LBB5_4: // %atomicrmw.start ; NOLSE-NEXT: .LBB5_4: // %atomicrmw.start
; NOLSE-NEXT: // in Loop: Header=BB5_1 Depth=1 ; NOLSE-NEXT: // in Loop: Header=BB5_1 Depth=1
; NOLSE-NEXT: subs w9, w8, w9, uxtb ; NOLSE-NEXT: subs w9, w8, w9, uxtb
; NOLSE-NEXT: cset w9, eq ; NOLSE-NEXT: cset w9, eq
; NOLSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill
; NOLSE-NEXT: subs w9, w9, #1 // =1 ; NOLSE-NEXT: subs w9, w9, #1
; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; NOLSE-NEXT: b.ne .LBB5_1 ; NOLSE-NEXT: b.ne .LBB5_1
; NOLSE-NEXT: b .LBB5_5 ; NOLSE-NEXT: b .LBB5_5
; NOLSE-NEXT: .LBB5_5: // %atomicrmw.end ; NOLSE-NEXT: .LBB5_5: // %atomicrmw.end
; NOLSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload ; NOLSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload
; NOLSE-NEXT: add sp, sp, #32 // =32 ; NOLSE-NEXT: add sp, sp, #32
; NOLSE-NEXT: ret ; NOLSE-NEXT: ret
; ;
; LSE-LABEL: test_rmw_nand_8: ; LSE-LABEL: test_rmw_nand_8:
; LSE: // %bb.0: // %entry ; LSE: // %bb.0: // %entry
; LSE-NEXT: sub sp, sp, #32 // =32 ; LSE-NEXT: sub sp, sp, #32
; LSE-NEXT: .cfi_def_cfa_offset 32 ; LSE-NEXT: .cfi_def_cfa_offset 32
; LSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill ; LSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill
; LSE-NEXT: ldrb w8, [x0] ; LSE-NEXT: ldrb w8, [x0]
; LSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; LSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; LSE-NEXT: b .LBB5_1 ; LSE-NEXT: b .LBB5_1
; LSE-NEXT: .LBB5_1: // %atomicrmw.start ; LSE-NEXT: .LBB5_1: // %atomicrmw.start
; LSE-NEXT: // =>This Inner Loop Header: Depth=1 ; LSE-NEXT: // =>This Inner Loop Header: Depth=1
; LSE-NEXT: ldr w9, [sp, #28] // 4-byte Folded Reload ; LSE-NEXT: ldr w9, [sp, #28] // 4-byte Folded Reload
; LSE-NEXT: ldr x11, [sp, #16] // 8-byte Folded Reload ; LSE-NEXT: ldr x11, [sp, #16] // 8-byte Folded Reload
; LSE-NEXT: mvn w8, w9 ; LSE-NEXT: mvn w8, w9
; LSE-NEXT: orr w10, w8, #0xfffffffe ; LSE-NEXT: orr w10, w8, #0xfffffffe
; LSE-NEXT: mov w8, w9 ; LSE-NEXT: mov w8, w9
; LSE-NEXT: casalb w8, w10, [x11] ; LSE-NEXT: casalb w8, w10, [x11]
; LSE-NEXT: str w8, [sp, #8] // 4-byte Folded Spill ; LSE-NEXT: str w8, [sp, #8] // 4-byte Folded Spill
; LSE-NEXT: subs w9, w8, w9, uxtb ; LSE-NEXT: subs w9, w8, w9, uxtb
; LSE-NEXT: cset w9, eq ; LSE-NEXT: cset w9, eq
; LSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill ; LSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill
; LSE-NEXT: subs w9, w9, #1 // =1 ; LSE-NEXT: subs w9, w9, #1
; LSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; LSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; LSE-NEXT: b.ne .LBB5_1 ; LSE-NEXT: b.ne .LBB5_1
; LSE-NEXT: b .LBB5_2 ; LSE-NEXT: b .LBB5_2
; LSE-NEXT: .LBB5_2: // %atomicrmw.end ; LSE-NEXT: .LBB5_2: // %atomicrmw.end
; LSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload ; LSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload
; LSE-NEXT: add sp, sp, #32 // =32 ; LSE-NEXT: add sp, sp, #32
; LSE-NEXT: ret ; LSE-NEXT: ret
entry: entry:
%res = atomicrmw nand i8* %dst, i8 1 seq_cst %res = atomicrmw nand i8* %dst, i8 1 seq_cst
ret i8 %res ret i8 %res
} }
define i16 @test_rmw_nand_16(i16* %dst) { define i16 @test_rmw_nand_16(i16* %dst) {
; NOLSE-LABEL: test_rmw_nand_16: ; NOLSE-LABEL: test_rmw_nand_16:
; NOLSE: // %bb.0: // %entry ; NOLSE: // %bb.0: // %entry
; NOLSE-NEXT: sub sp, sp, #32 // =32 ; NOLSE-NEXT: sub sp, sp, #32
; NOLSE-NEXT: .cfi_def_cfa_offset 32 ; NOLSE-NEXT: .cfi_def_cfa_offset 32
; NOLSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill ; NOLSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill
; NOLSE-NEXT: ldrh w8, [x0] ; NOLSE-NEXT: ldrh w8, [x0]
; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; NOLSE-NEXT: b .LBB6_1 ; NOLSE-NEXT: b .LBB6_1
; NOLSE-NEXT: .LBB6_1: // %atomicrmw.start ; NOLSE-NEXT: .LBB6_1: // %atomicrmw.start
; NOLSE-NEXT: // =>This Loop Header: Depth=1 ; NOLSE-NEXT: // =>This Loop Header: Depth=1
; NOLSE-NEXT: // Child Loop BB6_2 Depth 2 ; NOLSE-NEXT: // Child Loop BB6_2 Depth 2
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; NOLSE-NEXT: // in Loop: Header=BB6_2 Depth=2 ; NOLSE-NEXT: // in Loop: Header=BB6_2 Depth=2
; NOLSE-NEXT: stlxrh w10, w12, [x11] ; NOLSE-NEXT: stlxrh w10, w12, [x11]
; NOLSE-NEXT: cbnz w10, .LBB6_2 ; NOLSE-NEXT: cbnz w10, .LBB6_2
; NOLSE-NEXT: .LBB6_4: // %atomicrmw.start ; NOLSE-NEXT: .LBB6_4: // %atomicrmw.start
; NOLSE-NEXT: // in Loop: Header=BB6_1 Depth=1 ; NOLSE-NEXT: // in Loop: Header=BB6_1 Depth=1
; NOLSE-NEXT: subs w9, w8, w9, uxth ; NOLSE-NEXT: subs w9, w8, w9, uxth
; NOLSE-NEXT: cset w9, eq ; NOLSE-NEXT: cset w9, eq
; NOLSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill
; NOLSE-NEXT: subs w9, w9, #1 // =1 ; NOLSE-NEXT: subs w9, w9, #1
; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; NOLSE-NEXT: b.ne .LBB6_1 ; NOLSE-NEXT: b.ne .LBB6_1
; NOLSE-NEXT: b .LBB6_5 ; NOLSE-NEXT: b .LBB6_5
; NOLSE-NEXT: .LBB6_5: // %atomicrmw.end ; NOLSE-NEXT: .LBB6_5: // %atomicrmw.end
; NOLSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload ; NOLSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload
; NOLSE-NEXT: add sp, sp, #32 // =32 ; NOLSE-NEXT: add sp, sp, #32
; NOLSE-NEXT: ret ; NOLSE-NEXT: ret
; ;
; LSE-LABEL: test_rmw_nand_16: ; LSE-LABEL: test_rmw_nand_16:
; LSE: // %bb.0: // %entry ; LSE: // %bb.0: // %entry
; LSE-NEXT: sub sp, sp, #32 // =32 ; LSE-NEXT: sub sp, sp, #32
; LSE-NEXT: .cfi_def_cfa_offset 32 ; LSE-NEXT: .cfi_def_cfa_offset 32
; LSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill ; LSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill
; LSE-NEXT: ldrh w8, [x0] ; LSE-NEXT: ldrh w8, [x0]
; LSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; LSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; LSE-NEXT: b .LBB6_1 ; LSE-NEXT: b .LBB6_1
; LSE-NEXT: .LBB6_1: // %atomicrmw.start ; LSE-NEXT: .LBB6_1: // %atomicrmw.start
; LSE-NEXT: // =>This Inner Loop Header: Depth=1 ; LSE-NEXT: // =>This Inner Loop Header: Depth=1
; LSE-NEXT: ldr w9, [sp, #28] // 4-byte Folded Reload ; LSE-NEXT: ldr w9, [sp, #28] // 4-byte Folded Reload
; LSE-NEXT: ldr x11, [sp, #16] // 8-byte Folded Reload ; LSE-NEXT: ldr x11, [sp, #16] // 8-byte Folded Reload
; LSE-NEXT: mvn w8, w9 ; LSE-NEXT: mvn w8, w9
; LSE-NEXT: orr w10, w8, #0xfffffffe ; LSE-NEXT: orr w10, w8, #0xfffffffe
; LSE-NEXT: mov w8, w9 ; LSE-NEXT: mov w8, w9
; LSE-NEXT: casalh w8, w10, [x11] ; LSE-NEXT: casalh w8, w10, [x11]
; LSE-NEXT: str w8, [sp, #8] // 4-byte Folded Spill ; LSE-NEXT: str w8, [sp, #8] // 4-byte Folded Spill
; LSE-NEXT: subs w9, w8, w9, uxth ; LSE-NEXT: subs w9, w8, w9, uxth
; LSE-NEXT: cset w9, eq ; LSE-NEXT: cset w9, eq
; LSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill ; LSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill
; LSE-NEXT: subs w9, w9, #1 // =1 ; LSE-NEXT: subs w9, w9, #1
; LSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; LSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; LSE-NEXT: b.ne .LBB6_1 ; LSE-NEXT: b.ne .LBB6_1
; LSE-NEXT: b .LBB6_2 ; LSE-NEXT: b .LBB6_2
; LSE-NEXT: .LBB6_2: // %atomicrmw.end ; LSE-NEXT: .LBB6_2: // %atomicrmw.end
; LSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload ; LSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload
; LSE-NEXT: add sp, sp, #32 // =32 ; LSE-NEXT: add sp, sp, #32
; LSE-NEXT: ret ; LSE-NEXT: ret
entry: entry:
%res = atomicrmw nand i16* %dst, i16 1 seq_cst %res = atomicrmw nand i16* %dst, i16 1 seq_cst
ret i16 %res ret i16 %res
} }
define i32 @test_rmw_nand_32(i32* %dst) { define i32 @test_rmw_nand_32(i32* %dst) {
; NOLSE-LABEL: test_rmw_nand_32: ; NOLSE-LABEL: test_rmw_nand_32:
; NOLSE: // %bb.0: // %entry ; NOLSE: // %bb.0: // %entry
; NOLSE-NEXT: sub sp, sp, #32 // =32 ; NOLSE-NEXT: sub sp, sp, #32
; NOLSE-NEXT: .cfi_def_cfa_offset 32 ; NOLSE-NEXT: .cfi_def_cfa_offset 32
; NOLSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill ; NOLSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill
; NOLSE-NEXT: ldr w8, [x0] ; NOLSE-NEXT: ldr w8, [x0]
; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; NOLSE-NEXT: b .LBB7_1 ; NOLSE-NEXT: b .LBB7_1
; NOLSE-NEXT: .LBB7_1: // %atomicrmw.start ; NOLSE-NEXT: .LBB7_1: // %atomicrmw.start
; NOLSE-NEXT: // =>This Loop Header: Depth=1 ; NOLSE-NEXT: // =>This Loop Header: Depth=1
; NOLSE-NEXT: // Child Loop BB7_2 Depth 2 ; NOLSE-NEXT: // Child Loop BB7_2 Depth 2
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; NOLSE-NEXT: // in Loop: Header=BB7_2 Depth=2 ; NOLSE-NEXT: // in Loop: Header=BB7_2 Depth=2
; NOLSE-NEXT: stlxr w10, w12, [x11] ; NOLSE-NEXT: stlxr w10, w12, [x11]
; NOLSE-NEXT: cbnz w10, .LBB7_2 ; NOLSE-NEXT: cbnz w10, .LBB7_2
; NOLSE-NEXT: .LBB7_4: // %atomicrmw.start ; NOLSE-NEXT: .LBB7_4: // %atomicrmw.start
; NOLSE-NEXT: // in Loop: Header=BB7_1 Depth=1 ; NOLSE-NEXT: // in Loop: Header=BB7_1 Depth=1
; NOLSE-NEXT: subs w9, w8, w9 ; NOLSE-NEXT: subs w9, w8, w9
; NOLSE-NEXT: cset w9, eq ; NOLSE-NEXT: cset w9, eq
; NOLSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill
; NOLSE-NEXT: subs w9, w9, #1 // =1 ; NOLSE-NEXT: subs w9, w9, #1
; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; NOLSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; NOLSE-NEXT: b.ne .LBB7_1 ; NOLSE-NEXT: b.ne .LBB7_1
; NOLSE-NEXT: b .LBB7_5 ; NOLSE-NEXT: b .LBB7_5
; NOLSE-NEXT: .LBB7_5: // %atomicrmw.end ; NOLSE-NEXT: .LBB7_5: // %atomicrmw.end
; NOLSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload ; NOLSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload
; NOLSE-NEXT: add sp, sp, #32 // =32 ; NOLSE-NEXT: add sp, sp, #32
; NOLSE-NEXT: ret ; NOLSE-NEXT: ret
; ;
; LSE-LABEL: test_rmw_nand_32: ; LSE-LABEL: test_rmw_nand_32:
; LSE: // %bb.0: // %entry ; LSE: // %bb.0: // %entry
; LSE-NEXT: sub sp, sp, #32 // =32 ; LSE-NEXT: sub sp, sp, #32
; LSE-NEXT: .cfi_def_cfa_offset 32 ; LSE-NEXT: .cfi_def_cfa_offset 32
; LSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill ; LSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill
; LSE-NEXT: ldr w8, [x0] ; LSE-NEXT: ldr w8, [x0]
; LSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; LSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; LSE-NEXT: b .LBB7_1 ; LSE-NEXT: b .LBB7_1
; LSE-NEXT: .LBB7_1: // %atomicrmw.start ; LSE-NEXT: .LBB7_1: // %atomicrmw.start
; LSE-NEXT: // =>This Inner Loop Header: Depth=1 ; LSE-NEXT: // =>This Inner Loop Header: Depth=1
; LSE-NEXT: ldr w9, [sp, #28] // 4-byte Folded Reload ; LSE-NEXT: ldr w9, [sp, #28] // 4-byte Folded Reload
; LSE-NEXT: ldr x11, [sp, #16] // 8-byte Folded Reload ; LSE-NEXT: ldr x11, [sp, #16] // 8-byte Folded Reload
; LSE-NEXT: mvn w8, w9 ; LSE-NEXT: mvn w8, w9
; LSE-NEXT: orr w10, w8, #0xfffffffe ; LSE-NEXT: orr w10, w8, #0xfffffffe
; LSE-NEXT: mov w8, w9 ; LSE-NEXT: mov w8, w9
; LSE-NEXT: casal w8, w10, [x11] ; LSE-NEXT: casal w8, w10, [x11]
; LSE-NEXT: str w8, [sp, #8] // 4-byte Folded Spill ; LSE-NEXT: str w8, [sp, #8] // 4-byte Folded Spill
; LSE-NEXT: subs w9, w8, w9 ; LSE-NEXT: subs w9, w8, w9
; LSE-NEXT: cset w9, eq ; LSE-NEXT: cset w9, eq
; LSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill ; LSE-NEXT: str w8, [sp, #12] // 4-byte Folded Spill
; LSE-NEXT: subs w9, w9, #1 // =1 ; LSE-NEXT: subs w9, w9, #1
; LSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill ; LSE-NEXT: str w8, [sp, #28] // 4-byte Folded Spill
; LSE-NEXT: b.ne .LBB7_1 ; LSE-NEXT: b.ne .LBB7_1
; LSE-NEXT: b .LBB7_2 ; LSE-NEXT: b .LBB7_2
; LSE-NEXT: .LBB7_2: // %atomicrmw.end ; LSE-NEXT: .LBB7_2: // %atomicrmw.end
; LSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload ; LSE-NEXT: ldr w0, [sp, #12] // 4-byte Folded Reload
; LSE-NEXT: add sp, sp, #32 // =32 ; LSE-NEXT: add sp, sp, #32
; LSE-NEXT: ret ; LSE-NEXT: ret
entry: entry:
%res = atomicrmw nand i32* %dst, i32 1 seq_cst %res = atomicrmw nand i32* %dst, i32 1 seq_cst
ret i32 %res ret i32 %res
} }
define i64 @test_rmw_nand_64(i64* %dst) { define i64 @test_rmw_nand_64(i64* %dst) {
; NOLSE-LABEL: test_rmw_nand_64: ; NOLSE-LABEL: test_rmw_nand_64:
; NOLSE: // %bb.0: // %entry ; NOLSE: // %bb.0: // %entry
; NOLSE-NEXT: sub sp, sp, #32 // =32 ; NOLSE-NEXT: sub sp, sp, #32
; NOLSE-NEXT: .cfi_def_cfa_offset 32 ; NOLSE-NEXT: .cfi_def_cfa_offset 32
; NOLSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill ; NOLSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill
; NOLSE-NEXT: ldr x8, [x0] ; NOLSE-NEXT: ldr x8, [x0]
; NOLSE-NEXT: str x8, [sp, #24] // 8-byte Folded Spill ; NOLSE-NEXT: str x8, [sp, #24] // 8-byte Folded Spill
; NOLSE-NEXT: b .LBB8_1 ; NOLSE-NEXT: b .LBB8_1
; NOLSE-NEXT: .LBB8_1: // %atomicrmw.start ; NOLSE-NEXT: .LBB8_1: // %atomicrmw.start
; NOLSE-NEXT: // =>This Loop Header: Depth=1 ; NOLSE-NEXT: // =>This Loop Header: Depth=1
; NOLSE-NEXT: // Child Loop BB8_2 Depth 2 ; NOLSE-NEXT: // Child Loop BB8_2 Depth 2
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; NOLSE-NEXT: // in Loop: Header=BB8_2 Depth=2 ; NOLSE-NEXT: // in Loop: Header=BB8_2 Depth=2
; NOLSE-NEXT: stlxr w10, x12, [x11] ; NOLSE-NEXT: stlxr w10, x12, [x11]
; NOLSE-NEXT: cbnz w10, .LBB8_2 ; NOLSE-NEXT: cbnz w10, .LBB8_2
; NOLSE-NEXT: .LBB8_4: // %atomicrmw.start ; NOLSE-NEXT: .LBB8_4: // %atomicrmw.start
; NOLSE-NEXT: // in Loop: Header=BB8_1 Depth=1 ; NOLSE-NEXT: // in Loop: Header=BB8_1 Depth=1
; NOLSE-NEXT: subs x9, x8, x9 ; NOLSE-NEXT: subs x9, x8, x9
; NOLSE-NEXT: cset w9, eq ; NOLSE-NEXT: cset w9, eq
; NOLSE-NEXT: str x8, [sp, #8] // 8-byte Folded Spill ; NOLSE-NEXT: str x8, [sp, #8] // 8-byte Folded Spill
; NOLSE-NEXT: subs w9, w9, #1 // =1 ; NOLSE-NEXT: subs w9, w9, #1
; NOLSE-NEXT: str x8, [sp, #24] // 8-byte Folded Spill ; NOLSE-NEXT: str x8, [sp, #24] // 8-byte Folded Spill
; NOLSE-NEXT: b.ne .LBB8_1 ; NOLSE-NEXT: b.ne .LBB8_1
; NOLSE-NEXT: b .LBB8_5 ; NOLSE-NEXT: b .LBB8_5
; NOLSE-NEXT: .LBB8_5: // %atomicrmw.end ; NOLSE-NEXT: .LBB8_5: // %atomicrmw.end
; NOLSE-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload ; NOLSE-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
; NOLSE-NEXT: add sp, sp, #32 // =32 ; NOLSE-NEXT: add sp, sp, #32
; NOLSE-NEXT: ret ; NOLSE-NEXT: ret
; ;
; LSE-LABEL: test_rmw_nand_64: ; LSE-LABEL: test_rmw_nand_64:
; LSE: // %bb.0: // %entry ; LSE: // %bb.0: // %entry
; LSE-NEXT: sub sp, sp, #32 // =32 ; LSE-NEXT: sub sp, sp, #32
; LSE-NEXT: .cfi_def_cfa_offset 32 ; LSE-NEXT: .cfi_def_cfa_offset 32
; LSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill ; LSE-NEXT: str x0, [sp, #16] // 8-byte Folded Spill
; LSE-NEXT: ldr x8, [x0] ; LSE-NEXT: ldr x8, [x0]
; LSE-NEXT: str x8, [sp, #24] // 8-byte Folded Spill ; LSE-NEXT: str x8, [sp, #24] // 8-byte Folded Spill
; LSE-NEXT: b .LBB8_1 ; LSE-NEXT: b .LBB8_1
; LSE-NEXT: .LBB8_1: // %atomicrmw.start ; LSE-NEXT: .LBB8_1: // %atomicrmw.start
; LSE-NEXT: // =>This Inner Loop Header: Depth=1 ; LSE-NEXT: // =>This Inner Loop Header: Depth=1
; LSE-NEXT: ldr x9, [sp, #24] // 8-byte Folded Reload ; LSE-NEXT: ldr x9, [sp, #24] // 8-byte Folded Reload
; LSE-NEXT: ldr x11, [sp, #16] // 8-byte Folded Reload ; LSE-NEXT: ldr x11, [sp, #16] // 8-byte Folded Reload
; LSE-NEXT: mov w8, w9 ; LSE-NEXT: mov w8, w9
; LSE-NEXT: mvn w10, w8 ; LSE-NEXT: mvn w10, w8
; LSE-NEXT: // implicit-def: $x8 ; LSE-NEXT: // implicit-def: $x8
; LSE-NEXT: mov w8, w10 ; LSE-NEXT: mov w8, w10
; LSE-NEXT: orr x10, x8, #0xfffffffffffffffe ; LSE-NEXT: orr x10, x8, #0xfffffffffffffffe
; LSE-NEXT: mov x8, x9 ; LSE-NEXT: mov x8, x9
; LSE-NEXT: casal x8, x10, [x11] ; LSE-NEXT: casal x8, x10, [x11]
; LSE-NEXT: str x8, [sp] // 8-byte Folded Spill ; LSE-NEXT: str x8, [sp] // 8-byte Folded Spill
; LSE-NEXT: subs x9, x8, x9 ; LSE-NEXT: subs x9, x8, x9
; LSE-NEXT: cset w9, eq ; LSE-NEXT: cset w9, eq
; LSE-NEXT: str x8, [sp, #8] // 8-byte Folded Spill ; LSE-NEXT: str x8, [sp, #8] // 8-byte Folded Spill
; LSE-NEXT: subs w9, w9, #1 // =1 ; LSE-NEXT: subs w9, w9, #1
; LSE-NEXT: str x8, [sp, #24] // 8-byte Folded Spill ; LSE-NEXT: str x8, [sp, #24] // 8-byte Folded Spill
; LSE-NEXT: b.ne .LBB8_1 ; LSE-NEXT: b.ne .LBB8_1
; LSE-NEXT: b .LBB8_2 ; LSE-NEXT: b .LBB8_2
; LSE-NEXT: .LBB8_2: // %atomicrmw.end ; LSE-NEXT: .LBB8_2: // %atomicrmw.end
; LSE-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload ; LSE-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
; LSE-NEXT: add sp, sp, #32 // =32 ; LSE-NEXT: add sp, sp, #32
; LSE-NEXT: ret ; LSE-NEXT: ret
entry: entry:
%res = atomicrmw nand i64* %dst, i64 1 seq_cst %res = atomicrmw nand i64* %dst, i64 1 seq_cst
ret i64 %res ret i64 %res
} }
define i128 @test_rmw_nand_128(i128* %dst) { define i128 @test_rmw_nand_128(i128* %dst) {
; NOLSE-LABEL: test_rmw_nand_128: ; NOLSE-LABEL: test_rmw_nand_128:
; NOLSE: // %bb.0: // %entry ; NOLSE: // %bb.0: // %entry
; NOLSE-NEXT: sub sp, sp, #48 // =48 ; NOLSE-NEXT: sub sp, sp, #48
; NOLSE-NEXT: .cfi_def_cfa_offset 48 ; NOLSE-NEXT: .cfi_def_cfa_offset 48
; NOLSE-NEXT: str x0, [sp, #24] // 8-byte Folded Spill ; NOLSE-NEXT: str x0, [sp, #24] // 8-byte Folded Spill
; NOLSE-NEXT: ldr x8, [x0, #8] ; NOLSE-NEXT: ldr x8, [x0, #8]
; NOLSE-NEXT: ldr x9, [x0] ; NOLSE-NEXT: ldr x9, [x0]
; NOLSE-NEXT: str x9, [sp, #32] // 8-byte Folded Spill ; NOLSE-NEXT: str x9, [sp, #32] // 8-byte Folded Spill
; NOLSE-NEXT: str x8, [sp, #40] // 8-byte Folded Spill ; NOLSE-NEXT: str x8, [sp, #40] // 8-byte Folded Spill
; NOLSE-NEXT: b .LBB9_1 ; NOLSE-NEXT: b .LBB9_1
; NOLSE-NEXT: .LBB9_1: // %atomicrmw.start ; NOLSE-NEXT: .LBB9_1: // %atomicrmw.start
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; NOLSE-NEXT: str x10, [sp, #16] // 8-byte Folded Spill ; NOLSE-NEXT: str x10, [sp, #16] // 8-byte Folded Spill
; NOLSE-NEXT: str x10, [sp, #32] // 8-byte Folded Spill ; NOLSE-NEXT: str x10, [sp, #32] // 8-byte Folded Spill
; NOLSE-NEXT: str x9, [sp, #40] // 8-byte Folded Spill ; NOLSE-NEXT: str x9, [sp, #40] // 8-byte Folded Spill
; NOLSE-NEXT: cbnz x8, .LBB9_1 ; NOLSE-NEXT: cbnz x8, .LBB9_1
; NOLSE-NEXT: b .LBB9_6 ; NOLSE-NEXT: b .LBB9_6
; NOLSE-NEXT: .LBB9_6: // %atomicrmw.end ; NOLSE-NEXT: .LBB9_6: // %atomicrmw.end
; NOLSE-NEXT: ldr x1, [sp, #8] // 8-byte Folded Reload ; NOLSE-NEXT: ldr x1, [sp, #8] // 8-byte Folded Reload
; NOLSE-NEXT: ldr x0, [sp, #16] // 8-byte Folded Reload ; NOLSE-NEXT: ldr x0, [sp, #16] // 8-byte Folded Reload
; NOLSE-NEXT: add sp, sp, #48 // =48 ; NOLSE-NEXT: add sp, sp, #48
; NOLSE-NEXT: ret ; NOLSE-NEXT: ret
; ;
; LSE-LABEL: test_rmw_nand_128: ; LSE-LABEL: test_rmw_nand_128:
; LSE: // %bb.0: // %entry ; LSE: // %bb.0: // %entry
; LSE-NEXT: sub sp, sp, #80 // =80 ; LSE-NEXT: sub sp, sp, #80
; LSE-NEXT: .cfi_def_cfa_offset 80 ; LSE-NEXT: .cfi_def_cfa_offset 80
; LSE-NEXT: str x0, [sp, #56] // 8-byte Folded Spill ; LSE-NEXT: str x0, [sp, #56] // 8-byte Folded Spill
; LSE-NEXT: ldr x8, [x0, #8] ; LSE-NEXT: ldr x8, [x0, #8]
; LSE-NEXT: ldr x9, [x0] ; LSE-NEXT: ldr x9, [x0]
; LSE-NEXT: str x9, [sp, #64] // 8-byte Folded Spill ; LSE-NEXT: str x9, [sp, #64] // 8-byte Folded Spill
; LSE-NEXT: str x8, [sp, #72] // 8-byte Folded Spill ; LSE-NEXT: str x8, [sp, #72] // 8-byte Folded Spill
; LSE-NEXT: b .LBB9_1 ; LSE-NEXT: b .LBB9_1
; LSE-NEXT: .LBB9_1: // %atomicrmw.start ; LSE-NEXT: .LBB9_1: // %atomicrmw.start
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; LSE-NEXT: orr x8, x8, x11 ; LSE-NEXT: orr x8, x8, x11
; LSE-NEXT: str x10, [sp, #64] // 8-byte Folded Spill ; LSE-NEXT: str x10, [sp, #64] // 8-byte Folded Spill
; LSE-NEXT: str x9, [sp, #72] // 8-byte Folded Spill ; LSE-NEXT: str x9, [sp, #72] // 8-byte Folded Spill
; LSE-NEXT: cbnz x8, .LBB9_1 ; LSE-NEXT: cbnz x8, .LBB9_1
; LSE-NEXT: b .LBB9_2 ; LSE-NEXT: b .LBB9_2
; LSE-NEXT: .LBB9_2: // %atomicrmw.end ; LSE-NEXT: .LBB9_2: // %atomicrmw.end
; LSE-NEXT: ldr x1, [sp, #40] // 8-byte Folded Reload ; LSE-NEXT: ldr x1, [sp, #40] // 8-byte Folded Reload
; LSE-NEXT: ldr x0, [sp, #48] // 8-byte Folded Reload ; LSE-NEXT: ldr x0, [sp, #48] // 8-byte Folded Reload
; LSE-NEXT: add sp, sp, #80 // =80 ; LSE-NEXT: add sp, sp, #80
; LSE-NEXT: ret ; LSE-NEXT: ret
entry: entry:
%res = atomicrmw nand i128* %dst, i128 1 seq_cst %res = atomicrmw nand i128* %dst, i128 1 seq_cst
ret i128 %res ret i128 %res
} }

llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; LSE-NEXT: ret ; LSE-NEXT: ret
%res = atomicrmw xchg double* %dst, double %new seq_cst %res = atomicrmw xchg double* %dst, double %new seq_cst
ret double %res ret double %res
} }
define fp128 @test_rmw_xchg_f128(fp128* %dst, fp128 %new) { define fp128 @test_rmw_xchg_f128(fp128* %dst, fp128 %new) {
; NOLSE-LABEL: test_rmw_xchg_f128: ; NOLSE-LABEL: test_rmw_xchg_f128:
; NOLSE: // %bb.0: ; NOLSE: // %bb.0:
; NOLSE-NEXT: sub sp, sp, #32 // =32 ; NOLSE-NEXT: sub sp, sp, #32
; NOLSE-NEXT: .cfi_def_cfa_offset 32 ; NOLSE-NEXT: .cfi_def_cfa_offset 32
; NOLSE-NEXT: str q0, [sp, #16] ; NOLSE-NEXT: str q0, [sp, #16]
; NOLSE-NEXT: ldp x9, x8, [sp, #16] ; NOLSE-NEXT: ldp x9, x8, [sp, #16]
; NOLSE-NEXT: .LBB3_1: // %atomicrmw.start ; NOLSE-NEXT: .LBB3_1: // %atomicrmw.start
; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1
; NOLSE-NEXT: ldaxp x11, x10, [x0] ; NOLSE-NEXT: ldaxp x11, x10, [x0]
; NOLSE-NEXT: stlxp w12, x9, x8, [x0] ; NOLSE-NEXT: stlxp w12, x9, x8, [x0]
; NOLSE-NEXT: cbnz w12, .LBB3_1 ; NOLSE-NEXT: cbnz w12, .LBB3_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
; NOLSE-NEXT: stp x11, x10, [sp] ; NOLSE-NEXT: stp x11, x10, [sp]
; NOLSE-NEXT: ldr q0, [sp], #32 ; NOLSE-NEXT: ldr q0, [sp], #32
; NOLSE-NEXT: ret ; NOLSE-NEXT: ret
; ;
; LSE-LABEL: test_rmw_xchg_f128: ; LSE-LABEL: test_rmw_xchg_f128:
; LSE: // %bb.0: ; LSE: // %bb.0:
; LSE-NEXT: sub sp, sp, #32 // =32 ; LSE-NEXT: sub sp, sp, #32
; LSE-NEXT: .cfi_def_cfa_offset 32 ; LSE-NEXT: .cfi_def_cfa_offset 32
; LSE-NEXT: str q0, [sp, #16] ; LSE-NEXT: str q0, [sp, #16]
; LSE-NEXT: ldp x9, x8, [sp, #16] ; LSE-NEXT: ldp x9, x8, [sp, #16]
; LSE-NEXT: .LBB3_1: // %atomicrmw.start ; LSE-NEXT: .LBB3_1: // %atomicrmw.start
; LSE-NEXT: // =>This Inner Loop Header: Depth=1 ; LSE-NEXT: // =>This Inner Loop Header: Depth=1
; LSE-NEXT: ldaxp x11, x10, [x0] ; LSE-NEXT: ldaxp x11, x10, [x0]
; LSE-NEXT: stlxp w12, x9, x8, [x0] ; LSE-NEXT: stlxp w12, x9, x8, [x0]
; LSE-NEXT: cbnz w12, .LBB3_1 ; LSE-NEXT: cbnz w12, .LBB3_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end ; LSE-NEXT: // %bb.2: // %atomicrmw.end
; LSE-NEXT: stp x11, x10, [sp] ; LSE-NEXT: stp x11, x10, [sp]
; LSE-NEXT: ldr q0, [sp], #32 ; LSE-NEXT: ldr q0, [sp], #32
; LSE-NEXT: ret ; LSE-NEXT: ret
%res = atomicrmw xchg fp128* %dst, fp128 %new seq_cst %res = atomicrmw xchg fp128* %dst, fp128 %new seq_cst
ret fp128 %res ret fp128 %res
} }

llvm/test/CodeGen/AArch64/branch-relax-bcc.ll

Show All 38 Linesbb1:
ret i32 0 ret i32 0
} }
declare i32 @foo() #0 declare i32 @foo() #0
define i32 @block_split(i32 %a, i32 %b) #0 { define i32 @block_split(i32 %a, i32 %b) #0 {
; CHECK-LABEL: block_split: ; CHECK-LABEL: block_split:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cmp w0, #5 ; =5 ; CHECK-NEXT: cmp w0, #5
; CHECK-NEXT: b.ne LBB1_1 ; CHECK-NEXT: b.ne LBB1_1
; CHECK-NEXT: b LBB1_2 ; CHECK-NEXT: b LBB1_2
; CHECK-NEXT: LBB1_1: ; %lor.lhs.false ; CHECK-NEXT: LBB1_1: ; %lor.lhs.false
; CHECK-NEXT: lsl w8, w1, #1 ; CHECK-NEXT: lsl w8, w1, #1
; CHECK-NEXT: cmp w1, #7 ; =7 ; CHECK-NEXT: cmp w1, #7
; CHECK-NEXT: csinc w8, w8, w1, lt ; CHECK-NEXT: csinc w8, w8, w1, lt
; CHECK-NEXT: cmp w8, #16 ; =16 ; CHECK-NEXT: cmp w8, #16
; CHECK-NEXT: b.le LBB1_2 ; CHECK-NEXT: b.le LBB1_2
; CHECK-NEXT: b LBB1_3 ; CHECK-NEXT: b LBB1_3
; CHECK-NEXT: LBB1_2: ; %if.then ; CHECK-NEXT: LBB1_2: ; %if.then
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: bl _foo ; CHECK-NEXT: bl _foo
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: LBB1_3: ; %if.end ; CHECK-NEXT: LBB1_3: ; %if.end
; CHECK-NEXT: mov w0, #7 ; CHECK-NEXT: mov w0, #7
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llvm/test/CodeGen/AArch64/branch-relax-cbz.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-cbz-offset-bits=3 < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-cbz-offset-bits=3 < %s | FileCheck %s
define void @split_block_no_fallthrough(i64 %val) #0 { define void @split_block_no_fallthrough(i64 %val) #0 {
; CHECK-LABEL: split_block_no_fallthrough: ; CHECK-LABEL: split_block_no_fallthrough:
; CHECK: ; %bb.0: ; %bb ; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: cmn x0, #5 ; =5 ; CHECK-NEXT: cmn x0, #5
; CHECK-NEXT: b.le LBB0_3 ; CHECK-NEXT: b.le LBB0_3
; CHECK-NEXT: ; %bb.1: ; %b3 ; CHECK-NEXT: ; %bb.1: ; %b3
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: cbnz w8, LBB0_2 ; CHECK-NEXT: cbnz w8, LBB0_2
; CHECK-NEXT: b LBB0_4 ; CHECK-NEXT: b LBB0_4
; CHECK-NEXT: LBB0_2: ; %common.ret ; CHECK-NEXT: LBB0_2: ; %common.ret
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
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llvm/test/CodeGen/AArch64/cgp-usubo.ll

Show All 32 Lines
; Constant operand should match. ; Constant operand should match.
define i1 @usubo_ugt_constant_op0_i8(i8 %x, i8* %p) nounwind { define i1 @usubo_ugt_constant_op0_i8(i8 %x, i8* %p) nounwind {
; CHECK-LABEL: usubo_ugt_constant_op0_i8: ; CHECK-LABEL: usubo_ugt_constant_op0_i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff ; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: mov w9, #42 ; CHECK-NEXT: mov w9, #42
; CHECK-NEXT: cmp w8, #42 // =42 ; CHECK-NEXT: cmp w8, #42
; CHECK-NEXT: sub w9, w9, w0 ; CHECK-NEXT: sub w9, w9, w0
; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: cset w0, hi
; CHECK-NEXT: strb w9, [x1] ; CHECK-NEXT: strb w9, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = sub i8 42, %x %s = sub i8 42, %x
%ov = icmp ugt i8 %x, 42 %ov = icmp ugt i8 %x, 42
store i8 %s, i8* %p store i8 %s, i8* %p
ret i1 %ov ret i1 %ov
} }
; Compare with constant operand 0 is canonicalized by commuting, but verify match for non-canonical form. ; Compare with constant operand 0 is canonicalized by commuting, but verify match for non-canonical form.
define i1 @usubo_ult_constant_op0_i16(i16 %x, i16* %p) nounwind { define i1 @usubo_ult_constant_op0_i16(i16 %x, i16* %p) nounwind {
; CHECK-LABEL: usubo_ult_constant_op0_i16: ; CHECK-LABEL: usubo_ult_constant_op0_i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff ; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: mov w9, #43 ; CHECK-NEXT: mov w9, #43
; CHECK-NEXT: cmp w8, #43 // =43 ; CHECK-NEXT: cmp w8, #43
; CHECK-NEXT: sub w9, w9, w0 ; CHECK-NEXT: sub w9, w9, w0
; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: cset w0, hi
; CHECK-NEXT: strh w9, [x1] ; CHECK-NEXT: strh w9, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = sub i16 43, %x %s = sub i16 43, %x
%ov = icmp ult i16 43, %x %ov = icmp ult i16 43, %x
store i16 %s, i16* %p store i16 %s, i16* %p
ret i1 %ov ret i1 %ov
} }
; Subtract with constant operand 1 is canonicalized to add. ; Subtract with constant operand 1 is canonicalized to add.
define i1 @usubo_ult_constant_op1_i16(i16 %x, i16* %p) nounwind { define i1 @usubo_ult_constant_op1_i16(i16 %x, i16* %p) nounwind {
; CHECK-LABEL: usubo_ult_constant_op1_i16: ; CHECK-LABEL: usubo_ult_constant_op1_i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff ; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: cmp w8, #44 // =44 ; CHECK-NEXT: cmp w8, #44
; CHECK-NEXT: sub w9, w0, #44 // =44 ; CHECK-NEXT: sub w9, w0, #44
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: strh w9, [x1] ; CHECK-NEXT: strh w9, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = add i16 %x, -44 %s = add i16 %x, -44
%ov = icmp ult i16 %x, 44 %ov = icmp ult i16 %x, 44
store i16 %s, i16* %p store i16 %s, i16* %p
ret i1 %ov ret i1 %ov
} }
define i1 @usubo_ugt_constant_op1_i8(i8 %x, i8* %p) nounwind { define i1 @usubo_ugt_constant_op1_i8(i8 %x, i8* %p) nounwind {
; CHECK-LABEL: usubo_ugt_constant_op1_i8: ; CHECK-LABEL: usubo_ugt_constant_op1_i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff ; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: cmp w8, #45 // =45 ; CHECK-NEXT: cmp w8, #45
; CHECK-NEXT: cset w8, lo ; CHECK-NEXT: cset w8, lo
; CHECK-NEXT: sub w9, w0, #45 // =45 ; CHECK-NEXT: sub w9, w0, #45
; CHECK-NEXT: mov w0, w8 ; CHECK-NEXT: mov w0, w8
; CHECK-NEXT: strb w9, [x1] ; CHECK-NEXT: strb w9, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ov = icmp ugt i8 45, %x %ov = icmp ugt i8 45, %x
%s = add i8 %x, -45 %s = add i8 %x, -45
store i8 %s, i8* %p store i8 %s, i8* %p
ret i1 %ov ret i1 %ov
} }
; Special-case: subtract 1 changes the compare predicate and constant. ; Special-case: subtract 1 changes the compare predicate and constant.
define i1 @usubo_eq_constant1_op1_i32(i32 %x, i32* %p) nounwind { define i1 @usubo_eq_constant1_op1_i32(i32 %x, i32* %p) nounwind {
; CHECK-LABEL: usubo_eq_constant1_op1_i32: ; CHECK-LABEL: usubo_eq_constant1_op1_i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: sub w8, w0, #1 // =1 ; CHECK-NEXT: sub w8, w0, #1
; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: str w8, [x1] ; CHECK-NEXT: str w8, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = add i32 %x, -1 %s = add i32 %x, -1
%ov = icmp eq i32 %x, 0 %ov = icmp eq i32 %x, 0
store i32 %s, i32* %p store i32 %s, i32* %p
ret i1 %ov ret i1 %ov
} }
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llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-gnu-linux -o - | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-gnu-linux -o - | FileCheck %s
; These tests make sure that the `cmp` instruction is rendered with an ; These tests make sure that the `cmp` instruction is rendered with an
; instruction that checks the sign bit of the original unextended data ; instruction that checks the sign bit of the original unextended data
; (%in) instead of the sign bit of the sign extended one that is ; (%in) instead of the sign bit of the sign extended one that is
; created by the type legalization process. ; created by the type legalization process.
; ;
; The tests are subdivided in tests that determine the sign bit ; The tests are subdivided in tests that determine the sign bit
; looking through a `sign_extend_inreg` and tests that determine the ; looking through a `sign_extend_inreg` and tests that determine the
; sign bit looking through a `sign_extend`. ; sign bit looking through a `sign_extend`.
define i32 @f_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind { define i32 @f_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind {
; CHECK-LABEL: f_i8_sign_extend_inreg: ; CHECK-LABEL: f_i8_sign_extend_inreg:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sxtb w8, w0 ; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: cmp w8, #0 // =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: csel w8, w1, w2, ge ; CHECK-NEXT: csel w8, w1, w2, ge
; CHECK-NEXT: add w0, w8, w0, uxtb ; CHECK-NEXT: add w0, w8, w0, uxtb
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i8 %in, -1 %cmp = icmp sgt i8 %in, -1
%ext = zext i8 %in to i32 %ext = zext i8 %in to i32
br i1 %cmp, label %A, label %B br i1 %cmp, label %A, label %B
A: A:
%retA = add i32 %ext, %a %retA = add i32 %ext, %a
ret i32 %retA ret i32 %retA
B: B:
%retB = add i32 %ext, %b %retB = add i32 %ext, %b
ret i32 %retB ret i32 %retB
} }
define i32 @f_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind { define i32 @f_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind {
; CHECK-LABEL: f_i16_sign_extend_inreg: ; CHECK-LABEL: f_i16_sign_extend_inreg:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sxth w8, w0 ; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: cmp w8, #0 // =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: csel w8, w1, w2, ge ; CHECK-NEXT: csel w8, w1, w2, ge
; CHECK-NEXT: add w0, w8, w0, uxth ; CHECK-NEXT: add w0, w8, w0, uxth
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i16 %in, -1 %cmp = icmp sgt i16 %in, -1
%ext = zext i16 %in to i32 %ext = zext i16 %in to i32
br i1 %cmp, label %A, label %B br i1 %cmp, label %A, label %B
A: A:
%retA = add i32 %ext, %a %retA = add i32 %ext, %a
ret i32 %retA ret i32 %retA
B: B:
%retB = add i32 %ext, %b %retB = add i32 %ext, %b
ret i32 %retB ret i32 %retB
} }
define i64 @f_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind { define i64 @f_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind {
; CHECK-LABEL: f_i32_sign_extend_inreg: ; CHECK-LABEL: f_i32_sign_extend_inreg:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel x8, x1, x2, ge ; CHECK-NEXT: csel x8, x1, x2, ge
; CHECK-NEXT: add x0, x8, w0, uxtw ; CHECK-NEXT: add x0, x8, w0, uxtw
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i32 %in, -1 %cmp = icmp sgt i32 %in, -1
%ext = zext i32 %in to i64 %ext = zext i32 %in to i64
br i1 %cmp, label %A, label %B br i1 %cmp, label %A, label %B
A: A:
%retA = add i64 %ext, %a %retA = add i64 %ext, %a
ret i64 %retA ret i64 %retA
B: B:
%retB = add i64 %ext, %b %retB = add i64 %ext, %b
ret i64 %retB ret i64 %retB
} }
define i32 @g_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind { define i32 @g_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind {
; CHECK-LABEL: g_i8_sign_extend_inreg: ; CHECK-LABEL: g_i8_sign_extend_inreg:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sxtb w8, w0 ; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: cmp w8, #0 // =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: csel w8, w1, w2, lt ; CHECK-NEXT: csel w8, w1, w2, lt
; CHECK-NEXT: add w0, w8, w0, uxtb ; CHECK-NEXT: add w0, w8, w0, uxtb
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp slt i8 %in, 0 %cmp = icmp slt i8 %in, 0
%ext = zext i8 %in to i32 %ext = zext i8 %in to i32
br i1 %cmp, label %A, label %B br i1 %cmp, label %A, label %B
A: A:
%retA = add i32 %ext, %a %retA = add i32 %ext, %a
ret i32 %retA ret i32 %retA
B: B:
%retB = add i32 %ext, %b %retB = add i32 %ext, %b
ret i32 %retB ret i32 %retB
} }
define i32 @g_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind { define i32 @g_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind {
; CHECK-LABEL: g_i16_sign_extend_inreg: ; CHECK-LABEL: g_i16_sign_extend_inreg:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sxth w8, w0 ; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: cmp w8, #0 // =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: csel w8, w1, w2, lt ; CHECK-NEXT: csel w8, w1, w2, lt
; CHECK-NEXT: add w0, w8, w0, uxth ; CHECK-NEXT: add w0, w8, w0, uxth
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp slt i16 %in, 0 %cmp = icmp slt i16 %in, 0
%ext = zext i16 %in to i32 %ext = zext i16 %in to i32
br i1 %cmp, label %A, label %B br i1 %cmp, label %A, label %B
A: A:
%retA = add i32 %ext, %a %retA = add i32 %ext, %a
ret i32 %retA ret i32 %retA
B: B:
%retB = add i32 %ext, %b %retB = add i32 %ext, %b
ret i32 %retB ret i32 %retB
} }
define i64 @g_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind { define i64 @g_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind {
; CHECK-LABEL: g_i32_sign_extend_inreg: ; CHECK-LABEL: g_i32_sign_extend_inreg:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel x8, x1, x2, lt ; CHECK-NEXT: csel x8, x1, x2, lt
; CHECK-NEXT: add x0, x8, w0, uxtw ; CHECK-NEXT: add x0, x8, w0, uxtw
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp slt i32 %in, 0 %cmp = icmp slt i32 %in, 0
%ext = zext i32 %in to i64 %ext = zext i32 %in to i64
br i1 %cmp, label %A, label %B br i1 %cmp, label %A, label %B
A: A:
%retA = add i64 %ext, %a %retA = add i64 %ext, %a
ret i64 %retA ret i64 %retA
B: B:
%retB = add i64 %ext, %b %retB = add i64 %ext, %b
ret i64 %retB ret i64 %retB
} }
define i64 @f_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind { define i64 @f_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind {
; CHECK-LABEL: f_i32_sign_extend_i64: ; CHECK-LABEL: f_i32_sign_extend_i64:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 ; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0 ; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: cmp x8, #0 // =0 ; CHECK-NEXT: cmp x8, #0
; CHECK-NEXT: csel x8, x1, x2, ge ; CHECK-NEXT: csel x8, x1, x2, ge
; CHECK-NEXT: add x0, x8, w0, uxtw ; CHECK-NEXT: add x0, x8, w0, uxtw
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%inext = sext i32 %in to i64 %inext = sext i32 %in to i64
%cmp = icmp sgt i64 %inext, -1 %cmp = icmp sgt i64 %inext, -1
%ext = zext i32 %in to i64 %ext = zext i32 %in to i64
br i1 %cmp, label %A, label %B br i1 %cmp, label %A, label %B
A: A:
%retA = add i64 %ext, %a %retA = add i64 %ext, %a
ret i64 %retA ret i64 %retA
B: B:
%retB = add i64 %ext, %b %retB = add i64 %ext, %b
ret i64 %retB ret i64 %retB
} }
define i64 @g_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind { define i64 @g_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind {
; CHECK-LABEL: g_i32_sign_extend_i64: ; CHECK-LABEL: g_i32_sign_extend_i64:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 ; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0 ; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: cmp x8, #0 // =0 ; CHECK-NEXT: cmp x8, #0
; CHECK-NEXT: csel x8, x1, x2, lt ; CHECK-NEXT: csel x8, x1, x2, lt
; CHECK-NEXT: add x0, x8, w0, uxtw ; CHECK-NEXT: add x0, x8, w0, uxtw
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%inext = sext i32 %in to i64 %inext = sext i32 %in to i64
%cmp = icmp slt i64 %inext, 0 %cmp = icmp slt i64 %inext, 0
%ext = zext i32 %in to i64 %ext = zext i32 %in to i64
br i1 %cmp, label %A, label %B br i1 %cmp, label %A, label %B
Show All 9 Lines

llvm/test/CodeGen/AArch64/cmp-select-sign.ll

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%res = select i1 %c, i64 1, i64 -1 %res = select i1 %c, i64 1, i64 -1
ret i64 %res ret i64 %res
} }
define i64 @not_sign_i64(i64 %a) { define i64 @not_sign_i64(i64 %a) {
; CHECK-LABEL: not_sign_i64: ; CHECK-LABEL: not_sign_i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp x0, #0 // =0 ; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: cneg x0, x8, le ; CHECK-NEXT: cneg x0, x8, le
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt i64 %a, 0 %c = icmp sgt i64 %a, 0
%res = select i1 %c, i64 1, i64 -1 %res = select i1 %c, i64 1, i64 -1
ret i64 %res ret i64 %res
} }
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%c = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1> %c = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
%res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> %res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
ret <4 x i32> %res ret <4 x i32> %res
} }
define <4 x i32> @sign_4xi32_multi_use(<4 x i32> %a) { define <4 x i32> @sign_4xi32_multi_use(<4 x i32> %a) {
; CHECK-LABEL: sign_4xi32_multi_use: ; CHECK-LABEL: sign_4xi32_multi_use:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT: sshr v2.4s, v0.4s, #31 ; CHECK-NEXT: sshr v2.4s, v0.4s, #31
; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s ; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s
; CHECK-NEXT: orr v2.4s, #1 ; CHECK-NEXT: orr v2.4s, #1
; CHECK-NEXT: xtn v0.4h, v0.4s ; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: str q2, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q2, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl use_4xi1 ; CHECK-NEXT: bl use_4xi1
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1> %c = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
%res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> %res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
call void @use_4xi1(<4 x i1> %c) call void @use_4xi1(<4 x i1> %c)
ret <4 x i32> %res ret <4 x i32> %res
} }
; Second icmp operand breaks sign pattern. ; Second icmp operand breaks sign pattern.
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llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -debugify-and-strip-all-safe < %s -mtriple=aarch64-linux-gnu | FileCheck %s ; RUN: llc -debugify-and-strip-all-safe < %s -mtriple=aarch64-linux-gnu | FileCheck %s
; marked as external to prevent possible optimizations ; marked as external to prevent possible optimizations
@a = external global i32 @a = external global i32
@b = external global i32 @b = external global i32
@c = external global i32 @c = external global i32
@d = external global i32 @d = external global i32
; (a > 10 && b == c) || (a >= 10 && b == d) ; (a > 10 && b == c) || (a >= 10 && b == d)
define i32 @combine_gt_ge_10() #0 { define i32 @combine_gt_ge_10() #0 {
; CHECK-LABEL: combine_gt_ge_10: ; CHECK-LABEL: combine_gt_ge_10:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:a ; CHECK-NEXT: adrp x8, :got:a
; CHECK-NEXT: ldr x8, [x8, :got_lo12:a] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:a]
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: cmp w8, #10 // =10 ; CHECK-NEXT: cmp w8, #10
; CHECK-NEXT: adrp x8, :got:b ; CHECK-NEXT: adrp x8, :got:b
; CHECK-NEXT: ldr x8, [x8, :got_lo12:b] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:b]
; CHECK-NEXT: b.le .LBB0_3 ; CHECK-NEXT: b.le .LBB0_3
; CHECK-NEXT: // %bb.1: // %land.lhs.true ; CHECK-NEXT: // %bb.1: // %land.lhs.true
; CHECK-NEXT: adrp x10, :got:c ; CHECK-NEXT: adrp x10, :got:c
; CHECK-NEXT: ldr w9, [x8] ; CHECK-NEXT: ldr w9, [x8]
; CHECK-NEXT: ldr x10, [x10, :got_lo12:c] ; CHECK-NEXT: ldr x10, [x10, :got_lo12:c]
; CHECK-NEXT: ldr w10, [x10] ; CHECK-NEXT: ldr w10, [x10]
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; (a > 5 && b == c) || (a < 5 && b == d) ; (a > 5 && b == c) || (a < 5 && b == d)
define i32 @combine_gt_lt_5() #0 { define i32 @combine_gt_lt_5() #0 {
; CHECK-LABEL: combine_gt_lt_5: ; CHECK-LABEL: combine_gt_lt_5:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:a ; CHECK-NEXT: adrp x8, :got:a
; CHECK-NEXT: ldr x8, [x8, :got_lo12:a] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:a]
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: cmp w8, #5 // =5 ; CHECK-NEXT: cmp w8, #5
; CHECK-NEXT: b.le .LBB1_3 ; CHECK-NEXT: b.le .LBB1_3
; CHECK-NEXT: // %bb.1: // %land.lhs.true ; CHECK-NEXT: // %bb.1: // %land.lhs.true
; CHECK-NEXT: adrp x8, :got:b ; CHECK-NEXT: adrp x8, :got:b
; CHECK-NEXT: adrp x9, :got:c ; CHECK-NEXT: adrp x9, :got:c
; CHECK-NEXT: ldr x8, [x8, :got_lo12:b] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:b]
; CHECK-NEXT: ldr x9, [x9, :got_lo12:c] ; CHECK-NEXT: ldr x9, [x9, :got_lo12:c]
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: ldr w9, [x9] ; CHECK-NEXT: ldr w9, [x9]
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; (a < 5 && b == c) || (a <= 5 && b == d) ; (a < 5 && b == c) || (a <= 5 && b == d)
define i32 @combine_lt_ge_5() #0 { define i32 @combine_lt_ge_5() #0 {
; CHECK-LABEL: combine_lt_ge_5: ; CHECK-LABEL: combine_lt_ge_5:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:a ; CHECK-NEXT: adrp x8, :got:a
; CHECK-NEXT: ldr x8, [x8, :got_lo12:a] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:a]
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: cmp w8, #5 // =5 ; CHECK-NEXT: cmp w8, #5
; CHECK-NEXT: adrp x8, :got:b ; CHECK-NEXT: adrp x8, :got:b
; CHECK-NEXT: ldr x8, [x8, :got_lo12:b] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:b]
; CHECK-NEXT: b.ge .LBB2_3 ; CHECK-NEXT: b.ge .LBB2_3
; CHECK-NEXT: // %bb.1: // %land.lhs.true ; CHECK-NEXT: // %bb.1: // %land.lhs.true
; CHECK-NEXT: adrp x10, :got:c ; CHECK-NEXT: adrp x10, :got:c
; CHECK-NEXT: ldr w9, [x8] ; CHECK-NEXT: ldr w9, [x8]
; CHECK-NEXT: ldr x10, [x10, :got_lo12:c] ; CHECK-NEXT: ldr x10, [x10, :got_lo12:c]
; CHECK-NEXT: ldr w10, [x10] ; CHECK-NEXT: ldr w10, [x10]
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; (a < 5 && b == c) || (a > 5 && b == d) ; (a < 5 && b == c) || (a > 5 && b == d)
define i32 @combine_lt_gt_5() #0 { define i32 @combine_lt_gt_5() #0 {
; CHECK-LABEL: combine_lt_gt_5: ; CHECK-LABEL: combine_lt_gt_5:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:a ; CHECK-NEXT: adrp x8, :got:a
; CHECK-NEXT: ldr x8, [x8, :got_lo12:a] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:a]
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: cmp w8, #5 // =5 ; CHECK-NEXT: cmp w8, #5
; CHECK-NEXT: b.ge .LBB3_3 ; CHECK-NEXT: b.ge .LBB3_3
; CHECK-NEXT: // %bb.1: // %land.lhs.true ; CHECK-NEXT: // %bb.1: // %land.lhs.true
; CHECK-NEXT: adrp x8, :got:b ; CHECK-NEXT: adrp x8, :got:b
; CHECK-NEXT: adrp x9, :got:c ; CHECK-NEXT: adrp x9, :got:c
; CHECK-NEXT: ldr x8, [x8, :got_lo12:b] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:b]
; CHECK-NEXT: ldr x9, [x9, :got_lo12:c] ; CHECK-NEXT: ldr x9, [x9, :got_lo12:c]
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: ldr w9, [x9] ; CHECK-NEXT: ldr w9, [x9]
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; (a > -5 && b == c) || (a < -5 && b == d) ; (a > -5 && b == c) || (a < -5 && b == d)
define i32 @combine_gt_lt_n5() #0 { define i32 @combine_gt_lt_n5() #0 {
; CHECK-LABEL: combine_gt_lt_n5: ; CHECK-LABEL: combine_gt_lt_n5:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:a ; CHECK-NEXT: adrp x8, :got:a
; CHECK-NEXT: ldr x8, [x8, :got_lo12:a] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:a]
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: cmn w8, #5 // =5 ; CHECK-NEXT: cmn w8, #5
; CHECK-NEXT: b.le .LBB4_3 ; CHECK-NEXT: b.le .LBB4_3
; CHECK-NEXT: // %bb.1: // %land.lhs.true ; CHECK-NEXT: // %bb.1: // %land.lhs.true
; CHECK-NEXT: adrp x8, :got:b ; CHECK-NEXT: adrp x8, :got:b
; CHECK-NEXT: adrp x9, :got:c ; CHECK-NEXT: adrp x9, :got:c
; CHECK-NEXT: ldr x8, [x8, :got_lo12:b] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:b]
; CHECK-NEXT: ldr x9, [x9, :got_lo12:c] ; CHECK-NEXT: ldr x9, [x9, :got_lo12:c]
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: ldr w9, [x9] ; CHECK-NEXT: ldr w9, [x9]
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; (a < -5 && b == c) || (a > -5 && b == d) ; (a < -5 && b == c) || (a > -5 && b == d)
define i32 @combine_lt_gt_n5() #0 { define i32 @combine_lt_gt_n5() #0 {
; CHECK-LABEL: combine_lt_gt_n5: ; CHECK-LABEL: combine_lt_gt_n5:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:a ; CHECK-NEXT: adrp x8, :got:a
; CHECK-NEXT: ldr x8, [x8, :got_lo12:a] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:a]
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: cmn w8, #5 // =5 ; CHECK-NEXT: cmn w8, #5
; CHECK-NEXT: b.ge .LBB5_3 ; CHECK-NEXT: b.ge .LBB5_3
; CHECK-NEXT: // %bb.1: // %land.lhs.true ; CHECK-NEXT: // %bb.1: // %land.lhs.true
; CHECK-NEXT: adrp x8, :got:b ; CHECK-NEXT: adrp x8, :got:b
; CHECK-NEXT: adrp x9, :got:c ; CHECK-NEXT: adrp x9, :got:c
; CHECK-NEXT: ldr x8, [x8, :got_lo12:b] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:b]
; CHECK-NEXT: ldr x9, [x9, :got_lo12:c] ; CHECK-NEXT: ldr x9, [x9, :got_lo12:c]
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: ldr w9, [x9] ; CHECK-NEXT: ldr w9, [x9]
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; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w21, -24 ; CHECK-NEXT: .cfi_offset w21, -24
; CHECK-NEXT: .cfi_offset w22, -32 ; CHECK-NEXT: .cfi_offset w22, -32
; CHECK-NEXT: .cfi_offset w30, -48 ; CHECK-NEXT: .cfi_offset w30, -48
; CHECK-NEXT: ldr x19, [x0] ; CHECK-NEXT: ldr x19, [x0]
; CHECK-NEXT: mov w20, #24 ; CHECK-NEXT: mov w20, #24
; CHECK-NEXT: adrp x22, glob ; CHECK-NEXT: adrp x22, glob
; CHECK-NEXT: add x21, x19, #2 // =2 ; CHECK-NEXT: add x21, x19, #2
; CHECK-NEXT: .LBB6_1: // %land.rhs ; CHECK-NEXT: .LBB6_1: // %land.rhs
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr x8, [x20] ; CHECK-NEXT: ldr x8, [x20]
; CHECK-NEXT: cmp x8, #1 // =1 ; CHECK-NEXT: cmp x8, #1
; CHECK-NEXT: b.lt .LBB6_3 ; CHECK-NEXT: b.lt .LBB6_3
; CHECK-NEXT: // %bb.2: // %while.body ; CHECK-NEXT: // %bb.2: // %while.body
; CHECK-NEXT: // in Loop: Header=BB6_1 Depth=1 ; CHECK-NEXT: // in Loop: Header=BB6_1 Depth=1
; CHECK-NEXT: ldr x0, [x22, :lo12:glob] ; CHECK-NEXT: ldr x0, [x22, :lo12:glob]
; CHECK-NEXT: bl Update ; CHECK-NEXT: bl Update
; CHECK-NEXT: sub x21, x21, #2 // =2 ; CHECK-NEXT: sub x21, x21, #2
; CHECK-NEXT: cmp x19, x21 ; CHECK-NEXT: cmp x19, x21
; CHECK-NEXT: b.lt .LBB6_1 ; CHECK-NEXT: b.lt .LBB6_1
; CHECK-NEXT: .LBB6_3: // %while.end ; CHECK-NEXT: .LBB6_3: // %while.end
; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp], #48 // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp], #48 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 28 Lines
; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w30, -32 ; CHECK-NEXT: .cfi_offset w30, -32
; CHECK-NEXT: adrp x19, :got:a ; CHECK-NEXT: adrp x19, :got:a
; CHECK-NEXT: ldr x19, [x19, :got_lo12:a] ; CHECK-NEXT: ldr x19, [x19, :got_lo12:a]
; CHECK-NEXT: ldr w8, [x19] ; CHECK-NEXT: ldr w8, [x19]
; CHECK-NEXT: cmn w8, #2 // =2 ; CHECK-NEXT: cmn w8, #2
; CHECK-NEXT: b.gt .LBB7_4 ; CHECK-NEXT: b.gt .LBB7_4
; CHECK-NEXT: // %bb.1: // %while.body.preheader ; CHECK-NEXT: // %bb.1: // %while.body.preheader
; CHECK-NEXT: sub w20, w8, #1 // =1 ; CHECK-NEXT: sub w20, w8, #1
; CHECK-NEXT: .LBB7_2: // %while.body ; CHECK-NEXT: .LBB7_2: // %while.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: bl do_something ; CHECK-NEXT: bl do_something
; CHECK-NEXT: adds w20, w20, #1 // =1 ; CHECK-NEXT: adds w20, w20, #1
; CHECK-NEXT: b.mi .LBB7_2 ; CHECK-NEXT: b.mi .LBB7_2
; CHECK-NEXT: // %bb.3: // %while.cond.while.end_crit_edge ; CHECK-NEXT: // %bb.3: // %while.cond.while.end_crit_edge
; CHECK-NEXT: ldr w8, [x19] ; CHECK-NEXT: ldr w8, [x19]
; CHECK-NEXT: .LBB7_4: // %while.end ; CHECK-NEXT: .LBB7_4: // %while.end
; CHECK-NEXT: cmp w8, #1 // =1 ; CHECK-NEXT: cmp w8, #1
; CHECK-NEXT: b.gt .LBB7_7 ; CHECK-NEXT: b.gt .LBB7_7
; CHECK-NEXT: // %bb.5: // %land.lhs.true ; CHECK-NEXT: // %bb.5: // %land.lhs.true
; CHECK-NEXT: adrp x8, :got:b ; CHECK-NEXT: adrp x8, :got:b
; CHECK-NEXT: adrp x9, :got:d ; CHECK-NEXT: adrp x9, :got:d
; CHECK-NEXT: ldr x8, [x8, :got_lo12:b] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:b]
; CHECK-NEXT: ldr x9, [x9, :got_lo12:d] ; CHECK-NEXT: ldr x9, [x9, :got_lo12:d]
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: ldr w9, [x9] ; CHECK-NEXT: ldr w9, [x9]
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; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: adrp x8, :got:a ; CHECK-NEXT: adrp x8, :got:a
; CHECK-NEXT: ldr x8, [x8, :got_lo12:a] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:a]
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: cmp w8, #0 // =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: b.gt .LBB8_3 ; CHECK-NEXT: b.gt .LBB8_3
; CHECK-NEXT: // %bb.1: // %while.body.preheader ; CHECK-NEXT: // %bb.1: // %while.body.preheader
; CHECK-NEXT: sub w19, w8, #1 // =1 ; CHECK-NEXT: sub w19, w8, #1
; CHECK-NEXT: .LBB8_2: // %while.body ; CHECK-NEXT: .LBB8_2: // %while.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: bl do_something ; CHECK-NEXT: bl do_something
; CHECK-NEXT: adds w19, w19, #1 // =1 ; CHECK-NEXT: adds w19, w19, #1
; CHECK-NEXT: b.mi .LBB8_2 ; CHECK-NEXT: b.mi .LBB8_2
; CHECK-NEXT: .LBB8_3: // %while.end ; CHECK-NEXT: .LBB8_3: // %while.end
; CHECK-NEXT: adrp x8, :got:c ; CHECK-NEXT: adrp x8, :got:c
; CHECK-NEXT: ldr x8, [x8, :got_lo12:c] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:c]
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: cmn w8, #2 // =2 ; CHECK-NEXT: cmn w8, #2
; CHECK-NEXT: b.lt .LBB8_6 ; CHECK-NEXT: b.lt .LBB8_6
; CHECK-NEXT: // %bb.4: // %land.lhs.true ; CHECK-NEXT: // %bb.4: // %land.lhs.true
; CHECK-NEXT: adrp x8, :got:b ; CHECK-NEXT: adrp x8, :got:b
; CHECK-NEXT: adrp x9, :got:d ; CHECK-NEXT: adrp x9, :got:d
; CHECK-NEXT: ldr x8, [x8, :got_lo12:b] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:b]
; CHECK-NEXT: ldr x9, [x9, :got_lo12:d] ; CHECK-NEXT: ldr x9, [x9, :got_lo12:d]
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: ldr w9, [x9] ; CHECK-NEXT: ldr w9, [x9]
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; CHECK-LABEL: fcmpri: ; CHECK-LABEL: fcmpri:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill ; CHECK-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
; CHECK-NEXT: stp x30, x19, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x19, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: .cfi_offset b8, -32 ; CHECK-NEXT: .cfi_offset b8, -32
; CHECK-NEXT: cmp w0, #2 // =2 ; CHECK-NEXT: cmp w0, #2
; CHECK-NEXT: b.lt .LBB9_3 ; CHECK-NEXT: b.lt .LBB9_3
; CHECK-NEXT: // %bb.1: // %land.lhs.true ; CHECK-NEXT: // %bb.1: // %land.lhs.true
; CHECK-NEXT: ldr x8, [x1, #8] ; CHECK-NEXT: ldr x8, [x1, #8]
; CHECK-NEXT: cbz x8, .LBB9_3 ; CHECK-NEXT: cbz x8, .LBB9_3
; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: // %bb.2:
; CHECK-NEXT: mov w0, #3 ; CHECK-NEXT: mov w0, #3
; CHECK-NEXT: b .LBB9_4 ; CHECK-NEXT: b .LBB9_4
; CHECK-NEXT: .LBB9_3: // %if.end ; CHECK-NEXT: .LBB9_3: // %if.end
; CHECK-NEXT: mov w0, #1 ; CHECK-NEXT: mov w0, #1
; CHECK-NEXT: bl zoo ; CHECK-NEXT: bl zoo
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: mov w0, #-1 ; CHECK-NEXT: mov w0, #-1
; CHECK-NEXT: bl yoo ; CHECK-NEXT: bl yoo
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: cinc w0, w19, gt ; CHECK-NEXT: cinc w0, w19, gt
; CHECK-NEXT: mov w1, #2 ; CHECK-NEXT: mov w1, #2
; CHECK-NEXT: mov v8.16b, v0.16b ; CHECK-NEXT: mov v8.16b, v0.16b
; CHECK-NEXT: bl xoo ; CHECK-NEXT: bl xoo
; CHECK-NEXT: fmov d0, #-1.00000000 ; CHECK-NEXT: fmov d0, #-1.00000000
; CHECK-NEXT: fadd d0, d8, d0 ; CHECK-NEXT: fadd d0, d8, d0
; CHECK-NEXT: fcmp d8, #0.0 ; CHECK-NEXT: fcmp d8, #0.0
; CHECK-NEXT: fcsel d0, d8, d0, gt ; CHECK-NEXT: fcsel d0, d8, d0, gt
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} }
define void @cmp_shifted(i32 %in, i32 %lhs, i32 %rhs) { define void @cmp_shifted(i32 %in, i32 %lhs, i32 %rhs) {
; CHECK-LABEL: cmp_shifted: ; CHECK-LABEL: cmp_shifted:
; CHECK: // %bb.0: // %common.ret ; CHECK: // %bb.0: // %common.ret
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w8, #42 ; CHECK-NEXT: mov w8, #42
; CHECK-NEXT: csinc w8, w8, wzr, gt ; CHECK-NEXT: csinc w8, w8, wzr, gt
; CHECK-NEXT: cmp w0, #2, lsl #12 // =8192 ; CHECK-NEXT: cmp w0, #2, lsl #12 // =8192
; CHECK-NEXT: mov w9, #128 ; CHECK-NEXT: mov w9, #128
; CHECK-NEXT: csel w0, w9, w8, ge ; CHECK-NEXT: csel w0, w9, w8, ge
; CHECK-NEXT: bl zoo ; CHECK-NEXT: bl zoo
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
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} }
define i32 @combine_gt_ge_sel(i64 %v, i64* %p) #0 { define i32 @combine_gt_ge_sel(i64 %v, i64* %p) #0 {
; CHECK-LABEL: combine_gt_ge_sel: ; CHECK-LABEL: combine_gt_ge_sel:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:a ; CHECK-NEXT: adrp x8, :got:a
; CHECK-NEXT: ldr x8, [x8, :got_lo12:a] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:a]
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: cmp w8, #0 // =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: csel x9, x0, xzr, gt ; CHECK-NEXT: csel x9, x0, xzr, gt
; CHECK-NEXT: str x9, [x1] ; CHECK-NEXT: str x9, [x1]
; CHECK-NEXT: b.le .LBB11_2 ; CHECK-NEXT: b.le .LBB11_2
; CHECK-NEXT: // %bb.1: // %lor.lhs.false ; CHECK-NEXT: // %bb.1: // %lor.lhs.false
; CHECK-NEXT: cmp w8, #2 // =2 ; CHECK-NEXT: cmp w8, #2
; CHECK-NEXT: b.ge .LBB11_4 ; CHECK-NEXT: b.ge .LBB11_4
; CHECK-NEXT: b .LBB11_6 ; CHECK-NEXT: b .LBB11_6
; CHECK-NEXT: .LBB11_2: // %land.lhs.true ; CHECK-NEXT: .LBB11_2: // %land.lhs.true
; CHECK-NEXT: adrp x8, :got:b ; CHECK-NEXT: adrp x8, :got:b
; CHECK-NEXT: adrp x9, :got:c ; CHECK-NEXT: adrp x9, :got:c
; CHECK-NEXT: ldr x8, [x8, :got_lo12:b] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:b]
; CHECK-NEXT: ldr x9, [x9, :got_lo12:c] ; CHECK-NEXT: ldr x9, [x9, :got_lo12:c]
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
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llvm/test/CodeGen/AArch64/extract-bits.ll

Show All 18 Lines
; ---------------------------------------------------------------------------- ; ; ---------------------------------------------------------------------------- ;
define i32 @bextr32_a0(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind { define i32 @bextr32_a0(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; CHECK-LABEL: bextr32_a0: ; CHECK-LABEL: bextr32_a0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w2 ; CHECK-NEXT: lsl w9, w9, w2
; CHECK-NEXT: lsr w8, w0, w1 ; CHECK-NEXT: lsr w8, w0, w1
; CHECK-NEXT: sub w9, w9, #1 // =1 ; CHECK-NEXT: sub w9, w9, #1
; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: and w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shifted = lshr i32 %val, %numskipbits %shifted = lshr i32 %val, %numskipbits
%onebit = shl i32 1, %numlowbits %onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1 %mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %shifted %masked = and i32 %mask, %shifted
ret i32 %masked ret i32 %masked
} }
define i32 @bextr32_a0_arithmetic(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind { define i32 @bextr32_a0_arithmetic(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; CHECK-LABEL: bextr32_a0_arithmetic: ; CHECK-LABEL: bextr32_a0_arithmetic:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w2 ; CHECK-NEXT: lsl w9, w9, w2
; CHECK-NEXT: asr w8, w0, w1 ; CHECK-NEXT: asr w8, w0, w1
; CHECK-NEXT: sub w9, w9, #1 // =1 ; CHECK-NEXT: sub w9, w9, #1
; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: and w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shifted = ashr i32 %val, %numskipbits %shifted = ashr i32 %val, %numskipbits
%onebit = shl i32 1, %numlowbits %onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1 %mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %shifted %masked = and i32 %mask, %shifted
ret i32 %masked ret i32 %masked
} }
define i32 @bextr32_a1_indexzext(i32 %val, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind { define i32 @bextr32_a1_indexzext(i32 %val, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bextr32_a1_indexzext: ; CHECK-LABEL: bextr32_a1_indexzext:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w2 ; CHECK-NEXT: lsl w9, w9, w2
; CHECK-NEXT: lsr w8, w0, w1 ; CHECK-NEXT: lsr w8, w0, w1
; CHECK-NEXT: sub w9, w9, #1 // =1 ; CHECK-NEXT: sub w9, w9, #1
; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: and w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%skip = zext i8 %numskipbits to i32 %skip = zext i8 %numskipbits to i32
%shifted = lshr i32 %val, %skip %shifted = lshr i32 %val, %skip
%conv = zext i8 %numlowbits to i32 %conv = zext i8 %numlowbits to i32
%onebit = shl i32 1, %conv %onebit = shl i32 1, %conv
%mask = add nsw i32 %onebit, -1 %mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %shifted %masked = and i32 %mask, %shifted
ret i32 %masked ret i32 %masked
} }
define i32 @bextr32_a2_load(i32* %w, i32 %numskipbits, i32 %numlowbits) nounwind { define i32 @bextr32_a2_load(i32* %w, i32 %numskipbits, i32 %numlowbits) nounwind {
; CHECK-LABEL: bextr32_a2_load: ; CHECK-LABEL: bextr32_a2_load:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0] ; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w2 ; CHECK-NEXT: lsl w9, w9, w2
; CHECK-NEXT: sub w9, w9, #1 // =1 ; CHECK-NEXT: sub w9, w9, #1
; CHECK-NEXT: lsr w8, w8, w1 ; CHECK-NEXT: lsr w8, w8, w1
; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: and w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val = load i32, i32* %w %val = load i32, i32* %w
%shifted = lshr i32 %val, %numskipbits %shifted = lshr i32 %val, %numskipbits
%onebit = shl i32 1, %numlowbits %onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1 %mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %shifted %masked = and i32 %mask, %shifted
ret i32 %masked ret i32 %masked
} }
define i32 @bextr32_a3_load_indexzext(i32* %w, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind { define i32 @bextr32_a3_load_indexzext(i32* %w, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bextr32_a3_load_indexzext: ; CHECK-LABEL: bextr32_a3_load_indexzext:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0] ; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w2 ; CHECK-NEXT: lsl w9, w9, w2
; CHECK-NEXT: sub w9, w9, #1 // =1 ; CHECK-NEXT: sub w9, w9, #1
; CHECK-NEXT: lsr w8, w8, w1 ; CHECK-NEXT: lsr w8, w8, w1
; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: and w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val = load i32, i32* %w %val = load i32, i32* %w
%skip = zext i8 %numskipbits to i32 %skip = zext i8 %numskipbits to i32
%shifted = lshr i32 %val, %skip %shifted = lshr i32 %val, %skip
%conv = zext i8 %numlowbits to i32 %conv = zext i8 %numlowbits to i32
%onebit = shl i32 1, %conv %onebit = shl i32 1, %conv
%mask = add nsw i32 %onebit, -1 %mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %shifted %masked = and i32 %mask, %shifted
ret i32 %masked ret i32 %masked
} }
define i32 @bextr32_a4_commutative(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind { define i32 @bextr32_a4_commutative(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; CHECK-LABEL: bextr32_a4_commutative: ; CHECK-LABEL: bextr32_a4_commutative:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w2 ; CHECK-NEXT: lsl w9, w9, w2
; CHECK-NEXT: lsr w8, w0, w1 ; CHECK-NEXT: lsr w8, w0, w1
; CHECK-NEXT: sub w9, w9, #1 // =1 ; CHECK-NEXT: sub w9, w9, #1
; CHECK-NEXT: and w0, w8, w9 ; CHECK-NEXT: and w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shifted = lshr i32 %val, %numskipbits %shifted = lshr i32 %val, %numskipbits
%onebit = shl i32 1, %numlowbits %onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1 %mask = add nsw i32 %onebit, -1
%masked = and i32 %shifted, %mask ; swapped order %masked = and i32 %shifted, %mask ; swapped order
ret i32 %masked ret i32 %masked
} }
; 64-bit ; 64-bit
define i64 @bextr64_a0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind { define i64 @bextr64_a0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; CHECK-LABEL: bextr64_a0: ; CHECK-LABEL: bextr64_a0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl x9, x9, x2 ; CHECK-NEXT: lsl x9, x9, x2
; CHECK-NEXT: lsr x8, x0, x1 ; CHECK-NEXT: lsr x8, x0, x1
; CHECK-NEXT: sub x9, x9, #1 // =1 ; CHECK-NEXT: sub x9, x9, #1
; CHECK-NEXT: and x0, x9, x8 ; CHECK-NEXT: and x0, x9, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shifted = lshr i64 %val, %numskipbits %shifted = lshr i64 %val, %numskipbits
%onebit = shl i64 1, %numlowbits %onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1 %mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %shifted %masked = and i64 %mask, %shifted
ret i64 %masked ret i64 %masked
} }
define i64 @bextr64_a0_arithmetic(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind { define i64 @bextr64_a0_arithmetic(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; CHECK-LABEL: bextr64_a0_arithmetic: ; CHECK-LABEL: bextr64_a0_arithmetic:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl x9, x9, x2 ; CHECK-NEXT: lsl x9, x9, x2
; CHECK-NEXT: asr x8, x0, x1 ; CHECK-NEXT: asr x8, x0, x1
; CHECK-NEXT: sub x9, x9, #1 // =1 ; CHECK-NEXT: sub x9, x9, #1
; CHECK-NEXT: and x0, x9, x8 ; CHECK-NEXT: and x0, x9, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shifted = ashr i64 %val, %numskipbits %shifted = ashr i64 %val, %numskipbits
%onebit = shl i64 1, %numlowbits %onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1 %mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %shifted %masked = and i64 %mask, %shifted
ret i64 %masked ret i64 %masked
} }
define i64 @bextr64_a1_indexzext(i64 %val, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind { define i64 @bextr64_a1_indexzext(i64 %val, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bextr64_a1_indexzext: ; CHECK-LABEL: bextr64_a1_indexzext:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2 ; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2
; CHECK-NEXT: lsl x9, x9, x2 ; CHECK-NEXT: lsl x9, x9, x2
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 ; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: lsr x8, x0, x1 ; CHECK-NEXT: lsr x8, x0, x1
; CHECK-NEXT: sub x9, x9, #1 // =1 ; CHECK-NEXT: sub x9, x9, #1
; CHECK-NEXT: and x0, x9, x8 ; CHECK-NEXT: and x0, x9, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%skip = zext i8 %numskipbits to i64 %skip = zext i8 %numskipbits to i64
%shifted = lshr i64 %val, %skip %shifted = lshr i64 %val, %skip
%conv = zext i8 %numlowbits to i64 %conv = zext i8 %numlowbits to i64
%onebit = shl i64 1, %conv %onebit = shl i64 1, %conv
%mask = add nsw i64 %onebit, -1 %mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %shifted %masked = and i64 %mask, %shifted
ret i64 %masked ret i64 %masked
} }
define i64 @bextr64_a2_load(i64* %w, i64 %numskipbits, i64 %numlowbits) nounwind { define i64 @bextr64_a2_load(i64* %w, i64 %numskipbits, i64 %numlowbits) nounwind {
; CHECK-LABEL: bextr64_a2_load: ; CHECK-LABEL: bextr64_a2_load:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0] ; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl x9, x9, x2 ; CHECK-NEXT: lsl x9, x9, x2
; CHECK-NEXT: sub x9, x9, #1 // =1 ; CHECK-NEXT: sub x9, x9, #1
; CHECK-NEXT: lsr x8, x8, x1 ; CHECK-NEXT: lsr x8, x8, x1
; CHECK-NEXT: and x0, x9, x8 ; CHECK-NEXT: and x0, x9, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val = load i64, i64* %w %val = load i64, i64* %w
%shifted = lshr i64 %val, %numskipbits %shifted = lshr i64 %val, %numskipbits
%onebit = shl i64 1, %numlowbits %onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1 %mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %shifted %masked = and i64 %mask, %shifted
ret i64 %masked ret i64 %masked
} }
define i64 @bextr64_a3_load_indexzext(i64* %w, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind { define i64 @bextr64_a3_load_indexzext(i64* %w, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bextr64_a3_load_indexzext: ; CHECK-LABEL: bextr64_a3_load_indexzext:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0] ; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2 ; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2
; CHECK-NEXT: lsl x9, x9, x2 ; CHECK-NEXT: lsl x9, x9, x2
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 ; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: sub x9, x9, #1 // =1 ; CHECK-NEXT: sub x9, x9, #1
; CHECK-NEXT: lsr x8, x8, x1 ; CHECK-NEXT: lsr x8, x8, x1
; CHECK-NEXT: and x0, x9, x8 ; CHECK-NEXT: and x0, x9, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val = load i64, i64* %w %val = load i64, i64* %w
%skip = zext i8 %numskipbits to i64 %skip = zext i8 %numskipbits to i64
%shifted = lshr i64 %val, %skip %shifted = lshr i64 %val, %skip
%conv = zext i8 %numlowbits to i64 %conv = zext i8 %numlowbits to i64
%onebit = shl i64 1, %conv %onebit = shl i64 1, %conv
%mask = add nsw i64 %onebit, -1 %mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %shifted %masked = and i64 %mask, %shifted
ret i64 %masked ret i64 %masked
} }
define i64 @bextr64_a4_commutative(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind { define i64 @bextr64_a4_commutative(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; CHECK-LABEL: bextr64_a4_commutative: ; CHECK-LABEL: bextr64_a4_commutative:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl x9, x9, x2 ; CHECK-NEXT: lsl x9, x9, x2
; CHECK-NEXT: lsr x8, x0, x1 ; CHECK-NEXT: lsr x8, x0, x1
; CHECK-NEXT: sub x9, x9, #1 // =1 ; CHECK-NEXT: sub x9, x9, #1
; CHECK-NEXT: and x0, x8, x9 ; CHECK-NEXT: and x0, x8, x9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shifted = lshr i64 %val, %numskipbits %shifted = lshr i64 %val, %numskipbits
%onebit = shl i64 1, %numlowbits %onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1 %mask = add nsw i64 %onebit, -1
%masked = and i64 %shifted, %mask ; swapped order %masked = and i64 %shifted, %mask ; swapped order
ret i64 %masked ret i64 %masked
} }
; 64-bit, but with 32-bit output ; 64-bit, but with 32-bit output
; Everything done in 64-bit, truncation happens last. ; Everything done in 64-bit, truncation happens last.
define i32 @bextr64_32_a0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind { define i32 @bextr64_32_a0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; CHECK-LABEL: bextr64_32_a0: ; CHECK-LABEL: bextr64_32_a0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl x9, x9, x2 ; CHECK-NEXT: lsl x9, x9, x2
; CHECK-NEXT: lsr x8, x0, x1 ; CHECK-NEXT: lsr x8, x0, x1
; CHECK-NEXT: sub w9, w9, #1 // =1 ; CHECK-NEXT: sub w9, w9, #1
; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: and w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shifted = lshr i64 %val, %numskipbits %shifted = lshr i64 %val, %numskipbits
%onebit = shl i64 1, %numlowbits %onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1 %mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %shifted %masked = and i64 %mask, %shifted
%res = trunc i64 %masked to i32 %res = trunc i64 %masked to i32
ret i32 %res ret i32 %res
} }
; Shifting happens in 64-bit, then truncation. Masking is 32-bit. ; Shifting happens in 64-bit, then truncation. Masking is 32-bit.
define i32 @bextr64_32_a1(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind { define i32 @bextr64_32_a1(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
; CHECK-LABEL: bextr64_32_a1: ; CHECK-LABEL: bextr64_32_a1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w2 ; CHECK-NEXT: lsl w9, w9, w2
; CHECK-NEXT: lsr x8, x0, x1 ; CHECK-NEXT: lsr x8, x0, x1
; CHECK-NEXT: sub w9, w9, #1 // =1 ; CHECK-NEXT: sub w9, w9, #1
; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: and w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shifted = lshr i64 %val, %numskipbits %shifted = lshr i64 %val, %numskipbits
%truncshifted = trunc i64 %shifted to i32 %truncshifted = trunc i64 %shifted to i32
%onebit = shl i32 1, %numlowbits %onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1 %mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %truncshifted %masked = and i32 %mask, %truncshifted
ret i32 %masked ret i32 %masked
} }
; Shifting happens in 64-bit. Mask is 32-bit, but extended to 64-bit. ; Shifting happens in 64-bit. Mask is 32-bit, but extended to 64-bit.
; Masking is 64-bit. Then truncation. ; Masking is 64-bit. Then truncation.
define i32 @bextr64_32_a2(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind { define i32 @bextr64_32_a2(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
; CHECK-LABEL: bextr64_32_a2: ; CHECK-LABEL: bextr64_32_a2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w2 ; CHECK-NEXT: lsl w9, w9, w2
; CHECK-NEXT: lsr x8, x0, x1 ; CHECK-NEXT: lsr x8, x0, x1
; CHECK-NEXT: sub w9, w9, #1 // =1 ; CHECK-NEXT: sub w9, w9, #1
; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: and w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shifted = lshr i64 %val, %numskipbits %shifted = lshr i64 %val, %numskipbits
%onebit = shl i32 1, %numlowbits %onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1 %mask = add nsw i32 %onebit, -1
%zextmask = zext i32 %mask to i64 %zextmask = zext i32 %mask to i64
%masked = and i64 %zextmask, %shifted %masked = and i64 %zextmask, %shifted
%truncmasked = trunc i64 %masked to i32 %truncmasked = trunc i64 %masked to i32
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; https://bugs.llvm.org/show_bug.cgi?id=38938 ; https://bugs.llvm.org/show_bug.cgi?id=38938
define void @pr38938(i32* %a0, i64* %a1) nounwind { define void @pr38938(i32* %a0, i64* %a1) nounwind {
; CHECK-LABEL: pr38938: ; CHECK-LABEL: pr38938:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x1] ; CHECK-NEXT: ldr x8, [x1]
; CHECK-NEXT: ubfx x8, x8, #21, #10 ; CHECK-NEXT: ubfx x8, x8, #21, #10
; CHECK-NEXT: lsl x8, x8, #2 ; CHECK-NEXT: lsl x8, x8, #2
; CHECK-NEXT: ldr w9, [x0, x8] ; CHECK-NEXT: ldr w9, [x0, x8]
; CHECK-NEXT: add w9, w9, #1 // =1 ; CHECK-NEXT: add w9, w9, #1
; CHECK-NEXT: str w9, [x0, x8] ; CHECK-NEXT: str w9, [x0, x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = load i64, i64* %a1, align 8 %tmp = load i64, i64* %a1, align 8
%tmp1 = lshr i64 %tmp, 21 %tmp1 = lshr i64 %tmp, 21
%tmp2 = and i64 %tmp1, 1023 %tmp2 = and i64 %tmp1, 1023
%tmp3 = getelementptr inbounds i32, i32* %a0, i64 %tmp2 %tmp3 = getelementptr inbounds i32, i32* %a0, i64 %tmp2
%tmp4 = load i32, i32* %tmp3, align 4 %tmp4 = load i32, i32* %tmp3, align 4
%tmp5 = add nsw i32 %tmp4, 1 %tmp5 = add nsw i32 %tmp4, 1
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llvm/test/CodeGen/AArch64/extract-lowbits.ll

Show All 17 Lines
; Pattern a. 32-bit ; Pattern a. 32-bit
; ---------------------------------------------------------------------------- ; ; ---------------------------------------------------------------------------- ;
define i32 @bzhi32_a0(i32 %val, i32 %numlowbits) nounwind { define i32 @bzhi32_a0(i32 %val, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_a0: ; CHECK-LABEL: bzhi32_a0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsl w8, w8, w1 ; CHECK-NEXT: lsl w8, w8, w1
; CHECK-NEXT: sub w8, w8, #1 // =1 ; CHECK-NEXT: sub w8, w8, #1
; CHECK-NEXT: and w0, w8, w0 ; CHECK-NEXT: and w0, w8, w0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%onebit = shl i32 1, %numlowbits %onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1 %mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %val %masked = and i32 %mask, %val
ret i32 %masked ret i32 %masked
} }
define i32 @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits) nounwind { define i32 @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_a1_indexzext: ; CHECK-LABEL: bzhi32_a1_indexzext:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsl w8, w8, w1 ; CHECK-NEXT: lsl w8, w8, w1
; CHECK-NEXT: sub w8, w8, #1 // =1 ; CHECK-NEXT: sub w8, w8, #1
; CHECK-NEXT: and w0, w8, w0 ; CHECK-NEXT: and w0, w8, w0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%conv = zext i8 %numlowbits to i32 %conv = zext i8 %numlowbits to i32
%onebit = shl i32 1, %conv %onebit = shl i32 1, %conv
%mask = add nsw i32 %onebit, -1 %mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %val %masked = and i32 %mask, %val
ret i32 %masked ret i32 %masked
} }
define i32 @bzhi32_a2_load(i32* %w, i32 %numlowbits) nounwind { define i32 @bzhi32_a2_load(i32* %w, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_a2_load: ; CHECK-LABEL: bzhi32_a2_load:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0] ; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w1 ; CHECK-NEXT: lsl w9, w9, w1
; CHECK-NEXT: sub w9, w9, #1 // =1 ; CHECK-NEXT: sub w9, w9, #1
; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: and w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val = load i32, i32* %w %val = load i32, i32* %w
%onebit = shl i32 1, %numlowbits %onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1 %mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %val %masked = and i32 %mask, %val
ret i32 %masked ret i32 %masked
} }
define i32 @bzhi32_a3_load_indexzext(i32* %w, i8 zeroext %numlowbits) nounwind { define i32 @bzhi32_a3_load_indexzext(i32* %w, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_a3_load_indexzext: ; CHECK-LABEL: bzhi32_a3_load_indexzext:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0] ; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w1 ; CHECK-NEXT: lsl w9, w9, w1
; CHECK-NEXT: sub w9, w9, #1 // =1 ; CHECK-NEXT: sub w9, w9, #1
; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: and w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val = load i32, i32* %w %val = load i32, i32* %w
%conv = zext i8 %numlowbits to i32 %conv = zext i8 %numlowbits to i32
%onebit = shl i32 1, %conv %onebit = shl i32 1, %conv
%mask = add nsw i32 %onebit, -1 %mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %val %masked = and i32 %mask, %val
ret i32 %masked ret i32 %masked
} }
define i32 @bzhi32_a4_commutative(i32 %val, i32 %numlowbits) nounwind { define i32 @bzhi32_a4_commutative(i32 %val, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_a4_commutative: ; CHECK-LABEL: bzhi32_a4_commutative:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsl w8, w8, w1 ; CHECK-NEXT: lsl w8, w8, w1
; CHECK-NEXT: sub w8, w8, #1 // =1 ; CHECK-NEXT: sub w8, w8, #1
; CHECK-NEXT: and w0, w0, w8 ; CHECK-NEXT: and w0, w0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%onebit = shl i32 1, %numlowbits %onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1 %mask = add nsw i32 %onebit, -1
%masked = and i32 %val, %mask ; swapped order %masked = and i32 %val, %mask ; swapped order
ret i32 %masked ret i32 %masked
} }
; 64-bit ; 64-bit
define i64 @bzhi64_a0(i64 %val, i64 %numlowbits) nounwind { define i64 @bzhi64_a0(i64 %val, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_a0: ; CHECK-LABEL: bzhi64_a0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsl x8, x8, x1 ; CHECK-NEXT: lsl x8, x8, x1
; CHECK-NEXT: sub x8, x8, #1 // =1 ; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: and x0, x8, x0 ; CHECK-NEXT: and x0, x8, x0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%onebit = shl i64 1, %numlowbits %onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1 %mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %val %masked = and i64 %mask, %val
ret i64 %masked ret i64 %masked
} }
define i64 @bzhi64_a1_indexzext(i64 %val, i8 zeroext %numlowbits) nounwind { define i64 @bzhi64_a1_indexzext(i64 %val, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_a1_indexzext: ; CHECK-LABEL: bzhi64_a1_indexzext:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 ; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: lsl x8, x8, x1 ; CHECK-NEXT: lsl x8, x8, x1
; CHECK-NEXT: sub x8, x8, #1 // =1 ; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: and x0, x8, x0 ; CHECK-NEXT: and x0, x8, x0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%conv = zext i8 %numlowbits to i64 %conv = zext i8 %numlowbits to i64
%onebit = shl i64 1, %conv %onebit = shl i64 1, %conv
%mask = add nsw i64 %onebit, -1 %mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %val %masked = and i64 %mask, %val
ret i64 %masked ret i64 %masked
} }
define i64 @bzhi64_a2_load(i64* %w, i64 %numlowbits) nounwind { define i64 @bzhi64_a2_load(i64* %w, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_a2_load: ; CHECK-LABEL: bzhi64_a2_load:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0] ; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl x9, x9, x1 ; CHECK-NEXT: lsl x9, x9, x1
; CHECK-NEXT: sub x9, x9, #1 // =1 ; CHECK-NEXT: sub x9, x9, #1
; CHECK-NEXT: and x0, x9, x8 ; CHECK-NEXT: and x0, x9, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val = load i64, i64* %w %val = load i64, i64* %w
%onebit = shl i64 1, %numlowbits %onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1 %mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %val %masked = and i64 %mask, %val
ret i64 %masked ret i64 %masked
} }
define i64 @bzhi64_a3_load_indexzext(i64* %w, i8 zeroext %numlowbits) nounwind { define i64 @bzhi64_a3_load_indexzext(i64* %w, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_a3_load_indexzext: ; CHECK-LABEL: bzhi64_a3_load_indexzext:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0] ; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 ; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: lsl x9, x9, x1 ; CHECK-NEXT: lsl x9, x9, x1
; CHECK-NEXT: sub x9, x9, #1 // =1 ; CHECK-NEXT: sub x9, x9, #1
; CHECK-NEXT: and x0, x9, x8 ; CHECK-NEXT: and x0, x9, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val = load i64, i64* %w %val = load i64, i64* %w
%conv = zext i8 %numlowbits to i64 %conv = zext i8 %numlowbits to i64
%onebit = shl i64 1, %conv %onebit = shl i64 1, %conv
%mask = add nsw i64 %onebit, -1 %mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %val %masked = and i64 %mask, %val
ret i64 %masked ret i64 %masked
} }
define i64 @bzhi64_a4_commutative(i64 %val, i64 %numlowbits) nounwind { define i64 @bzhi64_a4_commutative(i64 %val, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_a4_commutative: ; CHECK-LABEL: bzhi64_a4_commutative:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsl x8, x8, x1 ; CHECK-NEXT: lsl x8, x8, x1
; CHECK-NEXT: sub x8, x8, #1 // =1 ; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: and x0, x0, x8 ; CHECK-NEXT: and x0, x0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%onebit = shl i64 1, %numlowbits %onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1 %mask = add nsw i64 %onebit, -1
%masked = and i64 %val, %mask ; swapped order %masked = and i64 %val, %mask ; swapped order
ret i64 %masked ret i64 %masked
} }
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llvm/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll

Show First 20 Lines • Show All 132 Lines • ▼ Show 20 Linesbb4:
ret i64 %2 ret i64 %2
} }
; If the branch is unpredictable, don't add another branch. ; If the branch is unpredictable, don't add another branch.
define i64 @test_or_unpredictable(i32 %a, i32 %b) { define i64 @test_or_unpredictable(i32 %a, i32 %b) {
; CHECK-LABEL: test_or_unpredictable: ; CHECK-LABEL: test_or_unpredictable:
; CHECK: ; %bb.0: ; %bb1 ; CHECK: ; %bb.0: ; %bb1
; CHECK-NEXT: cmp w0, #0 ; =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: cset w8, eq ; CHECK-NEXT: cset w8, eq
; CHECK-NEXT: cmp w1, #0 ; =0 ; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: cset w9, eq ; CHECK-NEXT: cset w9, eq
; CHECK-NEXT: orr w8, w8, w9 ; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: mov x0, xzr ; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: tbnz w8, #0, LBB4_2 ; CHECK-NEXT: tbnz w8, #0, LBB4_2
; CHECK-NEXT: ; %bb.1: ; %bb4 ; CHECK-NEXT: ; %bb.1: ; %bb4
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
Show All 14 Lines
bb4: bb4:
%2 = call i64 @bar() %2 = call i64 @bar()
ret i64 %2 ret i64 %2
} }
define i64 @test_and_unpredictable(i32 %a, i32 %b) { define i64 @test_and_unpredictable(i32 %a, i32 %b) {
; CHECK-LABEL: test_and_unpredictable: ; CHECK-LABEL: test_and_unpredictable:
; CHECK: ; %bb.0: ; %bb1 ; CHECK: ; %bb.0: ; %bb1
; CHECK-NEXT: cmp w0, #0 ; =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: cset w8, ne ; CHECK-NEXT: cset w8, ne
; CHECK-NEXT: cmp w1, #0 ; =0 ; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: cset w9, ne ; CHECK-NEXT: cset w9, ne
; CHECK-NEXT: and w8, w8, w9 ; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: mov x0, xzr ; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: tbz w8, #0, LBB5_2 ; CHECK-NEXT: tbz w8, #0, LBB5_2
; CHECK-NEXT: ; %bb.1: ; %bb4 ; CHECK-NEXT: ; %bb.1: ; %bb4
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
Show All 25 Lines

llvm/test/CodeGen/AArch64/fast-isel-sdiv.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK ; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK
; RUN: llc -mtriple=aarch64-linux-gnu -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK ; RUN: llc -mtriple=aarch64-linux-gnu -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK
define i32 @sdiv_i32_exact(i32 %a) { define i32 @sdiv_i32_exact(i32 %a) {
; CHECK-LABEL: sdiv_i32_exact: ; CHECK-LABEL: sdiv_i32_exact:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: asr w0, w0, #3 ; CHECK-NEXT: asr w0, w0, #3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = sdiv exact i32 %a, 8 %1 = sdiv exact i32 %a, 8
ret i32 %1 ret i32 %1
} }
define i32 @sdiv_i32_pos(i32 %a) { define i32 @sdiv_i32_pos(i32 %a) {
; CHECK-LABEL: sdiv_i32_pos: ; CHECK-LABEL: sdiv_i32_pos:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #7 // =7 ; CHECK-NEXT: add w8, w0, #7
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, w8, w0, lt ; CHECK-NEXT: csel w8, w8, w0, lt
; CHECK-NEXT: asr w0, w8, #3 ; CHECK-NEXT: asr w0, w8, #3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = sdiv i32 %a, 8 %1 = sdiv i32 %a, 8
ret i32 %1 ret i32 %1
} }
define i32 @sdiv_i32_neg(i32 %a) { define i32 @sdiv_i32_neg(i32 %a) {
; CHECK-LABEL: sdiv_i32_neg: ; CHECK-LABEL: sdiv_i32_neg:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #7 // =7 ; CHECK-NEXT: add w8, w0, #7
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, w8, w0, lt ; CHECK-NEXT: csel w8, w8, w0, lt
; CHECK-NEXT: neg w0, w8, asr #3 ; CHECK-NEXT: neg w0, w8, asr #3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = sdiv i32 %a, -8 %1 = sdiv i32 %a, -8
ret i32 %1 ret i32 %1
} }
define i64 @sdiv_i64_exact(i64 %a) { define i64 @sdiv_i64_exact(i64 %a) {
; CHECK-LABEL: sdiv_i64_exact: ; CHECK-LABEL: sdiv_i64_exact:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: asr x0, x0, #4 ; CHECK-NEXT: asr x0, x0, #4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = sdiv exact i64 %a, 16 %1 = sdiv exact i64 %a, 16
ret i64 %1 ret i64 %1
} }
define i64 @sdiv_i64_pos(i64 %a) { define i64 @sdiv_i64_pos(i64 %a) {
; CHECK-LABEL: sdiv_i64_pos: ; CHECK-LABEL: sdiv_i64_pos:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #15 // =15 ; CHECK-NEXT: add x8, x0, #15
; CHECK-NEXT: cmp x0, #0 // =0 ; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: csel x8, x8, x0, lt ; CHECK-NEXT: csel x8, x8, x0, lt
; CHECK-NEXT: asr x0, x8, #4 ; CHECK-NEXT: asr x0, x8, #4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = sdiv i64 %a, 16 %1 = sdiv i64 %a, 16
ret i64 %1 ret i64 %1
} }
define i64 @sdiv_i64_neg(i64 %a) { define i64 @sdiv_i64_neg(i64 %a) {
; CHECK-LABEL: sdiv_i64_neg: ; CHECK-LABEL: sdiv_i64_neg:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #15 // =15 ; CHECK-NEXT: add x8, x0, #15
; CHECK-NEXT: cmp x0, #0 // =0 ; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: csel x8, x8, x0, lt ; CHECK-NEXT: csel x8, x8, x0, lt
; CHECK-NEXT: neg x0, x8, asr #4 ; CHECK-NEXT: neg x0, x8, asr #4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = sdiv i64 %a, -16 %1 = sdiv i64 %a, -16
ret i64 %1 ret i64 %1
} }

llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

Show First 20 Lines • Show All 266 Lines • ▼ Show 20 Lines
declare <1 x i32> @llvm.fptosi.sat.v1f128.v1i32 (<1 x fp128>) declare <1 x i32> @llvm.fptosi.sat.v1f128.v1i32 (<1 x fp128>)
declare <2 x i32> @llvm.fptosi.sat.v2f128.v2i32 (<2 x fp128>) declare <2 x i32> @llvm.fptosi.sat.v2f128.v2i32 (<2 x fp128>)
declare <3 x i32> @llvm.fptosi.sat.v3f128.v3i32 (<3 x fp128>) declare <3 x i32> @llvm.fptosi.sat.v3f128.v3i32 (<3 x fp128>)
declare <4 x i32> @llvm.fptosi.sat.v4f128.v4i32 (<4 x fp128>) declare <4 x i32> @llvm.fptosi.sat.v4f128.v4i32 (<4 x fp128>)
define <1 x i32> @test_signed_v1f128_v1i32(<1 x fp128> %f) { define <1 x i32> @test_signed_v1f128_v1i32(<1 x fp128> %f) {
; CHECK-LABEL: test_signed_v1f128_v1i32: ; CHECK-LABEL: test_signed_v1f128_v1i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: stp x30, x19, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x19, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: adrp x8, .LCPI14_0 ; CHECK-NEXT: adrp x8, .LCPI14_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixtfsi ; CHECK-NEXT: bl __fixtfsi
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: mov w8, #-2147483648 ; CHECK-NEXT: mov w8, #-2147483648
; CHECK-NEXT: csel w19, w8, w0, lt ; CHECK-NEXT: csel w19, w8, w0, lt
; CHECK-NEXT: adrp x8, .LCPI14_1 ; CHECK-NEXT: adrp x8, .LCPI14_1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w8, #2147483647 ; CHECK-NEXT: mov w8, #2147483647
; CHECK-NEXT: csel w19, w8, w19, gt ; CHECK-NEXT: csel w19, w8, w19, gt
; CHECK-NEXT: mov v1.16b, v0.16b ; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: bl __unordtf2 ; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, wzr, w19, ne ; CHECK-NEXT: csel w8, wzr, w19, ne
; CHECK-NEXT: ldp x30, x19, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <1 x i32> @llvm.fptosi.sat.v1f128.v1i32(<1 x fp128> %f) %x = call <1 x i32> @llvm.fptosi.sat.v1f128.v1i32(<1 x fp128> %f)
ret <1 x i32> %x ret <1 x i32> %x
} }
define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) { define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-LABEL: test_signed_v2f128_v2i32: ; CHECK-LABEL: test_signed_v2f128_v2i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #112 // =112 ; CHECK-NEXT: sub sp, sp, #112
; CHECK-NEXT: str x30, [sp, #64] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #64] // 8-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #80] // 16-byte Folded Spill ; CHECK-NEXT: stp x22, x21, [sp, #80] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 112 ; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w21, -24 ; CHECK-NEXT: .cfi_offset w21, -24
; CHECK-NEXT: .cfi_offset w22, -32 ; CHECK-NEXT: .cfi_offset w22, -32
; CHECK-NEXT: .cfi_offset w30, -48 ; CHECK-NEXT: .cfi_offset w30, -48
; CHECK-NEXT: adrp x8, .LCPI15_0 ; CHECK-NEXT: adrp x8, .LCPI15_0
; CHECK-NEXT: mov v2.16b, v1.16b ; CHECK-NEXT: mov v2.16b, v1.16b
; CHECK-NEXT: stp q1, q0, [sp, #32] // 32-byte Folded Spill ; CHECK-NEXT: stp q1, q0, [sp, #32] // 32-byte Folded Spill
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: str q1, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixtfsi ; CHECK-NEXT: bl __fixtfsi
; CHECK-NEXT: adrp x8, .LCPI15_1 ; CHECK-NEXT: adrp x8, .LCPI15_1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: mov w20, #-2147483648 ; CHECK-NEXT: mov w20, #-2147483648
; CHECK-NEXT: csel w19, w20, w0, lt ; CHECK-NEXT: csel w19, w20, w0, lt
; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w21, #2147483647 ; CHECK-NEXT: mov w21, #2147483647
; CHECK-NEXT: csel w19, w21, w19, gt ; CHECK-NEXT: csel w19, w21, w19, gt
; CHECK-NEXT: mov v1.16b, v0.16b ; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: bl __unordtf2 ; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w22, wzr, w19, ne ; CHECK-NEXT: csel w22, wzr, w19, ne
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixtfsi ; CHECK-NEXT: bl __fixtfsi
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, w20, w0, lt ; CHECK-NEXT: csel w19, w20, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w19, w21, w19, gt ; CHECK-NEXT: csel w19, w21, w19, gt
; CHECK-NEXT: mov v1.16b, v0.16b ; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: bl __unordtf2 ; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, wzr, w19, ne ; CHECK-NEXT: csel w8, wzr, w19, ne
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: mov v0.s[1], w22 ; CHECK-NEXT: mov v0.s[1], w22
; CHECK-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Folded Reload
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: add sp, sp, #112 // =112 ; CHECK-NEXT: add sp, sp, #112
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptosi.sat.v2f128.v2i32(<2 x fp128> %f) %x = call <2 x i32> @llvm.fptosi.sat.v2f128.v2i32(<2 x fp128> %f)
ret <2 x i32> %x ret <2 x i32> %x
} }
define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) { define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-LABEL: test_signed_v3f128_v3i32: ; CHECK-LABEL: test_signed_v3f128_v3i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #128 // =128 ; CHECK-NEXT: sub sp, sp, #128
; CHECK-NEXT: str x30, [sp, #80] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #80] // 8-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #96] // 16-byte Folded Spill ; CHECK-NEXT: stp x22, x21, [sp, #96] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 128 ; CHECK-NEXT: .cfi_def_cfa_offset 128
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w21, -24 ; CHECK-NEXT: .cfi_offset w21, -24
; CHECK-NEXT: .cfi_offset w22, -32 ; CHECK-NEXT: .cfi_offset w22, -32
; CHECK-NEXT: .cfi_offset w30, -48 ; CHECK-NEXT: .cfi_offset w30, -48
; CHECK-NEXT: adrp x8, .LCPI16_0 ; CHECK-NEXT: adrp x8, .LCPI16_0
; CHECK-NEXT: stp q0, q2, [sp, #48] // 32-byte Folded Spill ; CHECK-NEXT: stp q0, q2, [sp, #48] // 32-byte Folded Spill
; CHECK-NEXT: mov v2.16b, v1.16b ; CHECK-NEXT: mov v2.16b, v1.16b
; CHECK-NEXT: str q1, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: str q1, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixtfsi ; CHECK-NEXT: bl __fixtfsi
; CHECK-NEXT: adrp x8, .LCPI16_1 ; CHECK-NEXT: adrp x8, .LCPI16_1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: mov w20, #-2147483648 ; CHECK-NEXT: mov w20, #-2147483648
; CHECK-NEXT: csel w19, w20, w0, lt ; CHECK-NEXT: csel w19, w20, w0, lt
; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w21, #2147483647 ; CHECK-NEXT: mov w21, #2147483647
; CHECK-NEXT: csel w19, w21, w19, gt ; CHECK-NEXT: csel w19, w21, w19, gt
; CHECK-NEXT: mov v1.16b, v0.16b ; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: bl __unordtf2 ; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w22, wzr, w19, ne ; CHECK-NEXT: csel w22, wzr, w19, ne
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixtfsi ; CHECK-NEXT: bl __fixtfsi
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, w20, w0, lt ; CHECK-NEXT: csel w19, w20, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w19, w21, w19, gt ; CHECK-NEXT: csel w19, w21, w19, gt
; CHECK-NEXT: mov v1.16b, v0.16b ; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: bl __unordtf2 ; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, wzr, w19, ne ; CHECK-NEXT: csel w8, wzr, w19, ne
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: mov v0.s[1], w22 ; CHECK-NEXT: mov v0.s[1], w22
; CHECK-NEXT: str q0, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixtfsi ; CHECK-NEXT: bl __fixtfsi
; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, w20, w0, lt ; CHECK-NEXT: csel w19, w20, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w19, w21, w19, gt ; CHECK-NEXT: csel w19, w21, w19, gt
; CHECK-NEXT: mov v1.16b, v0.16b ; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: bl __unordtf2 ; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: csel w8, wzr, w19, ne ; CHECK-NEXT: csel w8, wzr, w19, ne
; CHECK-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #96] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #96] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #80] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #80] // 8-byte Folded Reload
; CHECK-NEXT: mov v0.s[2], w8 ; CHECK-NEXT: mov v0.s[2], w8
; CHECK-NEXT: add sp, sp, #128 // =128 ; CHECK-NEXT: add sp, sp, #128
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <3 x i32> @llvm.fptosi.sat.v3f128.v3i32(<3 x fp128> %f) %x = call <3 x i32> @llvm.fptosi.sat.v3f128.v3i32(<3 x fp128> %f)
ret <3 x i32> %x ret <3 x i32> %x
} }
define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) { define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-LABEL: test_signed_v4f128_v4i32: ; CHECK-LABEL: test_signed_v4f128_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #144 // =144 ; CHECK-NEXT: sub sp, sp, #144
; CHECK-NEXT: str x30, [sp, #96] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #96] // 8-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #112] // 16-byte Folded Spill ; CHECK-NEXT: stp x22, x21, [sp, #112] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #128] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #128] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 144 ; CHECK-NEXT: .cfi_def_cfa_offset 144
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w21, -24 ; CHECK-NEXT: .cfi_offset w21, -24
; CHECK-NEXT: .cfi_offset w22, -32 ; CHECK-NEXT: .cfi_offset w22, -32
; CHECK-NEXT: .cfi_offset w30, -48 ; CHECK-NEXT: .cfi_offset w30, -48
; CHECK-NEXT: adrp x8, .LCPI17_0 ; CHECK-NEXT: adrp x8, .LCPI17_0
; CHECK-NEXT: stp q2, q3, [sp, #64] // 32-byte Folded Spill ; CHECK-NEXT: stp q2, q3, [sp, #64] // 32-byte Folded Spill
; CHECK-NEXT: mov v2.16b, v1.16b ; CHECK-NEXT: mov v2.16b, v1.16b
; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_0]
; CHECK-NEXT: str q0, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: str q1, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixtfsi ; CHECK-NEXT: bl __fixtfsi
; CHECK-NEXT: adrp x8, .LCPI17_1 ; CHECK-NEXT: adrp x8, .LCPI17_1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: mov w20, #-2147483648 ; CHECK-NEXT: mov w20, #-2147483648
; CHECK-NEXT: csel w19, w20, w0, lt ; CHECK-NEXT: csel w19, w20, w0, lt
; CHECK-NEXT: str q1, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w21, #2147483647 ; CHECK-NEXT: mov w21, #2147483647
; CHECK-NEXT: csel w19, w21, w19, gt ; CHECK-NEXT: csel w19, w21, w19, gt
; CHECK-NEXT: mov v1.16b, v0.16b ; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: bl __unordtf2 ; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload ; CHECK-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w22, wzr, w19, ne ; CHECK-NEXT: csel w22, wzr, w19, ne
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixtfsi ; CHECK-NEXT: bl __fixtfsi
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, w20, w0, lt ; CHECK-NEXT: csel w19, w20, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w19, w21, w19, gt ; CHECK-NEXT: csel w19, w21, w19, gt
; CHECK-NEXT: mov v1.16b, v0.16b ; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: bl __unordtf2 ; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, wzr, w19, ne ; CHECK-NEXT: csel w8, wzr, w19, ne
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: mov v0.s[1], w22 ; CHECK-NEXT: mov v0.s[1], w22
; CHECK-NEXT: str q0, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixtfsi ; CHECK-NEXT: bl __fixtfsi
; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, w20, w0, lt ; CHECK-NEXT: csel w19, w20, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w19, w21, w19, gt ; CHECK-NEXT: csel w19, w21, w19, gt
; CHECK-NEXT: mov v1.16b, v0.16b ; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: bl __unordtf2 ; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload ; CHECK-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, wzr, w19, ne ; CHECK-NEXT: csel w8, wzr, w19, ne
; CHECK-NEXT: mov v0.s[2], w8 ; CHECK-NEXT: mov v0.s[2], w8
; CHECK-NEXT: str q0, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixtfsi ; CHECK-NEXT: bl __fixtfsi
; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, w20, w0, lt ; CHECK-NEXT: csel w19, w20, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w19, w21, w19, gt ; CHECK-NEXT: csel w19, w21, w19, gt
; CHECK-NEXT: mov v1.16b, v0.16b ; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: bl __unordtf2 ; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: csel w8, wzr, w19, ne ; CHECK-NEXT: csel w8, wzr, w19, ne
; CHECK-NEXT: ldp x20, x19, [sp, #128] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #128] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #112] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #112] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #96] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #96] // 8-byte Folded Reload
; CHECK-NEXT: mov v0.s[3], w8 ; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: add sp, sp, #144 // =144 ; CHECK-NEXT: add sp, sp, #144
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i32> @llvm.fptosi.sat.v4f128.v4i32(<4 x fp128> %f) %x = call <4 x i32> @llvm.fptosi.sat.v4f128.v4i32(<4 x fp128> %f)
ret <4 x i32> %x ret <4 x i32> %x
} }
; ;
; FP16 to signed 32-bit -- Vector size variation ; FP16 to signed 32-bit -- Vector size variation
; ;
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i64> @llvm.fptosi.sat.v2f32.v2i64(<2 x float> %f) %x = call <2 x i64> @llvm.fptosi.sat.v2f32.v2i64(<2 x float> %f)
ret <2 x i64> %x ret <2 x i64> %x
} }
define <2 x i100> @test_signed_v2f32_v2i100(<2 x float> %f) { define <2 x i100> @test_signed_v2f32_v2i100(<2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i100: ; CHECK-LABEL: test_signed_v2f32_v2i100:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #80 // =80 ; CHECK-NEXT: sub sp, sp, #80
; CHECK-NEXT: str d10, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str d10, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill ; CHECK-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
; CHECK-NEXT: str x30, [sp, #40] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #40] // 8-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 80 ; CHECK-NEXT: .cfi_def_cfa_offset 80
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
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; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: csel x1, xzr, x8, vs ; CHECK-NEXT: csel x1, xzr, x8, vs
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #80 // =80 ; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i100> @llvm.fptosi.sat.v2f32.v2i100(<2 x float> %f) %x = call <2 x i100> @llvm.fptosi.sat.v2f32.v2i100(<2 x float> %f)
ret <2 x i100> %x ret <2 x i100> %x
} }
define <2 x i128> @test_signed_v2f32_v2i128(<2 x float> %f) { define <2 x i128> @test_signed_v2f32_v2i128(<2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i128: ; CHECK-LABEL: test_signed_v2f32_v2i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #80 // =80 ; CHECK-NEXT: sub sp, sp, #80
; CHECK-NEXT: str d10, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str d10, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill ; CHECK-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
; CHECK-NEXT: str x30, [sp, #40] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #40] // 8-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 80 ; CHECK-NEXT: .cfi_def_cfa_offset 80
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
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; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: csel x1, xzr, x8, vs ; CHECK-NEXT: csel x1, xzr, x8, vs
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #80 // =80 ; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i128> @llvm.fptosi.sat.v2f32.v2i128(<2 x float> %f) %x = call <2 x i128> @llvm.fptosi.sat.v2f32.v2i128(<2 x float> %f)
ret <2 x i128> %x ret <2 x i128> %x
} }
; ;
; 2-Vector double to signed integer -- result size variation ; 2-Vector double to signed integer -- result size variation
; ;
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i64> @llvm.fptosi.sat.v2f64.v2i64(<2 x double> %f) %x = call <2 x i64> @llvm.fptosi.sat.v2f64.v2i64(<2 x double> %f)
ret <2 x i64> %x ret <2 x i64> %x
} }
define <2 x i100> @test_signed_v2f64_v2i100(<2 x double> %f) { define <2 x i100> @test_signed_v2f64_v2i100(<2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i100: ; CHECK-LABEL: test_signed_v2f64_v2i100:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #80 // =80 ; CHECK-NEXT: sub sp, sp, #80
; CHECK-NEXT: str d10, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str d10, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill ; CHECK-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
; CHECK-NEXT: str x30, [sp, #40] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #40] // 8-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 80 ; CHECK-NEXT: .cfi_def_cfa_offset 80
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
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; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: csel x1, xzr, x8, vs ; CHECK-NEXT: csel x1, xzr, x8, vs
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #80 // =80 ; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i100> @llvm.fptosi.sat.v2f64.v2i100(<2 x double> %f) %x = call <2 x i100> @llvm.fptosi.sat.v2f64.v2i100(<2 x double> %f)
ret <2 x i100> %x ret <2 x i100> %x
} }
define <2 x i128> @test_signed_v2f64_v2i128(<2 x double> %f) { define <2 x i128> @test_signed_v2f64_v2i128(<2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i128: ; CHECK-LABEL: test_signed_v2f64_v2i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #80 // =80 ; CHECK-NEXT: sub sp, sp, #80
; CHECK-NEXT: str d10, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str d10, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill ; CHECK-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
; CHECK-NEXT: str x30, [sp, #40] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #40] // 8-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 80 ; CHECK-NEXT: .cfi_def_cfa_offset 80
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
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; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: csel x1, xzr, x8, vs ; CHECK-NEXT: csel x1, xzr, x8, vs
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #80 // =80 ; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i128> @llvm.fptosi.sat.v2f64.v2i128(<2 x double> %f) %x = call <2 x i128> @llvm.fptosi.sat.v2f64.v2i128(<2 x double> %f)
ret <2 x i128> %x ret <2 x i128> %x
} }
; ;
; 4-Vector half to signed integer -- result size variation ; 4-Vector half to signed integer -- result size variation
; ;
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i64> @llvm.fptosi.sat.v4f16.v4i64(<4 x half> %f) %x = call <4 x i64> @llvm.fptosi.sat.v4f16.v4i64(<4 x half> %f)
ret <4 x i64> %x ret <4 x i64> %x
} }
define <4 x i100> @test_signed_v4f16_v4i100(<4 x half> %f) { define <4 x i100> @test_signed_v4f16_v4i100(<4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i100: ; CHECK-LABEL: test_signed_v4f16_v4i100:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #112 // =112 ; CHECK-NEXT: sub sp, sp, #112
; CHECK-NEXT: str d10, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str d10, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill ; CHECK-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
; CHECK-NEXT: str x30, [sp, #40] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #40] // 8-byte Folded Spill
; CHECK-NEXT: stp x26, x25, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: stp x26, x25, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: stp x24, x23, [sp, #64] // 16-byte Folded Spill ; CHECK-NEXT: stp x24, x23, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #80] // 16-byte Folded Spill ; CHECK-NEXT: stp x22, x21, [sp, #80] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 112 ; CHECK-NEXT: .cfi_def_cfa_offset 112
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; CHECK-NEXT: ldp x26, x25, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x26, x25, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: csel x1, xzr, x8, vs ; CHECK-NEXT: csel x1, xzr, x8, vs
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #112 // =112 ; CHECK-NEXT: add sp, sp, #112
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i100> @llvm.fptosi.sat.v4f16.v4i100(<4 x half> %f) %x = call <4 x i100> @llvm.fptosi.sat.v4f16.v4i100(<4 x half> %f)
ret <4 x i100> %x ret <4 x i100> %x
} }
define <4 x i128> @test_signed_v4f16_v4i128(<4 x half> %f) { define <4 x i128> @test_signed_v4f16_v4i128(<4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i128: ; CHECK-LABEL: test_signed_v4f16_v4i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #112 // =112 ; CHECK-NEXT: sub sp, sp, #112
; CHECK-NEXT: str d10, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str d10, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill ; CHECK-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
; CHECK-NEXT: str x30, [sp, #40] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #40] // 8-byte Folded Spill
; CHECK-NEXT: stp x26, x25, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: stp x26, x25, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: stp x24, x23, [sp, #64] // 16-byte Folded Spill ; CHECK-NEXT: stp x24, x23, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #80] // 16-byte Folded Spill ; CHECK-NEXT: stp x22, x21, [sp, #80] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 112 ; CHECK-NEXT: .cfi_def_cfa_offset 112
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; CHECK-NEXT: ldp x26, x25, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x26, x25, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: csel x1, xzr, x8, vs ; CHECK-NEXT: csel x1, xzr, x8, vs
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #112 // =112 ; CHECK-NEXT: add sp, sp, #112
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i128> @llvm.fptosi.sat.v4f16.v4i128(<4 x half> %f) %x = call <4 x i128> @llvm.fptosi.sat.v4f16.v4i128(<4 x half> %f)
ret <4 x i128> %x ret <4 x i128> %x
} }

llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll

Show First 20 Lines • Show All 266 Lines • ▼ Show 20 Lines
declare <1 x i32> @llvm.fptoui.sat.v1f128.v1i32 (<1 x fp128>) declare <1 x i32> @llvm.fptoui.sat.v1f128.v1i32 (<1 x fp128>)
declare <2 x i32> @llvm.fptoui.sat.v2f128.v2i32 (<2 x fp128>) declare <2 x i32> @llvm.fptoui.sat.v2f128.v2i32 (<2 x fp128>)
declare <3 x i32> @llvm.fptoui.sat.v3f128.v3i32 (<3 x fp128>) declare <3 x i32> @llvm.fptoui.sat.v3f128.v3i32 (<3 x fp128>)
declare <4 x i32> @llvm.fptoui.sat.v4f128.v4i32 (<4 x fp128>) declare <4 x i32> @llvm.fptoui.sat.v4f128.v4i32 (<4 x fp128>)
define <1 x i32> @test_unsigned_v1f128_v1i32(<1 x fp128> %f) { define <1 x i32> @test_unsigned_v1f128_v1i32(<1 x fp128> %f) {
; CHECK-LABEL: test_unsigned_v1f128_v1i32: ; CHECK-LABEL: test_unsigned_v1f128_v1i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: stp x30, x19, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x19, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: adrp x8, .LCPI14_0 ; CHECK-NEXT: adrp x8, .LCPI14_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixunstfsi ; CHECK-NEXT: bl __fixunstfsi
; CHECK-NEXT: adrp x8, .LCPI14_1 ; CHECK-NEXT: adrp x8, .LCPI14_1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt ; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csinv w8, w19, wzr, le ; CHECK-NEXT: csinv w8, w19, wzr, le
; CHECK-NEXT: ldp x30, x19, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <1 x i32> @llvm.fptoui.sat.v1f128.v1i32(<1 x fp128> %f) %x = call <1 x i32> @llvm.fptoui.sat.v1f128.v1i32(<1 x fp128> %f)
ret <1 x i32> %x ret <1 x i32> %x
} }
define <2 x i32> @test_unsigned_v2f128_v2i32(<2 x fp128> %f) { define <2 x i32> @test_unsigned_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-LABEL: test_unsigned_v2f128_v2i32: ; CHECK-LABEL: test_unsigned_v2f128_v2i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #96 // =96 ; CHECK-NEXT: sub sp, sp, #96
; CHECK-NEXT: str x30, [sp, #64] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #64] // 8-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 96 ; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w30, -32 ; CHECK-NEXT: .cfi_offset w30, -32
; CHECK-NEXT: adrp x8, .LCPI15_0 ; CHECK-NEXT: adrp x8, .LCPI15_0
; CHECK-NEXT: mov v2.16b, v1.16b ; CHECK-NEXT: mov v2.16b, v1.16b
; CHECK-NEXT: stp q1, q0, [sp, #32] // 32-byte Folded Spill ; CHECK-NEXT: stp q1, q0, [sp, #32] // 32-byte Folded Spill
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: str q1, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixunstfsi ; CHECK-NEXT: bl __fixunstfsi
; CHECK-NEXT: adrp x8, .LCPI15_1 ; CHECK-NEXT: adrp x8, .LCPI15_1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt ; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csinv w20, w19, wzr, le ; CHECK-NEXT: csinv w20, w19, wzr, le
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixunstfsi ; CHECK-NEXT: bl __fixunstfsi
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt ; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csinv w8, w19, wzr, le ; CHECK-NEXT: csinv w8, w19, wzr, le
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: mov v0.s[1], w20 ; CHECK-NEXT: mov v0.s[1], w20
; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Folded Reload
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: add sp, sp, #96 // =96 ; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptoui.sat.v2f128.v2i32(<2 x fp128> %f) %x = call <2 x i32> @llvm.fptoui.sat.v2f128.v2i32(<2 x fp128> %f)
ret <2 x i32> %x ret <2 x i32> %x
} }
define <3 x i32> @test_unsigned_v3f128_v3i32(<3 x fp128> %f) { define <3 x i32> @test_unsigned_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-LABEL: test_unsigned_v3f128_v3i32: ; CHECK-LABEL: test_unsigned_v3f128_v3i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #112 // =112 ; CHECK-NEXT: sub sp, sp, #112
; CHECK-NEXT: str x30, [sp, #80] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #80] // 8-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 112 ; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w30, -32 ; CHECK-NEXT: .cfi_offset w30, -32
; CHECK-NEXT: adrp x8, .LCPI16_0 ; CHECK-NEXT: adrp x8, .LCPI16_0
; CHECK-NEXT: stp q0, q2, [sp, #48] // 32-byte Folded Spill ; CHECK-NEXT: stp q0, q2, [sp, #48] // 32-byte Folded Spill
; CHECK-NEXT: mov v2.16b, v1.16b ; CHECK-NEXT: mov v2.16b, v1.16b
; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: str q1, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixunstfsi ; CHECK-NEXT: bl __fixunstfsi
; CHECK-NEXT: adrp x8, .LCPI16_1 ; CHECK-NEXT: adrp x8, .LCPI16_1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt ; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: str q1, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload ; CHECK-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csinv w20, w19, wzr, le ; CHECK-NEXT: csinv w20, w19, wzr, le
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixunstfsi ; CHECK-NEXT: bl __fixunstfsi
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt ; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csinv w8, w19, wzr, le ; CHECK-NEXT: csinv w8, w19, wzr, le
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: mov v0.s[1], w20 ; CHECK-NEXT: mov v0.s[1], w20
; CHECK-NEXT: str q0, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixunstfsi ; CHECK-NEXT: bl __fixunstfsi
; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt ; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: csinv w8, w19, wzr, le ; CHECK-NEXT: csinv w8, w19, wzr, le
; CHECK-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #80] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #80] // 8-byte Folded Reload
; CHECK-NEXT: mov v0.s[2], w8 ; CHECK-NEXT: mov v0.s[2], w8
; CHECK-NEXT: add sp, sp, #112 // =112 ; CHECK-NEXT: add sp, sp, #112
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <3 x i32> @llvm.fptoui.sat.v3f128.v3i32(<3 x fp128> %f) %x = call <3 x i32> @llvm.fptoui.sat.v3f128.v3i32(<3 x fp128> %f)
ret <3 x i32> %x ret <3 x i32> %x
} }
define <4 x i32> @test_unsigned_v4f128_v4i32(<4 x fp128> %f) { define <4 x i32> @test_unsigned_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-LABEL: test_unsigned_v4f128_v4i32: ; CHECK-LABEL: test_unsigned_v4f128_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #128 // =128 ; CHECK-NEXT: sub sp, sp, #128
; CHECK-NEXT: str x30, [sp, #96] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #96] // 8-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 128 ; CHECK-NEXT: .cfi_def_cfa_offset 128
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w30, -32 ; CHECK-NEXT: .cfi_offset w30, -32
; CHECK-NEXT: adrp x8, .LCPI17_0 ; CHECK-NEXT: adrp x8, .LCPI17_0
; CHECK-NEXT: stp q0, q2, [sp, #16] // 32-byte Folded Spill ; CHECK-NEXT: stp q0, q2, [sp, #16] // 32-byte Folded Spill
; CHECK-NEXT: mov v2.16b, v1.16b ; CHECK-NEXT: mov v2.16b, v1.16b
; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_0]
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: str q3, [sp, #80] // 16-byte Folded Spill ; CHECK-NEXT: str q3, [sp, #80] // 16-byte Folded Spill
; CHECK-NEXT: str q1, [sp, #64] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixunstfsi ; CHECK-NEXT: bl __fixunstfsi
; CHECK-NEXT: adrp x8, .LCPI17_1 ; CHECK-NEXT: adrp x8, .LCPI17_1
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt ; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: str q1, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csinv w20, w19, wzr, le ; CHECK-NEXT: csinv w20, w19, wzr, le
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixunstfsi ; CHECK-NEXT: bl __fixunstfsi
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt ; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csinv w8, w19, wzr, le ; CHECK-NEXT: csinv w8, w19, wzr, le
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: mov v0.s[1], w20 ; CHECK-NEXT: mov v0.s[1], w20
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixunstfsi ; CHECK-NEXT: bl __fixunstfsi
; CHECK-NEXT: ldp q0, q1, [sp, #32] // 32-byte Folded Reload ; CHECK-NEXT: ldp q0, q1, [sp, #32] // 32-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt ; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csinv w8, w19, wzr, le ; CHECK-NEXT: csinv w8, w19, wzr, le
; CHECK-NEXT: mov v0.s[2], w8 ; CHECK-NEXT: mov v0.s[2], w8
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload ; CHECK-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixunstfsi ; CHECK-NEXT: bl __fixunstfsi
; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: ldr q1, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 // =0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt ; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: csinv w8, w19, wzr, le ; CHECK-NEXT: csinv w8, w19, wzr, le
; CHECK-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #96] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #96] // 8-byte Folded Reload
; CHECK-NEXT: mov v0.s[3], w8 ; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: add sp, sp, #128 // =128 ; CHECK-NEXT: add sp, sp, #128
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i32> @llvm.fptoui.sat.v4f128.v4i32(<4 x fp128> %f) %x = call <4 x i32> @llvm.fptoui.sat.v4f128.v4i32(<4 x fp128> %f)
ret <4 x i32> %x ret <4 x i32> %x
} }
; ;
; FP16 to unsigned 32-bit -- Vector size variation ; FP16 to unsigned 32-bit -- Vector size variation
; ;
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i64> @llvm.fptoui.sat.v2f32.v2i64(<2 x float> %f) %x = call <2 x i64> @llvm.fptoui.sat.v2f32.v2i64(<2 x float> %f)
ret <2 x i64> %x ret <2 x i64> %x
} }
define <2 x i100> @test_unsigned_v2f32_v2i100(<2 x float> %f) { define <2 x i100> @test_unsigned_v2f32_v2i100(<2 x float> %f) {
; CHECK-LABEL: test_unsigned_v2f32_v2i100: ; CHECK-LABEL: test_unsigned_v2f32_v2i100:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #64 // =64 ; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: stp x30, x21, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x21, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w21, -24 ; CHECK-NEXT: .cfi_offset w21, -24
; CHECK-NEXT: .cfi_offset w30, -32 ; CHECK-NEXT: .cfi_offset w30, -32
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; CHECK-NEXT: fcmp s0, s9 ; CHECK-NEXT: fcmp s0, s9
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csel x1, x21, x9, gt ; CHECK-NEXT: csel x1, x21, x9, gt
; CHECK-NEXT: ldp x30, x21, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x21, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #64 // =64 ; CHECK-NEXT: add sp, sp, #64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i100> @llvm.fptoui.sat.v2f32.v2i100(<2 x float> %f) %x = call <2 x i100> @llvm.fptoui.sat.v2f32.v2i100(<2 x float> %f)
ret <2 x i100> %x ret <2 x i100> %x
} }
define <2 x i128> @test_unsigned_v2f32_v2i128(<2 x float> %f) { define <2 x i128> @test_unsigned_v2f32_v2i128(<2 x float> %f) {
; CHECK-LABEL: test_unsigned_v2f32_v2i128: ; CHECK-LABEL: test_unsigned_v2f32_v2i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #64 // =64 ; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w30, -32 ; CHECK-NEXT: .cfi_offset w30, -32
; CHECK-NEXT: .cfi_offset b8, -40 ; CHECK-NEXT: .cfi_offset b8, -40
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; CHECK-NEXT: fcmp s0, s9 ; CHECK-NEXT: fcmp s0, s9
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: csinv x1, x9, xzr, le ; CHECK-NEXT: csinv x1, x9, xzr, le
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #64 // =64 ; CHECK-NEXT: add sp, sp, #64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i128> @llvm.fptoui.sat.v2f32.v2i128(<2 x float> %f) %x = call <2 x i128> @llvm.fptoui.sat.v2f32.v2i128(<2 x float> %f)
ret <2 x i128> %x ret <2 x i128> %x
} }
; ;
; 2-Vector double to unsigned integer -- result size variation ; 2-Vector double to unsigned integer -- result size variation
; ;
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i64> @llvm.fptoui.sat.v2f64.v2i64(<2 x double> %f) %x = call <2 x i64> @llvm.fptoui.sat.v2f64.v2i64(<2 x double> %f)
ret <2 x i64> %x ret <2 x i64> %x
} }
define <2 x i100> @test_unsigned_v2f64_v2i100(<2 x double> %f) { define <2 x i100> @test_unsigned_v2f64_v2i100(<2 x double> %f) {
; CHECK-LABEL: test_unsigned_v2f64_v2i100: ; CHECK-LABEL: test_unsigned_v2f64_v2i100:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #64 // =64 ; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: stp x30, x21, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x21, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w21, -24 ; CHECK-NEXT: .cfi_offset w21, -24
; CHECK-NEXT: .cfi_offset w30, -32 ; CHECK-NEXT: .cfi_offset w30, -32
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; CHECK-NEXT: fcmp d0, d9 ; CHECK-NEXT: fcmp d0, d9
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csel x1, x21, x9, gt ; CHECK-NEXT: csel x1, x21, x9, gt
; CHECK-NEXT: ldp x30, x21, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x21, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #64 // =64 ; CHECK-NEXT: add sp, sp, #64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i100> @llvm.fptoui.sat.v2f64.v2i100(<2 x double> %f) %x = call <2 x i100> @llvm.fptoui.sat.v2f64.v2i100(<2 x double> %f)
ret <2 x i100> %x ret <2 x i100> %x
} }
define <2 x i128> @test_unsigned_v2f64_v2i128(<2 x double> %f) { define <2 x i128> @test_unsigned_v2f64_v2i128(<2 x double> %f) {
; CHECK-LABEL: test_unsigned_v2f64_v2i128: ; CHECK-LABEL: test_unsigned_v2f64_v2i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #64 // =64 ; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w30, -32 ; CHECK-NEXT: .cfi_offset w30, -32
; CHECK-NEXT: .cfi_offset b8, -40 ; CHECK-NEXT: .cfi_offset b8, -40
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; CHECK-NEXT: fcmp d0, d9 ; CHECK-NEXT: fcmp d0, d9
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: csinv x1, x9, xzr, le ; CHECK-NEXT: csinv x1, x9, xzr, le
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #64 // =64 ; CHECK-NEXT: add sp, sp, #64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i128> @llvm.fptoui.sat.v2f64.v2i128(<2 x double> %f) %x = call <2 x i128> @llvm.fptoui.sat.v2f64.v2i128(<2 x double> %f)
ret <2 x i128> %x ret <2 x i128> %x
} }
; ;
; 4-Vector half to unsigned integer -- result size variation ; 4-Vector half to unsigned integer -- result size variation
; ;
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i64> @llvm.fptoui.sat.v4f16.v4i64(<4 x half> %f) %x = call <4 x i64> @llvm.fptoui.sat.v4f16.v4i64(<4 x half> %f)
ret <4 x i64> %x ret <4 x i64> %x
} }
define <4 x i100> @test_unsigned_v4f16_v4i100(<4 x half> %f) { define <4 x i100> @test_unsigned_v4f16_v4i100(<4 x half> %f) {
; CHECK-LABEL: test_unsigned_v4f16_v4i100: ; CHECK-LABEL: test_unsigned_v4f16_v4i100:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #96 // =96 ; CHECK-NEXT: sub sp, sp, #96
; CHECK-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: stp x30, x25, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x25, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: stp x24, x23, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: stp x24, x23, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #64] // 16-byte Folded Spill ; CHECK-NEXT: stp x22, x21, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 96 ; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
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; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldp x30, x25, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x25, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #96 // =96 ; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i100> @llvm.fptoui.sat.v4f16.v4i100(<4 x half> %f) %x = call <4 x i100> @llvm.fptoui.sat.v4f16.v4i100(<4 x half> %f)
ret <4 x i100> %x ret <4 x i100> %x
} }
define <4 x i128> @test_unsigned_v4f16_v4i128(<4 x half> %f) { define <4 x i128> @test_unsigned_v4f16_v4i128(<4 x half> %f) {
; CHECK-LABEL: test_unsigned_v4f16_v4i128: ; CHECK-LABEL: test_unsigned_v4f16_v4i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #96 // =96 ; CHECK-NEXT: sub sp, sp, #96
; CHECK-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: stp x24, x23, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: stp x24, x23, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: stp x22, x21, [sp, #64] // 16-byte Folded Spill ; CHECK-NEXT: stp x22, x21, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 96 ; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
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; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: csinv x1, x9, xzr, le ; CHECK-NEXT: csinv x1, x9, xzr, le
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #96 // =96 ; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i128> @llvm.fptoui.sat.v4f16.v4i128(<4 x half> %f) %x = call <4 x i128> @llvm.fptoui.sat.v4f16.v4i128(<4 x half> %f)
ret <4 x i128> %x ret <4 x i128> %x
} }

llvm/test/CodeGen/AArch64/funnel-shift.ll

Show First 20 Lines • Show All 187 Lines • ▼ Show 20 Lines
; CHECK-NEXT: movk x8, #3542, lsl #16 ; CHECK-NEXT: movk x8, #3542, lsl #16
; CHECK-NEXT: movk x8, #51366, lsl #32 ; CHECK-NEXT: movk x8, #51366, lsl #32
; CHECK-NEXT: movk x8, #56679, lsl #48 ; CHECK-NEXT: movk x8, #56679, lsl #48
; CHECK-NEXT: umulh x8, x2, x8 ; CHECK-NEXT: umulh x8, x2, x8
; CHECK-NEXT: mov w9, #37 ; CHECK-NEXT: mov w9, #37
; CHECK-NEXT: lsr x8, x8, #5 ; CHECK-NEXT: lsr x8, x8, #5
; CHECK-NEXT: msub w8, w8, w9, w2 ; CHECK-NEXT: msub w8, w8, w9, w2
; CHECK-NEXT: lsl x10, x1, #27 ; CHECK-NEXT: lsl x10, x1, #27
; CHECK-NEXT: add w8, w8, #27 // =27 ; CHECK-NEXT: add w8, w8, #27
; CHECK-NEXT: lsr x9, x10, x8 ; CHECK-NEXT: lsr x9, x10, x8
; CHECK-NEXT: mvn w8, w8 ; CHECK-NEXT: mvn w8, w8
; CHECK-NEXT: lsl x10, x0, #1 ; CHECK-NEXT: lsl x10, x0, #1
; CHECK-NEXT: lsl x8, x10, x8 ; CHECK-NEXT: lsl x8, x10, x8
; CHECK-NEXT: orr x0, x8, x9 ; CHECK-NEXT: orr x0, x8, x9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z) %f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z)
ret i37 %f ret i37 %f
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llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

Show First 20 Lines • Show All 295 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%res = icmp eq i32 %t1, 0 %res = icmp eq i32 %t1, 0
ret i1 %res ret i1 %res
} }
define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind { define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
; CHECK-LABEL: scalar_i32_x_is_const2_eq: ; CHECK-LABEL: scalar_i32_x_is_const2_eq:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsr w8, w8, w0 ; CHECK-NEXT: lsr w8, w8, w0
; CHECK-NEXT: cmp w8, #0 // =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = lshr i32 1, %y %t0 = lshr i32 1, %y
%t1 = and i32 %t0, 2857740885 %t1 = and i32 %t0, 2857740885
%res = icmp eq i32 %t1, 0 %res = icmp eq i32 %t1, 0
ret i1 %res ret i1 %res
} }
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define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind { define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
; CHECK-LABEL: scalar_i8_signbit_eq_with_nonzero: ; CHECK-LABEL: scalar_i8_signbit_eq_with_nonzero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #128 ; CHECK-NEXT: mov w8, #128
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 ; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: lsr w8, w8, w1 ; CHECK-NEXT: lsr w8, w8, w1
; CHECK-NEXT: and w8, w8, w0 ; CHECK-NEXT: and w8, w8, w0
; CHECK-NEXT: cmp w8, #1 // =1 ; CHECK-NEXT: cmp w8, #1
; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = lshr i8 128, %y %t0 = lshr i8 128, %y
%t1 = and i8 %t0, %x %t1 = and i8 %t0, %x
%res = icmp eq i8 %t1, 1 ; should be comparing with 0 %res = icmp eq i8 %t1, 1 ; should be comparing with 0
ret i1 %res ret i1 %res
} }

llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

Show First 20 Lines • Show All 333 Lines • ▼ Show 20 Lines
define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind { define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
; CHECK-LABEL: scalar_i8_signbit_eq_with_nonzero: ; CHECK-LABEL: scalar_i8_signbit_eq_with_nonzero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-128 ; CHECK-NEXT: mov w8, #-128
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 ; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: lsl w8, w8, w1 ; CHECK-NEXT: lsl w8, w8, w1
; CHECK-NEXT: and w8, w8, w0 ; CHECK-NEXT: and w8, w8, w0
; CHECK-NEXT: and w8, w8, #0x80 ; CHECK-NEXT: and w8, w8, #0x80
; CHECK-NEXT: cmp w8, #1 // =1 ; CHECK-NEXT: cmp w8, #1
; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = shl i8 128, %y %t0 = shl i8 128, %y
%t1 = and i8 %t0, %x %t1 = and i8 %t0, %x
%res = icmp eq i8 %t1, 1 ; should be comparing with 0 %res = icmp eq i8 %t1, 1 ; should be comparing with 0
ret i1 %res ret i1 %res
} }

llvm/test/CodeGen/AArch64/i128_volatile_load_store.ll

Show All 32 Lines; CHECK-NEXT: ret
ret void ret void
} }
define void @test3() { define void @test3() {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, x ; CHECK-NEXT: adrp x8, x
; CHECK-NEXT: add x8, x8, :lo12:x ; CHECK-NEXT: add x8, x8, :lo12:x
; CHECK-NEXT: add x8, x8, #512 // =512 ; CHECK-NEXT: add x8, x8, #512
; CHECK-NEXT: ldp x8, x9, [x8] ; CHECK-NEXT: ldp x8, x9, [x8]
; CHECK-NEXT: adrp x10, y ; CHECK-NEXT: adrp x10, y
; CHECK-NEXT: add x10, x10, :lo12:y ; CHECK-NEXT: add x10, x10, :lo12:y
; CHECK-NEXT: add x10, x10, #512 // =512 ; CHECK-NEXT: add x10, x10, #512
; CHECK-NEXT: stp x8, x9, [x10] ; CHECK-NEXT: stp x8, x9, [x10]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = load volatile i128, i128* bitcast (i8* getelementptr (i8, i8* bitcast (i128* @x to i8*), i64 512) to i128*) %tmp = load volatile i128, i128* bitcast (i8* getelementptr (i8, i8* bitcast (i128* @x to i8*), i64 512) to i128*)
store volatile i128 %tmp, i128* bitcast (i8* getelementptr (i8, i8* bitcast (i128* @y to i8*), i64 512) to i128*) store volatile i128 %tmp, i128* bitcast (i8* getelementptr (i8, i8* bitcast (i128* @y to i8*), i64 512) to i128*)
ret void ret void
} }
define void @test4() { define void @test4() {
Show All 11 Lines; CHECK-NEXT: ret
ret void ret void
} }
define void @test5() { define void @test5() {
; CHECK-LABEL: test5: ; CHECK-LABEL: test5:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, x ; CHECK-NEXT: adrp x8, x
; CHECK-NEXT: add x8, x8, :lo12:x ; CHECK-NEXT: add x8, x8, :lo12:x
; CHECK-NEXT: sub x8, x8, #520 // =520 ; CHECK-NEXT: sub x8, x8, #520
; CHECK-NEXT: ldp x8, x9, [x8] ; CHECK-NEXT: ldp x8, x9, [x8]
; CHECK-NEXT: adrp x10, y ; CHECK-NEXT: adrp x10, y
; CHECK-NEXT: add x10, x10, :lo12:y ; CHECK-NEXT: add x10, x10, :lo12:y
; CHECK-NEXT: sub x10, x10, #520 // =520 ; CHECK-NEXT: sub x10, x10, #520
; CHECK-NEXT: stp x8, x9, [x10] ; CHECK-NEXT: stp x8, x9, [x10]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = load volatile i128, i128* bitcast (i8* getelementptr (i8, i8* bitcast (i128* @x to i8*), i64 -520) to i128*) %tmp = load volatile i128, i128* bitcast (i8* getelementptr (i8, i8* bitcast (i128* @x to i8*), i64 -520) to i128*)
store volatile i128 %tmp, i128* bitcast (i8* getelementptr (i8, i8* bitcast (i128* @y to i8*), i64 -520) to i128*) store volatile i128 %tmp, i128* bitcast (i8* getelementptr (i8, i8* bitcast (i128* @y to i8*), i64 -520) to i128*)
ret void ret void
} }
define void @test6() { define void @test6() {
; CHECK-LABEL: test6: ; CHECK-LABEL: test6:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, x ; CHECK-NEXT: adrp x8, x
; CHECK-NEXT: add x8, x8, :lo12:x ; CHECK-NEXT: add x8, x8, :lo12:x
; CHECK-NEXT: sub x8, x8, #520 // =520 ; CHECK-NEXT: sub x8, x8, #520
; CHECK-NEXT: ldp x8, x9, [x8] ; CHECK-NEXT: ldp x8, x9, [x8]
; CHECK-NEXT: adrp x10, y ; CHECK-NEXT: adrp x10, y
; CHECK-NEXT: add x10, x10, :lo12:y ; CHECK-NEXT: add x10, x10, :lo12:y
; CHECK-NEXT: sub x10, x10, #520 // =520 ; CHECK-NEXT: sub x10, x10, #520
; CHECK-NEXT: stp x8, x9, [x10] ; CHECK-NEXT: stp x8, x9, [x10]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = load volatile i128, i128* bitcast (i8* getelementptr (i8, i8* bitcast (i128* @x to i8*), i64 -520) to i128*) %tmp = load volatile i128, i128* bitcast (i8* getelementptr (i8, i8* bitcast (i128* @x to i8*), i64 -520) to i128*)
store volatile i128 %tmp, i128* bitcast (i8* getelementptr (i8, i8* bitcast (i128* @y to i8*), i64 -520) to i128*) store volatile i128 %tmp, i128* bitcast (i8* getelementptr (i8, i8* bitcast (i128* @y to i8*), i64 -520) to i128*)
ret void ret void
} }
define void @test7() { define void @test7() {
; CHECK-LABEL: test7: ; CHECK-LABEL: test7:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, x ; CHECK-NEXT: adrp x8, x
; CHECK-NEXT: add x8, x8, :lo12:x ; CHECK-NEXT: add x8, x8, :lo12:x
; CHECK-NEXT: add x8, x8, #503 // =503 ; CHECK-NEXT: add x8, x8, #503
; CHECK-NEXT: ldp x8, x9, [x8] ; CHECK-NEXT: ldp x8, x9, [x8]
; CHECK-NEXT: adrp x10, y ; CHECK-NEXT: adrp x10, y
; CHECK-NEXT: add x10, x10, :lo12:y ; CHECK-NEXT: add x10, x10, :lo12:y
; CHECK-NEXT: add x10, x10, #503 // =503 ; CHECK-NEXT: add x10, x10, #503
; CHECK-NEXT: stp x8, x9, [x10] ; CHECK-NEXT: stp x8, x9, [x10]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = load volatile i128, i128* bitcast (i8* getelementptr (i8, i8* bitcast (i128* @x to i8*), i64 503) to i128*) %tmp = load volatile i128, i128* bitcast (i8* getelementptr (i8, i8* bitcast (i128* @x to i8*), i64 503) to i128*)
store volatile i128 %tmp, i128* bitcast (i8* getelementptr (i8, i8* bitcast (i128* @y to i8*), i64 503) to i128*) store volatile i128 %tmp, i128* bitcast (i8* getelementptr (i8, i8* bitcast (i128* @y to i8*), i64 503) to i128*)
ret void ret void
} }

llvm/test/CodeGen/AArch64/implicit-null-check.ll

Show First 20 Lines • Show All 278 Lines • ▼ Show 20 Lines
define i32 @imp_null_check_gep_load_with_use_dep(i32* %x, i32 %a) { define i32 @imp_null_check_gep_load_with_use_dep(i32* %x, i32 %a) {
; CHECK-LABEL: imp_null_check_gep_load_with_use_dep: ; CHECK-LABEL: imp_null_check_gep_load_with_use_dep:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: .Ltmp7: ; CHECK-NEXT: .Ltmp7:
; CHECK-NEXT: ldr w8, [x0] // on-fault: .LBB11_2 ; CHECK-NEXT: ldr w8, [x0] // on-fault: .LBB11_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: add w9, w0, w1 ; CHECK-NEXT: add w9, w0, w1
; CHECK-NEXT: add w8, w9, w8 ; CHECK-NEXT: add w8, w9, w8
; CHECK-NEXT: add w0, w8, #4 // =4 ; CHECK-NEXT: add w0, w8, #4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB11_2: ; CHECK-NEXT: .LBB11_2:
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i32* %x, null %c = icmp eq i32* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
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llvm/test/CodeGen/AArch64/inc-of-add.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
; These two forms are equivalent: ; These two forms are equivalent:
; sub %y, (xor %x, -1) ; sub %y, (xor %x, -1)
; add (add %x, 1), %y ; add (add %x, 1), %y
; Some targets may prefer one to the other. ; Some targets may prefer one to the other.
define i8 @scalar_i8(i8 %x, i8 %y) nounwind { define i8 @scalar_i8(i8 %x, i8 %y) nounwind {
; CHECK-LABEL: scalar_i8: ; CHECK-LABEL: scalar_i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1 ; CHECK-NEXT: add w8, w0, w1
; CHECK-NEXT: add w0, w8, #1 // =1 ; CHECK-NEXT: add w0, w8, #1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add i8 %x, 1 %t0 = add i8 %x, 1
%t1 = add i8 %y, %t0 %t1 = add i8 %y, %t0
ret i8 %t1 ret i8 %t1
} }
define i16 @scalar_i16(i16 %x, i16 %y) nounwind { define i16 @scalar_i16(i16 %x, i16 %y) nounwind {
; CHECK-LABEL: scalar_i16: ; CHECK-LABEL: scalar_i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1 ; CHECK-NEXT: add w8, w0, w1
; CHECK-NEXT: add w0, w8, #1 // =1 ; CHECK-NEXT: add w0, w8, #1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add i16 %x, 1 %t0 = add i16 %x, 1
%t1 = add i16 %y, %t0 %t1 = add i16 %y, %t0
ret i16 %t1 ret i16 %t1
} }
define i32 @scalar_i32(i32 %x, i32 %y) nounwind { define i32 @scalar_i32(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: scalar_i32: ; CHECK-LABEL: scalar_i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1 ; CHECK-NEXT: add w8, w0, w1
; CHECK-NEXT: add w0, w8, #1 // =1 ; CHECK-NEXT: add w0, w8, #1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add i32 %x, 1 %t0 = add i32 %x, 1
%t1 = add i32 %y, %t0 %t1 = add i32 %y, %t0
ret i32 %t1 ret i32 %t1
} }
define i64 @scalar_i64(i64 %x, i64 %y) nounwind { define i64 @scalar_i64(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: scalar_i64: ; CHECK-LABEL: scalar_i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, x1 ; CHECK-NEXT: add x8, x0, x1
; CHECK-NEXT: add x0, x8, #1 // =1 ; CHECK-NEXT: add x0, x8, #1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add i64 %x, 1 %t0 = add i64 %x, 1
%t1 = add i64 %y, %t0 %t1 = add i64 %y, %t0
ret i64 %t1 ret i64 %t1
} }
define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind { define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; CHECK-LABEL: vector_i128_i8: ; CHECK-LABEL: vector_i128_i8:
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i8: ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0] ; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: cnth x9 ; CHECK-NEXT: cnth x9
; CHECK-NEXT: sub x9, x9, #8 // =8 ; CHECK-NEXT: sub x9, x9, #8
; CHECK-NEXT: mov w8, #8 ; CHECK-NEXT: mov w8, #8
; CHECK-NEXT: cmp x9, #8 // =8 ; CHECK-NEXT: cmp x9, #8
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: lsl x8, x8, #1 ; CHECK-NEXT: lsl x8, x8, #1
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: ushll v0.8h, v1.8b, #0 ; CHECK-NEXT: ushll v0.8h, v1.8b, #0
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: str q0, [x9, x8] ; CHECK-NEXT: str q0, [x9, x8]
; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
Show All 30 Lines
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i16: ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: cntw x9 ; CHECK-NEXT: cntw x9
; CHECK-NEXT: sub x9, x9, #4 // =4 ; CHECK-NEXT: sub x9, x9, #4
; CHECK-NEXT: mov w8, #4 ; CHECK-NEXT: mov w8, #4
; CHECK-NEXT: cmp x9, #4 // =4 ; CHECK-NEXT: cmp x9, #4
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: lsl x8, x8, #2 ; CHECK-NEXT: lsl x8, x8, #2
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: ushll v0.4s, v1.4h, #0 ; CHECK-NEXT: ushll v0.4s, v1.4h, #0
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: str q0, [x9, x8] ; CHECK-NEXT: str q0, [x9, x8]
; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
Show All 30 Lines
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i32: ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0] ; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: cntd x9 ; CHECK-NEXT: cntd x9
; CHECK-NEXT: sub x9, x9, #2 // =2 ; CHECK-NEXT: sub x9, x9, #2
; CHECK-NEXT: mov w8, #2 ; CHECK-NEXT: mov w8, #2
; CHECK-NEXT: cmp x9, #2 // =2 ; CHECK-NEXT: cmp x9, #2
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: ushll v0.2d, v1.2s, #0 ; CHECK-NEXT: ushll v0.2d, v1.2s, #0
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: str q0, [x9, x8] ; CHECK-NEXT: str q0, [x9, x8]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
Show All 10 Lines
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ptrue p1.s, vl8 ; CHECK-NEXT: ptrue p1.s, vl8
; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0] ; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
; CHECK-NEXT: ld1w { z1.s }, p1/z, [x1] ; CHECK-NEXT: ld1w { z1.s }, p1/z, [x1]
; CHECK-NEXT: cntd x8 ; CHECK-NEXT: cntd x8
; CHECK-NEXT: subs x8, x8, #8 // =8 ; CHECK-NEXT: subs x8, x8, #8
; CHECK-NEXT: csel x8, xzr, x8, lo ; CHECK-NEXT: csel x8, xzr, x8, lo
; CHECK-NEXT: mov w9, #8 ; CHECK-NEXT: mov w9, #8
; CHECK-NEXT: cmp x8, #8 // =8 ; CHECK-NEXT: cmp x8, #8
; CHECK-NEXT: ptrue p1.d, vl8 ; CHECK-NEXT: ptrue p1.d, vl8
; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: uunpklo z0.d, z1.s ; CHECK-NEXT: uunpklo z0.d, z1.s
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st1d { z0.d }, p1, [x9, x8, lsl #3] ; CHECK-NEXT: st1d { z0.d }, p1, [x9, x8, lsl #3]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
Show All 19 Lines

llvm/test/CodeGen/AArch64/lack-of-signed-truncation-check.ll

Show First 20 Lines • Show All 267 Lines • ▼ Show 20 Lines
; ---------------------------------------------------------------------------- ; ; ---------------------------------------------------------------------------- ;
; Adding not a constant ; Adding not a constant
define i1 @add_ugecmp_bad_i16_i8_add(i16 %x, i16 %y) nounwind { define i1 @add_ugecmp_bad_i16_i8_add(i16 %x, i16 %y) nounwind {
; CHECK-LABEL: add_ugecmp_bad_i16_i8_add: ; CHECK-LABEL: add_ugecmp_bad_i16_i8_add:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1 ; CHECK-NEXT: add w8, w0, w1
; CHECK-NEXT: and w8, w8, #0xffff ; CHECK-NEXT: and w8, w8, #0xffff
; CHECK-NEXT: cmp w8, #255 // =255 ; CHECK-NEXT: cmp w8, #255
; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: cset w0, hi
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i16 %x, %y %tmp0 = add i16 %x, %y
%tmp1 = icmp uge i16 %tmp0, 256 ; 1U << 8 %tmp1 = icmp uge i16 %tmp0, 256 ; 1U << 8
ret i1 %tmp1 ret i1 %tmp1
} }
; Comparing not with a constant ; Comparing not with a constant
define i1 @add_ugecmp_bad_i16_i8_cmp(i16 %x, i16 %y) nounwind { define i1 @add_ugecmp_bad_i16_i8_cmp(i16 %x, i16 %y) nounwind {
; CHECK-LABEL: add_ugecmp_bad_i16_i8_cmp: ; CHECK-LABEL: add_ugecmp_bad_i16_i8_cmp:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #128 // =128 ; CHECK-NEXT: add w8, w0, #128
; CHECK-NEXT: and w8, w8, #0xffff ; CHECK-NEXT: and w8, w8, #0xffff
; CHECK-NEXT: cmp w8, w1, uxth ; CHECK-NEXT: cmp w8, w1, uxth
; CHECK-NEXT: cset w0, hs ; CHECK-NEXT: cset w0, hs
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i16 %x, 128 ; 1U << (8-1) %tmp0 = add i16 %x, 128 ; 1U << (8-1)
%tmp1 = icmp uge i16 %tmp0, %y %tmp1 = icmp uge i16 %tmp0, %y
ret i1 %tmp1 ret i1 %tmp1
} }
; Second constant is not larger than the first one ; Second constant is not larger than the first one
define i1 @add_ugecmp_bad_i8_i16(i16 %x) nounwind { define i1 @add_ugecmp_bad_i8_i16(i16 %x) nounwind {
; CHECK-LABEL: add_ugecmp_bad_i8_i16: ; CHECK-LABEL: add_ugecmp_bad_i8_i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #128 // =128 ; CHECK-NEXT: add w8, w0, #128
; CHECK-NEXT: and w8, w8, #0xffff ; CHECK-NEXT: and w8, w8, #0xffff
; CHECK-NEXT: cmp w8, #127 // =127 ; CHECK-NEXT: cmp w8, #127
; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: cset w0, hi
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i16 %x, 128 ; 1U << (8-1) %tmp0 = add i16 %x, 128 ; 1U << (8-1)
%tmp1 = icmp uge i16 %tmp0, 128 ; 1U << (8-1) %tmp1 = icmp uge i16 %tmp0, 128 ; 1U << (8-1)
ret i1 %tmp1 ret i1 %tmp1
} }
; First constant is not power of two ; First constant is not power of two
define i1 @add_ugecmp_bad_i16_i8_c0notpoweroftwo(i16 %x) nounwind { define i1 @add_ugecmp_bad_i16_i8_c0notpoweroftwo(i16 %x) nounwind {
; CHECK-LABEL: add_ugecmp_bad_i16_i8_c0notpoweroftwo: ; CHECK-LABEL: add_ugecmp_bad_i16_i8_c0notpoweroftwo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #192 // =192 ; CHECK-NEXT: add w8, w0, #192
; CHECK-NEXT: and w8, w8, #0xffff ; CHECK-NEXT: and w8, w8, #0xffff
; CHECK-NEXT: cmp w8, #255 // =255 ; CHECK-NEXT: cmp w8, #255
; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: cset w0, hi
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i16 %x, 192 ; (1U << (8-1)) + (1U << (8-1-1)) %tmp0 = add i16 %x, 192 ; (1U << (8-1)) + (1U << (8-1-1))
%tmp1 = icmp uge i16 %tmp0, 256 ; 1U << 8 %tmp1 = icmp uge i16 %tmp0, 256 ; 1U << 8
ret i1 %tmp1 ret i1 %tmp1
} }
; Second constant is not power of two ; Second constant is not power of two
define i1 @add_ugecmp_bad_i16_i8_c1notpoweroftwo(i16 %x) nounwind { define i1 @add_ugecmp_bad_i16_i8_c1notpoweroftwo(i16 %x) nounwind {
; CHECK-LABEL: add_ugecmp_bad_i16_i8_c1notpoweroftwo: ; CHECK-LABEL: add_ugecmp_bad_i16_i8_c1notpoweroftwo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #128 // =128 ; CHECK-NEXT: add w8, w0, #128
; CHECK-NEXT: and w8, w8, #0xffff ; CHECK-NEXT: and w8, w8, #0xffff
; CHECK-NEXT: cmp w8, #767 // =767 ; CHECK-NEXT: cmp w8, #767
; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: cset w0, hi
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i16 %x, 128 ; 1U << (8-1) %tmp0 = add i16 %x, 128 ; 1U << (8-1)
%tmp1 = icmp uge i16 %tmp0, 768 ; (1U << 8)) + (1U << (8+1)) %tmp1 = icmp uge i16 %tmp0, 768 ; (1U << 8)) + (1U << (8+1))
ret i1 %tmp1 ret i1 %tmp1
} }
; Magic check fails, 64 << 1 != 256 ; Magic check fails, 64 << 1 != 256
define i1 @add_ugecmp_bad_i16_i8_magic(i16 %x) nounwind { define i1 @add_ugecmp_bad_i16_i8_magic(i16 %x) nounwind {
; CHECK-LABEL: add_ugecmp_bad_i16_i8_magic: ; CHECK-LABEL: add_ugecmp_bad_i16_i8_magic:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #64 // =64 ; CHECK-NEXT: add w8, w0, #64
; CHECK-NEXT: and w8, w8, #0xffff ; CHECK-NEXT: and w8, w8, #0xffff
; CHECK-NEXT: cmp w8, #255 // =255 ; CHECK-NEXT: cmp w8, #255
; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: cset w0, hi
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i16 %x, 64 ; 1U << (8-1-1) %tmp0 = add i16 %x, 64 ; 1U << (8-1-1)
%tmp1 = icmp uge i16 %tmp0, 256 ; 1U << 8 %tmp1 = icmp uge i16 %tmp0, 256 ; 1U << 8
ret i1 %tmp1 ret i1 %tmp1
} }
; Bad 'destination type' ; Bad 'destination type'
define i1 @add_ugecmp_bad_i16_i4(i16 %x) nounwind { define i1 @add_ugecmp_bad_i16_i4(i16 %x) nounwind {
; CHECK-LABEL: add_ugecmp_bad_i16_i4: ; CHECK-LABEL: add_ugecmp_bad_i16_i4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #8 // =8 ; CHECK-NEXT: add w8, w0, #8
; CHECK-NEXT: and w8, w8, #0xffff ; CHECK-NEXT: and w8, w8, #0xffff
; CHECK-NEXT: cmp w8, #15 // =15 ; CHECK-NEXT: cmp w8, #15
; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: cset w0, hi
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i16 %x, 8 ; 1U << (4-1) %tmp0 = add i16 %x, 8 ; 1U << (4-1)
%tmp1 = icmp uge i16 %tmp0, 16 ; 1U << 4 %tmp1 = icmp uge i16 %tmp0, 16 ; 1U << 4
ret i1 %tmp1 ret i1 %tmp1
} }
; Bad storage type ; Bad storage type
define i1 @add_ugecmp_bad_i24_i8(i24 %x) nounwind { define i1 @add_ugecmp_bad_i24_i8(i24 %x) nounwind {
; CHECK-LABEL: add_ugecmp_bad_i24_i8: ; CHECK-LABEL: add_ugecmp_bad_i24_i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #128 // =128 ; CHECK-NEXT: add w8, w0, #128
; CHECK-NEXT: and w8, w8, #0xffffff ; CHECK-NEXT: and w8, w8, #0xffffff
; CHECK-NEXT: cmp w8, #255 // =255 ; CHECK-NEXT: cmp w8, #255
; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: cset w0, hi
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i24 %x, 128 ; 1U << (8-1) %tmp0 = add i24 %x, 128 ; 1U << (8-1)
%tmp1 = icmp uge i24 %tmp0, 256 ; 1U << 8 %tmp1 = icmp uge i24 %tmp0, 256 ; 1U << 8
ret i1 %tmp1 ret i1 %tmp1
} }
; Slightly more canonical variant ; Slightly more canonical variant
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llvm/test/CodeGen/AArch64/ldst-paired-aliasing.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu cortex-a53 < %s | FileCheck %s ; RUN: llc -mcpu cortex-a53 < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-i128:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-i128:128-n8:16:32:64-S128"
target triple = "aarch64--linux-gnu" target triple = "aarch64--linux-gnu"
declare void @f(i8*, i8*) declare void @f(i8*, i8*)
declare void @f2(i8*, i8*) declare void @f2(i8*, i8*)
declare void @_Z5setupv() declare void @_Z5setupv()
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) #3 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) #3
define i32 @main() local_unnamed_addr #1 { define i32 @main() local_unnamed_addr #1 {
; Make sure the stores happen in the correct order (the exact instructions could change). ; Make sure the stores happen in the correct order (the exact instructions could change).
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: // %bb.0: // %for.body.lr.ph.i.i.i.i.i.i63 ; CHECK: // %bb.0: // %for.body.lr.ph.i.i.i.i.i.i63
; CHECK-NEXT: sub sp, sp, #112 // =112 ; CHECK-NEXT: sub sp, sp, #112
; CHECK-NEXT: str x30, [sp, #96] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #96] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 112 ; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: bl _Z5setupv ; CHECK-NEXT: bl _Z5setupv
; CHECK-NEXT: movi v0.4s, #1 ; CHECK-NEXT: movi v0.4s, #1
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: add x0, sp, #48 // =48 ; CHECK-NEXT: add x0, sp, #48
; CHECK-NEXT: mov x1, sp ; CHECK-NEXT: mov x1, sp
; CHECK-NEXT: str xzr, [sp, #80] ; CHECK-NEXT: str xzr, [sp, #80]
; CHECK-NEXT: str w9, [sp, #80] ; CHECK-NEXT: str w9, [sp, #80]
; CHECK-NEXT: stp q0, q0, [sp, #48] ; CHECK-NEXT: stp q0, q0, [sp, #48]
; CHECK-NEXT: ldr w8, [sp, #48] ; CHECK-NEXT: ldr w8, [sp, #48]
; CHECK-NEXT: cmp w8, #1 // =1 ; CHECK-NEXT: cmp w8, #1
; CHECK-NEXT: b.ne .LBB0_2 ; CHECK-NEXT: b.ne .LBB0_2
; CHECK-NEXT: // %bb.1: // %for.inc ; CHECK-NEXT: // %bb.1: // %for.inc
; CHECK-NEXT: bl f ; CHECK-NEXT: bl f
; CHECK-NEXT: b .LBB0_3 ; CHECK-NEXT: b .LBB0_3
; CHECK-NEXT: .LBB0_2: // %if.then ; CHECK-NEXT: .LBB0_2: // %if.then
; CHECK-NEXT: bl f2 ; CHECK-NEXT: bl f2
; CHECK-NEXT: .LBB0_3: // %common.ret ; CHECK-NEXT: .LBB0_3: // %common.ret
; CHECK-NEXT: ldr x30, [sp, #96] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #96] // 8-byte Folded Reload
; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: add sp, sp, #112 // =112 ; CHECK-NEXT: add sp, sp, #112
; CHECK-NEXT: ret ; CHECK-NEXT: ret
for.body.lr.ph.i.i.i.i.i.i63: for.body.lr.ph.i.i.i.i.i.i63:
%b1 = alloca [10 x i32], align 16 %b1 = alloca [10 x i32], align 16
%x0 = bitcast [10 x i32]* %b1 to i8* %x0 = bitcast [10 x i32]* %b1 to i8*
%b2 = alloca [10 x i32], align 16 %b2 = alloca [10 x i32], align 16
%x1 = bitcast [10 x i32]* %b2 to i8* %x1 = bitcast [10 x i32]* %b2 to i8*
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llvm/test/CodeGen/AArch64/logical_shifted_reg.ll

Show First 20 Lines • Show All 260 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ldr x10, [x10] ; CHECK-NEXT: ldr x10, [x10]
; CHECK-NEXT: tst x9, x10 ; CHECK-NEXT: tst x9, x10
; CHECK-NEXT: b.gt .LBB2_4 ; CHECK-NEXT: b.gt .LBB2_4
; CHECK-NEXT: // %bb.1: // %test2 ; CHECK-NEXT: // %bb.1: // %test2
; CHECK-NEXT: tst x9, x10, lsl #63 ; CHECK-NEXT: tst x9, x10, lsl #63
; CHECK-NEXT: b.lt .LBB2_4 ; CHECK-NEXT: b.lt .LBB2_4
; CHECK-NEXT: // %bb.2: // %test3 ; CHECK-NEXT: // %bb.2: // %test3
; CHECK-NEXT: and x10, x9, x10, asr #12 ; CHECK-NEXT: and x10, x9, x10, asr #12
; CHECK-NEXT: cmp x10, #1 // =1 ; CHECK-NEXT: cmp x10, #1
; CHECK-NEXT: b.ge .LBB2_4 ; CHECK-NEXT: b.ge .LBB2_4
; CHECK-NEXT: // %bb.3: // %other_exit ; CHECK-NEXT: // %bb.3: // %other_exit
; CHECK-NEXT: str x9, [x8] ; CHECK-NEXT: str x9, [x8]
; CHECK-NEXT: .LBB2_4: // %common.ret ; CHECK-NEXT: .LBB2_4: // %common.ret
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val1 = load i64, i64* @var1_64 %val1 = load i64, i64* @var1_64
%val2 = load i64, i64* @var2_64 %val2 = load i64, i64* @var2_64
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llvm/test/CodeGen/AArch64/ls64-inline-asm.ll

Show All 36 Linesentry:
%val = load i512, i512* %incast, align 8 %val = load i512, i512* %incast, align 8
call void asm sideeffect "st64b $0,[$1]", "r,r,~{memory}"(i512 %val, i8* %addr) call void asm sideeffect "st64b $0,[$1]", "r,r,~{memory}"(i512 %val, i8* %addr)
ret void ret void
} }
define void @store2(i32* %in, i8* %addr) { define void @store2(i32* %in, i8* %addr) {
; CHECK-LABEL: store2: ; CHECK-LABEL: store2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #64 // =64 ; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: ldpsw x2, x3, [x0] ; CHECK-NEXT: ldpsw x2, x3, [x0]
; CHECK-NEXT: ldrsw x4, [x0, #16] ; CHECK-NEXT: ldrsw x4, [x0, #16]
; CHECK-NEXT: ldrsw x5, [x0, #64] ; CHECK-NEXT: ldrsw x5, [x0, #64]
; CHECK-NEXT: ldrsw x6, [x0, #100] ; CHECK-NEXT: ldrsw x6, [x0, #100]
; CHECK-NEXT: ldrsw x7, [x0, #144] ; CHECK-NEXT: ldrsw x7, [x0, #144]
; CHECK-NEXT: ldrsw x8, [x0, #196] ; CHECK-NEXT: ldrsw x8, [x0, #196]
; CHECK-NEXT: ldrsw x9, [x0, #256] ; CHECK-NEXT: ldrsw x9, [x0, #256]
; CHECK-NEXT: //APP ; CHECK-NEXT: //APP
; CHECK-NEXT: st64b x2, [x1] ; CHECK-NEXT: st64b x2, [x1]
; CHECK-NEXT: //NO_APP ; CHECK-NEXT: //NO_APP
; CHECK-NEXT: add sp, sp, #64 // =64 ; CHECK-NEXT: add sp, sp, #64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = load i32, i32* %in, align 4 %0 = load i32, i32* %in, align 4
%conv = sext i32 %0 to i64 %conv = sext i32 %0 to i64
%arrayidx1 = getelementptr inbounds i32, i32* %in, i64 1 %arrayidx1 = getelementptr inbounds i32, i32* %in, i64 1
%1 = load i32, i32* %arrayidx1, align 4 %1 = load i32, i32* %arrayidx1, align 4
%conv2 = sext i32 %1 to i64 %conv2 = sext i32 %1 to i64
%arrayidx4 = getelementptr inbounds i32, i32* %in, i64 4 %arrayidx4 = getelementptr inbounds i32, i32* %in, i64 4
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llvm/test/CodeGen/AArch64/machine-licm-sink-instr.ll

Show All 10 Lines
; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w21, -24 ; CHECK-NEXT: .cfi_offset w21, -24
; CHECK-NEXT: .cfi_offset w30, -32 ; CHECK-NEXT: .cfi_offset w30, -32
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: cmp w0, #1 // =1 ; CHECK-NEXT: cmp w0, #1
; CHECK-NEXT: b.lt .LBB0_3 ; CHECK-NEXT: b.lt .LBB0_3
; CHECK-NEXT: // %bb.1: // %for.body.preheader ; CHECK-NEXT: // %bb.1: // %for.body.preheader
; CHECK-NEXT: adrp x8, A ; CHECK-NEXT: adrp x8, A
; CHECK-NEXT: ldr w21, [x8, :lo12:A] ; CHECK-NEXT: ldr w21, [x8, :lo12:A]
; CHECK-NEXT: mov w20, w19 ; CHECK-NEXT: mov w20, w19
; CHECK-NEXT: .LBB0_2: // %for.body ; CHECK-NEXT: .LBB0_2: // %for.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: mov w0, w21 ; CHECK-NEXT: mov w0, w21
; CHECK-NEXT: bl _Z3usei ; CHECK-NEXT: bl _Z3usei
; CHECK-NEXT: subs w19, w19, #1 // =1 ; CHECK-NEXT: subs w19, w19, #1
; CHECK-NEXT: sdiv w20, w20, w0 ; CHECK-NEXT: sdiv w20, w20, w0
; CHECK-NEXT: b.ne .LBB0_2 ; CHECK-NEXT: b.ne .LBB0_2
; CHECK-NEXT: b .LBB0_4 ; CHECK-NEXT: b .LBB0_4
; CHECK-NEXT: .LBB0_3: ; CHECK-NEXT: .LBB0_3:
; CHECK-NEXT: mov w20, w19 ; CHECK-NEXT: mov w20, w19
; CHECK-NEXT: .LBB0_4: // %for.cond.cleanup ; CHECK-NEXT: .LBB0_4: // %for.cond.cleanup
; CHECK-NEXT: mov w0, w20 ; CHECK-NEXT: mov w0, w20
; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
Show All 27 Lines
; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w21, -24 ; CHECK-NEXT: .cfi_offset w21, -24
; CHECK-NEXT: .cfi_offset w30, -32 ; CHECK-NEXT: .cfi_offset w30, -32
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: cmp w0, #1 // =1 ; CHECK-NEXT: cmp w0, #1
; CHECK-NEXT: b.lt .LBB1_3 ; CHECK-NEXT: b.lt .LBB1_3
; CHECK-NEXT: // %bb.1: // %for.body.preheader ; CHECK-NEXT: // %bb.1: // %for.body.preheader
; CHECK-NEXT: adrp x8, A ; CHECK-NEXT: adrp x8, A
; CHECK-NEXT: ldr w20, [x8, :lo12:A] ; CHECK-NEXT: ldr w20, [x8, :lo12:A]
; CHECK-NEXT: mov w0, w19 ; CHECK-NEXT: mov w0, w19
; CHECK-NEXT: bl _Z3usei ; CHECK-NEXT: bl _Z3usei
; CHECK-NEXT: mov w21, w19 ; CHECK-NEXT: mov w21, w19
; CHECK-NEXT: .LBB1_2: // %for.body ; CHECK-NEXT: .LBB1_2: // %for.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: mov w0, w20 ; CHECK-NEXT: mov w0, w20
; CHECK-NEXT: bl _Z3usei ; CHECK-NEXT: bl _Z3usei
; CHECK-NEXT: subs w19, w19, #1 // =1 ; CHECK-NEXT: subs w19, w19, #1
; CHECK-NEXT: sdiv w21, w21, w0 ; CHECK-NEXT: sdiv w21, w21, w0
; CHECK-NEXT: b.ne .LBB1_2 ; CHECK-NEXT: b.ne .LBB1_2
; CHECK-NEXT: b .LBB1_4 ; CHECK-NEXT: b .LBB1_4
; CHECK-NEXT: .LBB1_3: ; CHECK-NEXT: .LBB1_3:
; CHECK-NEXT: mov w21, w19 ; CHECK-NEXT: mov w21, w19
; CHECK-NEXT: .LBB1_4: // %for.cond.cleanup ; CHECK-NEXT: .LBB1_4: // %for.cond.cleanup
; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov w0, w21 ; CHECK-NEXT: mov w0, w21
Show All 28 Lines
; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill ; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w21, -24 ; CHECK-NEXT: .cfi_offset w21, -24
; CHECK-NEXT: .cfi_offset w30, -32 ; CHECK-NEXT: .cfi_offset w30, -32
; CHECK-NEXT: mov w19, w1 ; CHECK-NEXT: mov w19, w1
; CHECK-NEXT: cmp w1, #1 // =1 ; CHECK-NEXT: cmp w1, #1
; CHECK-NEXT: b.lt .LBB2_3 ; CHECK-NEXT: b.lt .LBB2_3
; CHECK-NEXT: // %bb.1: // %for.body.preheader ; CHECK-NEXT: // %bb.1: // %for.body.preheader
; CHECK-NEXT: adrp x8, A ; CHECK-NEXT: adrp x8, A
; CHECK-NEXT: ldr w20, [x8, :lo12:A] ; CHECK-NEXT: ldr w20, [x8, :lo12:A]
; CHECK-NEXT: mov w8, #42 ; CHECK-NEXT: mov w8, #42
; CHECK-NEXT: mov w21, w19 ; CHECK-NEXT: mov w21, w19
; CHECK-NEXT: str w8, [x0] ; CHECK-NEXT: str w8, [x0]
; CHECK-NEXT: .LBB2_2: // %for.body ; CHECK-NEXT: .LBB2_2: // %for.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: mov w0, w20 ; CHECK-NEXT: mov w0, w20
; CHECK-NEXT: bl _Z3usei ; CHECK-NEXT: bl _Z3usei
; CHECK-NEXT: subs w19, w19, #1 // =1 ; CHECK-NEXT: subs w19, w19, #1
; CHECK-NEXT: sdiv w21, w21, w0 ; CHECK-NEXT: sdiv w21, w21, w0
; CHECK-NEXT: b.ne .LBB2_2 ; CHECK-NEXT: b.ne .LBB2_2
; CHECK-NEXT: b .LBB2_4 ; CHECK-NEXT: b .LBB2_4
; CHECK-NEXT: .LBB2_3: ; CHECK-NEXT: .LBB2_3:
; CHECK-NEXT: mov w21, w19 ; CHECK-NEXT: mov w21, w19
; CHECK-NEXT: .LBB2_4: // %for.cond.cleanup ; CHECK-NEXT: .LBB2_4: // %for.cond.cleanup
; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov w0, w21 ; CHECK-NEXT: mov w0, w21
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llvm/test/CodeGen/AArch64/machine-outliner-thunk.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -enable-machine-outliner -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -enable-machine-outliner -verify-machineinstrs | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-pc-linux-gnu" target triple = "aarch64-pc-linux-gnu"
declare i32 @thunk_called_fn(i32, i32, i32, i32) declare i32 @thunk_called_fn(i32, i32, i32, i32)
define i32 @a() { define i32 @a() {
; CHECK-LABEL: a: ; CHECK-LABEL: a:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: bl [[OUTLINED_DIRECT:OUTLINED_FUNCTION_[0-9]+]] ; CHECK-NEXT: bl [[OUTLINED_DIRECT:OUTLINED_FUNCTION_[0-9]+]]
; CHECK-NEXT: add w0, w0, #8 // =8 ; CHECK-NEXT: add w0, w0, #8
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%call = tail call i32 @thunk_called_fn(i32 1, i32 2, i32 3, i32 4) %call = tail call i32 @thunk_called_fn(i32 1, i32 2, i32 3, i32 4)
%cx = add i32 %call, 8 %cx = add i32 %call, 8
ret i32 %cx ret i32 %cx
} }
define i32 @b() { define i32 @b() {
; CHECK-LABEL: b: ; CHECK-LABEL: b:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: bl [[OUTLINED_DIRECT]] ; CHECK-NEXT: bl [[OUTLINED_DIRECT]]
; CHECK-NEXT: add w0, w0, #88 // =88 ; CHECK-NEXT: add w0, w0, #88
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%call = tail call i32 @thunk_called_fn(i32 1, i32 2, i32 3, i32 4) %call = tail call i32 @thunk_called_fn(i32 1, i32 2, i32 3, i32 4)
%cx = add i32 %call, 88 %cx = add i32 %call, 88
ret i32 %cx ret i32 %cx
} }
define hidden i32 @c(i32 (i32, i32, i32, i32)* %fptr) { define hidden i32 @c(i32 (i32, i32, i32, i32)* %fptr) {
; CHECK-LABEL: c: ; CHECK-LABEL: c:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: bl [[OUTLINED_INDIRECT:OUTLINED_FUNCTION_[0-9]+]] ; CHECK-NEXT: bl [[OUTLINED_INDIRECT:OUTLINED_FUNCTION_[0-9]+]]
; CHECK-NEXT: add w0, w0, #8 // =8 ; CHECK-NEXT: add w0, w0, #8
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%call = tail call i32 %fptr(i32 1, i32 2, i32 3, i32 4) %call = tail call i32 %fptr(i32 1, i32 2, i32 3, i32 4)
%add = add nsw i32 %call, 8 %add = add nsw i32 %call, 8
ret i32 %add ret i32 %add
} }
define hidden i32 @d(i32 (i32, i32, i32, i32)* %fptr) { define hidden i32 @d(i32 (i32, i32, i32, i32)* %fptr) {
; CHECK-LABEL: d: ; CHECK-LABEL: d:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: bl [[OUTLINED_INDIRECT]] ; CHECK-NEXT: bl [[OUTLINED_INDIRECT]]
; CHECK-NEXT: add w0, w0, #88 // =88 ; CHECK-NEXT: add w0, w0, #88
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%call = tail call i32 %fptr(i32 1, i32 2, i32 3, i32 4) %call = tail call i32 %fptr(i32 1, i32 2, i32 3, i32 4)
%add = add nsw i32 %call, 88 %add = add nsw i32 %call, 88
ret i32 %add ret i32 %add
} }
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llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
; CHECK-SELDAG-NEXT: rev64 v1.4s, v1.4s ; CHECK-SELDAG-NEXT: rev64 v1.4s, v1.4s
; CHECK-SELDAG-NEXT: rev64 v2.4s, v0.4s ; CHECK-SELDAG-NEXT: rev64 v2.4s, v0.4s
; CHECK-SELDAG-NEXT: ext v0.16b, v1.16b, v1.16b, #8 ; CHECK-SELDAG-NEXT: ext v0.16b, v1.16b, v1.16b, #8
; CHECK-SELDAG-NEXT: ext v1.16b, v2.16b, v2.16b, #8 ; CHECK-SELDAG-NEXT: ext v1.16b, v2.16b, v2.16b, #8
; CHECK-SELDAG-NEXT: ret ; CHECK-SELDAG-NEXT: ret
; ;
; CHECK-FASTISEL-LABEL: reverse_v8i32: ; CHECK-FASTISEL-LABEL: reverse_v8i32:
; CHECK-FASTISEL: // %bb.0: ; CHECK-FASTISEL: // %bb.0:
; CHECK-FASTISEL-NEXT: sub sp, sp, #16 // =16 ; CHECK-FASTISEL-NEXT: sub sp, sp, #16
; CHECK-FASTISEL-NEXT: str q1, [sp] // 16-byte Folded Spill ; CHECK-FASTISEL-NEXT: str q1, [sp] // 16-byte Folded Spill
; CHECK-FASTISEL-NEXT: mov v1.16b, v0.16b ; CHECK-FASTISEL-NEXT: mov v1.16b, v0.16b
; CHECK-FASTISEL-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-FASTISEL-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-FASTISEL-NEXT: rev64 v0.4s, v0.4s ; CHECK-FASTISEL-NEXT: rev64 v0.4s, v0.4s
; CHECK-FASTISEL-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-FASTISEL-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-FASTISEL-NEXT: rev64 v1.4s, v1.4s ; CHECK-FASTISEL-NEXT: rev64 v1.4s, v1.4s
; CHECK-FASTISEL-NEXT: ext v1.16b, v1.16b, v1.16b, #8 ; CHECK-FASTISEL-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-FASTISEL-NEXT: add sp, sp, #16 // =16 ; CHECK-FASTISEL-NEXT: add sp, sp, #16
; CHECK-FASTISEL-NEXT: ret ; CHECK-FASTISEL-NEXT: ret
%res = call <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32> %a) %res = call <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32> %a)
ret <8 x i32> %res ret <8 x i32> %res
} }
; Verify splitvec type legalisation works as expected. ; Verify splitvec type legalisation works as expected.
define <16 x float> @reverse_v16f32(<16 x float> %a) #0 { define <16 x float> @reverse_v16f32(<16 x float> %a) #0 {
; CHECK-SELDAG-LABEL: reverse_v16f32: ; CHECK-SELDAG-LABEL: reverse_v16f32:
; CHECK-SELDAG: // %bb.0: ; CHECK-SELDAG: // %bb.0:
; CHECK-SELDAG-NEXT: rev64 v3.4s, v3.4s ; CHECK-SELDAG-NEXT: rev64 v3.4s, v3.4s
; CHECK-SELDAG-NEXT: rev64 v2.4s, v2.4s ; CHECK-SELDAG-NEXT: rev64 v2.4s, v2.4s
; CHECK-SELDAG-NEXT: rev64 v4.4s, v1.4s ; CHECK-SELDAG-NEXT: rev64 v4.4s, v1.4s
; CHECK-SELDAG-NEXT: rev64 v5.4s, v0.4s ; CHECK-SELDAG-NEXT: rev64 v5.4s, v0.4s
; CHECK-SELDAG-NEXT: ext v0.16b, v3.16b, v3.16b, #8 ; CHECK-SELDAG-NEXT: ext v0.16b, v3.16b, v3.16b, #8
; CHECK-SELDAG-NEXT: ext v1.16b, v2.16b, v2.16b, #8 ; CHECK-SELDAG-NEXT: ext v1.16b, v2.16b, v2.16b, #8
; CHECK-SELDAG-NEXT: ext v2.16b, v4.16b, v4.16b, #8 ; CHECK-SELDAG-NEXT: ext v2.16b, v4.16b, v4.16b, #8
; CHECK-SELDAG-NEXT: ext v3.16b, v5.16b, v5.16b, #8 ; CHECK-SELDAG-NEXT: ext v3.16b, v5.16b, v5.16b, #8
; CHECK-SELDAG-NEXT: ret ; CHECK-SELDAG-NEXT: ret
; ;
; CHECK-FASTISEL-LABEL: reverse_v16f32: ; CHECK-FASTISEL-LABEL: reverse_v16f32:
; CHECK-FASTISEL: // %bb.0: ; CHECK-FASTISEL: // %bb.0:
; CHECK-FASTISEL-NEXT: sub sp, sp, #32 // =32 ; CHECK-FASTISEL-NEXT: sub sp, sp, #32
; CHECK-FASTISEL-NEXT: str q3, [sp, #16] // 16-byte Folded Spill ; CHECK-FASTISEL-NEXT: str q3, [sp, #16] // 16-byte Folded Spill
; CHECK-FASTISEL-NEXT: str q2, [sp] // 16-byte Folded Spill ; CHECK-FASTISEL-NEXT: str q2, [sp] // 16-byte Folded Spill
; CHECK-FASTISEL-NEXT: mov v2.16b, v1.16b ; CHECK-FASTISEL-NEXT: mov v2.16b, v1.16b
; CHECK-FASTISEL-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-FASTISEL-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-FASTISEL-NEXT: mov v3.16b, v0.16b ; CHECK-FASTISEL-NEXT: mov v3.16b, v0.16b
; CHECK-FASTISEL-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-FASTISEL-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-FASTISEL-NEXT: rev64 v0.4s, v0.4s ; CHECK-FASTISEL-NEXT: rev64 v0.4s, v0.4s
; CHECK-FASTISEL-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-FASTISEL-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-FASTISEL-NEXT: rev64 v1.4s, v1.4s ; CHECK-FASTISEL-NEXT: rev64 v1.4s, v1.4s
; CHECK-FASTISEL-NEXT: ext v1.16b, v1.16b, v1.16b, #8 ; CHECK-FASTISEL-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-FASTISEL-NEXT: rev64 v2.4s, v2.4s ; CHECK-FASTISEL-NEXT: rev64 v2.4s, v2.4s
; CHECK-FASTISEL-NEXT: ext v2.16b, v2.16b, v2.16b, #8 ; CHECK-FASTISEL-NEXT: ext v2.16b, v2.16b, v2.16b, #8
; CHECK-FASTISEL-NEXT: rev64 v3.4s, v3.4s ; CHECK-FASTISEL-NEXT: rev64 v3.4s, v3.4s
; CHECK-FASTISEL-NEXT: ext v3.16b, v3.16b, v3.16b, #8 ; CHECK-FASTISEL-NEXT: ext v3.16b, v3.16b, v3.16b, #8
; CHECK-FASTISEL-NEXT: add sp, sp, #32 // =32 ; CHECK-FASTISEL-NEXT: add sp, sp, #32
; CHECK-FASTISEL-NEXT: ret ; CHECK-FASTISEL-NEXT: ret
%res = call <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float> %a) %res = call <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float> %a)
ret <16 x float> %res ret <16 x float> %res
} }
declare <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8>) declare <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8>)
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llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

Show All 26 Lines
; Ensure index is clamped when we cannot prove it's less than VL-1. ; Ensure index is clamped when we cannot prove it's less than VL-1.
define <vscale x 16 x i8> @splice_nxv16i8_clamped_idx(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 { define <vscale x 16 x i8> @splice_nxv16i8_clamped_idx(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv16i8_clamped_idx: ; CHECK-LABEL: splice_nxv16i8_clamped_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: rdvl x9, #1 ; CHECK-NEXT: rdvl x9, #1
; CHECK-NEXT: sub x9, x9, #1 // =1 ; CHECK-NEXT: sub x9, x9, #1
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w10, #16 ; CHECK-NEXT: mov w10, #16
; CHECK-NEXT: cmp x9, #16 // =16 ; CHECK-NEXT: cmp x9, #16
; CHECK-NEXT: st1b { z0.b }, p0, [sp] ; CHECK-NEXT: st1b { z0.b }, p0, [sp]
; CHECK-NEXT: st1b { z1.b }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1b { z1.b }, p0, [x8, #1, mul vl]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8, x9] ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8, x9]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 16) %res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 16)
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; Ensure index is clamped when we cannot prove it's less than VL-1. ; Ensure index is clamped when we cannot prove it's less than VL-1.
define <vscale x 8 x i16> @splice_nxv8i16_clamped_idx(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 { define <vscale x 8 x i16> @splice_nxv8i16_clamped_idx(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv8i16_clamped_idx: ; CHECK-LABEL: splice_nxv8i16_clamped_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: cnth x10 ; CHECK-NEXT: cnth x10
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w9, #8 ; CHECK-NEXT: mov w9, #8
; CHECK-NEXT: cmp x10, #8 // =8 ; CHECK-NEXT: cmp x10, #8
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl]
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, x9, lsl #1] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, x9, lsl #1]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 8) %res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 8)
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; Ensure index is clamped when we cannot prove it's less than VL-1. ; Ensure index is clamped when we cannot prove it's less than VL-1.
define <vscale x 4 x i32> @splice_nxv4i32_clamped_idx(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 { define <vscale x 4 x i32> @splice_nxv4i32_clamped_idx(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv4i32_clamped_idx: ; CHECK-LABEL: splice_nxv4i32_clamped_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: cntw x10 ; CHECK-NEXT: cntw x10
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w9, #4 ; CHECK-NEXT: mov w9, #4
; CHECK-NEXT: cmp x10, #4 // =4 ; CHECK-NEXT: cmp x10, #4
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl]
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, x9, lsl #2] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, x9, lsl #2]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 4) %res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 4)
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; Ensure index is clamped when we cannot prove it's less than VL-1. ; Ensure index is clamped when we cannot prove it's less than VL-1.
define <vscale x 2 x i64> @splice_nxv2i64_clamped_idx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 { define <vscale x 2 x i64> @splice_nxv2i64_clamped_idx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv2i64_clamped_idx: ; CHECK-LABEL: splice_nxv2i64_clamped_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: cntd x10 ; CHECK-NEXT: cntd x10
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w9, #2 ; CHECK-NEXT: mov w9, #2
; CHECK-NEXT: cmp x10, #2 // =2 ; CHECK-NEXT: cmp x10, #2
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl]
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, x9, lsl #3] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, x9, lsl #3]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 2) %res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 2)
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; Ensure index is clamped when we cannot prove it's less than VL-1. ; Ensure index is clamped when we cannot prove it's less than VL-1.
define <vscale x 2 x half> @splice_nxv2f16_last_idx(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 { define <vscale x 2 x half> @splice_nxv2f16_last_idx(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {
; CHECK-LABEL: splice_nxv2f16_last_idx: ; CHECK-LABEL: splice_nxv2f16_last_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: cntd x10 ; CHECK-NEXT: cntd x10
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: mov w9, #2 ; CHECK-NEXT: mov w9, #2
; CHECK-NEXT: cmp x10, #2 // =2 ; CHECK-NEXT: cmp x10, #2
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: ptrue p1.b ; CHECK-NEXT: ptrue p1.b
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl]
; CHECK-NEXT: lsl x9, x9, #3 ; CHECK-NEXT: lsl x9, x9, #3
; CHECK-NEXT: ld1b { z0.b }, p1/z, [x8, x9] ; CHECK-NEXT: ld1b { z0.b }, p1/z, [x8, x9]
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; Ensure index is clamped when we cannot prove it's less than VL-1. ; Ensure index is clamped when we cannot prove it's less than VL-1.
define <vscale x 4 x half> @splice_nxv4f16_last_idx(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 { define <vscale x 4 x half> @splice_nxv4f16_last_idx(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {
; CHECK-LABEL: splice_nxv4f16_last_idx: ; CHECK-LABEL: splice_nxv4f16_last_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: cntw x10 ; CHECK-NEXT: cntw x10
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: mov w9, #4 ; CHECK-NEXT: mov w9, #4
; CHECK-NEXT: cmp x10, #4 // =4 ; CHECK-NEXT: cmp x10, #4
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: ptrue p1.b ; CHECK-NEXT: ptrue p1.b
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl]
; CHECK-NEXT: lsl x9, x9, #2 ; CHECK-NEXT: lsl x9, x9, #2
; CHECK-NEXT: ld1b { z0.b }, p1/z, [x8, x9] ; CHECK-NEXT: ld1b { z0.b }, p1/z, [x8, x9]
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; Ensure index is clamped when we cannot prove it's less than VL-1. ; Ensure index is clamped when we cannot prove it's less than VL-1.
define <vscale x 8 x half> @splice_nxv8f16_clamped_idx(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 { define <vscale x 8 x half> @splice_nxv8f16_clamped_idx(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
; CHECK-LABEL: splice_nxv8f16_clamped_idx: ; CHECK-LABEL: splice_nxv8f16_clamped_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: cnth x10 ; CHECK-NEXT: cnth x10
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w9, #8 ; CHECK-NEXT: mov w9, #8
; CHECK-NEXT: cmp x10, #8 // =8 ; CHECK-NEXT: cmp x10, #8
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl]
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, x9, lsl #1] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, x9, lsl #1]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 8) %res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 8)
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; Ensure index is clamped when we cannot prove it's less than VL-1. ; Ensure index is clamped when we cannot prove it's less than VL-1.
define <vscale x 2 x float> @splice_nxv2f32_last_idx(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 { define <vscale x 2 x float> @splice_nxv2f32_last_idx(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 {
; CHECK-LABEL: splice_nxv2f32_last_idx: ; CHECK-LABEL: splice_nxv2f32_last_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: cntd x10 ; CHECK-NEXT: cntd x10
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: mov w9, #2 ; CHECK-NEXT: mov w9, #2
; CHECK-NEXT: cmp x10, #2 // =2 ; CHECK-NEXT: cmp x10, #2
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: ptrue p1.b ; CHECK-NEXT: ptrue p1.b
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl]
; CHECK-NEXT: lsl x9, x9, #3 ; CHECK-NEXT: lsl x9, x9, #3
; CHECK-NEXT: ld1b { z0.b }, p1/z, [x8, x9] ; CHECK-NEXT: ld1b { z0.b }, p1/z, [x8, x9]
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; Ensure index is clamped when we cannot prove it's less than VL-1. ; Ensure index is clamped when we cannot prove it's less than VL-1.
define <vscale x 4 x float> @splice_nxv4f32_clamped_idx(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 { define <vscale x 4 x float> @splice_nxv4f32_clamped_idx(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
; CHECK-LABEL: splice_nxv4f32_clamped_idx: ; CHECK-LABEL: splice_nxv4f32_clamped_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: cntw x10 ; CHECK-NEXT: cntw x10
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w9, #4 ; CHECK-NEXT: mov w9, #4
; CHECK-NEXT: cmp x10, #4 // =4 ; CHECK-NEXT: cmp x10, #4
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl]
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, x9, lsl #2] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, x9, lsl #2]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 4) %res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 4)
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; Ensure index is clamped when we cannot prove it's less than VL-1. ; Ensure index is clamped when we cannot prove it's less than VL-1.
define <vscale x 2 x double> @splice_nxv2f64_clamped_idx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 { define <vscale x 2 x double> @splice_nxv2f64_clamped_idx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
; CHECK-LABEL: splice_nxv2f64_clamped_idx: ; CHECK-LABEL: splice_nxv2f64_clamped_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: cntd x10 ; CHECK-NEXT: cntd x10
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w9, #2 ; CHECK-NEXT: mov w9, #2
; CHECK-NEXT: cmp x10, #2 // =2 ; CHECK-NEXT: cmp x10, #2
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl]
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, x9, lsl #3] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, x9, lsl #3]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 2) %res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 2)
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; Verify splitvec type legalisation works as expected. ; Verify splitvec type legalisation works as expected.
define <vscale x 16 x float> @splice_nxv16f32_clamped_idx(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 { define <vscale x 16 x float> @splice_nxv16f32_clamped_idx(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 {
; CHECK-LABEL: splice_nxv16f32_clamped_idx: ; CHECK-LABEL: splice_nxv16f32_clamped_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-8 ; CHECK-NEXT: addvl sp, sp, #-8
; CHECK-NEXT: rdvl x10, #1 ; CHECK-NEXT: rdvl x10, #1
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w9, #16 ; CHECK-NEXT: mov w9, #16
; CHECK-NEXT: cmp x10, #16 // =16 ; CHECK-NEXT: cmp x10, #16
; CHECK-NEXT: st1w { z3.s }, p0, [x8, #3, mul vl] ; CHECK-NEXT: st1w { z3.s }, p0, [x8, #3, mul vl]
; CHECK-NEXT: st1w { z2.s }, p0, [x8, #2, mul vl] ; CHECK-NEXT: st1w { z2.s }, p0, [x8, #2, mul vl]
; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: st1w { z7.s }, p0, [x8, #7, mul vl] ; CHECK-NEXT: st1w { z7.s }, p0, [x8, #7, mul vl]
; CHECK-NEXT: st1w { z4.s }, p0, [x8, #4, mul vl] ; CHECK-NEXT: st1w { z4.s }, p0, [x8, #4, mul vl]
; CHECK-NEXT: st1w { z5.s }, p0, [x8, #5, mul vl] ; CHECK-NEXT: st1w { z5.s }, p0, [x8, #5, mul vl]
; CHECK-NEXT: st1w { z6.s }, p0, [x8, #6, mul vl] ; CHECK-NEXT: st1w { z6.s }, p0, [x8, #6, mul vl]
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; CHECK-LABEL: splice_nxv16i8_clamped: ; CHECK-LABEL: splice_nxv16i8_clamped:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: rdvl x9, #1 ; CHECK-NEXT: rdvl x9, #1
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w10, #17 ; CHECK-NEXT: mov w10, #17
; CHECK-NEXT: cmp x9, #17 // =17 ; CHECK-NEXT: cmp x9, #17
; CHECK-NEXT: st1b { z0.b }, p0, [sp] ; CHECK-NEXT: st1b { z0.b }, p0, [sp]
; CHECK-NEXT: st1b { z1.b }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1b { z1.b }, p0, [x8, #1, mul vl]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: addvl x8, x8, #1 ; CHECK-NEXT: addvl x8, x8, #1
; CHECK-NEXT: sub x8, x8, x9 ; CHECK-NEXT: sub x8, x8, x9
; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8] ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
Show All 38 Lines
; CHECK-LABEL: splice_nxv8i16_clamped: ; CHECK-LABEL: splice_nxv8i16_clamped:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: rdvl x9, #1 ; CHECK-NEXT: rdvl x9, #1
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w10, #18 ; CHECK-NEXT: mov w10, #18
; CHECK-NEXT: cmp x9, #18 // =18 ; CHECK-NEXT: cmp x9, #18
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: addvl x8, x8, #1 ; CHECK-NEXT: addvl x8, x8, #1
; CHECK-NEXT: sub x8, x8, x9 ; CHECK-NEXT: sub x8, x8, x9
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
Show All 38 Lines
; CHECK-LABEL: splice_nxv4i32_clamped: ; CHECK-LABEL: splice_nxv4i32_clamped:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: rdvl x9, #1 ; CHECK-NEXT: rdvl x9, #1
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w10, #20 ; CHECK-NEXT: mov w10, #20
; CHECK-NEXT: cmp x9, #20 // =20 ; CHECK-NEXT: cmp x9, #20
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: addvl x8, x8, #1 ; CHECK-NEXT: addvl x8, x8, #1
; CHECK-NEXT: sub x8, x8, x9 ; CHECK-NEXT: sub x8, x8, x9
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-LABEL: splice_nxv2i64_clamped: ; CHECK-LABEL: splice_nxv2i64_clamped:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: rdvl x9, #1 ; CHECK-NEXT: rdvl x9, #1
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w10, #24 ; CHECK-NEXT: mov w10, #24
; CHECK-NEXT: cmp x9, #24 // =24 ; CHECK-NEXT: cmp x9, #24
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: addvl x8, x8, #1 ; CHECK-NEXT: addvl x8, x8, #1
; CHECK-NEXT: sub x8, x8, x9 ; CHECK-NEXT: sub x8, x8, x9
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-LABEL: splice_nxv8f16_clamped: ; CHECK-LABEL: splice_nxv8f16_clamped:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: rdvl x9, #1 ; CHECK-NEXT: rdvl x9, #1
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w10, #18 ; CHECK-NEXT: mov w10, #18
; CHECK-NEXT: cmp x9, #18 // =18 ; CHECK-NEXT: cmp x9, #18
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: addvl x8, x8, #1 ; CHECK-NEXT: addvl x8, x8, #1
; CHECK-NEXT: sub x8, x8, x9 ; CHECK-NEXT: sub x8, x8, x9
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-LABEL: splice_nxv4f32_clamped: ; CHECK-LABEL: splice_nxv4f32_clamped:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: rdvl x9, #1 ; CHECK-NEXT: rdvl x9, #1
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w10, #20 ; CHECK-NEXT: mov w10, #20
; CHECK-NEXT: cmp x9, #20 // =20 ; CHECK-NEXT: cmp x9, #20
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: addvl x8, x8, #1 ; CHECK-NEXT: addvl x8, x8, #1
; CHECK-NEXT: sub x8, x8, x9 ; CHECK-NEXT: sub x8, x8, x9
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
Show All 38 Lines
; CHECK-LABEL: splice_nxv2f64_clamped: ; CHECK-LABEL: splice_nxv2f64_clamped:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: rdvl x9, #1 ; CHECK-NEXT: rdvl x9, #1
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w10, #24 ; CHECK-NEXT: mov w10, #24
; CHECK-NEXT: cmp x9, #24 // =24 ; CHECK-NEXT: cmp x9, #24
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: addvl x8, x8, #1 ; CHECK-NEXT: addvl x8, x8, #1
; CHECK-NEXT: sub x8, x8, x9 ; CHECK-NEXT: sub x8, x8, x9
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov x9, #-8 ; CHECK-NEXT: mov x9, #-8
; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: st1w { z3.s }, p0, [x8, #3, mul vl] ; CHECK-NEXT: st1w { z3.s }, p0, [x8, #3, mul vl]
; CHECK-NEXT: st1w { z2.s }, p0, [x8, #2, mul vl] ; CHECK-NEXT: st1w { z2.s }, p0, [x8, #2, mul vl]
; CHECK-NEXT: addvl x8, x8, #2 ; CHECK-NEXT: addvl x8, x8, #2
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, x9, lsl #2] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, x9, lsl #2]
; CHECK-NEXT: sub x8, x8, #32 // =32 ; CHECK-NEXT: sub x8, x8, #32
; CHECK-NEXT: ld1w { z1.s }, p0/z, [x8, #1, mul vl] ; CHECK-NEXT: ld1w { z1.s }, p0/z, [x8, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #4 ; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 -8) %res = call <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 -8)
ret <vscale x 8 x i32> %res ret <vscale x 8 x i32> %res
} }
; Verify splitvec type legalisation works as expected. ; Verify splitvec type legalisation works as expected.
define <vscale x 16 x float> @splice_nxv16f32_clamped(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 { define <vscale x 16 x float> @splice_nxv16f32_clamped(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 {
; CHECK-LABEL: splice_nxv16f32_clamped: ; CHECK-LABEL: splice_nxv16f32_clamped:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-8 ; CHECK-NEXT: addvl sp, sp, #-8
; CHECK-NEXT: rdvl x9, #4 ; CHECK-NEXT: rdvl x9, #4
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w10, #68 ; CHECK-NEXT: mov w10, #68
; CHECK-NEXT: cmp x9, #68 // =68 ; CHECK-NEXT: cmp x9, #68
; CHECK-NEXT: st1w { z3.s }, p0, [x8, #3, mul vl] ; CHECK-NEXT: st1w { z3.s }, p0, [x8, #3, mul vl]
; CHECK-NEXT: st1w { z2.s }, p0, [x8, #2, mul vl] ; CHECK-NEXT: st1w { z2.s }, p0, [x8, #2, mul vl]
; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: st1w { z7.s }, p0, [x8, #7, mul vl] ; CHECK-NEXT: st1w { z7.s }, p0, [x8, #7, mul vl]
; CHECK-NEXT: st1w { z4.s }, p0, [x8, #4, mul vl] ; CHECK-NEXT: st1w { z4.s }, p0, [x8, #4, mul vl]
; CHECK-NEXT: st1w { z5.s }, p0, [x8, #5, mul vl] ; CHECK-NEXT: st1w { z5.s }, p0, [x8, #5, mul vl]
; CHECK-NEXT: st1w { z6.s }, p0, [x8, #6, mul vl] ; CHECK-NEXT: st1w { z6.s }, p0, [x8, #6, mul vl]
Show All 33 Lines

llvm/test/CodeGen/AArch64/neg-abs.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs \ ; RUN: llc -verify-machineinstrs \
; RUN: -mtriple=aarch64-unknown-unknown < %s | FileCheck %s ; RUN: -mtriple=aarch64-unknown-unknown < %s | FileCheck %s
declare i64 @llvm.abs.i64(i64, i1 immarg) declare i64 @llvm.abs.i64(i64, i1 immarg)
define i64 @neg_abs64(i64 %x) { define i64 @neg_abs64(i64 %x) {
; CHECK-LABEL: neg_abs64: ; CHECK-LABEL: neg_abs64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp x0, #0 // =0 ; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: cneg x8, x0, mi ; CHECK-NEXT: cneg x8, x0, mi
; CHECK-NEXT: neg x0, x8 ; CHECK-NEXT: neg x0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
%neg = sub nsw i64 0, %abs %neg = sub nsw i64 0, %abs
ret i64 %neg ret i64 %neg
} }
declare i32 @llvm.abs.i32(i32, i1 immarg) declare i32 @llvm.abs.i32(i32, i1 immarg)
define i32 @neg_abs32(i32 %x) { define i32 @neg_abs32(i32 %x) {
; CHECK-LABEL: neg_abs32: ; CHECK-LABEL: neg_abs32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: cneg w8, w0, mi ; CHECK-NEXT: cneg w8, w0, mi
; CHECK-NEXT: neg w0, w8 ; CHECK-NEXT: neg w0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
%neg = sub nsw i32 0, %abs %neg = sub nsw i32 0, %abs
ret i32 %neg ret i32 %neg
} }
Show All 28 Lines; CHECK-NEXT: ret
ret i128 %neg ret i128 %neg
} }
define i64 @abs64(i64 %x) { define i64 @abs64(i64 %x) {
; CHECK-LABEL: abs64: ; CHECK-LABEL: abs64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp x0, #0 // =0 ; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: cneg x0, x0, mi ; CHECK-NEXT: cneg x0, x0, mi
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
ret i64 %abs ret i64 %abs
} }
define i32 @abs32(i32 %x) { define i32 @abs32(i32 %x) {
; CHECK-LABEL: abs32: ; CHECK-LABEL: abs32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: cneg w0, w0, mi ; CHECK-NEXT: cneg w0, w0, mi
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
ret i32 %abs ret i32 %abs
} }
define i16 @abs16(i16 %x) { define i16 @abs16(i16 %x) {
; CHECK-LABEL: abs16: ; CHECK-LABEL: abs16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w0 ; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: cmp w8, #0 // =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cneg w0, w8, mi ; CHECK-NEXT: cneg w0, w8, mi
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true) %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
ret i16 %abs ret i16 %abs
} }
define i128 @abs128(i128 %x) { define i128 @abs128(i128 %x) {
; CHECK-LABEL: abs128: ; CHECK-LABEL: abs128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: negs x8, x0 ; CHECK-NEXT: negs x8, x0
; CHECK-NEXT: ngcs x9, x1 ; CHECK-NEXT: ngcs x9, x1
; CHECK-NEXT: cmp x1, #0 // =0 ; CHECK-NEXT: cmp x1, #0
; CHECK-NEXT: csel x0, x8, x0, lt ; CHECK-NEXT: csel x0, x8, x0, lt
; CHECK-NEXT: csel x1, x9, x1, lt ; CHECK-NEXT: csel x1, x9, x1, lt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true) %abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true)
ret i128 %abs ret i128 %abs
} }

llvm/test/CodeGen/AArch64/pow.ll

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; CHECK-NEXT: b pow ; CHECK-NEXT: b pow
%r = call nsz ninf double @llvm.pow.f64(double %x, double 2.5e-01) %r = call nsz ninf double @llvm.pow.f64(double %x, double 2.5e-01)
ret double %r ret double %r
} }
define <4 x float> @pow_v4f32_one_fourth_not_enough_fmf(<4 x float> %x) nounwind { define <4 x float> @pow_v4f32_one_fourth_not_enough_fmf(<4 x float> %x) nounwind {
; CHECK-LABEL: pow_v4f32_one_fourth_not_enough_fmf: ; CHECK-LABEL: pow_v4f32_one_fourth_not_enough_fmf:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: mov s0, v0.s[1] ; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: fmov s1, #0.25000000 ; CHECK-NEXT: fmov s1, #0.25000000
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: fmov s1, #0.25000000 ; CHECK-NEXT: fmov s1, #0.25000000
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
Show All 15 Lines
; CHECK-NEXT: fmov s1, #0.25000000 ; CHECK-NEXT: fmov s1, #0.25000000
; CHECK-NEXT: mov s0, v0.s[3] ; CHECK-NEXT: mov s0, v0.s[3]
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v1.s[3], v0.s[0] ; CHECK-NEXT: mov v1.s[3], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48 // =48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call afn nsz <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 2.5e-1, float 2.5e-1, float 2.5e-01, float 2.5e-01>) %r = call afn nsz <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 2.5e-1, float 2.5e-1, float 2.5e-01, float 2.5e-01>)
ret <4 x float> %r ret <4 x float> %r
} }
define <2 x double> @pow_v2f64_one_fourth_not_enough_fmf(<2 x double> %x) nounwind { define <2 x double> @pow_v2f64_one_fourth_not_enough_fmf(<2 x double> %x) nounwind {
; CHECK-LABEL: pow_v2f64_one_fourth_not_enough_fmf: ; CHECK-LABEL: pow_v2f64_one_fourth_not_enough_fmf:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: mov d0, v0.d[1] ; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: fmov d1, #0.25000000 ; CHECK-NEXT: fmov d1, #0.25000000
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: bl pow ; CHECK-NEXT: bl pow
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: fmov d1, #0.25000000 ; CHECK-NEXT: fmov d1, #0.25000000
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: bl pow ; CHECK-NEXT: bl pow
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov v0.d[1], v1.d[0] ; CHECK-NEXT: mov v0.d[1], v1.d[0]
; CHECK-NEXT: add sp, sp, #48 // =48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call nsz nnan reassoc <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 2.5e-1, double 2.5e-1>) %r = call nsz nnan reassoc <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 2.5e-1, double 2.5e-1>)
ret <2 x double> %r ret <2 x double> %r
} }

llvm/test/CodeGen/AArch64/pr48188.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -O0 -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
; GlobalISel cannot legalize this phi, so we fall back to SDAG. ; GlobalISel cannot legalize this phi, so we fall back to SDAG.
define void @test() nounwind { define void @test() nounwind {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #16 // =16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: mov x1, xzr ; CHECK-NEXT: mov x1, xzr
; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: mov x0, x1
; CHECK-NEXT: str x1, [sp] // 8-byte Folded Spill ; CHECK-NEXT: str x1, [sp] // 8-byte Folded Spill
; CHECK-NEXT: str x0, [sp, #8] // 8-byte Folded Spill ; CHECK-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
; CHECK-NEXT: b .LBB0_1 ; CHECK-NEXT: b .LBB0_1
; CHECK-NEXT: .LBB0_1: // %loop ; CHECK-NEXT: .LBB0_1: // %loop
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload ; CHECK-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
Show All 11 Lines

llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll

Show First 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
; CHECK-NEXT: add v29.2d, v29.2d, v14.2d ; CHECK-NEXT: add v29.2d, v29.2d, v14.2d
; CHECK-NEXT: fmov d14, x13 ; CHECK-NEXT: fmov d14, x13
; CHECK-NEXT: mul x17, x17, x1 ; CHECK-NEXT: mul x17, x17, x1
; CHECK-NEXT: mov v14.d[1], x12 ; CHECK-NEXT: mov v14.d[1], x12
; CHECK-NEXT: mul x16, x16, x1 ; CHECK-NEXT: mul x16, x16, x1
; CHECK-NEXT: add v28.2d, v28.2d, v14.2d ; CHECK-NEXT: add v28.2d, v28.2d, v14.2d
; CHECK-NEXT: fmov d14, x17 ; CHECK-NEXT: fmov d14, x17
; CHECK-NEXT: mov v14.d[1], x16 ; CHECK-NEXT: mov v14.d[1], x16
; CHECK-NEXT: add x8, x8, #8 // =8 ; CHECK-NEXT: add x8, x8, #8
; CHECK-NEXT: add v27.2d, v27.2d, v14.2d ; CHECK-NEXT: add v27.2d, v27.2d, v14.2d
; CHECK-NEXT: cmp x8, #64 // =64 ; CHECK-NEXT: cmp x8, #64
; CHECK-NEXT: add x9, x9, #1 // =1 ; CHECK-NEXT: add x9, x9, #1
; CHECK-NEXT: b.ne .LBB0_1 ; CHECK-NEXT: b.ne .LBB0_1
; CHECK-NEXT: // %bb.2: // %for.cond.cleanup ; CHECK-NEXT: // %bb.2: // %for.cond.cleanup
; CHECK-NEXT: adrp x8, C ; CHECK-NEXT: adrp x8, C
; CHECK-NEXT: add x8, x8, :lo12:C ; CHECK-NEXT: add x8, x8, :lo12:C
; CHECK-NEXT: stp q13, q12, [x8] ; CHECK-NEXT: stp q13, q12, [x8]
; CHECK-NEXT: stp q11, q10, [x8, #32] ; CHECK-NEXT: stp q11, q10, [x8, #32]
; CHECK-NEXT: stp q9, q8, [x8, #64] ; CHECK-NEXT: stp q9, q8, [x8, #64]
; CHECK-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
▲ Show 20 Lines • Show All 181 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/sadd_sat.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
declare i4 @llvm.sadd.sat.i4(i4, i4) declare i4 @llvm.sadd.sat.i4(i4, i4)
declare i8 @llvm.sadd.sat.i8(i8, i8) declare i8 @llvm.sadd.sat.i8(i8, i8)
declare i16 @llvm.sadd.sat.i16(i16, i16) declare i16 @llvm.sadd.sat.i16(i16, i16)
declare i32 @llvm.sadd.sat.i32(i32, i32) declare i32 @llvm.sadd.sat.i32(i32, i32)
declare i64 @llvm.sadd.sat.i64(i64, i64) declare i64 @llvm.sadd.sat.i64(i64, i64)
declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>) declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
define i32 @func(i32 %x, i32 %y) nounwind { define i32 @func(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: func: ; CHECK-LABEL: func:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adds w8, w0, w1 ; CHECK-NEXT: adds w8, w0, w1
; CHECK-NEXT: mov w9, #2147483647 ; CHECK-NEXT: mov w9, #2147483647
; CHECK-NEXT: cmp w8, #0 // =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cinv w8, w9, ge ; CHECK-NEXT: cinv w8, w9, ge
; CHECK-NEXT: adds w9, w0, w1 ; CHECK-NEXT: adds w9, w0, w1
; CHECK-NEXT: csel w0, w8, w9, vs ; CHECK-NEXT: csel w0, w8, w9, vs
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y); %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y);
ret i32 %tmp; ret i32 %tmp;
} }
define i64 @func2(i64 %x, i64 %y) nounwind { define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: func2: ; CHECK-LABEL: func2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adds x8, x0, x1 ; CHECK-NEXT: adds x8, x0, x1
; CHECK-NEXT: mov x9, #9223372036854775807 ; CHECK-NEXT: mov x9, #9223372036854775807
; CHECK-NEXT: cmp x8, #0 // =0 ; CHECK-NEXT: cmp x8, #0
; CHECK-NEXT: cinv x8, x9, ge ; CHECK-NEXT: cinv x8, x9, ge
; CHECK-NEXT: adds x9, x0, x1 ; CHECK-NEXT: adds x9, x0, x1
; CHECK-NEXT: csel x0, x8, x9, vs ; CHECK-NEXT: csel x0, x8, x9, vs
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y); %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y);
ret i64 %tmp; ret i64 %tmp;
} }
Show All 14 Lines
} }
define i8 @func8(i8 %x, i8 %y) nounwind { define i8 @func8(i8 %x, i8 %y) nounwind {
; CHECK-LABEL: func8: ; CHECK-LABEL: func8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0 ; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: add w8, w8, w1, sxtb ; CHECK-NEXT: add w8, w8, w1, sxtb
; CHECK-NEXT: mov w9, #127 ; CHECK-NEXT: mov w9, #127
; CHECK-NEXT: cmp w8, #127 // =127 ; CHECK-NEXT: cmp w8, #127
; CHECK-NEXT: csel w8, w8, w9, lt ; CHECK-NEXT: csel w8, w8, w9, lt
; CHECK-NEXT: cmn w8, #128 // =128 ; CHECK-NEXT: cmn w8, #128
; CHECK-NEXT: mov w9, #-128 ; CHECK-NEXT: mov w9, #-128
; CHECK-NEXT: csel w0, w8, w9, gt ; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y); %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y);
ret i8 %tmp; ret i8 %tmp;
} }
define i4 @func3(i4 %x, i4 %y) nounwind { define i4 @func3(i4 %x, i4 %y) nounwind {
; CHECK-LABEL: func3: ; CHECK-LABEL: func3:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: lsl w8, w1, #28 ; CHECK-NEXT: lsl w8, w1, #28
; CHECK-NEXT: sbfx w9, w0, #0, #4 ; CHECK-NEXT: sbfx w9, w0, #0, #4
; CHECK-NEXT: add w8, w9, w8, asr #28 ; CHECK-NEXT: add w8, w9, w8, asr #28
; CHECK-NEXT: mov w10, #7 ; CHECK-NEXT: mov w10, #7
; CHECK-NEXT: cmp w8, #7 // =7 ; CHECK-NEXT: cmp w8, #7
; CHECK-NEXT: csel w8, w8, w10, lt ; CHECK-NEXT: csel w8, w8, w10, lt
; CHECK-NEXT: cmn w8, #8 // =8 ; CHECK-NEXT: cmn w8, #8
; CHECK-NEXT: mov w9, #-8 ; CHECK-NEXT: mov w9, #-8
; CHECK-NEXT: csel w0, w8, w9, gt ; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y); %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);
ret i4 %tmp; ret i4 %tmp;
} }
define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: vec: ; CHECK-LABEL: vec:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sqadd v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sqadd v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y); %tmp = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y);
ret <4 x i32> %tmp; ret <4 x i32> %tmp;
} }

llvm/test/CodeGen/AArch64/sadd_sat_plus.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
declare i4 @llvm.sadd.sat.i4(i4, i4) declare i4 @llvm.sadd.sat.i4(i4, i4)
declare i8 @llvm.sadd.sat.i8(i8, i8) declare i8 @llvm.sadd.sat.i8(i8, i8)
declare i16 @llvm.sadd.sat.i16(i16, i16) declare i16 @llvm.sadd.sat.i16(i16, i16)
declare i32 @llvm.sadd.sat.i32(i32, i32) declare i32 @llvm.sadd.sat.i32(i32, i32)
declare i64 @llvm.sadd.sat.i64(i64, i64) declare i64 @llvm.sadd.sat.i64(i64, i64)
define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind { define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-LABEL: func32: ; CHECK-LABEL: func32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mul w8, w1, w2 ; CHECK-NEXT: mul w8, w1, w2
; CHECK-NEXT: adds w10, w0, w8 ; CHECK-NEXT: adds w10, w0, w8
; CHECK-NEXT: mov w9, #2147483647 ; CHECK-NEXT: mov w9, #2147483647
; CHECK-NEXT: cmp w10, #0 // =0 ; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: cinv w9, w9, ge ; CHECK-NEXT: cinv w9, w9, ge
; CHECK-NEXT: adds w8, w0, w8 ; CHECK-NEXT: adds w8, w0, w8
; CHECK-NEXT: csel w0, w9, w8, vs ; CHECK-NEXT: csel w0, w9, w8, vs
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = mul i32 %y, %z %a = mul i32 %y, %z
%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a) %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)
ret i32 %tmp ret i32 %tmp
} }
define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind { define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; CHECK-LABEL: func64: ; CHECK-LABEL: func64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adds x8, x0, x2 ; CHECK-NEXT: adds x8, x0, x2
; CHECK-NEXT: mov x9, #9223372036854775807 ; CHECK-NEXT: mov x9, #9223372036854775807
; CHECK-NEXT: cmp x8, #0 // =0 ; CHECK-NEXT: cmp x8, #0
; CHECK-NEXT: cinv x8, x9, ge ; CHECK-NEXT: cinv x8, x9, ge
; CHECK-NEXT: adds x9, x0, x2 ; CHECK-NEXT: adds x9, x0, x2
; CHECK-NEXT: csel x0, x8, x9, vs ; CHECK-NEXT: csel x0, x8, x9, vs
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = mul i64 %y, %z %a = mul i64 %y, %z
%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z) %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
ret i64 %tmp ret i64 %tmp
} }
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define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind { define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
; CHECK-LABEL: func8: ; CHECK-LABEL: func8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0 ; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: mul w9, w1, w2 ; CHECK-NEXT: mul w9, w1, w2
; CHECK-NEXT: add w8, w8, w9, sxtb ; CHECK-NEXT: add w8, w8, w9, sxtb
; CHECK-NEXT: mov w10, #127 ; CHECK-NEXT: mov w10, #127
; CHECK-NEXT: cmp w8, #127 // =127 ; CHECK-NEXT: cmp w8, #127
; CHECK-NEXT: csel w8, w8, w10, lt ; CHECK-NEXT: csel w8, w8, w10, lt
; CHECK-NEXT: cmn w8, #128 // =128 ; CHECK-NEXT: cmn w8, #128
; CHECK-NEXT: mov w9, #-128 ; CHECK-NEXT: mov w9, #-128
; CHECK-NEXT: csel w0, w8, w9, gt ; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = mul i8 %y, %z %a = mul i8 %y, %z
%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %a) %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %a)
ret i8 %tmp ret i8 %tmp
} }
define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind { define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
; CHECK-LABEL: func4: ; CHECK-LABEL: func4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mul w9, w1, w2 ; CHECK-NEXT: mul w9, w1, w2
; CHECK-NEXT: sbfx w8, w0, #0, #4 ; CHECK-NEXT: sbfx w8, w0, #0, #4
; CHECK-NEXT: lsl w9, w9, #28 ; CHECK-NEXT: lsl w9, w9, #28
; CHECK-NEXT: add w8, w8, w9, asr #28 ; CHECK-NEXT: add w8, w8, w9, asr #28
; CHECK-NEXT: mov w10, #7 ; CHECK-NEXT: mov w10, #7
; CHECK-NEXT: cmp w8, #7 // =7 ; CHECK-NEXT: cmp w8, #7
; CHECK-NEXT: csel w8, w8, w10, lt ; CHECK-NEXT: csel w8, w8, w10, lt
; CHECK-NEXT: cmn w8, #8 // =8 ; CHECK-NEXT: cmn w8, #8
; CHECK-NEXT: mov w9, #-8 ; CHECK-NEXT: mov w9, #-8
; CHECK-NEXT: csel w0, w8, w9, gt ; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = mul i4 %y, %z %a = mul i4 %y, %z
%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %a) %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %a)
ret i4 %tmp ret i4 %tmp
} }

llvm/test/CodeGen/AArch64/sadd_sat_vec.ll

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret void ret void
} }
define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind { define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
; CHECK-LABEL: v2i8: ; CHECK-LABEL: v2i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ld1 { v0.b }[0], [x1] ; CHECK-NEXT: ld1 { v0.b }[0], [x1]
; CHECK-NEXT: ld1 { v1.b }[0], [x0] ; CHECK-NEXT: ld1 { v1.b }[0], [x0]
; CHECK-NEXT: add x8, x0, #1 // =1 ; CHECK-NEXT: add x8, x0, #1
; CHECK-NEXT: add x9, x1, #1 // =1 ; CHECK-NEXT: add x9, x1, #1
; CHECK-NEXT: ld1 { v0.b }[4], [x9] ; CHECK-NEXT: ld1 { v0.b }[4], [x9]
; CHECK-NEXT: ld1 { v1.b }[4], [x8] ; CHECK-NEXT: ld1 { v1.b }[4], [x8]
; CHECK-NEXT: shl v0.2s, v0.2s, #24 ; CHECK-NEXT: shl v0.2s, v0.2s, #24
; CHECK-NEXT: shl v1.2s, v1.2s, #24 ; CHECK-NEXT: shl v1.2s, v1.2s, #24
; CHECK-NEXT: sqadd v0.2s, v1.2s, v0.2s ; CHECK-NEXT: sqadd v0.2s, v1.2s, v0.2s
; CHECK-NEXT: ushr v0.2s, v0.2s, #24 ; CHECK-NEXT: ushr v0.2s, v0.2s, #24
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
Show All 22 Lines; CHECK-NEXT: ret
ret void ret void
} }
define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind { define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
; CHECK-LABEL: v2i16: ; CHECK-LABEL: v2i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ld1 { v0.h }[0], [x1] ; CHECK-NEXT: ld1 { v0.h }[0], [x1]
; CHECK-NEXT: ld1 { v1.h }[0], [x0] ; CHECK-NEXT: ld1 { v1.h }[0], [x0]
; CHECK-NEXT: add x8, x0, #2 // =2 ; CHECK-NEXT: add x8, x0, #2
; CHECK-NEXT: add x9, x1, #2 // =2 ; CHECK-NEXT: add x9, x1, #2
; CHECK-NEXT: ld1 { v0.h }[2], [x9] ; CHECK-NEXT: ld1 { v0.h }[2], [x9]
; CHECK-NEXT: ld1 { v1.h }[2], [x8] ; CHECK-NEXT: ld1 { v1.h }[2], [x8]
; CHECK-NEXT: shl v0.2s, v0.2s, #16 ; CHECK-NEXT: shl v0.2s, v0.2s, #16
; CHECK-NEXT: shl v1.2s, v1.2s, #16 ; CHECK-NEXT: shl v1.2s, v1.2s, #16
; CHECK-NEXT: sqadd v0.2s, v1.2s, v0.2s ; CHECK-NEXT: sqadd v0.2s, v1.2s, v0.2s
; CHECK-NEXT: ushr v0.2s, v0.2s, #16 ; CHECK-NEXT: ushr v0.2s, v0.2s, #16
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
▲ Show 20 Lines • Show All 161 Lines • ▼ Show 20 Lines
define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind { define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; CHECK-LABEL: v2i128: ; CHECK-LABEL: v2i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adds x8, x2, x6 ; CHECK-NEXT: adds x8, x2, x6
; CHECK-NEXT: adcs x12, x3, x7 ; CHECK-NEXT: adcs x12, x3, x7
; CHECK-NEXT: mov x9, #9223372036854775807 ; CHECK-NEXT: mov x9, #9223372036854775807
; CHECK-NEXT: eor x10, x3, x7 ; CHECK-NEXT: eor x10, x3, x7
; CHECK-NEXT: cmp x12, #0 // =0 ; CHECK-NEXT: cmp x12, #0
; CHECK-NEXT: eor x13, x3, x12 ; CHECK-NEXT: eor x13, x3, x12
; CHECK-NEXT: cinv x14, x9, ge ; CHECK-NEXT: cinv x14, x9, ge
; CHECK-NEXT: bics xzr, x13, x10 ; CHECK-NEXT: bics xzr, x13, x10
; CHECK-NEXT: asr x10, x12, #63 ; CHECK-NEXT: asr x10, x12, #63
; CHECK-NEXT: csel x2, x10, x8, lt ; CHECK-NEXT: csel x2, x10, x8, lt
; CHECK-NEXT: csel x3, x14, x12, lt ; CHECK-NEXT: csel x3, x14, x12, lt
; CHECK-NEXT: adds x8, x0, x4 ; CHECK-NEXT: adds x8, x0, x4
; CHECK-NEXT: adcs x10, x1, x5 ; CHECK-NEXT: adcs x10, x1, x5
; CHECK-NEXT: eor x11, x1, x5 ; CHECK-NEXT: eor x11, x1, x5
; CHECK-NEXT: cmp x10, #0 // =0 ; CHECK-NEXT: cmp x10, #0
; CHECK-NEXT: eor x12, x1, x10 ; CHECK-NEXT: eor x12, x1, x10
; CHECK-NEXT: cinv x9, x9, ge ; CHECK-NEXT: cinv x9, x9, ge
; CHECK-NEXT: bics xzr, x12, x11 ; CHECK-NEXT: bics xzr, x12, x11
; CHECK-NEXT: asr x11, x10, #63 ; CHECK-NEXT: asr x11, x10, #63
; CHECK-NEXT: csel x8, x11, x8, lt ; CHECK-NEXT: csel x8, x11, x8, lt
; CHECK-NEXT: csel x1, x9, x10, lt ; CHECK-NEXT: csel x1, x9, x10, lt
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y) %z = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
ret <2 x i128> %z ret <2 x i128> %z
} }

llvm/test/CodeGen/AArch64/sat-add.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
; There are at least 3 potential patterns corresponding to an unsigned saturated add: min, cmp with sum, cmp with not. ; There are at least 3 potential patterns corresponding to an unsigned saturated add: min, cmp with sum, cmp with not.
; Test each of those patterns with i8/i16/i32/i64. ; Test each of those patterns with i8/i16/i32/i64.
; Test each of those with a constant operand and a variable operand. ; Test each of those with a constant operand and a variable operand.
; Test each of those with a 128-bit vector type. ; Test each of those with a 128-bit vector type.
define i8 @unsigned_sat_constant_i8_using_min(i8 %x) { define i8 @unsigned_sat_constant_i8_using_min(i8 %x) {
; CHECK-LABEL: unsigned_sat_constant_i8_using_min: ; CHECK-LABEL: unsigned_sat_constant_i8_using_min:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff ; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: cmp w8, #213 // =213 ; CHECK-NEXT: cmp w8, #213
; CHECK-NEXT: mov w8, #-43 ; CHECK-NEXT: mov w8, #-43
; CHECK-NEXT: csel w8, w0, w8, lo ; CHECK-NEXT: csel w8, w0, w8, lo
; CHECK-NEXT: add w0, w8, #42 // =42 ; CHECK-NEXT: add w0, w8, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp ult i8 %x, -43 %c = icmp ult i8 %x, -43
%s = select i1 %c, i8 %x, i8 -43 %s = select i1 %c, i8 %x, i8 -43
%r = add i8 %s, 42 %r = add i8 %s, 42
ret i8 %r ret i8 %r
} }
define i8 @unsigned_sat_constant_i8_using_cmp_sum(i8 %x) { define i8 @unsigned_sat_constant_i8_using_cmp_sum(i8 %x) {
; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_sum: ; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_sum:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff ; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: add w8, w8, #42 // =42 ; CHECK-NEXT: add w8, w8, #42
; CHECK-NEXT: tst w8, #0x100 ; CHECK-NEXT: tst w8, #0x100
; CHECK-NEXT: csinv w0, w8, wzr, eq ; CHECK-NEXT: csinv w0, w8, wzr, eq
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = add i8 %x, 42 %a = add i8 %x, 42
%c = icmp ugt i8 %x, %a %c = icmp ugt i8 %x, %a
%r = select i1 %c, i8 -1, i8 %a %r = select i1 %c, i8 -1, i8 %a
ret i8 %r ret i8 %r
} }
define i8 @unsigned_sat_constant_i8_using_cmp_notval(i8 %x) { define i8 @unsigned_sat_constant_i8_using_cmp_notval(i8 %x) {
; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_notval: ; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_notval:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff ; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: add w9, w0, #42 // =42 ; CHECK-NEXT: add w9, w0, #42
; CHECK-NEXT: cmp w8, #213 // =213 ; CHECK-NEXT: cmp w8, #213
; CHECK-NEXT: csinv w0, w9, wzr, ls ; CHECK-NEXT: csinv w0, w9, wzr, ls
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = add i8 %x, 42 %a = add i8 %x, 42
%c = icmp ugt i8 %x, -43 %c = icmp ugt i8 %x, -43
%r = select i1 %c, i8 -1, i8 %a %r = select i1 %c, i8 -1, i8 %a
ret i8 %r ret i8 %r
} }
define i16 @unsigned_sat_constant_i16_using_min(i16 %x) { define i16 @unsigned_sat_constant_i16_using_min(i16 %x) {
; CHECK-LABEL: unsigned_sat_constant_i16_using_min: ; CHECK-LABEL: unsigned_sat_constant_i16_using_min:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #65493 ; CHECK-NEXT: mov w8, #65493
; CHECK-NEXT: cmp w8, w0, uxth ; CHECK-NEXT: cmp w8, w0, uxth
; CHECK-NEXT: mov w8, #-43 ; CHECK-NEXT: mov w8, #-43
; CHECK-NEXT: csel w8, w0, w8, hi ; CHECK-NEXT: csel w8, w0, w8, hi
; CHECK-NEXT: add w0, w8, #42 // =42 ; CHECK-NEXT: add w0, w8, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp ult i16 %x, -43 %c = icmp ult i16 %x, -43
%s = select i1 %c, i16 %x, i16 -43 %s = select i1 %c, i16 %x, i16 -43
%r = add i16 %s, 42 %r = add i16 %s, 42
ret i16 %r ret i16 %r
} }
define i16 @unsigned_sat_constant_i16_using_cmp_sum(i16 %x) { define i16 @unsigned_sat_constant_i16_using_cmp_sum(i16 %x) {
; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_sum: ; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_sum:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff ; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: add w8, w8, #42 // =42 ; CHECK-NEXT: add w8, w8, #42
; CHECK-NEXT: tst w8, #0x10000 ; CHECK-NEXT: tst w8, #0x10000
; CHECK-NEXT: csinv w0, w8, wzr, eq ; CHECK-NEXT: csinv w0, w8, wzr, eq
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = add i16 %x, 42 %a = add i16 %x, 42
%c = icmp ugt i16 %x, %a %c = icmp ugt i16 %x, %a
%r = select i1 %c, i16 -1, i16 %a %r = select i1 %c, i16 -1, i16 %a
ret i16 %r ret i16 %r
} }
define i16 @unsigned_sat_constant_i16_using_cmp_notval(i16 %x) { define i16 @unsigned_sat_constant_i16_using_cmp_notval(i16 %x) {
; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_notval: ; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_notval:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w9, #65493 ; CHECK-NEXT: mov w9, #65493
; CHECK-NEXT: add w8, w0, #42 // =42 ; CHECK-NEXT: add w8, w0, #42
; CHECK-NEXT: cmp w9, w0, uxth ; CHECK-NEXT: cmp w9, w0, uxth
; CHECK-NEXT: csinv w0, w8, wzr, hs ; CHECK-NEXT: csinv w0, w8, wzr, hs
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = add i16 %x, 42 %a = add i16 %x, 42
%c = icmp ugt i16 %x, -43 %c = icmp ugt i16 %x, -43
%r = select i1 %c, i16 -1, i16 %a %r = select i1 %c, i16 -1, i16 %a
ret i16 %r ret i16 %r
} }
define i32 @unsigned_sat_constant_i32_using_min(i32 %x) { define i32 @unsigned_sat_constant_i32_using_min(i32 %x) {
; CHECK-LABEL: unsigned_sat_constant_i32_using_min: ; CHECK-LABEL: unsigned_sat_constant_i32_using_min:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmn w0, #43 // =43 ; CHECK-NEXT: cmn w0, #43
; CHECK-NEXT: mov w8, #-43 ; CHECK-NEXT: mov w8, #-43
; CHECK-NEXT: csel w8, w0, w8, lo ; CHECK-NEXT: csel w8, w0, w8, lo
; CHECK-NEXT: add w0, w8, #42 // =42 ; CHECK-NEXT: add w0, w8, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp ult i32 %x, -43 %c = icmp ult i32 %x, -43
%s = select i1 %c, i32 %x, i32 -43 %s = select i1 %c, i32 %x, i32 -43
%r = add i32 %s, 42 %r = add i32 %s, 42
ret i32 %r ret i32 %r
} }
define i32 @unsigned_sat_constant_i32_using_cmp_sum(i32 %x) { define i32 @unsigned_sat_constant_i32_using_cmp_sum(i32 %x) {
; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_sum: ; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_sum:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adds w8, w0, #42 // =42 ; CHECK-NEXT: adds w8, w0, #42
; CHECK-NEXT: csinv w0, w8, wzr, lo ; CHECK-NEXT: csinv w0, w8, wzr, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = add i32 %x, 42 %a = add i32 %x, 42
%c = icmp ugt i32 %x, %a %c = icmp ugt i32 %x, %a
%r = select i1 %c, i32 -1, i32 %a %r = select i1 %c, i32 -1, i32 %a
ret i32 %r ret i32 %r
} }
define i32 @unsigned_sat_constant_i32_using_cmp_notval(i32 %x) { define i32 @unsigned_sat_constant_i32_using_cmp_notval(i32 %x) {
; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_notval: ; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_notval:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adds w8, w0, #42 // =42 ; CHECK-NEXT: adds w8, w0, #42
; CHECK-NEXT: csinv w0, w8, wzr, lo ; CHECK-NEXT: csinv w0, w8, wzr, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = add i32 %x, 42 %a = add i32 %x, 42
%c = icmp ugt i32 %x, -43 %c = icmp ugt i32 %x, -43
%r = select i1 %c, i32 -1, i32 %a %r = select i1 %c, i32 -1, i32 %a
ret i32 %r ret i32 %r
} }
define i64 @unsigned_sat_constant_i64_using_min(i64 %x) { define i64 @unsigned_sat_constant_i64_using_min(i64 %x) {
; CHECK-LABEL: unsigned_sat_constant_i64_using_min: ; CHECK-LABEL: unsigned_sat_constant_i64_using_min:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmn x0, #43 // =43 ; CHECK-NEXT: cmn x0, #43
; CHECK-NEXT: mov x8, #-43 ; CHECK-NEXT: mov x8, #-43
; CHECK-NEXT: csel x8, x0, x8, lo ; CHECK-NEXT: csel x8, x0, x8, lo
; CHECK-NEXT: add x0, x8, #42 // =42 ; CHECK-NEXT: add x0, x8, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp ult i64 %x, -43 %c = icmp ult i64 %x, -43
%s = select i1 %c, i64 %x, i64 -43 %s = select i1 %c, i64 %x, i64 -43
%r = add i64 %s, 42 %r = add i64 %s, 42
ret i64 %r ret i64 %r
} }
define i64 @unsigned_sat_constant_i64_using_cmp_sum(i64 %x) { define i64 @unsigned_sat_constant_i64_using_cmp_sum(i64 %x) {
; CHECK-LABEL: unsigned_sat_constant_i64_using_cmp_sum: ; CHECK-LABEL: unsigned_sat_constant_i64_using_cmp_sum:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adds x8, x0, #42 // =42 ; CHECK-NEXT: adds x8, x0, #42
; CHECK-NEXT: csinv x0, x8, xzr, lo ; CHECK-NEXT: csinv x0, x8, xzr, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = add i64 %x, 42 %a = add i64 %x, 42
%c = icmp ugt i64 %x, %a %c = icmp ugt i64 %x, %a
%r = select i1 %c, i64 -1, i64 %a %r = select i1 %c, i64 -1, i64 %a
ret i64 %r ret i64 %r
} }
define i64 @unsigned_sat_constant_i64_using_cmp_notval(i64 %x) { define i64 @unsigned_sat_constant_i64_using_cmp_notval(i64 %x) {
; CHECK-LABEL: unsigned_sat_constant_i64_using_cmp_notval: ; CHECK-LABEL: unsigned_sat_constant_i64_using_cmp_notval:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adds x8, x0, #42 // =42 ; CHECK-NEXT: adds x8, x0, #42
; CHECK-NEXT: csinv x0, x8, xzr, lo ; CHECK-NEXT: csinv x0, x8, xzr, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = add i64 %x, 42 %a = add i64 %x, 42
%c = icmp ugt i64 %x, -43 %c = icmp ugt i64 %x, -43
%r = select i1 %c, i64 -1, i64 %a %r = select i1 %c, i64 -1, i64 %a
ret i64 %r ret i64 %r
} }
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llvm/test/CodeGen/AArch64/sdivpow2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ISEL ; RUN: llc -mtriple=aarch64-linux-gnu -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ISEL
; RUN: llc -mtriple=aarch64-linux-gnu -fast-isel=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,FAST ; RUN: llc -mtriple=aarch64-linux-gnu -fast-isel=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,FAST
define i32 @test1(i32 %x) { define i32 @test1(i32 %x) {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #7 // =7 ; CHECK-NEXT: add w8, w0, #7
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, w8, w0, lt ; CHECK-NEXT: csel w8, w8, w0, lt
; CHECK-NEXT: asr w0, w8, #3 ; CHECK-NEXT: asr w0, w8, #3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%div = sdiv i32 %x, 8 %div = sdiv i32 %x, 8
ret i32 %div ret i32 %div
} }
define i32 @test2(i32 %x) { define i32 @test2(i32 %x) {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #7 // =7 ; CHECK-NEXT: add w8, w0, #7
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, w8, w0, lt ; CHECK-NEXT: csel w8, w8, w0, lt
; CHECK-NEXT: neg w0, w8, asr #3 ; CHECK-NEXT: neg w0, w8, asr #3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%div = sdiv i32 %x, -8 %div = sdiv i32 %x, -8
ret i32 %div ret i32 %div
} }
define i32 @test3(i32 %x) { define i32 @test3(i32 %x) {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #31 // =31 ; CHECK-NEXT: add w8, w0, #31
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, w8, w0, lt ; CHECK-NEXT: csel w8, w8, w0, lt
; CHECK-NEXT: asr w0, w8, #5 ; CHECK-NEXT: asr w0, w8, #5
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%div = sdiv i32 %x, 32 %div = sdiv i32 %x, 32
ret i32 %div ret i32 %div
} }
define i64 @test4(i64 %x) { define i64 @test4(i64 %x) {
; CHECK-LABEL: test4: ; CHECK-LABEL: test4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #7 // =7 ; CHECK-NEXT: add x8, x0, #7
; CHECK-NEXT: cmp x0, #0 // =0 ; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: csel x8, x8, x0, lt ; CHECK-NEXT: csel x8, x8, x0, lt
; CHECK-NEXT: asr x0, x8, #3 ; CHECK-NEXT: asr x0, x8, #3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%div = sdiv i64 %x, 8 %div = sdiv i64 %x, 8
ret i64 %div ret i64 %div
} }
define i64 @test5(i64 %x) { define i64 @test5(i64 %x) {
; CHECK-LABEL: test5: ; CHECK-LABEL: test5:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #7 // =7 ; CHECK-NEXT: add x8, x0, #7
; CHECK-NEXT: cmp x0, #0 // =0 ; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: csel x8, x8, x0, lt ; CHECK-NEXT: csel x8, x8, x0, lt
; CHECK-NEXT: neg x0, x8, asr #3 ; CHECK-NEXT: neg x0, x8, asr #3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%div = sdiv i64 %x, -8 %div = sdiv i64 %x, -8
ret i64 %div ret i64 %div
} }
define i64 @test6(i64 %x) { define i64 @test6(i64 %x) {
; CHECK-LABEL: test6: ; CHECK-LABEL: test6:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #63 // =63 ; CHECK-NEXT: add x8, x0, #63
; CHECK-NEXT: cmp x0, #0 // =0 ; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: csel x8, x8, x0, lt ; CHECK-NEXT: csel x8, x8, x0, lt
; CHECK-NEXT: asr x0, x8, #6 ; CHECK-NEXT: asr x0, x8, #6
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%div = sdiv i64 %x, 64 %div = sdiv i64 %x, 64
ret i64 %div ret i64 %div
} }
define i64 @test7(i64 %x) { define i64 @test7(i64 %x) {
; CHECK-LABEL: test7: ; CHECK-LABEL: test7:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #281474976710655 ; CHECK-NEXT: mov x8, #281474976710655
; CHECK-NEXT: add x8, x0, x8 ; CHECK-NEXT: add x8, x0, x8
; CHECK-NEXT: cmp x0, #0 // =0 ; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: csel x8, x8, x0, lt ; CHECK-NEXT: csel x8, x8, x0, lt
; CHECK-NEXT: asr x0, x8, #48 ; CHECK-NEXT: asr x0, x8, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%div = sdiv i64 %x, 281474976710656 %div = sdiv i64 %x, 281474976710656
ret i64 %div ret i64 %div
} }
define i64 @test8(i64 %x) { define i64 @test8(i64 %x) {
; ISEL-LABEL: test8: ; ISEL-LABEL: test8:
; ISEL: // %bb.0: ; ISEL: // %bb.0:
; ISEL-NEXT: cmp x0, #0 // =0 ; ISEL-NEXT: cmp x0, #0
; ISEL-NEXT: cinc x8, x0, lt ; ISEL-NEXT: cinc x8, x0, lt
; ISEL-NEXT: asr x0, x8, #1 ; ISEL-NEXT: asr x0, x8, #1
; ISEL-NEXT: ret ; ISEL-NEXT: ret
; ;
; FAST-LABEL: test8: ; FAST-LABEL: test8:
; FAST: // %bb.0: ; FAST: // %bb.0:
; FAST-NEXT: add x8, x0, #1 // =1 ; FAST-NEXT: add x8, x0, #1
; FAST-NEXT: cmp x0, #0 // =0 ; FAST-NEXT: cmp x0, #0
; FAST-NEXT: csel x8, x8, x0, lt ; FAST-NEXT: csel x8, x8, x0, lt
; FAST-NEXT: asr x0, x8, #1 ; FAST-NEXT: asr x0, x8, #1
; FAST-NEXT: ret ; FAST-NEXT: ret
%div = sdiv i64 %x, 2 %div = sdiv i64 %x, 2
ret i64 %div ret i64 %div
} }

llvm/test/CodeGen/AArch64/select_const.ll

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
} }
; select Cond, 0, -1 --> sext (!Cond) ; select Cond, 0, -1 --> sext (!Cond)
define i32 @select_0_or_neg1(i1 %cond) { define i32 @select_0_or_neg1(i1 %cond) {
; CHECK-LABEL: select_0_or_neg1: ; CHECK-LABEL: select_0_or_neg1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x1 ; CHECK-NEXT: and w8, w0, #0x1
; CHECK-NEXT: sub w0, w8, #1 // =1 ; CHECK-NEXT: sub w0, w8, #1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sel = select i1 %cond, i32 0, i32 -1 %sel = select i1 %cond, i32 0, i32 -1
ret i32 %sel ret i32 %sel
} }
define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) { define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) {
; CHECK-LABEL: select_0_or_neg1_zeroext: ; CHECK-LABEL: select_0_or_neg1_zeroext:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub w0, w0, #1 // =1 ; CHECK-NEXT: sub w0, w0, #1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sel = select i1 %cond, i32 0, i32 -1 %sel = select i1 %cond, i32 0, i32 -1
ret i32 %sel ret i32 %sel
} }
define i32 @select_0_or_neg1_signext(i1 signext %cond) { define i32 @select_0_or_neg1_signext(i1 signext %cond) {
; CHECK-LABEL: select_0_or_neg1_signext: ; CHECK-LABEL: select_0_or_neg1_signext:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sel = select i1 %cond, i32 42, i32 41 %sel = select i1 %cond, i32 42, i32 41
ret i32 %sel ret i32 %sel
} }
define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) { define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) {
; CHECK-LABEL: select_Cplus1_C_zeroext: ; CHECK-LABEL: select_Cplus1_C_zeroext:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w8, #41 ; CHECK-NEXT: mov w8, #41
; CHECK-NEXT: cinc w0, w8, ne ; CHECK-NEXT: cinc w0, w8, ne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sel = select i1 %cond, i32 42, i32 41 %sel = select i1 %cond, i32 42, i32 41
ret i32 %sel ret i32 %sel
} }
define i32 @select_Cplus1_C_signext(i1 signext %cond) { define i32 @select_Cplus1_C_signext(i1 signext %cond) {
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sel = select i1 %cond, i32 41, i32 42 %sel = select i1 %cond, i32 41, i32 42
ret i32 %sel ret i32 %sel
} }
define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) { define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) {
; CHECK-LABEL: select_C_Cplus1_zeroext: ; CHECK-LABEL: select_C_Cplus1_zeroext:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w8, #41 ; CHECK-NEXT: mov w8, #41
; CHECK-NEXT: cinc w0, w8, eq ; CHECK-NEXT: cinc w0, w8, eq
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sel = select i1 %cond, i32 41, i32 42 %sel = select i1 %cond, i32 41, i32 42
ret i32 %sel ret i32 %sel
} }
define i32 @select_C_Cplus1_signext(i1 signext %cond) { define i32 @select_C_Cplus1_signext(i1 signext %cond) {
Show All 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sel = select i1 %cond, i32 421, i32 42 %sel = select i1 %cond, i32 421, i32 42
ret i32 %sel ret i32 %sel
} }
define i32 @select_C1_C2_zeroext(i1 zeroext %cond) { define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {
; CHECK-LABEL: select_C1_C2_zeroext: ; CHECK-LABEL: select_C1_C2_zeroext:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w8, #42 ; CHECK-NEXT: mov w8, #42
; CHECK-NEXT: mov w9, #421 ; CHECK-NEXT: mov w9, #421
; CHECK-NEXT: csel w0, w9, w8, ne ; CHECK-NEXT: csel w0, w9, w8, ne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sel = select i1 %cond, i32 421, i32 42 %sel = select i1 %cond, i32 421, i32 42
ret i32 %sel ret i32 %sel
} }
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llvm/test/CodeGen/AArch64/shift-mod.ll

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Linesentry:
ret i64 %shr ret i64 %shr
} }
; PR42644 - https://bugs.llvm.org/show_bug.cgi?id=42644 ; PR42644 - https://bugs.llvm.org/show_bug.cgi?id=42644
define i64 @ashr_add_shl_i32(i64 %r) { define i64 @ashr_add_shl_i32(i64 %r) {
; CHECK-LABEL: ashr_add_shl_i32: ; CHECK-LABEL: ashr_add_shl_i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #1 // =1 ; CHECK-NEXT: add w8, w0, #1
; CHECK-NEXT: sxtw x0, w8 ; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%conv = shl i64 %r, 32 %conv = shl i64 %r, 32
%sext = add i64 %conv, 4294967296 %sext = add i64 %conv, 4294967296
%conv1 = ashr i64 %sext, 32 %conv1 = ashr i64 %sext, 32
ret i64 %conv1 ret i64 %conv1
} }
define i64 @ashr_add_shl_i8(i64 %r) { define i64 @ashr_add_shl_i8(i64 %r) {
; CHECK-LABEL: ashr_add_shl_i8: ; CHECK-LABEL: ashr_add_shl_i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #1 // =1 ; CHECK-NEXT: add w8, w0, #1
; CHECK-NEXT: sxtb x0, w8 ; CHECK-NEXT: sxtb x0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%conv = shl i64 %r, 56 %conv = shl i64 %r, 56
%sext = add i64 %conv, 72057594037927936 %sext = add i64 %conv, 72057594037927936
%conv1 = ashr i64 %sext, 56 %conv1 = ashr i64 %sext, 56
ret i64 %conv1 ret i64 %conv1
} }
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llvm/test/CodeGen/AArch64/signbit-shift.ll

Show All 12 Lines; CHECK-NEXT: ret
%e = zext i1 %c to i32 %e = zext i1 %c to i32
ret i32 %e ret i32 %e
} }
define i32 @add_zext_ifpos(i32 %x) { define i32 @add_zext_ifpos(i32 %x) {
; CHECK-LABEL: add_zext_ifpos: ; CHECK-LABEL: add_zext_ifpos:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: asr w8, w0, #31 ; CHECK-NEXT: asr w8, w0, #31
; CHECK-NEXT: add w0, w8, #42 // =42 ; CHECK-NEXT: add w0, w8, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt i32 %x, -1 %c = icmp sgt i32 %x, -1
%e = zext i1 %c to i32 %e = zext i1 %c to i32
%r = add i32 %e, 41 %r = add i32 %e, 41
ret i32 %r ret i32 %r
} }
define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) { define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: add_zext_ifpos_vec_splat: ; CHECK-LABEL: add_zext_ifpos_vec_splat:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s ; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s
; CHECK-NEXT: movi v1.4s, #41 ; CHECK-NEXT: movi v1.4s, #41
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = zext <4 x i1> %c to <4 x i32> %e = zext <4 x i1> %c to <4 x i32>
%r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41> %r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>
ret <4 x i32> %r ret <4 x i32> %r
} }
define i32 @sel_ifpos_tval_bigger(i32 %x) { define i32 @sel_ifpos_tval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifpos_tval_bigger: ; CHECK-LABEL: sel_ifpos_tval_bigger:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w8, #41 ; CHECK-NEXT: mov w8, #41
; CHECK-NEXT: cinc w0, w8, ge ; CHECK-NEXT: cinc w0, w8, ge
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt i32 %x, -1 %c = icmp sgt i32 %x, -1
%r = select i1 %c, i32 42, i32 41 %r = select i1 %c, i32 42, i32 41
ret i32 %r ret i32 %r
} }
define i32 @sext_ifpos(i32 %x) { define i32 @sext_ifpos(i32 %x) {
; CHECK-LABEL: sext_ifpos: ; CHECK-LABEL: sext_ifpos:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mvn w8, w0 ; CHECK-NEXT: mvn w8, w0
; CHECK-NEXT: asr w0, w8, #31 ; CHECK-NEXT: asr w0, w8, #31
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt i32 %x, -1 %c = icmp sgt i32 %x, -1
%e = sext i1 %c to i32 %e = sext i1 %c to i32
ret i32 %e ret i32 %e
} }
define i32 @add_sext_ifpos(i32 %x) { define i32 @add_sext_ifpos(i32 %x) {
; CHECK-LABEL: add_sext_ifpos: ; CHECK-LABEL: add_sext_ifpos:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: lsr w8, w0, #31 ; CHECK-NEXT: lsr w8, w0, #31
; CHECK-NEXT: add w0, w8, #41 // =41 ; CHECK-NEXT: add w0, w8, #41
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt i32 %x, -1 %c = icmp sgt i32 %x, -1
%e = sext i1 %c to i32 %e = sext i1 %c to i32
%r = add i32 %e, 42 %r = add i32 %e, 42
ret i32 %r ret i32 %r
} }
define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) { define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: add_sext_ifpos_vec_splat: ; CHECK-LABEL: add_sext_ifpos_vec_splat:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s ; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s
; CHECK-NEXT: movi v1.4s, #42 ; CHECK-NEXT: movi v1.4s, #42
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = sext <4 x i1> %c to <4 x i32> %e = sext <4 x i1> %c to <4 x i32>
%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42> %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
ret <4 x i32> %r ret <4 x i32> %r
} }
define i32 @sel_ifpos_fval_bigger(i32 %x) { define i32 @sel_ifpos_fval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifpos_fval_bigger: ; CHECK-LABEL: sel_ifpos_fval_bigger:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w8, #41 ; CHECK-NEXT: mov w8, #41
; CHECK-NEXT: cinc w0, w8, lt ; CHECK-NEXT: cinc w0, w8, lt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp sgt i32 %x, -1 %c = icmp sgt i32 %x, -1
%r = select i1 %c, i32 41, i32 42 %r = select i1 %c, i32 41, i32 42
ret i32 %r ret i32 %r
} }
; If negative... ; If negative...
define i32 @zext_ifneg(i32 %x) { define i32 @zext_ifneg(i32 %x) {
; CHECK-LABEL: zext_ifneg: ; CHECK-LABEL: zext_ifneg:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: lsr w0, w0, #31 ; CHECK-NEXT: lsr w0, w0, #31
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp slt i32 %x, 0 %c = icmp slt i32 %x, 0
%r = zext i1 %c to i32 %r = zext i1 %c to i32
ret i32 %r ret i32 %r
} }
define i32 @add_zext_ifneg(i32 %x) { define i32 @add_zext_ifneg(i32 %x) {
; CHECK-LABEL: add_zext_ifneg: ; CHECK-LABEL: add_zext_ifneg:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: lsr w8, w0, #31 ; CHECK-NEXT: lsr w8, w0, #31
; CHECK-NEXT: add w0, w8, #41 // =41 ; CHECK-NEXT: add w0, w8, #41
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp slt i32 %x, 0 %c = icmp slt i32 %x, 0
%e = zext i1 %c to i32 %e = zext i1 %c to i32
%r = add i32 %e, 41 %r = add i32 %e, 41
ret i32 %r ret i32 %r
} }
define i32 @sel_ifneg_tval_bigger(i32 %x) { define i32 @sel_ifneg_tval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifneg_tval_bigger: ; CHECK-LABEL: sel_ifneg_tval_bigger:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w8, #41 ; CHECK-NEXT: mov w8, #41
; CHECK-NEXT: cinc w0, w8, lt ; CHECK-NEXT: cinc w0, w8, lt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp slt i32 %x, 0 %c = icmp slt i32 %x, 0
%r = select i1 %c, i32 42, i32 41 %r = select i1 %c, i32 42, i32 41
ret i32 %r ret i32 %r
} }
define i32 @sext_ifneg(i32 %x) { define i32 @sext_ifneg(i32 %x) {
; CHECK-LABEL: sext_ifneg: ; CHECK-LABEL: sext_ifneg:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: asr w0, w0, #31 ; CHECK-NEXT: asr w0, w0, #31
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp slt i32 %x, 0 %c = icmp slt i32 %x, 0
%r = sext i1 %c to i32 %r = sext i1 %c to i32
ret i32 %r ret i32 %r
} }
define i32 @add_sext_ifneg(i32 %x) { define i32 @add_sext_ifneg(i32 %x) {
; CHECK-LABEL: add_sext_ifneg: ; CHECK-LABEL: add_sext_ifneg:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: asr w8, w0, #31 ; CHECK-NEXT: asr w8, w0, #31
; CHECK-NEXT: add w0, w8, #42 // =42 ; CHECK-NEXT: add w0, w8, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp slt i32 %x, 0 %c = icmp slt i32 %x, 0
%e = sext i1 %c to i32 %e = sext i1 %c to i32
%r = add i32 %e, 42 %r = add i32 %e, 42
ret i32 %r ret i32 %r
} }
define i32 @sel_ifneg_fval_bigger(i32 %x) { define i32 @sel_ifneg_fval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifneg_fval_bigger: ; CHECK-LABEL: sel_ifneg_fval_bigger:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w8, #41 ; CHECK-NEXT: mov w8, #41
; CHECK-NEXT: cinc w0, w8, ge ; CHECK-NEXT: cinc w0, w8, ge
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp slt i32 %x, 0 %c = icmp slt i32 %x, 0
%r = select i1 %c, i32 41, i32 42 %r = select i1 %c, i32 41, i32 42
ret i32 %r ret i32 %r
} }
define i32 @add_lshr_not(i32 %x) { define i32 @add_lshr_not(i32 %x) {
; CHECK-LABEL: add_lshr_not: ; CHECK-LABEL: add_lshr_not:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: asr w8, w0, #31 ; CHECK-NEXT: asr w8, w0, #31
; CHECK-NEXT: add w0, w8, #42 // =42 ; CHECK-NEXT: add w0, w8, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%not = xor i32 %x, -1 %not = xor i32 %x, -1
%sh = lshr i32 %not, 31 %sh = lshr i32 %not, 31
%r = add i32 %sh, 41 %r = add i32 %sh, 41
ret i32 %r ret i32 %r
} }
define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) { define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%r = sub <4 x i32> %y, %sh %r = sub <4 x i32> %y, %sh
ret <4 x i32> %r ret <4 x i32> %r
} }
define i32 @sub_const_op_lshr(i32 %x) { define i32 @sub_const_op_lshr(i32 %x) {
; CHECK-LABEL: sub_const_op_lshr: ; CHECK-LABEL: sub_const_op_lshr:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: asr w8, w0, #31 ; CHECK-NEXT: asr w8, w0, #31
; CHECK-NEXT: add w0, w8, #43 // =43 ; CHECK-NEXT: add w0, w8, #43
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sh = lshr i32 %x, 31 %sh = lshr i32 %x, 31
%r = sub i32 43, %sh %r = sub i32 43, %sh
ret i32 %r ret i32 %r
} }
define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) { define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) {
; CHECK-LABEL: sub_const_op_lshr_vec: ; CHECK-LABEL: sub_const_op_lshr_vec:
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llvm/test/CodeGen/AArch64/signed-truncation-check.ll

Show First 20 Lines • Show All 267 Lines • ▼ Show 20 Lines
; ---------------------------------------------------------------------------- ; ; ---------------------------------------------------------------------------- ;
; Adding not a constant ; Adding not a constant
define i1 @add_ultcmp_bad_i16_i8_add(i16 %x, i16 %y) nounwind { define i1 @add_ultcmp_bad_i16_i8_add(i16 %x, i16 %y) nounwind {
; CHECK-LABEL: add_ultcmp_bad_i16_i8_add: ; CHECK-LABEL: add_ultcmp_bad_i16_i8_add:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1 ; CHECK-NEXT: add w8, w0, w1
; CHECK-NEXT: and w8, w8, #0xffff ; CHECK-NEXT: and w8, w8, #0xffff
; CHECK-NEXT: cmp w8, #256 // =256 ; CHECK-NEXT: cmp w8, #256
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i16 %x, %y %tmp0 = add i16 %x, %y
%tmp1 = icmp ult i16 %tmp0, 256 ; 1U << 8 %tmp1 = icmp ult i16 %tmp0, 256 ; 1U << 8
ret i1 %tmp1 ret i1 %tmp1
} }
; Comparing not with a constant ; Comparing not with a constant
define i1 @add_ultcmp_bad_i16_i8_cmp(i16 %x, i16 %y) nounwind { define i1 @add_ultcmp_bad_i16_i8_cmp(i16 %x, i16 %y) nounwind {
; CHECK-LABEL: add_ultcmp_bad_i16_i8_cmp: ; CHECK-LABEL: add_ultcmp_bad_i16_i8_cmp:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #128 // =128 ; CHECK-NEXT: add w8, w0, #128
; CHECK-NEXT: and w8, w8, #0xffff ; CHECK-NEXT: and w8, w8, #0xffff
; CHECK-NEXT: cmp w8, w1, uxth ; CHECK-NEXT: cmp w8, w1, uxth
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i16 %x, 128 ; 1U << (8-1) %tmp0 = add i16 %x, 128 ; 1U << (8-1)
%tmp1 = icmp ult i16 %tmp0, %y %tmp1 = icmp ult i16 %tmp0, %y
ret i1 %tmp1 ret i1 %tmp1
} }
; Second constant is not larger than the first one ; Second constant is not larger than the first one
define i1 @add_ultcmp_bad_i8_i16(i16 %x) nounwind { define i1 @add_ultcmp_bad_i8_i16(i16 %x) nounwind {
; CHECK-LABEL: add_ultcmp_bad_i8_i16: ; CHECK-LABEL: add_ultcmp_bad_i8_i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff ; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: add w8, w8, #128 // =128 ; CHECK-NEXT: add w8, w8, #128
; CHECK-NEXT: lsr w0, w8, #16 ; CHECK-NEXT: lsr w0, w8, #16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i16 %x, 128 ; 1U << (8-1) %tmp0 = add i16 %x, 128 ; 1U << (8-1)
%tmp1 = icmp ult i16 %tmp0, 128 ; 1U << (8-1) %tmp1 = icmp ult i16 %tmp0, 128 ; 1U << (8-1)
ret i1 %tmp1 ret i1 %tmp1
} }
; First constant is not power of two ; First constant is not power of two
define i1 @add_ultcmp_bad_i16_i8_c0notpoweroftwo(i16 %x) nounwind { define i1 @add_ultcmp_bad_i16_i8_c0notpoweroftwo(i16 %x) nounwind {
; CHECK-LABEL: add_ultcmp_bad_i16_i8_c0notpoweroftwo: ; CHECK-LABEL: add_ultcmp_bad_i16_i8_c0notpoweroftwo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #192 // =192 ; CHECK-NEXT: add w8, w0, #192
; CHECK-NEXT: and w8, w8, #0xffff ; CHECK-NEXT: and w8, w8, #0xffff
; CHECK-NEXT: cmp w8, #256 // =256 ; CHECK-NEXT: cmp w8, #256
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i16 %x, 192 ; (1U << (8-1)) + (1U << (8-1-1)) %tmp0 = add i16 %x, 192 ; (1U << (8-1)) + (1U << (8-1-1))
%tmp1 = icmp ult i16 %tmp0, 256 ; 1U << 8 %tmp1 = icmp ult i16 %tmp0, 256 ; 1U << 8
ret i1 %tmp1 ret i1 %tmp1
} }
; Second constant is not power of two ; Second constant is not power of two
define i1 @add_ultcmp_bad_i16_i8_c1notpoweroftwo(i16 %x) nounwind { define i1 @add_ultcmp_bad_i16_i8_c1notpoweroftwo(i16 %x) nounwind {
; CHECK-LABEL: add_ultcmp_bad_i16_i8_c1notpoweroftwo: ; CHECK-LABEL: add_ultcmp_bad_i16_i8_c1notpoweroftwo:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #128 // =128 ; CHECK-NEXT: add w8, w0, #128
; CHECK-NEXT: and w8, w8, #0xffff ; CHECK-NEXT: and w8, w8, #0xffff
; CHECK-NEXT: cmp w8, #768 // =768 ; CHECK-NEXT: cmp w8, #768
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i16 %x, 128 ; 1U << (8-1) %tmp0 = add i16 %x, 128 ; 1U << (8-1)
%tmp1 = icmp ult i16 %tmp0, 768 ; (1U << 8)) + (1U << (8+1)) %tmp1 = icmp ult i16 %tmp0, 768 ; (1U << 8)) + (1U << (8+1))
ret i1 %tmp1 ret i1 %tmp1
} }
; Magic check fails, 64 << 1 != 256 ; Magic check fails, 64 << 1 != 256
define i1 @add_ultcmp_bad_i16_i8_magic(i16 %x) nounwind { define i1 @add_ultcmp_bad_i16_i8_magic(i16 %x) nounwind {
; CHECK-LABEL: add_ultcmp_bad_i16_i8_magic: ; CHECK-LABEL: add_ultcmp_bad_i16_i8_magic:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #64 // =64 ; CHECK-NEXT: add w8, w0, #64
; CHECK-NEXT: and w8, w8, #0xffff ; CHECK-NEXT: and w8, w8, #0xffff
; CHECK-NEXT: cmp w8, #256 // =256 ; CHECK-NEXT: cmp w8, #256
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i16 %x, 64 ; 1U << (8-1-1) %tmp0 = add i16 %x, 64 ; 1U << (8-1-1)
%tmp1 = icmp ult i16 %tmp0, 256 ; 1U << 8 %tmp1 = icmp ult i16 %tmp0, 256 ; 1U << 8
ret i1 %tmp1 ret i1 %tmp1
} }
; Bad 'destination type' ; Bad 'destination type'
define i1 @add_ultcmp_bad_i16_i4(i16 %x) nounwind { define i1 @add_ultcmp_bad_i16_i4(i16 %x) nounwind {
; CHECK-LABEL: add_ultcmp_bad_i16_i4: ; CHECK-LABEL: add_ultcmp_bad_i16_i4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #8 // =8 ; CHECK-NEXT: add w8, w0, #8
; CHECK-NEXT: and w8, w8, #0xffff ; CHECK-NEXT: and w8, w8, #0xffff
; CHECK-NEXT: cmp w8, #16 // =16 ; CHECK-NEXT: cmp w8, #16
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i16 %x, 8 ; 1U << (4-1) %tmp0 = add i16 %x, 8 ; 1U << (4-1)
%tmp1 = icmp ult i16 %tmp0, 16 ; 1U << 4 %tmp1 = icmp ult i16 %tmp0, 16 ; 1U << 4
ret i1 %tmp1 ret i1 %tmp1
} }
; Bad storage type ; Bad storage type
define i1 @add_ultcmp_bad_i24_i8(i24 %x) nounwind { define i1 @add_ultcmp_bad_i24_i8(i24 %x) nounwind {
; CHECK-LABEL: add_ultcmp_bad_i24_i8: ; CHECK-LABEL: add_ultcmp_bad_i24_i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #128 // =128 ; CHECK-NEXT: add w8, w0, #128
; CHECK-NEXT: and w8, w8, #0xffffff ; CHECK-NEXT: and w8, w8, #0xffffff
; CHECK-NEXT: cmp w8, #256 // =256 ; CHECK-NEXT: cmp w8, #256
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i24 %x, 128 ; 1U << (8-1) %tmp0 = add i24 %x, 128 ; 1U << (8-1)
%tmp1 = icmp ult i24 %tmp0, 256 ; 1U << 8 %tmp1 = icmp ult i24 %tmp0, 256 ; 1U << 8
ret i1 %tmp1 ret i1 %tmp1
} }
define i1 @add_ulecmp_bad_i16_i8(i16 %x) nounwind { define i1 @add_ulecmp_bad_i16_i8(i16 %x) nounwind {
; CHECK-LABEL: add_ulecmp_bad_i16_i8: ; CHECK-LABEL: add_ulecmp_bad_i16_i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w0, #1 ; CHECK-NEXT: mov w0, #1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp0 = add i16 %x, 128 ; 1U << (8-1) %tmp0 = add i16 %x, 128 ; 1U << (8-1)
%tmp1 = icmp ule i16 %tmp0, -1 ; when we +1 it, it will wrap to 0 %tmp1 = icmp ule i16 %tmp0, -1 ; when we +1 it, it will wrap to 0
ret i1 %tmp1 ret i1 %tmp1
} }

llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
; Scalar tests. ; Scalar tests.
; add (add %x, C), %y ; add (add %x, C), %y
; Outer 'add' is commutative - 2 variants. ; Outer 'add' is commutative - 2 variants.
define i32 @sink_add_of_const_to_add0(i32 %a, i32 %b) { define i32 @sink_add_of_const_to_add0(i32 %a, i32 %b) {
; CHECK-LABEL: sink_add_of_const_to_add0: ; CHECK-LABEL: sink_add_of_const_to_add0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1 ; CHECK-NEXT: add w8, w0, w1
; CHECK-NEXT: add w0, w8, #32 // =32 ; CHECK-NEXT: add w0, w8, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add i32 %a, 32 ; constant always on RHS %t0 = add i32 %a, 32 ; constant always on RHS
%r = add i32 %t0, %b %r = add i32 %t0, %b
ret i32 %r ret i32 %r
} }
define i32 @sink_add_of_const_to_add1(i32 %a, i32 %b) { define i32 @sink_add_of_const_to_add1(i32 %a, i32 %b) {
; CHECK-LABEL: sink_add_of_const_to_add1: ; CHECK-LABEL: sink_add_of_const_to_add1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1 ; CHECK-NEXT: add w8, w0, w1
; CHECK-NEXT: add w0, w8, #32 // =32 ; CHECK-NEXT: add w0, w8, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add i32 %a, 32 ; constant always on RHS %t0 = add i32 %a, 32 ; constant always on RHS
%r = add i32 %b, %t0 %r = add i32 %b, %t0
ret i32 %r ret i32 %r
} }
; add (sub %x, C), %y ; add (sub %x, C), %y
; Outer 'add' is commutative - 2 variants. ; Outer 'add' is commutative - 2 variants.
define i32 @sink_sub_of_const_to_add0(i32 %a, i32 %b) { define i32 @sink_sub_of_const_to_add0(i32 %a, i32 %b) {
; CHECK-LABEL: sink_sub_of_const_to_add0: ; CHECK-LABEL: sink_sub_of_const_to_add0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1 ; CHECK-NEXT: add w8, w0, w1
; CHECK-NEXT: sub w0, w8, #32 // =32 ; CHECK-NEXT: sub w0, w8, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 %a, 32 %t0 = sub i32 %a, 32
%r = add i32 %t0, %b %r = add i32 %t0, %b
ret i32 %r ret i32 %r
} }
define i32 @sink_sub_of_const_to_add1(i32 %a, i32 %b) { define i32 @sink_sub_of_const_to_add1(i32 %a, i32 %b) {
; CHECK-LABEL: sink_sub_of_const_to_add1: ; CHECK-LABEL: sink_sub_of_const_to_add1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1 ; CHECK-NEXT: add w8, w0, w1
; CHECK-NEXT: sub w0, w8, #32 // =32 ; CHECK-NEXT: sub w0, w8, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 %a, 32 %t0 = sub i32 %a, 32
%r = add i32 %b, %t0 %r = add i32 %b, %t0
ret i32 %r ret i32 %r
} }
; add (sub C, %x), %y ; add (sub C, %x), %y
; Outer 'add' is commutative - 2 variants. ; Outer 'add' is commutative - 2 variants.
define i32 @sink_sub_from_const_to_add0(i32 %a, i32 %b) { define i32 @sink_sub_from_const_to_add0(i32 %a, i32 %b) {
; CHECK-LABEL: sink_sub_from_const_to_add0: ; CHECK-LABEL: sink_sub_from_const_to_add0:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0 ; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: add w0, w8, #32 // =32 ; CHECK-NEXT: add w0, w8, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 32, %a %t0 = sub i32 32, %a
%r = add i32 %t0, %b %r = add i32 %t0, %b
ret i32 %r ret i32 %r
} }
define i32 @sink_sub_from_const_to_add1(i32 %a, i32 %b) { define i32 @sink_sub_from_const_to_add1(i32 %a, i32 %b) {
; CHECK-LABEL: sink_sub_from_const_to_add1: ; CHECK-LABEL: sink_sub_from_const_to_add1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0 ; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: add w0, w8, #32 // =32 ; CHECK-NEXT: add w0, w8, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 32, %a %t0 = sub i32 32, %a
%r = add i32 %b, %t0 %r = add i32 %b, %t0
ret i32 %r ret i32 %r
} }
; sub (add %x, C), %y ; sub (add %x, C), %y
; sub %y, (add %x, C) ; sub %y, (add %x, C)
define i32 @sink_add_of_const_to_sub(i32 %a, i32 %b) { define i32 @sink_add_of_const_to_sub(i32 %a, i32 %b) {
; CHECK-LABEL: sink_add_of_const_to_sub: ; CHECK-LABEL: sink_add_of_const_to_sub:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w0, w1 ; CHECK-NEXT: sub w8, w0, w1
; CHECK-NEXT: add w0, w8, #32 // =32 ; CHECK-NEXT: add w0, w8, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add i32 %a, 32 ; constant always on RHS %t0 = add i32 %a, 32 ; constant always on RHS
%r = sub i32 %t0, %b %r = sub i32 %t0, %b
ret i32 %r ret i32 %r
} }
define i32 @sink_add_of_const_to_sub2(i32 %a, i32 %b) { define i32 @sink_add_of_const_to_sub2(i32 %a, i32 %b) {
; CHECK-LABEL: sink_add_of_const_to_sub2: ; CHECK-LABEL: sink_add_of_const_to_sub2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0 ; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: sub w0, w8, #32 // =32 ; CHECK-NEXT: sub w0, w8, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add i32 %a, 32 ; constant always on RHS %t0 = add i32 %a, 32 ; constant always on RHS
%r = sub i32 %b, %t0 %r = sub i32 %b, %t0
ret i32 %r ret i32 %r
} }
; sub (sub %x, C), %y ; sub (sub %x, C), %y
; sub %y, (sub %x, C) ; sub %y, (sub %x, C)
define i32 @sink_sub_of_const_to_sub(i32 %a, i32 %b) { define i32 @sink_sub_of_const_to_sub(i32 %a, i32 %b) {
; CHECK-LABEL: sink_sub_of_const_to_sub: ; CHECK-LABEL: sink_sub_of_const_to_sub:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w0, w1 ; CHECK-NEXT: sub w8, w0, w1
; CHECK-NEXT: sub w0, w8, #32 // =32 ; CHECK-NEXT: sub w0, w8, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 %a, 32 %t0 = sub i32 %a, 32
%r = sub i32 %t0, %b %r = sub i32 %t0, %b
ret i32 %r ret i32 %r
} }
define i32 @sink_sub_of_const_to_sub2(i32 %a, i32 %b) { define i32 @sink_sub_of_const_to_sub2(i32 %a, i32 %b) {
; CHECK-LABEL: sink_sub_of_const_to_sub2: ; CHECK-LABEL: sink_sub_of_const_to_sub2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w1, w0 ; CHECK-NEXT: sub w8, w1, w0
; CHECK-NEXT: add w0, w8, #32 // =32 ; CHECK-NEXT: add w0, w8, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 %a, 32 %t0 = sub i32 %a, 32
%r = sub i32 %b, %t0 %r = sub i32 %b, %t0
ret i32 %r ret i32 %r
} }
; sub (sub C, %x), %y ; sub (sub C, %x), %y
; sub %y, (sub C, %x) ; sub %y, (sub C, %x)
define i32 @sink_sub_from_const_to_sub(i32 %a, i32 %b) { define i32 @sink_sub_from_const_to_sub(i32 %a, i32 %b) {
; CHECK-LABEL: sink_sub_from_const_to_sub: ; CHECK-LABEL: sink_sub_from_const_to_sub:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1 ; CHECK-NEXT: add w8, w0, w1
; CHECK-NEXT: mov w9, #32 ; CHECK-NEXT: mov w9, #32
; CHECK-NEXT: sub w0, w9, w8 ; CHECK-NEXT: sub w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 32, %a %t0 = sub i32 32, %a
%r = sub i32 %t0, %b %r = sub i32 %t0, %b
ret i32 %r ret i32 %r
} }
define i32 @sink_sub_from_const_to_sub2(i32 %a, i32 %b) { define i32 @sink_sub_from_const_to_sub2(i32 %a, i32 %b) {
; CHECK-LABEL: sink_sub_from_const_to_sub2: ; CHECK-LABEL: sink_sub_from_const_to_sub2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1 ; CHECK-NEXT: add w8, w0, w1
; CHECK-NEXT: sub w0, w8, #32 // =32 ; CHECK-NEXT: sub w0, w8, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 32, %a %t0 = sub i32 32, %a
%r = sub i32 %b, %t0 %r = sub i32 %b, %t0
ret i32 %r ret i32 %r
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; Basic vector tests. Here it is easier to see where the constant operand is. ; Basic vector tests. Here it is easier to see where the constant operand is.
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llvm/test/CodeGen/AArch64/split-vector-insert.ll

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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-4 ; CHECK-NEXT: addvl sp, sp, #-4
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: cntd x9 ; CHECK-NEXT: cntd x9
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: str q1, [sp] ; CHECK-NEXT: str q1, [sp]
; CHECK-NEXT: sub x9, x9, #2 // =2 ; CHECK-NEXT: sub x9, x9, #2
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT: mov w8, #2 ; CHECK-NEXT: mov w8, #2
; CHECK-NEXT: cmp x9, #2 // =2 ; CHECK-NEXT: cmp x9, #2
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: addvl x10, sp, #1 ; CHECK-NEXT: addvl x10, sp, #1
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: st1d { z0.d }, p0, [sp, #1, mul vl] ; CHECK-NEXT: st1d { z0.d }, p0, [sp, #1, mul vl]
; CHECK-NEXT: str q2, [x10, x8] ; CHECK-NEXT: str q2, [x10, x8]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #1, mul vl] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: mov w8, #4 ; CHECK-NEXT: mov w8, #4
; CHECK-NEXT: cmp x9, #4 // =4 ; CHECK-NEXT: cmp x9, #4
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: addvl x10, sp, #2 ; CHECK-NEXT: addvl x10, sp, #2
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: st1d { z0.d }, p0, [sp, #2, mul vl] ; CHECK-NEXT: st1d { z0.d }, p0, [sp, #2, mul vl]
; CHECK-NEXT: str q3, [x10, x8] ; CHECK-NEXT: str q3, [x10, x8]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #2, mul vl] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #2, mul vl]
; CHECK-NEXT: mov w8, #6 ; CHECK-NEXT: mov w8, #6
; CHECK-NEXT: cmp x9, #6 // =6 ; CHECK-NEXT: cmp x9, #6
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: addvl x10, sp, #3 ; CHECK-NEXT: addvl x10, sp, #3
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: st1d { z0.d }, p0, [sp, #3, mul vl] ; CHECK-NEXT: st1d { z0.d }, p0, [sp, #3, mul vl]
; CHECK-NEXT: str q4, [x10, x8] ; CHECK-NEXT: str q4, [x10, x8]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #3, mul vl] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #3, mul vl]
; CHECK-NEXT: addvl sp, sp, #4 ; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-4 ; CHECK-NEXT: addvl sp, sp, #-4
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: cntd x9 ; CHECK-NEXT: cntd x9
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: str q1, [sp] ; CHECK-NEXT: str q1, [sp]
; CHECK-NEXT: sub x9, x9, #2 // =2 ; CHECK-NEXT: sub x9, x9, #2
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT: mov w8, #2 ; CHECK-NEXT: mov w8, #2
; CHECK-NEXT: cmp x9, #2 // =2 ; CHECK-NEXT: cmp x9, #2
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: addvl x10, sp, #1 ; CHECK-NEXT: addvl x10, sp, #1
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: st1d { z0.d }, p0, [sp, #1, mul vl] ; CHECK-NEXT: st1d { z0.d }, p0, [sp, #1, mul vl]
; CHECK-NEXT: str q2, [x10, x8] ; CHECK-NEXT: str q2, [x10, x8]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #1, mul vl] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: mov w8, #4 ; CHECK-NEXT: mov w8, #4
; CHECK-NEXT: cmp x9, #4 // =4 ; CHECK-NEXT: cmp x9, #4
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: addvl x10, sp, #2 ; CHECK-NEXT: addvl x10, sp, #2
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: st1d { z0.d }, p0, [sp, #2, mul vl] ; CHECK-NEXT: st1d { z0.d }, p0, [sp, #2, mul vl]
; CHECK-NEXT: str q3, [x10, x8] ; CHECK-NEXT: str q3, [x10, x8]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #2, mul vl] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #2, mul vl]
; CHECK-NEXT: mov w8, #6 ; CHECK-NEXT: mov w8, #6
; CHECK-NEXT: cmp x9, #6 // =6 ; CHECK-NEXT: cmp x9, #6
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: addvl x10, sp, #3 ; CHECK-NEXT: addvl x10, sp, #3
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: st1d { z0.d }, p0, [sp, #3, mul vl] ; CHECK-NEXT: st1d { z0.d }, p0, [sp, #3, mul vl]
; CHECK-NEXT: str q4, [x10, x8] ; CHECK-NEXT: str q4, [x10, x8]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #3, mul vl] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #3, mul vl]
; CHECK-NEXT: addvl sp, sp, #4 ; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> %a, <8 x double> %b, i64 0) %r = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> %a, <8 x double> %b, i64 0)
ret <vscale x 2 x double> %r ret <vscale x 2 x double> %r
} }

llvm/test/CodeGen/AArch64/srem-lkk.ll

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%3 = add i32 %1, %2 %3 = add i32 %1, %2
ret i32 %3 ret i32 %3
} }
; Don't fold for divisors that are a power of two. ; Don't fold for divisors that are a power of two.
define i32 @dont_fold_srem_power_of_two(i32 %x) { define i32 @dont_fold_srem_power_of_two(i32 %x) {
; CHECK-LABEL: dont_fold_srem_power_of_two: ; CHECK-LABEL: dont_fold_srem_power_of_two:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #63 // =63 ; CHECK-NEXT: add w8, w0, #63
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, w8, w0, lt ; CHECK-NEXT: csel w8, w8, w0, lt
; CHECK-NEXT: and w8, w8, #0xffffffc0 ; CHECK-NEXT: and w8, w8, #0xffffffc0
; CHECK-NEXT: sub w0, w0, w8 ; CHECK-NEXT: sub w0, w0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = srem i32 %x, 64 %1 = srem i32 %x, 64
ret i32 %1 ret i32 %1
} }
; Don't fold if the divisor is one. ; Don't fold if the divisor is one.
define i32 @dont_fold_srem_one(i32 %x) { define i32 @dont_fold_srem_one(i32 %x) {
; CHECK-LABEL: dont_fold_srem_one: ; CHECK-LABEL: dont_fold_srem_one:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = srem i32 %x, 1 %1 = srem i32 %x, 1
ret i32 %1 ret i32 %1
} }
; Don't fold if the divisor is 2^31. ; Don't fold if the divisor is 2^31.
define i32 @dont_fold_srem_i32_smax(i32 %x) { define i32 @dont_fold_srem_i32_smax(i32 %x) {
; CHECK-LABEL: dont_fold_srem_i32_smax: ; CHECK-LABEL: dont_fold_srem_i32_smax:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #2147483647 ; CHECK-NEXT: mov w8, #2147483647
; CHECK-NEXT: add w8, w0, w8 ; CHECK-NEXT: add w8, w0, w8
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, w8, w0, lt ; CHECK-NEXT: csel w8, w8, w0, lt
; CHECK-NEXT: and w8, w8, #0x80000000 ; CHECK-NEXT: and w8, w8, #0x80000000
; CHECK-NEXT: add w0, w0, w8 ; CHECK-NEXT: add w0, w0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = srem i32 %x, 2147483648 %1 = srem i32 %x, 2147483648
ret i32 %1 ret i32 %1
} }
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llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll

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; CHECK-NEXT: sbfx w8, w0, #0, #4 ; CHECK-NEXT: sbfx w8, w0, #0, #4
; CHECK-NEXT: movk w9, #10922, lsl #16 ; CHECK-NEXT: movk w9, #10922, lsl #16
; CHECK-NEXT: smull x9, w8, w9 ; CHECK-NEXT: smull x9, w8, w9
; CHECK-NEXT: lsr x10, x9, #63 ; CHECK-NEXT: lsr x10, x9, #63
; CHECK-NEXT: lsr x9, x9, #32 ; CHECK-NEXT: lsr x9, x9, #32
; CHECK-NEXT: add w9, w9, w10 ; CHECK-NEXT: add w9, w9, w10
; CHECK-NEXT: mov w10, #6 ; CHECK-NEXT: mov w10, #6
; CHECK-NEXT: msub w8, w9, w10, w8 ; CHECK-NEXT: msub w8, w9, w10, w8
; CHECK-NEXT: cmp w8, #1 // =1 ; CHECK-NEXT: cmp w8, #1
; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem i4 %X, 6 %srem = srem i4 %X, 6
%cmp = icmp eq i4 %srem, 1 %cmp = icmp eq i4 %srem, 1
ret i1 %cmp ret i1 %cmp
} }
define i1 @test_srem_pow2_setne(i6 %X) nounwind { define i1 @test_srem_pow2_setne(i6 %X) nounwind {
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llvm/test/CodeGen/AArch64/srem-seteq.ll

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; This is like test_srem_odd, except the divisor has bit 30 set. ; This is like test_srem_odd, except the divisor has bit 30 set.
define i32 @test_srem_odd_bit30(i32 %X) nounwind { define i32 @test_srem_odd_bit30(i32 %X) nounwind {
; CHECK-LABEL: test_srem_odd_bit30: ; CHECK-LABEL: test_srem_odd_bit30:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #43691 ; CHECK-NEXT: mov w8, #43691
; CHECK-NEXT: movk w8, #27306, lsl #16 ; CHECK-NEXT: movk w8, #27306, lsl #16
; CHECK-NEXT: orr w9, wzr, #0x1 ; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: madd w8, w0, w8, w9 ; CHECK-NEXT: madd w8, w0, w8, w9
; CHECK-NEXT: cmp w8, #3 // =3 ; CHECK-NEXT: cmp w8, #3
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem i32 %X, 1073741827 %srem = srem i32 %X, 1073741827
%cmp = icmp eq i32 %srem, 0 %cmp = icmp eq i32 %srem, 0
%ret = zext i1 %cmp to i32 %ret = zext i1 %cmp to i32
ret i32 %ret ret i32 %ret
} }
; This is like test_srem_odd, except the divisor has bit 31 set. ; This is like test_srem_odd, except the divisor has bit 31 set.
define i32 @test_srem_odd_bit31(i32 %X) nounwind { define i32 @test_srem_odd_bit31(i32 %X) nounwind {
; CHECK-LABEL: test_srem_odd_bit31: ; CHECK-LABEL: test_srem_odd_bit31:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #21845 ; CHECK-NEXT: mov w8, #21845
; CHECK-NEXT: movk w8, #54613, lsl #16 ; CHECK-NEXT: movk w8, #54613, lsl #16
; CHECK-NEXT: orr w9, wzr, #0x1 ; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: madd w8, w0, w8, w9 ; CHECK-NEXT: madd w8, w0, w8, w9
; CHECK-NEXT: cmp w8, #3 // =3 ; CHECK-NEXT: cmp w8, #3
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem i32 %X, 2147483651 %srem = srem i32 %X, 2147483651
%cmp = icmp eq i32 %srem, 0 %cmp = icmp eq i32 %srem, 0
%ret = zext i1 %cmp to i32 %ret = zext i1 %cmp to i32
ret i32 %ret ret i32 %ret
} }
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define i32 @test_srem_even_bit30(i32 %X) nounwind { define i32 @test_srem_even_bit30(i32 %X) nounwind {
; CHECK-LABEL: test_srem_even_bit30: ; CHECK-LABEL: test_srem_even_bit30:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #20165 ; CHECK-NEXT: mov w8, #20165
; CHECK-NEXT: movk w8, #64748, lsl #16 ; CHECK-NEXT: movk w8, #64748, lsl #16
; CHECK-NEXT: orr w9, wzr, #0x8 ; CHECK-NEXT: orr w9, wzr, #0x8
; CHECK-NEXT: madd w8, w0, w8, w9 ; CHECK-NEXT: madd w8, w0, w8, w9
; CHECK-NEXT: ror w8, w8, #3 ; CHECK-NEXT: ror w8, w8, #3
; CHECK-NEXT: cmp w8, #3 // =3 ; CHECK-NEXT: cmp w8, #3
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem i32 %X, 1073741928 %srem = srem i32 %X, 1073741928
%cmp = icmp eq i32 %srem, 0 %cmp = icmp eq i32 %srem, 0
%ret = zext i1 %cmp to i32 %ret = zext i1 %cmp to i32
ret i32 %ret ret i32 %ret
} }
; This is like test_srem_odd, except the divisor has bit 31 set. ; This is like test_srem_odd, except the divisor has bit 31 set.
define i32 @test_srem_even_bit31(i32 %X) nounwind { define i32 @test_srem_even_bit31(i32 %X) nounwind {
; CHECK-LABEL: test_srem_even_bit31: ; CHECK-LABEL: test_srem_even_bit31:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1285 ; CHECK-NEXT: mov w8, #1285
; CHECK-NEXT: movk w8, #50437, lsl #16 ; CHECK-NEXT: movk w8, #50437, lsl #16
; CHECK-NEXT: orr w9, wzr, #0x2 ; CHECK-NEXT: orr w9, wzr, #0x2
; CHECK-NEXT: madd w8, w0, w8, w9 ; CHECK-NEXT: madd w8, w0, w8, w9
; CHECK-NEXT: ror w8, w8, #1 ; CHECK-NEXT: ror w8, w8, #1
; CHECK-NEXT: cmp w8, #3 // =3 ; CHECK-NEXT: cmp w8, #3
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem i32 %X, 2147483750 %srem = srem i32 %X, 2147483750
%cmp = icmp eq i32 %srem, 0 %cmp = icmp eq i32 %srem, 0
%ret = zext i1 %cmp to i32 %ret = zext i1 %cmp to i32
ret i32 %ret ret i32 %ret
} }
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%ret = zext i1 %cmp to i32 %ret = zext i1 %cmp to i32
ret i32 %ret ret i32 %ret
} }
; We can lower remainder of division by powers of two much better elsewhere. ; We can lower remainder of division by powers of two much better elsewhere.
define i32 @test_srem_pow2(i32 %X) nounwind { define i32 @test_srem_pow2(i32 %X) nounwind {
; CHECK-LABEL: test_srem_pow2: ; CHECK-LABEL: test_srem_pow2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, #15 // =15 ; CHECK-NEXT: add w8, w0, #15
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, w8, w0, lt ; CHECK-NEXT: csel w8, w8, w0, lt
; CHECK-NEXT: and w8, w8, #0xfffffff0 ; CHECK-NEXT: and w8, w8, #0xfffffff0
; CHECK-NEXT: cmp w0, w8 ; CHECK-NEXT: cmp w0, w8
; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem i32 %X, 16 %srem = srem i32 %X, 16
%cmp = icmp eq i32 %srem, 0 %cmp = icmp eq i32 %srem, 0
%ret = zext i1 %cmp to i32 %ret = zext i1 %cmp to i32
ret i32 %ret ret i32 %ret
} }
; The fold is only valid for positive divisors, and we can't negate INT_MIN. ; The fold is only valid for positive divisors, and we can't negate INT_MIN.
define i32 @test_srem_int_min(i32 %X) nounwind { define i32 @test_srem_int_min(i32 %X) nounwind {
; CHECK-LABEL: test_srem_int_min: ; CHECK-LABEL: test_srem_int_min:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #2147483647 ; CHECK-NEXT: mov w8, #2147483647
; CHECK-NEXT: add w8, w0, w8 ; CHECK-NEXT: add w8, w0, w8
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, w8, w0, lt ; CHECK-NEXT: csel w8, w8, w0, lt
; CHECK-NEXT: and w8, w8, #0x80000000 ; CHECK-NEXT: and w8, w8, #0x80000000
; CHECK-NEXT: cmn w0, w8 ; CHECK-NEXT: cmn w0, w8
; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%srem = srem i32 %X, 2147483648 %srem = srem i32 %X, 2147483648
%cmp = icmp eq i32 %srem, 0 %cmp = icmp eq i32 %srem, 0
%ret = zext i1 %cmp to i32 %ret = zext i1 %cmp to i32
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llvm/test/CodeGen/AArch64/srem-vector-lkk.ll

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} }
; Don't fold for divisors that are a power of two. ; Don't fold for divisors that are a power of two.
define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) { define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
; CHECK-LABEL: dont_fold_srem_power_of_two: ; CHECK-LABEL: dont_fold_srem_power_of_two:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: smov w8, v0.h[1] ; CHECK-NEXT: smov w8, v0.h[1]
; CHECK-NEXT: add w12, w8, #31 // =31 ; CHECK-NEXT: add w12, w8, #31
; CHECK-NEXT: cmp w8, #0 // =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: mov w11, #37253 ; CHECK-NEXT: mov w11, #37253
; CHECK-NEXT: csel w12, w12, w8, lt ; CHECK-NEXT: csel w12, w12, w8, lt
; CHECK-NEXT: smov w9, v0.h[0] ; CHECK-NEXT: smov w9, v0.h[0]
; CHECK-NEXT: smov w10, v0.h[3] ; CHECK-NEXT: smov w10, v0.h[3]
; CHECK-NEXT: movk w11, #44150, lsl #16 ; CHECK-NEXT: movk w11, #44150, lsl #16
; CHECK-NEXT: and w12, w12, #0xffffffe0 ; CHECK-NEXT: and w12, w12, #0xffffffe0
; CHECK-NEXT: sub w8, w8, w12 ; CHECK-NEXT: sub w8, w8, w12
; CHECK-NEXT: add w12, w9, #63 // =63 ; CHECK-NEXT: add w12, w9, #63
; CHECK-NEXT: smull x11, w10, w11 ; CHECK-NEXT: smull x11, w10, w11
; CHECK-NEXT: cmp w9, #0 // =0 ; CHECK-NEXT: cmp w9, #0
; CHECK-NEXT: lsr x11, x11, #32 ; CHECK-NEXT: lsr x11, x11, #32
; CHECK-NEXT: csel w12, w12, w9, lt ; CHECK-NEXT: csel w12, w12, w9, lt
; CHECK-NEXT: add w11, w11, w10 ; CHECK-NEXT: add w11, w11, w10
; CHECK-NEXT: and w12, w12, #0xffffffc0 ; CHECK-NEXT: and w12, w12, #0xffffffc0
; CHECK-NEXT: sub w9, w9, w12 ; CHECK-NEXT: sub w9, w9, w12
; CHECK-NEXT: asr w12, w11, #6 ; CHECK-NEXT: asr w12, w11, #6
; CHECK-NEXT: add w11, w12, w11, lsr #31 ; CHECK-NEXT: add w11, w12, w11, lsr #31
; CHECK-NEXT: smov w12, v0.h[2] ; CHECK-NEXT: smov w12, v0.h[2]
; CHECK-NEXT: fmov s0, w9 ; CHECK-NEXT: fmov s0, w9
; CHECK-NEXT: add w9, w12, #7 // =7 ; CHECK-NEXT: add w9, w12, #7
; CHECK-NEXT: cmp w12, #0 // =0 ; CHECK-NEXT: cmp w12, #0
; CHECK-NEXT: csel w9, w9, w12, lt ; CHECK-NEXT: csel w9, w9, w12, lt
; CHECK-NEXT: and w9, w9, #0xfffffff8 ; CHECK-NEXT: and w9, w9, #0xfffffff8
; CHECK-NEXT: sub w9, w12, w9 ; CHECK-NEXT: sub w9, w12, w9
; CHECK-NEXT: mov v0.h[1], w8 ; CHECK-NEXT: mov v0.h[1], w8
; CHECK-NEXT: mov w8, #95 ; CHECK-NEXT: mov w8, #95
; CHECK-NEXT: mov v0.h[2], w9 ; CHECK-NEXT: mov v0.h[2], w9
; CHECK-NEXT: msub w8, w11, w8, w10 ; CHECK-NEXT: msub w8, w11, w8, w10
; CHECK-NEXT: mov v0.h[3], w8 ; CHECK-NEXT: mov v0.h[3], w8
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; CHECK-NEXT: movk w10, #24749, lsl #16 ; CHECK-NEXT: movk w10, #24749, lsl #16
; CHECK-NEXT: smull x10, w12, w10 ; CHECK-NEXT: smull x10, w12, w10
; CHECK-NEXT: lsr x11, x10, #63 ; CHECK-NEXT: lsr x11, x10, #63
; CHECK-NEXT: asr x10, x10, #43 ; CHECK-NEXT: asr x10, x10, #43
; CHECK-NEXT: smov w8, v0.h[1] ; CHECK-NEXT: smov w8, v0.h[1]
; CHECK-NEXT: add w10, w10, w11 ; CHECK-NEXT: add w10, w10, w11
; CHECK-NEXT: mov w11, #32767 ; CHECK-NEXT: mov w11, #32767
; CHECK-NEXT: add w11, w8, w11 ; CHECK-NEXT: add w11, w8, w11
; CHECK-NEXT: cmp w8, #0 // =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: csel w11, w11, w8, lt ; CHECK-NEXT: csel w11, w11, w8, lt
; CHECK-NEXT: and w11, w11, #0xffff8000 ; CHECK-NEXT: and w11, w11, #0xffff8000
; CHECK-NEXT: sub w8, w8, w11 ; CHECK-NEXT: sub w8, w8, w11
; CHECK-NEXT: movi d0, #0000000000000000 ; CHECK-NEXT: movi d0, #0000000000000000
; CHECK-NEXT: mov v0.h[1], w8 ; CHECK-NEXT: mov v0.h[1], w8
; CHECK-NEXT: mov w8, #5423 ; CHECK-NEXT: mov w8, #5423
; CHECK-NEXT: mov v0.h[2], w9 ; CHECK-NEXT: mov v0.h[2], w9
; CHECK-NEXT: msub w8, w10, w8, w12 ; CHECK-NEXT: msub w8, w10, w8, w12
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llvm/test/CodeGen/AArch64/ssub_sat.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
declare i4 @llvm.ssub.sat.i4(i4, i4) declare i4 @llvm.ssub.sat.i4(i4, i4)
declare i8 @llvm.ssub.sat.i8(i8, i8) declare i8 @llvm.ssub.sat.i8(i8, i8)
declare i16 @llvm.ssub.sat.i16(i16, i16) declare i16 @llvm.ssub.sat.i16(i16, i16)
declare i32 @llvm.ssub.sat.i32(i32, i32) declare i32 @llvm.ssub.sat.i32(i32, i32)
declare i64 @llvm.ssub.sat.i64(i64, i64) declare i64 @llvm.ssub.sat.i64(i64, i64)
declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>) declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
define i32 @func(i32 %x, i32 %y) nounwind { define i32 @func(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: func: ; CHECK-LABEL: func:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: subs w8, w0, w1 ; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: mov w9, #2147483647 ; CHECK-NEXT: mov w9, #2147483647
; CHECK-NEXT: cmp w8, #0 // =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: cinv w8, w9, ge ; CHECK-NEXT: cinv w8, w9, ge
; CHECK-NEXT: subs w9, w0, w1 ; CHECK-NEXT: subs w9, w0, w1
; CHECK-NEXT: csel w0, w8, w9, vs ; CHECK-NEXT: csel w0, w8, w9, vs
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y); %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y);
ret i32 %tmp; ret i32 %tmp;
} }
define i64 @func2(i64 %x, i64 %y) nounwind { define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: func2: ; CHECK-LABEL: func2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x0, x1 ; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: mov x9, #9223372036854775807 ; CHECK-NEXT: mov x9, #9223372036854775807
; CHECK-NEXT: cmp x8, #0 // =0 ; CHECK-NEXT: cmp x8, #0
; CHECK-NEXT: cinv x8, x9, ge ; CHECK-NEXT: cinv x8, x9, ge
; CHECK-NEXT: subs x9, x0, x1 ; CHECK-NEXT: subs x9, x0, x1
; CHECK-NEXT: csel x0, x8, x9, vs ; CHECK-NEXT: csel x0, x8, x9, vs
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y); %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y);
ret i64 %tmp; ret i64 %tmp;
} }
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} }
define i8 @func8(i8 %x, i8 %y) nounwind { define i8 @func8(i8 %x, i8 %y) nounwind {
; CHECK-LABEL: func8: ; CHECK-LABEL: func8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0 ; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: sub w8, w8, w1, sxtb ; CHECK-NEXT: sub w8, w8, w1, sxtb
; CHECK-NEXT: mov w9, #127 ; CHECK-NEXT: mov w9, #127
; CHECK-NEXT: cmp w8, #127 // =127 ; CHECK-NEXT: cmp w8, #127
; CHECK-NEXT: csel w8, w8, w9, lt ; CHECK-NEXT: csel w8, w8, w9, lt
; CHECK-NEXT: cmn w8, #128 // =128 ; CHECK-NEXT: cmn w8, #128
; CHECK-NEXT: mov w9, #-128 ; CHECK-NEXT: mov w9, #-128
; CHECK-NEXT: csel w0, w8, w9, gt ; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y); %tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y);
ret i8 %tmp; ret i8 %tmp;
} }
define i4 @func3(i4 %x, i4 %y) nounwind { define i4 @func3(i4 %x, i4 %y) nounwind {
; CHECK-LABEL: func3: ; CHECK-LABEL: func3:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: lsl w8, w1, #28 ; CHECK-NEXT: lsl w8, w1, #28
; CHECK-NEXT: sbfx w9, w0, #0, #4 ; CHECK-NEXT: sbfx w9, w0, #0, #4
; CHECK-NEXT: sub w8, w9, w8, asr #28 ; CHECK-NEXT: sub w8, w9, w8, asr #28
; CHECK-NEXT: mov w10, #7 ; CHECK-NEXT: mov w10, #7
; CHECK-NEXT: cmp w8, #7 // =7 ; CHECK-NEXT: cmp w8, #7
; CHECK-NEXT: csel w8, w8, w10, lt ; CHECK-NEXT: csel w8, w8, w10, lt
; CHECK-NEXT: cmn w8, #8 // =8 ; CHECK-NEXT: cmn w8, #8
; CHECK-NEXT: mov w9, #-8 ; CHECK-NEXT: mov w9, #-8
; CHECK-NEXT: csel w0, w8, w9, gt ; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y); %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y);
ret i4 %tmp; ret i4 %tmp;
} }
define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: vec: ; CHECK-LABEL: vec:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sqsub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sqsub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y); %tmp = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y);
ret <4 x i32> %tmp; ret <4 x i32> %tmp;
} }

llvm/test/CodeGen/AArch64/ssub_sat_plus.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
declare i4 @llvm.ssub.sat.i4(i4, i4) declare i4 @llvm.ssub.sat.i4(i4, i4)
declare i8 @llvm.ssub.sat.i8(i8, i8) declare i8 @llvm.ssub.sat.i8(i8, i8)
declare i16 @llvm.ssub.sat.i16(i16, i16) declare i16 @llvm.ssub.sat.i16(i16, i16)
declare i32 @llvm.ssub.sat.i32(i32, i32) declare i32 @llvm.ssub.sat.i32(i32, i32)
declare i64 @llvm.ssub.sat.i64(i64, i64) declare i64 @llvm.ssub.sat.i64(i64, i64)
define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind { define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-LABEL: func32: ; CHECK-LABEL: func32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mul w8, w1, w2 ; CHECK-NEXT: mul w8, w1, w2
; CHECK-NEXT: subs w10, w0, w8 ; CHECK-NEXT: subs w10, w0, w8
; CHECK-NEXT: mov w9, #2147483647 ; CHECK-NEXT: mov w9, #2147483647
; CHECK-NEXT: cmp w10, #0 // =0 ; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: cinv w9, w9, ge ; CHECK-NEXT: cinv w9, w9, ge
; CHECK-NEXT: subs w8, w0, w8 ; CHECK-NEXT: subs w8, w0, w8
; CHECK-NEXT: csel w0, w9, w8, vs ; CHECK-NEXT: csel w0, w9, w8, vs
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = mul i32 %y, %z %a = mul i32 %y, %z
%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a) %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a)
ret i32 %tmp ret i32 %tmp
} }
define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind { define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; CHECK-LABEL: func64: ; CHECK-LABEL: func64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x0, x2 ; CHECK-NEXT: subs x8, x0, x2
; CHECK-NEXT: mov x9, #9223372036854775807 ; CHECK-NEXT: mov x9, #9223372036854775807
; CHECK-NEXT: cmp x8, #0 // =0 ; CHECK-NEXT: cmp x8, #0
; CHECK-NEXT: cinv x8, x9, ge ; CHECK-NEXT: cinv x8, x9, ge
; CHECK-NEXT: subs x9, x0, x2 ; CHECK-NEXT: subs x9, x0, x2
; CHECK-NEXT: csel x0, x8, x9, vs ; CHECK-NEXT: csel x0, x8, x9, vs
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = mul i64 %y, %z %a = mul i64 %y, %z
%tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z) %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)
ret i64 %tmp ret i64 %tmp
} }
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define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind { define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
; CHECK-LABEL: func8: ; CHECK-LABEL: func8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0 ; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: mul w9, w1, w2 ; CHECK-NEXT: mul w9, w1, w2
; CHECK-NEXT: sub w8, w8, w9, sxtb ; CHECK-NEXT: sub w8, w8, w9, sxtb
; CHECK-NEXT: mov w10, #127 ; CHECK-NEXT: mov w10, #127
; CHECK-NEXT: cmp w8, #127 // =127 ; CHECK-NEXT: cmp w8, #127
; CHECK-NEXT: csel w8, w8, w10, lt ; CHECK-NEXT: csel w8, w8, w10, lt
; CHECK-NEXT: cmn w8, #128 // =128 ; CHECK-NEXT: cmn w8, #128
; CHECK-NEXT: mov w9, #-128 ; CHECK-NEXT: mov w9, #-128
; CHECK-NEXT: csel w0, w8, w9, gt ; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = mul i8 %y, %z %a = mul i8 %y, %z
%tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %a) %tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %a)
ret i8 %tmp ret i8 %tmp
} }
define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind { define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
; CHECK-LABEL: func4: ; CHECK-LABEL: func4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mul w9, w1, w2 ; CHECK-NEXT: mul w9, w1, w2
; CHECK-NEXT: sbfx w8, w0, #0, #4 ; CHECK-NEXT: sbfx w8, w0, #0, #4
; CHECK-NEXT: lsl w9, w9, #28 ; CHECK-NEXT: lsl w9, w9, #28
; CHECK-NEXT: sub w8, w8, w9, asr #28 ; CHECK-NEXT: sub w8, w8, w9, asr #28
; CHECK-NEXT: mov w10, #7 ; CHECK-NEXT: mov w10, #7
; CHECK-NEXT: cmp w8, #7 // =7 ; CHECK-NEXT: cmp w8, #7
; CHECK-NEXT: csel w8, w8, w10, lt ; CHECK-NEXT: csel w8, w8, w10, lt
; CHECK-NEXT: cmn w8, #8 // =8 ; CHECK-NEXT: cmn w8, #8
; CHECK-NEXT: mov w9, #-8 ; CHECK-NEXT: mov w9, #-8
; CHECK-NEXT: csel w0, w8, w9, gt ; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = mul i4 %y, %z %a = mul i4 %y, %z
%tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %a) %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %a)
ret i4 %tmp ret i4 %tmp
} }

llvm/test/CodeGen/AArch64/ssub_sat_vec.ll

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret void ret void
} }
define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind { define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
; CHECK-LABEL: v2i8: ; CHECK-LABEL: v2i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ld1 { v0.b }[0], [x1] ; CHECK-NEXT: ld1 { v0.b }[0], [x1]
; CHECK-NEXT: ld1 { v1.b }[0], [x0] ; CHECK-NEXT: ld1 { v1.b }[0], [x0]
; CHECK-NEXT: add x8, x0, #1 // =1 ; CHECK-NEXT: add x8, x0, #1
; CHECK-NEXT: add x9, x1, #1 // =1 ; CHECK-NEXT: add x9, x1, #1
; CHECK-NEXT: ld1 { v0.b }[4], [x9] ; CHECK-NEXT: ld1 { v0.b }[4], [x9]
; CHECK-NEXT: ld1 { v1.b }[4], [x8] ; CHECK-NEXT: ld1 { v1.b }[4], [x8]
; CHECK-NEXT: shl v0.2s, v0.2s, #24 ; CHECK-NEXT: shl v0.2s, v0.2s, #24
; CHECK-NEXT: shl v1.2s, v1.2s, #24 ; CHECK-NEXT: shl v1.2s, v1.2s, #24
; CHECK-NEXT: sqsub v0.2s, v1.2s, v0.2s ; CHECK-NEXT: sqsub v0.2s, v1.2s, v0.2s
; CHECK-NEXT: ushr v0.2s, v0.2s, #24 ; CHECK-NEXT: ushr v0.2s, v0.2s, #24
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
Show All 22 Lines; CHECK-NEXT: ret
ret void ret void
} }
define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind { define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
; CHECK-LABEL: v2i16: ; CHECK-LABEL: v2i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ld1 { v0.h }[0], [x1] ; CHECK-NEXT: ld1 { v0.h }[0], [x1]
; CHECK-NEXT: ld1 { v1.h }[0], [x0] ; CHECK-NEXT: ld1 { v1.h }[0], [x0]
; CHECK-NEXT: add x8, x0, #2 // =2 ; CHECK-NEXT: add x8, x0, #2
; CHECK-NEXT: add x9, x1, #2 // =2 ; CHECK-NEXT: add x9, x1, #2
; CHECK-NEXT: ld1 { v0.h }[2], [x9] ; CHECK-NEXT: ld1 { v0.h }[2], [x9]
; CHECK-NEXT: ld1 { v1.h }[2], [x8] ; CHECK-NEXT: ld1 { v1.h }[2], [x8]
; CHECK-NEXT: shl v0.2s, v0.2s, #16 ; CHECK-NEXT: shl v0.2s, v0.2s, #16
; CHECK-NEXT: shl v1.2s, v1.2s, #16 ; CHECK-NEXT: shl v1.2s, v1.2s, #16
; CHECK-NEXT: sqsub v0.2s, v1.2s, v0.2s ; CHECK-NEXT: sqsub v0.2s, v1.2s, v0.2s
; CHECK-NEXT: ushr v0.2s, v0.2s, #16 ; CHECK-NEXT: ushr v0.2s, v0.2s, #16
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
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define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind { define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; CHECK-LABEL: v2i128: ; CHECK-LABEL: v2i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x2, x6 ; CHECK-NEXT: subs x8, x2, x6
; CHECK-NEXT: sbcs x12, x3, x7 ; CHECK-NEXT: sbcs x12, x3, x7
; CHECK-NEXT: mov x9, #9223372036854775807 ; CHECK-NEXT: mov x9, #9223372036854775807
; CHECK-NEXT: eor x10, x3, x7 ; CHECK-NEXT: eor x10, x3, x7
; CHECK-NEXT: cmp x12, #0 // =0 ; CHECK-NEXT: cmp x12, #0
; CHECK-NEXT: eor x13, x3, x12 ; CHECK-NEXT: eor x13, x3, x12
; CHECK-NEXT: cinv x14, x9, ge ; CHECK-NEXT: cinv x14, x9, ge
; CHECK-NEXT: tst x10, x13 ; CHECK-NEXT: tst x10, x13
; CHECK-NEXT: asr x10, x12, #63 ; CHECK-NEXT: asr x10, x12, #63
; CHECK-NEXT: csel x2, x10, x8, lt ; CHECK-NEXT: csel x2, x10, x8, lt
; CHECK-NEXT: csel x3, x14, x12, lt ; CHECK-NEXT: csel x3, x14, x12, lt
; CHECK-NEXT: subs x8, x0, x4 ; CHECK-NEXT: subs x8, x0, x4
; CHECK-NEXT: sbcs x10, x1, x5 ; CHECK-NEXT: sbcs x10, x1, x5
; CHECK-NEXT: eor x11, x1, x5 ; CHECK-NEXT: eor x11, x1, x5
; CHECK-NEXT: cmp x10, #0 // =0 ; CHECK-NEXT: cmp x10, #0
; CHECK-NEXT: eor x12, x1, x10 ; CHECK-NEXT: eor x12, x1, x10
; CHECK-NEXT: cinv x9, x9, ge ; CHECK-NEXT: cinv x9, x9, ge
; CHECK-NEXT: tst x11, x12 ; CHECK-NEXT: tst x11, x12
; CHECK-NEXT: asr x11, x10, #63 ; CHECK-NEXT: asr x11, x10, #63
; CHECK-NEXT: csel x8, x11, x8, lt ; CHECK-NEXT: csel x8, x11, x8, lt
; CHECK-NEXT: csel x1, x9, x10, lt ; CHECK-NEXT: csel x1, x9, x10, lt
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %x, <2 x i128> %y) %z = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
ret <2 x i128> %z ret <2 x i128> %z
} }

llvm/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm64-apple-ios -relocation-model=pic -frame-pointer=all | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios -relocation-model=pic -frame-pointer=all | FileCheck %s
@__stack_chk_guard = external global i64* @__stack_chk_guard = external global i64*
; PR20558 ; PR20558
define i32 @test_stack_guard_remat2() ssp { define i32 @test_stack_guard_remat2() ssp {
; CHECK-LABEL: test_stack_guard_remat2: ; CHECK-LABEL: test_stack_guard_remat2:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: sub sp, sp, #64 ; =64 ; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: stp x29, x30, [sp, #48] ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #48] ; 16-byte Folded Spill
; CHECK-NEXT: add x29, sp, #48 ; =48 ; CHECK-NEXT: add x29, sp, #48
; CHECK-NEXT: .cfi_def_cfa w29, 16 ; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: Lloh0: ; CHECK-NEXT: Lloh0:
; CHECK-NEXT: adrp x8, ___stack_chk_guard@GOTPAGE ; CHECK-NEXT: adrp x8, ___stack_chk_guard@GOTPAGE
; CHECK-NEXT: Lloh1: ; CHECK-NEXT: Lloh1:
; Load the stack guard for the second time, just in case the previous value gets spilled. ; Load the stack guard for the second time, just in case the previous value gets spilled.
; CHECK-NEXT: adrp x9, ___stack_chk_guard@GOTPAGE ; CHECK-NEXT: adrp x9, ___stack_chk_guard@GOTPAGE
Show All 14 Lines
; CHECK-NEXT: ldr x9, [x9, ___stack_chk_guard@GOTPAGEOFF] ; CHECK-NEXT: ldr x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
; CHECK-NEXT: Lloh8: ; CHECK-NEXT: Lloh8:
; CHECK-NEXT: ldr x9, [x9] ; CHECK-NEXT: ldr x9, [x9]
; CHECK-NEXT: cmp x9, x8 ; CHECK-NEXT: cmp x9, x8
; CHECK-NEXT: b.ne LBB0_2 ; CHECK-NEXT: b.ne LBB0_2
; CHECK-NEXT: ; %bb.1: ; %entry ; CHECK-NEXT: ; %bb.1: ; %entry
; CHECK-NEXT: ldp x29, x30, [sp, #48] ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp, #48] ; 16-byte Folded Reload
; CHECK-NEXT: mov w0, #-1 ; CHECK-NEXT: mov w0, #-1
; CHECK-NEXT: add sp, sp, #64 ; =64 ; CHECK-NEXT: add sp, sp, #64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: LBB0_2: ; %entry ; CHECK-NEXT: LBB0_2: ; %entry
; CHECK-NEXT: bl ___stack_chk_fail ; CHECK-NEXT: bl ___stack_chk_fail
; CHECK-NEXT: .loh AdrpLdrGotLdr Lloh6, Lloh7, Lloh8 ; CHECK-NEXT: .loh AdrpLdrGotLdr Lloh6, Lloh7, Lloh8
; CHECK-NEXT: .loh AdrpLdrGotLdr Lloh1, Lloh3, Lloh5 ; CHECK-NEXT: .loh AdrpLdrGotLdr Lloh1, Lloh3, Lloh5
; CHECK-NEXT: .loh AdrpLdrGotLdr Lloh0, Lloh2, Lloh4 ; CHECK-NEXT: .loh AdrpLdrGotLdr Lloh0, Lloh2, Lloh4
entry: entry:
%StackGuardSlot = alloca i8* %StackGuardSlot = alloca i8*
Show All 9 Lines

llvm/test/CodeGen/AArch64/stack-guard-sysreg.ll

Show All 37 Lines
; Verify that we `mrs` from `SP_EL0` twice, rather than load from ; Verify that we `mrs` from `SP_EL0` twice, rather than load from
; __stack_chk_guard. ; __stack_chk_guard.
define dso_local void @foo(i64 %t) local_unnamed_addr #0 { define dso_local void @foo(i64 %t) local_unnamed_addr #0 {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: mov x29, sp ; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: sub sp, sp, #16 // =16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa w29, 16 ; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: mrs x8, SP_EL0 ; CHECK-NEXT: mrs x8, SP_EL0
; CHECK-NO-OFFSET: ldr x8, [x8] ; CHECK-NO-OFFSET: ldr x8, [x8]
; CHECK-POSITIVE-OFFSET: ldr x8, [x8, #8] ; CHECK-POSITIVE-OFFSET: ldr x8, [x8, #8]
; CHECK-NEGATIVE-OFFSET: ldur x8, [x8, #-8] ; CHECK-NEGATIVE-OFFSET: ldur x8, [x8, #-8]
; CHECK-NPOT-OFFSET: ldur x8, [x8, #1] ; CHECK-NPOT-OFFSET: ldur x8, [x8, #1]
; CHECK-NPOT-NEG-OFFSET: ldur x8, [x8, #-1] ; CHECK-NPOT-NEG-OFFSET: ldur x8, [x8, #-1]
; CHECK-257-OFFSET: add x8, x8, #257 ; CHECK-257-OFFSET: add x8, x8, #257
; CHECK-257-OFFSET-NEXT: ldr x8, [x8] ; CHECK-257-OFFSET-NEXT: ldr x8, [x8]
; CHECK-MINUS-257-OFFSET: sub x8, x8, #257 ; CHECK-MINUS-257-OFFSET: sub x8, x8, #257
; CHECK-MINUS-257-OFFSET-NEXT: ldr x8, [x8] ; CHECK-MINUS-257-OFFSET-NEXT: ldr x8, [x8]
; CHECK-NEXT: lsl x9, x0, #2 ; CHECK-NEXT: lsl x9, x0, #2
; CHECK-NEXT: add x9, x9, #15 // =15 ; CHECK-NEXT: add x9, x9, #15
; CHECK-NEXT: and x9, x9, #0xfffffffffffffff0 ; CHECK-NEXT: and x9, x9, #0xfffffffffffffff0
; CHECK-NEXT: stur x8, [x29, #-8] ; CHECK-NEXT: stur x8, [x29, #-8]
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: sub x0, x8, x9 ; CHECK-NEXT: sub x0, x8, x9
; CHECK-NEXT: mov sp, x0 ; CHECK-NEXT: mov sp, x0
; CHECK-NEXT: bl baz ; CHECK-NEXT: bl baz
; CHECK-NEXT: ldur x8, [x29, #-8] ; CHECK-NEXT: ldur x8, [x29, #-8]
; CHECK-NEXT: mrs x9, SP_EL0 ; CHECK-NEXT: mrs x9, SP_EL0
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llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Linesentry:
%safepoint_token = tail call token (i64, i32, %struct ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_structf(i64 0, i32 0, %struct ()* @return_struct, i32 0, i32 0, i32 0, i32 0) %safepoint_token = tail call token (i64, i32, %struct ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_structf(i64 0, i32 0, %struct ()* @return_struct, i32 0, i32 0, i32 0, i32 0)
%call1 = call %struct @llvm.experimental.gc.result.struct(token %safepoint_token) %call1 = call %struct @llvm.experimental.gc.result.struct(token %safepoint_token)
ret %struct %call1 ret %struct %call1
} }
define i1 @test_relocate(i32 addrspace(1)* %a) gc "statepoint-example" { define i1 @test_relocate(i32 addrspace(1)* %a) gc "statepoint-example" {
; CHECK-LABEL: test_relocate: ; CHECK-LABEL: test_relocate:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #16 // =16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: str x0, [sp, #8] ; CHECK-NEXT: str x0, [sp, #8]
; CHECK-NEXT: bl return_i1 ; CHECK-NEXT: bl return_i1
; CHECK-NEXT: .Ltmp7: ; CHECK-NEXT: .Ltmp7:
; CHECK-NEXT: and w0, w0, #0x1 ; CHECK-NEXT: and w0, w0, #0x1
; CHECK-NEXT: add sp, sp, #16 // =16 ; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; Check that an ununsed relocate has no code-generation impact ; Check that an ununsed relocate has no code-generation impact
entry: entry:
%safepoint_token = tail call token (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0) ["gc-live" (i32 addrspace(1)* %a)] %safepoint_token = tail call token (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0) ["gc-live" (i32 addrspace(1)* %a)]
%call1 = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token %safepoint_token, i32 0, i32 0) %call1 = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token %safepoint_token, i32 0, i32 0)
%call2 = call zeroext i1 @llvm.experimental.gc.result.i1(token %safepoint_token) %call2 = call zeroext i1 @llvm.experimental.gc.result.i1(token %safepoint_token)
ret i1 %call2 ret i1 %call2
} }
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%struct2 = type { i64, i64, i64 } %struct2 = type { i64, i64, i64 }
declare void @consume_attributes(i32, i8* nest, i32, %struct2* byval(%struct2)) declare void @consume_attributes(i32, i8* nest, i32, %struct2* byval(%struct2))
define void @test_attributes(%struct2* byval(%struct2) %s) gc "statepoint-example" { define void @test_attributes(%struct2* byval(%struct2) %s) gc "statepoint-example" {
; CHECK-LABEL: test_attributes: ; CHECK-LABEL: test_attributes:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: ldr x8, [sp, #48] ; CHECK-NEXT: ldr x8, [sp, #48]
; CHECK-NEXT: ldr q0, [sp, #32] ; CHECK-NEXT: ldr q0, [sp, #32]
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: mov w1, #17 ; CHECK-NEXT: mov w1, #17
; CHECK-NEXT: mov x18, xzr ; CHECK-NEXT: mov x18, xzr
; CHECK-NEXT: str x8, [sp, #16] ; CHECK-NEXT: str x8, [sp, #16]
; CHECK-NEXT: str q0, [sp] ; CHECK-NEXT: str q0, [sp]
; CHECK-NEXT: bl consume_attributes ; CHECK-NEXT: bl consume_attributes
; CHECK-NEXT: .Ltmp11: ; CHECK-NEXT: .Ltmp11:
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
; Check that arguments with attributes are lowered correctly. ; Check that arguments with attributes are lowered correctly.
; We call a function that has a nest argument and a byval argument. ; We call a function that has a nest argument and a byval argument.
%statepoint_token = call token (i64, i32, void (i32, i8*, i32, %struct2*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidi32p0i8i32p0s_struct2sf(i64 0, i32 0, void (i32, i8*, i32, %struct2*)* @consume_attributes, i32 4, i32 0, i32 42, i8* nest null, i32 17, %struct2* byval(%struct2) %s, i32 0, i32 0) %statepoint_token = call token (i64, i32, void (i32, i8*, i32, %struct2*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidi32p0i8i32p0s_struct2sf(i64 0, i32 0, void (i32, i8*, i32, %struct2*)* @consume_attributes, i32 4, i32 0, i32 42, i8* nest null, i32 17, %struct2* byval(%struct2) %s, i32 0, i32 0)
ret void ret void
} }
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llvm/test/CodeGen/AArch64/sub-of-not.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
; These two forms are equivalent: ; These two forms are equivalent:
; sub %y, (xor %x, -1) ; sub %y, (xor %x, -1)
; add (add %x, 1), %y ; add (add %x, 1), %y
; Some targets may prefer one to the other. ; Some targets may prefer one to the other.
define i8 @scalar_i8(i8 %x, i8 %y) nounwind { define i8 @scalar_i8(i8 %x, i8 %y) nounwind {
; CHECK-LABEL: scalar_i8: ; CHECK-LABEL: scalar_i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w1, w0 ; CHECK-NEXT: add w8, w1, w0
; CHECK-NEXT: add w0, w8, #1 // =1 ; CHECK-NEXT: add w0, w8, #1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = xor i8 %x, -1 %t0 = xor i8 %x, -1
%t1 = sub i8 %y, %t0 %t1 = sub i8 %y, %t0
ret i8 %t1 ret i8 %t1
} }
define i16 @scalar_i16(i16 %x, i16 %y) nounwind { define i16 @scalar_i16(i16 %x, i16 %y) nounwind {
; CHECK-LABEL: scalar_i16: ; CHECK-LABEL: scalar_i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w1, w0 ; CHECK-NEXT: add w8, w1, w0
; CHECK-NEXT: add w0, w8, #1 // =1 ; CHECK-NEXT: add w0, w8, #1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = xor i16 %x, -1 %t0 = xor i16 %x, -1
%t1 = sub i16 %y, %t0 %t1 = sub i16 %y, %t0
ret i16 %t1 ret i16 %t1
} }
define i32 @scalar_i32(i32 %x, i32 %y) nounwind { define i32 @scalar_i32(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: scalar_i32: ; CHECK-LABEL: scalar_i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w1, w0 ; CHECK-NEXT: add w8, w1, w0
; CHECK-NEXT: add w0, w8, #1 // =1 ; CHECK-NEXT: add w0, w8, #1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = xor i32 %x, -1 %t0 = xor i32 %x, -1
%t1 = sub i32 %y, %t0 %t1 = sub i32 %y, %t0
ret i32 %t1 ret i32 %t1
} }
define i64 @scalar_i64(i64 %x, i64 %y) nounwind { define i64 @scalar_i64(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: scalar_i64: ; CHECK-LABEL: scalar_i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x1, x0 ; CHECK-NEXT: add x8, x1, x0
; CHECK-NEXT: add x0, x8, #1 // =1 ; CHECK-NEXT: add x0, x8, #1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = xor i64 %x, -1 %t0 = xor i64 %x, -1
%t1 = sub i64 %y, %t0 %t1 = sub i64 %y, %t0
ret i64 %t1 ret i64 %t1
} }
define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind { define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; CHECK-LABEL: vector_i128_i8: ; CHECK-LABEL: vector_i128_i8:
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llvm/test/CodeGen/AArch64/sub1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
define i64 @sub1_disguised_constant(i64 %x) { define i64 @sub1_disguised_constant(i64 %x) {
; CHECK-LABEL: sub1_disguised_constant: ; CHECK-LABEL: sub1_disguised_constant:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w0, #1 // =1 ; CHECK-NEXT: sub w8, w0, #1
; CHECK-NEXT: and w8, w0, w8 ; CHECK-NEXT: and w8, w0, w8
; CHECK-NEXT: and x0, x8, #0xffff ; CHECK-NEXT: and x0, x8, #0xffff
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a1 = and i64 %x, 65535 %a1 = and i64 %x, 65535
%a2 = add i64 %x, 65535 %a2 = add i64 %x, 65535
%r = and i64 %a1, %a2 %r = and i64 %a1, %a2
ret i64 %r ret i64 %r
} }

llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll

Show All 36 Linesentry:
ret float %call ret float %call
} }
define float @foo2(double* %x0, double* %x1) nounwind { define float @foo2(double* %x0, double* %x1) nounwind {
; CHECK-LABEL: foo2: ; CHECK-LABEL: foo2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-4 ; CHECK-NEXT: addvl sp, sp, #-4
; CHECK-NEXT: sub sp, sp, #16 // =16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: ld4d { z1.d, z2.d, z3.d, z4.d }, p0/z, [x0] ; CHECK-NEXT: ld4d { z1.d, z2.d, z3.d, z4.d }, p0/z, [x0]
; CHECK-NEXT: ld4d { z16.d, z17.d, z18.d, z19.d }, p0/z, [x1] ; CHECK-NEXT: ld4d { z16.d, z17.d, z18.d, z19.d }, p0/z, [x1]
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: add x8, sp, #16 // =16 ; CHECK-NEXT: add x8, sp, #16
; CHECK-NEXT: add x9, sp, #16 // =16 ; CHECK-NEXT: add x9, sp, #16
; CHECK-NEXT: fmov s0, #1.00000000 ; CHECK-NEXT: fmov s0, #1.00000000
; CHECK-NEXT: mov w1, #1 ; CHECK-NEXT: mov w1, #1
; CHECK-NEXT: mov w2, #2 ; CHECK-NEXT: mov w2, #2
; CHECK-NEXT: mov w3, #3 ; CHECK-NEXT: mov w3, #3
; CHECK-NEXT: mov w4, #4 ; CHECK-NEXT: mov w4, #4
; CHECK-NEXT: mov w5, #5 ; CHECK-NEXT: mov w5, #5
; CHECK-NEXT: mov w6, #6 ; CHECK-NEXT: mov w6, #6
; CHECK-NEXT: mov w7, #7 ; CHECK-NEXT: mov w7, #7
; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: st1d { z16.d }, p0, [x9] ; CHECK-NEXT: st1d { z16.d }, p0, [x9]
; CHECK-NEXT: st1d { z17.d }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1d { z17.d }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1d { z18.d }, p0, [x8, #2, mul vl] ; CHECK-NEXT: st1d { z18.d }, p0, [x8, #2, mul vl]
; CHECK-NEXT: st1d { z19.d }, p0, [x8, #3, mul vl] ; CHECK-NEXT: st1d { z19.d }, p0, [x8, #3, mul vl]
; CHECK-NEXT: str x8, [sp] ; CHECK-NEXT: str x8, [sp]
; CHECK-NEXT: bl callee2 ; CHECK-NEXT: bl callee2
; CHECK-NEXT: addvl sp, sp, #4 ; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: add sp, sp, #16 // =16 ; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
%1 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0) %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
%2 = call <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1(<vscale x 2 x i1> %1, double* %x0) %2 = call <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1(<vscale x 2 x i1> %1, double* %x0)
%3 = call <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1(<vscale x 2 x i1> %1, double* %x1) %3 = call <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1(<vscale x 2 x i1> %1, double* %x1)
%call = call float @callee2(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, float 1.000000e+00, <vscale x 8 x double> %2, <vscale x 8 x double> %3) %call = call float @callee2(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, float 1.000000e+00, <vscale x 8 x double> %2, <vscale x 8 x double> %3)
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llvm/test/CodeGen/AArch64/sve-extract-vector.ll

Show All 12 Lines
; Goes through memory currently; idx != 0. ; Goes through memory currently; idx != 0.
define <2 x i64> @extract_v2i64_nxv2i64_idx2(<vscale x 2 x i64> %vec) nounwind { define <2 x i64> @extract_v2i64_nxv2i64_idx2(<vscale x 2 x i64> %vec) nounwind {
; CHECK-LABEL: extract_v2i64_nxv2i64_idx2: ; CHECK-LABEL: extract_v2i64_nxv2i64_idx2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cntd x9 ; CHECK-NEXT: cntd x9
; CHECK-NEXT: sub x9, x9, #2 // =2 ; CHECK-NEXT: sub x9, x9, #2
; CHECK-NEXT: mov w8, #2 ; CHECK-NEXT: mov w8, #2
; CHECK-NEXT: cmp x9, #2 // =2 ; CHECK-NEXT: cmp x9, #2
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ldr q0, [x9, x8] ; CHECK-NEXT: ldr q0, [x9, x8]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; Goes through memory currently; idx != 0. ; Goes through memory currently; idx != 0.
define <4 x i32> @extract_v4i32_nxv4i32_idx4(<vscale x 4 x i32> %vec) nounwind { define <4 x i32> @extract_v4i32_nxv4i32_idx4(<vscale x 4 x i32> %vec) nounwind {
; CHECK-LABEL: extract_v4i32_nxv4i32_idx4: ; CHECK-LABEL: extract_v4i32_nxv4i32_idx4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cntw x9 ; CHECK-NEXT: cntw x9
; CHECK-NEXT: sub x9, x9, #4 // =4 ; CHECK-NEXT: sub x9, x9, #4
; CHECK-NEXT: mov w8, #4 ; CHECK-NEXT: mov w8, #4
; CHECK-NEXT: cmp x9, #4 // =4 ; CHECK-NEXT: cmp x9, #4
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: lsl x8, x8, #2 ; CHECK-NEXT: lsl x8, x8, #2
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ldr q0, [x9, x8] ; CHECK-NEXT: ldr q0, [x9, x8]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; Goes through memory currently; idx != 0. ; Goes through memory currently; idx != 0.
define <8 x i16> @extract_v8i16_nxv8i16_idx8(<vscale x 8 x i16> %vec) nounwind { define <8 x i16> @extract_v8i16_nxv8i16_idx8(<vscale x 8 x i16> %vec) nounwind {
; CHECK-LABEL: extract_v8i16_nxv8i16_idx8: ; CHECK-LABEL: extract_v8i16_nxv8i16_idx8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cnth x9 ; CHECK-NEXT: cnth x9
; CHECK-NEXT: sub x9, x9, #8 // =8 ; CHECK-NEXT: sub x9, x9, #8
; CHECK-NEXT: mov w8, #8 ; CHECK-NEXT: mov w8, #8
; CHECK-NEXT: cmp x9, #8 // =8 ; CHECK-NEXT: cmp x9, #8
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: lsl x8, x8, #1 ; CHECK-NEXT: lsl x8, x8, #1
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ldr q0, [x9, x8] ; CHECK-NEXT: ldr q0, [x9, x8]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
Show All 14 Lines
; Goes through memory currently; idx != 0. ; Goes through memory currently; idx != 0.
define <16 x i8> @extract_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec) nounwind { define <16 x i8> @extract_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec) nounwind {
; CHECK-LABEL: extract_v16i8_nxv16i8_idx16: ; CHECK-LABEL: extract_v16i8_nxv16i8_idx16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: rdvl x9, #1 ; CHECK-NEXT: rdvl x9, #1
; CHECK-NEXT: sub x9, x9, #16 // =16 ; CHECK-NEXT: sub x9, x9, #16
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: mov w8, #16 ; CHECK-NEXT: mov w8, #16
; CHECK-NEXT: cmp x9, #16 // =16 ; CHECK-NEXT: cmp x9, #16
; CHECK-NEXT: st1b { z0.b }, p0, [sp] ; CHECK-NEXT: st1b { z0.b }, p0, [sp]
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ldr q0, [x9, x8] ; CHECK-NEXT: ldr q0, [x9, x8]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> %vec, i64 16) %retval = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> %vec, i64 16)
Show All 22 Lines
; Fixed length clamping ; Fixed length clamping
define <2 x i64> @extract_fixed_v2i64_nxv2i64(<vscale x 2 x i64> %vec) nounwind #0 { define <2 x i64> @extract_fixed_v2i64_nxv2i64(<vscale x 2 x i64> %vec) nounwind #0 {
; CHECK-LABEL: extract_fixed_v2i64_nxv2i64: ; CHECK-LABEL: extract_fixed_v2i64_nxv2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cntd x9 ; CHECK-NEXT: cntd x9
; CHECK-NEXT: sub x9, x9, #2 // =2 ; CHECK-NEXT: sub x9, x9, #2
; CHECK-NEXT: mov w8, #2 ; CHECK-NEXT: mov w8, #2
; CHECK-NEXT: cmp x9, #2 // =2 ; CHECK-NEXT: cmp x9, #2
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ldr q0, [x9, x8] ; CHECK-NEXT: ldr q0, [x9, x8]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> %vec, i64 2) %retval = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> %vec, i64 2)
ret <2 x i64> %retval ret <2 x i64> %retval
} }
define <4 x i64> @extract_fixed_v4i64_nxv2i64(<vscale x 2 x i64> %vec) nounwind #0 { define <4 x i64> @extract_fixed_v4i64_nxv2i64(<vscale x 2 x i64> %vec) nounwind #0 {
; CHECK-LABEL: extract_fixed_v4i64_nxv2i64: ; CHECK-LABEL: extract_fixed_v4i64_nxv2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cntd x9 ; CHECK-NEXT: cntd x9
; CHECK-NEXT: subs x9, x9, #4 // =4 ; CHECK-NEXT: subs x9, x9, #4
; CHECK-NEXT: csel x9, xzr, x9, lo ; CHECK-NEXT: csel x9, xzr, x9, lo
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov w10, #4 ; CHECK-NEXT: mov w10, #4
; CHECK-NEXT: cmp x9, #4 // =4 ; CHECK-NEXT: cmp x9, #4
; CHECK-NEXT: ptrue p1.d, vl4 ; CHECK-NEXT: ptrue p1.d, vl4
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: mov x10, sp ; CHECK-NEXT: mov x10, sp
; CHECK-NEXT: ld1d { z0.d }, p1/z, [x10, x9, lsl #3] ; CHECK-NEXT: ld1d { z0.d }, p1/z, [x10, x9, lsl #3]
; CHECK-NEXT: st1d { z0.d }, p1, [x8] ; CHECK-NEXT: st1d { z0.d }, p1, [x8]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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llvm/test/CodeGen/AArch64/sve-insert-element.ll

Show First 20 Lines • Show All 500 Lines • ▼ Show 20 Lines
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: rdvl x10, #2 ; CHECK-NEXT: rdvl x10, #2
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 ; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: sxtw x9, w1 ; CHECK-NEXT: sxtw x9, w1
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: cmp x9, x10 ; CHECK-NEXT: cmp x9, x10
; CHECK-NEXT: mov z0.b, p1/z, #1 // =0x1 ; CHECK-NEXT: mov z0.b, p1/z, #1 // =0x1
; CHECK-NEXT: ptrue p1.b ; CHECK-NEXT: ptrue p1.b
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov z1.b, p0/z, #1 // =0x1 ; CHECK-NEXT: mov z1.b, p0/z, #1 // =0x1
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: st1b { z0.b }, p1, [x8, #1, mul vl] ; CHECK-NEXT: st1b { z0.b }, p1, [x8, #1, mul vl]
; CHECK-NEXT: st1b { z1.b }, p1, [sp] ; CHECK-NEXT: st1b { z1.b }, p1, [sp]
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llvm/test/CodeGen/AArch64/sve-insert-vector.ll

Show All 17 Lines
} }
define <vscale x 2 x i64> @insert_v2i64_nxv2i64_idx2(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind { define <vscale x 2 x i64> @insert_v2i64_nxv2i64_idx2(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind {
; CHECK-LABEL: insert_v2i64_nxv2i64_idx2: ; CHECK-LABEL: insert_v2i64_nxv2i64_idx2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cntd x9 ; CHECK-NEXT: cntd x9
; CHECK-NEXT: sub x9, x9, #2 // =2 ; CHECK-NEXT: sub x9, x9, #2
; CHECK-NEXT: mov w8, #2 ; CHECK-NEXT: mov w8, #2
; CHECK-NEXT: cmp x9, #2 // =2 ; CHECK-NEXT: cmp x9, #2
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: str q1, [x9, x8] ; CHECK-NEXT: str q1, [x9, x8]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
Show All 20 Lines
} }
define <vscale x 4 x i32> @insert_v4i32_nxv4i32_idx4(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind { define <vscale x 4 x i32> @insert_v4i32_nxv4i32_idx4(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind {
; CHECK-LABEL: insert_v4i32_nxv4i32_idx4: ; CHECK-LABEL: insert_v4i32_nxv4i32_idx4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cntw x9 ; CHECK-NEXT: cntw x9
; CHECK-NEXT: sub x9, x9, #4 // =4 ; CHECK-NEXT: sub x9, x9, #4
; CHECK-NEXT: mov w8, #4 ; CHECK-NEXT: mov w8, #4
; CHECK-NEXT: cmp x9, #4 // =4 ; CHECK-NEXT: cmp x9, #4
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: lsl x8, x8, #2 ; CHECK-NEXT: lsl x8, x8, #2
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: str q1, [x9, x8] ; CHECK-NEXT: str q1, [x9, x8]
; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
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} }
define <vscale x 8 x i16> @insert_v8i16_nxv8i16_idx8(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind { define <vscale x 8 x i16> @insert_v8i16_nxv8i16_idx8(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind {
; CHECK-LABEL: insert_v8i16_nxv8i16_idx8: ; CHECK-LABEL: insert_v8i16_nxv8i16_idx8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cnth x9 ; CHECK-NEXT: cnth x9
; CHECK-NEXT: sub x9, x9, #8 // =8 ; CHECK-NEXT: sub x9, x9, #8
; CHECK-NEXT: mov w8, #8 ; CHECK-NEXT: mov w8, #8
; CHECK-NEXT: cmp x9, #8 // =8 ; CHECK-NEXT: cmp x9, #8
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: lsl x8, x8, #1 ; CHECK-NEXT: lsl x8, x8, #1
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: str q1, [x9, x8] ; CHECK-NEXT: str q1, [x9, x8]
; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
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} }
define <vscale x 16 x i8> @insert_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind { define <vscale x 16 x i8> @insert_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind {
; CHECK-LABEL: insert_v16i8_nxv16i8_idx16: ; CHECK-LABEL: insert_v16i8_nxv16i8_idx16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: rdvl x9, #1 ; CHECK-NEXT: rdvl x9, #1
; CHECK-NEXT: sub x9, x9, #16 // =16 ; CHECK-NEXT: sub x9, x9, #16
; CHECK-NEXT: mov w8, #16 ; CHECK-NEXT: mov w8, #16
; CHECK-NEXT: cmp x9, #16 // =16 ; CHECK-NEXT: cmp x9, #16
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st1b { z0.b }, p0, [sp] ; CHECK-NEXT: st1b { z0.b }, p0, [sp]
; CHECK-NEXT: str q1, [x9, x8] ; CHECK-NEXT: str q1, [x9, x8]
; CHECK-NEXT: ld1b { z0.b }, p0/z, [sp] ; CHECK-NEXT: ld1b { z0.b }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; Fixed length clamping ; Fixed length clamping
define <vscale x 2 x i64> @insert_fixed_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind #0 { define <vscale x 2 x i64> @insert_fixed_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind #0 {
; CHECK-LABEL: insert_fixed_v2i64_nxv2i64: ; CHECK-LABEL: insert_fixed_v2i64_nxv2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: cntd x9 ; CHECK-NEXT: cntd x9
; CHECK-NEXT: sub x9, x9, #2 // =2 ; CHECK-NEXT: sub x9, x9, #2
; CHECK-NEXT: mov w8, #2 ; CHECK-NEXT: mov w8, #2
; CHECK-NEXT: cmp x9, #2 // =2 ; CHECK-NEXT: cmp x9, #2
; CHECK-NEXT: csel x8, x9, x8, lo ; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: str q1, [x9, x8] ; CHECK-NEXT: str q1, [x9, x8]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 2) %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 2)
ret <vscale x 2 x i64> %retval ret <vscale x 2 x i64> %retval
} }
define <vscale x 2 x i64> @insert_fixed_v4i64_nxv2i64(<vscale x 2 x i64> %vec, <4 x i64>* %ptr) nounwind #0 { define <vscale x 2 x i64> @insert_fixed_v4i64_nxv2i64(<vscale x 2 x i64> %vec, <4 x i64>* %ptr) nounwind #0 {
; CHECK-LABEL: insert_fixed_v4i64_nxv2i64: ; CHECK-LABEL: insert_fixed_v4i64_nxv2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.d, vl4 ; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: cntd x8 ; CHECK-NEXT: cntd x8
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0]
; CHECK-NEXT: subs x8, x8, #4 // =4 ; CHECK-NEXT: subs x8, x8, #4
; CHECK-NEXT: csel x8, xzr, x8, lo ; CHECK-NEXT: csel x8, xzr, x8, lo
; CHECK-NEXT: mov w9, #4 ; CHECK-NEXT: mov w9, #4
; CHECK-NEXT: cmp x8, #4 // =4 ; CHECK-NEXT: cmp x8, #4
; CHECK-NEXT: ptrue p1.d ; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st1d { z0.d }, p1, [sp] ; CHECK-NEXT: st1d { z0.d }, p1, [sp]
; CHECK-NEXT: st1d { z1.d }, p0, [x9, x8, lsl #3] ; CHECK-NEXT: st1d { z1.d }, p0, [x9, x8, lsl #3]
; CHECK-NEXT: ld1d { z0.d }, p1/z, [sp] ; CHECK-NEXT: ld1d { z0.d }, p1/z, [sp]
; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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llvm/test/CodeGen/AArch64/sve-ld1r.ll

Show All 11 Lines
; ;
@g8 = external global i8 @g8 = external global i8
; One-off test for splatted value coming from stack load. ; One-off test for splatted value coming from stack load.
define <vscale x 16 x i8> @ld1r_stack() { define <vscale x 16 x i8> @ld1r_stack() {
; CHECK-LABEL: ld1r_stack: ; CHECK-LABEL: ld1r_stack:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #16 // =16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: adrp x8, :got:g8 ; CHECK-NEXT: adrp x8, :got:g8
; CHECK-NEXT: ldr x8, [x8, :got_lo12:g8] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:g8]
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: ldrb w8, [x8] ; CHECK-NEXT: ldrb w8, [x8]
; CHECK-NEXT: strb w8, [sp, #12] ; CHECK-NEXT: strb w8, [sp, #12]
; CHECK-NEXT: ld1rb { z0.b }, p0/z, [sp, #14] ; CHECK-NEXT: ld1rb { z0.b }, p0/z, [sp, #14]
; CHECK-NEXT: add sp, sp, #16 // =16 ; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp = alloca i8 %valp = alloca i8
%valp2 = load volatile i8, i8* @g8 %valp2 = load volatile i8, i8* @g8
store volatile i8 %valp2, i8* %valp store volatile i8 %valp2, i8* %valp
%valp3 = getelementptr i8, i8* %valp, i32 2 %valp3 = getelementptr i8, i8* %valp, i32 2
%val = load i8, i8* %valp3 %val = load i8, i8* %valp3
%1 = insertelement <vscale x 16 x i8> undef, i8 %val, i32 0 %1 = insertelement <vscale x 16 x i8> undef, i8 %val, i32 0
%2 = shufflevector <vscale x 16 x i8> %1, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer %2 = shufflevector <vscale x 16 x i8> %1, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
Show All 23 Lines; CHECK-NEXT: ret
%ins = insertelement <vscale x 16 x i8> undef, i8 %val, i32 0 %ins = insertelement <vscale x 16 x i8> undef, i8 %val, i32 0
%shf = shufflevector <vscale x 16 x i8> %ins, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer %shf = shufflevector <vscale x 16 x i8> %ins, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
ret <vscale x 16 x i8> %shf ret <vscale x 16 x i8> %shf
} }
define <vscale x 16 x i8> @ld1rb_gep_out_of_range_up(i8* %valp) { define <vscale x 16 x i8> @ld1rb_gep_out_of_range_up(i8* %valp) {
; CHECK-LABEL: ld1rb_gep_out_of_range_up: ; CHECK-LABEL: ld1rb_gep_out_of_range_up:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #64 // =64 ; CHECK-NEXT: add x8, x0, #64
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: ld1rb { z0.b }, p0/z, [x8] ; CHECK-NEXT: ld1rb { z0.b }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr i8, i8* %valp, i32 64 %valp2 = getelementptr i8, i8* %valp, i32 64
%val = load i8, i8* %valp2 %val = load i8, i8* %valp2
%ins = insertelement <vscale x 16 x i8> undef, i8 %val, i32 0 %ins = insertelement <vscale x 16 x i8> undef, i8 %val, i32 0
%shf = shufflevector <vscale x 16 x i8> %ins, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer %shf = shufflevector <vscale x 16 x i8> %ins, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
ret <vscale x 16 x i8> %shf ret <vscale x 16 x i8> %shf
} }
define <vscale x 16 x i8> @ld1rb_gep_out_of_range_down(i8* %valp) { define <vscale x 16 x i8> @ld1rb_gep_out_of_range_down(i8* %valp) {
; CHECK-LABEL: ld1rb_gep_out_of_range_down: ; CHECK-LABEL: ld1rb_gep_out_of_range_down:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x0, #1 // =1 ; CHECK-NEXT: sub x8, x0, #1
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: ld1rb { z0.b }, p0/z, [x8] ; CHECK-NEXT: ld1rb { z0.b }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr i8, i8* %valp, i32 -1 %valp2 = getelementptr i8, i8* %valp, i32 -1
%val = load i8, i8* %valp2 %val = load i8, i8* %valp2
%ins = insertelement <vscale x 16 x i8> undef, i8 %val, i32 0 %ins = insertelement <vscale x 16 x i8> undef, i8 %val, i32 0
%shf = shufflevector <vscale x 16 x i8> %ins, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer %shf = shufflevector <vscale x 16 x i8> %ins, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
ret <vscale x 16 x i8> %shf ret <vscale x 16 x i8> %shf
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%ins = insertelement <vscale x 8 x i16> undef, i16 %val, i32 0 %ins = insertelement <vscale x 8 x i16> undef, i16 %val, i32 0
%shf = shufflevector <vscale x 8 x i16> %ins, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %shf = shufflevector <vscale x 8 x i16> %ins, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
ret <vscale x 8 x i16> %shf ret <vscale x 8 x i16> %shf
} }
define <vscale x 8 x i16> @ld1rh_gep_out_of_range_up(i16* %valp) { define <vscale x 8 x i16> @ld1rh_gep_out_of_range_up(i16* %valp) {
; CHECK-LABEL: ld1rh_gep_out_of_range_up: ; CHECK-LABEL: ld1rh_gep_out_of_range_up:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #128 // =128 ; CHECK-NEXT: add x8, x0, #128
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ld1rh { z0.h }, p0/z, [x8] ; CHECK-NEXT: ld1rh { z0.h }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr i16, i16* %valp, i32 64 %valp2 = getelementptr i16, i16* %valp, i32 64
%val = load i16, i16* %valp2 %val = load i16, i16* %valp2
%ins = insertelement <vscale x 8 x i16> undef, i16 %val, i32 0 %ins = insertelement <vscale x 8 x i16> undef, i16 %val, i32 0
%shf = shufflevector <vscale x 8 x i16> %ins, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %shf = shufflevector <vscale x 8 x i16> %ins, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
ret <vscale x 8 x i16> %shf ret <vscale x 8 x i16> %shf
} }
define <vscale x 8 x i16> @ld1rh_gep_out_of_range_down(i16* %valp) { define <vscale x 8 x i16> @ld1rh_gep_out_of_range_down(i16* %valp) {
; CHECK-LABEL: ld1rh_gep_out_of_range_down: ; CHECK-LABEL: ld1rh_gep_out_of_range_down:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x0, #2 // =2 ; CHECK-NEXT: sub x8, x0, #2
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ld1rh { z0.h }, p0/z, [x8] ; CHECK-NEXT: ld1rh { z0.h }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr i16, i16* %valp, i32 -1 %valp2 = getelementptr i16, i16* %valp, i32 -1
%val = load i16, i16* %valp2 %val = load i16, i16* %valp2
%ins = insertelement <vscale x 8 x i16> undef, i16 %val, i32 0 %ins = insertelement <vscale x 8 x i16> undef, i16 %val, i32 0
%shf = shufflevector <vscale x 8 x i16> %ins, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %shf = shufflevector <vscale x 8 x i16> %ins, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
ret <vscale x 8 x i16> %shf ret <vscale x 8 x i16> %shf
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%ins = insertelement <vscale x 4 x i32> undef, i32 %val, i32 0 %ins = insertelement <vscale x 4 x i32> undef, i32 %val, i32 0
%shf = shufflevector <vscale x 4 x i32> %ins, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer %shf = shufflevector <vscale x 4 x i32> %ins, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
ret <vscale x 4 x i32> %shf ret <vscale x 4 x i32> %shf
} }
define <vscale x 4 x i32> @ld1rw_gep_out_of_range_up(i32* %valp) { define <vscale x 4 x i32> @ld1rw_gep_out_of_range_up(i32* %valp) {
; CHECK-LABEL: ld1rw_gep_out_of_range_up: ; CHECK-LABEL: ld1rw_gep_out_of_range_up:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #256 // =256 ; CHECK-NEXT: add x8, x0, #256
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1rw { z0.s }, p0/z, [x8] ; CHECK-NEXT: ld1rw { z0.s }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr i32, i32* %valp, i32 64 %valp2 = getelementptr i32, i32* %valp, i32 64
%val = load i32, i32* %valp2 %val = load i32, i32* %valp2
%ins = insertelement <vscale x 4 x i32> undef, i32 %val, i32 0 %ins = insertelement <vscale x 4 x i32> undef, i32 %val, i32 0
%shf = shufflevector <vscale x 4 x i32> %ins, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer %shf = shufflevector <vscale x 4 x i32> %ins, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
ret <vscale x 4 x i32> %shf ret <vscale x 4 x i32> %shf
} }
define <vscale x 4 x i32> @ld1rw_gep_out_of_range_down(i32* %valp) { define <vscale x 4 x i32> @ld1rw_gep_out_of_range_down(i32* %valp) {
; CHECK-LABEL: ld1rw_gep_out_of_range_down: ; CHECK-LABEL: ld1rw_gep_out_of_range_down:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x0, #4 // =4 ; CHECK-NEXT: sub x8, x0, #4
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1rw { z0.s }, p0/z, [x8] ; CHECK-NEXT: ld1rw { z0.s }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr i32, i32* %valp, i32 -1 %valp2 = getelementptr i32, i32* %valp, i32 -1
%val = load i32, i32* %valp2 %val = load i32, i32* %valp2
%ins = insertelement <vscale x 4 x i32> undef, i32 %val, i32 0 %ins = insertelement <vscale x 4 x i32> undef, i32 %val, i32 0
%shf = shufflevector <vscale x 4 x i32> %ins, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer %shf = shufflevector <vscale x 4 x i32> %ins, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
ret <vscale x 4 x i32> %shf ret <vscale x 4 x i32> %shf
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%ins = insertelement <vscale x 2 x i64> undef, i64 %val, i32 0 %ins = insertelement <vscale x 2 x i64> undef, i64 %val, i32 0
%shf = shufflevector <vscale x 2 x i64> %ins, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer %shf = shufflevector <vscale x 2 x i64> %ins, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
ret <vscale x 2 x i64> %shf ret <vscale x 2 x i64> %shf
} }
define <vscale x 2 x i64> @ld1rd_gep_out_of_range_up(i64* %valp) { define <vscale x 2 x i64> @ld1rd_gep_out_of_range_up(i64* %valp) {
; CHECK-LABEL: ld1rd_gep_out_of_range_up: ; CHECK-LABEL: ld1rd_gep_out_of_range_up:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #512 // =512 ; CHECK-NEXT: add x8, x0, #512
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1rd { z0.d }, p0/z, [x8] ; CHECK-NEXT: ld1rd { z0.d }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr i64, i64* %valp, i32 64 %valp2 = getelementptr i64, i64* %valp, i32 64
%val = load i64, i64* %valp2 %val = load i64, i64* %valp2
%ins = insertelement <vscale x 2 x i64> undef, i64 %val, i32 0 %ins = insertelement <vscale x 2 x i64> undef, i64 %val, i32 0
%shf = shufflevector <vscale x 2 x i64> %ins, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer %shf = shufflevector <vscale x 2 x i64> %ins, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
ret <vscale x 2 x i64> %shf ret <vscale x 2 x i64> %shf
} }
define <vscale x 2 x i64> @ld1rd_gep_out_of_range_down(i64* %valp) { define <vscale x 2 x i64> @ld1rd_gep_out_of_range_down(i64* %valp) {
; CHECK-LABEL: ld1rd_gep_out_of_range_down: ; CHECK-LABEL: ld1rd_gep_out_of_range_down:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x0, #8 // =8 ; CHECK-NEXT: sub x8, x0, #8
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1rd { z0.d }, p0/z, [x8] ; CHECK-NEXT: ld1rd { z0.d }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr i64, i64* %valp, i32 -1 %valp2 = getelementptr i64, i64* %valp, i32 -1
%val = load i64, i64* %valp2 %val = load i64, i64* %valp2
%ins = insertelement <vscale x 2 x i64> undef, i64 %val, i32 0 %ins = insertelement <vscale x 2 x i64> undef, i64 %val, i32 0
%shf = shufflevector <vscale x 2 x i64> %ins, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer %shf = shufflevector <vscale x 2 x i64> %ins, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
ret <vscale x 2 x i64> %shf ret <vscale x 2 x i64> %shf
Show All 22 Lines; CHECK-NEXT: ret
%ins = insertelement <vscale x 8 x half> undef, half %val, i32 0 %ins = insertelement <vscale x 8 x half> undef, half %val, i32 0
%shf = shufflevector <vscale x 8 x half> %ins, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %shf = shufflevector <vscale x 8 x half> %ins, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
ret <vscale x 8 x half> %shf ret <vscale x 8 x half> %shf
} }
define <vscale x 8 x half> @ld1rh_half_gep_out_of_range_up(half* %valp) { define <vscale x 8 x half> @ld1rh_half_gep_out_of_range_up(half* %valp) {
; CHECK-LABEL: ld1rh_half_gep_out_of_range_up: ; CHECK-LABEL: ld1rh_half_gep_out_of_range_up:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #128 // =128 ; CHECK-NEXT: add x8, x0, #128
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ld1rh { z0.h }, p0/z, [x8] ; CHECK-NEXT: ld1rh { z0.h }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr half, half* %valp, i32 64 %valp2 = getelementptr half, half* %valp, i32 64
%val = load half, half* %valp2 %val = load half, half* %valp2
%ins = insertelement <vscale x 8 x half> undef, half %val, i32 0 %ins = insertelement <vscale x 8 x half> undef, half %val, i32 0
%shf = shufflevector <vscale x 8 x half> %ins, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %shf = shufflevector <vscale x 8 x half> %ins, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
ret <vscale x 8 x half> %shf ret <vscale x 8 x half> %shf
} }
define <vscale x 8 x half> @ld1rh_half_gep_out_of_range_down(half* %valp) { define <vscale x 8 x half> @ld1rh_half_gep_out_of_range_down(half* %valp) {
; CHECK-LABEL: ld1rh_half_gep_out_of_range_down: ; CHECK-LABEL: ld1rh_half_gep_out_of_range_down:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x0, #2 // =2 ; CHECK-NEXT: sub x8, x0, #2
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ld1rh { z0.h }, p0/z, [x8] ; CHECK-NEXT: ld1rh { z0.h }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr half, half* %valp, i32 -1 %valp2 = getelementptr half, half* %valp, i32 -1
%val = load half, half* %valp2 %val = load half, half* %valp2
%ins = insertelement <vscale x 8 x half> undef, half %val, i32 0 %ins = insertelement <vscale x 8 x half> undef, half %val, i32 0
%shf = shufflevector <vscale x 8 x half> %ins, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %shf = shufflevector <vscale x 8 x half> %ins, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
ret <vscale x 8 x half> %shf ret <vscale x 8 x half> %shf
Show All 22 Lines; CHECK-NEXT: ret
%ins = insertelement <vscale x 4 x half> undef, half %val, i32 0 %ins = insertelement <vscale x 4 x half> undef, half %val, i32 0
%shf = shufflevector <vscale x 4 x half> %ins, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer %shf = shufflevector <vscale x 4 x half> %ins, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
ret <vscale x 4 x half> %shf ret <vscale x 4 x half> %shf
} }
define <vscale x 4 x half> @ld1rh_half_unpacked4_gep_out_of_range_up(half* %valp) { define <vscale x 4 x half> @ld1rh_half_unpacked4_gep_out_of_range_up(half* %valp) {
; CHECK-LABEL: ld1rh_half_unpacked4_gep_out_of_range_up: ; CHECK-LABEL: ld1rh_half_unpacked4_gep_out_of_range_up:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #128 // =128 ; CHECK-NEXT: add x8, x0, #128
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1rh { z0.s }, p0/z, [x8] ; CHECK-NEXT: ld1rh { z0.s }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr half, half* %valp, i32 64 %valp2 = getelementptr half, half* %valp, i32 64
%val = load half, half* %valp2 %val = load half, half* %valp2
%ins = insertelement <vscale x 4 x half> undef, half %val, i32 0 %ins = insertelement <vscale x 4 x half> undef, half %val, i32 0
%shf = shufflevector <vscale x 4 x half> %ins, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer %shf = shufflevector <vscale x 4 x half> %ins, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
ret <vscale x 4 x half> %shf ret <vscale x 4 x half> %shf
} }
define <vscale x 4 x half> @ld1rh_half_unpacked4_gep_out_of_range_down(half* %valp) { define <vscale x 4 x half> @ld1rh_half_unpacked4_gep_out_of_range_down(half* %valp) {
; CHECK-LABEL: ld1rh_half_unpacked4_gep_out_of_range_down: ; CHECK-LABEL: ld1rh_half_unpacked4_gep_out_of_range_down:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x0, #2 // =2 ; CHECK-NEXT: sub x8, x0, #2
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1rh { z0.s }, p0/z, [x8] ; CHECK-NEXT: ld1rh { z0.s }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr half, half* %valp, i32 -1 %valp2 = getelementptr half, half* %valp, i32 -1
%val = load half, half* %valp2 %val = load half, half* %valp2
%ins = insertelement <vscale x 4 x half> undef, half %val, i32 0 %ins = insertelement <vscale x 4 x half> undef, half %val, i32 0
%shf = shufflevector <vscale x 4 x half> %ins, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer %shf = shufflevector <vscale x 4 x half> %ins, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
ret <vscale x 4 x half> %shf ret <vscale x 4 x half> %shf
Show All 22 Lines; CHECK-NEXT: ret
%ins = insertelement <vscale x 2 x half> undef, half %val, i32 0 %ins = insertelement <vscale x 2 x half> undef, half %val, i32 0
%shf = shufflevector <vscale x 2 x half> %ins, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer %shf = shufflevector <vscale x 2 x half> %ins, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
ret <vscale x 2 x half> %shf ret <vscale x 2 x half> %shf
} }
define <vscale x 2 x half> @ld1rh_half_unpacked2_gep_out_of_range_up(half* %valp) { define <vscale x 2 x half> @ld1rh_half_unpacked2_gep_out_of_range_up(half* %valp) {
; CHECK-LABEL: ld1rh_half_unpacked2_gep_out_of_range_up: ; CHECK-LABEL: ld1rh_half_unpacked2_gep_out_of_range_up:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #128 // =128 ; CHECK-NEXT: add x8, x0, #128
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1rh { z0.d }, p0/z, [x8] ; CHECK-NEXT: ld1rh { z0.d }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr half, half* %valp, i32 64 %valp2 = getelementptr half, half* %valp, i32 64
%val = load half, half* %valp2 %val = load half, half* %valp2
%ins = insertelement <vscale x 2 x half> undef, half %val, i32 0 %ins = insertelement <vscale x 2 x half> undef, half %val, i32 0
%shf = shufflevector <vscale x 2 x half> %ins, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer %shf = shufflevector <vscale x 2 x half> %ins, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
ret <vscale x 2 x half> %shf ret <vscale x 2 x half> %shf
} }
define <vscale x 2 x half> @ld1rh_half_unpacked2_gep_out_of_range_down(half* %valp) { define <vscale x 2 x half> @ld1rh_half_unpacked2_gep_out_of_range_down(half* %valp) {
; CHECK-LABEL: ld1rh_half_unpacked2_gep_out_of_range_down: ; CHECK-LABEL: ld1rh_half_unpacked2_gep_out_of_range_down:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x0, #2 // =2 ; CHECK-NEXT: sub x8, x0, #2
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1rh { z0.d }, p0/z, [x8] ; CHECK-NEXT: ld1rh { z0.d }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr half, half* %valp, i32 -1 %valp2 = getelementptr half, half* %valp, i32 -1
%val = load half, half* %valp2 %val = load half, half* %valp2
%ins = insertelement <vscale x 2 x half> undef, half %val, i32 0 %ins = insertelement <vscale x 2 x half> undef, half %val, i32 0
%shf = shufflevector <vscale x 2 x half> %ins, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer %shf = shufflevector <vscale x 2 x half> %ins, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
ret <vscale x 2 x half> %shf ret <vscale x 2 x half> %shf
Show All 22 Lines; CHECK-NEXT: ret
%ins = insertelement <vscale x 4 x float> undef, float %val, i32 0 %ins = insertelement <vscale x 4 x float> undef, float %val, i32 0
%shf = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer %shf = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
ret <vscale x 4 x float> %shf ret <vscale x 4 x float> %shf
} }
define <vscale x 4 x float> @ld1rw_float_gep_out_of_range_up(float* %valp) { define <vscale x 4 x float> @ld1rw_float_gep_out_of_range_up(float* %valp) {
; CHECK-LABEL: ld1rw_float_gep_out_of_range_up: ; CHECK-LABEL: ld1rw_float_gep_out_of_range_up:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #256 // =256 ; CHECK-NEXT: add x8, x0, #256
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1rw { z0.s }, p0/z, [x8] ; CHECK-NEXT: ld1rw { z0.s }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr float, float* %valp, i32 64 %valp2 = getelementptr float, float* %valp, i32 64
%val = load float, float* %valp2 %val = load float, float* %valp2
%ins = insertelement <vscale x 4 x float> undef, float %val, i32 0 %ins = insertelement <vscale x 4 x float> undef, float %val, i32 0
%shf = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer %shf = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
ret <vscale x 4 x float> %shf ret <vscale x 4 x float> %shf
} }
define <vscale x 4 x float> @ld1rw_float_gep_out_of_range_down(float* %valp) { define <vscale x 4 x float> @ld1rw_float_gep_out_of_range_down(float* %valp) {
; CHECK-LABEL: ld1rw_float_gep_out_of_range_down: ; CHECK-LABEL: ld1rw_float_gep_out_of_range_down:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x0, #4 // =4 ; CHECK-NEXT: sub x8, x0, #4
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1rw { z0.s }, p0/z, [x8] ; CHECK-NEXT: ld1rw { z0.s }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr float, float* %valp, i32 -1 %valp2 = getelementptr float, float* %valp, i32 -1
%val = load float, float* %valp2 %val = load float, float* %valp2
%ins = insertelement <vscale x 4 x float> undef, float %val, i32 0 %ins = insertelement <vscale x 4 x float> undef, float %val, i32 0
%shf = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer %shf = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
ret <vscale x 4 x float> %shf ret <vscale x 4 x float> %shf
Show All 22 Lines; CHECK-NEXT: ret
%ins = insertelement <vscale x 2 x float> undef, float %val, i32 0 %ins = insertelement <vscale x 2 x float> undef, float %val, i32 0
%shf = shufflevector <vscale x 2 x float> %ins, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer %shf = shufflevector <vscale x 2 x float> %ins, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
ret <vscale x 2 x float> %shf ret <vscale x 2 x float> %shf
} }
define <vscale x 2 x float> @ld1rw_float_unpacked2_gep_out_of_range_up(float* %valp) { define <vscale x 2 x float> @ld1rw_float_unpacked2_gep_out_of_range_up(float* %valp) {
; CHECK-LABEL: ld1rw_float_unpacked2_gep_out_of_range_up: ; CHECK-LABEL: ld1rw_float_unpacked2_gep_out_of_range_up:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #256 // =256 ; CHECK-NEXT: add x8, x0, #256
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1rw { z0.d }, p0/z, [x8] ; CHECK-NEXT: ld1rw { z0.d }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr float, float* %valp, i32 64 %valp2 = getelementptr float, float* %valp, i32 64
%val = load float, float* %valp2 %val = load float, float* %valp2
%ins = insertelement <vscale x 2 x float> undef, float %val, i32 0 %ins = insertelement <vscale x 2 x float> undef, float %val, i32 0
%shf = shufflevector <vscale x 2 x float> %ins, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer %shf = shufflevector <vscale x 2 x float> %ins, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
ret <vscale x 2 x float> %shf ret <vscale x 2 x float> %shf
} }
define <vscale x 2 x float> @ld1rw_float_unpacked2_gep_out_of_range_down(float* %valp) { define <vscale x 2 x float> @ld1rw_float_unpacked2_gep_out_of_range_down(float* %valp) {
; CHECK-LABEL: ld1rw_float_unpacked2_gep_out_of_range_down: ; CHECK-LABEL: ld1rw_float_unpacked2_gep_out_of_range_down:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x0, #4 // =4 ; CHECK-NEXT: sub x8, x0, #4
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1rw { z0.d }, p0/z, [x8] ; CHECK-NEXT: ld1rw { z0.d }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr float, float* %valp, i32 -1 %valp2 = getelementptr float, float* %valp, i32 -1
%val = load float, float* %valp2 %val = load float, float* %valp2
%ins = insertelement <vscale x 2 x float> undef, float %val, i32 0 %ins = insertelement <vscale x 2 x float> undef, float %val, i32 0
%shf = shufflevector <vscale x 2 x float> %ins, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer %shf = shufflevector <vscale x 2 x float> %ins, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
ret <vscale x 2 x float> %shf ret <vscale x 2 x float> %shf
Show All 22 Lines; CHECK-NEXT: ret
%ins = insertelement <vscale x 2 x double> undef, double %val, i32 0 %ins = insertelement <vscale x 2 x double> undef, double %val, i32 0
%shf = shufflevector <vscale x 2 x double> %ins, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer %shf = shufflevector <vscale x 2 x double> %ins, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
ret <vscale x 2 x double> %shf ret <vscale x 2 x double> %shf
} }
define <vscale x 2 x double> @ld1rd_double_gep_out_of_range_up(double* %valp) { define <vscale x 2 x double> @ld1rd_double_gep_out_of_range_up(double* %valp) {
; CHECK-LABEL: ld1rd_double_gep_out_of_range_up: ; CHECK-LABEL: ld1rd_double_gep_out_of_range_up:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, #512 // =512 ; CHECK-NEXT: add x8, x0, #512
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1rd { z0.d }, p0/z, [x8] ; CHECK-NEXT: ld1rd { z0.d }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr double, double* %valp, i32 64 %valp2 = getelementptr double, double* %valp, i32 64
%val = load double, double* %valp2 %val = load double, double* %valp2
%ins = insertelement <vscale x 2 x double> undef, double %val, i32 0 %ins = insertelement <vscale x 2 x double> undef, double %val, i32 0
%shf = shufflevector <vscale x 2 x double> %ins, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer %shf = shufflevector <vscale x 2 x double> %ins, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
ret <vscale x 2 x double> %shf ret <vscale x 2 x double> %shf
} }
define <vscale x 2 x double> @ld1rd_double_gep_out_of_range_down(double* %valp) { define <vscale x 2 x double> @ld1rd_double_gep_out_of_range_down(double* %valp) {
; CHECK-LABEL: ld1rd_double_gep_out_of_range_down: ; CHECK-LABEL: ld1rd_double_gep_out_of_range_down:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x0, #8 // =8 ; CHECK-NEXT: sub x8, x0, #8
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1rd { z0.d }, p0/z, [x8] ; CHECK-NEXT: ld1rd { z0.d }, p0/z, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%valp2 = getelementptr double, double* %valp, i32 -1 %valp2 = getelementptr double, double* %valp, i32 -1
%val = load double, double* %valp2 %val = load double, double* %valp2
%ins = insertelement <vscale x 2 x double> undef, double %val, i32 0 %ins = insertelement <vscale x 2 x double> undef, double %val, i32 0
%shf = shufflevector <vscale x 2 x double> %ins, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer %shf = shufflevector <vscale x 2 x double> %ins, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
ret <vscale x 2 x double> %shf ret <vscale x 2 x double> %shf
} }

llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; ASM-NEXT: cnth x9 ; ASM-NEXT: cnth x9
; ASM-NEXT: ptrue p0.h ; ASM-NEXT: ptrue p0.h
; ASM-NEXT: .LBB0_1: // %loop ; ASM-NEXT: .LBB0_1: // %loop
; ASM-NEXT: // =>This Inner Loop Header: Depth=1 ; ASM-NEXT: // =>This Inner Loop Header: Depth=1
; ASM-NEXT: ld1h { z1.h }, p0/z, [x0, x8, lsl #1] ; ASM-NEXT: ld1h { z1.h }, p0/z, [x0, x8, lsl #1]
; ASM-NEXT: add z1.h, z1.h, z0.h ; ASM-NEXT: add z1.h, z1.h, z0.h
; ASM-NEXT: st1h { z1.h }, p0, [x1, x8, lsl #1] ; ASM-NEXT: st1h { z1.h }, p0, [x1, x8, lsl #1]
; ASM-NEXT: add x8, x8, x9 ; ASM-NEXT: add x8, x8, x9
; ASM-NEXT: cmp x8, #1024 // =1024 ; ASM-NEXT: cmp x8, #1024
; ASM-NEXT: b.ne .LBB0_1 ; ASM-NEXT: b.ne .LBB0_1
; ASM-NEXT: // %bb.2: // %exit ; ASM-NEXT: // %bb.2: // %exit
; ASM-NEXT: ret ; ASM-NEXT: ret
entry: entry:
br label %loop.ph br label %loop.ph
loop.ph: loop.ph:
%p_vec.splatinsert = insertelement <vscale x 8 x i16> undef, i16 3, i32 0 %p_vec.splatinsert = insertelement <vscale x 8 x i16> undef, i16 3, i32 0
▲ Show 20 Lines • Show All 107 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll

Show All 20 Lines
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: rdvl x10, #2 ; CHECK-NEXT: rdvl x10, #2
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 ; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x9, w0 ; CHECK-NEXT: sxtw x9, w0
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: cmp x9, x10 ; CHECK-NEXT: cmp x9, x10
; CHECK-NEXT: st1b { z1.b }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1b { z1.b }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1b { z0.b }, p0, [sp] ; CHECK-NEXT: st1b { z0.b }, p0, [sp]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: ldrb w0, [x8, x9] ; CHECK-NEXT: ldrb w0, [x8, x9]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ext = extractelement <vscale x 32 x i8> %a, i32 %idx %ext = extractelement <vscale x 32 x i8> %a, i32 %idx
ret i8 %ext ret i8 %ext
} }
define i16 @split_extract_16i16_idx(<vscale x 16 x i16> %a, i32 %idx) { define i16 @split_extract_16i16_idx(<vscale x 16 x i16> %a, i32 %idx) {
; CHECK-LABEL: split_extract_16i16_idx: ; CHECK-LABEL: split_extract_16i16_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: rdvl x10, #1 ; CHECK-NEXT: rdvl x10, #1
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 ; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x9, w0 ; CHECK-NEXT: sxtw x9, w0
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: cmp x9, x10 ; CHECK-NEXT: cmp x9, x10
; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: ldrh w0, [x8, x9, lsl #1] ; CHECK-NEXT: ldrh w0, [x8, x9, lsl #1]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ext = extractelement <vscale x 16 x i16> %a, i32 %idx %ext = extractelement <vscale x 16 x i16> %a, i32 %idx
ret i16 %ext ret i16 %ext
} }
define i32 @split_extract_8i32_idx(<vscale x 8 x i32> %a, i32 %idx) { define i32 @split_extract_8i32_idx(<vscale x 8 x i32> %a, i32 %idx) {
; CHECK-LABEL: split_extract_8i32_idx: ; CHECK-LABEL: split_extract_8i32_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: cnth x10 ; CHECK-NEXT: cnth x10
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 ; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x9, w0 ; CHECK-NEXT: sxtw x9, w0
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: cmp x9, x10 ; CHECK-NEXT: cmp x9, x10
; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: ldr w0, [x8, x9, lsl #2] ; CHECK-NEXT: ldr w0, [x8, x9, lsl #2]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ext = extractelement <vscale x 8 x i32> %a, i32 %idx %ext = extractelement <vscale x 8 x i32> %a, i32 %idx
ret i32 %ext ret i32 %ext
} }
define i64 @split_extract_8i64_idx(<vscale x 8 x i64> %a, i32 %idx) { define i64 @split_extract_8i64_idx(<vscale x 8 x i64> %a, i32 %idx) {
; CHECK-LABEL: split_extract_8i64_idx: ; CHECK-LABEL: split_extract_8i64_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-4 ; CHECK-NEXT: addvl sp, sp, #-4
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: cnth x10 ; CHECK-NEXT: cnth x10
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 ; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x9, w0 ; CHECK-NEXT: sxtw x9, w0
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: cmp x9, x10 ; CHECK-NEXT: cmp x9, x10
; CHECK-NEXT: st1d { z3.d }, p0, [x8, #3, mul vl] ; CHECK-NEXT: st1d { z3.d }, p0, [x8, #3, mul vl]
; CHECK-NEXT: st1d { z2.d }, p0, [x8, #2, mul vl] ; CHECK-NEXT: st1d { z2.d }, p0, [x8, #2, mul vl]
; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
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define i16 @split_extract_16i16(<vscale x 16 x i16> %a) { define i16 @split_extract_16i16(<vscale x 16 x i16> %a) {
; CHECK-LABEL: split_extract_16i16: ; CHECK-LABEL: split_extract_16i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: rdvl x10, #1 ; CHECK-NEXT: rdvl x10, #1
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w9, #128 ; CHECK-NEXT: mov w9, #128
; CHECK-NEXT: cmp x10, #128 // =128 ; CHECK-NEXT: cmp x10, #128
; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: ldrh w0, [x8, x9, lsl #1] ; CHECK-NEXT: ldrh w0, [x8, x9, lsl #1]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ext = extractelement <vscale x 16 x i16> %a, i32 128 %ext = extractelement <vscale x 16 x i16> %a, i32 128
ret i16 %ext ret i16 %ext
} }
define i32 @split_extract_16i32(<vscale x 16 x i32> %a) { define i32 @split_extract_16i32(<vscale x 16 x i32> %a) {
; CHECK-LABEL: split_extract_16i32: ; CHECK-LABEL: split_extract_16i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-4 ; CHECK-NEXT: addvl sp, sp, #-4
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: mov w9, #34464 ; CHECK-NEXT: mov w9, #34464
; CHECK-NEXT: rdvl x10, #1 ; CHECK-NEXT: rdvl x10, #1
; CHECK-NEXT: movk w9, #1, lsl #16 ; CHECK-NEXT: movk w9, #1, lsl #16
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: cmp x10, x9 ; CHECK-NEXT: cmp x10, x9
; CHECK-NEXT: st1w { z3.s }, p0, [x8, #3, mul vl] ; CHECK-NEXT: st1w { z3.s }, p0, [x8, #3, mul vl]
; CHECK-NEXT: st1w { z2.s }, p0, [x8, #2, mul vl] ; CHECK-NEXT: st1w { z2.s }, p0, [x8, #2, mul vl]
; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: ldr w0, [x8, x9, lsl #2] ; CHECK-NEXT: ldr w0, [x8, x9, lsl #2]
; CHECK-NEXT: addvl sp, sp, #4 ; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ext = extractelement <vscale x 16 x i32> %a, i32 100000 %ext = extractelement <vscale x 16 x i32> %a, i32 100000
ret i32 %ext ret i32 %ext
} }
define i64 @split_extract_4i64(<vscale x 4 x i64> %a) { define i64 @split_extract_4i64(<vscale x 4 x i64> %a) {
; CHECK-LABEL: split_extract_4i64: ; CHECK-LABEL: split_extract_4i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: cntw x10 ; CHECK-NEXT: cntw x10
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w9, #10 ; CHECK-NEXT: mov w9, #10
; CHECK-NEXT: cmp x10, #10 // =10 ; CHECK-NEXT: cmp x10, #10
; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: ldr x0, [x8, x9, lsl #3] ; CHECK-NEXT: ldr x0, [x8, x9, lsl #3]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ext = extractelement <vscale x 4 x i64> %a, i32 10 %ext = extractelement <vscale x 4 x i64> %a, i32 10
ret i64 %ext ret i64 %ext
} }

llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll

Show All 18 Lines
define <vscale x 32 x i8> @split_insert_32i8_idx(<vscale x 32 x i8> %a, i8 %elt, i64 %idx) { define <vscale x 32 x i8> @split_insert_32i8_idx(<vscale x 32 x i8> %a, i8 %elt, i64 %idx) {
; CHECK-LABEL: split_insert_32i8_idx: ; CHECK-LABEL: split_insert_32i8_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: rdvl x8, #2 ; CHECK-NEXT: rdvl x8, #2
; CHECK-NEXT: sub x8, x8, #1 // =1 ; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: cmp x1, x8 ; CHECK-NEXT: cmp x1, x8
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: csel x8, x1, x8, lo ; CHECK-NEXT: csel x8, x1, x8, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st1b { z1.b }, p0, [x9, #1, mul vl] ; CHECK-NEXT: st1b { z1.b }, p0, [x9, #1, mul vl]
; CHECK-NEXT: st1b { z0.b }, p0, [sp] ; CHECK-NEXT: st1b { z0.b }, p0, [sp]
; CHECK-NEXT: strb w0, [x9, x8] ; CHECK-NEXT: strb w0, [x9, x8]
; CHECK-NEXT: ld1b { z1.b }, p0/z, [x9, #1, mul vl] ; CHECK-NEXT: ld1b { z1.b }, p0/z, [x9, #1, mul vl]
; CHECK-NEXT: ld1b { z0.b }, p0/z, [sp] ; CHECK-NEXT: ld1b { z0.b }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ins = insertelement <vscale x 32 x i8> %a, i8 %elt, i64 %idx %ins = insertelement <vscale x 32 x i8> %a, i8 %elt, i64 %idx
ret <vscale x 32 x i8> %ins ret <vscale x 32 x i8> %ins
} }
define <vscale x 8 x float> @split_insert_8f32_idx(<vscale x 8 x float> %a, float %elt, i64 %idx) { define <vscale x 8 x float> @split_insert_8f32_idx(<vscale x 8 x float> %a, float %elt, i64 %idx) {
; CHECK-LABEL: split_insert_8f32_idx: ; CHECK-LABEL: split_insert_8f32_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: cnth x8 ; CHECK-NEXT: cnth x8
; CHECK-NEXT: sub x8, x8, #1 // =1 ; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: cmp x0, x8 ; CHECK-NEXT: cmp x0, x8
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: csel x8, x0, x8, lo ; CHECK-NEXT: csel x8, x0, x8, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st1w { z1.s }, p0, [x9, #1, mul vl] ; CHECK-NEXT: st1w { z1.s }, p0, [x9, #1, mul vl]
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: str s2, [x9, x8, lsl #2] ; CHECK-NEXT: str s2, [x9, x8, lsl #2]
; CHECK-NEXT: ld1w { z1.s }, p0/z, [x9, #1, mul vl] ; CHECK-NEXT: ld1w { z1.s }, p0/z, [x9, #1, mul vl]
; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ins = insertelement <vscale x 8 x float> %a, float %elt, i64 %idx %ins = insertelement <vscale x 8 x float> %a, float %elt, i64 %idx
ret <vscale x 8 x float> %ins ret <vscale x 8 x float> %ins
} }
define <vscale x 8 x i64> @split_insert_8i64_idx(<vscale x 8 x i64> %a, i64 %elt, i64 %idx) { define <vscale x 8 x i64> @split_insert_8i64_idx(<vscale x 8 x i64> %a, i64 %elt, i64 %idx) {
; CHECK-LABEL: split_insert_8i64_idx: ; CHECK-LABEL: split_insert_8i64_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-4 ; CHECK-NEXT: addvl sp, sp, #-4
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: cnth x8 ; CHECK-NEXT: cnth x8
; CHECK-NEXT: sub x8, x8, #1 // =1 ; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: cmp x1, x8 ; CHECK-NEXT: cmp x1, x8
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: csel x8, x1, x8, lo ; CHECK-NEXT: csel x8, x1, x8, lo
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st1d { z3.d }, p0, [x9, #3, mul vl] ; CHECK-NEXT: st1d { z3.d }, p0, [x9, #3, mul vl]
; CHECK-NEXT: st1d { z2.d }, p0, [x9, #2, mul vl] ; CHECK-NEXT: st1d { z2.d }, p0, [x9, #2, mul vl]
; CHECK-NEXT: st1d { z1.d }, p0, [x9, #1, mul vl] ; CHECK-NEXT: st1d { z1.d }, p0, [x9, #1, mul vl]
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
define <vscale x 32 x i16> @split_insert_32i16(<vscale x 32 x i16> %a, i16 %elt) { define <vscale x 32 x i16> @split_insert_32i16(<vscale x 32 x i16> %a, i16 %elt) {
; CHECK-LABEL: split_insert_32i16: ; CHECK-LABEL: split_insert_32i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-4 ; CHECK-NEXT: addvl sp, sp, #-4
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: rdvl x10, #2 ; CHECK-NEXT: rdvl x10, #2
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: mov w9, #128 ; CHECK-NEXT: mov w9, #128
; CHECK-NEXT: cmp x10, #128 // =128 ; CHECK-NEXT: cmp x10, #128
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: st1h { z3.h }, p0, [x8, #3, mul vl] ; CHECK-NEXT: st1h { z3.h }, p0, [x8, #3, mul vl]
; CHECK-NEXT: st1h { z2.h }, p0, [x8, #2, mul vl] ; CHECK-NEXT: st1h { z2.h }, p0, [x8, #2, mul vl]
; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: strh w0, [x8, x9, lsl #1] ; CHECK-NEXT: strh w0, [x8, x9, lsl #1]
Show All 13 Lines
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: mov w9, #16960 ; CHECK-NEXT: mov w9, #16960
; CHECK-NEXT: cnth x10 ; CHECK-NEXT: cnth x10
; CHECK-NEXT: movk w9, #15, lsl #16 ; CHECK-NEXT: movk w9, #15, lsl #16
; CHECK-NEXT: sub x10, x10, #1 // =1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: cmp x10, x9 ; CHECK-NEXT: cmp x10, x9
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: str w0, [x8, x9, lsl #2] ; CHECK-NEXT: str w0, [x8, x9, lsl #2]
; CHECK-NEXT: ld1w { z1.s }, p0/z, [x8, #1, mul vl] ; CHECK-NEXT: ld1w { z1.s }, p0/z, [x8, #1, mul vl]
; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp]
; CHECK-NEXT: addvl sp, sp, #2 ; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ins = insertelement <vscale x 8 x i32> %a, i32 %elt, i64 1000000 %ins = insertelement <vscale x 8 x i32> %a, i32 %elt, i64 1000000
ret <vscale x 8 x i32> %ins ret <vscale x 8 x i32> %ins
} }

llvm/test/CodeGen/AArch64/uadd_sat.ll

Show All 39 Lines; CHECK-NEXT: ret
ret i16 %tmp; ret i16 %tmp;
} }
define i8 @func8(i8 %x, i8 %y) nounwind { define i8 @func8(i8 %x, i8 %y) nounwind {
; CHECK-LABEL: func8: ; CHECK-LABEL: func8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff ; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: add w8, w8, w1, uxtb ; CHECK-NEXT: add w8, w8, w1, uxtb
; CHECK-NEXT: cmp w8, #255 // =255 ; CHECK-NEXT: cmp w8, #255
; CHECK-NEXT: mov w9, #255 ; CHECK-NEXT: mov w9, #255
; CHECK-NEXT: csel w0, w8, w9, lo ; CHECK-NEXT: csel w0, w8, w9, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %y); %tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %y);
ret i8 %tmp; ret i8 %tmp;
} }
define i4 @func3(i4 %x, i4 %y) nounwind { define i4 @func3(i4 %x, i4 %y) nounwind {
; CHECK-LABEL: func3: ; CHECK-LABEL: func3:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w1, #0xf ; CHECK-NEXT: and w8, w1, #0xf
; CHECK-NEXT: and w9, w0, #0xf ; CHECK-NEXT: and w9, w0, #0xf
; CHECK-NEXT: add w8, w9, w8 ; CHECK-NEXT: add w8, w9, w8
; CHECK-NEXT: cmp w8, #15 // =15 ; CHECK-NEXT: cmp w8, #15
; CHECK-NEXT: mov w9, #15 ; CHECK-NEXT: mov w9, #15
; CHECK-NEXT: csel w0, w8, w9, lo ; CHECK-NEXT: csel w0, w8, w9, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %y); %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %y);
ret i4 %tmp; ret i4 %tmp;
} }

llvm/test/CodeGen/AArch64/uadd_sat_plus.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
} }
define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind { define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
; CHECK-LABEL: func8: ; CHECK-LABEL: func8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff ; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: mul w9, w1, w2 ; CHECK-NEXT: mul w9, w1, w2
; CHECK-NEXT: add w8, w8, w9, uxtb ; CHECK-NEXT: add w8, w8, w9, uxtb
; CHECK-NEXT: cmp w8, #255 // =255 ; CHECK-NEXT: cmp w8, #255
; CHECK-NEXT: mov w9, #255 ; CHECK-NEXT: mov w9, #255
; CHECK-NEXT: csel w0, w8, w9, lo ; CHECK-NEXT: csel w0, w8, w9, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = mul i8 %y, %z %a = mul i8 %y, %z
%tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %a) %tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %a)
ret i8 %tmp ret i8 %tmp
} }
define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind { define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
; CHECK-LABEL: func4: ; CHECK-LABEL: func4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mul w9, w1, w2 ; CHECK-NEXT: mul w9, w1, w2
; CHECK-NEXT: and w8, w0, #0xf ; CHECK-NEXT: and w8, w0, #0xf
; CHECK-NEXT: and w9, w9, #0xf ; CHECK-NEXT: and w9, w9, #0xf
; CHECK-NEXT: add w8, w8, w9 ; CHECK-NEXT: add w8, w8, w9
; CHECK-NEXT: cmp w8, #15 // =15 ; CHECK-NEXT: cmp w8, #15
; CHECK-NEXT: mov w9, #15 ; CHECK-NEXT: mov w9, #15
; CHECK-NEXT: csel w0, w8, w9, lo ; CHECK-NEXT: csel w0, w8, w9, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = mul i4 %y, %z %a = mul i4 %y, %z
%tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %a) %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %a)
ret i4 %tmp ret i4 %tmp
} }

llvm/test/CodeGen/AArch64/uadd_sat_vec.ll

Show First 20 Lines • Show All 349 Lines • ▼ Show 20 Lines
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adds x8, x2, x6 ; CHECK-NEXT: adds x8, x2, x6
; CHECK-NEXT: adcs x9, x3, x7 ; CHECK-NEXT: adcs x9, x3, x7
; CHECK-NEXT: cmp x8, x2 ; CHECK-NEXT: cmp x8, x2
; CHECK-NEXT: cset w10, lo ; CHECK-NEXT: cset w10, lo
; CHECK-NEXT: cmp x9, x3 ; CHECK-NEXT: cmp x9, x3
; CHECK-NEXT: cset w11, lo ; CHECK-NEXT: cset w11, lo
; CHECK-NEXT: csel w10, w10, w11, eq ; CHECK-NEXT: csel w10, w10, w11, eq
; CHECK-NEXT: cmp w10, #0 // =0 ; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: csinv x3, x9, xzr, eq ; CHECK-NEXT: csinv x3, x9, xzr, eq
; CHECK-NEXT: csinv x2, x8, xzr, eq ; CHECK-NEXT: csinv x2, x8, xzr, eq
; CHECK-NEXT: adds x8, x0, x4 ; CHECK-NEXT: adds x8, x0, x4
; CHECK-NEXT: adcs x9, x1, x5 ; CHECK-NEXT: adcs x9, x1, x5
; CHECK-NEXT: cmp x8, x0 ; CHECK-NEXT: cmp x8, x0
; CHECK-NEXT: cset w10, lo ; CHECK-NEXT: cset w10, lo
; CHECK-NEXT: cmp x9, x1 ; CHECK-NEXT: cmp x9, x1
; CHECK-NEXT: cset w11, lo ; CHECK-NEXT: cset w11, lo
; CHECK-NEXT: csel w10, w10, w11, eq ; CHECK-NEXT: csel w10, w10, w11, eq
; CHECK-NEXT: cmp w10, #0 // =0 ; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: csinv x8, x8, xzr, eq ; CHECK-NEXT: csinv x8, x8, xzr, eq
; CHECK-NEXT: csinv x1, x9, xzr, eq ; CHECK-NEXT: csinv x1, x9, xzr, eq
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y) %z = call <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
ret <2 x i128> %z ret <2 x i128> %z
} }

llvm/test/CodeGen/AArch64/uaddo.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
; PR31754 ; PR31754
; The overflow check may be against the input rather than the sum. ; The overflow check may be against the input rather than the sum.
define i1 @uaddo_i64_increment_alt(i64 %x, i64* %p) { define i1 @uaddo_i64_increment_alt(i64 %x, i64* %p) {
; CHECK-LABEL: uaddo_i64_increment_alt: ; CHECK-LABEL: uaddo_i64_increment_alt:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adds x8, x0, #1 // =1 ; CHECK-NEXT: adds x8, x0, #1
; CHECK-NEXT: cset w0, hs ; CHECK-NEXT: cset w0, hs
; CHECK-NEXT: str x8, [x1] ; CHECK-NEXT: str x8, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = add i64 %x, 1 %a = add i64 %x, 1
store i64 %a, i64* %p store i64 %a, i64* %p
%ov = icmp eq i64 %x, -1 %ov = icmp eq i64 %x, -1
ret i1 %ov ret i1 %ov
} }
; Make sure insertion is done correctly based on dominance. ; Make sure insertion is done correctly based on dominance.
define i1 @uaddo_i64_increment_alt_dom(i64 %x, i64* %p) { define i1 @uaddo_i64_increment_alt_dom(i64 %x, i64* %p) {
; CHECK-LABEL: uaddo_i64_increment_alt_dom: ; CHECK-LABEL: uaddo_i64_increment_alt_dom:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adds x8, x0, #1 // =1 ; CHECK-NEXT: adds x8, x0, #1
; CHECK-NEXT: cset w0, hs ; CHECK-NEXT: cset w0, hs
; CHECK-NEXT: str x8, [x1] ; CHECK-NEXT: str x8, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ov = icmp eq i64 %x, -1 %ov = icmp eq i64 %x, -1
%a = add i64 %x, 1 %a = add i64 %x, 1
store i64 %a, i64* %p store i64 %a, i64* %p
ret i1 %ov ret i1 %ov
} }
; The overflow check may be against the input rather than the sum. ; The overflow check may be against the input rather than the sum.
define i1 @uaddo_i64_decrement_alt(i64 %x, i64* %p) { define i1 @uaddo_i64_decrement_alt(i64 %x, i64* %p) {
; CHECK-LABEL: uaddo_i64_decrement_alt: ; CHECK-LABEL: uaddo_i64_decrement_alt:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x0, #1 // =1 ; CHECK-NEXT: subs x8, x0, #1
; CHECK-NEXT: cset w0, hs ; CHECK-NEXT: cset w0, hs
; CHECK-NEXT: str x8, [x1] ; CHECK-NEXT: str x8, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = add i64 %x, -1 %a = add i64 %x, -1
store i64 %a, i64* %p store i64 %a, i64* %p
%ov = icmp ne i64 %x, 0 %ov = icmp ne i64 %x, 0
ret i1 %ov ret i1 %ov
} }
; Make sure insertion is done correctly based on dominance. ; Make sure insertion is done correctly based on dominance.
define i1 @uaddo_i64_decrement_alt_dom(i64 %x, i64* %p) { define i1 @uaddo_i64_decrement_alt_dom(i64 %x, i64* %p) {
; CHECK-LABEL: uaddo_i64_decrement_alt_dom: ; CHECK-LABEL: uaddo_i64_decrement_alt_dom:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x0, #1 // =1 ; CHECK-NEXT: subs x8, x0, #1
; CHECK-NEXT: cset w0, hs ; CHECK-NEXT: cset w0, hs
; CHECK-NEXT: str x8, [x1] ; CHECK-NEXT: str x8, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ov = icmp ne i64 %x, 0 %ov = icmp ne i64 %x, 0
%a = add i64 %x, -1 %a = add i64 %x, -1
store i64 %a, i64* %p store i64 %a, i64* %p
ret i1 %ov ret i1 %ov
} }

llvm/test/CodeGen/AArch64/umulo-128-legalisation-lowering.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s --check-prefixes=AARCH ; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s --check-prefixes=AARCH
define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 { define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
; AARCH-LABEL: muloti_test: ; AARCH-LABEL: muloti_test:
; AARCH: // %bb.0: // %start ; AARCH: // %bb.0: // %start
; AARCH-NEXT: cmp x3, #0 // =0 ; AARCH-NEXT: cmp x3, #0
; AARCH-NEXT: umulh x8, x1, x2 ; AARCH-NEXT: umulh x8, x1, x2
; AARCH-NEXT: cset w10, ne ; AARCH-NEXT: cset w10, ne
; AARCH-NEXT: cmp x1, #0 // =0 ; AARCH-NEXT: cmp x1, #0
; AARCH-NEXT: mul x9, x3, x0 ; AARCH-NEXT: mul x9, x3, x0
; AARCH-NEXT: cset w11, ne ; AARCH-NEXT: cset w11, ne
; AARCH-NEXT: cmp xzr, x8 ; AARCH-NEXT: cmp xzr, x8
; AARCH-NEXT: umulh x8, x3, x0 ; AARCH-NEXT: umulh x8, x3, x0
; AARCH-NEXT: madd x9, x1, x2, x9 ; AARCH-NEXT: madd x9, x1, x2, x9
; AARCH-NEXT: and w10, w11, w10 ; AARCH-NEXT: and w10, w11, w10
; AARCH-NEXT: cset w11, ne ; AARCH-NEXT: cset w11, ne
; AARCH-NEXT: cmp xzr, x8 ; AARCH-NEXT: cmp xzr, x8
Show All 26 Lines

llvm/test/CodeGen/AArch64/unwind-preserved.ll

Show First 20 Lines • Show All 258 Lines • ▼ Show 20 Lines
; Test that q0 is saved/restored, as the unwinder may only retain the low 64bits (d0). ; Test that q0 is saved/restored, as the unwinder may only retain the low 64bits (d0).
define aarch64_vector_pcs <4 x i32> @invoke_callee_may_throw_neon(<4 x i32> %v) personality i8 0 { define aarch64_vector_pcs <4 x i32> @invoke_callee_may_throw_neon(<4 x i32> %v) personality i8 0 {
; CHECK-LABEL: invoke_callee_may_throw_neon: ; CHECK-LABEL: invoke_callee_may_throw_neon:
; CHECK: .Lfunc_begin1: ; CHECK: .Lfunc_begin1:
; CHECK-NEXT: .cfi_startproc ; CHECK-NEXT: .cfi_startproc
; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: sub sp, sp, #304 // =304 ; CHECK-NEXT: sub sp, sp, #304
; CHECK-NEXT: stp q23, q22, [sp, #32] // 32-byte Folded Spill ; CHECK-NEXT: stp q23, q22, [sp, #32] // 32-byte Folded Spill
; CHECK-NEXT: stp q21, q20, [sp, #64] // 32-byte Folded Spill ; CHECK-NEXT: stp q21, q20, [sp, #64] // 32-byte Folded Spill
; CHECK-NEXT: stp q19, q18, [sp, #96] // 32-byte Folded Spill ; CHECK-NEXT: stp q19, q18, [sp, #96] // 32-byte Folded Spill
; CHECK-NEXT: stp q17, q16, [sp, #128] // 32-byte Folded Spill ; CHECK-NEXT: stp q17, q16, [sp, #128] // 32-byte Folded Spill
; CHECK-NEXT: stp q15, q14, [sp, #160] // 32-byte Folded Spill ; CHECK-NEXT: stp q15, q14, [sp, #160] // 32-byte Folded Spill
; CHECK-NEXT: stp q13, q12, [sp, #192] // 32-byte Folded Spill ; CHECK-NEXT: stp q13, q12, [sp, #192] // 32-byte Folded Spill
; CHECK-NEXT: stp q11, q10, [sp, #224] // 32-byte Folded Spill ; CHECK-NEXT: stp q11, q10, [sp, #224] // 32-byte Folded Spill
; CHECK-NEXT: stp q9, q8, [sp, #256] // 32-byte Folded Spill ; CHECK-NEXT: stp q9, q8, [sp, #256] // 32-byte Folded Spill
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; CHECK-NEXT: ldp q9, q8, [sp, #256] // 32-byte Folded Reload ; CHECK-NEXT: ldp q9, q8, [sp, #256] // 32-byte Folded Reload
; CHECK-NEXT: ldp q11, q10, [sp, #224] // 32-byte Folded Reload ; CHECK-NEXT: ldp q11, q10, [sp, #224] // 32-byte Folded Reload
; CHECK-NEXT: ldp q13, q12, [sp, #192] // 32-byte Folded Reload ; CHECK-NEXT: ldp q13, q12, [sp, #192] // 32-byte Folded Reload
; CHECK-NEXT: ldp q15, q14, [sp, #160] // 32-byte Folded Reload ; CHECK-NEXT: ldp q15, q14, [sp, #160] // 32-byte Folded Reload
; CHECK-NEXT: ldp q17, q16, [sp, #128] // 32-byte Folded Reload ; CHECK-NEXT: ldp q17, q16, [sp, #128] // 32-byte Folded Reload
; CHECK-NEXT: ldp q19, q18, [sp, #96] // 32-byte Folded Reload ; CHECK-NEXT: ldp q19, q18, [sp, #96] // 32-byte Folded Reload
; CHECK-NEXT: ldp q21, q20, [sp, #64] // 32-byte Folded Reload ; CHECK-NEXT: ldp q21, q20, [sp, #64] // 32-byte Folded Reload
; CHECK-NEXT: ldp q23, q22, [sp, #32] // 32-byte Folded Reload ; CHECK-NEXT: ldp q23, q22, [sp, #32] // 32-byte Folded Reload
; CHECK-NEXT: add sp, sp, #304 // =304 ; CHECK-NEXT: add sp, sp, #304
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: // %.Lunwind ; CHECK-NEXT: .LBB1_2: // %.Lunwind
; CHECK-NEXT: .Ltmp5: ; CHECK-NEXT: .Ltmp5:
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldp x29, x30, [sp, #288] // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp, #288] // 16-byte Folded Reload
; CHECK-NEXT: ldp q9, q8, [sp, #256] // 32-byte Folded Reload ; CHECK-NEXT: ldp q9, q8, [sp, #256] // 32-byte Folded Reload
; CHECK-NEXT: ldp q11, q10, [sp, #224] // 32-byte Folded Reload ; CHECK-NEXT: ldp q11, q10, [sp, #224] // 32-byte Folded Reload
; CHECK-NEXT: ldp q13, q12, [sp, #192] // 32-byte Folded Reload ; CHECK-NEXT: ldp q13, q12, [sp, #192] // 32-byte Folded Reload
; CHECK-NEXT: ldp q15, q14, [sp, #160] // 32-byte Folded Reload ; CHECK-NEXT: ldp q15, q14, [sp, #160] // 32-byte Folded Reload
; CHECK-NEXT: ldp q17, q16, [sp, #128] // 32-byte Folded Reload ; CHECK-NEXT: ldp q17, q16, [sp, #128] // 32-byte Folded Reload
; CHECK-NEXT: ldp q19, q18, [sp, #96] // 32-byte Folded Reload ; CHECK-NEXT: ldp q19, q18, [sp, #96] // 32-byte Folded Reload
; CHECK-NEXT: ldp q21, q20, [sp, #64] // 32-byte Folded Reload ; CHECK-NEXT: ldp q21, q20, [sp, #64] // 32-byte Folded Reload
; CHECK-NEXT: ldp q23, q22, [sp, #32] // 32-byte Folded Reload ; CHECK-NEXT: ldp q23, q22, [sp, #32] // 32-byte Folded Reload
; CHECK-NEXT: add sp, sp, #304 // =304 ; CHECK-NEXT: add sp, sp, #304
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; GISEL-LABEL: invoke_callee_may_throw_neon: ; GISEL-LABEL: invoke_callee_may_throw_neon:
; GISEL: .Lfunc_begin1: ; GISEL: .Lfunc_begin1:
; GISEL-NEXT: .cfi_startproc ; GISEL-NEXT: .cfi_startproc
; GISEL-NEXT: // %bb.0: ; GISEL-NEXT: // %bb.0:
; GISEL-NEXT: sub sp, sp, #304 // =304 ; GISEL-NEXT: sub sp, sp, #304
; GISEL-NEXT: stp q23, q22, [sp, #32] // 32-byte Folded Spill ; GISEL-NEXT: stp q23, q22, [sp, #32] // 32-byte Folded Spill
; GISEL-NEXT: stp q21, q20, [sp, #64] // 32-byte Folded Spill ; GISEL-NEXT: stp q21, q20, [sp, #64] // 32-byte Folded Spill
; GISEL-NEXT: stp q19, q18, [sp, #96] // 32-byte Folded Spill ; GISEL-NEXT: stp q19, q18, [sp, #96] // 32-byte Folded Spill
; GISEL-NEXT: stp q17, q16, [sp, #128] // 32-byte Folded Spill ; GISEL-NEXT: stp q17, q16, [sp, #128] // 32-byte Folded Spill
; GISEL-NEXT: stp q15, q14, [sp, #160] // 32-byte Folded Spill ; GISEL-NEXT: stp q15, q14, [sp, #160] // 32-byte Folded Spill
; GISEL-NEXT: stp q13, q12, [sp, #192] // 32-byte Folded Spill ; GISEL-NEXT: stp q13, q12, [sp, #192] // 32-byte Folded Spill
; GISEL-NEXT: stp q11, q10, [sp, #224] // 32-byte Folded Spill ; GISEL-NEXT: stp q11, q10, [sp, #224] // 32-byte Folded Spill
; GISEL-NEXT: stp q9, q8, [sp, #256] // 32-byte Folded Spill ; GISEL-NEXT: stp q9, q8, [sp, #256] // 32-byte Folded Spill
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; GISEL-NEXT: ldp q9, q8, [sp, #256] // 32-byte Folded Reload ; GISEL-NEXT: ldp q9, q8, [sp, #256] // 32-byte Folded Reload
; GISEL-NEXT: ldp q11, q10, [sp, #224] // 32-byte Folded Reload ; GISEL-NEXT: ldp q11, q10, [sp, #224] // 32-byte Folded Reload
; GISEL-NEXT: ldp q13, q12, [sp, #192] // 32-byte Folded Reload ; GISEL-NEXT: ldp q13, q12, [sp, #192] // 32-byte Folded Reload
; GISEL-NEXT: ldp q15, q14, [sp, #160] // 32-byte Folded Reload ; GISEL-NEXT: ldp q15, q14, [sp, #160] // 32-byte Folded Reload
; GISEL-NEXT: ldp q17, q16, [sp, #128] // 32-byte Folded Reload ; GISEL-NEXT: ldp q17, q16, [sp, #128] // 32-byte Folded Reload
; GISEL-NEXT: ldp q19, q18, [sp, #96] // 32-byte Folded Reload ; GISEL-NEXT: ldp q19, q18, [sp, #96] // 32-byte Folded Reload
; GISEL-NEXT: ldp q21, q20, [sp, #64] // 32-byte Folded Reload ; GISEL-NEXT: ldp q21, q20, [sp, #64] // 32-byte Folded Reload
; GISEL-NEXT: ldp q23, q22, [sp, #32] // 32-byte Folded Reload ; GISEL-NEXT: ldp q23, q22, [sp, #32] // 32-byte Folded Reload
; GISEL-NEXT: add sp, sp, #304 // =304 ; GISEL-NEXT: add sp, sp, #304
; GISEL-NEXT: ret ; GISEL-NEXT: ret
; GISEL-NEXT: .LBB1_2: // %.Lunwind ; GISEL-NEXT: .LBB1_2: // %.Lunwind
; GISEL-NEXT: .Ltmp5: ; GISEL-NEXT: .Ltmp5:
; GISEL-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; GISEL-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; GISEL-NEXT: ldp x29, x30, [sp, #288] // 16-byte Folded Reload ; GISEL-NEXT: ldp x29, x30, [sp, #288] // 16-byte Folded Reload
; GISEL-NEXT: ldp q9, q8, [sp, #256] // 32-byte Folded Reload ; GISEL-NEXT: ldp q9, q8, [sp, #256] // 32-byte Folded Reload
; GISEL-NEXT: ldp q11, q10, [sp, #224] // 32-byte Folded Reload ; GISEL-NEXT: ldp q11, q10, [sp, #224] // 32-byte Folded Reload
; GISEL-NEXT: ldp q13, q12, [sp, #192] // 32-byte Folded Reload ; GISEL-NEXT: ldp q13, q12, [sp, #192] // 32-byte Folded Reload
; GISEL-NEXT: ldp q15, q14, [sp, #160] // 32-byte Folded Reload ; GISEL-NEXT: ldp q15, q14, [sp, #160] // 32-byte Folded Reload
; GISEL-NEXT: ldp q17, q16, [sp, #128] // 32-byte Folded Reload ; GISEL-NEXT: ldp q17, q16, [sp, #128] // 32-byte Folded Reload
; GISEL-NEXT: ldp q19, q18, [sp, #96] // 32-byte Folded Reload ; GISEL-NEXT: ldp q19, q18, [sp, #96] // 32-byte Folded Reload
; GISEL-NEXT: ldp q21, q20, [sp, #64] // 32-byte Folded Reload ; GISEL-NEXT: ldp q21, q20, [sp, #64] // 32-byte Folded Reload
; GISEL-NEXT: ldp q23, q22, [sp, #32] // 32-byte Folded Reload ; GISEL-NEXT: ldp q23, q22, [sp, #32] // 32-byte Folded Reload
; GISEL-NEXT: add sp, sp, #304 // =304 ; GISEL-NEXT: add sp, sp, #304
; GISEL-NEXT: ret ; GISEL-NEXT: ret
%result = invoke aarch64_vector_pcs <4 x i32> @may_throw_neon(<4 x i32> %v) to label %.Lcontinue unwind label %.Lunwind %result = invoke aarch64_vector_pcs <4 x i32> @may_throw_neon(<4 x i32> %v) to label %.Lcontinue unwind label %.Lunwind
.Lcontinue: .Lcontinue:
ret <4 x i32> %result ret <4 x i32> %result
.Lunwind: .Lunwind:
%lp = landingpad { i8*, i32 } cleanup %lp = landingpad { i8*, i32 } cleanup
ret <4 x i32> %v; ret <4 x i32> %v;
} }
declare aarch64_vector_pcs <4 x i32> @may_throw_neon(<4 x i32> %v); declare aarch64_vector_pcs <4 x i32> @may_throw_neon(<4 x i32> %v);

llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
define i1 @test_urem_odd(i13 %X) nounwind { define i1 @test_urem_odd(i13 %X) nounwind {
; CHECK-LABEL: test_urem_odd: ; CHECK-LABEL: test_urem_odd:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #3277 ; CHECK-NEXT: mov w8, #3277
; CHECK-NEXT: mul w8, w0, w8 ; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: and w8, w8, #0x1fff ; CHECK-NEXT: and w8, w8, #0x1fff
; CHECK-NEXT: cmp w8, #1639 // =1639 ; CHECK-NEXT: cmp w8, #1639
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem i13 %X, 5 %urem = urem i13 %X, 5
%cmp = icmp eq i13 %urem, 0 %cmp = icmp eq i13 %urem, 0
ret i1 %cmp ret i1 %cmp
} }
define i1 @test_urem_even(i27 %X) nounwind { define i1 @test_urem_even(i27 %X) nounwind {
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} }
define i1 @test_urem_odd_setne(i4 %X) nounwind { define i1 @test_urem_odd_setne(i4 %X) nounwind {
; CHECK-LABEL: test_urem_odd_setne: ; CHECK-LABEL: test_urem_odd_setne:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #13 ; CHECK-NEXT: mov w8, #13
; CHECK-NEXT: mul w8, w0, w8 ; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: and w8, w8, #0xf ; CHECK-NEXT: and w8, w8, #0xf
; CHECK-NEXT: cmp w8, #3 // =3 ; CHECK-NEXT: cmp w8, #3
; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: cset w0, hi
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem i4 %X, 5 %urem = urem i4 %X, 5
%cmp = icmp ne i4 %urem, 0 %cmp = icmp ne i4 %urem, 0
ret i1 %cmp ret i1 %cmp
} }
define i1 @test_urem_negative_odd(i9 %X) nounwind { define i1 @test_urem_negative_odd(i9 %X) nounwind {
; CHECK-LABEL: test_urem_negative_odd: ; CHECK-LABEL: test_urem_negative_odd:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #307 ; CHECK-NEXT: mov w8, #307
; CHECK-NEXT: mul w8, w0, w8 ; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: and w8, w8, #0x1ff ; CHECK-NEXT: and w8, w8, #0x1ff
; CHECK-NEXT: cmp w8, #1 // =1 ; CHECK-NEXT: cmp w8, #1
; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: cset w0, hi
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem i9 %X, -5 %urem = urem i9 %X, -5
%cmp = icmp ne i9 %urem, 0 %cmp = icmp ne i9 %urem, 0
ret i1 %cmp ret i1 %cmp
} }
define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind { define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
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llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll

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} }
define i1 @t32_6_3(i32 %X) nounwind { define i1 @t32_6_3(i32 %X) nounwind {
; CHECK-LABEL: t32_6_3: ; CHECK-LABEL: t32_6_3:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #43691 ; CHECK-NEXT: mov w8, #43691
; CHECK-NEXT: movk w8, #43690, lsl #16 ; CHECK-NEXT: movk w8, #43690, lsl #16
; CHECK-NEXT: mul w8, w0, w8 ; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: sub w8, w8, #1 // =1 ; CHECK-NEXT: sub w8, w8, #1
; CHECK-NEXT: mov w9, #43691 ; CHECK-NEXT: mov w9, #43691
; CHECK-NEXT: ror w8, w8, #1 ; CHECK-NEXT: ror w8, w8, #1
; CHECK-NEXT: movk w9, #10922, lsl #16 ; CHECK-NEXT: movk w9, #10922, lsl #16
; CHECK-NEXT: cmp w8, w9 ; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem i32 %X, 6 %urem = urem i32 %X, 6
%cmp = icmp eq i32 %urem, 3 %cmp = icmp eq i32 %urem, 3
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ret i1 %cmp ret i1 %cmp
} }
define i1 @t8_3_2(i8 %X) nounwind { define i1 @t8_3_2(i8 %X) nounwind {
; CHECK-LABEL: t8_3_2: ; CHECK-LABEL: t8_3_2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-85 ; CHECK-NEXT: mov w8, #-85
; CHECK-NEXT: mul w8, w0, w8 ; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: sub w8, w8, #86 // =86 ; CHECK-NEXT: sub w8, w8, #86
; CHECK-NEXT: and w8, w8, #0xff ; CHECK-NEXT: and w8, w8, #0xff
; CHECK-NEXT: cmp w8, #85 // =85 ; CHECK-NEXT: cmp w8, #85
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem i8 %X, 3 %urem = urem i8 %X, 3
%cmp = icmp eq i8 %urem, 2 %cmp = icmp eq i8 %urem, 2
ret i1 %cmp ret i1 %cmp
} }
define i1 @t64_3_2(i64 %X) nounwind { define i1 @t64_3_2(i64 %X) nounwind {
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llvm/test/CodeGen/AArch64/urem-seteq.ll

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; This is like test_urem_odd, except the divisor has bit 30 set. ; This is like test_urem_odd, except the divisor has bit 30 set.
define i32 @test_urem_odd_bit30(i32 %X) nounwind { define i32 @test_urem_odd_bit30(i32 %X) nounwind {
; CHECK-LABEL: test_urem_odd_bit30: ; CHECK-LABEL: test_urem_odd_bit30:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #43691 ; CHECK-NEXT: mov w8, #43691
; CHECK-NEXT: movk w8, #27306, lsl #16 ; CHECK-NEXT: movk w8, #27306, lsl #16
; CHECK-NEXT: mul w8, w0, w8 ; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: cmp w8, #4 // =4 ; CHECK-NEXT: cmp w8, #4
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem i32 %X, 1073741827 %urem = urem i32 %X, 1073741827
%cmp = icmp eq i32 %urem, 0 %cmp = icmp eq i32 %urem, 0
%ret = zext i1 %cmp to i32 %ret = zext i1 %cmp to i32
ret i32 %ret ret i32 %ret
} }
; This is like test_urem_odd, except the divisor has bit 31 set. ; This is like test_urem_odd, except the divisor has bit 31 set.
define i32 @test_urem_odd_bit31(i32 %X) nounwind { define i32 @test_urem_odd_bit31(i32 %X) nounwind {
; CHECK-LABEL: test_urem_odd_bit31: ; CHECK-LABEL: test_urem_odd_bit31:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #43691 ; CHECK-NEXT: mov w8, #43691
; CHECK-NEXT: movk w8, #10922, lsl #16 ; CHECK-NEXT: movk w8, #10922, lsl #16
; CHECK-NEXT: mul w8, w0, w8 ; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: cmp w8, #2 // =2 ; CHECK-NEXT: cmp w8, #2
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem i32 %X, 2147483651 %urem = urem i32 %X, 2147483651
%cmp = icmp eq i32 %urem, 0 %cmp = icmp eq i32 %urem, 0
%ret = zext i1 %cmp to i32 %ret = zext i1 %cmp to i32
ret i32 %ret ret i32 %ret
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; Even divisors ; Even divisors
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
define i16 @test_urem_even(i16 %X) nounwind { define i16 @test_urem_even(i16 %X) nounwind {
; CHECK-LABEL: test_urem_even: ; CHECK-LABEL: test_urem_even:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #28087 ; CHECK-NEXT: mov w8, #28087
; CHECK-NEXT: mul w8, w0, w8 ; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: and w9, w8, #0xfffc ; CHECK-NEXT: and w9, w8, #0xfffc
; CHECK-NEXT: lsr w9, w9, #1 ; CHECK-NEXT: lsr w9, w9, #1
; CHECK-NEXT: bfi w9, w8, #15, #17 ; CHECK-NEXT: bfi w9, w8, #15, #17
; CHECK-NEXT: ubfx w8, w9, #1, #15 ; CHECK-NEXT: ubfx w8, w9, #1, #15
; CHECK-NEXT: cmp w8, #2340 // =2340 ; CHECK-NEXT: cmp w8, #2340
; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: cset w0, hi
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem i16 %X, 14 %urem = urem i16 %X, 14
%cmp = icmp ne i16 %urem, 0 %cmp = icmp ne i16 %urem, 0
%ret = zext i1 %cmp to i16 %ret = zext i1 %cmp to i16
ret i16 %ret ret i16 %ret
} }
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; This is like test_urem_even, except the divisor has bit 30 set. ; This is like test_urem_even, except the divisor has bit 30 set.
define i32 @test_urem_even_bit30(i32 %X) nounwind { define i32 @test_urem_even_bit30(i32 %X) nounwind {
; CHECK-LABEL: test_urem_even_bit30: ; CHECK-LABEL: test_urem_even_bit30:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #20165 ; CHECK-NEXT: mov w8, #20165
; CHECK-NEXT: movk w8, #64748, lsl #16 ; CHECK-NEXT: movk w8, #64748, lsl #16
; CHECK-NEXT: mul w8, w0, w8 ; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: ror w8, w8, #3 ; CHECK-NEXT: ror w8, w8, #3
; CHECK-NEXT: cmp w8, #4 // =4 ; CHECK-NEXT: cmp w8, #4
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem i32 %X, 1073741928 %urem = urem i32 %X, 1073741928
%cmp = icmp eq i32 %urem, 0 %cmp = icmp eq i32 %urem, 0
%ret = zext i1 %cmp to i32 %ret = zext i1 %cmp to i32
ret i32 %ret ret i32 %ret
} }
; This is like test_urem_odd, except the divisor has bit 31 set. ; This is like test_urem_odd, except the divisor has bit 31 set.
define i32 @test_urem_even_bit31(i32 %X) nounwind { define i32 @test_urem_even_bit31(i32 %X) nounwind {
; CHECK-LABEL: test_urem_even_bit31: ; CHECK-LABEL: test_urem_even_bit31:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #64251 ; CHECK-NEXT: mov w8, #64251
; CHECK-NEXT: movk w8, #47866, lsl #16 ; CHECK-NEXT: movk w8, #47866, lsl #16
; CHECK-NEXT: mul w8, w0, w8 ; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: ror w8, w8, #1 ; CHECK-NEXT: ror w8, w8, #1
; CHECK-NEXT: cmp w8, #2 // =2 ; CHECK-NEXT: cmp w8, #2
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem i32 %X, 2147483750 %urem = urem i32 %X, 2147483750
%cmp = icmp eq i32 %urem, 0 %cmp = icmp eq i32 %urem, 0
%ret = zext i1 %cmp to i32 %ret = zext i1 %cmp to i32
ret i32 %ret ret i32 %ret
} }
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} }
; The fold is only valid for positive divisors, negative-ones should be negated. ; The fold is only valid for positive divisors, negative-ones should be negated.
define i32 @test_urem_negative_odd(i32 %X) nounwind { define i32 @test_urem_negative_odd(i32 %X) nounwind {
; CHECK-LABEL: test_urem_negative_odd: ; CHECK-LABEL: test_urem_negative_odd:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #858993459 ; CHECK-NEXT: mov w8, #858993459
; CHECK-NEXT: mul w8, w0, w8 ; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: cmp w8, #1 // =1 ; CHECK-NEXT: cmp w8, #1
; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: cset w0, hi
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem i32 %X, -5 %urem = urem i32 %X, -5
%cmp = icmp ne i32 %urem, 0 %cmp = icmp ne i32 %urem, 0
%ret = zext i1 %cmp to i32 %ret = zext i1 %cmp to i32
ret i32 %ret ret i32 %ret
} }
define i32 @test_urem_negative_even(i32 %X) nounwind { define i32 @test_urem_negative_even(i32 %X) nounwind {
; CHECK-LABEL: test_urem_negative_even: ; CHECK-LABEL: test_urem_negative_even:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #37449 ; CHECK-NEXT: mov w8, #37449
; CHECK-NEXT: movk w8, #51492, lsl #16 ; CHECK-NEXT: movk w8, #51492, lsl #16
; CHECK-NEXT: mul w8, w0, w8 ; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: ror w8, w8, #1 ; CHECK-NEXT: ror w8, w8, #1
; CHECK-NEXT: cmp w8, #1 // =1 ; CHECK-NEXT: cmp w8, #1
; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: cset w0, hi
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem i32 %X, -14 %urem = urem i32 %X, -14
%cmp = icmp ne i32 %urem, 0 %cmp = icmp ne i32 %urem, 0
%ret = zext i1 %cmp to i32 %ret = zext i1 %cmp to i32
ret i32 %ret ret i32 %ret
} }
Show All 39 Lines; CHECK-NEXT: ret
ret i32 %ret ret i32 %ret
} }
; We can lower remainder of division by all-ones much better elsewhere. ; We can lower remainder of division by all-ones much better elsewhere.
define i32 @test_urem_allones(i32 %X) nounwind { define i32 @test_urem_allones(i32 %X) nounwind {
; CHECK-LABEL: test_urem_allones: ; CHECK-LABEL: test_urem_allones:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: neg w8, w0 ; CHECK-NEXT: neg w8, w0
; CHECK-NEXT: cmp w8, #2 // =2 ; CHECK-NEXT: cmp w8, #2
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem i32 %X, 4294967295 %urem = urem i32 %X, 4294967295
%cmp = icmp eq i32 %urem, 0 %cmp = icmp eq i32 %urem, 0
%ret = zext i1 %cmp to i32 %ret = zext i1 %cmp to i32
ret i32 %ret ret i32 %ret
} }

llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll

Show All 12 Lines
; for example. ll is PARAM, a_op_b (i.e., a << b) is LHS, _1 (i.e., -1) is RHS. ; for example. ll is PARAM, a_op_b (i.e., a << b) is LHS, _1 (i.e., -1) is RHS.
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
define i64 @ll_a_op_b__2(i64 %a, i64 %b) { define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_op_b__2: ; CHECK-LABEL: ll_a_op_b__2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl x8, x0, x1 ; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: cmn x8, #2 // =2 ; CHECK-NEXT: cmn x8, #2
; CHECK-NEXT: csinc x8, x1, xzr, eq ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x8, x8, x0 ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: csel x0, x1, x8, gt ; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shl = shl i64 %a, %b %shl = shl i64 %a, %b
%cmp = icmp sgt i64 %shl, -2 %cmp = icmp sgt i64 %shl, -2
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp2 = icmp eq i64 %shl, -2 %cmp2 = icmp eq i64 %shl, -2
%mul = select i1 %cmp2, i64 %b, i64 1 %mul = select i1 %cmp2, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a_op_b__1(i64 %a, i64 %b) { define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_op_b__1: ; CHECK-LABEL: ll_a_op_b__1:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl x8, x0, x1 ; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: cmn x8, #1 // =1 ; CHECK-NEXT: cmn x8, #1
; CHECK-NEXT: csinc x9, x1, xzr, eq ; CHECK-NEXT: csinc x9, x1, xzr, eq
; CHECK-NEXT: mul x9, x9, x0 ; CHECK-NEXT: mul x9, x9, x0
; CHECK-NEXT: cmp x8, #0 // =0 ; CHECK-NEXT: cmp x8, #0
; CHECK-NEXT: csel x0, x1, x9, ge ; CHECK-NEXT: csel x0, x1, x9, ge
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shl = shl i64 %a, %b %shl = shl i64 %a, %b
%cmp = icmp sgt i64 %shl, -1 %cmp = icmp sgt i64 %shl, -1
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp2 = icmp eq i64 %shl, -1 %cmp2 = icmp eq i64 %shl, -1
%mul = select i1 %cmp2, i64 %b, i64 1 %mul = select i1 %cmp2, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a_op_b_0(i64 %a, i64 %b) { define i64 @ll_a_op_b_0(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_op_b_0: ; CHECK-LABEL: ll_a_op_b_0:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl x8, x0, x1 ; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: cmp x8, #0 // =0 ; CHECK-NEXT: cmp x8, #0
; CHECK-NEXT: csinc x8, x1, xzr, eq ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x8, x8, x0 ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: csel x0, x1, x8, gt ; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shl = shl i64 %a, %b %shl = shl i64 %a, %b
%cmp = icmp sgt i64 %shl, 0 %cmp = icmp sgt i64 %shl, 0
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp2 = icmp eq i64 %shl, 0 %cmp2 = icmp eq i64 %shl, 0
%mul = select i1 %cmp2, i64 %b, i64 1 %mul = select i1 %cmp2, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a_op_b_1(i64 %a, i64 %b) { define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_op_b_1: ; CHECK-LABEL: ll_a_op_b_1:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl x8, x0, x1 ; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: cmp x8, #1 // =1 ; CHECK-NEXT: cmp x8, #1
; CHECK-NEXT: csinc x8, x1, xzr, eq ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x8, x8, x0 ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: csel x0, x1, x8, gt ; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shl = shl i64 %a, %b %shl = shl i64 %a, %b
%cmp = icmp sgt i64 %shl, 1 %cmp = icmp sgt i64 %shl, 1
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp2 = icmp eq i64 %shl, 1 %cmp2 = icmp eq i64 %shl, 1
%mul = select i1 %cmp2, i64 %b, i64 1 %mul = select i1 %cmp2, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a_op_b_2(i64 %a, i64 %b) { define i64 @ll_a_op_b_2(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_op_b_2: ; CHECK-LABEL: ll_a_op_b_2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl x8, x0, x1 ; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: cmp x8, #2 // =2 ; CHECK-NEXT: cmp x8, #2
; CHECK-NEXT: csinc x8, x1, xzr, eq ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x8, x8, x0 ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: csel x0, x1, x8, gt ; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shl = shl i64 %a, %b %shl = shl i64 %a, %b
%cmp = icmp sgt i64 %shl, 2 %cmp = icmp sgt i64 %shl, 2
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp2 = icmp eq i64 %shl, 2 %cmp2 = icmp eq i64 %shl, 2
%mul = select i1 %cmp2, i64 %b, i64 1 %mul = select i1 %cmp2, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a__2(i64 %a, i64 %b) { define i64 @ll_a__2(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a__2: ; CHECK-LABEL: ll_a__2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmn x0, #2 // =2 ; CHECK-NEXT: cmn x0, #2
; CHECK-NEXT: csinc x8, x1, xzr, eq ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x8, x8, x0 ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: csel x0, x1, x8, gt ; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i64 %a, -2 %cmp = icmp sgt i64 %a, -2
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp1 = icmp eq i64 %a, -2 %cmp1 = icmp eq i64 %a, -2
%mul = select i1 %cmp1, i64 %b, i64 1 %mul = select i1 %cmp1, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a__1(i64 %a, i64 %b) { define i64 @ll_a__1(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a__1: ; CHECK-LABEL: ll_a__1:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmn x0, #1 // =1 ; CHECK-NEXT: cmn x0, #1
; CHECK-NEXT: csinc x8, x1, xzr, eq ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x8, x8, x0 ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: cmp x0, #0 // =0 ; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: csel x0, x1, x8, ge ; CHECK-NEXT: csel x0, x1, x8, ge
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i64 %a, -1 %cmp = icmp sgt i64 %a, -1
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp1 = icmp eq i64 %a, -1 %cmp1 = icmp eq i64 %a, -1
%mul = select i1 %cmp1, i64 %b, i64 1 %mul = select i1 %cmp1, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a_0(i64 %a, i64 %b) { define i64 @ll_a_0(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_0: ; CHECK-LABEL: ll_a_0:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp x0, #0 // =0 ; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: csinc x8, x1, xzr, eq ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x8, x8, x0 ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: csel x0, x1, x8, gt ; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i64 %a, 0 %cmp = icmp sgt i64 %a, 0
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp1 = icmp eq i64 %a, 0 %cmp1 = icmp eq i64 %a, 0
%mul = select i1 %cmp1, i64 %b, i64 1 %mul = select i1 %cmp1, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a_1(i64 %a, i64 %b) { define i64 @ll_a_1(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_1: ; CHECK-LABEL: ll_a_1:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp x0, #1 // =1 ; CHECK-NEXT: cmp x0, #1
; CHECK-NEXT: csinc x8, x1, xzr, eq ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x8, x8, x0 ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: csel x0, x1, x8, gt ; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i64 %a, 1 %cmp = icmp sgt i64 %a, 1
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp1 = icmp eq i64 %a, 1 %cmp1 = icmp eq i64 %a, 1
%mul = select i1 %cmp1, i64 %b, i64 1 %mul = select i1 %cmp1, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a_2(i64 %a, i64 %b) { define i64 @ll_a_2(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_2: ; CHECK-LABEL: ll_a_2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp x0, #2 // =2 ; CHECK-NEXT: cmp x0, #2
; CHECK-NEXT: csinc x8, x1, xzr, eq ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x8, x8, x0 ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: csel x0, x1, x8, gt ; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i64 %a, 2 %cmp = icmp sgt i64 %a, 2
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp1 = icmp eq i64 %a, 2 %cmp1 = icmp eq i64 %a, 2
%mul = select i1 %cmp1, i64 %b, i64 1 %mul = select i1 %cmp1, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) { define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a_op_b__2: ; CHECK-LABEL: i_a_op_b__2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl w8, w0, w1 ; CHECK-NEXT: lsl w8, w0, w1
; CHECK-NEXT: cmn w8, #2 // =2 ; CHECK-NEXT: cmn w8, #2
; CHECK-NEXT: csinc w8, w1, wzr, eq ; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0 ; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: csel w8, w1, w8, gt ; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8 ; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shl = shl i32 %a, %b %shl = shl i32 %a, %b
%cmp = icmp sgt i32 %shl, -2 %cmp = icmp sgt i32 %shl, -2
Show All 10 Linesreturn: ; preds = %if.end, %entry
%retval.0 = sext i32 %retval.0.in to i64 %retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0 ret i64 %retval.0
} }
define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) { define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a_op_b__1: ; CHECK-LABEL: i_a_op_b__1:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl w8, w0, w1 ; CHECK-NEXT: lsl w8, w0, w1
; CHECK-NEXT: cmn w8, #1 // =1 ; CHECK-NEXT: cmn w8, #1
; CHECK-NEXT: csinc w9, w1, wzr, eq ; CHECK-NEXT: csinc w9, w1, wzr, eq
; CHECK-NEXT: mul w9, w9, w0 ; CHECK-NEXT: mul w9, w9, w0
; CHECK-NEXT: cmp w8, #0 // =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: csel w8, w1, w9, ge ; CHECK-NEXT: csel w8, w1, w9, ge
; CHECK-NEXT: sxtw x0, w8 ; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shl = shl i32 %a, %b %shl = shl i32 %a, %b
%cmp = icmp sgt i32 %shl, -1 %cmp = icmp sgt i32 %shl, -1
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp2 = icmp eq i32 %shl, -1 %cmp2 = icmp eq i32 %shl, -1
%mul = select i1 %cmp2, i32 %b, i32 1 %mul = select i1 %cmp2, i32 %b, i32 1
%spec.select = mul nsw i32 %mul, %a %spec.select = mul nsw i32 %mul, %a
br label %return br label %return
return: ; preds = %if.end, %entry return: ; preds = %if.end, %entry
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ] %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
%retval.0 = sext i32 %retval.0.in to i64 %retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0 ret i64 %retval.0
} }
define i64 @i_a_op_b_0(i32 signext %a, i32 signext %b) { define i64 @i_a_op_b_0(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a_op_b_0: ; CHECK-LABEL: i_a_op_b_0:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl w8, w0, w1 ; CHECK-NEXT: lsl w8, w0, w1
; CHECK-NEXT: cmp w8, #0 // =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: csinc w8, w1, wzr, eq ; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0 ; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: csel w8, w1, w8, gt ; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8 ; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shl = shl i32 %a, %b %shl = shl i32 %a, %b
%cmp = icmp sgt i32 %shl, 0 %cmp = icmp sgt i32 %shl, 0
Show All 10 Linesreturn: ; preds = %if.end, %entry
%retval.0 = sext i32 %retval.0.in to i64 %retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0 ret i64 %retval.0
} }
define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) { define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a_op_b_1: ; CHECK-LABEL: i_a_op_b_1:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl w8, w0, w1 ; CHECK-NEXT: lsl w8, w0, w1
; CHECK-NEXT: cmp w8, #1 // =1 ; CHECK-NEXT: cmp w8, #1
; CHECK-NEXT: csinc w8, w1, wzr, eq ; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0 ; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: csel w8, w1, w8, gt ; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8 ; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shl = shl i32 %a, %b %shl = shl i32 %a, %b
%cmp = icmp sgt i32 %shl, 1 %cmp = icmp sgt i32 %shl, 1
Show All 10 Linesreturn: ; preds = %if.end, %entry
%retval.0 = sext i32 %retval.0.in to i64 %retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0 ret i64 %retval.0
} }
define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) { define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a_op_b_2: ; CHECK-LABEL: i_a_op_b_2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl w8, w0, w1 ; CHECK-NEXT: lsl w8, w0, w1
; CHECK-NEXT: cmp w8, #2 // =2 ; CHECK-NEXT: cmp w8, #2
; CHECK-NEXT: csinc w8, w1, wzr, eq ; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0 ; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: csel w8, w1, w8, gt ; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8 ; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shl = shl i32 %a, %b %shl = shl i32 %a, %b
%cmp = icmp sgt i32 %shl, 2 %cmp = icmp sgt i32 %shl, 2
Show All 9 Linesreturn: ; preds = %if.end, %entry
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ] %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
%retval.0 = sext i32 %retval.0.in to i64 %retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0 ret i64 %retval.0
} }
define i64 @i_a__2(i32 signext %a, i32 signext %b) { define i64 @i_a__2(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a__2: ; CHECK-LABEL: i_a__2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmn w0, #2 // =2 ; CHECK-NEXT: cmn w0, #2
; CHECK-NEXT: csinc w8, w1, wzr, eq ; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0 ; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: csel w8, w1, w8, gt ; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8 ; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i32 %a, -2 %cmp = icmp sgt i32 %a, -2
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp1 = icmp eq i32 %a, -2 %cmp1 = icmp eq i32 %a, -2
%mul = select i1 %cmp1, i32 %b, i32 1 %mul = select i1 %cmp1, i32 %b, i32 1
%spec.select = mul nsw i32 %mul, %a %spec.select = mul nsw i32 %mul, %a
br label %return br label %return
return: ; preds = %if.end, %entry return: ; preds = %if.end, %entry
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ] %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
%retval.0 = sext i32 %retval.0.in to i64 %retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0 ret i64 %retval.0
} }
define i64 @i_a__1(i32 signext %a, i32 signext %b) { define i64 @i_a__1(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a__1: ; CHECK-LABEL: i_a__1:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmn w0, #1 // =1 ; CHECK-NEXT: cmn w0, #1
; CHECK-NEXT: csinc w8, w1, wzr, eq ; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0 ; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, w1, w8, ge ; CHECK-NEXT: csel w8, w1, w8, ge
; CHECK-NEXT: sxtw x0, w8 ; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i32 %a, -1 %cmp = icmp sgt i32 %a, -1
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp1 = icmp eq i32 %a, -1 %cmp1 = icmp eq i32 %a, -1
%mul = select i1 %cmp1, i32 %b, i32 1 %mul = select i1 %cmp1, i32 %b, i32 1
%spec.select = mul nsw i32 %mul, %a %spec.select = mul nsw i32 %mul, %a
br label %return br label %return
return: ; preds = %if.end, %entry return: ; preds = %if.end, %entry
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ] %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
%retval.0 = sext i32 %retval.0.in to i64 %retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0 ret i64 %retval.0
} }
define i64 @i_a_0(i32 signext %a, i32 signext %b) { define i64 @i_a_0(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a_0: ; CHECK-LABEL: i_a_0:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp w0, #0 // =0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csinc w8, w1, wzr, eq ; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0 ; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: csel w8, w1, w8, gt ; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8 ; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i32 %a, 0 %cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp1 = icmp eq i32 %a, 0 %cmp1 = icmp eq i32 %a, 0
%mul = select i1 %cmp1, i32 %b, i32 1 %mul = select i1 %cmp1, i32 %b, i32 1
%spec.select = mul nsw i32 %mul, %a %spec.select = mul nsw i32 %mul, %a
br label %return br label %return
return: ; preds = %if.end, %entry return: ; preds = %if.end, %entry
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ] %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
%retval.0 = sext i32 %retval.0.in to i64 %retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0 ret i64 %retval.0
} }
define i64 @i_a_1(i32 signext %a, i32 signext %b) { define i64 @i_a_1(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a_1: ; CHECK-LABEL: i_a_1:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp w0, #1 // =1 ; CHECK-NEXT: cmp w0, #1
; CHECK-NEXT: csinc w8, w1, wzr, eq ; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0 ; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: csel w8, w1, w8, gt ; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8 ; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i32 %a, 1 %cmp = icmp sgt i32 %a, 1
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp1 = icmp eq i32 %a, 1 %cmp1 = icmp eq i32 %a, 1
%mul = select i1 %cmp1, i32 %b, i32 1 %mul = select i1 %cmp1, i32 %b, i32 1
%spec.select = mul nsw i32 %mul, %a %spec.select = mul nsw i32 %mul, %a
br label %return br label %return
return: ; preds = %if.end, %entry return: ; preds = %if.end, %entry
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ] %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
%retval.0 = sext i32 %retval.0.in to i64 %retval.0 = sext i32 %retval.0.in to i64
ret i64 %retval.0 ret i64 %retval.0
} }
define i64 @i_a_2(i32 signext %a, i32 signext %b) { define i64 @i_a_2(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: i_a_2: ; CHECK-LABEL: i_a_2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp w0, #2 // =2 ; CHECK-NEXT: cmp w0, #2
; CHECK-NEXT: csinc w8, w1, wzr, eq ; CHECK-NEXT: csinc w8, w1, wzr, eq
; CHECK-NEXT: mul w8, w8, w0 ; CHECK-NEXT: mul w8, w8, w0
; CHECK-NEXT: csel w8, w1, w8, gt ; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8 ; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i32 %a, 2 %cmp = icmp sgt i32 %a, 2
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
Show All 12 Lines

llvm/test/CodeGen/AArch64/usub_sat_vec.ll

Show First 20 Lines • Show All 345 Lines • ▼ Show 20 Lines
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x2, x6 ; CHECK-NEXT: subs x8, x2, x6
; CHECK-NEXT: sbcs x9, x3, x7 ; CHECK-NEXT: sbcs x9, x3, x7
; CHECK-NEXT: cmp x8, x2 ; CHECK-NEXT: cmp x8, x2
; CHECK-NEXT: cset w10, hi ; CHECK-NEXT: cset w10, hi
; CHECK-NEXT: cmp x9, x3 ; CHECK-NEXT: cmp x9, x3
; CHECK-NEXT: cset w11, hi ; CHECK-NEXT: cset w11, hi
; CHECK-NEXT: csel w10, w10, w11, eq ; CHECK-NEXT: csel w10, w10, w11, eq
; CHECK-NEXT: cmp w10, #0 // =0 ; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: csel x3, xzr, x9, ne ; CHECK-NEXT: csel x3, xzr, x9, ne
; CHECK-NEXT: csel x2, xzr, x8, ne ; CHECK-NEXT: csel x2, xzr, x8, ne
; CHECK-NEXT: subs x8, x0, x4 ; CHECK-NEXT: subs x8, x0, x4
; CHECK-NEXT: sbcs x9, x1, x5 ; CHECK-NEXT: sbcs x9, x1, x5
; CHECK-NEXT: cmp x8, x0 ; CHECK-NEXT: cmp x8, x0
; CHECK-NEXT: cset w10, hi ; CHECK-NEXT: cset w10, hi
; CHECK-NEXT: cmp x9, x1 ; CHECK-NEXT: cmp x9, x1
; CHECK-NEXT: cset w11, hi ; CHECK-NEXT: cset w11, hi
; CHECK-NEXT: csel w10, w10, w11, eq ; CHECK-NEXT: csel w10, w10, w11, eq
; CHECK-NEXT: cmp w10, #0 // =0 ; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: csel x8, xzr, x8, ne ; CHECK-NEXT: csel x8, xzr, x8, ne
; CHECK-NEXT: csel x1, xzr, x9, ne ; CHECK-NEXT: csel x1, xzr, x9, ne
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <2 x i128> @llvm.usub.sat.v2i128(<2 x i128> %x, <2 x i128> %y) %z = call <2 x i128> @llvm.usub.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
ret <2 x i128> %z ret <2 x i128> %z
} }

llvm/test/CodeGen/AArch64/vec-libcalls.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <1 x float> @llvm.sin.v1f32(<1 x float> %x) %r = call <1 x float> @llvm.sin.v1f32(<1 x float> %x)
ret <1 x float> %r ret <1 x float> %r
} }
define <2 x float> @sin_v2f32(<2 x float> %x) nounwind { define <2 x float> @sin_v2f32(<2 x float> %x) nounwind {
; CHECK-LABEL: sin_v2f32: ; CHECK-LABEL: sin_v2f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: mov s0, v0.s[1] ; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: str d0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str d0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0] ; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: add sp, sp, #48 // =48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <2 x float> @llvm.sin.v2f32(<2 x float> %x) %r = call <2 x float> @llvm.sin.v2f32(<2 x float> %x)
ret <2 x float> %r ret <2 x float> %r
} }
define <3 x float> @sin_v3f32(<3 x float> %x) nounwind { define <3 x float> @sin_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: sin_v3f32: ; CHECK-LABEL: sin_v3f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: mov s0, v0.s[1] ; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0] ; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov s0, v0.s[2] ; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v1.s[2], v0.s[0] ; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48 // =48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <3 x float> @llvm.sin.v3f32(<3 x float> %x) %r = call <3 x float> @llvm.sin.v3f32(<3 x float> %x)
ret <3 x float> %r ret <3 x float> %r
} }
define <4 x float> @sin_v4f32(<4 x float> %x) nounwind { define <4 x float> @sin_v4f32(<4 x float> %x) nounwind {
; CHECK-LABEL: sin_v4f32: ; CHECK-LABEL: sin_v4f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: mov s0, v0.s[1] ; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
Show All 11 Lines
; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
; CHECK-NEXT: mov s0, v0.s[3] ; CHECK-NEXT: mov s0, v0.s[3]
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v1.s[3], v0.s[0] ; CHECK-NEXT: mov v1.s[3], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48 // =48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <4 x float> @llvm.sin.v4f32(<4 x float> %x) %r = call <4 x float> @llvm.sin.v4f32(<4 x float> %x)
ret <4 x float> %r ret <4 x float> %r
} }
define <5 x float> @sin_v5f32(<5 x float> %x) nounwind { define <5 x float> @sin_v5f32(<5 x float> %x) nounwind {
; CHECK-LABEL: sin_v5f32: ; CHECK-LABEL: sin_v5f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <3 x float> @llvm.ceil.v3f32(<3 x float> %x) %r = call <3 x float> @llvm.ceil.v3f32(<3 x float> %x)
ret <3 x float> %r ret <3 x float> %r
} }
define <3 x float> @cos_v3f32(<3 x float> %x) nounwind { define <3 x float> @cos_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: cos_v3f32: ; CHECK-LABEL: cos_v3f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: mov s0, v0.s[1] ; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0] ; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov s0, v0.s[2] ; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v1.s[2], v0.s[0] ; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48 // =48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <3 x float> @llvm.cos.v3f32(<3 x float> %x) %r = call <3 x float> @llvm.cos.v3f32(<3 x float> %x)
ret <3 x float> %r ret <3 x float> %r
} }
define <3 x float> @exp_v3f32(<3 x float> %x) nounwind { define <3 x float> @exp_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: exp_v3f32: ; CHECK-LABEL: exp_v3f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: mov s0, v0.s[1] ; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0] ; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov s0, v0.s[2] ; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v1.s[2], v0.s[0] ; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48 // =48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <3 x float> @llvm.exp.v3f32(<3 x float> %x) %r = call <3 x float> @llvm.exp.v3f32(<3 x float> %x)
ret <3 x float> %r ret <3 x float> %r
} }
define <3 x float> @exp2_v3f32(<3 x float> %x) nounwind { define <3 x float> @exp2_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: exp2_v3f32: ; CHECK-LABEL: exp2_v3f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: mov s0, v0.s[1] ; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0] ; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov s0, v0.s[2] ; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v1.s[2], v0.s[0] ; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48 // =48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <3 x float> @llvm.exp2.v3f32(<3 x float> %x) %r = call <3 x float> @llvm.exp2.v3f32(<3 x float> %x)
ret <3 x float> %r ret <3 x float> %r
} }
define <3 x float> @floor_v3f32(<3 x float> %x) nounwind { define <3 x float> @floor_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: floor_v3f32: ; CHECK-LABEL: floor_v3f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: frintm v0.4s, v0.4s ; CHECK-NEXT: frintm v0.4s, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <3 x float> @llvm.floor.v3f32(<3 x float> %x) %r = call <3 x float> @llvm.floor.v3f32(<3 x float> %x)
ret <3 x float> %r ret <3 x float> %r
} }
define <3 x float> @log_v3f32(<3 x float> %x) nounwind { define <3 x float> @log_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: log_v3f32: ; CHECK-LABEL: log_v3f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: mov s0, v0.s[1] ; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0] ; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov s0, v0.s[2] ; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v1.s[2], v0.s[0] ; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48 // =48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <3 x float> @llvm.log.v3f32(<3 x float> %x) %r = call <3 x float> @llvm.log.v3f32(<3 x float> %x)
ret <3 x float> %r ret <3 x float> %r
} }
define <3 x float> @log10_v3f32(<3 x float> %x) nounwind { define <3 x float> @log10_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: log10_v3f32: ; CHECK-LABEL: log10_v3f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: mov s0, v0.s[1] ; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0] ; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov s0, v0.s[2] ; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v1.s[2], v0.s[0] ; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48 // =48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <3 x float> @llvm.log10.v3f32(<3 x float> %x) %r = call <3 x float> @llvm.log10.v3f32(<3 x float> %x)
ret <3 x float> %r ret <3 x float> %r
} }
define <3 x float> @log2_v3f32(<3 x float> %x) nounwind { define <3 x float> @log2_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: log2_v3f32: ; CHECK-LABEL: log2_v3f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: mov s0, v0.s[1] ; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str d0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0] ; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov s0, v0.s[2] ; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v1.s[2], v0.s[0] ; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48 // =48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call <3 x float> @llvm.log2.v3f32(<3 x float> %x) %r = call <3 x float> @llvm.log2.v3f32(<3 x float> %x)
ret <3 x float> %r ret <3 x float> %r
} }
define <3 x float> @nearbyint__v3f32(<3 x float> %x) nounwind { define <3 x float> @nearbyint__v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: nearbyint__v3f32: ; CHECK-LABEL: nearbyint__v3f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
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llvm/test/CodeGen/AArch64/vec_uaddo.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
store <2 x i32> %val, <2 x i32>* %p2 store <2 x i32> %val, <2 x i32>* %p2
ret <2 x i32> %res ret <2 x i32> %res
} }
define <3 x i32> @uaddo_v3i32(<3 x i32> %a0, <3 x i32> %a1, <3 x i32>* %p2) nounwind { define <3 x i32> @uaddo_v3i32(<3 x i32> %a0, <3 x i32> %a1, <3 x i32>* %p2) nounwind {
; CHECK-LABEL: uaddo_v3i32: ; CHECK-LABEL: uaddo_v3i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v1.4s, v0.4s, v1.4s ; CHECK-NEXT: add v1.4s, v0.4s, v1.4s
; CHECK-NEXT: add x8, x0, #8 // =8 ; CHECK-NEXT: add x8, x0, #8
; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
; CHECK-NEXT: st1 { v1.s }[2], [x8] ; CHECK-NEXT: st1 { v1.s }[2], [x8]
; CHECK-NEXT: str d1, [x0] ; CHECK-NEXT: str d1, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<3 x i32>, <3 x i1>} @llvm.uadd.with.overflow.v3i32(<3 x i32> %a0, <3 x i32> %a1) %t = call {<3 x i32>, <3 x i1>} @llvm.uadd.with.overflow.v3i32(<3 x i32> %a0, <3 x i32> %a1)
%val = extractvalue {<3 x i32>, <3 x i1>} %t, 0 %val = extractvalue {<3 x i32>, <3 x i1>} %t, 0
%obit = extractvalue {<3 x i32>, <3 x i1>} %t, 1 %obit = extractvalue {<3 x i32>, <3 x i1>} %t, 1
%res = sext <3 x i1> %obit to <3 x i32> %res = sext <3 x i1> %obit to <3 x i32>
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define <6 x i32> @uaddo_v6i32(<6 x i32> %a0, <6 x i32> %a1, <6 x i32>* %p2) nounwind { define <6 x i32> @uaddo_v6i32(<6 x i32> %a0, <6 x i32> %a1, <6 x i32>* %p2) nounwind {
; CHECK-LABEL: uaddo_v6i32: ; CHECK-LABEL: uaddo_v6i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fmov s2, w6 ; CHECK-NEXT: fmov s2, w6
; CHECK-NEXT: ldr s0, [sp, #16] ; CHECK-NEXT: ldr s0, [sp, #16]
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: mov v2.s[1], w7 ; CHECK-NEXT: mov v2.s[1], w7
; CHECK-NEXT: ld1 { v2.s }[2], [x9] ; CHECK-NEXT: ld1 { v2.s }[2], [x9]
; CHECK-NEXT: add x8, sp, #24 // =24 ; CHECK-NEXT: add x8, sp, #24
; CHECK-NEXT: add x10, sp, #8 // =8 ; CHECK-NEXT: add x10, sp, #8
; CHECK-NEXT: ld1 { v0.s }[1], [x8] ; CHECK-NEXT: ld1 { v0.s }[1], [x8]
; CHECK-NEXT: fmov s3, w0 ; CHECK-NEXT: fmov s3, w0
; CHECK-NEXT: ldr x11, [sp, #32] ; CHECK-NEXT: ldr x11, [sp, #32]
; CHECK-NEXT: ld1 { v2.s }[3], [x10] ; CHECK-NEXT: ld1 { v2.s }[3], [x10]
; CHECK-NEXT: fmov s1, w4 ; CHECK-NEXT: fmov s1, w4
; CHECK-NEXT: mov v3.s[1], w1 ; CHECK-NEXT: mov v3.s[1], w1
; CHECK-NEXT: mov v1.s[1], w5 ; CHECK-NEXT: mov v1.s[1], w5
; CHECK-NEXT: mov v3.s[2], w2 ; CHECK-NEXT: mov v3.s[2], w2
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llvm/test/CodeGen/AArch64/vec_umulo.ll

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
define <3 x i32> @umulo_v3i32(<3 x i32> %a0, <3 x i32> %a1, <3 x i32>* %p2) nounwind { define <3 x i32> @umulo_v3i32(<3 x i32> %a0, <3 x i32> %a1, <3 x i32>* %p2) nounwind {
; CHECK-LABEL: umulo_v3i32: ; CHECK-LABEL: umulo_v3i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s ; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s
; CHECK-NEXT: umull v3.2d, v0.2s, v1.2s ; CHECK-NEXT: umull v3.2d, v0.2s, v1.2s
; CHECK-NEXT: mul v1.4s, v0.4s, v1.4s ; CHECK-NEXT: mul v1.4s, v0.4s, v1.4s
; CHECK-NEXT: uzp2 v0.4s, v3.4s, v2.4s ; CHECK-NEXT: uzp2 v0.4s, v3.4s, v2.4s
; CHECK-NEXT: add x8, x0, #8 // =8 ; CHECK-NEXT: add x8, x0, #8
; CHECK-NEXT: cmtst v0.4s, v0.4s, v0.4s ; CHECK-NEXT: cmtst v0.4s, v0.4s, v0.4s
; CHECK-NEXT: st1 { v1.s }[2], [x8] ; CHECK-NEXT: st1 { v1.s }[2], [x8]
; CHECK-NEXT: str d1, [x0] ; CHECK-NEXT: str d1, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t = call {<3 x i32>, <3 x i1>} @llvm.umul.with.overflow.v3i32(<3 x i32> %a0, <3 x i32> %a1) %t = call {<3 x i32>, <3 x i1>} @llvm.umul.with.overflow.v3i32(<3 x i32> %a0, <3 x i32> %a1)
%val = extractvalue {<3 x i32>, <3 x i1>} %t, 0 %val = extractvalue {<3 x i32>, <3 x i1>} %t, 0
%obit = extractvalue {<3 x i32>, <3 x i1>} %t, 1 %obit = extractvalue {<3 x i32>, <3 x i1>} %t, 1
%res = sext <3 x i1> %obit to <3 x i32> %res = sext <3 x i1> %obit to <3 x i32>
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define <6 x i32> @umulo_v6i32(<6 x i32> %a0, <6 x i32> %a1, <6 x i32>* %p2) nounwind { define <6 x i32> @umulo_v6i32(<6 x i32> %a0, <6 x i32> %a1, <6 x i32>* %p2) nounwind {
; CHECK-LABEL: umulo_v6i32: ; CHECK-LABEL: umulo_v6i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fmov s2, w6 ; CHECK-NEXT: fmov s2, w6
; CHECK-NEXT: ldr s0, [sp, #16] ; CHECK-NEXT: ldr s0, [sp, #16]
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: mov v2.s[1], w7 ; CHECK-NEXT: mov v2.s[1], w7
; CHECK-NEXT: ld1 { v2.s }[2], [x9] ; CHECK-NEXT: ld1 { v2.s }[2], [x9]
; CHECK-NEXT: add x8, sp, #24 // =24 ; CHECK-NEXT: add x8, sp, #24
; CHECK-NEXT: add x10, sp, #8 // =8 ; CHECK-NEXT: add x10, sp, #8
; CHECK-NEXT: ld1 { v0.s }[1], [x8] ; CHECK-NEXT: ld1 { v0.s }[1], [x8]
; CHECK-NEXT: fmov s3, w0 ; CHECK-NEXT: fmov s3, w0
; CHECK-NEXT: ldr x11, [sp, #32] ; CHECK-NEXT: ldr x11, [sp, #32]
; CHECK-NEXT: ld1 { v2.s }[3], [x10] ; CHECK-NEXT: ld1 { v2.s }[3], [x10]
; CHECK-NEXT: fmov s1, w4 ; CHECK-NEXT: fmov s1, w4
; CHECK-NEXT: mov v3.s[1], w1 ; CHECK-NEXT: mov v3.s[1], w1
; CHECK-NEXT: mov v1.s[1], w5 ; CHECK-NEXT: mov v1.s[1], w5
; CHECK-NEXT: mov v3.s[2], w2 ; CHECK-NEXT: mov v3.s[2], w2
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%res = sext <4 x i1> %obit to <4 x i32> %res = sext <4 x i1> %obit to <4 x i32>
store <4 x i1> %val, <4 x i1>* %p2 store <4 x i1> %val, <4 x i1>* %p2
ret <4 x i32> %res ret <4 x i32> %res
} }
define <2 x i32> @umulo_v2i128(<2 x i128> %a0, <2 x i128> %a1, <2 x i128>* %p2) nounwind { define <2 x i32> @umulo_v2i128(<2 x i128> %a0, <2 x i128> %a1, <2 x i128>* %p2) nounwind {
; CHECK-LABEL: umulo_v2i128: ; CHECK-LABEL: umulo_v2i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp x7, #0 // =0 ; CHECK-NEXT: cmp x7, #0
; CHECK-NEXT: umulh x8, x3, x6 ; CHECK-NEXT: umulh x8, x3, x6
; CHECK-NEXT: cset w13, ne ; CHECK-NEXT: cset w13, ne
; CHECK-NEXT: cmp x3, #0 // =0 ; CHECK-NEXT: cmp x3, #0
; CHECK-NEXT: umulh x9, x7, x2 ; CHECK-NEXT: umulh x9, x7, x2
; CHECK-NEXT: mul x10, x7, x2 ; CHECK-NEXT: mul x10, x7, x2
; CHECK-NEXT: cset w14, ne ; CHECK-NEXT: cset w14, ne
; CHECK-NEXT: cmp xzr, x8 ; CHECK-NEXT: cmp xzr, x8
; CHECK-NEXT: ldr x8, [sp] ; CHECK-NEXT: ldr x8, [sp]
; CHECK-NEXT: umulh x11, x2, x6 ; CHECK-NEXT: umulh x11, x2, x6
; CHECK-NEXT: madd x10, x3, x6, x10 ; CHECK-NEXT: madd x10, x3, x6, x10
; CHECK-NEXT: and w13, w14, w13 ; CHECK-NEXT: and w13, w14, w13
; CHECK-NEXT: cset w14, ne ; CHECK-NEXT: cset w14, ne
; CHECK-NEXT: cmp xzr, x9 ; CHECK-NEXT: cmp xzr, x9
; CHECK-NEXT: orr w13, w13, w14 ; CHECK-NEXT: orr w13, w13, w14
; CHECK-NEXT: cset w14, ne ; CHECK-NEXT: cset w14, ne
; CHECK-NEXT: adds x10, x11, x10 ; CHECK-NEXT: adds x10, x11, x10
; CHECK-NEXT: mul x12, x2, x6 ; CHECK-NEXT: mul x12, x2, x6
; CHECK-NEXT: orr w13, w13, w14 ; CHECK-NEXT: orr w13, w13, w14
; CHECK-NEXT: cset w14, hs ; CHECK-NEXT: cset w14, hs
; CHECK-NEXT: cmp x5, #0 // =0 ; CHECK-NEXT: cmp x5, #0
; CHECK-NEXT: umulh x17, x1, x4 ; CHECK-NEXT: umulh x17, x1, x4
; CHECK-NEXT: stp x12, x10, [x8, #16] ; CHECK-NEXT: stp x12, x10, [x8, #16]
; CHECK-NEXT: cset w10, ne ; CHECK-NEXT: cset w10, ne
; CHECK-NEXT: cmp x1, #0 // =0 ; CHECK-NEXT: cmp x1, #0
; CHECK-NEXT: umulh x9, x5, x0 ; CHECK-NEXT: umulh x9, x5, x0
; CHECK-NEXT: mul x11, x5, x0 ; CHECK-NEXT: mul x11, x5, x0
; CHECK-NEXT: cset w12, ne ; CHECK-NEXT: cset w12, ne
; CHECK-NEXT: cmp xzr, x17 ; CHECK-NEXT: cmp xzr, x17
; CHECK-NEXT: umulh x15, x0, x4 ; CHECK-NEXT: umulh x15, x0, x4
; CHECK-NEXT: madd x11, x1, x4, x11 ; CHECK-NEXT: madd x11, x1, x4, x11
; CHECK-NEXT: and w10, w12, w10 ; CHECK-NEXT: and w10, w12, w10
; CHECK-NEXT: cset w12, ne ; CHECK-NEXT: cset w12, ne
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llvm/test/CodeGen/AArch64/vecreduce-bool.ll

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declare i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %a) declare i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %a)
declare i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %a) declare i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %a)
define i32 @reduce_and_v1(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind { define i32 @reduce_and_v1(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind {
; CHECK-LABEL: reduce_and_v1: ; CHECK-LABEL: reduce_and_v1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: smov w8, v0.b[0] ; CHECK-NEXT: smov w8, v0.b[0]
; CHECK-NEXT: cmp w8, #0 // =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: csel w0, w0, w1, lt ; CHECK-NEXT: csel w0, w0, w1, lt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = icmp slt <1 x i8> %a0, zeroinitializer %x = icmp slt <1 x i8> %a0, zeroinitializer
%y = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %x) %y = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %x)
%z = select i1 %y, i32 %a1, i32 %a2 %z = select i1 %y, i32 %a1, i32 %a2
ret i32 %z ret i32 %z
} }
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ret i32 %z ret i32 %z
} }
define i32 @reduce_or_v1(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind { define i32 @reduce_or_v1(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind {
; CHECK-LABEL: reduce_or_v1: ; CHECK-LABEL: reduce_or_v1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: smov w8, v0.b[0] ; CHECK-NEXT: smov w8, v0.b[0]
; CHECK-NEXT: cmp w8, #0 // =0 ; CHECK-NEXT: cmp w8, #0
; CHECK-NEXT: csel w0, w0, w1, lt ; CHECK-NEXT: csel w0, w0, w1, lt
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = icmp slt <1 x i8> %a0, zeroinitializer %x = icmp slt <1 x i8> %a0, zeroinitializer
%y = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %x) %y = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %x)
%z = select i1 %y, i32 %a1, i32 %a2 %z = select i1 %y, i32 %a1, i32 %a2
ret i32 %z ret i32 %z
} }
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llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll

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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%b = call float @llvm.vector.reduce.fadd.f32.v5f32(float -0.0, <5 x float> %a) %b = call float @llvm.vector.reduce.fadd.f32.v5f32(float -0.0, <5 x float> %a)
ret float %b ret float %b
} }
define fp128 @test_v2f128(<2 x fp128> %a, fp128 %s) nounwind { define fp128 @test_v2f128(<2 x fp128> %a, fp128 %s) nounwind {
; CHECK-LABEL: test_v2f128: ; CHECK-LABEL: test_v2f128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
; CHECK-NEXT: mov v1.16b, v0.16b ; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: bl __addtf3 ; CHECK-NEXT: bl __addtf3
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: b __addtf3 ; CHECK-NEXT: b __addtf3
%b = call fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 %s, <2 x fp128> %a) %b = call fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 %s, <2 x fp128> %a)
ret fp128 %b ret fp128 %b
} }
define fp128 @test_v2f128_neutral(<2 x fp128> %a) nounwind { define fp128 @test_v2f128_neutral(<2 x fp128> %a) nounwind {
; CHECK-LABEL: test_v2f128_neutral: ; CHECK-LABEL: test_v2f128_neutral:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
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llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll

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; CHECK-NOFP-NEXT: fcvt h0, s0 ; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: ret ; CHECK-NOFP-NEXT: ret
; ;
; CHECK-FP-LABEL: test_v11f16: ; CHECK-FP-LABEL: test_v11f16:
; CHECK-FP: // %bb.0: ; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: movi v16.8h, #252, lsl #8 ; CHECK-FP-NEXT: movi v16.8h, #252, lsl #8
; CHECK-FP-NEXT: mov x8, sp ; CHECK-FP-NEXT: mov x8, sp
; CHECK-FP-NEXT: ld1 { v16.h }[0], [x8] ; CHECK-FP-NEXT: ld1 { v16.h }[0], [x8]
; CHECK-FP-NEXT: add x8, sp, #8 // =8 ; CHECK-FP-NEXT: add x8, sp, #8
; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0 ; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1 ; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2 ; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3 ; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4 ; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5 ; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6 ; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7 ; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
; CHECK-FP-NEXT: mov v0.h[1], v1.h[0] ; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
; CHECK-FP-NEXT: ld1 { v16.h }[1], [x8] ; CHECK-FP-NEXT: ld1 { v16.h }[1], [x8]
; CHECK-FP-NEXT: mov v0.h[2], v2.h[0] ; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
; CHECK-FP-NEXT: mov v0.h[3], v3.h[0] ; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
; CHECK-FP-NEXT: add x8, sp, #16 // =16 ; CHECK-FP-NEXT: add x8, sp, #16
; CHECK-FP-NEXT: mov v0.h[4], v4.h[0] ; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
; CHECK-FP-NEXT: ld1 { v16.h }[2], [x8] ; CHECK-FP-NEXT: ld1 { v16.h }[2], [x8]
; CHECK-FP-NEXT: mov v0.h[5], v5.h[0] ; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
; CHECK-FP-NEXT: mov v0.h[6], v6.h[0] ; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
; CHECK-FP-NEXT: mov v0.h[7], v7.h[0] ; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
; CHECK-FP-NEXT: fmaxnm v0.8h, v0.8h, v16.8h ; CHECK-FP-NEXT: fmaxnm v0.8h, v0.8h, v16.8h
; CHECK-FP-NEXT: fmaxnmv h0, v0.8h ; CHECK-FP-NEXT: fmaxnmv h0, v0.8h
; CHECK-FP-NEXT: ret ; CHECK-FP-NEXT: ret
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; CHECK-NOFP-NEXT: fcvt h0, s0 ; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: ret ; CHECK-NOFP-NEXT: ret
; ;
; CHECK-FP-LABEL: test_v11f16_ninf: ; CHECK-FP-LABEL: test_v11f16_ninf:
; CHECK-FP: // %bb.0: ; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: mvni v16.8h, #4, lsl #8 ; CHECK-FP-NEXT: mvni v16.8h, #4, lsl #8
; CHECK-FP-NEXT: mov x8, sp ; CHECK-FP-NEXT: mov x8, sp
; CHECK-FP-NEXT: ld1 { v16.h }[0], [x8] ; CHECK-FP-NEXT: ld1 { v16.h }[0], [x8]
; CHECK-FP-NEXT: add x8, sp, #8 // =8 ; CHECK-FP-NEXT: add x8, sp, #8
; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0 ; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1 ; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2 ; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3 ; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4 ; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5 ; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6 ; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7 ; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
; CHECK-FP-NEXT: mov v0.h[1], v1.h[0] ; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
; CHECK-FP-NEXT: ld1 { v16.h }[1], [x8] ; CHECK-FP-NEXT: ld1 { v16.h }[1], [x8]
; CHECK-FP-NEXT: mov v0.h[2], v2.h[0] ; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
; CHECK-FP-NEXT: mov v0.h[3], v3.h[0] ; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
; CHECK-FP-NEXT: add x8, sp, #16 // =16 ; CHECK-FP-NEXT: add x8, sp, #16
; CHECK-FP-NEXT: mov v0.h[4], v4.h[0] ; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
; CHECK-FP-NEXT: ld1 { v16.h }[2], [x8] ; CHECK-FP-NEXT: ld1 { v16.h }[2], [x8]
; CHECK-FP-NEXT: mov v0.h[5], v5.h[0] ; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
; CHECK-FP-NEXT: mov v0.h[6], v6.h[0] ; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
; CHECK-FP-NEXT: mov v0.h[7], v7.h[0] ; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
; CHECK-FP-NEXT: fmaxnm v0.8h, v0.8h, v16.8h ; CHECK-FP-NEXT: fmaxnm v0.8h, v0.8h, v16.8h
; CHECK-FP-NEXT: fmaxnmv h0, v0.8h ; CHECK-FP-NEXT: fmaxnmv h0, v0.8h
; CHECK-FP-NEXT: ret ; CHECK-FP-NEXT: ret
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llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll

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; CHECK-NOFP-NEXT: fcvt h0, s0 ; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: ret ; CHECK-NOFP-NEXT: ret
; ;
; CHECK-FP-LABEL: test_v11f16: ; CHECK-FP-LABEL: test_v11f16:
; CHECK-FP: // %bb.0: ; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: movi v16.8h, #124, lsl #8 ; CHECK-FP-NEXT: movi v16.8h, #124, lsl #8
; CHECK-FP-NEXT: mov x8, sp ; CHECK-FP-NEXT: mov x8, sp
; CHECK-FP-NEXT: ld1 { v16.h }[0], [x8] ; CHECK-FP-NEXT: ld1 { v16.h }[0], [x8]
; CHECK-FP-NEXT: add x8, sp, #8 // =8 ; CHECK-FP-NEXT: add x8, sp, #8
; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0 ; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1 ; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2 ; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3 ; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4 ; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5 ; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6 ; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7 ; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
; CHECK-FP-NEXT: mov v0.h[1], v1.h[0] ; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
; CHECK-FP-NEXT: ld1 { v16.h }[1], [x8] ; CHECK-FP-NEXT: ld1 { v16.h }[1], [x8]
; CHECK-FP-NEXT: mov v0.h[2], v2.h[0] ; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
; CHECK-FP-NEXT: mov v0.h[3], v3.h[0] ; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
; CHECK-FP-NEXT: add x8, sp, #16 // =16 ; CHECK-FP-NEXT: add x8, sp, #16
; CHECK-FP-NEXT: mov v0.h[4], v4.h[0] ; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
; CHECK-FP-NEXT: ld1 { v16.h }[2], [x8] ; CHECK-FP-NEXT: ld1 { v16.h }[2], [x8]
; CHECK-FP-NEXT: mov v0.h[5], v5.h[0] ; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
; CHECK-FP-NEXT: mov v0.h[6], v6.h[0] ; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
; CHECK-FP-NEXT: mov v0.h[7], v7.h[0] ; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v16.8h ; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v16.8h
; CHECK-FP-NEXT: fminnmv h0, v0.8h ; CHECK-FP-NEXT: fminnmv h0, v0.8h
; CHECK-FP-NEXT: ret ; CHECK-FP-NEXT: ret
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; CHECK-NOFP-NEXT: fcvt h0, s0 ; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: ret ; CHECK-NOFP-NEXT: ret
; ;
; CHECK-FP-LABEL: test_v11f16_ninf: ; CHECK-FP-LABEL: test_v11f16_ninf:
; CHECK-FP: // %bb.0: ; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: mvni v16.8h, #132, lsl #8 ; CHECK-FP-NEXT: mvni v16.8h, #132, lsl #8
; CHECK-FP-NEXT: mov x8, sp ; CHECK-FP-NEXT: mov x8, sp
; CHECK-FP-NEXT: ld1 { v16.h }[0], [x8] ; CHECK-FP-NEXT: ld1 { v16.h }[0], [x8]
; CHECK-FP-NEXT: add x8, sp, #8 // =8 ; CHECK-FP-NEXT: add x8, sp, #8
; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0 ; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1 ; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2 ; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3 ; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4 ; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5 ; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6 ; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7 ; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
; CHECK-FP-NEXT: mov v0.h[1], v1.h[0] ; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
; CHECK-FP-NEXT: ld1 { v16.h }[1], [x8] ; CHECK-FP-NEXT: ld1 { v16.h }[1], [x8]
; CHECK-FP-NEXT: mov v0.h[2], v2.h[0] ; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
; CHECK-FP-NEXT: mov v0.h[3], v3.h[0] ; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
; CHECK-FP-NEXT: add x8, sp, #16 // =16 ; CHECK-FP-NEXT: add x8, sp, #16
; CHECK-FP-NEXT: mov v0.h[4], v4.h[0] ; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
; CHECK-FP-NEXT: ld1 { v16.h }[2], [x8] ; CHECK-FP-NEXT: ld1 { v16.h }[2], [x8]
; CHECK-FP-NEXT: mov v0.h[5], v5.h[0] ; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
; CHECK-FP-NEXT: mov v0.h[6], v6.h[0] ; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
; CHECK-FP-NEXT: mov v0.h[7], v7.h[0] ; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v16.8h ; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v16.8h
; CHECK-FP-NEXT: fminnmv h0, v0.8h ; CHECK-FP-NEXT: fminnmv h0, v0.8h
; CHECK-FP-NEXT: ret ; CHECK-FP-NEXT: ret
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llvm/test/CodeGen/AArch64/vldn_shuffle.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-eabif | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-none-eabif | FileCheck %s
define void @vld2(float* nocapture readonly %pSrc, float* noalias nocapture %pDst, i32 %numSamples) { define void @vld2(float* nocapture readonly %pSrc, float* noalias nocapture %pDst, i32 %numSamples) {
; CHECK-LABEL: vld2: ; CHECK-LABEL: vld2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov x8, xzr ; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: .LBB0_1: // %vector.body ; CHECK-NEXT: .LBB0_1: // %vector.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ld2 { v0.4s, v1.4s }, [x0], #32 ; CHECK-NEXT: ld2 { v0.4s, v1.4s }, [x0], #32
; CHECK-NEXT: fmul v2.4s, v0.4s, v0.4s ; CHECK-NEXT: fmul v2.4s, v0.4s, v0.4s
; CHECK-NEXT: fmla v2.4s, v1.4s, v1.4s ; CHECK-NEXT: fmla v2.4s, v1.4s, v1.4s
; CHECK-NEXT: str q2, [x1, x8] ; CHECK-NEXT: str q2, [x1, x8]
; CHECK-NEXT: add x8, x8, #16 // =16 ; CHECK-NEXT: add x8, x8, #16
; CHECK-NEXT: cmp x8, #1, lsl #12 // =4096 ; CHECK-NEXT: cmp x8, #1, lsl #12 // =4096
; CHECK-NEXT: b.ne .LBB0_1 ; CHECK-NEXT: b.ne .LBB0_1
; CHECK-NEXT: // %bb.2: // %while.end ; CHECK-NEXT: // %bb.2: // %while.end
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
br label %vector.body br label %vector.body
vector.body: ; preds = %vector.body, %entry vector.body: ; preds = %vector.body, %entry
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; CHECK-NEXT: mov x8, xzr ; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: .LBB1_1: // %vector.body ; CHECK-NEXT: .LBB1_1: // %vector.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ld3 { v0.4s, v1.4s, v2.4s }, [x0], #48 ; CHECK-NEXT: ld3 { v0.4s, v1.4s, v2.4s }, [x0], #48
; CHECK-NEXT: fmul v3.4s, v0.4s, v0.4s ; CHECK-NEXT: fmul v3.4s, v0.4s, v0.4s
; CHECK-NEXT: fmla v3.4s, v1.4s, v1.4s ; CHECK-NEXT: fmla v3.4s, v1.4s, v1.4s
; CHECK-NEXT: fmla v3.4s, v2.4s, v2.4s ; CHECK-NEXT: fmla v3.4s, v2.4s, v2.4s
; CHECK-NEXT: str q3, [x1, x8] ; CHECK-NEXT: str q3, [x1, x8]
; CHECK-NEXT: add x8, x8, #16 // =16 ; CHECK-NEXT: add x8, x8, #16
; CHECK-NEXT: cmp x8, #1, lsl #12 // =4096 ; CHECK-NEXT: cmp x8, #1, lsl #12 // =4096
; CHECK-NEXT: b.ne .LBB1_1 ; CHECK-NEXT: b.ne .LBB1_1
; CHECK-NEXT: // %bb.2: // %while.end ; CHECK-NEXT: // %bb.2: // %while.end
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
br label %vector.body br label %vector.body
vector.body: ; preds = %vector.body, %entry vector.body: ; preds = %vector.body, %entry
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define void @vld4(float* nocapture readonly %pSrc, float* noalias nocapture %pDst, i32 %numSamples) { define void @vld4(float* nocapture readonly %pSrc, float* noalias nocapture %pDst, i32 %numSamples) {
; CHECK-LABEL: vld4: ; CHECK-LABEL: vld4:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov x8, xzr ; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: .LBB2_1: // %vector.body ; CHECK-NEXT: .LBB2_1: // %vector.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64 ; CHECK-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
; CHECK-NEXT: add x9, x1, x8 ; CHECK-NEXT: add x9, x1, x8
; CHECK-NEXT: add x8, x8, #32 // =32 ; CHECK-NEXT: add x8, x8, #32
; CHECK-NEXT: cmp x8, #2, lsl #12 // =8192 ; CHECK-NEXT: cmp x8, #2, lsl #12 // =8192
; CHECK-NEXT: fmul v4.4s, v0.4s, v0.4s ; CHECK-NEXT: fmul v4.4s, v0.4s, v0.4s
; CHECK-NEXT: fmla v4.4s, v1.4s, v1.4s ; CHECK-NEXT: fmla v4.4s, v1.4s, v1.4s
; CHECK-NEXT: fmul v5.4s, v2.4s, v2.4s ; CHECK-NEXT: fmul v5.4s, v2.4s, v2.4s
; CHECK-NEXT: fmla v5.4s, v3.4s, v3.4s ; CHECK-NEXT: fmla v5.4s, v3.4s, v3.4s
; CHECK-NEXT: st2 { v4.4s, v5.4s }, [x9] ; CHECK-NEXT: st2 { v4.4s, v5.4s }, [x9]
; CHECK-NEXT: b.ne .LBB2_1 ; CHECK-NEXT: b.ne .LBB2_1
; CHECK-NEXT: // %bb.2: // %while.end ; CHECK-NEXT: // %bb.2: // %while.end
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; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov x8, xzr ; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: .LBB3_1: // %vector.body ; CHECK-NEXT: .LBB3_1: // %vector.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: add x9, x0, x8 ; CHECK-NEXT: add x9, x0, x8
; CHECK-NEXT: add x10, x1, x8 ; CHECK-NEXT: add x10, x1, x8
; CHECK-NEXT: ld2 { v0.4s, v1.4s }, [x9] ; CHECK-NEXT: ld2 { v0.4s, v1.4s }, [x9]
; CHECK-NEXT: ld2 { v2.4s, v3.4s }, [x10] ; CHECK-NEXT: ld2 { v2.4s, v3.4s }, [x10]
; CHECK-NEXT: add x8, x8, #32 // =32 ; CHECK-NEXT: add x8, x8, #32
; CHECK-NEXT: cmp x8, #2, lsl #12 // =8192 ; CHECK-NEXT: cmp x8, #2, lsl #12 // =8192
; CHECK-NEXT: fmul v4.4s, v2.4s, v0.4s ; CHECK-NEXT: fmul v4.4s, v2.4s, v0.4s
; CHECK-NEXT: fmla v4.4s, v1.4s, v3.4s ; CHECK-NEXT: fmla v4.4s, v1.4s, v3.4s
; CHECK-NEXT: str q4, [x2], #16 ; CHECK-NEXT: str q4, [x2], #16
; CHECK-NEXT: b.ne .LBB3_1 ; CHECK-NEXT: b.ne .LBB3_1
; CHECK-NEXT: // %bb.2: // %while.end ; CHECK-NEXT: // %bb.2: // %while.end
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
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llvm/test/CodeGen/AArch64/wineh-try-catch-nobase.ll

; RUN: llc -o - %s -mtriple=aarch64-windows -verify-machineinstrs | FileCheck %s ; RUN: llc -o - %s -mtriple=aarch64-windows -verify-machineinstrs | FileCheck %s
; Make sure we don't have a base pointer. ; Make sure we don't have a base pointer.
; CHECK-LABEL: "?a@@YAXXZ": ; CHECK-LABEL: "?a@@YAXXZ":
; CHECK-NOT: x19 ; CHECK-NOT: x19
; Check that we compute the address relative to fp. ; Check that we compute the address relative to fp.
; CHECK-LABEL: "?catch$2@?0??a@@YAXXZ@4HA": ; CHECK-LABEL: "?catch$2@?0??a@@YAXXZ@4HA":
; CHECK: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: .seh_save_fplr_x 16 ; CHECK-NEXT: .seh_save_fplr_x 16
; CHECK-NEXT: .seh_endprologue ; CHECK-NEXT: .seh_endprologue
; CHECK-NEXT: sub x0, x29, #16 // =16 ; CHECK-NEXT: sub x0, x29, #16
; CHECK-NEXT: mov x1, xzr ; CHECK-NEXT: mov x1, xzr
; CHECK-NEXT: bl "?bb@@YAXPEAHH@Z" ; CHECK-NEXT: bl "?bb@@YAXPEAHH@Z"
; CHECK-NEXT: adrp x0, .LBB0_1 ; CHECK-NEXT: adrp x0, .LBB0_1
; CHECK-NEXT: add x0, x0, .LBB0_1 ; CHECK-NEXT: add x0, x0, .LBB0_1
; CHECK-NEXT: .seh_startepilogue ; CHECK-NEXT: .seh_startepilogue
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .seh_save_fplr_x 16 ; CHECK-NEXT: .seh_save_fplr_x 16
; CHECK-NEXT: .seh_endepilogue ; CHECK-NEXT: .seh_endepilogue
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llvm/test/Transforms/CanonicalizeFreezeInLoops/aarch64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm64-unknown-unknown -O3 < %s | FileCheck %s ; RUN: llc -mtriple=arm64-unknown-unknown -O3 < %s | FileCheck %s
; This test should show that @f and @f_without_freeze generate equivalent ; This test should show that @f and @f_without_freeze generate equivalent
; assembly ; assembly
; REQUIRES: aarch64-registered-target ; REQUIRES: aarch64-registered-target
define void @f(i8* %p, i32 %n, i32 %m) { define void @f(i8* %p, i32 %n, i32 %m) {
; CHECK-LABEL: f: ; CHECK-LABEL: f:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: add w8, w2, #1 // =1 ; CHECK-NEXT: add w8, w2, #1
; CHECK-NEXT: .LBB0_1: // %loop ; CHECK-NEXT: .LBB0_1: // %loop
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: strb wzr, [x0, w8, sxtw] ; CHECK-NEXT: strb wzr, [x0, w8, sxtw]
; CHECK-NEXT: subs w1, w1, #1 // =1 ; CHECK-NEXT: subs w1, w1, #1
; CHECK-NEXT: add w8, w8, #1 // =1 ; CHECK-NEXT: add w8, w8, #1
; CHECK-NEXT: b.ne .LBB0_1 ; CHECK-NEXT: b.ne .LBB0_1
; CHECK-NEXT: // %bb.2: // %exit ; CHECK-NEXT: // %bb.2: // %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
br label %loop br label %loop
loop: loop:
%i = phi i32 [0, %entry], [%i.next, %loop] %i = phi i32 [0, %entry], [%i.next, %loop]
%i.next = add i32 %i, 1 %i.next = add i32 %i, 1
%i.next.fr = freeze i32 %i.next %i.next.fr = freeze i32 %i.next
%j = add i32 %m, %i.next.fr %j = add i32 %m, %i.next.fr
%q = getelementptr i8, i8* %p, i32 %j %q = getelementptr i8, i8* %p, i32 %j
store i8 0, i8* %q store i8 0, i8* %q
%cond = icmp eq i32 %i.next.fr, %n %cond = icmp eq i32 %i.next.fr, %n
br i1 %cond, label %exit, label %loop br i1 %cond, label %exit, label %loop
exit: exit:
ret void ret void
} }
define void @f_without_freeze(i8* %p, i32 %n, i32 %m) { define void @f_without_freeze(i8* %p, i32 %n, i32 %m) {
; CHECK-LABEL: f_without_freeze: ; CHECK-LABEL: f_without_freeze:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: add w8, w2, #1 // =1 ; CHECK-NEXT: add w8, w2, #1
; CHECK-NEXT: .LBB1_1: // %loop ; CHECK-NEXT: .LBB1_1: // %loop
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: strb wzr, [x0, w8, sxtw] ; CHECK-NEXT: strb wzr, [x0, w8, sxtw]
; CHECK-NEXT: subs w1, w1, #1 // =1 ; CHECK-NEXT: subs w1, w1, #1
; CHECK-NEXT: add w8, w8, #1 // =1 ; CHECK-NEXT: add w8, w8, #1
; CHECK-NEXT: b.ne .LBB1_1 ; CHECK-NEXT: b.ne .LBB1_1
; CHECK-NEXT: // %bb.2: // %exit ; CHECK-NEXT: // %bb.2: // %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
br label %loop br label %loop
loop: loop:
%i = phi i32 [0, %entry], [%i.next, %loop] %i = phi i32 [0, %entry], [%i.next, %loop]
%i.next = add i32 %i, 1 %i.next = add i32 %i, 1
%j = add i32 %m, %i.next %j = add i32 %m, %i.next
%q = getelementptr i8, i8* %p, i32 %j %q = getelementptr i8, i8* %p, i32 %j
store i8 0, i8* %q store i8 0, i8* %q
%cond = icmp eq i32 %i.next, %n %cond = icmp eq i32 %i.next, %n
br i1 %cond, label %exit, label %loop br i1 %cond, label %exit, label %loop
exit: exit:
ret void ret void
} }

llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-pre-inc-offset-check.ll

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; when building a bootstrap build on an AArch64 machine, where the ; when building a bootstrap build on an AArch64 machine, where the
; preferred addresing mode is preindexed. ; preferred addresing mode is preindexed.
%"Type" = type <{[166 x [338 x i8]]}> %"Type" = type <{[166 x [338 x i8]]}>
define void @test_lsr_pre_inc_offset_check(%"Type"* %p) { define void @test_lsr_pre_inc_offset_check(%"Type"* %p) {
; CHECK-LABEL: test_lsr_pre_inc_offset_check: ; CHECK-LABEL: test_lsr_pre_inc_offset_check:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: add x8, x0, #340 // =340 ; CHECK-NEXT: add x8, x0, #340
; CHECK-NEXT: mov w9, #165 ; CHECK-NEXT: mov w9, #165
; CHECK-NEXT: mov w10, #2 ; CHECK-NEXT: mov w10, #2
; CHECK-NEXT: .LBB0_1: // %main ; CHECK-NEXT: .LBB0_1: // %main
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: stur wzr, [x8, #-1] ; CHECK-NEXT: stur wzr, [x8, #-1]
; CHECK-NEXT: strb w10, [x8] ; CHECK-NEXT: strb w10, [x8]
; CHECK-NEXT: subs x9, x9, #1 // =1 ; CHECK-NEXT: subs x9, x9, #1
; CHECK-NEXT: add x8, x8, #338 // =338 ; CHECK-NEXT: add x8, x8, #338
; CHECK-NEXT: b.ne .LBB0_1 ; CHECK-NEXT: b.ne .LBB0_1
; CHECK-NEXT: // %bb.2: // %exit ; CHECK-NEXT: // %bb.2: // %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
br label %main br label %main
exit: exit:
ret void ret void
if.then: if.then:
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llvm/test/Transforms/LoopStrengthReduce/AArch64/small-constant.ll

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; } ; }
; return -7; ; return -7;
; } ; }
define float @test1(float* nocapture readonly %arr, i64 %start, float %threshold) { define float @test1(float* nocapture readonly %arr, i64 %start, float %threshold) {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cbz x1, .LBB0_4 ; CHECK-NEXT: cbz x1, .LBB0_4
; CHECK-NEXT: // %bb.1: // %for.body.preheader ; CHECK-NEXT: // %bb.1: // %for.body.preheader
; CHECK-NEXT: add x8, x0, #28 // =28 ; CHECK-NEXT: add x8, x0, #28
; CHECK-NEXT: .LBB0_2: // %for.body ; CHECK-NEXT: .LBB0_2: // %for.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr s1, [x8, x1, lsl #2] ; CHECK-NEXT: ldr s1, [x8, x1, lsl #2]
; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: fcmp s1, s0
; CHECK-NEXT: b.gt .LBB0_5 ; CHECK-NEXT: b.gt .LBB0_5
; CHECK-NEXT: // %bb.3: // %for.cond ; CHECK-NEXT: // %bb.3: // %for.cond
; CHECK-NEXT: // in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: // in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: add x1, x1, #1 // =1 ; CHECK-NEXT: add x1, x1, #1
; CHECK-NEXT: cbnz x1, .LBB0_2 ; CHECK-NEXT: cbnz x1, .LBB0_2
; CHECK-NEXT: .LBB0_4: ; CHECK-NEXT: .LBB0_4:
; CHECK-NEXT: fmov s0, #-7.00000000 ; CHECK-NEXT: fmov s0, #-7.00000000
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_5: // %cleanup2 ; CHECK-NEXT: .LBB0_5: // %cleanup2
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
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; Same as test1, except i has another use: ; Same as test1, except i has another use:
; if (x > threshold) ---> if (x > threshold + i) ; if (x > threshold) ---> if (x > threshold + i)
define float @test2(float* nocapture readonly %arr, i64 %start, float %threshold) { define float @test2(float* nocapture readonly %arr, i64 %start, float %threshold) {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cbz x1, .LBB1_4 ; CHECK-NEXT: cbz x1, .LBB1_4
; CHECK-NEXT: // %bb.1: // %for.body.preheader ; CHECK-NEXT: // %bb.1: // %for.body.preheader
; CHECK-NEXT: add x8, x0, #28 // =28 ; CHECK-NEXT: add x8, x0, #28
; CHECK-NEXT: .LBB1_2: // %for.body ; CHECK-NEXT: .LBB1_2: // %for.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr s1, [x8, x1, lsl #2] ; CHECK-NEXT: ldr s1, [x8, x1, lsl #2]
; CHECK-NEXT: scvtf s2, x1 ; CHECK-NEXT: scvtf s2, x1
; CHECK-NEXT: fadd s2, s2, s0 ; CHECK-NEXT: fadd s2, s2, s0
; CHECK-NEXT: fcmp s1, s2 ; CHECK-NEXT: fcmp s1, s2
; CHECK-NEXT: b.gt .LBB1_5 ; CHECK-NEXT: b.gt .LBB1_5
; CHECK-NEXT: // %bb.3: // %for.cond ; CHECK-NEXT: // %bb.3: // %for.cond
; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1 ; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
; CHECK-NEXT: add x1, x1, #1 // =1 ; CHECK-NEXT: add x1, x1, #1
; CHECK-NEXT: cbnz x1, .LBB1_2 ; CHECK-NEXT: cbnz x1, .LBB1_2
; CHECK-NEXT: .LBB1_4: ; CHECK-NEXT: .LBB1_4:
; CHECK-NEXT: fmov s0, #-7.00000000 ; CHECK-NEXT: fmov s0, #-7.00000000
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_5: // %cleanup4 ; CHECK-NEXT: .LBB1_5: // %cleanup4
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
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llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Linesdefine dso_local i32 @main() #0 {
store i32 3, i32* %4, align 4 store i32 3, i32* %4, align 4
store i32 4, i32* %5, align 4 store i32 4, i32* %5, align 4
ret i32 0 ret i32 0
} }
attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
; CHECK-LABEL: check_boundaries: ; CHECK-LABEL: check_boundaries:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: stp x29, x30, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: add x29, sp, #32 // =32 ; CHECK-NEXT: add x29, sp, #32
; CHECK-NEXT: .cfi_def_cfa w29, 16 ; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: stur xzr, [x29, #-8] ; CHECK-NEXT: stur xzr, [x29, #-8]
; CHECK-NEXT: cbz wzr, .LBB0_3 ; CHECK-NEXT: cbz wzr, .LBB0_3
; CHECK-NEXT: // %bb.1: ; CHECK-NEXT: // %bb.1:
; CHECK-NEXT: str w8, [sp, #16] ; CHECK-NEXT: str w8, [sp, #16]
Show All 11 Lines
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: bl OUTLINED_FUNCTION_0 ; CHECK-NEXT: bl OUTLINED_FUNCTION_0
; CHECK-NEXT: .LBB0_5: ; CHECK-NEXT: .LBB0_5:
; CHECK-NEXT: ldp x29, x30, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: b OUTLINED_FUNCTION_1 ; CHECK-NEXT: b OUTLINED_FUNCTION_1
; ;
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: stp x29, x30, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: add x29, sp, #32 // =32 ; CHECK-NEXT: add x29, sp, #32
; CHECK-NEXT: .cfi_def_cfa w29, 16 ; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: adrp x8, x ; CHECK-NEXT: adrp x8, x
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: mov w10, #2 ; CHECK-NEXT: mov w10, #2
; CHECK-NEXT: mov w11, #3 ; CHECK-NEXT: mov w11, #3
; CHECK-NEXT: mov w12, #4 ; CHECK-NEXT: mov w12, #4
Show All 15 Lines
; CHECK-NEXT: mov w11, #4 ; CHECK-NEXT: mov w11, #4
; CHECK-NEXT: stp w9, w8, [x29, #-12] ; CHECK-NEXT: stp w9, w8, [x29, #-12]
; CHECK-NEXT: stp w11, w10, [sp, #12] ; CHECK-NEXT: stp w11, w10, [sp, #12]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECK-LABEL: OUTLINED_FUNCTION_1: ; CHECK-LABEL: OUTLINED_FUNCTION_1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: add sp, sp, #48 // =48 ; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret ; CHECK-NEXT: ret

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -enable-machine-outliner -mtriple=aarch64-unknown-linux < %s | FileCheck %s ; RUN: llc -enable-machine-outliner -mtriple=aarch64-unknown-linux < %s | FileCheck %s
@x = dso_local global i32 0, align 4 @x = dso_local global i32 0, align 4
define dso_local i32 @check_boundaries() #0 { define dso_local i32 @check_boundaries() #0 {
; CHECK-LABEL: check_boundaries: ; CHECK-LABEL: check_boundaries:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: stp x29, x30, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: add x29, sp, #32 // =32 ; CHECK-NEXT: add x29, sp, #32
; CHECK-NEXT: .cfi_def_cfa w29, 16 ; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: stur xzr, [x29, #-8] ; CHECK-NEXT: stur xzr, [x29, #-8]
; CHECK-NEXT: cbz wzr, .LBB0_3 ; CHECK-NEXT: cbz wzr, .LBB0_3
; CHECK-NEXT: // %bb.1: ; CHECK-NEXT: // %bb.1:
; CHECK-NEXT: str w8, [sp, #16] ; CHECK-NEXT: str w8, [sp, #16]
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines; CHECK-NEXT: b OUTLINED_FUNCTION_1
br label %15 br label %15
ret i32 0 ret i32 0
} }
define dso_local i32 @main() #0 { define dso_local i32 @main() #0 {
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48 // =48 ; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: stp x29, x30, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: add x29, sp, #32 // =32 ; CHECK-NEXT: add x29, sp, #32
; CHECK-NEXT: .cfi_def_cfa w29, 16 ; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: adrp x8, x ; CHECK-NEXT: adrp x8, x
; CHECK-NEXT: mov w9, #1 ; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: mov w10, #2 ; CHECK-NEXT: mov w10, #2
; CHECK-NEXT: mov w11, #3 ; CHECK-NEXT: mov w11, #3
; CHECK-NEXT: mov w12, #4 ; CHECK-NEXT: mov w12, #4
Show All 32 Lines

llvm/test/tools/llvm-objdump/ELF/AArch64/disassemble-align.s

# RUN: llvm-mc -filetype=obj -triple=aarch64 %s -o %t # RUN: llvm-mc -filetype=obj -triple=aarch64 %s -o %t
# RUN: llvm-objdump -d %t | tr '\t' '|' | FileCheck --match-full-lines --strict-whitespace %s # RUN: llvm-objdump -d %t | tr '\t' '|' | FileCheck --match-full-lines --strict-whitespace %s
## Use '|' to show where the tabs line up. ## Use '|' to show where the tabs line up.
# CHECK:0000000000000000 <$x.0>: # CHECK:0000000000000000 <$x.0>:
# CHECK-NEXT: 0: 62 10 00 91 |add|x2, x3, #4 // =4 # CHECK-NEXT: 0: 62 10 00 91 |add|x2, x3, #4{{$}}
MaskRayUnsubmitted
Not Done
ReplyInline Actions

Perhaps append {{$}} to ensure there is no comment.

MaskRay: Perhaps append `{{$}}` to ensure there is no comment.
jhendersonUnsubmitted
Not Done
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+1

jhenderson: +1
# CHECK-NEXT: 4: 1f 20 03 d5 |nop # CHECK-NEXT: 4: 1f 20 03 d5 |nop
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT:0000000000000008 <$d.1>: # CHECK-NEXT:0000000000000008 <$d.1>:
# CHECK-NEXT: 8:|ff ff 00 00|.word|0x0000ffff # CHECK-NEXT: 8:|ff ff 00 00|.word|0x0000ffff
add x2, x3, #4 add x2, x3, #4
nop nop
.word 0xffff .word 0xffff