This is an archive of the discontinued LLVM Phabricator instance.

Differential D107101

[PowerPC] Fix issue where hint was providing the incorrect regsiter class.
ClosedPublic

Authored by stefanp on Jul 29 2021, 1:40 PM.

Details

Reviewers
nemanjai
jsji
qcolombet
rzurob
Group Reviewers
Restricted Project
Commits
rG754520a2bf55: [PowerPC] Fix issue where hint was providing the incorrect regsiter class.
Summary

Regsier hints when copying to a UACC register do not always produce VSRp
registers. This patch makes sure that we do not produce hints in cases
where the subregsiter of the UACC is not a VSRp.

Diff Detail

Event Timeline

stefanp created this revision.Jul 29 2021, 1:40 PM
Herald added subscribers: shchenz, kbarton, hiraditya, MatzeB. · View Herald TranscriptJul 29 2021, 1:40 PM
stefanp requested review of this revision.Jul 29 2021, 1:40 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 29 2021, 1:40 PM
stefanp added a reviewer: Restricted Project.Jul 29 2021, 1:40 PM
stefanp added a reviewer: rzurob.Jul 29 2021, 1:47 PM
Harbormaster completed remote builds in B117036: Diff 362871.Jul 29 2021, 2:13 PM
nemanjai accepted this revision.Jul 29 2021, 3:26 PM

LGTM. Thanks for fixing this.

This revision is now accepted and ready to land.Jul 29 2021, 3:26 PM
Closed by commit rG754520a2bf55: [PowerPC] Fix issue where hint was providing the incorrect regsiter class. (authored by stefanp). · Explain WhyJul 29 2021, 7:10 PM
This revision was automatically updated to reflect the committed changes.
stefanp added a commit: rG754520a2bf55: [PowerPC] Fix issue where hint was providing the incorrect regsiter class..

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
4 lines
test/
CodeGen/
PowerPC/
22 lines

Diff 362871

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

Show First 20 Lines • Show All 500 Lines • ▼ Show 20 Lines for (MachineInstr &Use : MRI->reg_nodbg_instructions(VirtReg)) {
case TargetOpcode::COPY: { case TargetOpcode::COPY: {
ResultOp = &Use.getOperand(0); ResultOp = &Use.getOperand(0);
ResultReg = ResultOp->getReg(); ResultReg = ResultOp->getReg();
if (Register::isVirtualRegister(ResultReg) && if (Register::isVirtualRegister(ResultReg) &&
MRI->getRegClass(ResultReg)->contains(PPC::UACC0) && MRI->getRegClass(ResultReg)->contains(PPC::UACC0) &&
VRM->hasPhys(ResultReg)) { VRM->hasPhys(ResultReg)) {
Register UACCPhys = VRM->getPhys(ResultReg); Register UACCPhys = VRM->getPhys(ResultReg);
Register HintReg = getSubReg(UACCPhys, ResultOp->getSubReg()); Register HintReg = getSubReg(UACCPhys, ResultOp->getSubReg());
// Ensure that the hint is a VSRp register.
if (HintReg >= PPC::VSRp0 && HintReg <= PPC::VSRp31)
Hints.push_back(HintReg); Hints.push_back(HintReg);
} }
break; break;
} }
case PPC::BUILD_UACC: { case PPC::BUILD_UACC: {
ResultOp = &Use.getOperand(0); ResultOp = &Use.getOperand(0);
ResultReg = ResultOp->getReg(); ResultReg = ResultOp->getReg();
if (MRI->getRegClass(ResultReg)->contains(PPC::ACC0) && if (MRI->getRegClass(ResultReg)->contains(PPC::ACC0) &&
VRM->hasPhys(ResultReg)) { VRM->hasPhys(ResultReg)) {
▲ Show 20 Lines • Show All 1,149 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
; RUN: | FileCheck %s
define void @copy_novsrp() local_unnamed_addr {
; CHECK-LABEL: copy_novsrp:
; CHECK: # %bb.0: # %dmblvi_entry
; CHECK-NEXT: xxlxor v2, v2, v2
; CHECK-NEXT: xxlxor vs0, vs0, vs0
; CHECK-NEXT: xxlor vs3, v2, v2
; CHECK-NEXT: stxv vs1, 0(0)
dmblvi_entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> undef, <16 x i8> undef, <16 x i8> zeroinitializer)
%1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)
%2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2
store <16 x i8> %2, <16 x i8>* null, align 1
unreachable
}
declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)