[RISCV][test] Add new tests for mul optimization in the zba extension with SH*ADD

[craig.topper]

LGTM

llvm/test/CodeGen/RISCV/rv32zba.ll

 ; RV32IBA:       # %bb.0:
 ; RV32IBA-NEXT:    addi a1, zero, 73
 ; RV32IBA-NEXT:    mul a0, a0, a1
 ; RV32IBA-NEXT:    ret
   %c = mul i32 %a, 73
   ret i32 %c
 }
 
+define i32 @mul27(i32 %a) {
+; RV32I-LABEL: mul27:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 27
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: mul27:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    addi a1, zero, 27
+; RV32IB-NEXT:    mul a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBA-LABEL: mul27:
+; RV32IBA:       # %bb.0:
+; RV32IBA-NEXT:    addi a1, zero, 27
+; RV32IBA-NEXT:    mul a0, a0, a1
+; RV32IBA-NEXT:    ret
+  %c = mul i32 %a, 27
+  ret i32 %c
+}
+
+define i32 @mul45(i32 %a) {
+; RV32I-LABEL: mul45:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 45
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: mul45:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    addi a1, zero, 45
+; RV32IB-NEXT:    mul a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBA-LABEL: mul45:
+; RV32IBA:       # %bb.0:
+; RV32IBA-NEXT:    addi a1, zero, 45
+; RV32IBA-NEXT:    mul a0, a0, a1
+; RV32IBA-NEXT:    ret
+  %c = mul i32 %a, 45
+  ret i32 %c
+}
+
+define i32 @mul81(i32 %a) {
+; RV32I-LABEL: mul81:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 81
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: mul81:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    addi a1, zero, 81
+; RV32IB-NEXT:    mul a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBA-LABEL: mul81:
+; RV32IBA:       # %bb.0:
+; RV32IBA-NEXT:    addi a1, zero, 81
+; RV32IBA-NEXT:    mul a0, a0, a1
+; RV32IBA-NEXT:    ret
+  %c = mul i32 %a, 81
+  ret i32 %c
+}
+
 define i32 @mul4098(i32 %a) {
 ; RV32I-LABEL: mul4098:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    addi a1, a1, 2
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;

llvm/test/CodeGen/RISCV/rv64zba.ll

 ; RV64IBA:       # %bb.0:
 ; RV64IBA-NEXT:    addi a1, zero, 73
 ; RV64IBA-NEXT:    mul a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %c = mul i64 %a, 73
   ret i64 %c
 }
 
+define i64 @mul27(i64 %a) {
+; RV64I-LABEL: mul27:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 27
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mul27:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 27
+; RV64IB-NEXT:    mul a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mul27:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    addi a1, zero, 27
+; RV64IBA-NEXT:    mul a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i64 %a, 27
+  ret i64 %c
+}
+
+define i64 @mul45(i64 %a) {
+; RV64I-LABEL: mul45:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 45
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mul45:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 45
+; RV64IB-NEXT:    mul a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mul45:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    addi a1, zero, 45
+; RV64IBA-NEXT:    mul a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i64 %a, 45
+  ret i64 %c
+}
+
+define i64 @mul81(i64 %a) {
+; RV64I-LABEL: mul81:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 81
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mul81:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 81
+; RV64IB-NEXT:    mul a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mul81:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    addi a1, zero, 81
+; RV64IBA-NEXT:    mul a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i64 %a, 81
+  ret i64 %c
+}
+
 define i64 @mul4098(i64 %a) {
 ; RV64I-LABEL: mul4098:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1
 ; RV64I-NEXT:    addiw a1, a1, 2
 ; RV64I-NEXT:    mul a0, a0, a1
 ; RV64I-NEXT:    ret
 ;