AArch64/GlobalISel: Cleanup unnecessary size checks in call lowering

[arsenm]

Summary

The CCValAssign types should now be accurate, so these are no longer
necessary.

[tmatheson]

There is more explanation in fa0b93b5a0866aad3ce517daab6cd91cc67823ad, is that commit also the fix that made these redundant? If so LGTM.

llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

171

The only use of ValTy so could be inlined here and below.

[arsenm]

In D106156#2886612, @tmatheson wrote:

There is more explanation in fa0b93b5a0866aad3ce517daab6cd91cc67823ad, is that commit also the fix that made these redundant? If so LGTM.

Yes

[arsenm]

e574fd9d524dd7e14be0f024c9a3e6ae68c983ba

llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

void assignValueToReg(Register ValVReg, Register PhysReg,
     markPhysRegUsed(PhysReg);
     IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
   }
 
   void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
                             MachinePointerInfo &MPO, CCValAssign &VA) override {
     MachineFunction &MF = MIRBuilder.getMF();
 
-    // The reported memory location may be wider than the value.
-    const LLT RealRegTy = MRI.getType(ValVReg);
     LLT ValTy(VA.getValVT());
     LLT LocTy(VA.getLocVT());
 
     // Fixup the types for the DAG compatibility hack.
     if (VA.getValVT() == MVT::i8 || VA.getValVT() == MVT::i16)
       std::swap(ValTy, LocTy);
 
     auto MMO = MF.getMachineMemOperand(
         MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, LocTy,
         inferAlignFromPtrInfo(MF, MPO));
-
-    if (RealRegTy.getSizeInBits() == ValTy.getSizeInBits()) {
-      // No extension information, or no extension necessary. Load into the
-      // incoming parameter type directly.
-      MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
-    } else {
-      auto Tmp = MIRBuilder.buildLoad(LocTy, Addr, *MMO);
-      MIRBuilder.buildTrunc(ValVReg, Tmp);
-    }
   }
 
   /// How the physical register gets marked varies between formal
   /// parameters (it's a basic-block live-in), and a call instruction
   /// (it's an implicit-def of the BL).
   virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
 };
 
if (VA.getLocInfo() != CCValAssign::LocInfo::FPExt) {
       MVT ValVT = VA.getValVT();
 
       if (VA.getValVT() == MVT::i8 || VA.getValVT() == MVT::i16) {
         std::swap(ValVT, LocVT);
         MemTy = LLT(VA.getValVT());
       }
 
       ValVReg = extendRegister(ValVReg, VA, MaxSize);
-      const LLT RegTy = MRI.getType(ValVReg);
-
-      if (RegTy.getSizeInBits() < LocVT.getSizeInBits())
-        ValVReg = MIRBuilder.buildTrunc(RegTy, ValVReg).getReg(0);
     } else {
       // The store does not cover the full allocated stack slot.
       MemTy = LLT(VA.getValVT());
     }
 
     assignValueToAddress(ValVReg, Addr, MemTy, MPO, VA);
   }