[RISCV] Make VLEN no greater than 65536.

[jacquesguan]

Summary

Add constraint of VLEN for RVV v1.0-rc

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

 
 def FPR64C : RegisterClass<"RISCV", [f64], 64, (add
   (sequence "F%u_D", 10, 15),
   (sequence "F%u_D", 8, 9)
 )>;
 
 // Vector type mapping to LLVM types.
 //
-// Though the V extension allows that VLEN be as small as 8,
-// this approach assumes that VLEN>=64.
+// The V vector extension requires that VLEN >= 128 and <= 65536.
 // Additionally, the only supported ELEN values are 32 and 64,
 // thus `vscale` can be defined as VLEN/64,
 // allowing the same types with either ELEN value.
 //
 //         MF8    MF4     MF2     M1      M2      M4       M8
 // i64*    N/A    N/A     N/A     nxv1i64 nxv2i64 nxv4i64  nxv8i64
 // i32     N/A    N/A     nxv1i32 nxv2i32 nxv4i32 nxv8i32  nxv16i32
 // i16     N/A    nxv1i16 nxv2i16 nxv4i16 nxv8i16 nxv16i16 nxv32i16

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

 const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
   return RegBankInfo.get();
 }
 
 unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
   assert(hasStdExtV() && "Tried to get vector length without V support!");
   if (RVVVectorBitsMax == 0)
     return 0;
-  assert(RVVVectorBitsMax >= 128 && isPowerOf2_32(RVVVectorBitsMax) &&
-         "V extension requires vector length to be at least 128 and a power of "
-         "2!");
+  assert(RVVVectorBitsMax >= 128 && RVVVectorBitsMax <= 65536 &&
+         isPowerOf2_32(RVVVectorBitsMax) &&
+         "V extension requires vector length to be in the range of 128 to "
+         "65536 and a power of 2!");
   assert(RVVVectorBitsMax >= RVVVectorBitsMin &&
          "Minimum V extension vector length should not be larger than its "
          "maximum!");
   unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
-  return PowerOf2Floor(Max < 128 ? 0 : Max);
+  return PowerOf2Floor((Max < 128 || Max > 65536) ? 0 : Max);
 }
 
 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
   assert(hasStdExtV() &&
          "Tried to get vector length without V extension support!");
   assert((RVVVectorBitsMin == 0 ||
-          (RVVVectorBitsMin >= 128 && isPowerOf2_32(RVVVectorBitsMin))) &&
-         "V extension requires vector length to be at least 128 and a power of "
-         "2!");
+          (RVVVectorBitsMin >= 128 && RVVVectorBitsMax <= 65536 &&
+           isPowerOf2_32(RVVVectorBitsMin))) &&
+         "V extension requires vector length to be in the range of 128 to "
+         "65536 and a power of 2!");
   assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) &&
          "Minimum V extension vector length should not be larger than its "
          "maximum!");
   unsigned Min = RVVVectorBitsMin;
   if (RVVVectorBitsMax != 0)
     Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax);
-  return PowerOf2Floor(Min < 128 ? 0 : Min);
+  return PowerOf2Floor((Min < 128 || Min > 65536) ? 0 : Min);
 }
 
 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
   assert(hasStdExtV() &&
          "Tried to get maximum LMUL without V extension support!");
   assert(RVVVectorLMULMax <= 8 && isPowerOf2_32(RVVVectorLMULMax) &&
          "V extension requires a LMUL to be at most 8 and a power of 2!");
   return PowerOf2Floor(std::max<unsigned>(RVVVectorLMULMax, 1));
 }
 
 bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
   return hasStdExtV() && getMinRVVVectorSizeInBits() != 0;
 }