[PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

[Conanap]

Summary

Implemented builtins for mtmsr, mfspr, mtspr on PowerPC;
the patch is intended for XL Compatibility.

[Conanap]

Added sema checking

[nemanjai]

Why does this review have no reviewers listed?

clang/lib/CodeGen/CGBuiltin.cpp

15586

Is this the formatting that clang-format produces? Seems surprising it would format it that way.

clang/lib/Sema/SemaChecking.cpp

3374

I don't think we should enforce the range. The architecture may add more SPR's in the future and then this check will need to be updated. Just ensure that the register number (as well as the value for mtspr) are constants.

llvm/include/llvm/IR/IntrinsicsPowerPC.td

1581

Nit: line too long

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

415

Unrelated whitespace change.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

5442

Shouldn't this be imm instead of i32?
Have you tried compiling the test cases with -filetype=obj and/or with -ppc-asm-full-reg-names?

[Conanap]

Changed i32 to timm for patterns, some nits

clang/lib/CodeGen/CGBuiltin.cpp

15586

I ran git clang-format HEAD^ and it didn't change it, so seems like it was happy with this.

[nemanjai]

Could you please add a check for constant arguments to clang/test/CodeGen/builtins-ppc-xlcompat-error.c?

[Conanap]

added an error test

[nemanjai]

LGTM.

[lei]

llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll

3

No need to add this NOTE. Just remove the atuo generate line above.

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_ppc_fctiw, "dd", "")
 BUILTIN(__builtin_ppc_fctiwz, "dd", "")
 BUILTIN(__builtin_ppc_fctudz, "dd", "")
 BUILTIN(__builtin_ppc_fctuwz, "dd", "")
 BUILTIN(__builtin_ppc_dcbtstt, "vv*", "")
 BUILTIN(__builtin_ppc_dcbtt, "vv*", "")
 BUILTIN(__builtin_ppc_mftbu, "Ui","")
 BUILTIN(__builtin_ppc_mfmsr, "Ui", "")
+BUILTIN(__builtin_ppc_mfspr, "ULiiC", "")
+BUILTIN(__builtin_ppc_mtmsr, "vUi", "")
+BUILTIN(__builtin_ppc_mtspr, "viCULi", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 
 // This is just a placeholder, the types and attributes are wrong.
 BUILTIN(__builtin_altivec_vaddcuw, "V4UiV4UiV4Ui", "")
 
 BUILTIN(__builtin_altivec_vaddsbs, "V16ScV16ScV16Sc", "")
 BUILTIN(__builtin_altivec_vaddubs, "V16UcV16UcV16Uc", "")

clang/lib/Basic/Targets/PPC.cpp

static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
   Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
   Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
   Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
   Builder.defineMacro("__dcbtstt", "__builtin_ppc_dcbtstt");
   Builder.defineMacro("__dcbtt", "__builtin_ppc_dcbtt");
   Builder.defineMacro("__mftbu", "__builtin_ppc_mftbu");
   Builder.defineMacro("__mfmsr", "__builtin_ppc_mfmsr");
+  Builder.defineMacro("__mtmsr", "__builtin_ppc_mtmsr");
+  Builder.defineMacro("__mfspr", "__builtin_ppc_mfspr");
+  Builder.defineMacro("__mtspr", "__builtin_ppc_mtspr");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
 /// #defines that are not tied to a specific subtarget.
 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
                                      MacroBuilder &Builder) const {
 
   defineXLCompatMacros(Builder);

clang/lib/CodeGen/CGBuiltin.cpp

#include "clang/Basic/BuiltinsPPC.def"
   case PPC::BI__builtin_ppc_fetch_and_swap:
   case PPC::BI__builtin_ppc_fetch_and_swaplp: {
     return MakeBinaryAtomicValue(*this, AtomicRMWInst::Xchg, E,
                                  llvm::AtomicOrdering::Monotonic);
   }
   case PPC::BI__builtin_ppc_ldarx:
   case PPC::BI__builtin_ppc_lwarx:
     return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
+  case PPC::BI__builtin_ppc_mfspr: {
+    llvm::Type *RetType = CGM.getDataLayout().getTypeSizeInBits(VoidPtrTy) == 32
+                              ? Int32Ty
+                              : Int64Ty;
+    Function *F = CGM.getIntrinsic(Intrinsic::ppc_mfspr, RetType);
+    return Builder.CreateCall(F, Ops);
+  }
+  case PPC::BI__builtin_ppc_mtspr: {
+    llvm::Type *RetType = CGM.getDataLayout().getTypeSizeInBits(VoidPtrTy) == 32
+                              ? Int32Ty
+                              : Int64Ty;
+    Function *F = CGM.getIntrinsic(Intrinsic::ppc_mtspr, RetType);
+    return Builder.CreateCall(F, Ops);
+  }
   }
 }
 
 namespace {
 // If \p E is not null pointer, insert address space cast to match return
 // type of \p E if necessary.
 Value *EmitAMDGPUDispatchPtr(CodeGenFunction &CGF,
                              const CallExpr *E = nullptr) {

clang/lib/Sema/SemaChecking.cpp

bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
   case PPC::BI__builtin_ppc_dcbtt:
     return SemaFeatureCheck(*this, TheCall, "extdiv",
                             diag::err_ppc_builtin_only_on_arch, "7");
   case PPC::BI__builtin_ppc_sthcx:
   case PPC::BI__builtin_ppc_lharx:
   case PPC::BI__builtin_ppc_lbarx:
     return SemaFeatureCheck(*this, TheCall, "extdiv",
                             diag::err_ppc_builtin_only_on_arch, "8");
+  case PPC::BI__builtin_ppc_mtspr:
+  case PPC::BI__builtin_ppc_mfspr:
+    return SemaBuiltinConstantArgRange(TheCall, 0, 1, 898);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
     return SemaBuiltinPPCMMACall(TheCall, Types);
 #include "clang/Basic/BuiltinsPPC.def"
   }
   return SemaBuiltinConstantArgRange(TheCall, i, l, u);
 }
 

clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c

 // RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
 // RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
 // RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
 // RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
 // RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \
-// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-32BIT
 // RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
 // RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
 
+extern unsigned long ula;
+
 unsigned int test_mftbu(void) {
   // CHECK-LABEL: @test_mftbu
   // CHECK: %0 = tail call i32 @llvm.ppc.mftbu()
   return __mftbu();
 }
 
 unsigned long test_mfmsr(void) {
   // CHECK-LABEL: @test_mfmsr
   // CHECK: %0 = tail call i32 @llvm.ppc.mfmsr()
   return __mfmsr();
 }
+
+void test_mtmsr(void) {
+  // CHECK-LABEL: @test_mtmsr
+  // CHECK: tail call void @llvm.ppc.mtmsr(i32 %conv)
+  // CHECK-32BIT-LABEL: @test_mtmsr
+  // CHECK-32BIT: tail call void @llvm.ppc.mtmsr(i32 %0)
+  __mtmsr(ula);
+}
+
+unsigned long test_mfspr(void) {
+  // CHECK-LABEL: @test_mfspr
+  // CHECK: %0 = tail call i64 @llvm.ppc.mfspr.i64(i32 898)
+  return __mfspr(898);
+}
+
+void test_mtspr(void) {
+  // CHECK-LABEL: @test_mtspr
+  // CHECK: tail call void @llvm.ppc.mtspr.i64(i32 1, i64 %0)
+  __mtspr(1, ula);
+}

llvm/include/llvm/IR/IntrinsicsPowerPC.td

let TargetPrefix = "ppc" in {
   def int_ppc_dcbtstt : GCCBuiltin<"__builtin_ppc_dcbtstt">,
                         Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
   def int_ppc_dcbtt : GCCBuiltin<"__builtin_ppc_dcbtt">,
                       Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
   def int_ppc_mftbu : GCCBuiltin<"__builtin_ppc_mftbu">,
                       Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
   def int_ppc_mfmsr : GCCBuiltin<"__builtin_ppc_mfmsr">,
                       Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
+  def int_ppc_mfspr : Intrinsic<[llvm_anyint_ty], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
+  def int_ppc_mtmsr
+      : GCCBuiltin<"__builtin_ppc_mtmsr">, Intrinsic<[], [llvm_i32_ty], []>;
+  def int_ppc_mtspr
+      : Intrinsic<[], [llvm_i32_ty, llvm_anyint_ty], [ImmArg<ArgIndex<0>>]>;
 }

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf),
                           Requires<[In64BitMode]>;
 }
 
 def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR),
                        "mfspr $RT, $SPR", IIC_SprMFSPR>;
 def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT),
                        "mtspr $SPR, $RT", IIC_SprMTSPR>;
 
-
 //===----------------------------------------------------------------------===//
 // 64-bit SPR manipulation instrs.
 
 let Uses = [CTR8] in {
 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
                            "mfctr $rT", IIC_SprMFSPR>,
              PPC970_DGroup_First, PPC970_Unit_FXU;
 }

 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
           (STDCX g8rc:$A, ForceXForm:$dst)>;
 def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, i32:$IMM),
           (TD $IMM, $A, $B)>;
 
 // trapd
 def : Pat<(int_ppc_trapd g8rc:$A),
           (TDI 24, $A, 0)>;
+def : Pat<(i64 (int_ppc_mfspr i32:$SPR)),
+          (MFSPR8 $SPR)>;
+def : Pat<(int_ppc_mtspr i32:$SPR, g8rc:$RT),
+          (MTSPR8 $SPR, $RT)>;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def : Pat<(int_ppc_fctiwz f64:$A),
         (XSCVDPSXWS $A)>;
 def : Pat<(int_ppc_fctudz f64:$A),
         (XSCVDPUXDS $A)>;
 def : Pat<(int_ppc_fctuwz f64:$A),
         (XSCVDPUXWS $A)>;
 
 def : Pat<(int_ppc_mfmsr), (MFMSR)>;
 def : Pat<(int_ppc_mftbu), (MFTB 269)>;
+def : Pat<(i32 (int_ppc_mfspr i32:$SPR)),
+          (MFSPR $SPR)>;
+def : Pat<(int_ppc_mtspr i32:$SPR, gprc:$RT),
+          (MTSPR $SPR, $RT)>;
+def : Pat<(int_ppc_mtmsr gprc:$RS),
+          (MTMSR $RS, 0)>;
 
 let Predicates = [IsISA2_07] in {
   def : Pat<(int_ppc_lharx xoaddr:$dst),
           (LHARX xoaddr:$dst)>;
   def : Pat<(int_ppc_lbarx xoaddr:$dst),
           (LBARX xoaddr:$dst)>;
   def : Pat<(int_ppc_sthcx xoaddr:$dst, gprc:$A),
           (STHCX (EXTSH gprc:$A), xoaddr:$dst)>;
 }
 def : Pat<(int_ppc_dcbtstt xoaddr:$dst),
           (DCBTST 16, xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbtt xoaddr:$dst),
           (DCBT 16, xoaddr:$dst)>;

llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-64bit-only.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare i64 @llvm.ppc.mfspr.i64(i32 immarg)
+declare void @llvm.ppc.mtspr.i64(i32 immarg, i64)
+
+@ula = external local_unnamed_addr global i64, align 8
+
+define dso_local i64 @test_mfxer() {
+; CHECK-LABEL: test_mfxer:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfxer 3
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX64-LABEL: test_mfxer:
+; CHECK-AIX64:       # %bb.0: # %entry
+; CHECK-AIX64-NEXT:    mfxer 3
+; CHECK-AIX64-NEXT:    blr
+entry:
+  %0 = call i64 @llvm.ppc.mfspr.i64(i32 1)
+  ret i64 %0
+}
+
+define dso_local i64 @test_mflr() {
+; CHECK-LABEL: test_mflr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr 3
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX64-LABEL: test_mflr:
+; CHECK-AIX64:       # %bb.0: # %entry
+; CHECK-AIX64-NEXT:    mfspr 3, 8
+; CHECK-AIX64-NEXT:    blr
+entry:
+  %0 = call i64 @llvm.ppc.mfspr.i64(i32 8)
+  ret i64 %0
+}
+
+define dso_local i64 @test_mfctr() {
+; CHECK-LABEL: test_mfctr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfctr 3
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX64-LABEL: test_mfctr:
+; CHECK-AIX64:       # %bb.0: # %entry
+; CHECK-AIX64-NEXT:    mfspr 3, 9
+; CHECK-AIX64-NEXT:    blr
+entry:
+  %0 = call i64 @llvm.ppc.mfspr.i64(i32 9)
+  ret i64 %0
+}
+
+define dso_local i64 @test_mfppr() {
+; CHECK-LABEL: test_mfppr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfspr 3, 896
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX64-LABEL: test_mfppr:
+; CHECK-AIX64:       # %bb.0: # %entry
+; CHECK-AIX64-NEXT:    mfspr 3, 896
+; CHECK-AIX64-NEXT:    blr
+entry:
+  %0 = call i64 @llvm.ppc.mfspr.i64(i32 896)
+  ret i64 %0
+}
+
+define dso_local i64 @test_mfppr32() {
+; CHECK-LABEL: test_mfppr32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfspr 3, 898
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX64-LABEL: test_mfppr32:
+; CHECK-AIX64:       # %bb.0: # %entry
+; CHECK-AIX64-NEXT:    mfspr 3, 898
+; CHECK-AIX64-NEXT:    blr
+entry:
+  %0 = call i64 @llvm.ppc.mfspr.i64(i32 898)
+  ret i64 %0
+}
+
+define dso_local void @test_mtxer() {
+; CHECK-LABEL: test_mtxer:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:    ld 3, 0(3)
+; CHECK-NEXT:    mtxer 3
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX64-LABEL: test_mtxer:
+; CHECK-AIX64:       # %bb.0: # %entry
+; CHECK-AIX64-NEXT:    ld 3, L..C0(2) # @ula
+; CHECK-AIX64-NEXT:    ld 3, 0(3)
+; CHECK-AIX64-NEXT:    mtxer 3
+; CHECK-AIX64-NEXT:    blr
+entry:
+  %0 = load i64, i64* @ula, align 8
+  tail call void @llvm.ppc.mtspr.i64(i32 1, i64 %0)
+  ret void
+}
+
+define dso_local void @test_mtlr() {
+; CHECK-LABEL: test_mtlr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:    ld 3, 0(3)
+; CHECK-NEXT:    mtlr 3
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX64-LABEL: test_mtlr:
+; CHECK-AIX64:       # %bb.0: # %entry
+; CHECK-AIX64-NEXT:    ld 3, L..C0(2) # @ula
+; CHECK-AIX64-NEXT:    ld 3, 0(3)
+; CHECK-AIX64-NEXT:    mtspr 8, 3
+; CHECK-AIX64-NEXT:    blr
+entry:
+  %0 = load i64, i64* @ula, align 8
+  tail call void @llvm.ppc.mtspr.i64(i32 8, i64 %0)
+  ret void
+}
+
+define dso_local void @test_mtctr() {
+; CHECK-LABEL: test_mtctr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:    ld 3, 0(3)
+; CHECK-NEXT:    mtctr 3
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX64-LABEL: test_mtctr:
+; CHECK-AIX64:       # %bb.0: # %entry
+; CHECK-AIX64-NEXT:    ld 3, L..C0(2) # @ula
+; CHECK-AIX64-NEXT:    ld 3, 0(3)
+; CHECK-AIX64-NEXT:    mtspr 9, 3
+; CHECK-AIX64-NEXT:    blr
+entry:
+  %0 = load i64, i64* @ula, align 8
+  tail call void @llvm.ppc.mtspr.i64(i32 9, i64 %0)
+  ret void
+}
+
+define dso_local void @test_mtppr() {
+; CHECK-LABEL: test_mtppr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:    ld 3, 0(3)
+; CHECK-NEXT:    mtspr 896, 3
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX64-LABEL: test_mtppr:
+; CHECK-AIX64:       # %bb.0: # %entry
+; CHECK-AIX64-NEXT:    ld 3, L..C0(2) # @ula
+; CHECK-AIX64-NEXT:    ld 3, 0(3)
+; CHECK-AIX64-NEXT:    mtspr 896, 3
+; CHECK-AIX64-NEXT:    blr
+entry:
+  %0 = load i64, i64* @ula, align 8
+  tail call void @llvm.ppc.mtspr.i64(i32 896, i64 %0)
+  ret void
+}
+
+define dso_local void @test_mtppr32() {
+; CHECK-LABEL: test_mtppr32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:    ld 3, 0(3)
+; CHECK-NEXT:    mtspr 898, 3
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX64-LABEL: test_mtppr32:
+; CHECK-AIX64:       # %bb.0: # %entry
+; CHECK-AIX64-NEXT:    ld 3, L..C0(2) # @ula
+; CHECK-AIX64-NEXT:    ld 3, 0(3)
+; CHECK-AIX64-NEXT:    mtspr 898, 3
+; CHECK-AIX64-NEXT:    blr
+entry:
+  %0 = load i64, i64* @ula, align 8
+  tail call void @llvm.ppc.mtspr.i64(i32 898, i64 %0)
+  ret void
+}

llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mfspr.i32(i32 immarg)
+declare void @llvm.ppc.mtspr.i32(i32 immarg, i32)
+
+@ula = external dso_local global i32, align 4
+
+define dso_local i32 @test_mfxer() {
+; CHECK-LABEL: test_mfxer:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfxer 3
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 1)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mflr() {
+; CHECK-LABEL: test_mflr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfspr 3, 8
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 8)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mfctr() {
+; CHECK-LABEL: test_mfctr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfspr 3, 9
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 9)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mfppr() {
+; CHECK-LABEL: test_mfppr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfspr 3, 896
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 896)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mfppr32() {
+; CHECK-LABEL: test_mfppr32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfspr 3, 898
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 898)
+  ret i32 %0
+}
+
+define dso_local void @test_mtxer() {
+; CHECK-LABEL: test_mtxer:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwz 3, L..C0(2) # @ula
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    mtxer 3
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i32, i32* @ula, align 8
+  tail call void @llvm.ppc.mtspr.i32(i32 1, i32 %0)
+  ret void
+}
+
+define dso_local void @test_mtlr() {
+; CHECK-LABEL: test_mtlr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwz 3, L..C0(2) # @ula
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    mtspr 8, 3
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i32, i32* @ula, align 8
+  tail call void @llvm.ppc.mtspr.i32(i32 8, i32 %0)
+  ret void
+}
+
+define dso_local void @test_mtctr() {
+; CHECK-LABEL: test_mtctr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwz 3, L..C0(2) # @ula
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    mtspr 9, 3
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i32, i32* @ula, align 8
+  tail call void @llvm.ppc.mtspr.i32(i32 9, i32 %0)
+  ret void
+}
+
+define dso_local void @test_mtppr() {
+; CHECK-LABEL: test_mtppr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwz 3, L..C0(2) # @ula
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    mtspr 896, 3
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i32, i32* @ula, align 8
+  tail call void @llvm.ppc.mtspr.i32(i32 896, i32 %0)
+  ret void
+}
+
+define dso_local void @test_mtppr32() {
+; CHECK-LABEL: test_mtppr32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwz 3, L..C0(2) # @ula
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    mtspr 898, 3
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i32, i32* @ula, align 8
+  tail call void @llvm.ppc.mtspr.i32(i32 898, i32 %0)
+  ret void
+}

llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; NOTE: Had to manually modify the last test case (mtmsr) to allow the
+; NOTE: common check of mtmsr instead of 4 different check prefixes
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
-; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
 
 declare i32 @llvm.ppc.mftbu()
 declare i32 @llvm.ppc.mfmsr()
+declare void @llvm.ppc.mtmsr(i32)
+
+@ula = external local_unnamed_addr global i64, align 8
 
 define dso_local zeroext i32 @test_mftbu() {
 ; CHECK-LABEL: test_mftbu:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mftbu 3
 ; CHECK-NEXT:    clrldi 3, 3, 32
 ; CHECK-NEXT:    blr
 ;
-; CHECK-AIX-LABEL: test_mftbu:
-; CHECK-AIX:       # %bb.0: # %entry
-; CHECK-AIX-NEXT:    mftbu 3
-; CHECK-AIX-NEXT:    blr
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT:       # %bb.0: # %entry
+; CHECK-32BIT-NEXT:    mftbu 3
+; CHECK-32BIT-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.mftbu()
   ret i32 %0
 }
 
 define dso_local i64 @test_mfmsr() {
 ; CHECK-LABEL: test_mfmsr:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfmsr 3
 ; CHECK-NEXT:    clrldi 3, 3, 32
 ; CHECK-NEXT:    blr
 ;
-; CHECK-AIX-LABEL: test_mfmsr:
-; CHECK-AIX:       # %bb.0: # %entry
-; CHECK-AIX-NEXT:    mfmsr 4
-; CHECK-AIX-NEXT:    li 3, 0
-; CHECK-AIX-NEXT:    blr
+; CHECK-32BIT-LABEL: test_mfmsr:
+; CHECK-32BIT:       # %bb.0: # %entry
+; CHECK-32BIT-NEXT:    mfmsr 4
+; CHECK-32BIT-NEXT:    li 3, 0
+; CHECK-32BIT-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.mfmsr()
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
+
+define dso_local void @test_mtmsr() {
+; CHECK-LABEL: test_mtmsr:
+; CHECK:    mtmsr 3
+; CHECK-NEXT:    blr
+;
+; CHECK-32BIT-LABEL: test_mtmsr:
+; CHECK-32BIT:       # %bb.0: # %entry
+; CHECK-32BIT-NEXT:    lwz 3, L..C0(2) # @ula
+; CHECK-32BIT-NEXT:    lwz 3, 4(3)
+; CHECK-32BIT-NEXT:    mtmsr 3, 0
+; CHECK-32BIT-NEXT:    blr
+entry:
+  %0 = load i64, i64* @ula, align 8
+  %conv = trunc i64 %0 to i32
+  call void @llvm.ppc.mtmsr(i32 %conv)
+  ret void
+}