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Differential D106079

[AMDGPU] Divergence-driven compare operations instruction selection
ClosedPublic

Authored by alex-t on Jul 15 2021, 9:47 AM.

Details

Reviewers
rampitec
arsenm
Commits
rGed0f4415f002: [AMDGPU] Divergence-driven compare operations instruction selection
Summary

Description: This change enables the compare operations to be selected to SALU/VALU form

dependent of the SDNode divergence flag.

Diff Detail

Unit TestsFailed

TimeTest
2,530 msx64 debian > libarcher.barrier::barrier.c
2,710 msx64 debian > libarcher.critical::critical.c
2,530 msx64 debian > libarcher.critical::lock-nested.c
2,780 msx64 debian > libarcher.critical::lock.c
2,550 msx64 debian > libarcher.parallel::parallel-simple2.c
View Full Test Results (20 Failed)

Event Timeline

alex-t created this revision.Jul 15 2021, 9:47 AM
Herald added subscribers: foad, kerbowa, asbirlea and 10 others. · View Herald TranscriptJul 15 2021, 9:47 AM
alex-t requested review of this revision.Jul 15 2021, 9:47 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 15 2021, 9:47 AM
Herald added a subscriber: wdng. · View Herald Transcript
Harbormaster completed remote builds in B114276: Diff 359021.Jul 15 2021, 11:34 AM
rampitec added inline comments.Jul 15 2021, 12:21 PM
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
594

TRI->getBoolRC()?

598

It is certainly too wide, you need to use clang-format.

llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
5135

This looks like a regression. A common one.

rampitec added a reviewer: arsenm.Jul 15 2021, 12:21 PM
rampitec added a subscriber: Restricted Project.
arsenm added inline comments.Jul 15 2021, 12:26 PM
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
592

When do copies from SCC appear? I thought the InstrEmitter could essentially always avoid these

critson added a subscriber: critson.Jul 16 2021, 1:01 AM

Can you explain the motivation for this change further?
Particularly as it increases generated code size.

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
4475

Do we now have to always use larger e64 instructions or are these later reduced if we can use vcc instead?

foad added inline comments.Jul 16 2021, 6:23 AM
llvm/lib/Target/AMDGPU/SIInstrInfo.td
530

I think you probably need to look ahead to see if this setcc is used by a divergent select. Otherwise you regress: a == b ? c : d where a and b are uniform but c or d are divergent. In this case it is better to use v_cmp than s_cmp, even though the operands are uniform, because it can feed straight into v_cndmask.

alex-t updated this revision to Diff 359563.Jul 17 2021, 7:27 AM

Fixed amdgpu-codegenprepare-idiv.ll test regression + several minor fixes.

alex-t added inline comments.Jul 17 2021, 7:39 AM
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
592

They appear if we have a uniform comparison that provides the operand for the select node. We haven't yet made it to be S_CSELECT if uniform and V_CNDMASK if divergent. That's why InstrEmitter has to adjust operands by adding the SCC copies. It may also happen for any VALU operation that takes SReg_64_XEXECRegClass operand.

594

No. getBoolRC returns the SReg_32RegClass but I really need SReg_32_XM0_XEXEC.

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
4475

SIShrinkInstructions does whatever is possible to reduce back to e32.
As for the change motivation, the main goal is to select SALU instructions for uniform SDNodes and VALU for the divergent ones.
It increases code size a bit but it changes the VALU instruction that operates over the 64 32bit lanes to SALU instruction that operates over 3 scalar registers.

alex-t added inline comments.Jul 17 2021, 7:44 AM
llvm/lib/Target/AMDGPU/SIInstrInfo.td
530

That's right. And is planned for the next change. I am just trying to keep it staged. In general, I am planning to add the dedicated procedure that checks the "VALU only" SDNode users beforehand and selects to VALU even uniform if any.

Harbormaster completed remote builds in B114686: Diff 359563.Jul 17 2021, 8:01 AM
rampitec added inline comments.Jul 19 2021, 10:09 AM
llvm/test/CodeGen/AMDGPU/addrspacecast.ll
14

This also needs a sort of a look ahead.

alex-t updated this revision to Diff 359844.Jul 19 2021, 10:52 AM

Formatting fixed

alex-t added inline comments.Jul 19 2021, 11:02 AM
llvm/test/CodeGen/AMDGPU/addrspacecast.ll
14

All such a kind of regressions need to be addressed in the separate patch I believe. Please note here 2 facts:

  1. v_cndmask that consumes VCC is uniform and should be selected to S_CSELECT itself but this part of the work is not done yet.
  2. To fix all of these patterns I need to add a lookahead in the selection predicate - scan over all CC users and select only if no VALU instructions were found. I was planning this as a separate change.
rampitec added inline comments.Jul 19 2021, 11:09 AM
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
5759

Unused variable initialization. You do not need to declare CondReg here at all.

Harbormaster completed remote builds in B114898: Diff 359844.Jul 19 2021, 11:26 AM
nhaehnle added inline comments.Jul 20 2021, 8:00 AM
llvm/lib/Target/AMDGPU/SIInstrInfo.td
530

Is it so clear-cut?

For a == b ? c : d with a and b uniform but c or d divergent, there's a choice between v_cmp + v_cndmask vs. s_cmp + s_cselect + v_cndmask.

So this change increases code size and trades 1 VALU for 2 SALU, but SALU utilization tends to be low, so purely based on instruction counts the s_cmp-based sequence is still better most of the time. On gfx10 there's a scheduling pitfall to watch out for though.

alex-t added inline comments.Jul 22 2021, 8:27 AM
llvm/lib/Target/AMDGPU/SIInstrInfo.td
530

For this concrete example, S_CMP is still better. In my comment above I meant that I am planning to add a selection predicate as the right place to decide if the given node should be selected to VALU or SALU.
Further, we can try different strategies - one described above or another one, more complex.

alex-t added a comment.Aug 19 2021, 1:10 PM

Following the discussion regarding uniform "setcc" with a divergent use:
In the current implementation of the divergence-driven ISel node is selected only depending on the divergence bit value regardless of VALU or SALU uses.
The latter is not necessarily related to the user divergence. The user may be uniform but selected to VALU just because corresponding SALU instruction does not exist.
As mentioned above, the alternative approach is to select the given node to VALU if it has VALU users. At first, this requires some reasonable heuristic.
Let's say we have a uniform SDNode that has 1 VALU but 10 SALU users. Is it profitable to select it to VALU?
The selection hook that looks ahead for the users needs to be controlled by the option to try different heuristics.
Also, the problem in question is common for all the opcodes - not the "setcc" only. Thus, adding such a hook would require changing all the places in the target where the divergence bit is currently checked. That is why I insist this should go to a separate patch.

For the current one, I checked the possible regression related to the "select" pattern by running the OpenCL conformance math_bruteforce with the clean and changed compiler. The timing shows that the new one is on par with the old one.

alex-t updated this revision to Diff 367605.Aug 19 2021, 1:45 PM

Unused variable initialization removed.

alex-t marked an inline comment as done.Aug 19 2021, 1:46 PM
Harbormaster completed remote builds in B120416: Diff 367605.Aug 19 2021, 2:25 PM
rampitec accepted this revision.Aug 20 2021, 11:26 AM

LGTM. Please wait other reviewers before landing.

This revision is now accepted and ready to land.Aug 20 2021, 11:26 AM
This revision was landed with ongoing or failed builds.Aug 25 2021, 8:30 AM
Closed by commit rGed0f4415f002: [AMDGPU] Divergence-driven compare operations instruction selection (authored by alex-t). · Explain Why
This revision was automatically updated to reflect the committed changes.
alex-t added a commit: rGed0f4415f002: [AMDGPU] Divergence-driven compare operations instruction selection.
critson mentioned this in D108925: [AMDGPU] enable scalar compare in truncate selection.Aug 31 2021, 12:43 AM

Revision Contents

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Diff 359021

llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp

//===- SIFixSGPRCopies.cpp - Remove potential VGPR => SGPR copies ---------===// //===- SIFixSGPRCopies.cpp - Remove potential VGPR => SGPR copies ---------===//
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clang-format not found in user’s local PATH; not linting file.

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// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 571 Lines • ▼ Show 20 Lines for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
default: default:
continue; continue;
case AMDGPU::COPY: case AMDGPU::COPY:
case AMDGPU::WQM: case AMDGPU::WQM:
case AMDGPU::STRICT_WQM: case AMDGPU::STRICT_WQM:
case AMDGPU::SOFT_WQM: case AMDGPU::SOFT_WQM:
case AMDGPU::STRICT_WWM: { case AMDGPU::STRICT_WWM: {
Register DstReg = MI.getOperand(0).getReg(); Register DstReg = MI.getOperand(0).getReg();
const TargetRegisterClass *SrcRC, *DstRC; const TargetRegisterClass *SrcRC, *DstRC;
std::tie(SrcRC, DstRC) = getCopyRegClasses(MI, *TRI, *MRI); std::tie(SrcRC, DstRC) = getCopyRegClasses(MI, *TRI, *MRI);
if (MI.isCopy()) {
Register SrcReg = MI.getOperand(1).getReg();
arsenmUnsubmitted
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When do copies from SCC appear? I thought the InstrEmitter could essentially always avoid these

arsenm: When do copies from SCC appear? I thought the InstrEmitter could essentially always avoid these
alex-tAuthorUnsubmitted
Done
ReplyInline Actions

They appear if we have a uniform comparison that provides the operand for the select node. We haven't yet made it to be S_CSELECT if uniform and V_CNDMASK if divergent. That's why InstrEmitter has to adjust operands by adding the SCC copies. It may also happen for any VALU operation that takes SReg_64_XEXECRegClass operand.

alex-t: They appear if we have a uniform comparison that provides the operand for the select node. We…
if (SrcReg == AMDGPU::SCC) {
Register SCCCopy = MRI->createVirtualRegister(ST.isWave32() ?
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-            Register SCCCopy = MRI->createVirtualRegister(ST.isWave32() ?
-               &AMDGPU::SReg_32RegClass : &AMDGPU::SReg_64_XEXECRegClass);
+            Register SCCCopy = MRI->createVirtualRegister(
+                ST.isWave32() ? &AMDGPU::SReg_32RegClass
+                              : &AMDGPU::SReg_64_XEXECRegClass);
Lint: Pre-merge checks: clang-format: please reformat the code ``` - Register SCCCopy = MRI…
rampitecUnsubmitted
Not Done
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TRI->getBoolRC()?

rampitec: TRI->getBoolRC()?
alex-tAuthorUnsubmitted
Done
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No. getBoolRC returns the SReg_32RegClass but I really need SReg_32_XM0_XEXEC.

alex-t: No. getBoolRC returns the SReg_32RegClass but I really need SReg_32_XM0_XEXEC.
&AMDGPU::SReg_32RegClass : &AMDGPU::SReg_64_XEXECRegClass);
I = BuildMI(*MI.getParent(),
std::next(MachineBasicBlock::iterator(MI)),
MI.getDebugLoc(), TII->get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 : AMDGPU::S_CSELECT_B64), SCCCopy)
Lint: Pre-merge checks
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clang-format: please reformat the code

-                        MI.getDebugLoc(), TII->get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 : AMDGPU::S_CSELECT_B64), SCCCopy)
+                        MI.getDebugLoc(),
+                        TII->get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
+                                               : AMDGPU::S_CSELECT_B64),
+                        SCCCopy)
Lint: Pre-merge checks: clang-format: please reformat the code ``` - MI.getDebugLoc(), TII->get…
rampitecUnsubmitted
Not Done
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It is certainly too wide, you need to use clang-format.

rampitec: It is certainly too wide, you need to use clang-format.
.addImm(-1)
.addImm(0);
BuildMI(*MI.getParent(), std::next(I), I->getDebugLoc(), TII->get(AMDGPU::COPY), DstReg)
Lint: Pre-merge checks
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clang-format: please reformat the code

-            BuildMI(*MI.getParent(), std::next(I), I->getDebugLoc(), TII->get(AMDGPU::COPY), DstReg)
-                    .addReg(SCCCopy);
+            BuildMI(*MI.getParent(), std::next(I), I->getDebugLoc(),
+                    TII->get(AMDGPU::COPY), DstReg)
+                .addReg(SCCCopy);
Lint: Pre-merge checks: clang-format: please reformat the code ``` - BuildMI(*MI.getParent(), std::next(I)…
.addReg(SCCCopy);
MI.eraseFromParent();
continue;
}
}
if (!DstReg.isVirtual()) { if (!DstReg.isVirtual()) {
// If the destination register is a physical register there isn't // If the destination register is a physical register there isn't
// really much we can do to fix this. // really much we can do to fix this.
// Some special instructions use M0 as an input. Some even only use // Some special instructions use M0 as an input. Some even only use
// the first lane. Insert a readfirstlane and hope for the best. // the first lane. Insert a readfirstlane and hope for the best.
if (DstReg == AMDGPU::M0 && TRI->hasVectorRegisters(SrcRC)) { if (DstReg == AMDGPU::M0 && TRI->hasVectorRegisters(SrcRC)) {
Register TmpReg Register TmpReg
= MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); = MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
▲ Show 20 Lines • Show All 286 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/SIInstrInfo.h

//===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===// //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
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clang-format not found in user’s local PATH; not linting file.

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// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Lines void movePackToVALU(SetVectorType &Worklist,
MachineRegisterInfo &MRI, MachineRegisterInfo &MRI,
MachineInstr &Inst) const; MachineInstr &Inst) const;
void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI, void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
SetVectorType &Worklist) const; SetVectorType &Worklist) const;
void addSCCDefUsersToVALUWorklist(MachineOperand &Op, void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
MachineInstr &SCCDefInst, MachineInstr &SCCDefInst,
SetVectorType &Worklist) const; SetVectorType &Worklist,
Register NewCond = Register()) const;
void addSCCDefsToVALUWorklist(MachineOperand &Op, void addSCCDefsToVALUWorklist(MachineOperand &Op,
SetVectorType &Worklist) const; SetVectorType &Worklist) const;
const TargetRegisterClass * const TargetRegisterClass *
getDestEquivalentVGPRClass(const MachineInstr &Inst) const; getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa, bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
const MachineInstr &MIb) const; const MachineInstr &MIb) const;
▲ Show 20 Lines • Show All 1,132 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
//===- SIInstrInfo.cpp - SI Instruction Information ----------------------===// //===- SIInstrInfo.cpp - SI Instruction Information ----------------------===//
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clang-format not found in user’s local PATH; not linting file.

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// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 4,445 Lines • ▼ Show 20 Linesunsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32_e64; case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32_e64;
case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32_e64; case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32_e64;
case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32_e64; case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32_e64;
case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32_e64; case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32_e64;
case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64; case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32; case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32; case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32; case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32; case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e64;
Lint: Pre-merge checks
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clang-format: please reformat the code

-  case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e64;
-  case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e64;
-  case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e64;
-  case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e64;
-  case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e64;
-  case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e64;
-  case AMDGPU::S_CMP_EQ_U32: return AMDGPU::V_CMP_EQ_U32_e64;
-  case AMDGPU::S_CMP_LG_U32: return AMDGPU::V_CMP_NE_U32_e64;
-  case AMDGPU::S_CMP_GT_U32: return AMDGPU::V_CMP_GT_U32_e64;
-  case AMDGPU::S_CMP_GE_U32: return AMDGPU::V_CMP_GE_U32_e64;

32 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - case AMDGPU::S_CMP_EQ_I32: return AMDGPU…
case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32; case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e64;
case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32; case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e64;
case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32; case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e64;
case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32; case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e64;
case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32; case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e64;
case AMDGPU::S_CMP_EQ_U32: return AMDGPU::V_CMP_EQ_U32_e32; case AMDGPU::S_CMP_EQ_U32: return AMDGPU::V_CMP_EQ_U32_e64;
case AMDGPU::S_CMP_LG_U32: return AMDGPU::V_CMP_NE_U32_e32; case AMDGPU::S_CMP_LG_U32: return AMDGPU::V_CMP_NE_U32_e64;
case AMDGPU::S_CMP_GT_U32: return AMDGPU::V_CMP_GT_U32_e32; case AMDGPU::S_CMP_GT_U32: return AMDGPU::V_CMP_GT_U32_e64;
case AMDGPU::S_CMP_GE_U32: return AMDGPU::V_CMP_GE_U32_e32; case AMDGPU::S_CMP_GE_U32: return AMDGPU::V_CMP_GE_U32_e64;
case AMDGPU::S_CMP_LT_U32: return AMDGPU::V_CMP_LT_U32_e32; case AMDGPU::S_CMP_LT_U32: return AMDGPU::V_CMP_LT_U32_e64;
case AMDGPU::S_CMP_LE_U32: return AMDGPU::V_CMP_LE_U32_e32; case AMDGPU::S_CMP_LE_U32: return AMDGPU::V_CMP_LE_U32_e64;
case AMDGPU::S_CMP_EQ_U64: return AMDGPU::V_CMP_EQ_U64_e32; case AMDGPU::S_CMP_EQ_U64: return AMDGPU::V_CMP_EQ_U64_e64;
case AMDGPU::S_CMP_LG_U64: return AMDGPU::V_CMP_NE_U64_e32; case AMDGPU::S_CMP_LG_U64: return AMDGPU::V_CMP_NE_U64_e64;
critsonUnsubmitted
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Do we now have to always use larger e64 instructions or are these later reduced if we can use vcc instead?

critson: Do we now have to always use larger e64 instructions or are these later reduced if we can use…
alex-tAuthorUnsubmitted
Done
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SIShrinkInstructions does whatever is possible to reduce back to e32.
As for the change motivation, the main goal is to select SALU instructions for uniform SDNodes and VALU for the divergent ones.
It increases code size a bit but it changes the VALU instruction that operates over the 64 32bit lanes to SALU instruction that operates over 3 scalar registers.

alex-t: SIShrinkInstructions does whatever is possible to reduce back to e32. As for the change…
case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64; case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32; case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32; case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64; case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
case AMDGPU::S_CBRANCH_SCC0: return AMDGPU::S_CBRANCH_VCCZ; case AMDGPU::S_CBRANCH_SCC0: return AMDGPU::S_CBRANCH_VCCZ;
case AMDGPU::S_CBRANCH_SCC1: return AMDGPU::S_CBRANCH_VCCNZ; case AMDGPU::S_CBRANCH_SCC1: return AMDGPU::S_CBRANCH_VCCNZ;
} }
llvm_unreachable( llvm_unreachable(
▲ Show 20 Lines • Show All 461 Lines • ▼ Show 20 Lines if (!MO.isReg()) {
} }
--LiteralLimit; --LiteralLimit;
--ConstantBusLimit; --ConstantBusLimit;
legalizeOpWithMove(MI, Idx); legalizeOpWithMove(MI, Idx);
continue; continue;
} }
if (RI.hasAGPRs(MRI.getRegClass(MO.getReg())) && if (RI.hasAGPRs(RI.getRegClassForReg(MRI, MO.getReg())) &&
!isOperandLegal(MI, Idx, &MO)) { !isOperandLegal(MI, Idx, &MO)) {
legalizeOpWithMove(MI, Idx); legalizeOpWithMove(MI, Idx);
continue; continue;
} }
if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg()))) if (!RI.isSGPRClass(RI.getRegClassForReg(MRI, MO.getReg())))
continue; // VGPRs are legal continue; // VGPRs are legal
// We can use one SGPR in each VOP3 instruction prior to GFX10 // We can use one SGPR in each VOP3 instruction prior to GFX10
// and two starting from GFX10. // and two starting from GFX10.
if (SGPRsUsed.count(MO.getReg())) if (SGPRsUsed.count(MO.getReg()))
continue; continue;
if (ConstantBusLimit > 0) { if (ConstantBusLimit > 0) {
SGPRsUsed.insert(MO.getReg()); SGPRsUsed.insert(MO.getReg());
▲ Show 20 Lines • Show All 783 Lines • ▼ Show 20 LinesMachineBasicBlock *SIInstrInfo::moveToVALU(MachineInstr &TopInst,
while (!Worklist.empty()) { while (!Worklist.empty()) {
MachineInstr &Inst = *Worklist.pop_back_val(); MachineInstr &Inst = *Worklist.pop_back_val();
MachineBasicBlock *MBB = Inst.getParent(); MachineBasicBlock *MBB = Inst.getParent();
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
unsigned Opcode = Inst.getOpcode(); unsigned Opcode = Inst.getOpcode();
unsigned NewOpcode = getVALUOp(Inst); unsigned NewOpcode = getVALUOp(Inst);
Register CondReg = RI.getVCC();
rampitecUnsubmitted
Done
ReplyInline Actions

Unused variable initialization. You do not need to declare CondReg here at all.

rampitec: Unused variable initialization. You do not need to declare CondReg here at all.
// Handle some special cases // Handle some special cases
switch (Opcode) { switch (Opcode) {
default: default:
break; break;
case AMDGPU::S_ADD_U64_PSEUDO: case AMDGPU::S_ADD_U64_PSEUDO:
case AMDGPU::S_SUB_U64_PSEUDO: case AMDGPU::S_SUB_U64_PSEUDO:
splitScalar64BitAddSub(Worklist, Inst, MDT); splitScalar64BitAddSub(Worklist, Inst, MDT);
Inst.eraseFromParent(); Inst.eraseFromParent();
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines case AMDGPU::S_LSHR_B64:
break; break;
case AMDGPU::S_ABS_I32: case AMDGPU::S_ABS_I32:
lowerScalarAbs(Worklist, Inst); lowerScalarAbs(Worklist, Inst);
Inst.eraseFromParent(); Inst.eraseFromParent();
continue; continue;
case AMDGPU::S_CBRANCH_SCC0: case AMDGPU::S_CBRANCH_SCC0:
case AMDGPU::S_CBRANCH_SCC1: case AMDGPU::S_CBRANCH_SCC1: {
// Clear unused bits of vcc // Clear unused bits of vcc
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-        // Clear unused bits of vcc
-        Register CondReg = Inst.getOperand(1).getReg();
-        bool IsSCC = CondReg == AMDGPU::SCC;
-        Register VCC = RI.getVCC();
-        Register EXEC = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
-        unsigned Opc = ST.isWave32() ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
-        BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(Opc), VCC)
-            .addReg(EXEC)
-            .addReg(IsSCC ? VCC : CondReg);
-        Inst.RemoveOperand(1);

13 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - // Clear unused bits of vcc…
if (ST.isWave32()) Register CondReg = Inst.getOperand(1).getReg();
BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(AMDGPU::S_AND_B32), bool IsSCC = CondReg == AMDGPU::SCC;
AMDGPU::VCC_LO) Register VCC = RI.getVCC();
.addReg(AMDGPU::EXEC_LO) Register EXEC = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
.addReg(AMDGPU::VCC_LO); unsigned Opc = ST.isWave32() ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
else BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(Opc), VCC)
BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(AMDGPU::S_AND_B64), .addReg(EXEC)
AMDGPU::VCC) .addReg(IsSCC ? VCC : CondReg);
.addReg(AMDGPU::EXEC) Inst.RemoveOperand(1);
.addReg(AMDGPU::VCC); }
break; break;
case AMDGPU::S_BFE_U64: case AMDGPU::S_BFE_U64:
case AMDGPU::S_BFM_B64: case AMDGPU::S_BFM_B64:
llvm_unreachable("Moving this op to VALU not implemented"); llvm_unreachable("Moving this op to VALU not implemented");
case AMDGPU::S_PACK_LL_B32_B16: case AMDGPU::S_PACK_LL_B32_B16:
case AMDGPU::S_PACK_LH_B32_B16: case AMDGPU::S_PACK_LH_B32_B16:
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines while (!Worklist.empty()) {
} }
continue; continue;
case AMDGPU::S_CSELECT_B32: case AMDGPU::S_CSELECT_B32:
case AMDGPU::S_CSELECT_B64: case AMDGPU::S_CSELECT_B64:
lowerSelect(Worklist, Inst, MDT); lowerSelect(Worklist, Inst, MDT);
Inst.eraseFromParent(); Inst.eraseFromParent();
continue; continue;
case AMDGPU::S_CMP_EQ_I32:
case AMDGPU::S_CMP_LG_I32:
case AMDGPU::S_CMP_GT_I32:
case AMDGPU::S_CMP_GE_I32:
case AMDGPU::S_CMP_LT_I32:
case AMDGPU::S_CMP_LE_I32:
case AMDGPU::S_CMP_EQ_U32:
case AMDGPU::S_CMP_LG_U32:
case AMDGPU::S_CMP_GT_U32:
case AMDGPU::S_CMP_GE_U32:
case AMDGPU::S_CMP_LT_U32:
case AMDGPU::S_CMP_LE_U32:
case AMDGPU::S_CMP_EQ_U64:
case AMDGPU::S_CMP_LG_U64: {
const MCInstrDesc &NewDesc = get(NewOpcode);
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-        const MCInstrDesc &NewDesc = get(NewOpcode);
-        CondReg = MRI.createVirtualRegister(RI.getWaveMaskRegClass());
-        MachineInstr *NewInstr =
-            BuildMI(*MBB, Inst, Inst.getDebugLoc(), NewDesc, CondReg)
-                .add(Inst.getOperand(0))
-                .add(Inst.getOperand(1));
-        legalizeOperands(*NewInstr, MDT);
-        int SCCIdx = Inst.findRegisterDefOperandIdx(AMDGPU::SCC);
-        MachineOperand SCCOp = Inst.getOperand(SCCIdx);
-        addSCCDefUsersToVALUWorklist(SCCOp, Inst, Worklist, CondReg);

14 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - const MCInstrDesc &NewDesc = get(NewOpcode)…
CondReg = MRI.createVirtualRegister(RI.getWaveMaskRegClass());
MachineInstr *NewInstr =
BuildMI(*MBB, Inst, Inst.getDebugLoc(), NewDesc, CondReg)
.add(Inst.getOperand(0))
.add(Inst.getOperand(1));
legalizeOperands(*NewInstr, MDT);
int SCCIdx = Inst.findRegisterDefOperandIdx(AMDGPU::SCC);
MachineOperand SCCOp = Inst.getOperand(SCCIdx);
addSCCDefUsersToVALUWorklist(SCCOp, Inst, Worklist, CondReg);
Inst.eraseFromParent();
} }
continue;
}
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-
Lint: Pre-merge checks: clang-format: please reformat the code ``` - ```
if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) { if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
// We cannot move this instruction to the VALU, so we should try to // We cannot move this instruction to the VALU, so we should try to
// legalize its operands instead. // legalize its operands instead.
CreatedBBTmp = legalizeOperands(Inst, MDT); CreatedBBTmp = legalizeOperands(Inst, MDT);
if (CreatedBBTmp && TopInst.getParent() == CreatedBBTmp) if (CreatedBBTmp && TopInst.getParent() == CreatedBBTmp)
CreatedBB = CreatedBBTmp; CreatedBB = CreatedBBTmp;
continue; continue;
} }
▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Linesvoid SIInstrInfo::lowerSelect(SetVectorType &Worklist, MachineInstr &Inst,
DebugLoc DL = Inst.getDebugLoc(); DebugLoc DL = Inst.getDebugLoc();
MachineOperand &Dest = Inst.getOperand(0); MachineOperand &Dest = Inst.getOperand(0);
MachineOperand &Src0 = Inst.getOperand(1); MachineOperand &Src0 = Inst.getOperand(1);
MachineOperand &Src1 = Inst.getOperand(2); MachineOperand &Src1 = Inst.getOperand(2);
MachineOperand &Cond = Inst.getOperand(3); MachineOperand &Cond = Inst.getOperand(3);
Register SCCSource = Cond.getReg(); Register SCCSource = Cond.getReg();
// Find SCC def, and if that is a copy (SCC = COPY reg) then use reg instead.
if (!Cond.isUndef()) {
for (MachineInstr &CandI :
make_range(std::next(MachineBasicBlock::reverse_iterator(Inst)),
Inst.getParent()->rend())) {
if (CandI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) !=
-1) {
if (CandI.isCopy() && CandI.getOperand(0).getReg() == AMDGPU::SCC) {
SCCSource = CandI.getOperand(1).getReg();
}
break;
}
}
}
// If this is a trivial select where the condition is effectively not SCC // If this is a trivial select where the condition is effectively not SCC
// (SCCSource is a source of copy to SCC), then the select is semantically // (SCCSource is a source of copy to SCC), then the select is semantically
// equivalent to copying SCCSource. Hence, there is no need to create // equivalent to copying SCCSource. Hence, there is no need to create
// V_CNDMASK, we can just use that and bail out. // V_CNDMASK, we can just use that and bail out.
if ((SCCSource != AMDGPU::SCC) && Src0.isImm() && (Src0.getImm() == -1) && if ((SCCSource != AMDGPU::SCC) && Src0.isImm() && (Src0.getImm() == -1) &&
Src1.isImm() && (Src1.getImm() == 0)) { Src1.isImm() && (Src1.getImm() == 0)) {
MRI.replaceRegWith(Dest.getReg(), SCCSource); MRI.replaceRegWith(Dest.getReg(), SCCSource);
return; return;
} }
const TargetRegisterClass *TC = ST.getWavefrontSize() == 64 const TargetRegisterClass *TC = ST.getWavefrontSize() == 64
? &AMDGPU::SReg_64_XEXECRegClass ? &AMDGPU::SReg_64_XEXECRegClass
: &AMDGPU::SReg_32_XM0_XEXECRegClass; : &AMDGPU::SReg_32_XM0_XEXECRegClass;
Register CopySCC = MRI.createVirtualRegister(TC); Register CopySCC = MRI.createVirtualRegister(TC);
bool NeedCopy = false;
if (SCCSource == AMDGPU::SCC) { if (SCCSource == AMDGPU::SCC) {
// Insert a trivial select instead of creating a copy, because a copy from // Insert a trivial select instead of creating a copy, because a copy from
// SCC would semantically mean just copying a single bit, but we may need // SCC would semantically mean just copying a single bit, but we may need
// the result to be a vector condition mask that needs preserving. // the result to be a vector condition mask that needs preserving.
unsigned Opcode = (ST.getWavefrontSize() == 64) ? AMDGPU::S_CSELECT_B64 unsigned Opcode = (ST.getWavefrontSize() == 64) ? AMDGPU::S_CSELECT_B64
: AMDGPU::S_CSELECT_B32; : AMDGPU::S_CSELECT_B32;
auto NewSelect = auto NewSelect =
BuildMI(MBB, MII, DL, get(Opcode), CopySCC).addImm(-1).addImm(0); BuildMI(MBB, MII, DL, get(Opcode), CopySCC).addImm(-1).addImm(0);
NewSelect->getOperand(3).setIsUndef(Cond.isUndef()); NewSelect->getOperand(3).setIsUndef(Cond.isUndef());
} else { NeedCopy = true;
BuildMI(MBB, MII, DL, get(AMDGPU::COPY), CopySCC).addReg(SCCSource);
} }
Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
auto UpdatedInst = auto UpdatedInst =
BuildMI(MBB, MII, DL, get(AMDGPU::V_CNDMASK_B32_e64), ResultReg) BuildMI(MBB, MII, DL, get(AMDGPU::V_CNDMASK_B32_e64), ResultReg)
.addImm(0) .addImm(0)
.add(Src1) // False .add(Src1) // False
.addImm(0) .addImm(0)
.add(Src0) // True .add(Src0) // True
.addReg(CopySCC); .addReg(NeedCopy? CopySCC:SCCSource);
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-          .addReg(NeedCopy? CopySCC:SCCSource);
+          .addReg(NeedCopy ? CopySCC : SCCSource);
Lint: Pre-merge checks: clang-format: please reformat the code ``` - .addReg(NeedCopy? CopySCC:SCCSource); +…
MRI.replaceRegWith(Dest.getReg(), ResultReg); MRI.replaceRegWith(Dest.getReg(), ResultReg);
legalizeOperands(*UpdatedInst, MDT); legalizeOperands(*UpdatedInst, MDT);
addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
} }
void SIInstrInfo::lowerScalarAbs(SetVectorType &Worklist, void SIInstrInfo::lowerScalarAbs(SetVectorType &Worklist,
MachineInstr &Inst) const { MachineInstr &Inst) const {
▲ Show 20 Lines • Show All 574 Lines • ▼ Show 20 Linesvoid SIInstrInfo::movePackToVALU(SetVectorType &Worklist,
MachineOperand &Dest = Inst.getOperand(0); MachineOperand &Dest = Inst.getOperand(0);
MRI.replaceRegWith(Dest.getReg(), ResultReg); MRI.replaceRegWith(Dest.getReg(), ResultReg);
addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
} }
void SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineOperand &Op, void SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineOperand &Op,
MachineInstr &SCCDefInst, MachineInstr &SCCDefInst,
SetVectorType &Worklist) const { SetVectorType &Worklist,
bool SCCUsedImplicitly = false; Register NewCond) const {
// Ensure that def inst defines SCC, which is still live. // Ensure that def inst defines SCC, which is still live.
assert(Op.isReg() && Op.getReg() == AMDGPU::SCC && Op.isDef() && assert(Op.isReg() && Op.getReg() == AMDGPU::SCC && Op.isDef() &&
!Op.isDead() && Op.getParent() == &SCCDefInst); !Op.isDead() && Op.getParent() == &SCCDefInst);
SmallVector<MachineInstr *, 4> CopyToDelete; SmallVector<MachineInstr *, 4> CopyToDelete;
// This assumes that all the users of SCC are in the same block // This assumes that all the users of SCC are in the same block
// as the SCC def. // as the SCC def.
for (MachineInstr &MI : // Skip the def inst itself. for (MachineInstr &MI : // Skip the def inst itself.
make_range(std::next(MachineBasicBlock::iterator(SCCDefInst)), make_range(std::next(MachineBasicBlock::iterator(SCCDefInst)),
SCCDefInst.getParent()->end())) { SCCDefInst.getParent()->end())) {
// Check if SCC is used first. // Check if SCC is used first.
if (MI.findRegisterUseOperandIdx(AMDGPU::SCC, false, &RI) != -1) { int SCCIdx = MI.findRegisterUseOperandIdx(AMDGPU::SCC, false, &RI);
if (SCCIdx != -1) {
if (MI.isCopy()) { if (MI.isCopy()) {
MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
Register DestReg = MI.getOperand(0).getReg(); Register DestReg = MI.getOperand(0).getReg();
for (auto &User : MRI.use_nodbg_instructions(DestReg)) { MRI.replaceRegWith(DestReg, NewCond);
if ((User.getOpcode() == AMDGPU::S_ADD_CO_PSEUDO) ||
(User.getOpcode() == AMDGPU::S_SUB_CO_PSEUDO)) {
User.getOperand(4).setReg(RI.getVCC());
Worklist.insert(&User);
} else if (User.getOpcode() == AMDGPU::V_CNDMASK_B32_e64) {
User.getOperand(5).setReg(RI.getVCC());
// No need to add to Worklist.
}
}
CopyToDelete.push_back(&MI); CopyToDelete.push_back(&MI);
} else { } else {
if (MI.getOpcode() == AMDGPU::S_CSELECT_B32 ||
MI.getOpcode() == AMDGPU::S_CSELECT_B64) { if (NewCond.isValid())
// This is an implicit use of SCC and it is really expected by MI.getOperand(SCCIdx).setReg(NewCond);
// the SCC users to handle.
// We cannot preserve the edge to the user so add the explicit
// copy: SCC = COPY VCC.
// The copy will be cleaned up during the processing of the user
// in lowerSelect.
SCCUsedImplicitly = true;
}
Worklist.insert(&MI); Worklist.insert(&MI);
} }
} }
// Exit if we find another SCC def. // Exit if we find another SCC def.
if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != -1) if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != -1)
break; break;
} }
for (auto &Copy : CopyToDelete) for (auto &Copy : CopyToDelete)
Copy->eraseFromParent(); Copy->eraseFromParent();
if (SCCUsedImplicitly) {
BuildMI(*SCCDefInst.getParent(), std::next(SCCDefInst.getIterator()),
SCCDefInst.getDebugLoc(), get(AMDGPU::COPY), AMDGPU::SCC)
.addReg(RI.getVCC());
}
} }
// Instructions that use SCC may be converted to VALU instructions. When that // Instructions that use SCC may be converted to VALU instructions. When that
// happens, the SCC register is changed to VCC_LO. The instruction that defines // happens, the SCC register is changed to VCC_LO. The instruction that defines
// SCC must be changed to an instruction that defines VCC. This function makes // SCC must be changed to an instruction that defines VCC. This function makes
// sure that the instruction that defines SCC is added to the moveToVALU // sure that the instruction that defines SCC is added to the moveToVALU
// worklist. // worklist.
void SIInstrInfo::addSCCDefsToVALUWorklist(MachineOperand &Op, void SIInstrInfo::addSCCDefsToVALUWorklist(MachineOperand &Op,
▲ Show 20 Lines • Show All 1,032 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/SIInstrInfo.td

Show First 20 Lines • Show All 521 Lines • ▼ Show 20 Linesdef atomic_store_local_64_m0 : PatFrag <
let MemoryVT = i64; let MemoryVT = i64;
} }
} // End let AddressSpaces = StoreAddress_local.AddrSpaces } // End let AddressSpaces = StoreAddress_local.AddrSpaces
def si_setcc_uniform : PatFrag < def si_setcc_uniform : PatFrag <
(ops node:$lhs, node:$rhs, node:$cond), (ops node:$lhs, node:$rhs, node:$cond),
(setcc node:$lhs, node:$rhs, node:$cond), [{ (setcc node:$lhs, node:$rhs, node:$cond), [{
for (SDNode *Use : N->uses()) { return !N->isDivergent();
foadUnsubmitted
Not Done
ReplyInline Actions

I think you probably need to look ahead to see if this setcc is used by a divergent select. Otherwise you regress: a == b ? c : d where a and b are uniform but c or d are divergent. In this case it is better to use v_cmp than s_cmp, even though the operands are uniform, because it can feed straight into v_cndmask.

foad: I think you probably need to look ahead to see if this setcc is used by a divergent select.
alex-tAuthorUnsubmitted
Done
ReplyInline Actions

That's right. And is planned for the next change. I am just trying to keep it staged. In general, I am planning to add the dedicated procedure that checks the "VALU only" SDNode users beforehand and selects to VALU even uniform if any.

alex-t: That's right. And is planned for the next change. I am just trying to keep it staged. In…
nhaehnleUnsubmitted
Not Done
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Is it so clear-cut?

For a == b ? c : d with a and b uniform but c or d divergent, there's a choice between v_cmp + v_cndmask vs. s_cmp + s_cselect + v_cndmask.

So this change increases code size and trades 1 VALU for 2 SALU, but SALU utilization tends to be low, so purely based on instruction counts the s_cmp-based sequence is still better most of the time. On gfx10 there's a scheduling pitfall to watch out for though.

nhaehnle: Is it so clear-cut? For `a == b ? c : d` with a and b uniform but c or d divergent, there's a…
alex-tAuthorUnsubmitted
Done
ReplyInline Actions

For this concrete example, S_CMP is still better. In my comment above I meant that I am planning to add a selection predicate as the right place to decide if the given node should be selected to VALU or SALU.
Further, we can try different strategies - one described above or another one, more complex.

alex-t: For this concrete example, S_CMP is still better. In my comment above I meant that I am…
if (Use->isMachineOpcode() || Use->getOpcode() != ISD::CopyToReg)
return false;
unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
if (Reg != AMDGPU::SCC)
return false;
}
return true;
}]>; }]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SDNodes PatFrags for a16 loads and stores with 3 components. // SDNodes PatFrags for a16 loads and stores with 3 components.
// v3f16/v3i16 is widened to v4f16/v4i16, so we need to match on the memory // v3f16/v3i16 is widened to v4f16/v4i16, so we need to match on the memory
// load/store size. // load/store size.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 2,025 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/addrspacecast.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s
; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast: ; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast:
; HSA: enable_sgpr_private_segment_buffer = 1 ; HSA: enable_sgpr_private_segment_buffer = 1
; HSA: enable_sgpr_dispatch_ptr = 0 ; HSA: enable_sgpr_dispatch_ptr = 0
; CI: enable_sgpr_queue_ptr = 1 ; CI: enable_sgpr_queue_ptr = 1
; GFX9: enable_sgpr_queue_ptr = 0 ; GFX9: enable_sgpr_queue_ptr = 0
; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}} ; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}}
; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}} ; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}}
; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]] ; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]]
; CI-DAG: v_cmp_ne_u32_e64 vcc, [[PTR]], -1 ; CI-DAG: s_cmp_lg_u32 [[PTR]], -1
; CI-DAG: s_cselect_b64 vcc, -1, 0
rampitecUnsubmitted
Not Done
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This also needs a sort of a look ahead.

rampitec: This also needs a sort of a look ahead.
alex-tAuthorUnsubmitted
Done
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All such a kind of regressions need to be addressed in the separate patch I believe. Please note here 2 facts:

  1. v_cndmask that consumes VCC is uniform and should be selected to S_CSELECT itself but this part of the work is not done yet.
  2. To fix all of these patterns I need to add a lookahead in the selection predicate - scan over all CC users and select only if no VALU instructions were found. I was planning this as a separate change.
alex-t: All such a kind of regressions need to be addressed in the separate patch I believe. Please…
; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc ; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
; CI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] ; CI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] ; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}} ; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}}
; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) ; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16)
; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 ; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16
; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_SHARED_BASE]] ; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_SHARED_BASE]]
; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_shared_base ; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_shared_base
; GFX9: v_cmp_ne_u32_e64 vcc, [[PTR]], -1 ; GFX9: s_cmp_lg_u32 [[PTR]], -1
; GFX9: s_cselect_b64 vcc, -1, 0
; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc ; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
; GFX9-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] ; GFX9-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] ; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] ; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]]
; At most 2 digits. Make sure src_shared_base is not counted as a high ; At most 2 digits. Make sure src_shared_base is not counted as a high
; number SGPR. ; number SGPR.
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; CI: enable_sgpr_queue_ptr = 1 ; CI: enable_sgpr_queue_ptr = 1
; GFX9: enable_sgpr_queue_ptr = 0 ; GFX9: enable_sgpr_queue_ptr = 0
; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}} ; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}}
; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11{{$}} ; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11{{$}}
; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]] ; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]]
; CI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 ; CI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
; CI-DAG: v_cmp_ne_u32_e64 vcc, [[PTR]], -1 ; CI-DAG: s_cmp_lg_u32 [[PTR]], -1
; CI-DAG: s_cselect_b64 vcc, -1, 0
; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc ; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
; CI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] ; CI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] ; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}} ; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}}
; GFX9-DAG: s_getreg_b32 [[SSRC_PRIVATE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16) ; GFX9-DAG: s_getreg_b32 [[SSRC_PRIVATE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16)
; GFX9-DAG: s_lshl_b32 [[SSRC_PRIVATE_BASE:s[0-9]+]], [[SSRC_PRIVATE]], 16 ; GFX9-DAG: s_lshl_b32 [[SSRC_PRIVATE_BASE:s[0-9]+]], [[SSRC_PRIVATE]], 16
; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_PRIVATE_BASE]] ; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_PRIVATE_BASE]]
; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_private_base ; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_private_base
; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 ; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
; GFX9: v_cmp_ne_u32_e64 vcc, [[PTR]], -1 ; GFX9: s_cmp_lg_u32 [[PTR]], -1
; GFX9: s_cselect_b64 vcc, -1, 0
; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc ; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
; GFX9: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] ; GFX9: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] ; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] ; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]]
; CI: NumSgprs: {{[0-9][0-9]+}} ; CI: NumSgprs: {{[0-9][0-9]+}}
; GFX9: NumSgprs: {{[0-9]+}} ; GFX9: NumSgprs: {{[0-9]+}}
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llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll

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; GCN-LABEL: {{^}}work_item_info: ; GCN-LABEL: {{^}}work_item_info:
; GCN-NOT: v0 ; GCN-NOT: v0
; GCN: s_load_dword [[IN:s[0-9]+]] ; GCN: s_load_dword [[IN:s[0-9]+]]
; GCN-NOT: v0 ; GCN-NOT: v0
; GCN-ALLOCA: v_add_{{[iu]}}32_e32 [[RESULT:v[0-9]+]], vcc, v{{[0-9]+}}, v0 ; GCN-ALLOCA: v_add_{{[iu]}}32_e32 [[RESULT:v[0-9]+]], vcc, v{{[0-9]+}}, v0
; GCN-PROMOTE: v_cmp_eq_u32_e64 vcc, [[IN]], 1 ; GCN-PROMOTE: s_cmp_eq_u32 [[IN]], 1
; GCN-PROMOTE-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-PROMOTE-NEXT: v_addc_u32_e32 [[RESULT:v[0-9]+]], vcc, 0, v0, vcc ; GCN-PROMOTE-NEXT: v_addc_u32_e32 [[RESULT:v[0-9]+]], vcc, 0, v0, vcc
; GCN: buffer_store_dword [[RESULT]] ; GCN: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @work_item_info(i32 addrspace(1)* %out, i32 %in) { define amdgpu_kernel void @work_item_info(i32 addrspace(1)* %out, i32 %in) {
entry: entry:
%0 = alloca [2 x i32], addrspace(5) %0 = alloca [2 x i32], addrspace(5)
%1 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 0 %1 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 0
%2 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 1 %2 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 1
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llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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; CHECK-NEXT: [[TMP37:%.*]] = xor i32 [[TMP36]], [[TMP3]] ; CHECK-NEXT: [[TMP37:%.*]] = xor i32 [[TMP36]], [[TMP3]]
; CHECK-NEXT: [[TMP38:%.*]] = sub i32 [[TMP37]], [[TMP3]] ; CHECK-NEXT: [[TMP38:%.*]] = sub i32 [[TMP37]], [[TMP3]]
; CHECK-NEXT: store i32 [[TMP38]], i32 addrspace(1)* [[OUT:%.*]], align 4 ; CHECK-NEXT: store i32 [[TMP38]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: sdiv_i32: ; GFX6-LABEL: sdiv_i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb ; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_ashr_i32 s8, s3, 31 ; GFX6-NEXT: s_ashr_i32 s8, s3, 31
; GFX6-NEXT: s_add_i32 s3, s3, s8 ; GFX6-NEXT: s_add_i32 s3, s3, s8
; GFX6-NEXT: s_xor_b32 s9, s3, s8 ; GFX6-NEXT: s_xor_b32 s3, s3, s8
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX6-NEXT: s_sub_i32 s3, 0, s9 ; GFX6-NEXT: s_sub_i32 s4, 0, s3
; GFX6-NEXT: s_ashr_i32 s0, s2, 31
; GFX6-NEXT: s_add_i32 s1, s2, s0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_xor_b32 s1, s1, s0
; GFX6-NEXT: s_xor_b32 s2, s0, s8
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0 ; GFX6-NEXT: v_mul_lo_u32 v1, s4, v0
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX6-NEXT: s_ashr_i32 s0, s2, 31
; GFX6-NEXT: s_add_i32 s1, s2, s0
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: s_xor_b32 s1, s1, s0
; GFX6-NEXT: s_xor_b32 s2, s0, s8
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
; GFX6-NEXT: v_mul_lo_u32 v1, v0, s9 ; GFX6-NEXT: v_mul_lo_u32 v1, v0, s3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v1 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v1 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s9, v1 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v1 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, s2, v0
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdiv_i32: ; GFX9-LABEL: sdiv_i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s4, s3, 31 ; GFX9-NEXT: s_ashr_i32 s4, s3, 31
; GFX9-NEXT: s_add_i32 s3, s3, s4 ; GFX9-NEXT: s_add_i32 s3, s3, s4
; GFX9-NEXT: s_xor_b32 s5, s3, s4 ; GFX9-NEXT: s_xor_b32 s3, s3, s4
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s5 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX9-NEXT: s_sub_i32 s3, 0, s5 ; GFX9-NEXT: s_sub_i32 s5, 0, s3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_lo_u32 v1, s3, v0 ; GFX9-NEXT: v_mul_lo_u32 v1, s5, v0
; GFX9-NEXT: s_ashr_i32 s3, s2, 31 ; GFX9-NEXT: s_ashr_i32 s5, s2, 31
; GFX9-NEXT: s_add_i32 s2, s2, s3 ; GFX9-NEXT: s_add_i32 s2, s2, s5
; GFX9-NEXT: s_xor_b32 s2, s2, s3 ; GFX9-NEXT: s_xor_b32 s2, s2, s5
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: s_xor_b32 s3, s3, s4 ; GFX9-NEXT: s_xor_b32 s4, s5, s4
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX9-NEXT: v_mul_lo_u32 v1, v0, s5 ; GFX9-NEXT: v_mul_lo_u32 v1, v0, s3
; GFX9-NEXT: v_add_u32_e32 v3, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
; GFX9-NEXT: v_sub_u32_e32 v1, s2, v1 ; GFX9-NEXT: v_sub_u32_e32 v1, s2, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, s5, v1 ; GFX9-NEXT: v_subrev_u32_e32 v3, s3, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_add_u32_e32 v3, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, s3, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0
; GFX9-NEXT: v_subrev_u32_e32 v0, s3, v0 ; GFX9-NEXT: v_subrev_u32_e32 v0, s4, v0
; GFX9-NEXT: global_store_dword v2, v0, s[0:1] ; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%r = sdiv i32 %x, %y %r = sdiv i32 %x, %y
store i32 %r, i32 addrspace(1)* %out store i32 %r, i32 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @srem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) { define amdgpu_kernel void @srem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
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; ;
; GFX6-LABEL: srem_i32: ; GFX6-LABEL: srem_i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb ; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_ashr_i32 s4, s3, 31 ; GFX6-NEXT: s_ashr_i32 s4, s3, 31
; GFX6-NEXT: s_add_i32 s3, s3, s4 ; GFX6-NEXT: s_add_i32 s3, s3, s4
; GFX6-NEXT: s_xor_b32 s6, s3, s4 ; GFX6-NEXT: s_xor_b32 s4, s3, s4
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s4
; GFX6-NEXT: s_sub_i32 s3, 0, s6 ; GFX6-NEXT: s_sub_i32 s3, 0, s4
; GFX6-NEXT: s_ashr_i32 s4, s2, 31 ; GFX6-NEXT: s_ashr_i32 s5, s2, 31
; GFX6-NEXT: s_add_i32 s2, s2, s4 ; GFX6-NEXT: s_add_i32 s2, s2, s5
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_xor_b32 s5, s2, s4 ; GFX6-NEXT: s_xor_b32 s6, s2, s5
; GFX6-NEXT: s_mov_b32 s2, -1 ; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0 ; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s6, v0
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s4
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0 ; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0 ; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, s4, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, s5, v0
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s5, v0
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: srem_i32: ; GFX9-LABEL: srem_i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0
; GFX9-NEXT: s_sub_i32 s2, 0, s10 ; GFX9-NEXT: s_sub_i32 s2, 0, s10
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_f32_e32 v2, s12, v5 ; GFX9-NEXT: v_mul_f32_e32 v3, s12, v5
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX9-NEXT: v_mul_lo_u32 v3, v0, s8
; GFX9-NEXT: v_add_u32_e32 v6, 1, v0
; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3 ; GFX9-NEXT: v_mul_lo_u32 v5, v0, s8
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 ; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s11
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX9-NEXT: v_subrev_u32_e32 v6, s8, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s11
; GFX9-NEXT: v_add_u32_e32 v6, 1, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, s2, v2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX9-NEXT: v_mul_lo_u32 v5, v1, s9
; GFX9-NEXT: s_sub_i32 s2, 0, s11
; GFX9-NEXT: v_mul_hi_u32 v6, v2, v6
; GFX9-NEXT: v_mul_f32_e32 v3, s12, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: v_sub_u32_e32 v5, s5, v5 ; GFX9-NEXT: v_add_u32_e32 v7, 1, v0
; GFX9-NEXT: v_add_u32_e32 v2, v2, v6 ; GFX9-NEXT: v_sub_u32_e32 v5, s4, v5
; GFX9-NEXT: v_add_u32_e32 v7, 1, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5
; GFX9-NEXT: v_mul_lo_u32 v6, s2, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5 ; GFX9-NEXT: v_subrev_u32_e32 v7, s8, v5
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX9-NEXT: v_subrev_u32_e32 v7, s9, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX9-NEXT: v_mul_hi_u32 v2, s6, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, v1, s9
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX9-NEXT: v_mul_hi_u32 v5, v3, v6 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5
; GFX9-NEXT: v_add_u32_e32 v7, 1, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v7, s2, v3
; GFX9-NEXT: v_sub_u32_e32 v6, s5, v6
; GFX9-NEXT: v_mul_f32_e32 v2, s12, v2
; GFX9-NEXT: v_add_u32_e32 v5, 1, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v6
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX9-NEXT: v_mul_hi_u32 v5, v3, v7
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX9-NEXT: s_sub_i32 s2, 0, s11
; GFX9-NEXT: v_subrev_u32_e32 v7, s9, v6
; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
; GFX9-NEXT: v_mul_lo_u32 v5, s2, v2
; GFX9-NEXT: v_mul_hi_u32 v3, s6, v3
; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GFX9-NEXT: v_add_u32_e32 v7, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v7, 1, v1
; GFX9-NEXT: v_mul_lo_u32 v8, v2, s10 ; GFX9-NEXT: v_mul_hi_u32 v5, v2, v5
; GFX9-NEXT: v_mul_lo_u32 v8, v3, s10
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v6
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX9-NEXT: v_add_u32_e32 v3, v3, v5 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
; GFX9-NEXT: v_mul_hi_u32 v3, s7, v3 ; GFX9-NEXT: v_mul_hi_u32 v5, s7, v2
; GFX9-NEXT: v_sub_u32_e32 v6, s6, v8 ; GFX9-NEXT: v_sub_u32_e32 v6, s6, v8
; GFX9-NEXT: v_add_u32_e32 v7, 1, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v6 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v6
; GFX9-NEXT: v_subrev_u32_e32 v5, s10, v6 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX9-NEXT: v_subrev_u32_e32 v3, s10, v6
; GFX9-NEXT: v_mul_lo_u32 v6, v3, s11 ; GFX9-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; GFX9-NEXT: v_add_u32_e32 v7, 1, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, v5, s11
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v5
; GFX9-NEXT: v_add_u32_e32 v7, 1, v2 ; GFX9-NEXT: v_add_u32_e32 v7, 1, v2
; GFX9-NEXT: v_sub_u32_e32 v5, s7, v6
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
; GFX9-NEXT: v_add_u32_e32 v6, 1, v3 ; GFX9-NEXT: v_sub_u32_e32 v3, s7, v6
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v5 ; GFX9-NEXT: v_add_u32_e32 v6, 1, v5
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
; GFX9-NEXT: v_subrev_u32_e32 v6, s11, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
; GFX9-NEXT: v_add_u32_e32 v6, 1, v3 ; GFX9-NEXT: v_subrev_u32_e32 v6, s11, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v5
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; GFX9-NEXT: v_add_u32_e32 v6, 1, v5
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%r = udiv <4 x i32> %x, %y %r = udiv <4 x i32> %x, %y
store <4 x i32> %r, <4 x i32> addrspace(1)* %out store <4 x i32> %r, <4 x i32> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @urem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) { define amdgpu_kernel void @urem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
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; GFX6-NEXT: s_load_dwordx8 s[8:15], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx8 s[8:15], s[0:1], 0xd
; GFX6-NEXT: s_mov_b32 s16, 0x4f7ffffe ; GFX6-NEXT: s_mov_b32 s16, 0x4f7ffffe
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_ashr_i32 s2, s12, 31 ; GFX6-NEXT: s_ashr_i32 s2, s12, 31
; GFX6-NEXT: s_add_i32 s3, s12, s2 ; GFX6-NEXT: s_add_i32 s3, s12, s2
; GFX6-NEXT: s_xor_b32 s12, s3, s2 ; GFX6-NEXT: s_xor_b32 s3, s3, s2
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX6-NEXT: s_ashr_i32 s3, s13, 31 ; GFX6-NEXT: s_ashr_i32 s12, s13, 31
; GFX6-NEXT: s_add_i32 s0, s13, s3 ; GFX6-NEXT: s_add_i32 s0, s13, s12
; GFX6-NEXT: s_xor_b32 s13, s0, s3 ; GFX6-NEXT: s_xor_b32 s13, s0, s12
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s13 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX6-NEXT: s_sub_i32 s1, 0, s12 ; GFX6-NEXT: s_sub_i32 s1, 0, s3
; GFX6-NEXT: s_ashr_i32 s0, s8, 31 ; GFX6-NEXT: s_ashr_i32 s0, s8, 31
; GFX6-NEXT: v_mul_f32_e32 v0, s16, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, s16, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: s_xor_b32 s2, s0, s2 ; GFX6-NEXT: s_xor_b32 s2, s0, s2
; GFX6-NEXT: v_mul_lo_u32 v2, s1, v0 ; GFX6-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX6-NEXT: s_add_i32 s1, s8, s0 ; GFX6-NEXT: s_add_i32 s1, s8, s0
; GFX6-NEXT: v_mul_f32_e32 v1, s16, v1 ; GFX6-NEXT: v_mul_f32_e32 v1, s16, v1
; GFX6-NEXT: s_xor_b32 s1, s1, s0 ; GFX6-NEXT: s_xor_b32 s1, s1, s0
; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: s_sub_i32 s0, 0, s13 ; GFX6-NEXT: s_sub_i32 s0, 0, s13
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
; GFX6-NEXT: v_mul_lo_u32 v2, s0, v1 ; GFX6-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX6-NEXT: v_mul_lo_u32 v3, v0, s12 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s3
; GFX6-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s1, v3 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s1, v3
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v3 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v3
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s12, v3 ; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s3, v3
; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v3 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, s2, v0
; GFX6-NEXT: s_ashr_i32 s0, s9, 31 ; GFX6-NEXT: s_ashr_i32 s0, s9, 31
; GFX6-NEXT: s_add_i32 s1, s9, s0 ; GFX6-NEXT: s_add_i32 s1, s9, s0
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, s2, v0
; GFX6-NEXT: s_xor_b32 s2, s0, s3
; GFX6-NEXT: s_ashr_i32 s3, s14, 31 ; GFX6-NEXT: s_ashr_i32 s3, s14, 31
; GFX6-NEXT: s_xor_b32 s1, s1, s0 ; GFX6-NEXT: s_xor_b32 s1, s1, s0
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
; GFX6-NEXT: s_xor_b32 s2, s0, s12
; GFX6-NEXT: s_add_i32 s0, s14, s3 ; GFX6-NEXT: s_add_i32 s0, s14, s3
; GFX6-NEXT: s_xor_b32 s9, s0, s3 ; GFX6-NEXT: s_xor_b32 s8, s0, s3
; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s9 ; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s8
; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1 ; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX6-NEXT: v_mul_lo_u32 v2, v1, s13 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s13
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v1 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v1
; GFX6-NEXT: v_mul_f32_e32 v3, s16, v3 ; GFX6-NEXT: v_mul_f32_e32 v3, s16, v3
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s1, v2 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s1, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v2 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v2
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s13, v2 ; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s13, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
; GFX6-NEXT: s_sub_i32 s0, 0, s9 ; GFX6-NEXT: s_sub_i32 s0, 0, s8
; GFX6-NEXT: v_mul_lo_u32 v5, s0, v3 ; GFX6-NEXT: v_mul_lo_u32 v5, s0, v3
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v1 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s13, v2 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s13, v2
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX6-NEXT: v_mul_hi_u32 v2, v3, v5 ; GFX6-NEXT: v_mul_hi_u32 v2, v3, v5
; GFX6-NEXT: v_xor_b32_e32 v1, s2, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, s2, v1
; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s2, v1 ; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s2, v1
; GFX6-NEXT: s_ashr_i32 s2, s15, 31 ; GFX6-NEXT: s_ashr_i32 s2, s15, 31
; GFX6-NEXT: s_ashr_i32 s0, s10, 31 ; GFX6-NEXT: s_ashr_i32 s0, s10, 31
; GFX6-NEXT: s_add_i32 s8, s15, s2 ; GFX6-NEXT: s_add_i32 s9, s15, s2
; GFX6-NEXT: s_add_i32 s1, s10, s0 ; GFX6-NEXT: s_add_i32 s1, s10, s0
; GFX6-NEXT: s_xor_b32 s8, s8, s2 ; GFX6-NEXT: s_xor_b32 s9, s9, s2
; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s8 ; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s9
; GFX6-NEXT: s_xor_b32 s1, s1, s0 ; GFX6-NEXT: s_xor_b32 s1, s1, s0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_mul_hi_u32 v2, s1, v2 ; GFX6-NEXT: v_mul_hi_u32 v2, s1, v2
; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GFX6-NEXT: s_xor_b32 s3, s0, s3 ; GFX6-NEXT: s_xor_b32 s3, s0, s3
; GFX6-NEXT: v_mul_lo_u32 v3, v2, s9 ; GFX6-NEXT: v_mul_lo_u32 v3, v2, s8
; GFX6-NEXT: v_mul_f32_e32 v4, s16, v4 ; GFX6-NEXT: v_mul_f32_e32 v4, s16, v4
; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v2 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v2
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s1, v3 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s1, v3
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v3 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v3
; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s9, v3 ; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s8, v3
; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
; GFX6-NEXT: s_sub_i32 s0, 0, s8 ; GFX6-NEXT: s_sub_i32 s0, 0, s9
; GFX6-NEXT: v_mul_lo_u32 v5, s0, v4 ; GFX6-NEXT: v_mul_lo_u32 v5, s0, v4
; GFX6-NEXT: s_ashr_i32 s0, s11, 31 ; GFX6-NEXT: s_ashr_i32 s0, s11, 31
; GFX6-NEXT: s_add_i32 s1, s11, s0 ; GFX6-NEXT: s_add_i32 s1, s11, s0
; GFX6-NEXT: s_xor_b32 s1, s1, s0 ; GFX6-NEXT: s_xor_b32 s1, s1, s0
; GFX6-NEXT: v_mul_hi_u32 v5, v4, v5 ; GFX6-NEXT: v_mul_hi_u32 v5, v4, v5
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v2 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v2
; GFX6-NEXT: s_xor_b32 s2, s0, s2 ; GFX6-NEXT: s_xor_b32 s2, s0, s2
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_mul_hi_u32 v4, s1, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, s1, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v3 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX6-NEXT: v_xor_b32_e32 v2, s3, v2 ; GFX6-NEXT: v_xor_b32_e32 v2, s3, v2
; GFX6-NEXT: v_mul_lo_u32 v3, v4, s8 ; GFX6-NEXT: v_mul_lo_u32 v3, v4, s9
; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v4 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v4
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v2 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v2
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s1, v3 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s1, v3
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v3 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v3
; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s8, v3 ; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s9, v3
; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v4 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
; GFX6-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; GFX6-NEXT: v_xor_b32_e32 v3, s2, v3 ; GFX6-NEXT: v_xor_b32_e32 v3, s2, v3
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s2, v3 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s2, v3
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdiv_v4i32: ; GFX9-LABEL: sdiv_v4i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX9-NEXT: s_mov_b32 s13, 0x4f7ffffe ; GFX9-NEXT: s_mov_b32 s15, 0x4f7ffffe
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s2, s8, 31 ; GFX9-NEXT: s_ashr_i32 s2, s8, 31
; GFX9-NEXT: s_add_i32 s3, s8, s2 ; GFX9-NEXT: s_add_i32 s3, s8, s2
; GFX9-NEXT: s_xor_b32 s14, s3, s2 ; GFX9-NEXT: s_xor_b32 s3, s3, s2
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s14 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX9-NEXT: s_ashr_i32 s8, s9, 31 ; GFX9-NEXT: s_ashr_i32 s12, s9, 31
; GFX9-NEXT: s_add_i32 s9, s9, s8 ; GFX9-NEXT: s_add_i32 s9, s9, s12
; GFX9-NEXT: s_xor_b32 s15, s9, s8 ; GFX9-NEXT: s_xor_b32 s9, s9, s12
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s15 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX9-NEXT: s_sub_i32 s12, 0, s14 ; GFX9-NEXT: s_sub_i32 s14, 0, s3
; GFX9-NEXT: s_ashr_i32 s3, s4, 31 ; GFX9-NEXT: s_ashr_i32 s8, s4, 31
; GFX9-NEXT: v_mul_f32_e32 v0, s13, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, s15, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: s_add_i32 s4, s4, s3 ; GFX9-NEXT: s_add_i32 s4, s4, s8
; GFX9-NEXT: s_xor_b32 s4, s4, s3 ; GFX9-NEXT: s_xor_b32 s4, s4, s8
; GFX9-NEXT: v_mul_lo_u32 v2, s12, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s14, v0
; GFX9-NEXT: v_mul_f32_e32 v1, s13, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, s15, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_sub_i32 s12, 0, s15 ; GFX9-NEXT: s_sub_i32 s14, 0, s9
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: s_ashr_i32 s9, s5, 31 ; GFX9-NEXT: s_ashr_i32 s13, s5, 31
; GFX9-NEXT: v_mul_lo_u32 v3, s12, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s14, v1
; GFX9-NEXT: s_xor_b32 s2, s3, s2 ; GFX9-NEXT: s_add_i32 s5, s5, s13
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX9-NEXT: v_mul_hi_u32 v2, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v2, v1, v3
; GFX9-NEXT: s_add_i32 s3, s5, s9 ; GFX9-NEXT: s_xor_b32 s5, s5, s13
; GFX9-NEXT: s_xor_b32 s3, s3, s9 ; GFX9-NEXT: s_xor_b32 s2, s8, s2
; GFX9-NEXT: v_mul_lo_u32 v3, v0, s14 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, s3
; GFX9-NEXT: v_add_u32_e32 v1, v1, v2 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v2
; GFX9-NEXT: v_mul_hi_u32 v1, s3, v1
; GFX9-NEXT: v_add_u32_e32 v2, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v2, 1, v0
; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3 ; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_subrev_u32_e32 v2, s14, v3 ; GFX9-NEXT: v_subrev_u32_e32 v2, s3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v2 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, s15
; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
; GFX9-NEXT: v_sub_u32_e32 v2, s3, v2
; GFX9-NEXT: s_ashr_i32 s3, s10, 31 ; GFX9-NEXT: s_ashr_i32 s3, s10, 31
; GFX9-NEXT: s_add_i32 s4, s10, s3 ; GFX9-NEXT: s_add_i32 s4, s10, s3
; GFX9-NEXT: v_subrev_u32_e32 v0, s2, v0 ; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
; GFX9-NEXT: s_xor_b32 s2, s9, s8 ; GFX9-NEXT: s_xor_b32 s4, s4, s3
; GFX9-NEXT: s_xor_b32 s9, s4, s3 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s9 ; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s4
; GFX9-NEXT: v_mul_lo_u32 v2, v1, s9
; GFX9-NEXT: v_add_u32_e32 v5, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v5, 1, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v2 ; GFX9-NEXT: s_ashr_i32 s8, s11, 31
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX9-NEXT: v_subrev_u32_e32 v5, s15, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, s5, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v2
; GFX9-NEXT: s_sub_i32 s4, 0, s9 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX9-NEXT: v_mul_f32_e32 v3, s13, v3 ; GFX9-NEXT: v_mul_f32_e32 v3, s15, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v2 ; GFX9-NEXT: v_subrev_u32_e32 v5, s9, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX9-NEXT: s_sub_i32 s5, 0, s4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v2
; GFX9-NEXT: v_mul_lo_u32 v2, s5, v3
; GFX9-NEXT: s_add_i32 s9, s11, s8
; GFX9-NEXT: v_add_u32_e32 v5, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v5, 1, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GFX9-NEXT: s_xor_b32 s9, s9, s8
; GFX9-NEXT: v_mul_lo_u32 v2, s4, v3
; GFX9-NEXT: s_ashr_i32 s4, s6, 31
; GFX9-NEXT: s_add_i32 s5, s6, s4
; GFX9-NEXT: s_ashr_i32 s6, s11, 31
; GFX9-NEXT: s_add_i32 s8, s11, s6
; GFX9-NEXT: s_xor_b32 s8, s8, s6
; GFX9-NEXT: v_mul_hi_u32 v2, v3, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v3, v2
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s8 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX9-NEXT: s_xor_b32 s5, s5, s4 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s9
; GFX9-NEXT: v_xor_b32_e32 v1, s2, v1 ; GFX9-NEXT: s_ashr_i32 s5, s6, 31
; GFX9-NEXT: s_add_i32 s6, s6, s5
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v5
; GFX9-NEXT: v_mul_hi_u32 v2, s5, v2 ; GFX9-NEXT: s_xor_b32 s6, s6, s5
; GFX9-NEXT: v_subrev_u32_e32 v1, s2, v1 ; GFX9-NEXT: v_mul_hi_u32 v2, s6, v2
; GFX9-NEXT: s_xor_b32 s2, s4, s3 ; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
; GFX9-NEXT: v_mul_f32_e32 v3, s13, v3 ; GFX9-NEXT: v_mul_f32_e32 v3, s15, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: v_mul_lo_u32 v5, v2, s9 ; GFX9-NEXT: v_mul_lo_u32 v5, v2, s4
; GFX9-NEXT: s_sub_i32 s3, 0, s8 ; GFX9-NEXT: v_subrev_u32_e32 v0, s2, v0
; GFX9-NEXT: v_add_u32_e32 v6, 1, v2 ; GFX9-NEXT: s_xor_b32 s2, s13, s12
; GFX9-NEXT: v_xor_b32_e32 v1, s2, v1
; GFX9-NEXT: v_subrev_u32_e32 v1, s2, v1
; GFX9-NEXT: s_xor_b32 s2, s5, s3
; GFX9-NEXT: s_sub_i32 s3, 0, s9
; GFX9-NEXT: v_mul_lo_u32 v7, s3, v3 ; GFX9-NEXT: v_mul_lo_u32 v7, s3, v3
; GFX9-NEXT: v_sub_u32_e32 v5, s5, v5 ; GFX9-NEXT: v_sub_u32_e32 v5, s6, v5
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5 ; GFX9-NEXT: v_add_u32_e32 v6, 1, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v5
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX9-NEXT: v_subrev_u32_e32 v6, s9, v5 ; GFX9-NEXT: v_subrev_u32_e32 v6, s4, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
; GFX9-NEXT: v_mul_hi_u32 v6, v3, v7 ; GFX9-NEXT: v_mul_hi_u32 v6, v3, v7
; GFX9-NEXT: s_ashr_i32 s3, s7, 31 ; GFX9-NEXT: s_ashr_i32 s3, s7, 31
; GFX9-NEXT: s_add_i32 s4, s7, s3 ; GFX9-NEXT: s_add_i32 s5, s7, s3
; GFX9-NEXT: s_xor_b32 s4, s4, s3 ; GFX9-NEXT: s_xor_b32 s5, s5, s3
; GFX9-NEXT: v_add_u32_e32 v3, v3, v6 ; GFX9-NEXT: v_add_u32_e32 v3, v3, v6
; GFX9-NEXT: v_mul_hi_u32 v3, s4, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, s5, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v5
; GFX9-NEXT: v_add_u32_e32 v6, 1, v2 ; GFX9-NEXT: v_add_u32_e32 v6, 1, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, v3, s8 ; GFX9-NEXT: v_mul_lo_u32 v5, v3, s9
; GFX9-NEXT: v_add_u32_e32 v6, 1, v3 ; GFX9-NEXT: v_add_u32_e32 v6, 1, v3
; GFX9-NEXT: v_xor_b32_e32 v2, s2, v2 ; GFX9-NEXT: v_xor_b32_e32 v2, s2, v2
; GFX9-NEXT: v_subrev_u32_e32 v2, s2, v2 ; GFX9-NEXT: v_subrev_u32_e32 v2, s2, v2
; GFX9-NEXT: v_sub_u32_e32 v5, s4, v5 ; GFX9-NEXT: v_sub_u32_e32 v5, s5, v5
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; GFX9-NEXT: v_subrev_u32_e32 v6, s8, v5 ; GFX9-NEXT: v_subrev_u32_e32 v6, s9, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
; GFX9-NEXT: v_add_u32_e32 v6, 1, v3 ; GFX9-NEXT: v_add_u32_e32 v6, 1, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5
; GFX9-NEXT: s_xor_b32 s2, s3, s6 ; GFX9-NEXT: s_xor_b32 s2, s3, s8
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; GFX9-NEXT: v_xor_b32_e32 v3, s2, v3 ; GFX9-NEXT: v_xor_b32_e32 v3, s2, v3
; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v3 ; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v3
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%r = sdiv <4 x i32> %x, %y %r = sdiv <4 x i32> %x, %y
store <4 x i32> %r, <4 x i32> addrspace(1)* %out store <4 x i32> %r, <4 x i32> addrspace(1)* %out
ret void ret void
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; CHECK-NEXT: [[TMP151:%.*]] = sub i32 [[TMP150]], [[TMP117]] ; CHECK-NEXT: [[TMP151:%.*]] = sub i32 [[TMP150]], [[TMP117]]
; CHECK-NEXT: [[TMP152:%.*]] = insertelement <4 x i32> [[TMP114]], i32 [[TMP151]], i64 3 ; CHECK-NEXT: [[TMP152:%.*]] = insertelement <4 x i32> [[TMP114]], i32 [[TMP151]], i64 3
; CHECK-NEXT: store <4 x i32> [[TMP152]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16 ; CHECK-NEXT: store <4 x i32> [[TMP152]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: srem_v4i32: ; GFX6-LABEL: srem_v4i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
; GFX6-NEXT: s_mov_b32 s13, 0x4f7ffffe ; GFX6-NEXT: s_mov_b32 s14, 0x4f7ffffe
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_ashr_i32 s2, s8, 31 ; GFX6-NEXT: s_ashr_i32 s2, s8, 31
; GFX6-NEXT: s_add_i32 s8, s8, s2 ; GFX6-NEXT: s_add_i32 s8, s8, s2
; GFX6-NEXT: s_xor_b32 s12, s8, s2 ; GFX6-NEXT: s_xor_b32 s8, s8, s2
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX6-NEXT: s_ashr_i32 s8, s9, 31 ; GFX6-NEXT: s_ashr_i32 s12, s9, 31
; GFX6-NEXT: s_add_i32 s9, s9, s8 ; GFX6-NEXT: s_add_i32 s9, s9, s12
; GFX6-NEXT: s_xor_b32 s14, s9, s8 ; GFX6-NEXT: s_xor_b32 s9, s9, s12
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s14 ; GFX6-NEXT: s_sub_i32 s13, 0, s8
; GFX6-NEXT: s_sub_i32 s9, 0, s12 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX6-NEXT: s_ashr_i32 s8, s4, 31 ; GFX6-NEXT: s_ashr_i32 s12, s4, 31
; GFX6-NEXT: v_mul_f32_e32 v0, s13, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, s14, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: s_add_i32 s4, s4, s8 ; GFX6-NEXT: s_add_i32 s4, s4, s12
; GFX6-NEXT: s_xor_b32 s4, s4, s8 ; GFX6-NEXT: s_xor_b32 s4, s4, s12
; GFX6-NEXT: v_mul_lo_u32 v2, s9, v0 ; GFX6-NEXT: v_mul_lo_u32 v2, s13, v0
; GFX6-NEXT: v_mul_f32_e32 v1, s13, v1 ; GFX6-NEXT: v_mul_f32_e32 v1, s14, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: s_sub_i32 s9, 0, s14 ; GFX6-NEXT: s_sub_i32 s13, 0, s9
; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: s_mov_b32 s2, -1 ; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX6-NEXT: v_mul_lo_u32 v2, s9, v1 ; GFX6-NEXT: v_mul_lo_u32 v2, s13, v1
; GFX6-NEXT: s_ashr_i32 s9, s5, 31 ; GFX6-NEXT: s_ashr_i32 s13, s5, 31
; GFX6-NEXT: s_add_i32 s5, s5, s9 ; GFX6-NEXT: s_add_i32 s5, s5, s13
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s12 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s8
; GFX6-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GFX6-NEXT: s_xor_b32 s4, s5, s9 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s8, v0
; GFX6-NEXT: s_ashr_i32 s5, s10, 31 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; GFX6-NEXT: s_add_i32 s10, s10, s5
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s12, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
; GFX6-NEXT: s_xor_b32 s10, s10, s5
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: s_xor_b32 s4, s5, s13
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s10 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s8, v0
; GFX6-NEXT: s_ashr_i32 s5, s10, 31
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; GFX6-NEXT: s_add_i32 s8, s10, s5
; GFX6-NEXT: s_xor_b32 s5, s8, s5
; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s5
; GFX6-NEXT: v_mul_hi_u32 v1, s4, v1 ; GFX6-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s12, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s14
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, s8, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, s12, v0
; GFX6-NEXT: v_mul_f32_e32 v2, s13, v2 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s9
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0
; GFX6-NEXT: s_ashr_i32 s8, s11, 31
; GFX6-NEXT: v_mul_f32_e32 v2, s14, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s4, v1 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s4, v1
; GFX6-NEXT: s_sub_i32 s4, 0, s10 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s9, v1
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0 ; GFX6-NEXT: s_sub_i32 s4, 0, s5
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s14, v1 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s14, v1
; GFX6-NEXT: v_mul_lo_u32 v4, s4, v2 ; GFX6-NEXT: v_mul_lo_u32 v4, s4, v2
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s14, v1 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s9, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s14, v1 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_mul_hi_u32 v3, v2, v4 ; GFX6-NEXT: v_mul_hi_u32 v3, v2, v4
; GFX6-NEXT: s_add_i32 s9, s11, s8
; GFX6-NEXT: s_ashr_i32 s4, s6, 31 ; GFX6-NEXT: s_ashr_i32 s4, s6, 31
; GFX6-NEXT: s_add_i32 s5, s6, s4 ; GFX6-NEXT: s_xor_b32 s8, s9, s8
; GFX6-NEXT: s_ashr_i32 s6, s11, 31 ; GFX6-NEXT: s_add_i32 s6, s6, s4
; GFX6-NEXT: s_add_i32 s8, s11, s6
; GFX6-NEXT: s_xor_b32 s8, s8, s6
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s8 ; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s8
; GFX6-NEXT: s_xor_b32 s5, s5, s4 ; GFX6-NEXT: s_xor_b32 s6, s6, s4
; GFX6-NEXT: v_mul_hi_u32 v2, s5, v2 ; GFX6-NEXT: v_mul_hi_u32 v2, s6, v2
; GFX6-NEXT: v_xor_b32_e32 v1, s9, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, s13, v1
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s9, v1 ; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s13, v1
; GFX6-NEXT: v_mul_lo_u32 v2, v2, s10 ; GFX6-NEXT: v_mul_lo_u32 v2, v2, s5
; GFX6-NEXT: v_mul_f32_e32 v3, s13, v3 ; GFX6-NEXT: v_mul_f32_e32 v3, s14, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s5, v2 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s6, v2
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s10, v2 ; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v2 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s5, v2
; GFX6-NEXT: s_sub_i32 s5, 0, s8 ; GFX6-NEXT: s_sub_i32 s6, 0, s8
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s5, v3 ; GFX6-NEXT: v_mul_lo_u32 v4, s6, v3
; GFX6-NEXT: s_ashr_i32 s5, s7, 31 ; GFX6-NEXT: s_ashr_i32 s6, s7, 31
; GFX6-NEXT: s_add_i32 s6, s7, s5 ; GFX6-NEXT: s_add_i32 s7, s7, s6
; GFX6-NEXT: s_xor_b32 s6, s6, s5 ; GFX6-NEXT: s_xor_b32 s7, s7, s6
; GFX6-NEXT: v_mul_hi_u32 v4, v3, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s10, v2 ; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GFX6-NEXT: v_mul_hi_u32 v3, s6, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, s7, v3
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v2 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s5, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX6-NEXT: v_xor_b32_e32 v2, s4, v2 ; GFX6-NEXT: v_xor_b32_e32 v2, s4, v2
; GFX6-NEXT: v_mul_lo_u32 v3, v3, s8 ; GFX6-NEXT: v_mul_lo_u32 v3, v3, s8
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s4, v2 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s4, v2
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s6, v3 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s7, v3
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s8, v3 ; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s8, v3
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s8, v3 ; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s8, v3
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX6-NEXT: v_xor_b32_e32 v3, s5, v3 ; GFX6-NEXT: v_xor_b32_e32 v3, s6, v3
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s5, v3 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s6, v3
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: srem_v4i32: ; GFX9-LABEL: srem_v4i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX9-NEXT: s_mov_b32 s13, 0x4f7ffffe ; GFX9-NEXT: s_mov_b32 s13, 0x4f7ffffe
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GFX9-NEXT: v_subrev_u32_e32 v2, s2, v0 ; GFX9-NEXT: v_subrev_u32_e32 v2, s2, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v0 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
; GFX9-NEXT: s_ashr_i32 s2, s10, 31 ; GFX9-NEXT: s_ashr_i32 s2, s10, 31
; GFX9-NEXT: s_add_i32 s4, s10, s2 ; GFX9-NEXT: s_add_i32 s4, s10, s2
; GFX9-NEXT: s_xor_b32 s2, s4, s2 ; GFX9-NEXT: s_xor_b32 s2, s4, s2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s2
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s3 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s3
; GFX9-NEXT: s_sub_i32 s4, 0, s2
; GFX9-NEXT: v_xor_b32_e32 v0, s8, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s8, v0
; GFX9-NEXT: v_subrev_u32_e32 v0, s8, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1 ; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
; GFX9-NEXT: v_subrev_u32_e32 v3, s3, v1 ; GFX9-NEXT: v_subrev_u32_e32 v3, s3, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GFX9-NEXT: v_mul_f32_e32 v2, s13, v2 ; GFX9-NEXT: v_mul_f32_e32 v2, s13, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, s3, v1 ; GFX9-NEXT: v_subrev_u32_e32 v3, s3, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GFX9-NEXT: s_sub_i32 s3, 0, s2
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, s4, v2 ; GFX9-NEXT: v_mul_lo_u32 v3, s3, v2
; GFX9-NEXT: s_ashr_i32 s4, s11, 31 ; GFX9-NEXT: s_ashr_i32 s3, s11, 31
; GFX9-NEXT: s_add_i32 s5, s11, s4 ; GFX9-NEXT: s_add_i32 s4, s11, s3
; GFX9-NEXT: s_xor_b32 s4, s5, s4 ; GFX9-NEXT: s_xor_b32 s3, s4, s3
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s4 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s3
; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3
; GFX9-NEXT: s_ashr_i32 s3, s6, 31 ; GFX9-NEXT: s_ashr_i32 s4, s6, 31
; GFX9-NEXT: s_add_i32 s5, s6, s3 ; GFX9-NEXT: s_add_i32 s5, s6, s4
; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GFX9-NEXT: v_add_u32_e32 v2, v2, v3 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v3
; GFX9-NEXT: s_xor_b32 s5, s5, s3 ; GFX9-NEXT: s_xor_b32 s5, s5, s4
; GFX9-NEXT: v_mul_hi_u32 v2, s5, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, s5, v2
; GFX9-NEXT: v_mul_f32_e32 v3, s13, v5 ; GFX9-NEXT: v_mul_f32_e32 v3, s13, v5
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: s_sub_i32 s6, 0, s4 ; GFX9-NEXT: s_sub_i32 s6, 0, s3
; GFX9-NEXT: v_mul_lo_u32 v2, v2, s2 ; GFX9-NEXT: v_mul_lo_u32 v2, v2, s2
; GFX9-NEXT: v_xor_b32_e32 v1, s9, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s9, v1
; GFX9-NEXT: v_mul_lo_u32 v5, s6, v3 ; GFX9-NEXT: v_mul_lo_u32 v5, s6, v3
; GFX9-NEXT: v_subrev_u32_e32 v0, s8, v0 ; GFX9-NEXT: v_subrev_u32_e32 v1, s9, v1
; GFX9-NEXT: v_sub_u32_e32 v2, s5, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, s5, v2
; GFX9-NEXT: s_ashr_i32 s5, s7, 31 ; GFX9-NEXT: s_ashr_i32 s5, s7, 31
; GFX9-NEXT: v_mul_hi_u32 v5, v3, v5 ; GFX9-NEXT: v_mul_hi_u32 v5, v3, v5
; GFX9-NEXT: s_add_i32 s6, s7, s5 ; GFX9-NEXT: s_add_i32 s6, s7, s5
; GFX9-NEXT: s_xor_b32 s6, s6, s5 ; GFX9-NEXT: s_xor_b32 s6, s6, s5
; GFX9-NEXT: v_subrev_u32_e32 v6, s2, v2 ; GFX9-NEXT: v_subrev_u32_e32 v6, s2, v2
; GFX9-NEXT: v_add_u32_e32 v3, v3, v5 ; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
; GFX9-NEXT: v_mul_hi_u32 v3, s6, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, s6, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX9-NEXT: v_subrev_u32_e32 v5, s2, v2 ; GFX9-NEXT: v_subrev_u32_e32 v5, s2, v2
; GFX9-NEXT: v_mul_lo_u32 v3, v3, s4 ; GFX9-NEXT: v_mul_lo_u32 v3, v3, s3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX9-NEXT: v_xor_b32_e32 v2, s3, v2 ; GFX9-NEXT: v_xor_b32_e32 v2, s4, v2
; GFX9-NEXT: v_sub_u32_e32 v3, s6, v3 ; GFX9-NEXT: v_sub_u32_e32 v3, s6, v3
; GFX9-NEXT: v_subrev_u32_e32 v5, s4, v3 ; GFX9-NEXT: v_subrev_u32_e32 v5, s3, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX9-NEXT: v_subrev_u32_e32 v5, s4, v3 ; GFX9-NEXT: v_subrev_u32_e32 v5, s3, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX9-NEXT: v_xor_b32_e32 v3, s5, v3 ; GFX9-NEXT: v_xor_b32_e32 v3, s5, v3
; GFX9-NEXT: v_subrev_u32_e32 v1, s9, v1 ; GFX9-NEXT: v_subrev_u32_e32 v2, s4, v2
; GFX9-NEXT: v_subrev_u32_e32 v2, s3, v2
; GFX9-NEXT: v_subrev_u32_e32 v3, s5, v3 ; GFX9-NEXT: v_subrev_u32_e32 v3, s5, v3
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%r = srem <4 x i32> %x, %y %r = srem <4 x i32> %x, %y
store <4 x i32> %r, <4 x i32> addrspace(1)* %out store <4 x i32> %r, <4 x i32> addrspace(1)* %out
ret void ret void
} }
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; GFX9-NEXT: v_add_u32_e32 v5, s0, v6 ; GFX9-NEXT: v_add_u32_e32 v5, s0, v6
; GFX9-NEXT: v_cvt_f32_i32_e32 v6, v0 ; GFX9-NEXT: v_cvt_f32_i32_e32 v6, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v3 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v3
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 ; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v0
; GFX9-NEXT: v_or_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_or_b32_e32 v0, 1, v0
; GFX9-NEXT: v_mul_f32_e32 v1, v6, v7 ; GFX9-NEXT: v_mul_f32_e32 v1, v6, v7
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_i32_f32_e32 v7, v1 ; GFX9-NEXT: v_mad_f32 v6, -v1, v3, v6
; GFX9-NEXT: v_mad_f32 v1, -v1, v3, v6 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v6|, |v3|
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v3| ; GFX9-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
rampitecUnsubmitted
Not Done
ReplyInline Actions

This looks like a regression. A common one.

rampitec: This looks like a regression. A common one.
; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX9-NEXT: s_movk_i32 s0, 0x7fff ; GFX9-NEXT: s_movk_i32 s0, 0x7fff
; GFX9-NEXT: v_add_u32_e32 v0, v7, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v1, v0
; GFX9-NEXT: v_and_b32_e32 v3, s0, v4 ; GFX9-NEXT: v_and_b32_e32 v3, s0, v4
; GFX9-NEXT: v_and_b32_e32 v4, s0, v5 ; GFX9-NEXT: v_and_b32_e32 v4, s0, v5
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4 ; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0 ; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
; GFX9-NEXT: global_store_dword v2, v0, s[2:3] ; GFX9-NEXT: global_store_dword v2, v0, s[2:3]
; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1 ; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
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; GFX9-NEXT: v_bfe_i32 v6, v0, 0, 15 ; GFX9-NEXT: v_bfe_i32 v6, v0, 0, 15
; GFX9-NEXT: v_cvt_f32_i32_e32 v7, v6 ; GFX9-NEXT: v_cvt_f32_i32_e32 v7, v6
; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v5 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v5
; GFX9-NEXT: v_xor_b32_e32 v4, v6, v4 ; GFX9-NEXT: v_xor_b32_e32 v4, v6, v4
; GFX9-NEXT: v_ashrrev_i32_e32 v4, 30, v4 ; GFX9-NEXT: v_ashrrev_i32_e32 v4, 30, v4
; GFX9-NEXT: v_or_b32_e32 v4, 1, v4 ; GFX9-NEXT: v_or_b32_e32 v4, 1, v4
; GFX9-NEXT: v_mul_f32_e32 v6, v7, v8 ; GFX9-NEXT: v_mul_f32_e32 v6, v7, v8
; GFX9-NEXT: v_trunc_f32_e32 v6, v6 ; GFX9-NEXT: v_trunc_f32_e32 v6, v6
; GFX9-NEXT: v_cvt_i32_f32_e32 v8, v6 ; GFX9-NEXT: v_mad_f32 v7, -v6, v5, v7
; GFX9-NEXT: v_mad_f32 v6, -v6, v5, v7 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v7|, |v5|
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v6|, |v5| ; GFX9-NEXT: v_cvt_i32_f32_e32 v6, v6
; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, v3, s7 ; GFX9-NEXT: v_mul_lo_u32 v3, v3, s7
; GFX9-NEXT: v_add_u32_e32 v4, v8, v4 ; GFX9-NEXT: v_add_u32_e32 v4, v6, v4
; GFX9-NEXT: v_mul_lo_u32 v2, v2, s6 ; GFX9-NEXT: v_mul_lo_u32 v2, v2, s6
; GFX9-NEXT: v_mul_lo_u32 v1, v4, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, v4, v1
; GFX9-NEXT: v_sub_u32_e32 v3, s9, v3 ; GFX9-NEXT: v_sub_u32_e32 v3, s9, v3
; GFX9-NEXT: v_and_b32_e32 v3, s8, v3 ; GFX9-NEXT: v_and_b32_e32 v3, s8, v3
; GFX9-NEXT: v_sub_u32_e32 v2, s4, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, s4, v2
; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1 ; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
; GFX9-NEXT: v_and_b32_e32 v2, s8, v2 ; GFX9-NEXT: v_and_b32_e32 v2, s8, v2
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; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: udiv_v2i32_pow2_shl_denom: ; GFX9-LABEL: udiv_v2i32_pow2_shl_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-NEXT: s_movk_i32 s4, 0x1000 ; GFX9-NEXT: s_movk_i32 s4, 0x1000
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s7, s4, s2 ; GFX9-NEXT: s_lshl_b32 s5, s4, s3
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7 ; GFX9-NEXT: s_lshl_b32 s4, s4, s2
; GFX9-NEXT: s_lshl_b32 s6, s4, s3 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s4
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s6 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s5
; GFX9-NEXT: s_mov_b32 s2, 0x4f7ffffe ; GFX9-NEXT: s_mov_b32 s2, 0x4f7ffffe
; GFX9-NEXT: s_sub_i32 s3, 0, s5
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_sub_i32 s3, 0, s6
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX9-NEXT: v_mul_f32_e32 v0, s2, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, s2, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v1, s2, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, s2, v1
; GFX9-NEXT: s_sub_i32 s2, 0, s4
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_sub_i32 s2, 0, s7
; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v1, s3, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, s3, v1
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_mul_lo_u32 v3, v0, s7 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, s4
; GFX9-NEXT: v_add_u32_e32 v5, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
; GFX9-NEXT: v_mul_lo_u32 v4, v1, s6 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, s5
; GFX9-NEXT: v_add_u32_e32 v6, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v6, 1, v1
; GFX9-NEXT: v_sub_u32_e32 v3, s2, v3 ; GFX9-NEXT: v_sub_u32_e32 v3, s2, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX9-NEXT: v_subrev_u32_e32 v5, s7, v3 ; GFX9-NEXT: v_subrev_u32_e32 v5, s4, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX9-NEXT: v_sub_u32_e32 v4, s3, v4 ; GFX9-NEXT: v_sub_u32_e32 v4, s3, v4
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
; GFX9-NEXT: v_subrev_u32_e32 v3, s6, v4
; GFX9-NEXT: v_add_u32_e32 v5, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v4
; GFX9-NEXT: v_subrev_u32_e32 v3, s5, v4
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v3
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
%r = udiv <2 x i32> %x, %shl.y %r = udiv <2 x i32> %x, %shl.y
store <2 x i32> %r, <2 x i32> addrspace(1)* %out store <2 x i32> %r, <2 x i32> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @urem_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) { define amdgpu_kernel void @urem_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
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; CHECK-NEXT: [[TMP60:%.*]] = insertelement <2 x i32> [[TMP30]], i32 [[TMP59]], i64 1 ; CHECK-NEXT: [[TMP60:%.*]] = insertelement <2 x i32> [[TMP30]], i32 [[TMP59]], i64 1
; CHECK-NEXT: store <2 x i32> [[TMP60]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8 ; CHECK-NEXT: store <2 x i32> [[TMP60]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: urem_v2i32_pow2_shl_denom: ; GFX6-LABEL: urem_v2i32_pow2_shl_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
; GFX6-NEXT: s_movk_i32 s4, 0x1000 ; GFX6-NEXT: s_movk_i32 s4, 0x1000
; GFX6-NEXT: s_mov_b32 s5, 0x4f7ffffe
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b32 s8, s4, s2 ; GFX6-NEXT: s_lshl_b32 s2, s4, s2
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX6-NEXT: s_lshl_b32 s3, s4, s3 ; GFX6-NEXT: s_lshl_b32 s3, s4, s3
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s3 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s3
; GFX6-NEXT: s_mov_b32 s4, 0x4f7ffffe ; GFX6-NEXT: s_sub_i32 s4, 0, s2
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_sub_i32 s2, 0, s8
; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: v_mul_f32_e32 v0, s4, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, s5, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v1, s4, v1 ; GFX6-NEXT: v_mul_f32_e32 v1, s5, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_mul_lo_u32 v2, s4, v0
; GFX6-NEXT: s_sub_i32 s4, 0, s3
; GFX6-NEXT: v_mul_lo_u32 v3, s4, v1
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; GFX6-NEXT: v_mul_lo_u32 v2, s2, v0
; GFX6-NEXT: s_sub_i32 s2, 0, s3
; GFX6-NEXT: v_mul_lo_u32 v3, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1
; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1 ; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s8 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s3 ; GFX6-NEXT: v_mul_lo_u32 v1, v1, s3
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s8, v0 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v0 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s8, v0 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v0 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v1 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
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; GFX9-NEXT: s_lshl_b32 s4, s4, s2 ; GFX9-NEXT: s_lshl_b32 s4, s4, s2
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s4 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s4
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s5 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s5
; GFX9-NEXT: s_mov_b32 s2, 0x4f7ffffe ; GFX9-NEXT: s_mov_b32 s2, 0x4f7ffffe
; GFX9-NEXT: s_sub_i32 s3, 0, s5 ; GFX9-NEXT: s_sub_i32 s3, 0, s5
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v0, s2, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, s2, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v1, s2, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, s2, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_sub_i32 s2, 0, s4 ; GFX9-NEXT: s_sub_i32 s2, 0, s4
; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v1, s3, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, s3, v1
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s4 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, s4
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s5 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s5
; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0
; GFX9-NEXT: v_sub_u32_e32 v1, s3, v1
; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v0 ; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_sub_u32_e32 v1, s3, v1 ; GFX9-NEXT: v_subrev_u32_e32 v4, s5, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v0 ; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_subrev_u32_e32 v4, s5, v1 ; GFX9-NEXT: v_subrev_u32_e32 v4, s5, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, s5, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
%r = urem <2 x i32> %x, %shl.y %r = urem <2 x i32> %x, %shl.y
store <2 x i32> %r, <2 x i32> addrspace(1)* %out store <2 x i32> %r, <2 x i32> addrspace(1)* %out
ret void ret void
} }
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; CHECK-NEXT: [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]] ; CHECK-NEXT: [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = sdiv i32 [[X:%.*]], [[SHL_Y]] ; CHECK-NEXT: [[R:%.*]] = sdiv i32 [[X:%.*]], [[SHL_Y]]
; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4 ; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: sdiv_i32_pow2_shl_denom: ; GFX6-LABEL: sdiv_i32_pow2_shl_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb ; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b32 s3, 0x1000, s3 ; GFX6-NEXT: s_lshl_b32 s3, 0x1000, s3
; GFX6-NEXT: s_ashr_i32 s4, s3, 31 ; GFX6-NEXT: s_ashr_i32 s8, s3, 31
; GFX6-NEXT: s_add_i32 s3, s3, s4 ; GFX6-NEXT: s_add_i32 s3, s3, s8
; GFX6-NEXT: s_xor_b32 s7, s3, s4 ; GFX6-NEXT: s_xor_b32 s3, s3, s8
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s7 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX6-NEXT: s_sub_i32 s3, 0, s7 ; GFX6-NEXT: s_sub_i32 s4, 0, s3
; GFX6-NEXT: s_ashr_i32 s5, s2, 31
; GFX6-NEXT: s_add_i32 s2, s2, s5
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_xor_b32 s6, s2, s5
; GFX6-NEXT: s_xor_b32 s4, s5, s4
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0 ; GFX6-NEXT: v_mul_lo_u32 v1, s4, v0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX6-NEXT: s_ashr_i32 s0, s2, 31
; GFX6-NEXT: s_add_i32 s1, s2, s0
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: s_xor_b32 s1, s1, s0
; GFX6-NEXT: s_xor_b32 s2, s0, s8
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s6, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
; GFX6-NEXT: v_mul_lo_u32 v1, v0, s7 ; GFX6-NEXT: v_mul_lo_u32 v1, v0, s3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s6, v1
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s7, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1
; GFX6-NEXT: v_xor_b32_e32 v0, s4, v0 ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, s2, v0
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdiv_i32_pow2_shl_denom: ; GFX9-LABEL: sdiv_i32_pow2_shl_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s3, 0x1000, s3 ; GFX9-NEXT: s_lshl_b32 s3, 0x1000, s3
; GFX9-NEXT: s_ashr_i32 s4, s3, 31 ; GFX9-NEXT: s_ashr_i32 s4, s3, 31
; GFX9-NEXT: s_add_i32 s3, s3, s4 ; GFX9-NEXT: s_add_i32 s3, s3, s4
; GFX9-NEXT: s_xor_b32 s5, s3, s4 ; GFX9-NEXT: s_xor_b32 s3, s3, s4
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s5 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX9-NEXT: s_sub_i32 s3, 0, s5 ; GFX9-NEXT: s_sub_i32 s5, 0, s3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_lo_u32 v1, s3, v0 ; GFX9-NEXT: v_mul_lo_u32 v1, s5, v0
; GFX9-NEXT: s_ashr_i32 s3, s2, 31 ; GFX9-NEXT: s_ashr_i32 s5, s2, 31
; GFX9-NEXT: s_add_i32 s2, s2, s3 ; GFX9-NEXT: s_add_i32 s2, s2, s5
; GFX9-NEXT: s_xor_b32 s2, s2, s3 ; GFX9-NEXT: s_xor_b32 s2, s2, s5
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX9-NEXT: v_mul_lo_u32 v1, v0, s5 ; GFX9-NEXT: v_mul_lo_u32 v1, v0, s3
; GFX9-NEXT: v_add_u32_e32 v3, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
; GFX9-NEXT: v_sub_u32_e32 v1, s2, v1 ; GFX9-NEXT: v_sub_u32_e32 v1, s2, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, s5, v1 ; GFX9-NEXT: v_subrev_u32_e32 v3, s3, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_add_u32_e32 v4, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX9-NEXT: s_xor_b32 s2, s3, s4 ; GFX9-NEXT: s_xor_b32 s2, s5, s4
; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
; GFX9-NEXT: v_subrev_u32_e32 v0, s2, v0 ; GFX9-NEXT: v_subrev_u32_e32 v0, s2, v0
; GFX9-NEXT: global_store_dword v2, v0, s[0:1] ; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%shl.y = shl i32 4096, %y %shl.y = shl i32 4096, %y
%r = sdiv i32 %x, %shl.y %r = sdiv i32 %x, %shl.y
store i32 %r, i32 addrspace(1)* %out store i32 %r, i32 addrspace(1)* %out
ret void ret void
▲ Show 20 Lines • Show All 196 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[TMP82:%.*]] = insertelement <2 x i32> [[TMP41]], i32 [[TMP81]], i64 1 ; CHECK-NEXT: [[TMP82:%.*]] = insertelement <2 x i32> [[TMP41]], i32 [[TMP81]], i64 1
; CHECK-NEXT: store <2 x i32> [[TMP82]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8 ; CHECK-NEXT: store <2 x i32> [[TMP82]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: sdiv_v2i32_pow2_shl_denom: ; GFX6-LABEL: sdiv_v2i32_pow2_shl_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
; GFX6-NEXT: s_movk_i32 s10, 0x1000 ; GFX6-NEXT: s_movk_i32 s10, 0x1000
; GFX6-NEXT: s_mov_b32 s13, 0x4f7ffffe ; GFX6-NEXT: s_mov_b32 s12, 0x4f7ffffe
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb ; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b32 s2, s10, s2 ; GFX6-NEXT: s_lshl_b32 s2, s10, s2
; GFX6-NEXT: s_ashr_i32 s11, s2, 31 ; GFX6-NEXT: s_ashr_i32 s11, s2, 31
; GFX6-NEXT: s_add_i32 s2, s2, s11 ; GFX6-NEXT: s_add_i32 s2, s2, s11
; GFX6-NEXT: s_xor_b32 s12, s2, s11 ; GFX6-NEXT: s_xor_b32 s2, s2, s11
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX6-NEXT: s_lshl_b32 s0, s10, s3 ; GFX6-NEXT: s_lshl_b32 s0, s10, s3
; GFX6-NEXT: s_sub_i32 s3, 0, s12 ; GFX6-NEXT: s_sub_i32 s10, 0, s2
; GFX6-NEXT: s_ashr_i32 s2, s0, 31 ; GFX6-NEXT: s_ashr_i32 s3, s0, 31
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_add_i32 s0, s0, s2 ; GFX6-NEXT: s_add_i32 s0, s0, s3
; GFX6-NEXT: s_xor_b32 s10, s0, s2
; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s10
; GFX6-NEXT: v_mul_f32_e32 v0, s13, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_ashr_i32 s1, s8, 31 ; GFX6-NEXT: s_ashr_i32 s1, s8, 31
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_mul_f32_e32 v0, s12, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_lo_u32 v1, s10, v0
; GFX6-NEXT: s_xor_b32 s10, s0, s3
; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s10
; GFX6-NEXT: s_add_i32 s0, s8, s1 ; GFX6-NEXT: s_add_i32 s0, s8, s1
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: s_xor_b32 s0, s0, s1 ; GFX6-NEXT: s_xor_b32 s0, s0, s1
; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX6-NEXT: s_xor_b32 s3, s1, s11 ; GFX6-NEXT: s_xor_b32 s8, s1, s11
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX6-NEXT: v_mul_f32_e32 v1, s13, v2 ; GFX6-NEXT: v_mul_f32_e32 v1, s12, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_mul_lo_u32 v2, v0, s12 ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s0, v2 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s0, v2
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v2 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v2
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s12, v2 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s2, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
; GFX6-NEXT: s_sub_i32 s0, 0, s10 ; GFX6-NEXT: s_sub_i32 s0, 0, s10
; GFX6-NEXT: v_mul_lo_u32 v3, s0, v1 ; GFX6-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX6-NEXT: s_ashr_i32 s0, s9, 31 ; GFX6-NEXT: s_ashr_i32 s0, s9, 31
; GFX6-NEXT: s_add_i32 s1, s9, s0 ; GFX6-NEXT: s_add_i32 s1, s9, s0
; GFX6-NEXT: s_xor_b32 s1, s1, s0 ; GFX6-NEXT: s_xor_b32 s1, s1, s0
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0
; GFX6-NEXT: s_xor_b32 s2, s0, s2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1
; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1 ; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v2 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, s3, v0 ; GFX6-NEXT: s_xor_b32 s2, s0, s3
; GFX6-NEXT: v_mul_lo_u32 v2, v1, s10 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s10
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, s8, v0
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s1, v2 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s1, v2
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v2 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v2
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s10, v2 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s10, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v2 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_xor_b32_e32 v1, s2, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, s2, v1
; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s2, v1 ; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s2, v1
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdiv_v2i32_pow2_shl_denom: ; GFX9-LABEL: sdiv_v2i32_pow2_shl_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-NEXT: s_movk_i32 s8, 0x1000 ; GFX9-NEXT: s_movk_i32 s8, 0x1000
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x2c
; GFX9-NEXT: s_mov_b32 s11, 0x4f7ffffe ; GFX9-NEXT: s_mov_b32 s10, 0x4f7ffffe
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s2, s8, s2 ; GFX9-NEXT: s_lshl_b32 s2, s8, s2
; GFX9-NEXT: s_ashr_i32 s9, s2, 31 ; GFX9-NEXT: s_ashr_i32 s9, s2, 31
; GFX9-NEXT: s_add_i32 s2, s2, s9 ; GFX9-NEXT: s_add_i32 s2, s2, s9
; GFX9-NEXT: s_xor_b32 s10, s2, s9 ; GFX9-NEXT: s_xor_b32 s2, s2, s9
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s10 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX9-NEXT: s_lshl_b32 s0, s8, s3 ; GFX9-NEXT: s_lshl_b32 s0, s8, s3
; GFX9-NEXT: s_ashr_i32 s1, s0, 31 ; GFX9-NEXT: s_ashr_i32 s1, s0, 31
; GFX9-NEXT: s_add_i32 s0, s0, s1 ; GFX9-NEXT: s_add_i32 s0, s0, s1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_xor_b32 s8, s0, s1 ; GFX9-NEXT: s_xor_b32 s0, s0, s1
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s0
; GFX9-NEXT: s_sub_i32 s0, 0, s10 ; GFX9-NEXT: s_sub_i32 s3, 0, s2
; GFX9-NEXT: v_mul_f32_e32 v0, s11, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, s10, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: s_sub_i32 s3, 0, s8 ; GFX9-NEXT: s_sub_i32 s8, 0, s0
; GFX9-NEXT: v_mul_lo_u32 v3, s0, v0 ; GFX9-NEXT: v_mul_lo_u32 v3, s3, v0
; GFX9-NEXT: v_mul_f32_e32 v1, s11, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, s10, v1
; GFX9-NEXT: s_ashr_i32 s0, s6, 31 ; GFX9-NEXT: s_ashr_i32 s3, s6, 31
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3
; GFX9-NEXT: s_add_i32 s2, s6, s0 ; GFX9-NEXT: s_add_i32 s6, s6, s3
; GFX9-NEXT: s_xor_b32 s2, s2, s0 ; GFX9-NEXT: s_xor_b32 s6, s6, s3
; GFX9-NEXT: s_xor_b32 s0, s0, s9 ; GFX9-NEXT: s_xor_b32 s3, s3, s9
; GFX9-NEXT: v_add_u32_e32 v0, v0, v3 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s6, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s8, v1
; GFX9-NEXT: s_ashr_i32 s3, s7, 31 ; GFX9-NEXT: s_ashr_i32 s8, s7, 31
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s10 ; GFX9-NEXT: s_xor_b32 s1, s8, s1
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s2
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_u32_e32 v5, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
; GFX9-NEXT: v_sub_u32_e32 v4, s2, v4 ; GFX9-NEXT: v_sub_u32_e32 v4, s6, v4
; GFX9-NEXT: s_add_i32 s2, s7, s3 ; GFX9-NEXT: s_add_i32 s6, s7, s8
; GFX9-NEXT: s_xor_b32 s2, s2, s3 ; GFX9-NEXT: s_xor_b32 s6, s6, s8
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v4
; GFX9-NEXT: v_mul_hi_u32 v1, s2, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, s6, v1
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX9-NEXT: v_subrev_u32_e32 v5, s10, v4 ; GFX9-NEXT: v_subrev_u32_e32 v5, s2, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v4
; GFX9-NEXT: v_add_u32_e32 v3, 1, v0 ; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, v1, s8 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, s0
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s3, v0
; GFX9-NEXT: v_subrev_u32_e32 v0, s0, v0 ; GFX9-NEXT: v_subrev_u32_e32 v0, s3, v0
; GFX9-NEXT: v_sub_u32_e32 v3, s2, v3 ; GFX9-NEXT: v_sub_u32_e32 v3, s6, v3
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v3
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_subrev_u32_e32 v4, s8, v3 ; GFX9-NEXT: v_subrev_u32_e32 v4, s0, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 ; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v3
; GFX9-NEXT: s_xor_b32 s0, s3, s1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_xor_b32_e32 v1, s0, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX9-NEXT: v_subrev_u32_e32 v1, s0, v1 ; GFX9-NEXT: v_subrev_u32_e32 v1, s1, v1
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
%r = sdiv <2 x i32> %x, %shl.y %r = sdiv <2 x i32> %x, %shl.y
store <2 x i32> %r, <2 x i32> addrspace(1)* %out store <2 x i32> %r, <2 x i32> addrspace(1)* %out
ret void ret void
} }
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; GFX6-LABEL: srem_i32_pow2_shl_denom: ; GFX6-LABEL: srem_i32_pow2_shl_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb ; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b32 s3, 0x1000, s3 ; GFX6-NEXT: s_lshl_b32 s3, 0x1000, s3
; GFX6-NEXT: s_ashr_i32 s4, s3, 31 ; GFX6-NEXT: s_ashr_i32 s4, s3, 31
; GFX6-NEXT: s_add_i32 s3, s3, s4 ; GFX6-NEXT: s_add_i32 s3, s3, s4
; GFX6-NEXT: s_xor_b32 s6, s3, s4 ; GFX6-NEXT: s_xor_b32 s4, s3, s4
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s4
; GFX6-NEXT: s_sub_i32 s3, 0, s6 ; GFX6-NEXT: s_sub_i32 s3, 0, s4
; GFX6-NEXT: s_ashr_i32 s4, s2, 31 ; GFX6-NEXT: s_ashr_i32 s5, s2, 31
; GFX6-NEXT: s_add_i32 s2, s2, s4 ; GFX6-NEXT: s_add_i32 s2, s2, s5
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_xor_b32 s5, s2, s4 ; GFX6-NEXT: s_xor_b32 s6, s2, s5
; GFX6-NEXT: s_mov_b32 s2, -1 ; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0 ; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s6, v0
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s4
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0 ; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0 ; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, s4, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, s5, v0
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s5, v0
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: srem_i32_pow2_shl_denom: ; GFX9-LABEL: srem_i32_pow2_shl_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: s_nop 0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
▲ Show 20 Lines • Show All 180 Lines • ▼ Show 20 Lines
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
; GFX6-NEXT: s_movk_i32 s6, 0x1000 ; GFX6-NEXT: s_movk_i32 s6, 0x1000
; GFX6-NEXT: s_mov_b32 s10, 0x4f7ffffe ; GFX6-NEXT: s_mov_b32 s10, 0x4f7ffffe
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b32 s2, s6, s2 ; GFX6-NEXT: s_lshl_b32 s2, s6, s2
; GFX6-NEXT: s_ashr_i32 s4, s2, 31 ; GFX6-NEXT: s_ashr_i32 s4, s2, 31
; GFX6-NEXT: s_add_i32 s2, s2, s4 ; GFX6-NEXT: s_add_i32 s2, s2, s4
; GFX6-NEXT: s_xor_b32 s9, s2, s4 ; GFX6-NEXT: s_xor_b32 s2, s2, s4
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX6-NEXT: s_lshl_b32 s2, s6, s3 ; GFX6-NEXT: s_lshl_b32 s3, s6, s3
; GFX6-NEXT: s_ashr_i32 s6, s2, 31 ; GFX6-NEXT: s_ashr_i32 s6, s3, 31
; GFX6-NEXT: s_add_i32 s2, s2, s6 ; GFX6-NEXT: s_add_i32 s3, s3, s6
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_sub_i32 s8, 0, s9 ; GFX6-NEXT: s_xor_b32 s3, s3, s6
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_sub_i32 s9, 0, s2
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb ; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s3
; GFX6-NEXT: v_mul_f32_e32 v0, s10, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, s10, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX6-NEXT: s_ashr_i32 s3, s0, 31 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; GFX6-NEXT: s_add_i32 s0, s0, s3
; GFX6-NEXT: v_mul_lo_u32 v1, s8, v0
; GFX6-NEXT: s_xor_b32 s8, s2, s6
; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s8
; GFX6-NEXT: s_xor_b32 s0, s0, s3
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: s_sub_i32 s2, 0, s8
; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_mul_lo_u32 v1, s9, v0
; GFX6-NEXT: s_sub_i32 s9, 0, s3
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_ashr_i32 s8, s0, 31
; GFX6-NEXT: s_add_i32 s0, s0, s8
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: s_xor_b32 s0, s0, s8
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX6-NEXT: v_mul_f32_e32 v1, s10, v2 ; GFX6-NEXT: v_mul_f32_e32 v1, s10, v2
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s9 ; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1 ; GFX6-NEXT: v_mul_lo_u32 v2, s9, v1
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2
; GFX6-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: s_ashr_i32 s0, s1, 31 ; GFX6-NEXT: s_ashr_i32 s0, s1, 31
; GFX6-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s2, v0
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s9, v0 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v0
; GFX6-NEXT: s_add_i32 s1, s1, s0 ; GFX6-NEXT: s_add_i32 s1, s1, s0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: s_xor_b32 s1, s1, s0 ; GFX6-NEXT: s_xor_b32 s1, s1, s0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1 ; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s9, v0 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s2, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v0 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s8 ; GFX6-NEXT: v_mul_lo_u32 v1, v1, s3
; GFX6-NEXT: v_xor_b32_e32 v0, s3, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, s8, v0
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v1 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s8, v1 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v1 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s8, v1 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v1 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_xor_b32_e32 v1, s0, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, s0, v1
; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s0, v1 ; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: srem_v2i32_pow2_shl_denom: ; GFX9-LABEL: srem_v2i32_pow2_shl_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x34
; GFX9-NEXT: s_movk_i32 s8, 0x1000 ; GFX9-NEXT: s_movk_i32 s8, 0x1000
; GFX9-NEXT: s_mov_b32 s9, 0x4f7ffffe ; GFX9-NEXT: s_mov_b32 s9, 0x4f7ffffe
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s0, s8, s6 ; GFX9-NEXT: s_lshl_b32 s0, s8, s6
; GFX9-NEXT: s_ashr_i32 s1, s0, 31 ; GFX9-NEXT: s_ashr_i32 s1, s0, 31
; GFX9-NEXT: s_add_i32 s0, s0, s1 ; GFX9-NEXT: s_add_i32 s0, s0, s1
; GFX9-NEXT: s_xor_b32 s0, s0, s1 ; GFX9-NEXT: s_xor_b32 s0, s0, s1
; GFX9-NEXT: s_lshl_b32 s1, s8, s7
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s0 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s0
; GFX9-NEXT: s_lshl_b32 s1, s8, s7
; GFX9-NEXT: s_ashr_i32 s6, s1, 31 ; GFX9-NEXT: s_ashr_i32 s6, s1, 31
; GFX9-NEXT: s_add_i32 s1, s1, s6 ; GFX9-NEXT: s_add_i32 s1, s1, s6
; GFX9-NEXT: s_xor_b32 s1, s1, s6 ; GFX9-NEXT: s_xor_b32 s1, s1, s6
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s1
; GFX9-NEXT: s_sub_i32 s7, 0, s0 ; GFX9-NEXT: s_sub_i32 s7, 0, s0
; GFX9-NEXT: s_ashr_i32 s6, s4, 31 ; GFX9-NEXT: s_ashr_i32 s6, s4, 31
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v0, s9, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, s9, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_add_i32 s4, s4, s6 ; GFX9-NEXT: s_add_i32 s4, s4, s6
; GFX9-NEXT: s_xor_b32 s4, s4, s6
; GFX9-NEXT: v_mul_f32_e32 v1, s9, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, s9, v1
; GFX9-NEXT: v_mul_lo_u32 v3, s7, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mul_lo_u32 v2, s7, v0
; GFX9-NEXT: s_sub_i32 s7, 0, s1 ; GFX9-NEXT: s_sub_i32 s7, 0, s1
; GFX9-NEXT: s_xor_b32 s4, s4, s6 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3
; GFX9-NEXT: v_mul_lo_u32 v3, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v4, s7, v1
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: s_ashr_i32 s7, s5, 31 ; GFX9-NEXT: s_ashr_i32 s7, s5, 31
; GFX9-NEXT: s_add_i32 s5, s5, s7 ; GFX9-NEXT: s_add_i32 s5, s5, s7
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v4
; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX9-NEXT: s_xor_b32 s5, s5, s7 ; GFX9-NEXT: s_xor_b32 s5, s5, s7
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s0 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, s0
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s1 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s1
; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
; GFX9-NEXT: v_subrev_u32_e32 v3, s0, v0 ; GFX9-NEXT: v_subrev_u32_e32 v3, s0, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v0 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_subrev_u32_e32 v3, s0, v0 ; GFX9-NEXT: v_subrev_u32_e32 v3, s0, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v0 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v0
; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1 ; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_lo_u32 v3, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2
; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v4, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v4, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v3 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v3
; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: s_movk_i32 s4, 0x11e ; GFX6-NEXT: s_mov_b32 s4, 0x976a7376
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
; GFX6-NEXT: s_mov_b32 s10, -1 ; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 ; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2
; GFX6-NEXT: v_mul_hi_u32 v5, v0, s3 ; GFX6-NEXT: v_mul_hi_u32 v5, v0, s3
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
; GFX6-NEXT: v_mul_lo_u32 v6, v2, s3 ; GFX6-NEXT: v_mul_lo_u32 v6, v2, s3
; GFX6-NEXT: s_mov_b32 s2, 0x976a7377 ; GFX6-NEXT: s_movk_i32 s2, 0x11f
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_mul_lo_u32 v5, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v5, v0, s3
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_mul_lo_u32 v6, v0, v4 ; GFX6-NEXT: v_mul_lo_u32 v6, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v10, v0, v4 ; GFX6-NEXT: v_mul_hi_u32 v10, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v9, v0, v5 ; GFX6-NEXT: v_mul_hi_u32 v9, v0, v5
; GFX6-NEXT: v_mul_hi_u32 v11, v2, v4 ; GFX6-NEXT: v_mul_hi_u32 v11, v2, v4
; GFX6-NEXT: s_movk_i32 s3, 0x11f ; GFX6-NEXT: s_mov_b32 s3, 0x976a7377
; GFX6-NEXT: s_mov_b32 s9, s5 ; GFX6-NEXT: s_mov_b32 s9, s5
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc ; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v10, v2, v5 ; GFX6-NEXT: v_mul_lo_u32 v10, v2, v5
; GFX6-NEXT: v_mul_hi_u32 v5, v2, v5 ; GFX6-NEXT: v_mul_hi_u32 v5, v2, v5
; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4 ; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v10 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v10
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc
Show All 13 Lines
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2
; GFX6-NEXT: v_mul_hi_u32 v3, v0, s2 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s3
; GFX6-NEXT: v_mul_lo_u32 v4, v1, s2 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s3
; GFX6-NEXT: v_mov_b32_e32 v5, s3 ; GFX6-NEXT: v_mov_b32_e32 v5, s2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_lo_u32 v3, v0, s2 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s7, v2 ; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s7, v2
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s6, v3 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s6, v3
; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc ; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s2, v3 ; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s3, v3
; GFX6-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] ; GFX6-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s4, v4 ; GFX6-NEXT: s_movk_i32 s3, 0x11e
; GFX6-NEXT: s_mov_b32 s2, 0x976a7376 ; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s3, v4
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s2, v5 ; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s4, v5
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s2, v4
; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
; GFX6-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 ; GFX6-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0
; GFX6-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 ; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0
; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GFX6-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1]
; GFX6-NEXT: v_mov_b32_e32 v6, s7 ; GFX6-NEXT: v_mov_b32_e32 v6, s7
; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc ; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc
; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s4, v2 ; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s3, v2
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s2, v3 ; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s4, v3
; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s3, v2 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s2, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: udiv_i64_oddk_denom: ; GFX9-LABEL: udiv_i64_oddk_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f176a73 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f176a73
; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000
; GFX9-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0 ; GFX9-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_movk_i32 s4, 0xfee0 ; GFX9-NEXT: s_movk_i32 s4, 0xfee0
; GFX9-NEXT: s_mov_b32 s5, 0x68958c89 ; GFX9-NEXT: s_mov_b32 s5, 0x68958c89
; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_movk_i32 s8, 0x11f ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: s_mov_b32 s9, 0x976a7376
; GFX9-NEXT: v_mul_lo_u32 v2, v0, s4 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, s4
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s5 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s5
; GFX9-NEXT: v_mul_lo_u32 v5, v1, s5 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, s5
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s5 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, s5
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_add_u32_e32 v2, v2, v5 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2
; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, v6
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4 ; GFX9-NEXT: v_mul_lo_u32 v7, v1, v6
; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v6, v1, v6
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v6, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4
; GFX9-NEXT: v_mul_hi_u32 v7, v0, s5 ; GFX9-NEXT: v_mul_hi_u32 v6, v0, s5
; GFX9-NEXT: v_mul_lo_u32 v8, v2, s5 ; GFX9-NEXT: v_mul_lo_u32 v7, v2, s5
; GFX9-NEXT: v_mul_lo_u32 v9, v0, s5 ; GFX9-NEXT: v_mul_lo_u32 v9, v0, s5
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: v_add_u32_e32 v4, v7, v4 ; GFX9-NEXT: v_add_u32_e32 v4, v6, v4
; GFX9-NEXT: v_add_u32_e32 v4, v4, v8 ; GFX9-NEXT: v_add_u32_e32 v4, v4, v7
; GFX9-NEXT: v_mul_lo_u32 v7, v0, v4 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v9 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v9
; GFX9-NEXT: v_mul_hi_u32 v10, v0, v4 ; GFX9-NEXT: v_mul_hi_u32 v10, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v11, v2, v4 ; GFX9-NEXT: v_mul_hi_u32 v11, v2, v4
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v8, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v10, v2, v9 ; GFX9-NEXT: v_mul_lo_u32 v10, v2, v9
; GFX9-NEXT: v_mul_hi_u32 v9, v2, v9 ; GFX9-NEXT: v_mul_hi_u32 v9, v2, v9
; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4 ; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v10 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v10
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v8, v9, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v9, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v11, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v11, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v7, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v6, v2
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0
; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX9-NEXT: s_mov_b32 s2, 0x976a7377 ; GFX9-NEXT: s_movk_i32 s2, 0x11f
; GFX9-NEXT: s_mov_b32 s3, 0x976a7377
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, s2
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s2 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s3
; GFX9-NEXT: v_mul_lo_u32 v4, v1, s2 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, s3
; GFX9-NEXT: v_mov_b32_e32 v5, s8 ; GFX9-NEXT: v_mov_b32_e32 v6, s2
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_mul_lo_u32 v3, v0, s2 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, s3
; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
; GFX9-NEXT: v_sub_u32_e32 v4, s7, v2 ; GFX9-NEXT: v_sub_u32_e32 v4, s7, v2
; GFX9-NEXT: v_sub_co_u32_e64 v3, s[0:1], s6, v3 ; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, s6, v3
; GFX9-NEXT: v_subb_co_u32_e64 v4, vcc, v4, v5, s[0:1] ; GFX9-NEXT: v_subb_co_u32_e64 v4, s[0:1], v4, v6, vcc
; GFX9-NEXT: v_subrev_co_u32_e32 v5, vcc, s2, v3 ; GFX9-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s3, v3
; GFX9-NEXT: v_subbrev_co_u32_e32 v4, vcc, 0, v4, vcc ; GFX9-NEXT: v_subbrev_co_u32_e64 v4, s[0:1], 0, v4, s[0:1]
; GFX9-NEXT: s_movk_i32 s6, 0x11e ; GFX9-NEXT: s_movk_i32 s3, 0x11e
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s6, v4 ; GFX9-NEXT: v_cmp_lt_u32_e64 s[0:1], s3, v4
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: s_mov_b32 s6, 0x976a7376
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s9, v5 ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX9-NEXT: v_cmp_lt_u32_e64 s[0:1], s6, v6
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s8, v4 ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v4, v7, v5, vcc ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s2, v4
; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, 2, v0 ; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v6, s[0:1]
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc ; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], 2, v0
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 1, v0 ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v1, s[0:1]
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc ; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 1, v0
; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v4 ; GFX9-NEXT: v_addc_co_u32_e64 v9, s[0:1], 0, v1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v4, v9, v7, s[2:3] ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GFX9-NEXT: v_cndmask_b32_e64 v4, v9, v7, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v7, s7 ; GFX9-NEXT: v_mov_b32_e32 v7, s7
; GFX9-NEXT: v_subb_co_u32_e64 v2, vcc, v7, v2, s[0:1] ; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v7, v2, vcc
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s6, v2 ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v2
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s9, v3 ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s6, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s8, v2 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s2, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, v5, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, v6, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[4:5] ; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[4:5]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%r = udiv i64 %x, 1235195949943 %r = udiv i64 %x, 1235195949943
store i64 %r, i64 addrspace(1)* %out store i64 %r, i64 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @udiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @udiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
; CHECK-LABEL: @udiv_i64_pow2k_denom( ; CHECK-LABEL: @udiv_i64_pow2k_denom(
▲ Show 20 Lines • Show All 128 Lines • ▼ Show 20 Lines
; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16 ; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: udiv_v2i64_mixed_pow2k_denom: ; GFX6-LABEL: udiv_v2i64_mixed_pow2k_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f800000 ; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f800000
; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000 ; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000
; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_movk_i32 s6, 0xf001 ; GFX6-NEXT: s_movk_i32 s2, 0xf001
; GFX6-NEXT: v_mov_b32_e32 v8, 0
; GFX6-NEXT: v_mov_b32_e32 v7, 0 ; GFX6-NEXT: v_mov_b32_e32 v7, 0
; GFX6-NEXT: v_mov_b32_e32 v2, 0
; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
; GFX6-NEXT: s_movk_i32 s0, 0xfff
; GFX6-NEXT: v_mul_hi_u32 v3, v0, s6
; GFX6-NEXT: v_mul_lo_u32 v5, v1, s6
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s6
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, v0, v3 ; GFX6-NEXT: v_mul_hi_u32 v2, v0, s2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v5, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, s2
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v4 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v4
; GFX6-NEXT: v_mul_lo_u32 v5, v0, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v8, v0, v3 ; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX6-NEXT: v_mul_hi_u32 v9, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
; GFX6-NEXT: v_mul_lo_u32 v8, v1, v4
; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v2, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GFX6-NEXT: v_add_i32_e64 v0, s[2:3], v0, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
; GFX6-NEXT: v_mul_hi_u32 v5, v0, s6
; GFX6-NEXT: v_addc_u32_e64 v3, vcc, v1, v4, s[2:3]
; GFX6-NEXT: v_mul_lo_u32 v6, v3, s6
; GFX6-NEXT: v_mul_lo_u32 v8, v0, s6
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, v0, v5
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GFX6-NEXT: v_mul_lo_u32 v6, v0, v5 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; GFX6-NEXT: v_mul_hi_u32 v9, v0, v8 ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GFX6-NEXT: v_mul_hi_u32 v10, v0, v5 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_hi_u32 v11, v3, v5 ; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v7, v10, vcc ; GFX6-NEXT: v_mul_hi_u32 v4, v0, s2
; GFX6-NEXT: v_mul_lo_u32 v10, v3, v8 ; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
; GFX6-NEXT: v_mul_hi_u32 v8, v3, v8 ; GFX6-NEXT: v_mul_lo_u32 v5, v2, s2
; GFX6-NEXT: v_mul_lo_u32 v3, v3, v5 ; GFX6-NEXT: v_mul_lo_u32 v6, v0, s2
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v10 ; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v9, v8, vcc
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v11, v2, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mul_lo_u32 v3, s10, v1 ; GFX6-NEXT: s_lshr_b64 s[2:3], s[8:9], 12
; GFX6-NEXT: v_mul_hi_u32 v4, s10, v0 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GFX6-NEXT: v_mul_hi_u32 v5, s10, v1 ; GFX6-NEXT: v_mul_lo_u32 v5, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v6, s11, v1 ; GFX6-NEXT: v_mul_hi_u32 v9, v0, v6
; GFX6-NEXT: v_mul_hi_u32 v10, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v11, v2, v4
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v9, v5
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v10, v2, v6
; GFX6-NEXT: v_mul_hi_u32 v6, v2, v6
; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v10
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, s10, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s10, v0
; GFX6-NEXT: v_mul_hi_u32 v4, s10, v1
; GFX6-NEXT: v_mul_hi_u32 v5, s11, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s11, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s11, v1
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, s11, v0 ; GFX6-NEXT: v_mul_lo_u32 v4, s11, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s11, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s11, v0
; GFX6-NEXT: s_lshr_b64 s[2:3], s[8:9], 12 ; GFX6-NEXT: s_movk_i32 s0, 0xfff
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v6, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v7, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v1, s0 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s0
; GFX6-NEXT: v_mul_hi_u32 v3, v0, s0 ; GFX6-NEXT: v_mul_hi_u32 v5, v0, s0
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 2, v0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_mul_lo_u32 v8, v0, s0
; GFX6-NEXT: v_mov_b32_e32 v3, s11 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s10, v4 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v0
; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s0, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc ; GFX6-NEXT: v_mov_b32_e32 v5, s11
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s10, v8
; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v5, v4, vcc
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s0, v8
; GFX6-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
; GFX6-NEXT: s_movk_i32 s0, 0xffe ; GFX6-NEXT: s_movk_i32 s0, 0xffe
; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v3 ; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v5
; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
; GFX6-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v5, vcc, 2, v0 ; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v8
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX6-NEXT: v_add_i32_e32 v7, vcc, 1, v0 ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v4 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v4, -1, v5, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX6-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
; GFX6-NEXT: v_cndmask_b32_e64 v3, v1, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v3, v1, v3, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1]
; GFX6-NEXT: v_mov_b32_e32 v0, s2 ; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s3 ; GFX6-NEXT: v_mov_b32_e32 v1, s3
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: udiv_v2i64_mixed_pow2k_denom: ; GFX9-LABEL: udiv_v2i64_mixed_pow2k_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f800000 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f800000
; GFX9-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000 ; GFX9-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000
; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_movk_i32 s4, 0xf001 ; GFX9-NEXT: s_movk_i32 s4, 0xf001
; GFX9-NEXT: v_mov_b32_e32 v7, 0 ; GFX9-NEXT: v_mov_b32_e32 v7, 0
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_movk_i32 s8, 0xfff
; GFX9-NEXT: v_mul_hi_u32 v2, v0, s4 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, s4
; GFX9-NEXT: v_mul_lo_u32 v4, v1, s4 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, s4
; GFX9-NEXT: v_mul_lo_u32 v3, v0, s4 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, s4
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0
; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
; GFX9-NEXT: v_mul_hi_u32 v6, v0, v3 ; GFX9-NEXT: v_mul_hi_u32 v6, v0, v3
; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v6, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v6, v4
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v8, v1, v3 ; GFX9-NEXT: v_mul_lo_u32 v8, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_hi_u32 v4, v0, s4 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, s4
; GFX9-NEXT: v_mul_lo_u32 v6, v2, s4 ; GFX9-NEXT: v_mul_lo_u32 v6, v2, s4
; GFX9-NEXT: v_mul_lo_u32 v8, v0, s4 ; GFX9-NEXT: v_mul_lo_u32 v8, v0, s4
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; GFX9-NEXT: v_sub_u32_e32 v4, v4, v0 ; GFX9-NEXT: v_sub_u32_e32 v4, v4, v0
; GFX9-NEXT: v_add_u32_e32 v4, v4, v6 ; GFX9-NEXT: v_add_u32_e32 v4, v4, v6
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v4 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v9, v0, v8 ; GFX9-NEXT: v_mul_hi_u32 v9, v0, v8
; GFX9-NEXT: v_mul_hi_u32 v10, v0, v4 ; GFX9-NEXT: v_mul_hi_u32 v10, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v11, v2, v4 ; GFX9-NEXT: v_mul_hi_u32 v11, v2, v4
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v9, v6 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v9, v6
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v7, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v7, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v10, v2, v8 ; GFX9-NEXT: v_mul_lo_u32 v10, v2, v8
; GFX9-NEXT: v_mul_hi_u32 v8, v2, v8 ; GFX9-NEXT: v_mul_hi_u32 v8, v2, v8
; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4 ; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_movk_i32 s0, 0xfff
; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], 12
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v10 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v10
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v9, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v9, v8, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v11, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v11, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v6, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v6, v2
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0
; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX9-NEXT: s_lshr_b64 s[2:3], s[4:5], 12
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s8 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 2, v0
; GFX9-NEXT: v_mul_lo_u32 v2, v1, s8 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, s0
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s8 ; GFX9-NEXT: v_mul_hi_u32 v6, v0, s0
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s6, v4 ; GFX9-NEXT: v_mul_lo_u32 v9, v0, s0
; GFX9-NEXT: s_movk_i32 s6, 0xffe ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, 1, v0
; GFX9-NEXT: v_mov_b32_e32 v3, s7 ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v3, v2, vcc ; GFX9-NEXT: v_add_u32_e32 v4, v6, v4
; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s8, v4 ; GFX9-NEXT: v_mov_b32_e32 v6, s7
; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc ; GFX9-NEXT: v_sub_co_u32_e32 v9, vcc, s6, v9
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s6, v3 ; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v6, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GFX9-NEXT: v_subrev_co_u32_e32 v6, vcc, s0, v9
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 ; GFX9-NEXT: v_subbrev_co_u32_e32 v10, vcc, 0, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc ; GFX9-NEXT: s_movk_i32 s0, 0xffe
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 2, v0 ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s0, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 1, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s6, v4 ; GFX9-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v9
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
; GFX9-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, -1, v6, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, v1, v3, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v8, v6, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: global_store_dwordx4 v5, v[0:3], s[8:9]
; GFX9-NEXT: global_store_dwordx4 v5, v[0:3], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%r = udiv <2 x i64> %x, <i64 4096, i64 4095> %r = udiv <2 x i64> %x, <i64 4096, i64 4095>
store <2 x i64> %r, <2 x i64> addrspace(1)* %out store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @udiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) { define amdgpu_kernel void @udiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @udiv_v2i64_pow2_shl_denom( ; CHECK-LABEL: @udiv_v2i64_pow2_shl_denom(
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; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_mov_b32_e32 v7, 0 ; GFX6-NEXT: v_mov_b32_e32 v7, 0
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2
; GFX6-NEXT: v_mul_hi_u32 v3, v0, s3 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s3
; GFX6-NEXT: v_mul_lo_u32 v4, v1, s3 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s3
; GFX6-NEXT: s_movk_i32 s12, 0x11f ; GFX6-NEXT: s_mov_b32 s12, 0x9761f7c9
; GFX6-NEXT: s_mov_b32 s13, 0x9761f7c9 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s8, s4
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_lo_u32 v3, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2
; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v4, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v4, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v3 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v3
; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_movk_i32 s4, 0x11f
; GFX6-NEXT: s_mov_b32 s9, s5
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
; GFX6-NEXT: s_movk_i32 s5, 0x11e ; GFX6-NEXT: s_mov_b32 s9, s5
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 ; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2
; GFX6-NEXT: v_mul_hi_u32 v5, v0, s3 ; GFX6-NEXT: v_mul_hi_u32 v5, v0, s3
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
; GFX6-NEXT: v_mul_lo_u32 v6, v2, s3 ; GFX6-NEXT: v_mul_lo_u32 v6, v2, s3
; GFX6-NEXT: s_mov_b32 s8, s4 ; GFX6-NEXT: s_movk_i32 s5, 0x11e
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_mul_lo_u32 v5, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v5, v0, s3
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_mul_lo_u32 v6, v0, v4 ; GFX6-NEXT: v_mul_lo_u32 v6, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v10, v0, v4 ; GFX6-NEXT: v_mul_hi_u32 v10, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v9, v0, v5 ; GFX6-NEXT: v_mul_hi_u32 v9, v0, v5
; GFX6-NEXT: v_mul_hi_u32 v11, v2, v4 ; GFX6-NEXT: v_mul_hi_u32 v11, v2, v4
; GFX6-NEXT: s_mov_b32 s4, 0x9761f7c8
; GFX6-NEXT: s_mov_b32 s11, 0xf000 ; GFX6-NEXT: s_mov_b32 s11, 0xf000
; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc ; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v10, v2, v5 ; GFX6-NEXT: v_mul_lo_u32 v10, v2, v5
; GFX6-NEXT: v_mul_hi_u32 v5, v2, v5 ; GFX6-NEXT: v_mul_hi_u32 v5, v2, v5
; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4 ; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v10 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v10
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, s6, v1 ; GFX6-NEXT: v_mul_lo_u32 v2, s6, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0
; GFX6-NEXT: v_mul_hi_u32 v4, s6, v1 ; GFX6-NEXT: v_mul_hi_u32 v4, s6, v1
; GFX6-NEXT: v_mul_hi_u32 v5, s7, v1 ; GFX6-NEXT: v_mul_hi_u32 v5, s7, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v0, s12 ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s4
; GFX6-NEXT: v_mul_hi_u32 v3, v0, s13 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s12
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s13 ; GFX6-NEXT: v_mul_lo_u32 v1, v1, s12
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s13 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s12
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s7, v1 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s7, v1
; GFX6-NEXT: v_mov_b32_e32 v3, s12
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
; GFX6-NEXT: v_mov_b32_e32 v3, s4
; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc ; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
; GFX6-NEXT: v_subrev_i32_e64 v4, s[0:1], s13, v0 ; GFX6-NEXT: v_subrev_i32_e64 v4, s[0:1], s12, v0
; GFX6-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1] ; GFX6-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
; GFX6-NEXT: v_cmp_lt_u32_e64 s[2:3], s5, v5 ; GFX6-NEXT: v_cmp_lt_u32_e64 s[2:3], s5, v5
; GFX6-NEXT: s_mov_b32 s6, 0x9761f7c8
; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1] ; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3] ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3]
; GFX6-NEXT: v_cmp_lt_u32_e64 s[2:3], s4, v4 ; GFX6-NEXT: v_cmp_lt_u32_e64 s[2:3], s6, v4
; GFX6-NEXT: v_subrev_i32_e64 v3, s[0:1], s13, v4 ; GFX6-NEXT: v_subrev_i32_e64 v3, s[0:1], s12, v4
; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3] ; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3]
; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s12, v5 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, v5
; GFX6-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3] ; GFX6-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3]
; GFX6-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] ; GFX6-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
; GFX6-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1]
; GFX6-NEXT: v_mov_b32_e32 v5, s7 ; GFX6-NEXT: v_mov_b32_e32 v5, s7
; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v5, v1, vcc ; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v5, v1, vcc
; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s5, v1 ; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s5, v1
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0 ; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s6, v0
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s12, v1 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s4, v1
; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: urem_i64_oddk_denom: ; GFX9-LABEL: urem_i64_oddk_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f1761f8 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f1761f8
; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000
; GFX9-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0 ; GFX9-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_movk_i32 s4, 0xfee0 ; GFX9-NEXT: s_movk_i32 s4, 0xfee0
; GFX9-NEXT: s_mov_b32 s5, 0x689e0837 ; GFX9-NEXT: s_mov_b32 s5, 0x689e0837
; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: s_movk_i32 s8, 0x11f ; GFX9-NEXT: s_movk_i32 s8, 0x11f
; GFX9-NEXT: s_mov_b32 s9, 0x9761f7c9
; GFX9-NEXT: v_mul_lo_u32 v2, v0, s4 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, s4
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s5 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s5
; GFX9-NEXT: v_mul_lo_u32 v5, v1, s5 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, s5
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s5 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, s5
; GFX9-NEXT: s_mov_b32 s10, 0x9761f7c8 ; GFX9-NEXT: s_mov_b32 s9, 0x9761f7c9
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_add_u32_e32 v2, v2, v5 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2
; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, v6
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4 ; GFX9-NEXT: v_mul_lo_u32 v7, v1, v6
; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v6, v1, v6
; GFX9-NEXT: s_mov_b32 s10, 0x9761f7c8
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v6, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4
; GFX9-NEXT: v_mul_hi_u32 v7, v0, s5 ; GFX9-NEXT: v_mul_hi_u32 v6, v0, s5
; GFX9-NEXT: v_mul_lo_u32 v8, v2, s5 ; GFX9-NEXT: v_mul_lo_u32 v7, v2, s5
; GFX9-NEXT: v_mul_lo_u32 v9, v0, s5 ; GFX9-NEXT: v_mul_lo_u32 v9, v0, s5
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: v_add_u32_e32 v4, v7, v4 ; GFX9-NEXT: v_add_u32_e32 v4, v6, v4
; GFX9-NEXT: v_add_u32_e32 v4, v4, v8 ; GFX9-NEXT: v_add_u32_e32 v4, v4, v7
; GFX9-NEXT: v_mul_lo_u32 v7, v0, v4 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v9 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v9
; GFX9-NEXT: v_mul_hi_u32 v10, v0, v4 ; GFX9-NEXT: v_mul_hi_u32 v10, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v11, v2, v4 ; GFX9-NEXT: v_mul_hi_u32 v11, v2, v4
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v8, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v10, v2, v9 ; GFX9-NEXT: v_mul_lo_u32 v10, v2, v9
; GFX9-NEXT: v_mul_hi_u32 v9, v2, v9 ; GFX9-NEXT: v_mul_hi_u32 v9, v2, v9
; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4 ; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v10 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v10
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v8, v9, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v9, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v11, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v11, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v7, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v6, v2
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0
; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, s8
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s9 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s9
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s9 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s9
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s9 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, s9
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 ; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
; GFX9-NEXT: v_sub_co_u32_e64 v0, s[0:1], s6, v0 ; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s6, v0
; GFX9-NEXT: v_sub_u32_e32 v2, s7, v1 ; GFX9-NEXT: v_sub_u32_e32 v2, s7, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s8 ; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_subb_co_u32_e64 v2, vcc, v2, v3, s[0:1] ; GFX9-NEXT: v_subb_co_u32_e64 v2, s[0:1], v2, v3, vcc
; GFX9-NEXT: v_subrev_co_u32_e64 v4, s[2:3], s9, v0 ; GFX9-NEXT: v_subrev_co_u32_e64 v4, s[0:1], s9, v0
; GFX9-NEXT: v_subbrev_co_u32_e64 v5, vcc, 0, v2, s[2:3] ; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[2:3], 0, v2, s[0:1]
; GFX9-NEXT: s_movk_i32 s6, 0x11e ; GFX9-NEXT: s_movk_i32 s6, 0x11e
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s6, v5 ; GFX9-NEXT: v_cmp_lt_u32_e64 s[2:3], s6, v6
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: v_subb_co_u32_e64 v2, s[0:1], v2, v3, s[0:1]
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s10, v4 ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GFX9-NEXT: v_cmp_lt_u32_e64 s[2:3], s10, v4
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s8, v5 ; GFX9-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s9, v4
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3]
; GFX9-NEXT: v_subb_co_u32_e64 v2, vcc, v2, v3, s[2:3] ; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s8, v6
; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s9, v4 ; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[2:3]
; GFX9-NEXT: v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_subbrev_co_u32_e64 v2, s[0:1], 0, v2, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v7 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7
; GFX9-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v5, s7 ; GFX9-NEXT: v_mov_b32_e32 v6, s7
; GFX9-NEXT: v_subb_co_u32_e64 v1, vcc, v5, v1, s[0:1] ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v6, v1, vcc
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1 ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s10, v0 ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s10, v0
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s8, v1 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s8, v1
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[4:5] ; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[4:5]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%r = urem i64 %x, 1235195393993 %r = urem i64 %x, 1235195393993
store i64 %r, i64 addrspace(1)* %out store i64 %r, i64 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @urem_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @urem_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
; CHECK-LABEL: @urem_i64_pow2k_denom( ; CHECK-LABEL: @urem_i64_pow2k_denom(
▲ Show 20 Lines • Show All 274 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_mul_lo_u32 v4, s1, v0 ; GFX6-NEXT: v_mul_lo_u32 v4, s1, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
; GFX6-NEXT: s_mov_b32 s3, 0x12d8fb ; GFX6-NEXT: s_mov_b32 s3, 0x12d8fb
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v1, s3 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s3
; GFX6-NEXT: v_mul_hi_u32 v3, s3, v0 ; GFX6-NEXT: v_mul_hi_u32 v5, s3, v0
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 2, v0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_mul_lo_u32 v8, v0, s3
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s0, v4 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX6-NEXT: v_mov_b32_e32 v3, s1 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v0
; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s3, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc ; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s0, v8
; GFX6-NEXT: v_mov_b32_e32 v5, s1
; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v5, v4, vcc
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s3, v8
; GFX6-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
; GFX6-NEXT: s_mov_b32 s0, 0x12d8fa ; GFX6-NEXT: s_mov_b32 s0, 0x12d8fa
; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v3 ; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v5
; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
; GFX6-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v5, vcc, 2, v0 ; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v8
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX6-NEXT: v_add_i32_e32 v7, vcc, 1, v0 ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v4 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v4, -1, v5, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX6-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1]
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GFX6-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, s2, v0
; GFX6-NEXT: v_xor_b32_e32 v1, s2, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, s2, v1
; GFX6-NEXT: v_mov_b32_e32 v2, s2 ; GFX6-NEXT: v_mov_b32_e32 v2, s2
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_lo_u32 v4, s1, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s1, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s1, v0
; GFX9-NEXT: s_mov_b32 s3, 0x12d8fb ; GFX9-NEXT: s_mov_b32 s3, 0x12d8fb
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s3 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 2, v0
; GFX9-NEXT: v_mul_lo_u32 v2, v1, s3 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, s3
; GFX9-NEXT: v_mul_hi_u32 v3, s3, v0 ; GFX9-NEXT: v_mul_hi_u32 v6, s3, v0
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s0, v4 ; GFX9-NEXT: v_mul_lo_u32 v9, v0, s3
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, 1, v0
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v3, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s3, v4 ; GFX9-NEXT: v_add_u32_e32 v4, v6, v4
; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc ; GFX9-NEXT: v_sub_co_u32_e32 v9, vcc, s0, v9
; GFX9-NEXT: s_mov_b32 s3, 0x12d8fa ; GFX9-NEXT: v_mov_b32_e32 v6, s1
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v3 ; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v6, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GFX9-NEXT: v_subrev_co_u32_e32 v6, vcc, s3, v9
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 ; GFX9-NEXT: v_subbrev_co_u32_e32 v10, vcc, 0, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc ; GFX9-NEXT: s_mov_b32 s0, 0x12d8fa
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 2, v0 ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s0, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 1, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v4 ; GFX9-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v9
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
; GFX9-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, -1, v6, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, v6, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
; GFX9-NEXT: v_xor_b32_e32 v1, s2, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s2, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s2, v0 ; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s2, v0
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[4:5] ; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[4:5]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%r = sdiv i64 %x, 1235195 %r = sdiv i64 %x, 1235195
▲ Show 20 Lines • Show All 253 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10 ; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
; GFX9-NEXT: v_mul_hi_u32 v7, v3, v5 ; GFX9-NEXT: v_mul_hi_u32 v7, v3, v5
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, v3, v5 ; GFX9-NEXT: v_mul_lo_u32 v3, v3, v5
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v8, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v8, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s12, s7, 31
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_u32_e32 v1, v1, v4 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v4
; GFX9-NEXT: s_add_u32 s0, s6, s12
; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s2, s7, 31
; GFX9-NEXT: s_add_u32 s0, s6, s2
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: s_mov_b32 s13, s12 ; GFX9-NEXT: s_mov_b32 s3, s2
; GFX9-NEXT: s_addc_u32 s1, s7, s12 ; GFX9-NEXT: s_addc_u32 s1, s7, s2
; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[12:13] ; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[2:3]
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, s6, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v0
; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v4, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v2, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, s10, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s10, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s10, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s10, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s11, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s11, v0
; GFX9-NEXT: v_mov_b32_e32 v6, s11 ; GFX9-NEXT: v_mov_b32_e32 v6, s11
; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_mul_lo_u32 v4, s10, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s10, v0
; GFX9-NEXT: v_add_u32_e32 v3, v3, v5 ; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
; GFX9-NEXT: v_sub_u32_e32 v5, s7, v3 ; GFX9-NEXT: v_sub_u32_e32 v5, s7, v3
; GFX9-NEXT: v_sub_co_u32_e64 v4, s[0:1], s6, v4 ; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s6, v4
; GFX9-NEXT: v_subb_co_u32_e64 v5, vcc, v5, v6, s[0:1] ; GFX9-NEXT: v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc
; GFX9-NEXT: v_subrev_co_u32_e32 v6, vcc, s10, v4 ; GFX9-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s10, v4
; GFX9-NEXT: v_subbrev_co_u32_e32 v5, vcc, 0, v5, vcc ; GFX9-NEXT: v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v5 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v5
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v6 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v6
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v5 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1]
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 2, v0 ; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], 2, v0
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v1, s[0:1]
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 1, v0 ; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 1, v0
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e64 v9, s[0:1], 0, v1, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v5 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
; GFX9-NEXT: v_cndmask_b32_e64 v5, v9, v7, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v5, v9, v7, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v7, s7 ; GFX9-NEXT: v_mov_b32_e32 v7, s7
; GFX9-NEXT: v_subb_co_u32_e64 v3, vcc, v7, v3, s[0:1] ; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v7, v3, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v4
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v3 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v4, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, v8, v6, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v8, v6, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: s_xor_b64 s[0:1], s[12:13], s[8:9] ; GFX9-NEXT: s_xor_b64 s[0:1], s[2:3], s[8:9]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0 ; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
; GFX6-NEXT: s_movk_i32 s9, 0xfff ; GFX6-NEXT: s_movk_i32 s9, 0xfff
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v1, s9 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s9
; GFX6-NEXT: v_mul_hi_u32 v3, s9, v0 ; GFX6-NEXT: v_mul_hi_u32 v5, s9, v0
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s9 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 2, v0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_mul_lo_u32 v8, v0, s9
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s0, v4 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX6-NEXT: v_mov_b32_e32 v3, s1 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v0
; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s9, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc ; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s0, v8
; GFX6-NEXT: v_mov_b32_e32 v5, s1
; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v5, v4, vcc
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s9, v8
; GFX6-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
; GFX6-NEXT: s_movk_i32 s0, 0xffe ; GFX6-NEXT: s_movk_i32 s0, 0xffe
; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v3 ; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v5
; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
; GFX6-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v5, vcc, 2, v0 ; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v8
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX6-NEXT: v_add_i32_e32 v7, vcc, 1, v0 ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v4 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v4, -1, v5, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX6-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1]
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GFX6-NEXT: v_xor_b32_e32 v0, s8, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, s8, v0
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s8, v0 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s8, v0
; GFX6-NEXT: v_xor_b32_e32 v1, s8, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, s8, v1
; GFX6-NEXT: v_mov_b32_e32 v3, s8 ; GFX6-NEXT: v_mov_b32_e32 v3, s8
; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc ; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc
; GFX6-NEXT: v_mov_b32_e32 v0, s2 ; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s3 ; GFX6-NEXT: v_mov_b32_e32 v1, s3
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0
; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX9-NEXT: s_movk_i32 s3, 0xfff ; GFX9-NEXT: s_movk_i32 s0, 0xfff
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v4, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, v0, s3 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 2, v0
; GFX9-NEXT: v_mul_lo_u32 v2, v1, s3 ; GFX9-NEXT: v_mul_lo_u32 v5, v1, s0
; GFX9-NEXT: v_mul_hi_u32 v3, s3, v0 ; GFX9-NEXT: v_mul_hi_u32 v6, s0, v0
; GFX9-NEXT: v_sub_co_u32_e32 v5, vcc, s6, v5 ; GFX9-NEXT: v_mul_lo_u32 v9, v0, s0
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v3, s7 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, 1, v0
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v3, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s3, v5 ; GFX9-NEXT: v_add_u32_e32 v5, v6, v5
; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc ; GFX9-NEXT: v_mov_b32_e32 v6, s7
; GFX9-NEXT: s_movk_i32 s3, 0xffe ; GFX9-NEXT: v_sub_co_u32_e32 v9, vcc, s6, v9
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v3 ; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v6, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GFX9-NEXT: v_subrev_co_u32_e32 v6, vcc, s0, v9
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 ; GFX9-NEXT: v_subbrev_co_u32_e32 v10, vcc, 0, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc ; GFX9-NEXT: s_movk_i32 s0, 0xffe
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 2, v0 ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s0, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 1, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v5 ; GFX9-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v9
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v5
; GFX9-NEXT: v_cndmask_b32_e32 v2, -1, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v5, -1, v6, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, v6, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s2, v0 ; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s2, v0
; GFX9-NEXT: v_xor_b32_e32 v1, s2, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s2, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s2 ; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
▲ Show 20 Lines • Show All 286 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc ; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdiv_v2i64_pow2_shl_denom: ; GFX9-LABEL: sdiv_v2i64_pow2_shl_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x44 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x44
; GFX9-NEXT: s_mov_b64 s[2:3], 0x1000 ; GFX9-NEXT: s_mov_b64 s[2:3], 0x1000
; GFX9-NEXT: s_mov_b32 s18, 0x4f800000 ; GFX9-NEXT: s_mov_b32 s16, 0x4f800000
; GFX9-NEXT: s_mov_b32 s19, 0x5f7ffffc ; GFX9-NEXT: s_mov_b32 s17, 0x5f7ffffc
; GFX9-NEXT: s_mov_b32 s20, 0x2f800000 ; GFX9-NEXT: s_mov_b32 s18, 0x2f800000
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b64 s[8:9], s[2:3], s6 ; GFX9-NEXT: s_lshl_b64 s[8:9], s[2:3], s6
; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s4 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
; GFX9-NEXT: s_ashr_i32 s12, s3, 31 ; GFX9-NEXT: s_ashr_i32 s12, s3, 31
; GFX9-NEXT: s_add_u32 s2, s2, s12 ; GFX9-NEXT: s_add_u32 s2, s2, s12
; GFX9-NEXT: s_mov_b32 s13, s12 ; GFX9-NEXT: s_mov_b32 s13, s12
; GFX9-NEXT: s_addc_u32 s3, s3, s12 ; GFX9-NEXT: s_addc_u32 s3, s3, s12
; GFX9-NEXT: s_xor_b64 s[10:11], s[2:3], s[12:13] ; GFX9-NEXT: s_xor_b64 s[10:11], s[2:3], s[12:13]
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s10 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s10
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s11 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s11
; GFX9-NEXT: s_mov_b32 s21, 0xcf800000 ; GFX9-NEXT: s_mov_b32 s19, 0xcf800000
; GFX9-NEXT: s_sub_u32 s14, 0, s10 ; GFX9-NEXT: s_sub_u32 s14, 0, s10
; GFX9-NEXT: s_subb_u32 s4, 0, s11 ; GFX9-NEXT: s_subb_u32 s4, 0, s11
; GFX9-NEXT: v_mac_f32_e32 v0, s18, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, s16, v1
; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_mov_b32_e32 v6, 0
; GFX9-NEXT: v_mul_f32_e32 v0, s19, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, s17, v0
; GFX9-NEXT: v_mul_f32_e32 v1, s20, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, s18, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, s21, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, s19, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s14, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s14, v0
; GFX9-NEXT: v_mul_lo_u32 v2, s14, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s14, v1
; GFX9-NEXT: v_mul_lo_u32 v5, s4, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s4, v0
; GFX9-NEXT: v_mul_lo_u32 v4, s14, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s14, v0
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_add_u32_e32 v2, v2, v5 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
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; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v8, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v8, v2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s14, s5, 31 ; GFX9-NEXT: s_ashr_i32 s14, s5, 31
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
; GFX9-NEXT: s_add_u32 s2, s4, s14 ; GFX9-NEXT: s_add_u32 s2, s4, s14
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: s_addc_u32 s3, s5, s14
; GFX9-NEXT: s_mov_b32 s15, s14 ; GFX9-NEXT: s_mov_b32 s15, s14
; GFX9-NEXT: s_xor_b64 s[16:17], s[2:3], s[14:15] ; GFX9-NEXT: s_addc_u32 s3, s5, s14
; GFX9-NEXT: s_xor_b64 s[4:5], s[2:3], s[14:15]
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, s16, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s4, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s16, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s4, v0
; GFX9-NEXT: v_mul_hi_u32 v4, s16, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s4, v1
; GFX9-NEXT: v_mul_hi_u32 v7, s17, v1 ; GFX9-NEXT: v_mul_hi_u32 v7, s5, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s17, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s5, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s17, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s5, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s17, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s5, v0
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_xor_b64 s[12:13], s[14:15], s[12:13]
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, s10, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s10, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s10, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s10, v0
; GFX9-NEXT: v_mul_lo_u32 v4, s11, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s11, v0
; GFX9-NEXT: v_mov_b32_e32 v7, s11 ; GFX9-NEXT: v_mov_b32_e32 v7, s11
; GFX9-NEXT: s_ashr_i32 s14, s9, 31
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_mul_lo_u32 v3, s10, v0 ; GFX9-NEXT: v_mul_lo_u32 v3, s10, v0
; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
; GFX9-NEXT: v_sub_u32_e32 v4, s17, v2 ; GFX9-NEXT: v_sub_u32_e32 v4, s5, v2
; GFX9-NEXT: s_mov_b32 s15, s14 ; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, s4, v3
; GFX9-NEXT: v_sub_co_u32_e64 v3, s[0:1], s16, v3 ; GFX9-NEXT: v_subb_co_u32_e64 v4, s[0:1], v4, v7, vcc
; GFX9-NEXT: v_subb_co_u32_e64 v4, vcc, v4, v7, s[0:1] ; GFX9-NEXT: v_subrev_co_u32_e64 v7, s[0:1], s10, v3
; GFX9-NEXT: v_subrev_co_u32_e32 v7, vcc, s10, v3 ; GFX9-NEXT: v_subbrev_co_u32_e64 v4, s[0:1], 0, v4, s[0:1]
; GFX9-NEXT: v_subbrev_co_u32_e32 v4, vcc, 0, v4, vcc ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v4 ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v7
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v7 ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v4
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v4 ; GFX9-NEXT: v_cndmask_b32_e64 v4, v8, v7, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v7, vcc ; GFX9-NEXT: v_add_co_u32_e64 v7, s[0:1], 2, v0
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, 2, v0 ; GFX9-NEXT: v_addc_co_u32_e64 v8, s[0:1], 0, v1, s[0:1]
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc ; GFX9-NEXT: v_add_co_u32_e64 v9, s[0:1], 1, v0
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, 1, v0 ; GFX9-NEXT: v_addc_co_u32_e64 v10, s[0:1], 0, v1, s[0:1]
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v1, vcc ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v4 ; GFX9-NEXT: v_cndmask_b32_e64 v4, v10, v8, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v4, v10, v8, s[2:3] ; GFX9-NEXT: v_mov_b32_e32 v8, s5
; GFX9-NEXT: v_mov_b32_e32 v8, s17 ; GFX9-NEXT: s_xor_b64 s[4:5], s[14:15], s[12:13]
; GFX9-NEXT: v_subb_co_u32_e64 v2, vcc, v8, v2, s[0:1] ; GFX9-NEXT: s_ashr_i32 s12, s9, 31
; GFX9-NEXT: s_add_u32 s0, s8, s14 ; GFX9-NEXT: s_add_u32 s8, s8, s12
; GFX9-NEXT: s_addc_u32 s1, s9, s14 ; GFX9-NEXT: s_mov_b32 s13, s12
; GFX9-NEXT: s_xor_b64 s[8:9], s[0:1], s[14:15] ; GFX9-NEXT: s_addc_u32 s9, s9, s12
; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT: v_cvt_f32_u32_e32 v10, s8 ; GFX9-NEXT: v_cvt_f32_u32_e32 v10, s8
; GFX9-NEXT: v_cvt_f32_u32_e32 v11, s9 ; GFX9-NEXT: v_cvt_f32_u32_e32 v11, s9
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v8, v2, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v2 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v2
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v2 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v2
; GFX9-NEXT: v_mac_f32_e32 v10, s18, v11 ; GFX9-NEXT: v_mac_f32_e32 v10, s16, v11
; GFX9-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc
; GFX9-NEXT: v_rcp_f32_e32 v3, v10 ; GFX9-NEXT: v_rcp_f32_e32 v3, v10
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, v9, v7, s[2:3] ; GFX9-NEXT: s_sub_u32 s10, 0, s8
; GFX9-NEXT: v_mul_f32_e32 v3, s19, v3 ; GFX9-NEXT: v_mul_f32_e32 v3, s17, v3
; GFX9-NEXT: v_mul_f32_e32 v4, s20, v3 ; GFX9-NEXT: v_mul_f32_e32 v4, s18, v3
; GFX9-NEXT: v_trunc_f32_e32 v4, v4 ; GFX9-NEXT: v_trunc_f32_e32 v4, v4
; GFX9-NEXT: v_mac_f32_e32 v3, s21, v4 ; GFX9-NEXT: v_mac_f32_e32 v3, s19, v4
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX9-NEXT: s_sub_u32 s2, 0, s8 ; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: s_subb_u32 s3, 0, s9 ; GFX9-NEXT: v_cndmask_b32_e64 v2, v9, v7, s[0:1]
; GFX9-NEXT: v_mul_hi_u32 v7, s2, v3 ; GFX9-NEXT: s_subb_u32 s11, 0, s9
; GFX9-NEXT: v_mul_lo_u32 v8, s2, v4 ; GFX9-NEXT: v_mul_lo_u32 v8, s10, v4
; GFX9-NEXT: v_mul_lo_u32 v9, s3, v3 ; GFX9-NEXT: v_mul_hi_u32 v7, s10, v3
; GFX9-NEXT: v_mul_lo_u32 v9, s11, v3
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, s2, v3 ; GFX9-NEXT: v_mul_lo_u32 v2, s10, v3
; GFX9-NEXT: v_add_u32_e32 v7, v7, v8 ; GFX9-NEXT: v_add_u32_e32 v7, v7, v8
; GFX9-NEXT: v_add_u32_e32 v7, v7, v9 ; GFX9-NEXT: v_add_u32_e32 v7, v7, v9
; GFX9-NEXT: v_mul_lo_u32 v8, v3, v7 ; GFX9-NEXT: v_mul_lo_u32 v8, v3, v7
; GFX9-NEXT: v_mul_hi_u32 v9, v3, v2 ; GFX9-NEXT: v_mul_hi_u32 v9, v3, v2
; GFX9-NEXT: v_mul_hi_u32 v10, v3, v7 ; GFX9-NEXT: v_mul_hi_u32 v10, v3, v7
; GFX9-NEXT: v_mul_hi_u32 v11, v4, v7 ; GFX9-NEXT: v_mul_hi_u32 v11, v4, v7
; GFX9-NEXT: v_mul_lo_u32 v7, v4, v7 ; GFX9-NEXT: v_mul_lo_u32 v7, v4, v7
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v10, v4, v2 ; GFX9-NEXT: v_mul_lo_u32 v10, v4, v2
; GFX9-NEXT: v_mul_hi_u32 v2, v4, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v4, v2
; GFX9-NEXT: s_ashr_i32 s10, s7, 31 ; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0
; GFX9-NEXT: s_mov_b32 s11, s10 ; GFX9-NEXT: v_xor_b32_e32 v1, s5, v1
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v9, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v9, v2, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v7 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v7
; GFX9-NEXT: v_add_co_u32_e64 v2, s[0:1], v3, v2 ; GFX9-NEXT: v_add_co_u32_e64 v2, s[0:1], v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v5, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v5, v8, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v4, v7, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v4, v7, s[0:1]
; GFX9-NEXT: v_mul_lo_u32 v8, s2, v3 ; GFX9-NEXT: v_mul_lo_u32 v8, s10, v3
; GFX9-NEXT: v_mul_hi_u32 v9, s2, v2 ; GFX9-NEXT: v_mul_hi_u32 v9, s10, v2
; GFX9-NEXT: v_mul_lo_u32 v10, s3, v2 ; GFX9-NEXT: v_mul_lo_u32 v10, s11, v2
; GFX9-NEXT: v_mul_lo_u32 v11, s2, v2 ; GFX9-NEXT: v_mul_lo_u32 v11, s10, v2
; GFX9-NEXT: v_add_u32_e32 v4, v4, v7 ; GFX9-NEXT: s_ashr_i32 s10, s7, 31
; GFX9-NEXT: v_add_u32_e32 v8, v9, v8 ; GFX9-NEXT: v_add_u32_e32 v8, v9, v8
; GFX9-NEXT: v_add_u32_e32 v8, v8, v10 ; GFX9-NEXT: v_add_u32_e32 v8, v8, v10
; GFX9-NEXT: v_mul_lo_u32 v12, v2, v8 ; GFX9-NEXT: v_mul_lo_u32 v12, v2, v8
; GFX9-NEXT: v_mul_hi_u32 v13, v2, v11 ; GFX9-NEXT: v_mul_hi_u32 v13, v2, v11
; GFX9-NEXT: v_mul_hi_u32 v14, v2, v8 ; GFX9-NEXT: v_mul_hi_u32 v14, v2, v8
; GFX9-NEXT: v_mul_hi_u32 v10, v3, v11 ; GFX9-NEXT: v_mul_hi_u32 v10, v3, v11
; GFX9-NEXT: v_mul_lo_u32 v11, v3, v11 ; GFX9-NEXT: v_mul_lo_u32 v11, v3, v11
; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v13, v12 ; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v13, v12
; GFX9-NEXT: v_mul_hi_u32 v9, v3, v8 ; GFX9-NEXT: v_mul_hi_u32 v9, v3, v8
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v14, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v14, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, v3, v8 ; GFX9-NEXT: v_mul_lo_u32 v3, v3, v8
; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v12, v11 ; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v12, v11
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v10, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v9, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v9, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v10, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v10, v3
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v5, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v5, v8, vcc
; GFX9-NEXT: v_add_u32_e32 v4, v4, v7
; GFX9-NEXT: v_addc_co_u32_e64 v4, vcc, v4, v8, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v4, vcc, v4, v8, s[0:1]
; GFX9-NEXT: s_add_u32 s0, s6, s10 ; GFX9-NEXT: s_add_u32 s0, s6, s10
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
; GFX9-NEXT: s_mov_b32 s11, s10
; GFX9-NEXT: s_addc_u32 s1, s7, s10 ; GFX9-NEXT: s_addc_u32 s1, s7, s10
; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11] ; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11]
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s6, v3 ; GFX9-NEXT: v_mul_lo_u32 v4, s6, v3
; GFX9-NEXT: v_mul_hi_u32 v7, s6, v2 ; GFX9-NEXT: v_mul_hi_u32 v7, s6, v2
; GFX9-NEXT: v_mul_hi_u32 v9, s6, v3 ; GFX9-NEXT: v_mul_hi_u32 v9, s6, v3
; GFX9-NEXT: v_mul_hi_u32 v10, s7, v3 ; GFX9-NEXT: v_mul_hi_u32 v10, s7, v3
; GFX9-NEXT: v_mul_lo_u32 v3, s7, v3 ; GFX9-NEXT: v_mul_lo_u32 v3, s7, v3
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v7, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v7, v4
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v9, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
; GFX9-NEXT: v_mul_lo_u32 v9, s7, v2 ; GFX9-NEXT: v_mul_lo_u32 v9, s7, v2
; GFX9-NEXT: v_mul_hi_u32 v2, s7, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, s7, v2
; GFX9-NEXT: v_xor_b32_e32 v0, s12, v0 ; GFX9-NEXT: v_mov_b32_e32 v8, s5
; GFX9-NEXT: v_xor_b32_e32 v1, s13, v1
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v9 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v9
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v2, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v10, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v10, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s8, v3 ; GFX9-NEXT: v_mul_lo_u32 v4, s8, v3
; GFX9-NEXT: v_mul_hi_u32 v5, s8, v2 ; GFX9-NEXT: v_mul_hi_u32 v5, s8, v2
; GFX9-NEXT: v_mul_lo_u32 v7, s9, v2 ; GFX9-NEXT: v_mul_lo_u32 v7, s9, v2
; GFX9-NEXT: v_mov_b32_e32 v8, s13 ; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s4, v0
; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s12, v0 ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v8, vcc
; GFX9-NEXT: v_add_u32_e32 v4, v5, v4 ; GFX9-NEXT: v_add_u32_e32 v4, v5, v4
; GFX9-NEXT: v_mul_lo_u32 v5, s8, v2 ; GFX9-NEXT: v_mul_lo_u32 v5, s8, v2
; GFX9-NEXT: v_add_u32_e32 v4, v4, v7 ; GFX9-NEXT: v_add_u32_e32 v4, v4, v7
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v8, vcc
; GFX9-NEXT: v_sub_u32_e32 v7, s7, v4 ; GFX9-NEXT: v_sub_u32_e32 v7, s7, v4
; GFX9-NEXT: v_mov_b32_e32 v8, s9 ; GFX9-NEXT: v_mov_b32_e32 v8, s9
; GFX9-NEXT: v_sub_co_u32_e64 v5, s[0:1], s6, v5 ; GFX9-NEXT: v_sub_co_u32_e32 v5, vcc, s6, v5
; GFX9-NEXT: v_subb_co_u32_e64 v7, vcc, v7, v8, s[0:1] ; GFX9-NEXT: v_subb_co_u32_e64 v7, s[0:1], v7, v8, vcc
; GFX9-NEXT: v_subrev_co_u32_e32 v8, vcc, s8, v5 ; GFX9-NEXT: v_subrev_co_u32_e64 v8, s[0:1], s8, v5
; GFX9-NEXT: v_subbrev_co_u32_e32 v7, vcc, 0, v7, vcc ; GFX9-NEXT: v_subbrev_co_u32_e64 v7, s[0:1], 0, v7, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v7 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v7
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v8 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v8
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v7 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v7
; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[0:1]
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 2, v2 ; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 2, v2
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e64 v9, s[0:1], 0, v3, s[0:1]
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 1, v2 ; GFX9-NEXT: v_add_co_u32_e64 v10, s[0:1], 1, v2
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e64 v11, s[0:1], 0, v3, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v7 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7
; GFX9-NEXT: v_cndmask_b32_e64 v7, v11, v9, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v7, v11, v9, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v9, s7 ; GFX9-NEXT: v_mov_b32_e32 v9, s7
; GFX9-NEXT: v_subb_co_u32_e64 v4, vcc, v9, v4, s[0:1] ; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v9, v4, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v4
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v4 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v9, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v9, v5, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GFX9-NEXT: v_cndmask_b32_e64 v4, v10, v8, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v4, v10, v8, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: s_xor_b64 s[0:1], s[10:11], s[14:15] ; GFX9-NEXT: s_xor_b64 s[0:1], s[10:11], s[12:13]
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX9-NEXT: v_xor_b32_e32 v2, s0, v2 ; GFX9-NEXT: v_xor_b32_e32 v2, s0, v2
; GFX9-NEXT: v_xor_b32_e32 v3, s1, v3 ; GFX9-NEXT: v_xor_b32_e32 v3, s1, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s1 ; GFX9-NEXT: v_mov_b32_e32 v4, s1
; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s0, v2 ; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s0, v2
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v4, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v4, vcc
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx4 v6, v[0:3], s[4:5] ; GFX9-NEXT: global_store_dwordx4 v6, v[0:3], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = sdiv <2 x i64> %x, %shl.y %r = sdiv <2 x i64> %x, %shl.y
store <2 x i64> %r, <2 x i64> addrspace(1)* %out store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
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; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
; GFX9-NEXT: v_mul_hi_u32 v2, s3, v0 ; GFX9-NEXT: v_mul_hi_u32 v2, s3, v0
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s3 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s3
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3
; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 ; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s0, v0 ; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s0, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc
; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s3, v0 ; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s3, v0
; GFX9-NEXT: v_subbrev_co_u32_e32 v3, vcc, 0, v1, vcc ; GFX9-NEXT: v_subbrev_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s3, v2 ; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s3, v2
; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v3, vcc ; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v3, vcc
; GFX9-NEXT: s_mov_b32 s3, 0x12d8fa ; GFX9-NEXT: s_mov_b32 s0, 0x12d8fa
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v2 ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s0, v2
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_cndmask_b32_e32 v7, -1, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, -1, v7, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v0 ; GFX9-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v0
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
; GFX9-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, -1, v6, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
; GFX9-NEXT: v_xor_b32_e32 v1, s2, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s2, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s2, v0 ; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s2, v0
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[4:5] ; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[4:5]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%r = srem i64 %x, 1235195 %r = srem i64 %x, 1235195
▲ Show 20 Lines • Show All 286 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v1, s8, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s8, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s8, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s8, v0
; GFX9-NEXT: v_mul_lo_u32 v4, s9, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s9, v0
; GFX9-NEXT: v_mul_lo_u32 v0, s8, v0 ; GFX9-NEXT: v_mul_lo_u32 v0, s8, v0
; GFX9-NEXT: v_add_u32_e32 v1, v3, v1 ; GFX9-NEXT: v_add_u32_e32 v1, v3, v1
; GFX9-NEXT: v_add_u32_e32 v1, v1, v4 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v4
; GFX9-NEXT: v_sub_co_u32_e64 v0, s[0:1], s6, v0
; GFX9-NEXT: v_sub_u32_e32 v3, s7, v1 ; GFX9-NEXT: v_sub_u32_e32 v3, s7, v1
; GFX9-NEXT: v_mov_b32_e32 v4, s9 ; GFX9-NEXT: v_mov_b32_e32 v4, s9
; GFX9-NEXT: v_subb_co_u32_e64 v3, vcc, v3, v4, s[0:1] ; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s6, v0
; GFX9-NEXT: v_subrev_co_u32_e64 v5, s[2:3], s8, v0 ; GFX9-NEXT: v_subb_co_u32_e64 v3, s[0:1], v3, v4, vcc
; GFX9-NEXT: v_subbrev_co_u32_e64 v6, vcc, 0, v3, s[2:3] ; GFX9-NEXT: v_subrev_co_u32_e64 v5, s[0:1], s8, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v6 ; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[2:3], 0, v3, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s9, v6
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5 ; GFX9-NEXT: v_subb_co_u32_e64 v3, s[0:1], v3, v4, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v6 ; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s8, v5
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc ; GFX9-NEXT: v_subrev_co_u32_e64 v4, s[0:1], s8, v5
; GFX9-NEXT: v_subb_co_u32_e64 v3, vcc, v3, v4, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3]
; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s8, v5 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s9, v6
; GFX9-NEXT: v_subbrev_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[2:3]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v7 ; GFX9-NEXT: v_subbrev_co_u32_e64 v3, s[0:1], 0, v3, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v6, v3, s[2:3] ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7
; GFX9-NEXT: v_cndmask_b32_e64 v3, v6, v3, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v6, s7 ; GFX9-NEXT: v_mov_b32_e32 v6, s7
; GFX9-NEXT: v_subb_co_u32_e64 v1, vcc, v6, v1, s[0:1] ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v6, v1, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v0 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v1 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v1
; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, s10, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s10, v0
; GFX9-NEXT: v_xor_b32_e32 v1, s10, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s10, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s10 ; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s10, v0 ; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s10, v0
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
▲ Show 20 Lines • Show All 453 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v1, s14, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s14, v1
; GFX9-NEXT: v_mul_hi_u32 v2, s14, v0 ; GFX9-NEXT: v_mul_hi_u32 v2, s14, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s15, v0 ; GFX9-NEXT: v_mul_lo_u32 v3, s15, v0
; GFX9-NEXT: v_mul_lo_u32 v0, s14, v0 ; GFX9-NEXT: v_mul_lo_u32 v0, s14, v0
; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 ; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_sub_co_u32_e64 v0, s[0:1], s8, v0
; GFX9-NEXT: v_sub_u32_e32 v2, s9, v1 ; GFX9-NEXT: v_sub_u32_e32 v2, s9, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s15 ; GFX9-NEXT: v_mov_b32_e32 v3, s15
; GFX9-NEXT: v_subb_co_u32_e64 v2, vcc, v2, v3, s[0:1] ; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s8, v0
; GFX9-NEXT: v_subrev_co_u32_e64 v4, s[2:3], s14, v0 ; GFX9-NEXT: v_subb_co_u32_e64 v2, s[0:1], v2, v3, vcc
; GFX9-NEXT: v_subbrev_co_u32_e64 v7, vcc, 0, v2, s[2:3] ; GFX9-NEXT: v_subrev_co_u32_e64 v4, s[0:1], s14, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v7 ; GFX9-NEXT: v_subbrev_co_u32_e64 v7, s[2:3], 0, v2, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s15, v7
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v4 ; GFX9-NEXT: v_subb_co_u32_e64 v2, s[0:1], v2, v3, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s15, v7 ; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s14, v4
; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc ; GFX9-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s14, v4
; GFX9-NEXT: v_subb_co_u32_e64 v2, vcc, v2, v3, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3]
; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s14, v4 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s15, v7
; GFX9-NEXT: v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[2:3]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v8 ; GFX9-NEXT: s_ashr_i32 s2, s13, 31
; GFX9-NEXT: v_cndmask_b32_e64 v2, v7, v2, s[2:3] ; GFX9-NEXT: v_subbrev_co_u32_e64 v2, s[0:1], 0, v2, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v8
; GFX9-NEXT: s_add_u32 s8, s12, s2
; GFX9-NEXT: v_cndmask_b32_e64 v2, v7, v2, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v7, s9 ; GFX9-NEXT: v_mov_b32_e32 v7, s9
; GFX9-NEXT: v_subb_co_u32_e64 v1, vcc, v7, v1, s[0:1] ; GFX9-NEXT: s_mov_b32 s3, s2
; GFX9-NEXT: s_ashr_i32 s0, s13, 31 ; GFX9-NEXT: s_addc_u32 s9, s13, s2
; GFX9-NEXT: s_add_u32 s8, s12, s0 ; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[2:3]
; GFX9-NEXT: s_mov_b32 s1, s0 ; GFX9-NEXT: v_cvt_f32_u32_e32 v8, s8
; GFX9-NEXT: s_addc_u32 s9, s13, s0 ; GFX9-NEXT: v_cvt_f32_u32_e32 v9, s9
; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[0:1] ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v7, v1, vcc
; GFX9-NEXT: v_cvt_f32_u32_e32 v9, s8
; GFX9-NEXT: v_cvt_f32_u32_e32 v10, s9
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v1 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v1
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX9-NEXT: v_mac_f32_e32 v8, s16, v9
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v0 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v0
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GFX9-NEXT: v_rcp_f32_e32 v8, v8
; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s15, v1 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s15, v1
; GFX9-NEXT: v_mac_f32_e32 v9, s16, v10 ; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GFX9-NEXT: v_rcp_f32_e32 v8, v9
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[0:1]
; GFX9-NEXT: v_mul_f32_e32 v3, s17, v8 ; GFX9-NEXT: v_mul_f32_e32 v3, s17, v8
; GFX9-NEXT: v_mul_f32_e32 v4, s18, v3 ; GFX9-NEXT: v_mul_f32_e32 v4, s18, v3
; GFX9-NEXT: v_trunc_f32_e32 v4, v4 ; GFX9-NEXT: v_trunc_f32_e32 v4, v4
; GFX9-NEXT: v_mac_f32_e32 v3, s19, v4 ; GFX9-NEXT: v_mac_f32_e32 v3, s19, v4
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX9-NEXT: s_sub_u32 s2, 0, s8 ; GFX9-NEXT: s_sub_u32 s2, 0, s8
; GFX9-NEXT: s_subb_u32 s3, 0, s9 ; GFX9-NEXT: s_subb_u32 s3, 0, s9
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v10, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v10, v6, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, s8, v3 ; GFX9-NEXT: v_mul_lo_u32 v3, s8, v3
; GFX9-NEXT: v_mul_hi_u32 v4, s8, v2 ; GFX9-NEXT: v_mul_hi_u32 v4, s8, v2
; GFX9-NEXT: v_mul_lo_u32 v5, s9, v2 ; GFX9-NEXT: v_mul_lo_u32 v5, s9, v2
; GFX9-NEXT: v_mul_lo_u32 v2, s8, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, s8, v2
; GFX9-NEXT: v_mov_b32_e32 v8, s6 ; GFX9-NEXT: v_mov_b32_e32 v8, s6
; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s6, v0
; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v8, vcc
; GFX9-NEXT: v_add_u32_e32 v3, v3, v5 ; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s6, v0
; GFX9-NEXT: v_sub_co_u32_e64 v2, s[0:1], s10, v2
; GFX9-NEXT: v_sub_u32_e32 v4, s11, v3 ; GFX9-NEXT: v_sub_u32_e32 v4, s11, v3
; GFX9-NEXT: v_mov_b32_e32 v5, s9 ; GFX9-NEXT: v_mov_b32_e32 v5, s9
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v8, vcc ; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, s10, v2
; GFX9-NEXT: v_subb_co_u32_e64 v4, vcc, v4, v5, s[0:1] ; GFX9-NEXT: v_subb_co_u32_e64 v4, s[0:1], v4, v5, vcc
; GFX9-NEXT: v_subrev_co_u32_e64 v7, s[2:3], s8, v2 ; GFX9-NEXT: v_subrev_co_u32_e64 v7, s[0:1], s8, v2
; GFX9-NEXT: v_subbrev_co_u32_e64 v8, vcc, 0, v4, s[2:3] ; GFX9-NEXT: v_subbrev_co_u32_e64 v8, s[2:3], 0, v4, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v8 ; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s9, v8
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; GFX9-NEXT: v_subb_co_u32_e64 v4, s[0:1], v4, v5, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v7 ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc ; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s8, v7
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v8 ; GFX9-NEXT: v_subrev_co_u32_e64 v5, s[0:1], s8, v7
; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[2:3]
; GFX9-NEXT: v_subb_co_u32_e64 v4, vcc, v4, v5, s[2:3] ; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s9, v8
; GFX9-NEXT: v_subrev_co_u32_e32 v5, vcc, s8, v7 ; GFX9-NEXT: v_cndmask_b32_e64 v9, v9, v10, s[2:3]
; GFX9-NEXT: v_subbrev_co_u32_e32 v4, vcc, 0, v4, vcc ; GFX9-NEXT: v_subbrev_co_u32_e64 v4, s[0:1], 0, v4, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v9 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v9
; GFX9-NEXT: v_cndmask_b32_e64 v4, v8, v4, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v4, v8, v4, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v8, s11 ; GFX9-NEXT: v_mov_b32_e32 v8, s11
; GFX9-NEXT: v_subb_co_u32_e64 v3, vcc, v8, v3, s[0:1] ; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v8, v3, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v2 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v2
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3
; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v5, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v5, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_xor_b32_e32 v2, s12, v2 ; GFX9-NEXT: v_xor_b32_e32 v2, s12, v2
; GFX9-NEXT: v_xor_b32_e32 v3, s12, v3 ; GFX9-NEXT: v_xor_b32_e32 v3, s12, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s12 ; GFX9-NEXT: v_mov_b32_e32 v4, s12
; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s12, v2 ; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s12, v2
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v4, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v4, vcc
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx4 v6, v[0:3], s[4:5] ; GFX9-NEXT: global_store_dwordx4 v6, v[0:3], s[4:5]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = srem <2 x i64> %x, %shl.y %r = srem <2 x i64> %x, %shl.y
store <2 x i64> %r, <2 x i64> addrspace(1)* %out store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/branch-relaxation.ll

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; GCN-LABEL: {{^}}expand_requires_expand: ; GCN-LABEL: {{^}}expand_requires_expand:
; GCN-NEXT: ; %bb.0: ; %bb0 ; GCN-NEXT: ; %bb.0: ; %bb0
; GCN: s_load_dword ; GCN: s_load_dword
; GCN: {{s|v}}_cmp_lt_i32 ; GCN: {{s|v}}_cmp_lt_i32
; GCN: s_cbranch ; GCN: s_cbranch
; GCN: s_load_dword ; GCN: s_load_dword
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_cmp_{{eq|ne}}_u32_e64 ; GCN-NEXT: s_cmp_lg_u32
; GCN-NEXT: s_cselect_b64
; GCN: s_cbranch_vccz [[BB2:BB[0-9]_[0-9]+]] ; GCN: s_cbranch_vccz [[BB2:BB[0-9]_[0-9]+]]
; GCN-NEXT: [[LONGBB1:BB[0-9]+_[0-9]+]]: ; GCN-NEXT: [[LONGBB1:BB[0-9]+_[0-9]+]]:
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}} ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}
; GCN-NEXT: s_add_u32 s[[PC1_LO]], s[[PC1_LO]], [[BB3:BB[0-9]+_[0-9]+]]-([[LONGBB1]]+4) ; GCN-NEXT: s_add_u32 s[[PC1_LO]], s[[PC1_LO]], [[BB3:BB[0-9]+_[0-9]+]]-([[LONGBB1]]+4)
; GCN-NEXT: s_addc_u32 s[[PC1_HI]], s[[PC1_HI]], 0{{$}} ; GCN-NEXT: s_addc_u32 s[[PC1_HI]], s[[PC1_HI]], 0{{$}}
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC1_LO]]:[[PC1_HI]]{{\]}} ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC1_LO]]:[[PC1_HI]]{{\]}}
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; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, [[LONG_BR_DEST0:BB[0-9]+_[0-9]+]]-( ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, [[LONG_BR_DEST0:BB[0-9]+_[0-9]+]]-(
; GCN-NEXT: s_addc_u32 ; GCN-NEXT: s_addc_u32
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
; GCN-NEXT: [[LONG_BR_0]]: ; GCN-NEXT: [[LONG_BR_0]]:
; GCN: [[LONG_BR_DEST0]]: ; GCN: [[LONG_BR_DEST0]]:
; GCN-DAG: v_cmp_lt_i32 ; GCN-DAG: s_cmp_lt_i32
; GCN-DAG: v_cmp_ge_i32 ; GCN-DAG: s_cmp_ge_i32
; GCN: s_cbranch_vccz ; GCN: s_cbranch_vccz
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @long_branch_hang(i32 addrspace(1)* nocapture %arg, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i64 %arg5) #0 { define amdgpu_kernel void @long_branch_hang(i32 addrspace(1)* nocapture %arg, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i64 %arg5) #0 {
bb: bb:
%tmp = icmp slt i32 %arg2, 9 %tmp = icmp slt i32 %arg2, 9
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llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i1 @llvm.amdgcn.class.f32(float, i32) declare i1 @llvm.amdgcn.class.f32(float, i32)
; Produces error after adding an implicit def to v_cndmask_b32 ; Produces error after adding an implicit def to v_cndmask_b32
; GCN-LABEL: {{^}}vcc_shrink_vcc_def: ; GCN-LABEL: {{^}}vcc_shrink_vcc_def:
; GCN: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}} ; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}}
; GCN: s_cselect_b64 vcc, -1, 0
; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc
define amdgpu_kernel void @vcc_shrink_vcc_def(float %arg, i32 %arg1, float %arg2, i32 %arg3) { define amdgpu_kernel void @vcc_shrink_vcc_def(float %arg, i32 %arg1, float %arg2, i32 %arg3) {
bb0: bb0:
%tmp = icmp sgt i32 %arg1, 4 %tmp = icmp sgt i32 %arg1, 4
%c = icmp eq i32 %arg3, 0 %c = icmp eq i32 %arg3, 0
%tmp4 = select i1 %c, float %arg, float 1.000000e+00 %tmp4 = select i1 %c, float %arg, float 1.000000e+00
%tmp5 = fcmp ogt float %arg2, 0.000000e+00 %tmp5 = fcmp ogt float %arg2, 0.000000e+00
%tmp6 = fcmp olt float %arg2, 1.000000e+00 %tmp6 = fcmp olt float %arg2, 1.000000e+00
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llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; optnone disables AMDGPUAnnotateUniformValues, so no branch is known ; optnone disables AMDGPUAnnotateUniformValues, so no branch is known
; to be uniform during instruction selection. The custom selection for ; to be uniform during instruction selection. The custom selection for
; brcond was not checking if the branch was uniform, relying on the ; brcond was not checking if the branch was uniform, relying on the
; selection pattern to check that. That would fail, so then the branch ; selection pattern to check that. That would fail, so then the branch
; would fail to select. ; would fail to select.
; GCN-LABEL: {{^}}copytoreg_divergent_brcond: ; GCN-LABEL: {{^}}copytoreg_divergent_brcond:
; GCN: s_branch ; GCN: s_branch
; GCN-DAG: v_cmp_lt_i32 ; GCN-DAG: v_cmp_lt_i32
; GCN-DAG: v_cmp_gt_i32 ; GCN-DAG: s_cmp_gt_i32
; GCN: s_and_b64 ; GCN: s_and_b64
; GCN: s_mov_b64 exec ; GCN: s_mov_b64 exec
; GCN: s_or_b64 exec, exec ; GCN: s_or_b64 exec, exec
; GCN: {{[s|v]}}_cmp_eq_u32 ; GCN: {{[s|v]}}_cmp_eq_u32
; GCN: s_cbranch ; GCN: s_cbranch
; GCN-NEXT: s_branch ; GCN-NEXT: s_branch
define amdgpu_kernel void @copytoreg_divergent_brcond(i32 %arg, i32 %arg1, i32 %arg2) #0 { define amdgpu_kernel void @copytoreg_divergent_brcond(i32 %arg, i32 %arg1, i32 %arg2) #0 {
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llvm/test/CodeGen/AMDGPU/ctlz.ll

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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
define amdgpu_kernel void @s_ctlz_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { define amdgpu_kernel void @s_ctlz_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
; SI-LABEL: s_ctlz_i32: ; SI-LABEL: s_ctlz_i32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dword s4, s[0:1], 0xb ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_flbit_i32_b32 s5, s4 ; SI-NEXT: s_flbit_i32_b32 s5, s4
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_mov_b32_e32 v0, s5 ; SI-NEXT: v_mov_b32_e32 v0, s5
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v0, 32, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, 32, v0, vcc
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: s_ctlz_i32: ; VI-LABEL: s_ctlz_i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; VI-NEXT: s_load_dword s0, s[0:1], 0x2c ; VI-NEXT: s_load_dword s0, s[0:1], 0x2c
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; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
; VI-NEXT: s_mov_b32 s7, 0xf000 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_mov_b32 s2, s6 ; VI-NEXT: s_mov_b32 s2, s6
; VI-NEXT: s_mov_b32 s3, s7 ; VI-NEXT: s_mov_b32 s3, s7
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 ; VI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_ffbh_u32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; VI-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0 ; VI-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc ; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: v_ffbh_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_cndmask_b32_e32 v0, 32, v0, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, -16, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, -16, v0
; VI-NEXT: v_add_u16_e32 v0, -8, v0 ; VI-NEXT: v_add_u16_e32 v0, -8, v0
; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0 ; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; EG-LABEL: v_ctlz_i8: ; EG-LABEL: v_ctlz_i8:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
Show All 27 Lines
; GFX10-LABEL: v_ctlz_i8: ; GFX10-LABEL: v_ctlz_i8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_ubyte v1, v0, s[2:3] ; GFX10-NEXT: global_load_ubyte v1, v0, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_ffbh_u32_sdwa v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX10-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v1 ; GFX10-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v1
; GFX10-NEXT: v_cndmask_b32_e32 v1, 32, v2, vcc_lo ; GFX10-NEXT: v_ffbh_u32_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX10-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX10-NEXT: v_cndmask_b32_e32 v1, 32, v1, vcc_lo
; GFX10-NEXT: v_add_nc_u32_e32 v1, -16, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v1, -16, v1
; GFX10-NEXT: v_add_nc_u16 v1, v1, -8 ; GFX10-NEXT: v_add_nc_u16 v1, v1, -8
; GFX10-NEXT: global_store_byte v0, v1, s[0:1] ; GFX10-NEXT: global_store_byte v0, v1, s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%val = load i8, i8 addrspace(1)* %valptr %val = load i8, i8 addrspace(1)* %valptr
%ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 false) nounwind readnone %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 false) nounwind readnone
store i8 %ctlz, i8 addrspace(1)* %out store i8 %ctlz, i8 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @s_ctlz_i64(i64 addrspace(1)* noalias %out, [8 x i32], i64 %val) nounwind { define amdgpu_kernel void @s_ctlz_i64(i64 addrspace(1)* noalias %out, [8 x i32], i64 %val) nounwind {
; SI-LABEL: s_ctlz_i64: ; SI-LABEL: s_ctlz_i64:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x13 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x13
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_flbit_i32_b32 s6, s4 ; SI-NEXT: s_flbit_i32_b32 s6, s4
; SI-NEXT: s_flbit_i32_b32 s7, s5 ; SI-NEXT: s_flbit_i32_b32 s7, s5
; SI-NEXT: s_add_i32 s6, s6, 32 ; SI-NEXT: s_add_i32 s6, s6, 32
; SI-NEXT: s_or_b32 s4, s4, s5
; SI-NEXT: v_mov_b32_e32 v0, s7 ; SI-NEXT: v_mov_b32_e32 v0, s7
; SI-NEXT: s_cmp_eq_u32 s5, 0
; SI-NEXT: v_mov_b32_e32 v1, s6 ; SI-NEXT: v_mov_b32_e32 v1, s6
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s5, 0 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 ; SI-NEXT: s_or_b32 s4, s4, s5
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: s_ctlz_i64: ; VI-LABEL: s_ctlz_i64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
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; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_flbit_i32_b32 s6, s4 ; SI-NEXT: s_flbit_i32_b32 s6, s4
; SI-NEXT: s_flbit_i32_b32 s7, s5 ; SI-NEXT: s_flbit_i32_b32 s7, s5
; SI-NEXT: s_add_i32 s6, s6, 32 ; SI-NEXT: s_add_i32 s6, s6, 32
; SI-NEXT: s_or_b32 s4, s4, s5
; SI-NEXT: v_mov_b32_e32 v0, s7 ; SI-NEXT: v_mov_b32_e32 v0, s7
; SI-NEXT: s_cmp_eq_u32 s5, 0
; SI-NEXT: v_mov_b32_e32 v1, s6 ; SI-NEXT: v_mov_b32_e32 v1, s6
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s5, 0 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 ; SI-NEXT: s_or_b32 s4, s4, s5
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: s_ctlz_i64_trunc: ; VI-LABEL: s_ctlz_i64_trunc:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
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llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_ctlz_zero_undef_i8(i8 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %valptr) nounwind {
%val = load i8, i8 addrspace(1)* %in.gep %val = load i8, i8 addrspace(1)* %in.gep
%ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 true) nounwind readnone %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 true) nounwind readnone
store i8 %ctlz, i8 addrspace(1)* %out store i8 %ctlz, i8 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i64: ; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i64:
; GCN: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}} ; GCN: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
; SI-DAG: v_cmp_eq_u32_e64 vcc, s[[HI]], 0{{$}} ; SI-DAG: s_cmp_eq_u32 s[[HI]], 0{{$}}
; SI-DAG: s_cselect_b64 vcc, -1, 0
; VI-DAG: s_cmp_eq_u32 s[[HI]], 0{{$}} ; VI-DAG: s_cmp_eq_u32 s[[HI]], 0{{$}}
; GCN-DAG: s_flbit_i32_b32 [[FFBH_LO:s[0-9]+]], s[[LO]] ; GCN-DAG: s_flbit_i32_b32 [[FFBH_LO:s[0-9]+]], s[[LO]]
; GCN-DAG: s_add_i32 [[ADD:s[0-9]+]], [[FFBH_LO]], 32 ; GCN-DAG: s_add_i32 [[ADD:s[0-9]+]], [[FFBH_LO]], 32
; GCN-DAG: s_flbit_i32_b32 [[FFBH_HI:s[0-9]+]], s[[HI]] ; GCN-DAG: s_flbit_i32_b32 [[FFBH_HI:s[0-9]+]], s[[HI]]
; SI-DAG: v_mov_b32_e32 [[VFFBH_LO:v[0-9]+]], [[ADD]] ; SI-DAG: v_mov_b32_e32 [[VFFBH_LO:v[0-9]+]], [[ADD]]
; SI-DAG: v_mov_b32_e32 [[VFFBH_HI:v[0-9]+]], [[FFBH_HI]] ; SI-DAG: v_mov_b32_e32 [[VFFBH_HI:v[0-9]+]], [[FFBH_HI]]
; SI-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]] ; SI-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]]
; VI-DAG: s_cselect_b32 [[RES:s[0-9]+]], [[ADD]], [[FFBH_HI]] ; VI-DAG: s_cselect_b32 [[RES:s[0-9]+]], [[ADD]], [[FFBH_HI]]
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llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx704 < %s | FileCheck -check-prefix=GFX7 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx704 < %s | FileCheck -check-prefix=GFX7 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
define i32 @s_add_co_select_user() { define i32 @s_add_co_select_user() {
; GFX7-LABEL: s_add_co_select_user: ; GFX7-LABEL: s_add_co_select_user:
; GFX7: ; %bb.0: ; %bb ; GFX7: ; %bb.0: ; %bb
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_mov_b64 s[4:5], 0 ; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: s_load_dword s6, s[4:5], 0x0 ; GFX7-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_add_i32_e64 v0, s[4:5], s6, s6 ; GFX7-NEXT: v_add_i32_e64 v0, s[4:5], s6, s6
; GFX7-NEXT: s_or_b32 s4, s4, s5 ; GFX7-NEXT: s_or_b32 s4, s4, s5
; GFX7-NEXT: s_cmp_lg_u32 s4, 0 ; GFX7-NEXT: s_cmp_lg_u32 s4, 0
; GFX7-NEXT: s_addc_u32 s4, s6, 0 ; GFX7-NEXT: s_addc_u32 s4, s6, 0
; GFX7-NEXT: v_mov_b32_e32 v1, s4
; GFX7-NEXT: s_cselect_b64 vcc, 1, 0 ; GFX7-NEXT: s_cselect_b64 vcc, 1, 0
; GFX7-NEXT: v_mov_b32_e32 v1, s4
; GFX7-NEXT: s_cmp_gt_u32 s6, 31
; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX7-NEXT: v_cmp_gt_u32_e64 vcc, s6, 31 ; GFX7-NEXT: s_cselect_b64 vcc, -1, 0
; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31] ; GFX7-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: s_add_co_select_user: ; GFX9-LABEL: s_add_co_select_user:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b64 s[4:5], 0 ; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_load_dword s6, s[4:5], 0x0 ; GFX9-NEXT: s_load_dword s6, s[4:5], 0x0
Show All 37 Linesbb:
%i8 = icmp ugt i32 %i, 31 %i8 = icmp ugt i32 %i, 31
%i9 = select i1 %i8, i32 %i1, i32 %i7 %i9 = select i1 %i8, i32 %i1, i32 %i7
ret i32 %i9 ret i32 %i9
} }
define amdgpu_kernel void @s_add_co_br_user(i32 %i) { define amdgpu_kernel void @s_add_co_br_user(i32 %i) {
; GFX7-LABEL: s_add_co_br_user: ; GFX7-LABEL: s_add_co_br_user:
; GFX7: ; %bb.0: ; %bb ; GFX7: ; %bb.0: ; %bb
; GFX7-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX7-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_add_i32 s1, s0, s0 ; GFX7-NEXT: s_add_i32 s0, s2, s2
; GFX7-NEXT: v_mov_b32_e32 v0, s0 ; GFX7-NEXT: s_cmp_lt_u32 s0, s2
; GFX7-NEXT: v_cmp_lt_u32_e32 vcc, s1, v0 ; GFX7-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX7-NEXT: s_or_b32 s1, vcc_lo, vcc_hi ; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX7-NEXT: s_cmp_lg_u32 s1, 0 ; GFX7-NEXT: s_or_b32 s0, s0, s1
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7-NEXT: s_cmp_lg_u32 s0, 0
; GFX7-NEXT: s_addc_u32 s0, s0, 0 ; GFX7-NEXT: s_addc_u32 s0, s2, 0
; GFX7-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0 ; GFX7-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
; GFX7-NEXT: s_and_b64 vcc, exec, vcc ; GFX7-NEXT: s_and_b64 vcc, exec, vcc
; GFX7-NEXT: s_cbranch_vccnz BB1_2 ; GFX7-NEXT: s_cbranch_vccnz BB1_2
; GFX7-NEXT: ; %bb.1: ; %bb0 ; GFX7-NEXT: ; %bb.1: ; %bb0
; GFX7-NEXT: v_mov_b32_e32 v0, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
; GFX7-NEXT: v_mov_b32_e32 v1, 0 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
; GFX7-NEXT: v_mov_b32_e32 v2, 9 ; GFX7-NEXT: v_mov_b32_e32 v2, 9
; GFX7-NEXT: flat_store_dword v[0:1], v2 ; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: BB1_2: ; %bb1 ; GFX7-NEXT: BB1_2: ; %bb1
; GFX7-NEXT: v_mov_b32_e32 v0, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
; GFX7-NEXT: v_mov_b32_e32 v1, 0 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
; GFX7-NEXT: v_mov_b32_e32 v2, 10 ; GFX7-NEXT: v_mov_b32_e32 v2, 10
; GFX7-NEXT: flat_store_dword v[0:1], v2 ; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX9-LABEL: s_add_co_br_user: ; GFX9-LABEL: s_add_co_br_user:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX9-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_add_i32 s1, s0, s0 ; GFX9-NEXT: s_add_i32 s0, s2, s2
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: s_cmp_lt_u32 s0, s2
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s1, v0 ; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX9-NEXT: s_addc_u32 s0, s0, 0 ; GFX9-NEXT: s_addc_u32 s0, s2, 0
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
; GFX9-NEXT: s_and_b64 vcc, exec, vcc ; GFX9-NEXT: s_and_b64 vcc, exec, vcc
; GFX9-NEXT: s_cbranch_vccnz BB1_2 ; GFX9-NEXT: s_cbranch_vccnz BB1_2
; GFX9-NEXT: ; %bb.1: ; %bb0 ; GFX9-NEXT: ; %bb.1: ; %bb0
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, 9 ; GFX9-NEXT: v_mov_b32_e32 v2, 9
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB1_2: ; %bb1 ; GFX9-NEXT: BB1_2: ; %bb1
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, 10 ; GFX9-NEXT: v_mov_b32_e32 v2, 10
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: s_add_co_br_user: ; GFX10-LABEL: s_add_co_br_user:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX10-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_add_i32 s1, s0, s0 ; GFX10-NEXT: s_add_i32 s1, s0, s0
; GFX10-NEXT: v_cmp_lt_u32_e64 s1, s1, s0 ; GFX10-NEXT: s_cmp_lt_u32 s1, s0
; GFX10-NEXT: s_cselect_b32 s1, -1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
; GFX10-NEXT: s_cmpk_lg_u32 s1, 0x0 ; GFX10-NEXT: s_cmpk_lg_u32 s1, 0x0
; GFX10-NEXT: s_addc_u32 s0, s0, 0 ; GFX10-NEXT: s_addc_u32 s0, s0, 0
; GFX10-NEXT: v_cmp_ge_u32_e32 vcc_lo, s0, v0 ; GFX10-NEXT: v_cmp_ge_u32_e32 vcc_lo, s0, v0
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo ; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
; GFX10-NEXT: s_cbranch_vccnz BB1_2 ; GFX10-NEXT: s_cbranch_vccnz BB1_2
; GFX10-NEXT: ; %bb.1: ; %bb0 ; GFX10-NEXT: ; %bb.1: ; %bb0
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
Show All 29 Lines

llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll

; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s
; GCN-LABEL: {{^}}float4_extelt: ; GCN-LABEL: {{^}}float4_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2 ; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 2
; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 3
; GCN-DAG: s_cselect_b64 [[C3:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 0, 1.0, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 0, 1.0, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], 2.0, [[V1]], [[C2]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], 2.0, [[V1]], [[C2]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], 4.0, [[V2]], [[C3]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], 4.0, [[V2]], [[C3]]
; GCN: store_dword v[{{[0-9:]+}}], [[V3]] ; GCN: store_dword v[{{[0-9:]+}}], [[V3]]
define amdgpu_kernel void @float4_extelt(float addrspace(1)* %out, i32 %sel) { define amdgpu_kernel void @float4_extelt(float addrspace(1)* %out, i32 %sel) {
entry: entry:
%ext = extractelement <4 x float> <float 0.0, float 1.0, float 2.0, float 4.0>, i32 %sel %ext = extractelement <4 x float> <float 0.0, float 1.0, float 2.0, float 4.0>, i32 %sel
store float %ext, float addrspace(1)* %out store float %ext, float addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}int4_extelt: ; GCN-LABEL: {{^}}int4_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: s_cmp_lg_u32 [[IDX:s[0-9]+]], 2 ; GCN-DAG: s_cmp_lg_u32 [[IDX:s[0-9]+]], 2
; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 1
; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 3 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 3
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 0, 1, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 0, 1, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], 2, [[V1]], vcc ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], 2, [[V1]], vcc
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], 4, [[V2]], vcc ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], 4, [[V2]], vcc
; GCN: store_dword v[{{[0-9:]+}}], [[V3]] ; GCN: store_dword v[{{[0-9:]+}}], [[V3]]
define amdgpu_kernel void @int4_extelt(i32 addrspace(1)* %out, i32 %sel) { define amdgpu_kernel void @int4_extelt(i32 addrspace(1)* %out, i32 %sel) {
entry: entry:
%ext = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 4>, i32 %sel %ext = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 4>, i32 %sel
store i32 %ext, i32 addrspace(1)* %out store i32 %ext, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}double4_extelt: ; GCN-LABEL: {{^}}double4_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: v_cmp_eq_u32_e64 [[C2:[^,]+]], [[IDX]], 2 ; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0
; GCN-DAG: v_cmp_eq_u32_e64 [[C3:[^,]+]], [[IDX]], 3 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2
; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0
; GCN-DAG: s_cmp_eq_u32 [[IDX]], 3
; GCN-DAG: s_cselect_b64 [[C3:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C2]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C2]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C3]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C3]]
; GCN: store_dwordx2 v[{{[0-9:]+}}] ; GCN: store_dwordx2 v[{{[0-9:]+}}]
define amdgpu_kernel void @double4_extelt(double addrspace(1)* %out, i32 %sel) { define amdgpu_kernel void @double4_extelt(double addrspace(1)* %out, i32 %sel) {
entry: entry:
%ext = extractelement <4 x double> <double 0.01, double 1.01, double 2.01, double 4.01>, i32 %sel %ext = extractelement <4 x double> <double 0.01, double 1.01, double 2.01, double 4.01>, i32 %sel
store double %ext, double addrspace(1)* %out store double %ext, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}double5_extelt: ; GCN-LABEL: {{^}}double5_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: v_cmp_eq_u32_e64 [[C2:[^,]+]], [[IDX]], 2 ; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0
; GCN-DAG: v_cmp_eq_u32_e64 [[C3:[^,]+]], [[IDX]], 3 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2
; GCN-DAG: v_cmp_eq_u32_e64 [[C4:[^,]+]], [[IDX]], 4 ; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0
; GCN-DAG: s_cmp_eq_u32 [[IDX]], 3
; GCN-DAG: s_cselect_b64 [[C3:[^,]+]], -1, 0
; GCN-DAG: s_cmp_eq_u32 [[IDX]], 4
; GCN-DAG: s_cselect_b64 [[C4:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C2]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C2]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C3]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C3]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C4]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C4]]
; GCN: store_dwordx2 v[{{[0-9:]+}}] ; GCN: store_dwordx2 v[{{[0-9:]+}}]
define amdgpu_kernel void @double5_extelt(double addrspace(1)* %out, i32 %sel) { define amdgpu_kernel void @double5_extelt(double addrspace(1)* %out, i32 %sel) {
entry: entry:
%ext = extractelement <5 x double> <double 0.01, double 1.01, double 2.01, double 4.01, double 5.01>, i32 %sel %ext = extractelement <5 x double> <double 0.01, double 1.01, double 2.01, double 4.01, double 5.01>, i32 %sel
Show All 13 Lines
entry: entry:
%ext = extractelement <4 x half> <half 1.0, half 2.0, half 3.0, half 4.0>, i32 %sel %ext = extractelement <4 x half> <half 1.0, half 2.0, half 3.0, half 4.0>, i32 %sel
store half %ext, half addrspace(1)* %out store half %ext, half addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}float2_extelt: ; GCN-LABEL: {{^}}float2_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 0, 1.0, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 0, 1.0, [[C1]]
; GCN: store_dword v[{{[0-9:]+}}], [[V1]] ; GCN: store_dword v[{{[0-9:]+}}], [[V1]]
define amdgpu_kernel void @float2_extelt(float addrspace(1)* %out, i32 %sel) { define amdgpu_kernel void @float2_extelt(float addrspace(1)* %out, i32 %sel) {
entry: entry:
%ext = extractelement <2 x float> <float 0.0, float 1.0>, i32 %sel %ext = extractelement <2 x float> <float 0.0, float 1.0>, i32 %sel
store float %ext, float addrspace(1)* %out store float %ext, float addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}double2_extelt: ; GCN-LABEL: {{^}}double2_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]]
; GCN: store_dwordx2 v[{{[0-9:]+}}] ; GCN: store_dwordx2 v[{{[0-9:]+}}]
define amdgpu_kernel void @double2_extelt(double addrspace(1)* %out, i32 %sel) { define amdgpu_kernel void @double2_extelt(double addrspace(1)* %out, i32 %sel) {
entry: entry:
%ext = extractelement <2 x double> <double 0.01, double 1.01>, i32 %sel %ext = extractelement <2 x double> <double 0.01, double 1.01>, i32 %sel
store double %ext, double addrspace(1)* %out store double %ext, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}half8_extelt: ; GCN-LABEL: {{^}}half8_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2 ; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 2
; GCN-DAG: v_cmp_ne_u32_e64 [[C4:[^,]+]], [[IDX]], 4 ; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C5:[^,]+]], [[IDX]], 5 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 3
; GCN-DAG: v_cmp_ne_u32_e64 [[C6:[^,]+]], [[IDX]], 6 ; GCN-DAG: s_cselect_b64 [[C3:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C7:[^,]+]], [[IDX]], 7 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 4
; GCN-DAG: s_cselect_b64 [[C4:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 5
; GCN-DAG: s_cselect_b64 [[C5:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 6
; GCN-DAG: s_cselect_b64 [[C6:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 7
; GCN-DAG: s_cselect_b64 [[C7:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], {{[^,]+}}, {{[^,]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], {{[^,]+}}, {{[^,]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], {{[^,]+}}, [[V1]], [[C2]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], {{[^,]+}}, [[V1]], [[C2]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], {{[^,]+}}, [[V2]], [[C3]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], {{[^,]+}}, [[V2]], [[C3]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V4:v[0-9]+]], {{[^,]+}}, [[V3]], [[C4]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V4:v[0-9]+]], {{[^,]+}}, [[V3]], [[C4]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V5:v[0-9]+]], {{[^,]+}}, [[V4]], [[C5]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V5:v[0-9]+]], {{[^,]+}}, [[V4]], [[C5]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V6:v[0-9]+]], {{[^,]+}}, [[V5]], [[C6]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V6:v[0-9]+]], {{[^,]+}}, [[V5]], [[C6]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V7:v[0-9]+]], {{[^,]+}}, [[V6]], [[C7]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V7:v[0-9]+]], {{[^,]+}}, [[V6]], [[C7]]
; GCN: store_short v[{{[0-9:]+}}], [[V7]] ; GCN: store_short v[{{[0-9:]+}}], [[V7]]
define amdgpu_kernel void @half8_extelt(half addrspace(1)* %out, i32 %sel) { define amdgpu_kernel void @half8_extelt(half addrspace(1)* %out, i32 %sel) {
entry: entry:
%ext = extractelement <8 x half> <half 1.0, half 2.0, half 3.0, half 4.0, half 5.0, half 6.0, half 7.0, half 8.0>, i32 %sel %ext = extractelement <8 x half> <half 1.0, half 2.0, half 3.0, half 4.0, half 5.0, half 6.0, half 7.0, half 8.0>, i32 %sel
store half %ext, half addrspace(1)* %out store half %ext, half addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}short8_extelt: ; GCN-LABEL: {{^}}short8_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2 ; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 2
; GCN-DAG: v_cmp_ne_u32_e64 [[C4:[^,]+]], [[IDX]], 4 ; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C5:[^,]+]], [[IDX]], 5 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 3
; GCN-DAG: v_cmp_ne_u32_e64 [[C6:[^,]+]], [[IDX]], 6 ; GCN-DAG: s_cselect_b64 [[C3:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C7:[^,]+]], [[IDX]], 7 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 4
; GCN-DAG: s_cselect_b64 [[C4:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 5
; GCN-DAG: s_cselect_b64 [[C5:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 6
; GCN-DAG: s_cselect_b64 [[C6:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 7
; GCN-DAG: s_cselect_b64 [[C7:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], {{[^,]+}}, {{[^,]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], {{[^,]+}}, {{[^,]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], {{[^,]+}}, [[V1]], [[C2]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], {{[^,]+}}, [[V1]], [[C2]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], {{[^,]+}}, [[V2]], [[C3]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], {{[^,]+}}, [[V2]], [[C3]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V4:v[0-9]+]], {{[^,]+}}, [[V3]], [[C4]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V4:v[0-9]+]], {{[^,]+}}, [[V3]], [[C4]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V5:v[0-9]+]], {{[^,]+}}, [[V4]], [[C5]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V5:v[0-9]+]], {{[^,]+}}, [[V4]], [[C5]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V6:v[0-9]+]], {{[^,]+}}, [[V5]], [[C6]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V6:v[0-9]+]], {{[^,]+}}, [[V5]], [[C6]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V7:v[0-9]+]], {{[^,]+}}, [[V6]], [[C7]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V7:v[0-9]+]], {{[^,]+}}, [[V6]], [[C7]]
; GCN: store_short v[{{[0-9:]+}}], [[V7]] ; GCN: store_short v[{{[0-9:]+}}], [[V7]]
define amdgpu_kernel void @short8_extelt(i16 addrspace(1)* %out, i32 %sel) { define amdgpu_kernel void @short8_extelt(i16 addrspace(1)* %out, i32 %sel) {
entry: entry:
%ext = extractelement <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i32 %sel %ext = extractelement <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i32 %sel
store i16 %ext, i16 addrspace(1)* %out store i16 %ext, i16 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}float8_extelt: ; GCN-LABEL: {{^}}float8_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2 ; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 2
; GCN-DAG: v_cmp_ne_u32_e64 [[C4:[^,]+]], [[IDX]], 4 ; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C5:[^,]+]], [[IDX]], 5 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 3
; GCN-DAG: v_cmp_ne_u32_e64 [[C6:[^,]+]], [[IDX]], 6 ; GCN-DAG: s_cselect_b64 [[C3:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C7:[^,]+]], [[IDX]], 7 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 4
; GCN-DAG: s_cselect_b64 [[C4:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 5
; GCN-DAG: s_cselect_b64 [[C5:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 6
; GCN-DAG: s_cselect_b64 [[C6:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 7
; GCN-DAG: s_cselect_b64 [[C7:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], {{[^,]+}}, {{[^,]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], {{[^,]+}}, {{[^,]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], {{[^,]+}}, [[V1]], [[C2]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], {{[^,]+}}, [[V1]], [[C2]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], {{[^,]+}}, [[V2]], [[C3]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], {{[^,]+}}, [[V2]], [[C3]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V4:v[0-9]+]], {{[^,]+}}, [[V3]], [[C4]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V4:v[0-9]+]], {{[^,]+}}, [[V3]], [[C4]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V5:v[0-9]+]], {{[^,]+}}, [[V4]], [[C5]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V5:v[0-9]+]], {{[^,]+}}, [[V4]], [[C5]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V6:v[0-9]+]], {{[^,]+}}, [[V5]], [[C6]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V6:v[0-9]+]], {{[^,]+}}, [[V5]], [[C6]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V7:v[0-9]+]], {{[^,]+}}, [[V6]], [[C7]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V7:v[0-9]+]], {{[^,]+}}, [[V6]], [[C7]]
; GCN: store_dword v[{{[0-9:]+}}], [[V7]] ; GCN: store_dword v[{{[0-9:]+}}], [[V7]]
▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines
entry: entry:
%ext = extractelement <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i32 %sel %ext = extractelement <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i32 %sel
store i8 %ext, i8 addrspace(1)* %out store i8 %ext, i8 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}byte16_extelt: ; GCN-LABEL: {{^}}byte16_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2 ; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 2
; GCN-DAG: v_cmp_ne_u32_e64 [[C4:[^,]+]], [[IDX]], 4 ; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C5:[^,]+]], [[IDX]], 5 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 3
; GCN-DAG: v_cmp_ne_u32_e64 [[C6:[^,]+]], [[IDX]], 6 ; GCN-DAG: s_cselect_b64 [[C3:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C7:[^,]+]], [[IDX]], 7 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 4
; GCN-DAG: v_cmp_ne_u32_e64 [[C8:[^,]+]], [[IDX]], 8 ; GCN-DAG: s_cselect_b64 [[C4:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C9:[^,]+]], [[IDX]], 9 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 5
; GCN-DAG: v_cmp_ne_u32_e64 [[C10:[^,]+]], [[IDX]], 10 ; GCN-DAG: s_cselect_b64 [[C5:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C11:[^,]+]], [[IDX]], 11 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 6
; GCN-DAG: v_cmp_ne_u32_e64 [[C12:[^,]+]], [[IDX]], 12 ; GCN-DAG: s_cselect_b64 [[C6:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C13:[^,]+]], [[IDX]], 13 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 7
; GCN-DAG: v_cmp_ne_u32_e64 [[C14:[^,]+]], [[IDX]], 14 ; GCN-DAG: s_cselect_b64 [[C7:[^,]+]], -1, 0
; GCN-DAG: v_cmp_ne_u32_e64 [[C15:[^,]+]], [[IDX]], 15 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 8
; GCN-DAG: s_cselect_b64 [[C8:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 9
; GCN-DAG: s_cselect_b64 [[C9:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 10
; GCN-DAG: s_cselect_b64 [[C10:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 11
; GCN-DAG: s_cselect_b64 [[C11:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 12
; GCN-DAG: s_cselect_b64 [[C12:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 13
; GCN-DAG: s_cselect_b64 [[C13:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 14
; GCN-DAG: s_cselect_b64 [[C14:[^,]+]], -1, 0
; GCN-DAG: s_cmp_lg_u32 [[IDX]], 15
; GCN-DAG: s_cselect_b64 [[C15:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], {{[^,]+}}, {{[^,]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], {{[^,]+}}, {{[^,]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], {{[^,]+}}, [[V1]], [[C2]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], {{[^,]+}}, [[V1]], [[C2]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], {{[^,]+}}, [[V2]], [[C3]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], {{[^,]+}}, [[V2]], [[C3]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V4:v[0-9]+]], {{[^,]+}}, [[V3]], [[C4]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V4:v[0-9]+]], {{[^,]+}}, [[V3]], [[C4]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V5:v[0-9]+]], {{[^,]+}}, [[V4]], [[C5]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V5:v[0-9]+]], {{[^,]+}}, [[V4]], [[C5]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V6:v[0-9]+]], {{[^,]+}}, [[V5]], [[C6]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V6:v[0-9]+]], {{[^,]+}}, [[V5]], [[C6]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V7:v[0-9]+]], {{[^,]+}}, [[V6]], [[C7]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V7:v[0-9]+]], {{[^,]+}}, [[V6]], [[C7]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V8:v[0-9]+]], {{[^,]+}}, [[V7]], [[C8]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V8:v[0-9]+]], {{[^,]+}}, [[V7]], [[C8]]
Show All 28 Linesentry:
%zext = zext i1 %ext to i32 %zext = zext i1 %ext to i32
store i32 %zext, i32 addrspace(1)* %out store i32 %zext, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}bit128_extelt: ; GCN-LABEL: {{^}}bit128_extelt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 0, 1 ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 0, 1
; GCN-DAG: v_mov_b32_e32 [[LASTIDX:v[0-9]+]], 0x7f ; GCN: s_cmpk_lg_i32 {{s[0-9]+}}, 0x7f
; GCN-DAG: v_cmp_ne_u32_e32 [[CL:[^,]+]], s{{[0-9]+}}, [[LASTIDX]] ; GCN: s_cselect_b64 [[CL:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e{{32|64}} [[VL:v[0-9]+]], 0, [[V1]], [[CL]] ; GCN: v_cndmask_b32_e{{32|64}} [[VL:v[0-9]+]], 0, [[V1]], [[CL]]
; GCN: v_and_b32_e32 [[RES:v[0-9]+]], 1, [[VL]] ; GCN: v_and_b32_e32 [[RES:v[0-9]+]], 1, [[VL]]
; GCN: store_dword v[{{[0-9:]+}}], [[RES]] ; GCN: store_dword v[{{[0-9:]+}}], [[RES]]
define amdgpu_kernel void @bit128_extelt(i32 addrspace(1)* %out, i32 %sel) { define amdgpu_kernel void @bit128_extelt(i32 addrspace(1)* %out, i32 %sel) {
entry: entry:
%ext = extractelement <128 x i1> <i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0>, i32 %sel %ext = extractelement <128 x i1> <i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0>, i32 %sel
%zext = zext i1 %ext to i32 %zext = zext i1 %ext to i32
store i32 %zext, i32 addrspace(1)* %out store i32 %zext, i32 addrspace(1)* %out
ret void ret void
Show All 29 Lines

llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; GCN-LABEL: {{^}}extract_vector_elt_v3f64_2: ; GCN-LABEL: {{^}}extract_vector_elt_v3f64_2:
; GCN: buffer_load_dwordx4 ; GCN: buffer_load_dwordx4
; GCN: buffer_load_dwordx2 ; GCN: buffer_load_dwordx2
; GCN: buffer_store_dwordx2 ; GCN: buffer_store_dwordx2
define amdgpu_kernel void @extract_vector_elt_v3f64_2(double addrspace(1)* %out, <3 x double> addrspace(1)* %in) #0 { define amdgpu_kernel void @extract_vector_elt_v3f64_2(double addrspace(1)* %out, <3 x double> addrspace(1)* %in) #0 {
%ld = load volatile <3 x double>, <3 x double> addrspace(1)* %in %ld = load volatile <3 x double>, <3 x double> addrspace(1)* %in
%elt = extractelement <3 x double> %ld, i32 2 %elt = extractelement <3 x double> %ld, i32 2
store volatile double %elt, double addrspace(1)* %out store volatile double %elt, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}dyn_extract_vector_elt_v3f64: ; GCN-LABEL: {{^}}dyn_extract_vector_elt_v3f64:
; GCN-NOT: buffer_load ; GCN-NOT: buffer_load
; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: v_cmp_eq_u32_e64 [[C2:[^,]+]], [[IDX]], 2 ; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0
; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2
; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]]
; GCN: store_dwordx2 v[{{[0-9:]+}}] ; GCN: store_dwordx2 v[{{[0-9:]+}}]
define amdgpu_kernel void @dyn_extract_vector_elt_v3f64(double addrspace(1)* %out, <3 x double> %foo, i32 %elt) #0 { define amdgpu_kernel void @dyn_extract_vector_elt_v3f64(double addrspace(1)* %out, <3 x double> %foo, i32 %elt) #0 {
%dynelt = extractelement <3 x double> %foo, i32 %elt %dynelt = extractelement <3 x double> %foo, i32 %elt
store volatile double %dynelt, double addrspace(1)* %out store volatile double %dynelt, double addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}dyn_extract_vector_elt_v4f64: ; GCN-LABEL: {{^}}dyn_extract_vector_elt_v4f64:
; GCN-NOT: buffer_load ; GCN-NOT: buffer_load
; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: v_cmp_eq_u32_e64 [[C2:[^,]+]], [[IDX]], 2 ; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0
; GCN-DAG: v_cmp_eq_u32_e64 [[C3:[^,]+]], [[IDX]], 3 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2
; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0
; GCN-DAG: s_cmp_eq_u32 [[IDX]], 3
; GCN-DAG: s_cselect_b64 [[C3:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C3]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C3]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C3]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C3]]
; GCN: store_dwordx2 v[{{[0-9:]+}}] ; GCN: store_dwordx2 v[{{[0-9:]+}}]
define amdgpu_kernel void @dyn_extract_vector_elt_v4f64(double addrspace(1)* %out, <4 x double> %foo, i32 %elt) #0 { define amdgpu_kernel void @dyn_extract_vector_elt_v4f64(double addrspace(1)* %out, <4 x double> %foo, i32 %elt) #0 {
%dynelt = extractelement <4 x double> %foo, i32 %elt %dynelt = extractelement <4 x double> %foo, i32 %elt
store volatile double %dynelt, double addrspace(1)* %out store volatile double %dynelt, double addrspace(1)* %out
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll

Show All 25 Linesdefine amdgpu_kernel void @extract_vector_elt_v2i64(i64 addrspace(1)* %out, <2 x i64> %foo) #0 {
%out1 = getelementptr i64, i64 addrspace(1)* %out, i32 1 %out1 = getelementptr i64, i64 addrspace(1)* %out, i32 1
store volatile i64 %p1, i64 addrspace(1)* %out store volatile i64 %p1, i64 addrspace(1)* %out
store volatile i64 %p0, i64 addrspace(1)* %out1 store volatile i64 %p0, i64 addrspace(1)* %out1
ret void ret void
} }
; GCN-LABEL: {{^}}dyn_extract_vector_elt_v2i64: ; GCN-LABEL: {{^}}dyn_extract_vector_elt_v2i64:
; GCN-NOT: buffer_load ; GCN-NOT: buffer_load
; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]]
; GCN: store_dwordx2 v[{{[0-9:]+}}] ; GCN: store_dwordx2 v[{{[0-9:]+}}]
define amdgpu_kernel void @dyn_extract_vector_elt_v2i64(i64 addrspace(1)* %out, <2 x i64> %foo, i32 %elt) #0 { define amdgpu_kernel void @dyn_extract_vector_elt_v2i64(i64 addrspace(1)* %out, <2 x i64> %foo, i32 %elt) #0 {
%dynelt = extractelement <2 x i64> %foo, i32 %elt %dynelt = extractelement <2 x i64> %foo, i32 %elt
store volatile i64 %dynelt, i64 addrspace(1)* %out store volatile i64 %dynelt, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}dyn_extract_vector_elt_v2i64_2: ; GCN-LABEL: {{^}}dyn_extract_vector_elt_v2i64_2:
; GCN: buffer_load_dwordx4 ; GCN: buffer_load_dwordx4
; GCN-NOT: buffer_load ; GCN-NOT: buffer_load
; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]]
; GCN: store_dwordx2 v[{{[0-9:]+}}] ; GCN: store_dwordx2 v[{{[0-9:]+}}]
define amdgpu_kernel void @dyn_extract_vector_elt_v2i64_2(i64 addrspace(1)* %out, <2 x i64> addrspace(1)* %foo, i32 %elt, <2 x i64> %arst) #0 { define amdgpu_kernel void @dyn_extract_vector_elt_v2i64_2(i64 addrspace(1)* %out, <2 x i64> addrspace(1)* %foo, i32 %elt, <2 x i64> %arst) #0 {
%load = load volatile <2 x i64>, <2 x i64> addrspace(1)* %foo %load = load volatile <2 x i64>, <2 x i64> addrspace(1)* %foo
%or = or <2 x i64> %load, %arst %or = or <2 x i64> %load, %arst
%dynelt = extractelement <2 x i64> %or, i32 %elt %dynelt = extractelement <2 x i64> %or, i32 %elt
store volatile i64 %dynelt, i64 addrspace(1)* %out store volatile i64 %dynelt, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}dyn_extract_vector_elt_v3i64: ; GCN-LABEL: {{^}}dyn_extract_vector_elt_v3i64:
; GCN-NOT: buffer_load ; GCN-NOT: buffer_load
; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: v_cmp_eq_u32_e64 [[C2:[^,]+]], [[IDX]], 2 ; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0
; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2
; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]]
; GCN: store_dwordx2 v[{{[0-9:]+}}] ; GCN: store_dwordx2 v[{{[0-9:]+}}]
define amdgpu_kernel void @dyn_extract_vector_elt_v3i64(i64 addrspace(1)* %out, <3 x i64> %foo, i32 %elt) #0 { define amdgpu_kernel void @dyn_extract_vector_elt_v3i64(i64 addrspace(1)* %out, <3 x i64> %foo, i32 %elt) #0 {
%dynelt = extractelement <3 x i64> %foo, i32 %elt %dynelt = extractelement <3 x i64> %foo, i32 %elt
store volatile i64 %dynelt, i64 addrspace(1)* %out store volatile i64 %dynelt, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}dyn_extract_vector_elt_v4i64: ; GCN-LABEL: {{^}}dyn_extract_vector_elt_v4i64:
; GCN-NOT: buffer_load ; GCN-NOT: buffer_load
; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: v_cmp_eq_u32_e64 [[C2:[^,]+]], [[IDX]], 2 ; GCN-DAG: s_cselect_b64 [[C1:[^,]+]], -1, 0
; GCN-DAG: v_cmp_eq_u32_e64 [[C3:[^,]+]], [[IDX]], 3 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2
; GCN-DAG: s_cselect_b64 [[C2:[^,]+]], -1, 0
; GCN-DAG: s_cmp_eq_u32 [[IDX]], 3
; GCN-DAG: s_cselect_b64 [[C3:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C1]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C2]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C3]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C3]]
; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C3]] ; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[C3]]
; GCN: store_dwordx2 v[{{[0-9:]+}}] ; GCN: store_dwordx2 v[{{[0-9:]+}}]
define amdgpu_kernel void @dyn_extract_vector_elt_v4i64(i64 addrspace(1)* %out, <4 x i64> %foo, i32 %elt) #0 { define amdgpu_kernel void @dyn_extract_vector_elt_v4i64(i64 addrspace(1)* %out, <4 x i64> %foo, i32 %elt) #0 {
%dynelt = extractelement <4 x i64> %foo, i32 %elt %dynelt = extractelement <4 x i64> %foo, i32 %elt
store volatile i64 %dynelt, i64 addrspace(1)* %out store volatile i64 %dynelt, i64 addrspace(1)* %out
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll

Show First 20 Lines • Show All 141 Lines • ▼ Show 20 Linesentry:
store i32 %elt2, i32 addrspace(1)* %out store i32 %elt2, i32 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @no_extract_volatile_load_dynextract(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %idx) { define amdgpu_kernel void @no_extract_volatile_load_dynextract(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %idx) {
; GCN-LABEL: no_extract_volatile_load_dynextract: ; GCN-LABEL: no_extract_volatile_load_dynextract:
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_load_dword s12, s[0:1], 0xd
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_load_dword s12, s[0:1], 0xd
; GCN-NEXT: s_mov_b32 s10, s2 ; GCN-NEXT: s_mov_b32 s10, s2
; GCN-NEXT: s_mov_b32 s11, s3 ; GCN-NEXT: s_mov_b32 s11, s3
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: s_mov_b32 s8, s6 ; GCN-NEXT: s_mov_b32 s8, s6
; GCN-NEXT: s_mov_b32 s9, s7 ; GCN-NEXT: s_mov_b32 s9, s7
; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 glc ; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_cmp_eq_u32 s12, 1
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s12, 1 ; GCN-NEXT: s_cmp_eq_u32 s12, 2
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s12, 2 ; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_eq_u32 s12, 3
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s12, 3 ; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%vec = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in %vec = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in
%eltN = extractelement <4 x i32> %vec, i32 %idx %eltN = extractelement <4 x i32> %vec, i32 %idx
store i32 %eltN, i32 addrspace(1)* %out store i32 %eltN, i32 addrspace(1)* %out
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
define amdgpu_ps void @i1_copy_from_loop(<4 x i32> inreg %rsrc, i32 %tid) { define amdgpu_ps void @i1_copy_from_loop(<4 x i32> inreg %rsrc, i32 %tid) {
; SI-LABEL: i1_copy_from_loop: ; SI-LABEL: i1_copy_from_loop:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_mov_b32 s6, 0 ; SI-NEXT: s_mov_b32 s8, 0
; SI-NEXT: s_mov_b64 s[4:5], 0 ; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: ; implicit-def: $sgpr8_sgpr9 ; SI-NEXT: ; implicit-def: $sgpr6_sgpr7
; SI-NEXT: ; implicit-def: $sgpr10_sgpr11 ; SI-NEXT: ; implicit-def: $sgpr10_sgpr11
; SI-NEXT: s_branch BB0_3 ; SI-NEXT: s_branch BB0_3
; SI-NEXT: BB0_1: ; %Flow1 ; SI-NEXT: BB0_1: ; in Loop: Header=BB0_3 Depth=1
; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1 ; SI-NEXT: ; implicit-def: $sgpr8
; SI-NEXT: s_or_b64 exec, exec, s[14:15]
; SI-NEXT: BB0_2: ; %Flow ; SI-NEXT: BB0_2: ; %Flow
; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1 ; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1
; SI-NEXT: s_and_b64 s[14:15], exec, s[10:11] ; SI-NEXT: s_and_b64 s[14:15], exec, s[10:11]
; SI-NEXT: s_or_b64 s[4:5], s[14:15], s[4:5] ; SI-NEXT: s_or_b64 s[4:5], s[14:15], s[4:5]
; SI-NEXT: s_andn2_b64 s[8:9], s[8:9], exec ; SI-NEXT: s_andn2_b64 s[6:7], s[6:7], exec
; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec ; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
; SI-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13] ; SI-NEXT: s_or_b64 s[6:7], s[6:7], s[12:13]
; SI-NEXT: s_andn2_b64 exec, exec, s[4:5] ; SI-NEXT: s_andn2_b64 exec, exec, s[4:5]
; SI-NEXT: s_cbranch_execz BB0_6 ; SI-NEXT: s_cbranch_execz BB0_7
; SI-NEXT: BB0_3: ; %for.body ; SI-NEXT: BB0_3: ; %for.body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_cmp_lt_u32 s8, 4
; SI-NEXT: s_cselect_b64 s[12:13], -1, 0
; SI-NEXT: s_or_b64 s[10:11], s[10:11], exec ; SI-NEXT: s_or_b64 s[10:11], s[10:11], exec
; SI-NEXT: s_cmp_gt_u32 s6, 3 ; SI-NEXT: s_cmp_gt_u32 s8, 3
; SI-NEXT: v_cmp_lt_u32_e64 s[12:13], s6, 4 ; SI-NEXT: s_cbranch_scc1 BB0_1
; SI-NEXT: s_cbranch_scc1 BB0_2
; SI-NEXT: ; %bb.4: ; %mid.loop ; SI-NEXT: ; %bb.4: ; %mid.loop
; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1 ; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1
; SI-NEXT: v_mov_b32_e32 v1, s6 ; SI-NEXT: v_mov_b32_e32 v1, s8
; SI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 idxen offen ; SI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 idxen offen
; SI-NEXT: s_mov_b64 s[12:13], -1 ; SI-NEXT: s_mov_b64 s[12:13], -1
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_le_f32_e32 vcc, 0, v1 ; SI-NEXT: v_cmp_le_f32_e32 vcc, 0, v1
; SI-NEXT: s_mov_b64 s[10:11], -1 ; SI-NEXT: s_mov_b64 s[10:11], -1
; SI-NEXT: s_and_saveexec_b64 s[14:15], vcc ; SI-NEXT: s_and_saveexec_b64 s[14:15], vcc
; SI-NEXT: s_cbranch_execz BB0_1
; SI-NEXT: ; %bb.5: ; %end.loop ; SI-NEXT: ; %bb.5: ; %end.loop
; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1 ; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1
; SI-NEXT: s_add_i32 s6, s6, 1 ; SI-NEXT: s_add_i32 s8, s8, 1
; SI-NEXT: s_xor_b64 s[10:11], exec, -1 ; SI-NEXT: s_xor_b64 s[10:11], exec, -1
; SI-NEXT: s_branch BB0_1 ; SI-NEXT: ; %bb.6: ; %Flow1
; SI-NEXT: BB0_6: ; %for.end ; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1
; SI-NEXT: s_or_b64 exec, exec, s[14:15]
; SI-NEXT: s_branch BB0_2
; SI-NEXT: BB0_7: ; %for.end
; SI-NEXT: s_or_b64 exec, exec, s[4:5] ; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_and_saveexec_b64 s[0:1], s[8:9] ; SI-NEXT: s_and_saveexec_b64 s[0:1], s[6:7]
; SI-NEXT: s_cbranch_execz BB0_8 ; SI-NEXT: s_cbranch_execz BB0_9
; SI-NEXT: ; %bb.7: ; %if ; SI-NEXT: ; %bb.8: ; %if
; SI-NEXT: exp mrt0 v0, v0, v0, v0 done vm ; SI-NEXT: exp mrt0 v0, v0, v0, v0 done vm
; SI-NEXT: BB0_8: ; %end ; SI-NEXT: BB0_9: ; %end
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
entry: entry:
br label %for.body br label %for.body
for.body: for.body:
%i = phi i32 [0, %entry], [%i.inc, %end.loop] %i = phi i32 [0, %entry], [%i.inc, %end.loop]
%cc = icmp ult i32 %i, 4 %cc = icmp ult i32 %i, 4
br i1 %cc, label %mid.loop, label %for.end br i1 %cc, label %mid.loop, label %for.end
Show All 26 Lines

llvm/test/CodeGen/AMDGPU/icmp64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
; SI-LABEL: {{^}}test_i64_eq: ; GCN-LABEL: {{^}}test_i64_eq:
; VI: s_cmp_eq_u64
; SI: v_cmp_eq_u64 ; SI: v_cmp_eq_u64
define amdgpu_kernel void @test_i64_eq(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { define amdgpu_kernel void @test_i64_eq(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%result = sext i1 %cmp to i32 %result = sext i1 %cmp to i32
store i32 %result, i32 addrspace(1)* %out, align 4 store i32 %result, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; SI-LABEL: {{^}}test_i64_ne: ; GCN-LABEL: {{^}}test_i64_ne:
; VI: s_cmp_lg_u64
; SI: v_cmp_ne_u64 ; SI: v_cmp_ne_u64
define amdgpu_kernel void @test_i64_ne(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { define amdgpu_kernel void @test_i64_ne(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
%cmp = icmp ne i64 %a, %b %cmp = icmp ne i64 %a, %b
%result = sext i1 %cmp to i32 %result = sext i1 %cmp to i32
store i32 %result, i32 addrspace(1)* %out, align 4 store i32 %result, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; SI-LABEL: {{^}}test_i64_slt: ; GCN-LABEL: {{^}}test_i64_slt:
; SI: v_cmp_lt_i64 ; GCN: v_cmp_lt_i64
define amdgpu_kernel void @test_i64_slt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { define amdgpu_kernel void @test_i64_slt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
%result = sext i1 %cmp to i32 %result = sext i1 %cmp to i32
store i32 %result, i32 addrspace(1)* %out, align 4 store i32 %result, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; SI-LABEL: {{^}}test_i64_ult: ; GCN-LABEL: {{^}}test_i64_ult:
; SI: v_cmp_lt_u64 ; GCN: v_cmp_lt_u64
define amdgpu_kernel void @test_i64_ult(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { define amdgpu_kernel void @test_i64_ult(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
%cmp = icmp ult i64 %a, %b %cmp = icmp ult i64 %a, %b
%result = sext i1 %cmp to i32 %result = sext i1 %cmp to i32
store i32 %result, i32 addrspace(1)* %out, align 4 store i32 %result, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; SI-LABEL: {{^}}test_i64_sle: ; GCN-LABEL: {{^}}test_i64_sle:
; SI: v_cmp_le_i64 ; GCN: v_cmp_le_i64
define amdgpu_kernel void @test_i64_sle(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { define amdgpu_kernel void @test_i64_sle(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%result = sext i1 %cmp to i32 %result = sext i1 %cmp to i32
store i32 %result, i32 addrspace(1)* %out, align 4 store i32 %result, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; SI-LABEL: {{^}}test_i64_ule: ; GCN-LABEL: {{^}}test_i64_ule:
; SI: v_cmp_le_u64 ; GCN: v_cmp_le_u64
define amdgpu_kernel void @test_i64_ule(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { define amdgpu_kernel void @test_i64_ule(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
%cmp = icmp ule i64 %a, %b %cmp = icmp ule i64 %a, %b
%result = sext i1 %cmp to i32 %result = sext i1 %cmp to i32
store i32 %result, i32 addrspace(1)* %out, align 4 store i32 %result, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; SI-LABEL: {{^}}test_i64_sgt: ; GCN-LABEL: {{^}}test_i64_sgt:
; SI: v_cmp_gt_i64 ; GCN: v_cmp_gt_i64
define amdgpu_kernel void @test_i64_sgt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { define amdgpu_kernel void @test_i64_sgt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%result = sext i1 %cmp to i32 %result = sext i1 %cmp to i32
store i32 %result, i32 addrspace(1)* %out, align 4 store i32 %result, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; SI-LABEL: {{^}}test_i64_ugt: ; GCN-LABEL: {{^}}test_i64_ugt:
; SI: v_cmp_gt_u64 ; GCN: v_cmp_gt_u64
define amdgpu_kernel void @test_i64_ugt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { define amdgpu_kernel void @test_i64_ugt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
%cmp = icmp ugt i64 %a, %b %cmp = icmp ugt i64 %a, %b
%result = sext i1 %cmp to i32 %result = sext i1 %cmp to i32
store i32 %result, i32 addrspace(1)* %out, align 4 store i32 %result, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; SI-LABEL: {{^}}test_i64_sge: ; GCN-LABEL: {{^}}test_i64_sge:
; SI: v_cmp_ge_i64 ; GCN: v_cmp_ge_i64
define amdgpu_kernel void @test_i64_sge(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { define amdgpu_kernel void @test_i64_sge(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%result = sext i1 %cmp to i32 %result = sext i1 %cmp to i32
store i32 %result, i32 addrspace(1)* %out, align 4 store i32 %result, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; SI-LABEL: {{^}}test_i64_uge: ; GCN-LABEL: {{^}}test_i64_uge:
; SI: v_cmp_ge_u64 ; GCN: v_cmp_ge_u64
define amdgpu_kernel void @test_i64_uge(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind { define amdgpu_kernel void @test_i64_uge(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
%cmp = icmp uge i64 %a, %b %cmp = icmp uge i64 %a, %b
%result = sext i1 %cmp to i32 %result = sext i1 %cmp to i32
store i32 %result, i32 addrspace(1)* %out, align 4 store i32 %result, i32 addrspace(1)* %out, align 4
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/idiv-licm.ll

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: BB0_1: ; %bb3 ; GFX10-NEXT: BB0_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mul_lo_u32 v2, s5, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s5, v0
; GFX10-NEXT: v_mul_hi_u32 v3, s4, v0 ; GFX10-NEXT: v_mul_hi_u32 v3, s4, v0
; GFX10-NEXT: v_add_nc_u32_e32 v2, v3, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v2, v3, v2
; GFX10-NEXT: v_mul_lo_u32 v4, s3, v2
; GFX10-NEXT: v_not_b32_e32 v3, v2 ; GFX10-NEXT: v_not_b32_e32 v3, v2
; GFX10-NEXT: v_mul_lo_u32 v4, s3, v2
; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v2
; GFX10-NEXT: v_mul_lo_u32 v3, s2, v3 ; GFX10-NEXT: v_mul_lo_u32 v3, s2, v3
; GFX10-NEXT: v_add_nc_u32_e32 v4, s4, v4 ; GFX10-NEXT: v_add_nc_u32_e32 v4, s4, v4
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v4
; GFX10-NEXT: v_add_nc_u32_e32 v3, s4, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v3, s4, v3
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v4
; GFX10-NEXT: s_add_u32 s4, s4, 1 ; GFX10-NEXT: s_add_u32 s4, s4, 1
; GFX10-NEXT: s_addc_u32 s5, s5, 0 ; GFX10-NEXT: s_addc_u32 s5, s5, 0
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v3 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v3
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: global_store_dword v1, v2, s[0:1] ; GFX10-NEXT: global_store_dword v1, v2, s[0:1]
▲ Show 20 Lines • Show All 513 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_xor_b32_e32 v8, s2, v5 ; GFX9-NEXT: v_xor_b32_e32 v8, s2, v5
; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3] ; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v7, s5 ; GFX9-NEXT: v_mov_b32_e32 v7, s5
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s4, v5 ; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s4, v5
; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1]
; GFX9-NEXT: v_mul_f32_e32 v7, v9, v1 ; GFX9-NEXT: v_mul_f32_e32 v7, v9, v1
; GFX9-NEXT: v_trunc_f32_e32 v7, v7 ; GFX9-NEXT: v_trunc_f32_e32 v7, v7
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 30, v8 ; GFX9-NEXT: v_ashrrev_i32_e32 v2, 30, v8
; GFX9-NEXT: v_cvt_i32_f32_e32 v8, v7 ; GFX9-NEXT: v_mad_f32 v8, -v7, v0, v9
; GFX9-NEXT: v_mad_f32 v7, -v7, v0, v9 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v8|, |v0|
; GFX9-NEXT: v_cvt_i32_f32_e32 v7, v7
; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: v_add_u16_e32 v4, 1, v4 ; GFX9-NEXT: v_add_u16_e32 v4, 1, v4
; GFX9-NEXT: v_or_b32_e32 v2, 1, v2 ; GFX9-NEXT: v_or_b32_e32 v2, 1, v2
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v7|, |v0| ; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s3, v4 ; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s3, v4
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1]
; GFX9-NEXT: v_add_u32_e32 v2, v8, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v7, v2
; GFX9-NEXT: s_and_b64 vcc, exec, vcc ; GFX9-NEXT: s_and_b64 vcc, exec, vcc
; GFX9-NEXT: global_store_short v[5:6], v2, off ; GFX9-NEXT: global_store_short v[5:6], v2, off
; GFX9-NEXT: s_cbranch_vccz BB6_1 ; GFX9-NEXT: s_cbranch_vccz BB6_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: sdiv16_invariant_denom: ; GFX10-LABEL: sdiv16_invariant_denom:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
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; GFX10-NEXT: v_add_nc_u16 v4, v4, 1 ; GFX10-NEXT: v_add_nc_u16 v4, v4, 1
; GFX10-NEXT: v_cvt_f32_i32_e32 v7, v5 ; GFX10-NEXT: v_cvt_f32_i32_e32 v7, v5
; GFX10-NEXT: v_xor_b32_e32 v8, s4, v5 ; GFX10-NEXT: v_xor_b32_e32 v8, s4, v5
; GFX10-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3]
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
; GFX10-NEXT: v_mul_f32_e32 v2, v7, v1 ; GFX10-NEXT: v_mul_f32_e32 v2, v7, v1
; GFX10-NEXT: v_ashrrev_i32_e32 v8, 30, v8 ; GFX10-NEXT: v_ashrrev_i32_e32 v8, 30, v8
; GFX10-NEXT: v_add_co_u32 v5, s0, s2, v5 ; GFX10-NEXT: v_add_co_u32 v5, s0, s2, v5
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
; GFX10-NEXT: v_trunc_f32_e32 v2, v2 ; GFX10-NEXT: v_trunc_f32_e32 v2, v2
; GFX10-NEXT: v_or_b32_e32 v8, 1, v8 ; GFX10-NEXT: v_or_b32_e32 v8, 1, v8
; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s0, s3, v6, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
; GFX10-NEXT: v_mad_f32 v7, -v2, v0, v7 ; GFX10-NEXT: v_mad_f32 v7, -v2, v0, v7
; GFX10-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GFX10-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX10-NEXT: v_cmp_ge_f32_e64 s1, |v7|, |v0| ; GFX10-NEXT: v_cmp_ge_f32_e64 s1, |v7|, |v0|
; GFX10-NEXT: s_cmp_lg_u32 s1, 0
; GFX10-NEXT: s_cselect_b32 s1, -1, 0
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, v8, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, v8, s1
; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v7
; GFX10-NEXT: global_store_short v[5:6], v2, off ; GFX10-NEXT: global_store_short v[5:6], v2, off
; GFX10-NEXT: s_cbranch_vccz BB6_1 ; GFX10-NEXT: s_cbranch_vccz BB6_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
Show All 11 Linesbb3: ; preds = %bb3, %bb
%tmp8 = icmp eq i16 %tmp7, 1024 %tmp8 = icmp eq i16 %tmp7, 1024
br i1 %tmp8, label %bb2, label %bb3 br i1 %tmp8, label %bb2, label %bb3
} }
define amdgpu_kernel void @srem16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) { define amdgpu_kernel void @srem16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
; GFX9-LABEL: srem16_invariant_denom: ; GFX9-LABEL: srem16_invariant_denom:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v3, 0 ; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: s_movk_i32 s5, 0x400 ; GFX9-NEXT: s_movk_i32 s3, 0x400
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_sext_i32_i16 s4, s2 ; GFX9-NEXT: s_sext_i32_i16 s2, s2
; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s4 ; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0
; GFX9-NEXT: BB7_1: ; %bb3 ; GFX9-NEXT: BB7_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_bfe_i32 v7, v4, 0, 16 ; GFX9-NEXT: v_bfe_i32 v7, v4, 0, 16
; GFX9-NEXT: v_cvt_f32_i32_e32 v10, v7
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v4 ; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v4
; GFX9-NEXT: v_xor_b32_e32 v9, s4, v7 ; GFX9-NEXT: v_cvt_f32_i32_e32 v10, v7
; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3] ; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, s5
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s4, v5
; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
; GFX9-NEXT: v_mul_f32_e32 v8, v10, v1
; GFX9-NEXT: v_xor_b32_e32 v9, s2, v7
; GFX9-NEXT: v_trunc_f32_e32 v8, v8
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 30, v9 ; GFX9-NEXT: v_ashrrev_i32_e32 v2, 30, v9
; GFX9-NEXT: v_mul_f32_e32 v9, v10, v1 ; GFX9-NEXT: v_mad_f32 v9, -v8, v0, v10
; GFX9-NEXT: v_trunc_f32_e32 v9, v9 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v9|, |v0|
; GFX9-NEXT: v_cvt_i32_f32_e32 v11, v9 ; GFX9-NEXT: v_cvt_i32_f32_e32 v8, v8
; GFX9-NEXT: v_mad_f32 v9, -v9, v0, v10 ; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: v_or_b32_e32 v2, 1, v2 ; GFX9-NEXT: v_or_b32_e32 v2, 1, v2
; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v9|, |v0| ; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1]
; GFX9-NEXT: v_add_u32_e32 v2, v11, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v8, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v2, s4 ; GFX9-NEXT: v_mul_lo_u32 v2, v2, s2
; GFX9-NEXT: v_add_u16_e32 v4, 1, v4 ; GFX9-NEXT: v_add_u16_e32 v4, 1, v4
; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s5, v4 ; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s3, v4
; GFX9-NEXT: v_mov_b32_e32 v8, s7
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s6, v5
; GFX9-NEXT: s_and_b64 vcc, exec, vcc ; GFX9-NEXT: s_and_b64 vcc, exec, vcc
; GFX9-NEXT: v_sub_u32_e32 v2, v7, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, v7, v2
; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
; GFX9-NEXT: global_store_short v[5:6], v2, off ; GFX9-NEXT: global_store_short v[5:6], v2, off
; GFX9-NEXT: s_cbranch_vccz BB7_1 ; GFX9-NEXT: s_cbranch_vccz BB7_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: srem16_invariant_denom: ; GFX10-LABEL: srem16_invariant_denom:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
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; GFX10-NEXT: v_cvt_f32_i32_e32 v5, v7 ; GFX10-NEXT: v_cvt_f32_i32_e32 v5, v7
; GFX10-NEXT: v_xor_b32_e32 v6, s1, v7 ; GFX10-NEXT: v_xor_b32_e32 v6, s1, v7
; GFX10-NEXT: v_mul_f32_e32 v8, v5, v1 ; GFX10-NEXT: v_mul_f32_e32 v8, v5, v1
; GFX10-NEXT: v_ashrrev_i32_e32 v6, 30, v6 ; GFX10-NEXT: v_ashrrev_i32_e32 v6, 30, v6
; GFX10-NEXT: v_trunc_f32_e32 v8, v8 ; GFX10-NEXT: v_trunc_f32_e32 v8, v8
; GFX10-NEXT: v_or_b32_e32 v6, 1, v6 ; GFX10-NEXT: v_or_b32_e32 v6, 1, v6
; GFX10-NEXT: v_mad_f32 v5, -v8, v0, v5 ; GFX10-NEXT: v_mad_f32 v5, -v8, v0, v5
; GFX10-NEXT: v_cvt_i32_f32_e32 v8, v8 ; GFX10-NEXT: v_cvt_i32_f32_e32 v8, v8
; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v5|, |v0| ; GFX10-NEXT: v_cmp_ge_f32_e64 s0, |v5|, |v0|
; GFX10-NEXT: s_cmp_lg_u32 s0, 0
; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX10-NEXT: v_cndmask_b32_e32 v9, 0, v6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v9, 0, v6, vcc_lo
; GFX10-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3]
; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4 ; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
; GFX10-NEXT: v_add_nc_u32_e32 v2, v8, v9 ; GFX10-NEXT: v_add_nc_u32_e32 v2, v8, v9
; GFX10-NEXT: v_add_co_u32 v5, s0, s2, v5 ; GFX10-NEXT: v_add_co_u32 v5, s0, s2, v5
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo ; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s0, s3, v6, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
; GFX10-NEXT: v_mul_lo_u32 v2, v2, s1 ; GFX10-NEXT: v_mul_lo_u32 v2, v2, s1
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llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll

; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s
; GCN-LABEL: {{^}}float4_inselt: ; GCN-LABEL: {{^}}float4_inselt:
; GCN-NOT: v_movrel ; GCN-NOT: v_movrel
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cmp_ne_u32_e64 [[CC1:[^,]+]], [[IDX:s[0-9]+]], 3 ; GCN-DAG: s_cmp_lg_u32 [[IDX:s[0-9]+]], 3
; GCN-DAG: s_cselect_b64 [[CC1:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v[[ELT_LAST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC1]] ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_LAST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC1]]
; GCN-DAG: v_cmp_ne_u32_e64 [[CC2:[^,]+]], [[IDX]], 2 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 2
; GCN-DAG: s_cselect_b64 [[CC2:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC2]] ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC2]]
; GCN-DAG: v_cmp_ne_u32_e64 [[CC3:[^,]+]], [[IDX]], 1 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 1
; GCN-DAG: s_cselect_b64 [[CC3:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC3]] ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC3]]
; GCN-DAG: v_cmp_ne_u32_e64 [[CC4:[^,]+]], [[IDX]], 0 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 0
; GCN-DAG: s_cselect_b64 [[CC4:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC4]] ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC4]]
; GCN: flat_store_dwordx4 v[{{[0-9:]+}}], v{{\[}}[[ELT_FIRST]]:[[ELT_LAST]]] ; GCN: flat_store_dwordx4 v[{{[0-9:]+}}], v{{\[}}[[ELT_FIRST]]:[[ELT_LAST]]]
define amdgpu_kernel void @float4_inselt(<4 x float> addrspace(1)* %out, <4 x float> %vec, i32 %sel) { define amdgpu_kernel void @float4_inselt(<4 x float> addrspace(1)* %out, <4 x float> %vec, i32 %sel) {
entry: entry:
%v = insertelement <4 x float> %vec, float 1.000000e+00, i32 %sel %v = insertelement <4 x float> %vec, float 1.000000e+00, i32 %sel
store <4 x float> %v, <4 x float> addrspace(1)* %out store <4 x float> %v, <4 x float> addrspace(1)* %out
ret void ret void
} }
Show All 35 Linesentry:
%v = insertelement <4 x i32> %vec, i32 1, i32 %sel %v = insertelement <4 x i32> %vec, i32 1, i32 %sel
store <4 x i32> %v, <4 x i32> addrspace(1)* %out store <4 x i32> %v, <4 x i32> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}float2_inselt: ; GCN-LABEL: {{^}}float2_inselt:
; GCN-NOT: v_movrel ; GCN-NOT: v_movrel
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cmp_ne_u32_e64 [[CC1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_lg_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: s_cselect_b64 [[CC1:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v[[ELT_LAST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC1]] ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_LAST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC1]]
; GCN-DAG: v_cmp_ne_u32_e64 [[CC2:[^,]+]], [[IDX]], 0 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 0
; GCN-DAG: s_cselect_b64 [[CC2:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC2]] ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC2]]
; GCN: flat_store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[ELT_FIRST]]:[[ELT_LAST]]] ; GCN: flat_store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[ELT_FIRST]]:[[ELT_LAST]]]
define amdgpu_kernel void @float2_inselt(<2 x float> addrspace(1)* %out, <2 x float> %vec, i32 %sel) { define amdgpu_kernel void @float2_inselt(<2 x float> addrspace(1)* %out, <2 x float> %vec, i32 %sel) {
entry: entry:
%v = insertelement <2 x float> %vec, float 1.000000e+00, i32 %sel %v = insertelement <2 x float> %vec, float 1.000000e+00, i32 %sel
store <2 x float> %v, <2 x float> addrspace(1)* %out store <2 x float> %v, <2 x float> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}float8_inselt: ; GCN-LABEL: {{^}}float8_inselt:
; GCN-NOT: v_movrel ; GCN-NOT: v_movrel
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cmp_ne_u32_e64 [[CC1:[^,]+]], [[IDX:s[0-9]+]], 3 ; GCN-DAG: s_cmp_lg_u32 [[IDX:s[0-9]+]], 3
; GCN-DAG: s_cselect_b64 [[CC1:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v[[ELT_LAST0:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC1]] ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_LAST0:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC1]]
; GCN-DAG: v_cmp_ne_u32_e64 [[CC2:[^,]+]], [[IDX]], 2 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 2
; GCN-DAG: s_cselect_b64 [[CC2:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC2]] ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC2]]
; GCN-DAG: v_cmp_ne_u32_e64 [[CC3:[^,]+]], [[IDX]], 1 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 1
; GCN-DAG: s_cselect_b64 [[CC3:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC3]] ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC3]]
; GCN-DAG: v_cmp_ne_u32_e64 [[CC4:[^,]+]], [[IDX]], 0 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 0
; GCN-DAG: s_cselect_b64 [[CC4:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST0:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC4]] ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST0:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC4]]
; GCN-DAG: v_cmp_ne_u32_e64 [[CC5:[^,]+]], [[IDX:s[0-9]+]], 7 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 7
; GCN-DAG: s_cselect_b64 [[CC5:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v[[ELT_LAST1:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC5]] ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_LAST1:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC5]]
; GCN-DAG: v_cmp_ne_u32_e64 [[CC6:[^,]+]], [[IDX]], 6 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 6
; GCN-DAG: s_cselect_b64 [[CC6:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC6]] ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC6]]
; GCN-DAG: v_cmp_ne_u32_e64 [[CC7:[^,]+]], [[IDX]], 5 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 5
; GCN-DAG: s_cselect_b64 [[CC7:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC7]] ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC7]]
; GCN-DAG: v_cmp_ne_u32_e64 [[CC8:[^,]+]], [[IDX]], 4 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 4
; GCN-DAG: s_cselect_b64 [[CC8:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST1:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC8]] ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST1:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC8]]
; GCN-DAG: flat_store_dwordx4 v[{{[0-9:]+}}], v{{\[}}[[ELT_FIRST0]]:[[ELT_LAST0]]] ; GCN-DAG: flat_store_dwordx4 v[{{[0-9:]+}}], v{{\[}}[[ELT_FIRST0]]:[[ELT_LAST0]]]
; GCN-DAG: flat_store_dwordx4 v[{{[0-9:]+}}], v{{\[}}[[ELT_FIRST1]]:[[ELT_LAST1]]] ; GCN-DAG: flat_store_dwordx4 v[{{[0-9:]+}}], v{{\[}}[[ELT_FIRST1]]:[[ELT_LAST1]]]
define amdgpu_kernel void @float8_inselt(<8 x float> addrspace(1)* %out, <8 x float> %vec, i32 %sel) { define amdgpu_kernel void @float8_inselt(<8 x float> addrspace(1)* %out, <8 x float> %vec, i32 %sel) {
entry: entry:
%v = insertelement <8 x float> %vec, float 1.000000e+00, i32 %sel %v = insertelement <8 x float> %vec, float 1.000000e+00, i32 %sel
store <8 x float> %v, <8 x float> addrspace(1)* %out store <8 x float> %v, <8 x float> addrspace(1)* %out
ret void ret void
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesentry:
%v = insertelement <2 x half> %vec, half 1.000000e+00, i32 %sel %v = insertelement <2 x half> %vec, half 1.000000e+00, i32 %sel
store <2 x half> %v, <2 x half> addrspace(1)* %out store <2 x half> %v, <2 x half> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}half8_inselt: ; GCN-LABEL: {{^}}half8_inselt:
; GCN-NOT: v_movrel ; GCN-NOT: v_movrel
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cmp_ne_u32_e64 {{[^,]+}}, {{s[0-9]+}}, 0 ; GCN-DAG: s_cmp_lg_u32 {{s[0-9]+}}, 0
; GCN-DAG: v_cmp_ne_u32_e64 {{[^,]+}}, {{s[0-9]+}}, 1 ; GCN-DAG: s_cmp_lg_u32 {{s[0-9]+}}, 1
; GCN-DAG: v_cmp_ne_u32_e64 {{[^,]+}}, {{s[0-9]+}}, 2 ; GCN-DAG: s_cmp_lg_u32 {{s[0-9]+}}, 2
; GCN-DAG: v_cmp_ne_u32_e64 {{[^,]+}}, {{s[0-9]+}}, 3 ; GCN-DAG: s_cmp_lg_u32 {{s[0-9]+}}, 3
; GCN-DAG: v_cmp_ne_u32_e64 {{[^,]+}}, {{s[0-9]+}}, 4 ; GCN-DAG: s_cmp_lg_u32 {{s[0-9]+}}, 4
; GCN-DAG: v_cmp_ne_u32_e64 {{[^,]+}}, {{s[0-9]+}}, 5 ; GCN-DAG: s_cmp_lg_u32 {{s[0-9]+}}, 5
; GCN-DAG: v_cmp_ne_u32_e64 {{[^,]+}}, {{s[0-9]+}}, 6 ; GCN-DAG: s_cmp_lg_u32 {{s[0-9]+}}, 6
; GCN-DAG: v_cmp_ne_u32_e64 {{[^,]+}}, {{s[0-9]+}}, 7 ; GCN-DAG: s_cmp_lg_u32 {{s[0-9]+}}, 7
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Linesentry:
%v = insertelement <8 x i8> %vec, i8 1, i32 %sel %v = insertelement <8 x i8> %vec, i8 1, i32 %sel
store <8 x i8> %v, <8 x i8> addrspace(1)* %out store <8 x i8> %v, <8 x i8> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}byte16_inselt: ; GCN-LABEL: {{^}}byte16_inselt:
; GCN-NOT: v_movrel ; GCN-NOT: v_movrel
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cmp_ne_u32_e64 {{[^,]+}}, {{s[0-9]+}}, 0 ; GCN-DAG: s_cmp_lg_u32 {{s[0-9]+}}, 0
; GCN-DAG: v_cmp_ne_u32_e64 {{[^,]+}}, {{s[0-9]+}}, 15 ; GCN-DAG: s_cmp_lg_u32 {{s[0-9]+}}, 15
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
Show All 18 Linesentry:
%v = insertelement <16 x i8> %vec, i8 1, i32 %sel %v = insertelement <16 x i8> %vec, i8 1, i32 %sel
store <16 x i8> %v, <16 x i8> addrspace(1)* %out store <16 x i8> %v, <16 x i8> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}double2_inselt: ; GCN-LABEL: {{^}}double2_inselt:
; GCN-NOT: v_movrel ; GCN-NOT: v_movrel
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cmp_eq_u32_e64 [[CC1:[^,]+]], [[IDX:s[0-9]+]], 1 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
; GCN-DAG: s_cselect_b64 [[CC1:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CC1]] ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CC1]]
; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, 0, [[CC1]] ; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, 0, [[CC1]]
; GCN-DAG: v_cmp_eq_u32_e64 [[CC2:[^,]+]], [[IDX]], 0 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 0
; GCN-DAG: s_cselect_b64 [[CC2:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CC2]] ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CC2]]
; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, 0, [[CC2]] ; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, 0, [[CC2]]
define amdgpu_kernel void @double2_inselt(<2 x double> addrspace(1)* %out, <2 x double> %vec, i32 %sel) { define amdgpu_kernel void @double2_inselt(<2 x double> addrspace(1)* %out, <2 x double> %vec, i32 %sel) {
entry: entry:
%v = insertelement <2 x double> %vec, double 1.000000e+00, i32 %sel %v = insertelement <2 x double> %vec, double 1.000000e+00, i32 %sel
store <2 x double> %v, <2 x double> addrspace(1)* %out store <2 x double> %v, <2 x double> addrspace(1)* %out
ret void ret void
} }
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
entry: entry:
%v = insertelement <4 x i1> %vec, i1 1, i32 %sel %v = insertelement <4 x i1> %vec, i1 1, i32 %sel
store <4 x i1> %v, <4 x i1> addrspace(1)* %out store <4 x i1> %v, <4 x i1> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}bit128_inselt: ; GCN-LABEL: {{^}}bit128_inselt:
; GCN-NOT: buffer_ ; GCN-NOT: buffer_
; GCN-DAG: v_cmp_ne_u32_e64 [[CC1:[^,]+]], s{{[0-9]+}}, 0 ; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0
; GCN-DAG: s_cselect_b64 [[CC1:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}, [[CC1]] ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}, [[CC1]]
; GCN-DAG: v_mov_b32_e32 [[LASTIDX:v[0-9]+]], 0x7f
; GCN-DAG: v_cmp_ne_u32_e32 [[CCL:[^,]+]], s{{[0-9]+}}, [[LASTIDX]] ; GCN-DAG: s_cmpk_lg_i32 {{s[0-9]+}}, 0x7f
; GCN-DAG: s_cselect_b64 [[CCL:[^,]+]], -1, 0
; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}, [[CCL]] ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}, [[CCL]]
define amdgpu_kernel void @bit128_inselt(<128 x i1> addrspace(1)* %out, <128 x i1> %vec, i32 %sel) { define amdgpu_kernel void @bit128_inselt(<128 x i1> addrspace(1)* %out, <128 x i1> %vec, i32 %sel) {
entry: entry:
%v = insertelement <128 x i1> %vec, i1 1, i32 %sel %v = insertelement <128 x i1> %vec, i1 1, i32 %sel
store <128 x i1> %v, <128 x i1> addrspace(1)* %out store <128 x i1> %v, <128 x i1> addrspace(1)* %out
ret void ret void
} }
Show All 33 Lines

llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll

Show First 20 Lines • Show All 284 Lines • ▼ Show 20 Lines
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2 ; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2
; SI-NEXT: s_load_dword s4, s[4:5], 0x4 ; SI-NEXT: s_load_dword s4, s[4:5], 0x4
; SI-NEXT: v_mov_b32_e32 v0, 0x40a00000 ; SI-NEXT: v_mov_b32_e32 v0, 0x40a00000
; SI-NEXT: s_mov_b32 s3, 0x100f000 ; SI-NEXT: s_mov_b32 s3, 0x100f000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s7 ; SI-NEXT: v_mov_b32_e32 v1, s7
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 ; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
; SI-NEXT: v_mov_b32_e32 v2, s6 ; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: dynamic_insertelement_v2f32: ; VI-LABEL: dynamic_insertelement_v2f32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x8 ; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x8
; VI-NEXT: s_load_dword s4, s[4:5], 0x10 ; VI-NEXT: s_load_dword s4, s[4:5], 0x10
; VI-NEXT: v_mov_b32_e32 v0, 0x40a00000 ; VI-NEXT: v_mov_b32_e32 v0, 0x40a00000
; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; VI-NEXT: s_mov_b32 s3, 0x1100f000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 ; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v2, s6 ; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 ; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 %b %vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 %b
store <2 x float> %vecins, <2 x float> addrspace(1)* %out, align 8 store <2 x float> %vecins, <2 x float> addrspace(1)* %out, align 8
ret void ret void
} }
define amdgpu_kernel void @dynamic_insertelement_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, i32 %b) nounwind { define amdgpu_kernel void @dynamic_insertelement_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, i32 %b) nounwind {
; SI-LABEL: dynamic_insertelement_v3f32: ; SI-LABEL: dynamic_insertelement_v3f32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4 ; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4
; SI-NEXT: s_load_dword s4, s[4:5], 0x8 ; SI-NEXT: s_load_dword s4, s[4:5], 0x8
; SI-NEXT: v_mov_b32_e32 v0, 0x40a00000 ; SI-NEXT: v_mov_b32_e32 v0, 0x40a00000
; SI-NEXT: s_mov_b32 s3, 0x100f000 ; SI-NEXT: s_mov_b32 s3, 0x100f000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s10 ; SI-NEXT: v_mov_b32_e32 v1, s10
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 ; SI-NEXT: s_cmp_lg_u32 s4, 2
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v1, s9 ; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 ; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
; SI-NEXT: v_mov_b32_e32 v3, s8 ; SI-NEXT: v_mov_b32_e32 v3, s8
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; SI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: dynamic_insertelement_v3f32: ; VI-LABEL: dynamic_insertelement_v3f32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10 ; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
; VI-NEXT: s_load_dword s4, s[4:5], 0x20 ; VI-NEXT: s_load_dword s4, s[4:5], 0x20
; VI-NEXT: v_mov_b32_e32 v0, 0x40a00000 ; VI-NEXT: v_mov_b32_e32 v0, 0x40a00000
; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; VI-NEXT: s_mov_b32 s3, 0x1100f000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s10 ; VI-NEXT: v_mov_b32_e32 v1, s10
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 ; VI-NEXT: s_cmp_lg_u32 s4, 2
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v1, s9 ; VI-NEXT: v_mov_b32_e32 v1, s9
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 ; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s8 ; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 ; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 %b %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 %b
store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
ret void ret void
} }
define amdgpu_kernel void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %b) nounwind { define amdgpu_kernel void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %b) nounwind {
; SI-LABEL: dynamic_insertelement_v4f32: ; SI-LABEL: dynamic_insertelement_v4f32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4 ; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4
; SI-NEXT: s_load_dword s4, s[4:5], 0x8 ; SI-NEXT: s_load_dword s4, s[4:5], 0x8
; SI-NEXT: v_mov_b32_e32 v0, 0x40a00000 ; SI-NEXT: v_mov_b32_e32 v0, 0x40a00000
; SI-NEXT: s_mov_b32 s3, 0x100f000 ; SI-NEXT: s_mov_b32 s3, 0x100f000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s11 ; SI-NEXT: v_mov_b32_e32 v1, s11
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3 ; SI-NEXT: s_cmp_lg_u32 s4, 3
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 2
; SI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v1, s10 ; SI-NEXT: v_mov_b32_e32 v1, s10
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 ; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v1, s9 ; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 ; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
; SI-NEXT: v_mov_b32_e32 v4, s8 ; SI-NEXT: v_mov_b32_e32 v4, s8
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: dynamic_insertelement_v4f32: ; VI-LABEL: dynamic_insertelement_v4f32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10 ; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
; VI-NEXT: s_load_dword s4, s[4:5], 0x20 ; VI-NEXT: s_load_dword s4, s[4:5], 0x20
; VI-NEXT: v_mov_b32_e32 v0, 0x40a00000 ; VI-NEXT: v_mov_b32_e32 v0, 0x40a00000
; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; VI-NEXT: s_mov_b32 s3, 0x1100f000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s11 ; VI-NEXT: v_mov_b32_e32 v1, s11
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3 ; VI-NEXT: s_cmp_lg_u32 s4, 3
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 2
; VI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v1, s10 ; VI-NEXT: v_mov_b32_e32 v1, s10
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 ; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v1, s9 ; VI-NEXT: v_mov_b32_e32 v1, s9
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 ; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v4, s8 ; VI-NEXT: v_mov_b32_e32 v4, s8
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 ; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 %b %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 %b
store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
ret void ret void
} }
define amdgpu_kernel void @dynamic_insertelement_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, i32 %b) nounwind { define amdgpu_kernel void @dynamic_insertelement_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, i32 %b) nounwind {
; SI-LABEL: dynamic_insertelement_v8f32: ; SI-LABEL: dynamic_insertelement_v8f32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8 ; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8
; SI-NEXT: s_load_dword s4, s[4:5], 0x10 ; SI-NEXT: s_load_dword s4, s[4:5], 0x10
; SI-NEXT: v_mov_b32_e32 v4, 0x40a00000 ; SI-NEXT: v_mov_b32_e32 v4, 0x40a00000
; SI-NEXT: s_mov_b32 s3, 0x100f000 ; SI-NEXT: s_mov_b32 s3, 0x100f000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s11 ; SI-NEXT: v_mov_b32_e32 v0, s11
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3 ; SI-NEXT: s_cmp_lg_u32 s4, 3
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 2
; SI-NEXT: v_cndmask_b32_e32 v3, v4, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v3, v4, v0, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s10 ; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 ; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s9 ; SI-NEXT: v_mov_b32_e32 v0, s9
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 ; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_cndmask_b32_e32 v1, v4, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, v4, v0, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s8 ; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 ; SI-NEXT: s_cmp_lg_u32 s4, 7
; SI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v5, s15 ; SI-NEXT: v_mov_b32_e32 v5, s15
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 7 ; SI-NEXT: s_cmp_lg_u32 s4, 6
; SI-NEXT: v_cndmask_b32_e32 v7, v4, v5, vcc ; SI-NEXT: v_cndmask_b32_e32 v7, v4, v5, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v5, s14 ; SI-NEXT: v_mov_b32_e32 v5, s14
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 6 ; SI-NEXT: s_cmp_lg_u32 s4, 5
; SI-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc ; SI-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v5, s13 ; SI-NEXT: v_mov_b32_e32 v5, s13
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 5 ; SI-NEXT: s_cmp_lg_u32 s4, 4
; SI-NEXT: v_cndmask_b32_e32 v5, v4, v5, vcc ; SI-NEXT: v_cndmask_b32_e32 v5, v4, v5, vcc
; SI-NEXT: v_mov_b32_e32 v8, s12 ; SI-NEXT: v_mov_b32_e32 v8, s12
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 4 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc ; SI-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 ; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: dynamic_insertelement_v8f32: ; VI-LABEL: dynamic_insertelement_v8f32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x20 ; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x20
; VI-NEXT: s_load_dword s4, s[4:5], 0x40 ; VI-NEXT: s_load_dword s4, s[4:5], 0x40
; VI-NEXT: v_mov_b32_e32 v4, 0x40a00000 ; VI-NEXT: v_mov_b32_e32 v4, 0x40a00000
; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; VI-NEXT: s_mov_b32 s3, 0x1100f000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s11 ; VI-NEXT: v_mov_b32_e32 v0, s11
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3 ; VI-NEXT: s_cmp_lg_u32 s4, 3
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 2
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v0, vcc ; VI-NEXT: v_cndmask_b32_e32 v3, v4, v0, vcc
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s10 ; VI-NEXT: v_mov_b32_e32 v0, s10
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 ; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc ; VI-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s9 ; VI-NEXT: v_mov_b32_e32 v0, s9
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 ; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_cndmask_b32_e32 v1, v4, v0, vcc ; VI-NEXT: v_cndmask_b32_e32 v1, v4, v0, vcc
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s8 ; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 ; VI-NEXT: s_cmp_lg_u32 s4, 7
; VI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v5, s15 ; VI-NEXT: v_mov_b32_e32 v5, s15
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 7 ; VI-NEXT: s_cmp_lg_u32 s4, 6
; VI-NEXT: v_cndmask_b32_e32 v7, v4, v5, vcc ; VI-NEXT: v_cndmask_b32_e32 v7, v4, v5, vcc
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v5, s14 ; VI-NEXT: v_mov_b32_e32 v5, s14
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 6 ; VI-NEXT: s_cmp_lg_u32 s4, 5
; VI-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc ; VI-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v5, s13 ; VI-NEXT: v_mov_b32_e32 v5, s13
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 5 ; VI-NEXT: s_cmp_lg_u32 s4, 4
; VI-NEXT: v_cndmask_b32_e32 v5, v4, v5, vcc ; VI-NEXT: v_cndmask_b32_e32 v5, v4, v5, vcc
; VI-NEXT: v_mov_b32_e32 v8, s12 ; VI-NEXT: v_mov_b32_e32 v8, s12
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 4 ; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc ; VI-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 ; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b %vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b
store <8 x float> %vecins, <8 x float> addrspace(1)* %out, align 32 store <8 x float> %vecins, <8 x float> addrspace(1)* %out, align 32
ret void ret void
} }
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; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2 ; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2
; SI-NEXT: s_load_dword s4, s[4:5], 0x4 ; SI-NEXT: s_load_dword s4, s[4:5], 0x4
; SI-NEXT: s_mov_b32 s3, 0x100f000 ; SI-NEXT: s_mov_b32 s3, 0x100f000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s7 ; SI-NEXT: v_mov_b32_e32 v0, s7
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 ; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, 5, v0, vcc
; SI-NEXT: v_mov_b32_e32 v0, s6 ; SI-NEXT: v_mov_b32_e32 v0, s6
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: dynamic_insertelement_v2i32: ; VI-LABEL: dynamic_insertelement_v2i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x8 ; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x8
Show All 19 Lines
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4 ; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4
; SI-NEXT: s_load_dword s4, s[4:5], 0x8 ; SI-NEXT: s_load_dword s4, s[4:5], 0x8
; SI-NEXT: s_mov_b32 s3, 0x100f000 ; SI-NEXT: s_mov_b32 s3, 0x100f000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s10 ; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 ; SI-NEXT: s_cmp_lg_u32 s4, 2
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: v_cndmask_b32_e32 v2, 5, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v2, 5, v0, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s9 ; SI-NEXT: v_mov_b32_e32 v0, s9
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 ; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, 5, v0, vcc
; SI-NEXT: v_mov_b32_e32 v0, s8 ; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; SI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: dynamic_insertelement_v3i32: ; VI-LABEL: dynamic_insertelement_v3i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10 ; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
Show All 23 Lines
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4 ; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4
; SI-NEXT: s_load_dword s6, s[4:5], 0x8 ; SI-NEXT: s_load_dword s6, s[4:5], 0x8
; SI-NEXT: s_load_dword s4, s[4:5], 0x11 ; SI-NEXT: s_load_dword s4, s[4:5], 0x11
; SI-NEXT: s_mov_b32 s3, 0x100f000 ; SI-NEXT: s_mov_b32 s3, 0x100f000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s11 ; SI-NEXT: v_mov_b32_e32 v0, s11
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s6, 3 ; SI-NEXT: s_cmp_eq_u32 s6, 3
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v4, s4 ; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: s_cmp_eq_u32 s6, 2
; SI-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s10 ; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s6, 2 ; SI-NEXT: s_cmp_eq_u32 s6, 1
; SI-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s9 ; SI-NEXT: v_mov_b32_e32 v0, s9
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s6, 1 ; SI-NEXT: s_cmp_eq_u32 s6, 0
; SI-NEXT: v_cndmask_b32_e32 v1, v0, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, v0, v4, vcc
; SI-NEXT: v_mov_b32_e32 v0, s8 ; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s6, 0 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: dynamic_insertelement_v4i32: ; VI-LABEL: dynamic_insertelement_v4i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10 ; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
Show All 26 Lines
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8 ; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8
; SI-NEXT: s_load_dword s4, s[4:5], 0x10 ; SI-NEXT: s_load_dword s4, s[4:5], 0x10
; SI-NEXT: s_mov_b32 s3, 0x100f000 ; SI-NEXT: s_mov_b32 s3, 0x100f000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s11 ; SI-NEXT: v_mov_b32_e32 v0, s11
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3 ; SI-NEXT: s_cmp_lg_u32 s4, 3
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 2
; SI-NEXT: v_cndmask_b32_e32 v3, 5, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v3, 5, v0, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s10 ; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 ; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: v_cndmask_b32_e32 v2, 5, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v2, 5, v0, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s9 ; SI-NEXT: v_mov_b32_e32 v0, s9
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 ; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, 5, v0, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s8 ; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 ; SI-NEXT: s_cmp_lg_u32 s4, 7
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v4, s15 ; SI-NEXT: v_mov_b32_e32 v4, s15
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 7 ; SI-NEXT: s_cmp_lg_u32 s4, 6
; SI-NEXT: v_cndmask_b32_e32 v7, 5, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v7, 5, v4, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v4, s14 ; SI-NEXT: v_mov_b32_e32 v4, s14
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 6 ; SI-NEXT: s_cmp_lg_u32 s4, 5
; SI-NEXT: v_cndmask_b32_e32 v6, 5, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v6, 5, v4, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v4, s13 ; SI-NEXT: v_mov_b32_e32 v4, s13
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 5 ; SI-NEXT: s_cmp_lg_u32 s4, 4
; SI-NEXT: v_cndmask_b32_e32 v5, 5, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v5, 5, v4, vcc
; SI-NEXT: v_mov_b32_e32 v4, s12 ; SI-NEXT: v_mov_b32_e32 v4, s12
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 4 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 ; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: dynamic_insertelement_v8i32: ; VI-LABEL: dynamic_insertelement_v8i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
▲ Show 20 Lines • Show All 376 Lines • ▼ Show 20 Lines
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4 ; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4
; SI-NEXT: s_load_dword s4, s[4:5], 0x8 ; SI-NEXT: s_load_dword s4, s[4:5], 0x8
; SI-NEXT: s_mov_b32 s3, 0x100f000 ; SI-NEXT: s_mov_b32 s3, 0x100f000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshr_b32 s5, s11, 24 ; SI-NEXT: s_lshr_b32 s5, s11, 24
; SI-NEXT: s_cmp_lg_u32 s4, 15
; SI-NEXT: v_mov_b32_e32 v0, s5 ; SI-NEXT: v_mov_b32_e32 v0, s5
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 15 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_lshr_b32 s5, s11, 16 ; SI-NEXT: s_lshr_b32 s5, s11, 16
; SI-NEXT: s_cmp_lg_u32 s4, 14
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; SI-NEXT: v_mov_b32_e32 v1, s5 ; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 14 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_lshr_b32 s6, s11, 8
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; SI-NEXT: s_movk_i32 s5, 0xff ; SI-NEXT: s_movk_i32 s5, 0xff
; SI-NEXT: s_cmp_lg_u32 s4, 13
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; SI-NEXT: v_and_b32_e32 v1, s5, v1 ; SI-NEXT: v_and_b32_e32 v1, s5, v1
; SI-NEXT: s_lshr_b32 s6, s11, 8
; SI-NEXT: v_or_b32_e32 v0, v1, v0 ; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_mov_b32_e32 v1, s6 ; SI-NEXT: v_mov_b32_e32 v1, s6
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 13 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 12
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v2, s11 ; SI-NEXT: v_mov_b32_e32 v2, s11
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 12
; SI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc ; SI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_and_b32_e32 v2, s5, v2 ; SI-NEXT: v_and_b32_e32 v2, s5, v2
; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: s_mov_b32 s6, 0xffff ; SI-NEXT: s_mov_b32 s6, 0xffff
; SI-NEXT: s_lshr_b32 s7, s10, 24
; SI-NEXT: s_cmp_lg_u32 s4, 11
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_and_b32_e32 v1, s6, v1 ; SI-NEXT: v_and_b32_e32 v1, s6, v1
; SI-NEXT: s_lshr_b32 s7, s10, 24
; SI-NEXT: v_or_b32_e32 v3, v1, v0 ; SI-NEXT: v_or_b32_e32 v3, v1, v0
; SI-NEXT: v_mov_b32_e32 v0, s7 ; SI-NEXT: v_mov_b32_e32 v0, s7
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 11 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_lshr_b32 s7, s10, 16 ; SI-NEXT: s_lshr_b32 s7, s10, 16
; SI-NEXT: s_cmp_lg_u32 s4, 10
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; SI-NEXT: v_mov_b32_e32 v1, s7 ; SI-NEXT: v_mov_b32_e32 v1, s7
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 10 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; SI-NEXT: s_lshr_b32 s7, s10, 8
; SI-NEXT: s_cmp_lg_u32 s4, 9
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; SI-NEXT: v_and_b32_e32 v1, s5, v1 ; SI-NEXT: v_and_b32_e32 v1, s5, v1
; SI-NEXT: s_lshr_b32 s7, s10, 8
; SI-NEXT: v_or_b32_e32 v0, v1, v0 ; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v1, s7 ; SI-NEXT: v_mov_b32_e32 v1, s7
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 9 ; SI-NEXT: s_cmp_lg_u32 s4, 8
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v2, s10 ; SI-NEXT: v_mov_b32_e32 v2, s10
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 8
; SI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc ; SI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_and_b32_e32 v2, s5, v2 ; SI-NEXT: v_and_b32_e32 v2, s5, v2
; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: s_lshr_b32 s7, s9, 24
; SI-NEXT: s_cmp_lg_u32 s4, 7
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_and_b32_e32 v1, s6, v1 ; SI-NEXT: v_and_b32_e32 v1, s6, v1
; SI-NEXT: s_lshr_b32 s7, s9, 24
; SI-NEXT: v_or_b32_e32 v2, v1, v0 ; SI-NEXT: v_or_b32_e32 v2, v1, v0
; SI-NEXT: v_mov_b32_e32 v0, s7 ; SI-NEXT: v_mov_b32_e32 v0, s7
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 7 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_lshr_b32 s7, s9, 16 ; SI-NEXT: s_lshr_b32 s7, s9, 16
; SI-NEXT: s_cmp_lg_u32 s4, 6
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; SI-NEXT: v_mov_b32_e32 v1, s7 ; SI-NEXT: v_mov_b32_e32 v1, s7
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 6 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; SI-NEXT: s_lshr_b32 s7, s9, 8
; SI-NEXT: s_cmp_lg_u32 s4, 5
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; SI-NEXT: v_and_b32_e32 v1, s5, v1 ; SI-NEXT: v_and_b32_e32 v1, s5, v1
; SI-NEXT: s_lshr_b32 s7, s9, 8
; SI-NEXT: v_or_b32_e32 v0, v1, v0 ; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v1, s7 ; SI-NEXT: v_mov_b32_e32 v1, s7
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 5 ; SI-NEXT: s_cmp_lg_u32 s4, 4
; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v4, s9 ; SI-NEXT: v_mov_b32_e32 v4, s9
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 4
; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; SI-NEXT: v_and_b32_e32 v4, s5, v4 ; SI-NEXT: v_and_b32_e32 v4, s5, v4
; SI-NEXT: v_or_b32_e32 v1, v4, v1 ; SI-NEXT: v_or_b32_e32 v1, v4, v1
; SI-NEXT: s_lshr_b32 s7, s8, 24
; SI-NEXT: s_cmp_lg_u32 s4, 3
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_and_b32_e32 v1, s6, v1 ; SI-NEXT: v_and_b32_e32 v1, s6, v1
; SI-NEXT: s_lshr_b32 s7, s8, 24
; SI-NEXT: v_or_b32_e32 v1, v1, v0 ; SI-NEXT: v_or_b32_e32 v1, v1, v0
; SI-NEXT: v_mov_b32_e32 v0, s7 ; SI-NEXT: v_mov_b32_e32 v0, s7
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_lshr_b32 s7, s8, 16 ; SI-NEXT: s_lshr_b32 s7, s8, 16
; SI-NEXT: s_cmp_lg_u32 s4, 2
; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; SI-NEXT: v_mov_b32_e32 v4, s7 ; SI-NEXT: v_mov_b32_e32 v4, s7
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
; SI-NEXT: s_lshr_b32 s7, s8, 8
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; SI-NEXT: v_and_b32_e32 v4, s5, v4 ; SI-NEXT: v_and_b32_e32 v4, s5, v4
; SI-NEXT: s_lshr_b32 s7, s8, 8
; SI-NEXT: v_or_b32_e32 v0, v4, v0 ; SI-NEXT: v_or_b32_e32 v0, v4, v0
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v4, s7 ; SI-NEXT: v_mov_b32_e32 v4, s7
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 ; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
; SI-NEXT: v_mov_b32_e32 v5, s8 ; SI-NEXT: v_mov_b32_e32 v5, s8
; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v5, 5, v5, vcc ; SI-NEXT: v_cndmask_b32_e32 v5, 5, v5, vcc
; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4 ; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; SI-NEXT: v_and_b32_e32 v5, s5, v5 ; SI-NEXT: v_and_b32_e32 v5, s5, v5
; SI-NEXT: v_or_b32_e32 v4, v5, v4 ; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_and_b32_e32 v4, s6, v4 ; SI-NEXT: v_and_b32_e32 v4, s6, v4
; SI-NEXT: v_or_b32_e32 v0, v4, v0 ; SI-NEXT: v_or_b32_e32 v0, v4, v0
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: dynamic_insertelement_v16i8: ; VI-LABEL: dynamic_insertelement_v16i8:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10 ; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
; VI-NEXT: s_load_dword s4, s[4:5], 0x20 ; VI-NEXT: s_load_dword s4, s[4:5], 0x20
; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; VI-NEXT: s_mov_b32 s3, 0x1100f000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshr_b32 s5, s11, 24 ; VI-NEXT: s_lshr_b32 s5, s11, 24
; VI-NEXT: s_cmp_lg_u32 s4, 15
; VI-NEXT: v_mov_b32_e32 v0, s5 ; VI-NEXT: v_mov_b32_e32 v0, s5
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 15 ; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: s_lshr_b32 s5, s11, 16 ; VI-NEXT: s_lshr_b32 s5, s11, 16
; VI-NEXT: s_cmp_lg_u32 s4, 14
; VI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 14 ; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; VI-NEXT: s_lshr_b32 s5, s11, 8 ; VI-NEXT: s_lshr_b32 s5, s11, 8
; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; VI-NEXT: s_cmp_lg_u32 s4, 13
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 13 ; VI-NEXT: s_cmp_lg_u32 s4, 12
; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v2, s11 ; VI-NEXT: v_mov_b32_e32 v2, s11
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 12 ; VI-NEXT: s_lshr_b32 s5, s10, 24
; VI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1 ; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; VI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: s_lshr_b32 s5, s10, 24 ; VI-NEXT: s_cmp_lg_u32 s4, 11
; VI-NEXT: v_or_b32_sdwa v3, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v3, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_mov_b32_e32 v0, s5 ; VI-NEXT: v_mov_b32_e32 v0, s5
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 11 ; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: s_lshr_b32 s5, s10, 16 ; VI-NEXT: s_lshr_b32 s5, s10, 16
; VI-NEXT: s_cmp_lg_u32 s4, 10
; VI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 10 ; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; VI-NEXT: s_lshr_b32 s5, s10, 8 ; VI-NEXT: s_lshr_b32 s5, s10, 8
; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; VI-NEXT: s_cmp_lg_u32 s4, 9
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 9 ; VI-NEXT: s_cmp_lg_u32 s4, 8
; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v2, s10 ; VI-NEXT: v_mov_b32_e32 v2, s10
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 8 ; VI-NEXT: s_lshr_b32 s5, s9, 24
; VI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1 ; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; VI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: s_lshr_b32 s5, s9, 24 ; VI-NEXT: s_cmp_lg_u32 s4, 7
; VI-NEXT: v_or_b32_sdwa v2, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v2, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_mov_b32_e32 v0, s5 ; VI-NEXT: v_mov_b32_e32 v0, s5
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 7 ; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: s_lshr_b32 s5, s9, 16 ; VI-NEXT: s_lshr_b32 s5, s9, 16
; VI-NEXT: s_cmp_lg_u32 s4, 6
; VI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 6 ; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; VI-NEXT: s_lshr_b32 s5, s9, 8 ; VI-NEXT: s_lshr_b32 s5, s9, 8
; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; VI-NEXT: s_cmp_lg_u32 s4, 5
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 5 ; VI-NEXT: s_cmp_lg_u32 s4, 4
; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v4, s9 ; VI-NEXT: v_mov_b32_e32 v4, s9
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 4 ; VI-NEXT: s_lshr_b32 s5, s8, 24
; VI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1 ; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; VI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
; VI-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: s_lshr_b32 s5, s8, 24 ; VI-NEXT: s_cmp_lg_u32 s4, 3
; VI-NEXT: v_or_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_mov_b32_e32 v0, s5 ; VI-NEXT: v_mov_b32_e32 v0, s5
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3 ; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: s_lshr_b32 s5, s8, 16 ; VI-NEXT: s_lshr_b32 s5, s8, 16
; VI-NEXT: s_cmp_lg_u32 s4, 2
; VI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; VI-NEXT: v_mov_b32_e32 v4, s5 ; VI-NEXT: v_mov_b32_e32 v4, s5
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 ; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; VI-NEXT: s_lshr_b32 s5, s8, 8 ; VI-NEXT: s_lshr_b32 s5, s8, 8
; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; VI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v4, s5 ; VI-NEXT: v_mov_b32_e32 v4, s5
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 ; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc ; VI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc
; VI-NEXT: v_mov_b32_e32 v5, s8 ; VI-NEXT: v_mov_b32_e32 v5, s8
; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 ; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v4 ; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v4
; VI-NEXT: v_cndmask_b32_e32 v5, 5, v5, vcc ; VI-NEXT: v_cndmask_b32_e32 v5, 5, v5, vcc
; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%vecins = insertelement <16 x i8> %a, i8 5, i32 %b %vecins = insertelement <16 x i8> %a, i8 5, i32 %b
store <16 x i8> %vecins, <16 x i8> addrspace(1)* %out, align 16 store <16 x i8> %vecins, <16 x i8> addrspace(1)* %out, align 16
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xc ; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xc
; SI-NEXT: s_load_dword s4, s[4:5], 0x18 ; SI-NEXT: s_load_dword s4, s[4:5], 0x18
; SI-NEXT: v_mov_b32_e32 v1, 0x40200000 ; SI-NEXT: v_mov_b32_e32 v1, 0x40200000
; SI-NEXT: s_mov_b32 s3, 0x100f000 ; SI-NEXT: s_mov_b32 s3, 0x100f000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s11 ; SI-NEXT: v_mov_b32_e32 v0, s11
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1 ; SI-NEXT: s_cmp_eq_u32 s4, 1
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
; SI-NEXT: v_mov_b32_e32 v0, s10 ; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: s_cmp_eq_u32 s4, 0
; SI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc
; SI-NEXT: v_mov_b32_e32 v0, s9 ; SI-NEXT: v_mov_b32_e32 v0, s9
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 0 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
; SI-NEXT: v_mov_b32_e32 v0, s8 ; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: dynamic_insertelement_v2f64: ; VI-LABEL: dynamic_insertelement_v2f64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x30 ; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x30
; VI-NEXT: s_load_dword s4, s[4:5], 0x60 ; VI-NEXT: s_load_dword s4, s[4:5], 0x60
; VI-NEXT: v_mov_b32_e32 v1, 0x40200000 ; VI-NEXT: v_mov_b32_e32 v1, 0x40200000
; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; VI-NEXT: s_mov_b32 s3, 0x1100f000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s11 ; VI-NEXT: v_mov_b32_e32 v0, s11
; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1 ; VI-NEXT: s_cmp_eq_u32 s4, 1
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v0, s10 ; VI-NEXT: v_mov_b32_e32 v0, s10
; VI-NEXT: s_cmp_eq_u32 s4, 0
; VI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc ; VI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc
; VI-NEXT: v_mov_b32_e32 v0, s9 ; VI-NEXT: v_mov_b32_e32 v0, s9
; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 0 ; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v0, s8 ; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc ; VI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%vecins = insertelement <2 x double> %a, double 8.0, i32 %b %vecins = insertelement <2 x double> %a, double 8.0, i32 %b
store <2 x double> %vecins, <2 x double> addrspace(1)* %out, align 16 store <2 x double> %vecins, <2 x double> addrspace(1)* %out, align 16
ret void ret void
} }
define amdgpu_kernel void @dynamic_insertelement_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %a, i32 %b) nounwind { define amdgpu_kernel void @dynamic_insertelement_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %a, i32 %b) nounwind {
; SI-LABEL: dynamic_insertelement_v2i64: ; SI-LABEL: dynamic_insertelement_v2i64:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dword s6, s[4:5], 0x8
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4 ; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4
; SI-NEXT: s_load_dword s6, s[4:5], 0x8
; SI-NEXT: s_mov_b32 s3, 0x100f000 ; SI-NEXT: s_mov_b32 s3, 0x100f000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_cmp_eq_u32 s6, 1
; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s11 ; SI-NEXT: v_mov_b32_e32 v0, s11
; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 1
; SI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] ; SI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
; SI-NEXT: v_mov_b32_e32 v0, s10 ; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: s_cmp_eq_u32 s6, 0
; SI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[4:5] ; SI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[4:5]
; SI-NEXT: v_mov_b32_e32 v0, s9 ; SI-NEXT: v_mov_b32_e32 v0, s9
; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 0 ; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5] ; SI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5]
; SI-NEXT: v_mov_b32_e32 v0, s8 ; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[4:5] ; SI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[4:5]
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: dynamic_insertelement_v2i64: ; VI-LABEL: dynamic_insertelement_v2i64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dword s6, s[4:5], 0x20
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10 ; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10
; VI-NEXT: s_load_dword s6, s[4:5], 0x20
; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; VI-NEXT: s_mov_b32 s3, 0x1100f000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_cmp_eq_u32 s6, 1
; VI-NEXT: s_cselect_b64 s[4:5], -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s11 ; VI-NEXT: v_mov_b32_e32 v0, s11
; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 1
; VI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] ; VI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
; VI-NEXT: v_mov_b32_e32 v0, s10 ; VI-NEXT: v_mov_b32_e32 v0, s10
; VI-NEXT: s_cmp_eq_u32 s6, 0
; VI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[4:5] ; VI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[4:5]
; VI-NEXT: v_mov_b32_e32 v0, s9 ; VI-NEXT: v_mov_b32_e32 v0, s9
; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 0 ; VI-NEXT: s_cselect_b64 s[4:5], -1, 0
; VI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5] ; VI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5]
; VI-NEXT: v_mov_b32_e32 v0, s8 ; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[4:5] ; VI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[4:5]
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%vecins = insertelement <2 x i64> %a, i64 5, i32 %b %vecins = insertelement <2 x i64> %a, i64 5, i32 %b
store <2 x i64> %vecins, <2 x i64> addrspace(1)* %out, align 8 store <2 x i64> %vecins, <2 x i64> addrspace(1)* %out, align 8
ret void ret void
} }
define amdgpu_kernel void @dynamic_insertelement_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> %a, i32 %b) nounwind { define amdgpu_kernel void @dynamic_insertelement_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> %a, i32 %b) nounwind {
; SI-LABEL: dynamic_insertelement_v3i64: ; SI-LABEL: dynamic_insertelement_v3i64:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x8 ; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x8
; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xc ; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xc
; SI-NEXT: s_load_dword s12, s[4:5], 0x10 ; SI-NEXT: s_load_dword s12, s[4:5], 0x10
; SI-NEXT: s_mov_b32 s3, 0x100f000 ; SI-NEXT: s_mov_b32 s3, 0x100f000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s11 ; SI-NEXT: v_mov_b32_e32 v0, s11
; SI-NEXT: v_mov_b32_e32 v4, s7 ; SI-NEXT: v_mov_b32_e32 v4, s7
; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], s12, 1 ; SI-NEXT: s_cmp_eq_u32 s12, 1
; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] ; SI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
; SI-NEXT: v_mov_b32_e32 v0, s10 ; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: s_cmp_eq_u32 s12, 0
; SI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[4:5] ; SI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[4:5]
; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s9 ; SI-NEXT: v_mov_b32_e32 v0, s9
; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], s12, 0
; SI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5] ; SI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5]
; SI-NEXT: v_mov_b32_e32 v0, s8 ; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_cmp_eq_u32 s12, 2
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[4:5] ; SI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[4:5]
; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], s12, 2 ; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v5, v4, 0, s[4:5] ; SI-NEXT: v_cndmask_b32_e64 v5, v4, 0, s[4:5]
; SI-NEXT: v_mov_b32_e32 v4, s6 ; SI-NEXT: v_mov_b32_e32 v4, s6
; SI-NEXT: v_cndmask_b32_e64 v4, v4, 5, s[4:5] ; SI-NEXT: v_cndmask_b32_e64 v4, v4, 5, s[4:5]
; SI-NEXT: buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:16 ; SI-NEXT: buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: dynamic_insertelement_v3i64: ; VI-LABEL: dynamic_insertelement_v3i64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x20 ; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x20
; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x30 ; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x30
; VI-NEXT: s_load_dword s12, s[4:5], 0x40 ; VI-NEXT: s_load_dword s12, s[4:5], 0x40
; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; VI-NEXT: s_mov_b32 s3, 0x1100f000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s11 ; VI-NEXT: v_mov_b32_e32 v0, s11
; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], s12, 1 ; VI-NEXT: s_cmp_eq_u32 s12, 1
; VI-NEXT: s_cselect_b64 s[4:5], -1, 0
; VI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] ; VI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
; VI-NEXT: v_mov_b32_e32 v0, s10 ; VI-NEXT: v_mov_b32_e32 v0, s10
; VI-NEXT: s_cmp_eq_u32 s12, 0
; VI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[4:5] ; VI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[4:5]
; VI-NEXT: s_cselect_b64 s[4:5], -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s9 ; VI-NEXT: v_mov_b32_e32 v0, s9
; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], s12, 0
; VI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5] ; VI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5]
; VI-NEXT: v_mov_b32_e32 v0, s8 ; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: s_cmp_eq_u32 s12, 2
; VI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[4:5] ; VI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[4:5]
; VI-NEXT: v_mov_b32_e32 v4, s7 ; VI-NEXT: v_mov_b32_e32 v4, s7
; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], s12, 2 ; VI-NEXT: s_cselect_b64 s[4:5], -1, 0
; VI-NEXT: v_cndmask_b32_e64 v5, v4, 0, s[4:5] ; VI-NEXT: v_cndmask_b32_e64 v5, v4, 0, s[4:5]
; VI-NEXT: v_mov_b32_e32 v4, s6 ; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_cndmask_b32_e64 v4, v4, 5, s[4:5] ; VI-NEXT: v_cndmask_b32_e64 v4, v4, 5, s[4:5]
; VI-NEXT: buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:16 ; VI-NEXT: buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:16
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%vecins = insertelement <3 x i64> %a, i64 5, i32 %b %vecins = insertelement <3 x i64> %a, i64 5, i32 %b
store <3 x i64> %vecins, <3 x i64> addrspace(1)* %out, align 32 store <3 x i64> %vecins, <3 x i64> addrspace(1)* %out, align 32
ret void ret void
} }
define amdgpu_kernel void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, i32 %b) nounwind { define amdgpu_kernel void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, i32 %b) nounwind {
; SI-LABEL: dynamic_insertelement_v4f64: ; SI-LABEL: dynamic_insertelement_v4f64:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8 ; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8
; SI-NEXT: s_load_dword s4, s[4:5], 0x10 ; SI-NEXT: s_load_dword s4, s[4:5], 0x10
; SI-NEXT: v_mov_b32_e32 v4, 0x40200000 ; SI-NEXT: v_mov_b32_e32 v4, 0x40200000
; SI-NEXT: s_mov_b32 s3, 0x100f000 ; SI-NEXT: s_mov_b32 s3, 0x100f000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s11 ; SI-NEXT: v_mov_b32_e32 v0, s11
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1 ; SI-NEXT: s_cmp_eq_u32 s4, 1
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; SI-NEXT: v_mov_b32_e32 v0, s10 ; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: s_cmp_eq_u32 s4, 0
; SI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s9 ; SI-NEXT: v_mov_b32_e32 v0, s9
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 0
; SI-NEXT: v_cndmask_b32_e32 v1, v0, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v1, v0, v4, vcc
; SI-NEXT: v_mov_b32_e32 v0, s8 ; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_cmp_eq_u32 s4, 3
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v5, s15 ; SI-NEXT: v_mov_b32_e32 v5, s15
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 3
; SI-NEXT: v_cndmask_b32_e32 v7, v5, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v7, v5, v4, vcc
; SI-NEXT: v_mov_b32_e32 v5, s14 ; SI-NEXT: v_mov_b32_e32 v5, s14
; SI-NEXT: s_cmp_eq_u32 s4, 2
; SI-NEXT: v_cndmask_b32_e64 v6, v5, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v6, v5, 0, vcc
; SI-NEXT: v_mov_b32_e32 v5, s13 ; SI-NEXT: v_mov_b32_e32 v5, s13
; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 2 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc
; SI-NEXT: v_mov_b32_e32 v4, s12 ; SI-NEXT: v_mov_b32_e32 v4, s12
; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 ; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: dynamic_insertelement_v4f64: ; VI-LABEL: dynamic_insertelement_v4f64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x20 ; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x20
; VI-NEXT: s_load_dword s4, s[4:5], 0x40 ; VI-NEXT: s_load_dword s4, s[4:5], 0x40
; VI-NEXT: v_mov_b32_e32 v4, 0x40200000 ; VI-NEXT: v_mov_b32_e32 v4, 0x40200000
; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; VI-NEXT: s_mov_b32 s3, 0x1100f000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s11 ; VI-NEXT: v_mov_b32_e32 v0, s11
; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1 ; VI-NEXT: s_cmp_eq_u32 s4, 1
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc ; VI-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; VI-NEXT: v_mov_b32_e32 v0, s10 ; VI-NEXT: v_mov_b32_e32 v0, s10
; VI-NEXT: s_cmp_eq_u32 s4, 0
; VI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc ; VI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s9 ; VI-NEXT: v_mov_b32_e32 v0, s9
; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 0
; VI-NEXT: v_cndmask_b32_e32 v1, v0, v4, vcc ; VI-NEXT: v_cndmask_b32_e32 v1, v0, v4, vcc
; VI-NEXT: v_mov_b32_e32 v0, s8 ; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: s_cmp_eq_u32 s4, 3
; VI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc ; VI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_mov_b32_e32 v5, s15 ; VI-NEXT: v_mov_b32_e32 v5, s15
; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 3
; VI-NEXT: v_cndmask_b32_e32 v7, v5, v4, vcc ; VI-NEXT: v_cndmask_b32_e32 v7, v5, v4, vcc
; VI-NEXT: v_mov_b32_e32 v5, s14 ; VI-NEXT: v_mov_b32_e32 v5, s14
; VI-NEXT: s_cmp_eq_u32 s4, 2
; VI-NEXT: v_cndmask_b32_e64 v6, v5, 0, vcc ; VI-NEXT: v_cndmask_b32_e64 v6, v5, 0, vcc
; VI-NEXT: v_mov_b32_e32 v5, s13 ; VI-NEXT: v_mov_b32_e32 v5, s13
; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 2 ; VI-NEXT: s_cselect_b64 vcc, -1, 0
; VI-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc ; VI-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc
; VI-NEXT: v_mov_b32_e32 v4, s12 ; VI-NEXT: v_mov_b32_e32 v4, s12
; VI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc ; VI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 ; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%vecins = insertelement <4 x double> %a, double 8.0, i32 %b %vecins = insertelement <4 x double> %a, double 8.0, i32 %b
store <4 x double> %vecins, <4 x double> addrspace(1)* %out, align 16 store <4 x double> %vecins, <4 x double> addrspace(1)* %out, align 16
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll

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; GCN: v_div_fmas_f64 ; GCN: v_div_fmas_f64
define amdgpu_kernel void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind { define amdgpu_kernel void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind {
%result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone %result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone
store double %result, double addrspace(1)* %out, align 8 store double %result, double addrspace(1)* %out, align 8
ret void ret void
} }
; GCN-LABEL: {{^}}test_div_fmas_f32_cond_to_vcc: ; GCN-LABEL: {{^}}test_div_fmas_f32_cond_to_vcc:
; GCN: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}} ; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}}
; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} ; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
define amdgpu_kernel void @test_div_fmas_f32_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c, i32 %i) nounwind { define amdgpu_kernel void @test_div_fmas_f32_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c, i32 %i) nounwind {
%cmp = icmp eq i32 %i, 0 %cmp = icmp eq i32 %i, 0
%result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cmp) nounwind readnone %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cmp) nounwind readnone
store float %result, float addrspace(1)* %out, align 4 store float %result, float addrspace(1)* %out, align 4
ret void ret void
} }
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} }
; GCN-LABEL: {{^}}test_div_fmas_f32_logical_cond_to_vcc: ; GCN-LABEL: {{^}}test_div_fmas_f32_logical_cond_to_vcc:
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}} ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}}
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}} ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: v_cmp_eq_u32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}} ; SI-DAG: v_cmp_eq_u32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}}
; SI-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}} ; SI-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0{{$}}
; SI-DAG: s_cselect_b64 [[CMP1:s\[[0-9]+:[0-9]+\]]], -1, 0
; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]] ; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]]
; SI: v_div_fmas_f32 {{v[0-9]+}}, [[A]], [[B]], [[C]] ; SI: v_div_fmas_f32 {{v[0-9]+}}, [[A]], [[B]], [[C]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 %d) nounwind { define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 %d) nounwind {
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
%gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid
%gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1 %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1
%gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2 %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.ll

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; SI: v_cmp_le_i32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[CVT]], [[K]] ; SI: v_cmp_le_i32_e64 s{{\[[0-9]+:[0-9]+\]}}, [[CVT]], [[K]]
define amdgpu_kernel void @v_icmp_i16_sle(i64 addrspace(1)* %out, i16 %src) { define amdgpu_kernel void @v_icmp_i16_sle(i64 addrspace(1)* %out, i16 %src) {
%result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 41) %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 41)
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_icmp_i1_ne0: ; GCN-LABEL: {{^}}v_icmp_i1_ne0:
; GCN: v_cmp_gt_u32_e64 s[[C0:\[[0-9]+:[0-9]+\]]], ; GCN: s_cmp_gt_u32
; GCN: v_cmp_gt_u32_e64 s[[C1:\[[0-9]+:[0-9]+\]]], ; GCN: s_cselect_b64 s[[C0:\[[0-9]+:[0-9]+\]]], -1, 0
; GCN: s_cmp_gt_u32
; GCN: s_cselect_b64 s[[C1:\[[0-9]+:[0-9]+\]]], -1, 0
; GCN: s_and_b64 s[[SRC:\[[0-9]+:[0-9]+\]]], s[[C0]], s[[C1]] ; GCN: s_and_b64 s[[SRC:\[[0-9]+:[0-9]+\]]], s[[C0]], s[[C1]]
; SI-NEXT: s_mov_b32 s{{[0-9]+}}, -1 ; SI-NEXT: s_mov_b32 s{{[0-9]+}}, -1
; GCN-NEXT: v_mov_b32_e32 ; GCN-NEXT: v_mov_b32_e32
; GCN-NEXT: v_mov_b32_e32 ; GCN-NEXT: v_mov_b32_e32
; GCN: {{global|flat|buffer}}_store_dwordx2 ; GCN: {{global|flat|buffer}}_store_dwordx2
define amdgpu_kernel void @v_icmp_i1_ne0(i64 addrspace(1)* %out, i32 %a, i32 %b) { define amdgpu_kernel void @v_icmp_i1_ne0(i64 addrspace(1)* %out, i32 %a, i32 %b) {
%c0 = icmp ugt i32 %a, 1 %c0 = icmp ugt i32 %a, 1
%c1 = icmp ugt i32 %b, 2 %c1 = icmp ugt i32 %b, 2
%src = and i1 %c0, %c1 %src = and i1 %c0, %c1
%result = call i64 @llvm.amdgcn.icmp.i1(i1 %src, i1 false, i32 33) %result = call i64 @llvm.amdgcn.icmp.i1(i1 %src, i1 false, i32 33)
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
attributes #0 = { nounwind readnone convergent } attributes #0 = { nounwind readnone convergent }

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll

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; GCN-LABEL: {{^}}is_private_sgpr: ; GCN-LABEL: {{^}}is_private_sgpr:
; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11{{$}} ; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11{{$}}
; GFX9-DAG: s_getreg_b32 [[APERTURE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16) ; GFX9-DAG: s_getreg_b32 [[APERTURE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16)
; CI-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[6:7], 0x1{{$}} ; CI-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[6:7], 0x1{{$}}
; GFX9-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[6:7], 0x4{{$}} ; GFX9-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[6:7], 0x4{{$}}
; GFX9: s_lshl_b32 [[APERTURE]], [[APERTURE]], 16 ; GFX9: s_lshl_b32 [[APERTURE]], [[APERTURE]], 16
; GCN: v_mov_b32_e32 [[V_APERTURE:v[0-9]+]], [[APERTURE]] ; GCN: s_cmp_eq_u32 [[PTR_HI]], [[APERTURE]]
; GCN: v_cmp_eq_u32_e32 vcc, [[PTR_HI]], [[V_APERTURE]]
; GCN: s_cbranch_vccnz ; GCN: s_cbranch_vccnz
define amdgpu_kernel void @is_private_sgpr(i8* %ptr) { define amdgpu_kernel void @is_private_sgpr(i8* %ptr) {
%val = call i1 @llvm.amdgcn.is.private(i8* %ptr) %val = call i1 @llvm.amdgcn.is.private(i8* %ptr)
br i1 %val, label %bb0, label %bb1 br i1 %val, label %bb0, label %bb1
bb0: bb0:
store volatile i32 0, i32 addrspace(1)* undef store volatile i32 0, i32 addrspace(1)* undef
br label %bb1 br label %bb1
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll

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; GCN-LABEL: {{^}}is_local_sgpr: ; GCN-LABEL: {{^}}is_local_sgpr:
; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}} ; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}}
; GFX9-DAG: s_getreg_b32 [[APERTURE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) ; GFX9-DAG: s_getreg_b32 [[APERTURE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16)
; GFX9-DAG: s_lshl_b32 [[APERTURE]], [[APERTURE]], 16 ; GFX9-DAG: s_lshl_b32 [[APERTURE]], [[APERTURE]], 16
; CI-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[6:7], 0x1{{$}} ; CI-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[6:7], 0x1{{$}}
; GFX9-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[6:7], 0x4{{$}} ; GFX9-DAG: s_load_dword [[PTR_HI:s[0-9]+]], s[6:7], 0x4{{$}}
; GCN: v_mov_b32_e32 [[V_APERTURE:v[0-9]+]], [[APERTURE]] ; GCN: s_cmp_eq_u32 [[PTR_HI]], [[APERTURE]]
; GCN: v_cmp_eq_u32_e32 vcc, [[PTR_HI]], [[V_APERTURE]]
; GCN: s_cbranch_vccnz ; GCN: s_cbranch_vccnz
define amdgpu_kernel void @is_local_sgpr(i8* %ptr) { define amdgpu_kernel void @is_local_sgpr(i8* %ptr) {
%val = call i1 @llvm.amdgcn.is.shared(i8* %ptr) %val = call i1 @llvm.amdgcn.is.shared(i8* %ptr)
br i1 %val, label %bb0, label %bb1 br i1 %val, label %bb0, label %bb1
bb0: bb0:
store volatile i32 0, i32 addrspace(1)* undef store volatile i32 0, i32 addrspace(1)* undef
br label %bb1 br label %bb1
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll

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; GCN-NOT: v_cmp_le_f32_e64 ; GCN-NOT: v_cmp_le_f32_e64
define amdgpu_ps void @test_non_inline_imm_sgpr(float inreg %a) #0 { define amdgpu_ps void @test_non_inline_imm_sgpr(float inreg %a) #0 {
%c = fcmp ole float %a, 1.500000e+00 %c = fcmp ole float %a, 1.500000e+00
call void @llvm.amdgcn.kill(i1 %c) #1 call void @llvm.amdgcn.kill(i1 %c) #1
ret void ret void
} }
; GCN-LABEL: {{^}}test_scc_liveness: ; GCN-LABEL: {{^}}test_scc_liveness:
; GCN: v_cmp ; GCN: s_cmp
; GCN: s_and_b64 exec ; GCN: s_and_b64 exec
; GCN: s_cmp ; GCN: s_cmp
; GCN: s_cbranch_scc ; GCN: s_cbranch_scc
define amdgpu_ps void @test_scc_liveness() #0 { define amdgpu_ps void @test_scc_liveness() #0 {
main_body: main_body:
br label %loop3 br label %loop3
loop3: ; preds = %loop3, %main_body loop3: ; preds = %loop3, %main_body
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llvm/test/CodeGen/AMDGPU/llvm.mulo.ll

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; GFX9-NEXT: s_mul_hi_u32 s10, s1, s3 ; GFX9-NEXT: s_mul_hi_u32 s10, s1, s3
; GFX9-NEXT: s_addc_u32 s4, s5, s4 ; GFX9-NEXT: s_addc_u32 s4, s5, s4
; GFX9-NEXT: s_addc_u32 s5, s10, 0 ; GFX9-NEXT: s_addc_u32 s5, s10, 0
; GFX9-NEXT: s_mul_i32 s1, s1, s3 ; GFX9-NEXT: s_mul_i32 s1, s1, s3
; GFX9-NEXT: s_add_u32 s4, s4, s1 ; GFX9-NEXT: s_add_u32 s4, s4, s1
; GFX9-NEXT: s_addc_u32 s5, 0, s5 ; GFX9-NEXT: s_addc_u32 s5, 0, s5
; GFX9-NEXT: s_add_i32 s1, s8, s7 ; GFX9-NEXT: s_add_i32 s1, s8, s7
; GFX9-NEXT: s_add_i32 s1, s1, s6 ; GFX9-NEXT: s_add_i32 s1, s1, s6
; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0
; GFX9-NEXT: s_mul_i32 s2, s0, s2 ; GFX9-NEXT: s_mul_i32 s2, s0, s2
; GFX9-NEXT: v_mov_b32_e32 v0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_cmp_ne_u64_e64 s[0:1], s[4:5], 0 ; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1]
; GFX9-NEXT: global_store_dwordx2 v[0:1], v[0:1], off ; GFX9-NEXT: global_store_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: umulo_i64_s: ; GFX10-LABEL: umulo_i64_s:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
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; GFX10-NEXT: s_add_u32 s3, s8, s7 ; GFX10-NEXT: s_add_u32 s3, s8, s7
; GFX10-NEXT: s_addc_u32 s5, 0, s5 ; GFX10-NEXT: s_addc_u32 s5, 0, s5
; GFX10-NEXT: s_add_u32 s3, s3, s6 ; GFX10-NEXT: s_add_u32 s3, s3, s6
; GFX10-NEXT: s_addc_u32 s3, s5, s4 ; GFX10-NEXT: s_addc_u32 s3, s5, s4
; GFX10-NEXT: s_addc_u32 s5, s9, 0 ; GFX10-NEXT: s_addc_u32 s5, s9, 0
; GFX10-NEXT: s_add_u32 s4, s3, s1 ; GFX10-NEXT: s_add_u32 s4, s3, s1
; GFX10-NEXT: s_addc_u32 s5, 0, s5 ; GFX10-NEXT: s_addc_u32 s5, 0, s5
; GFX10-NEXT: s_add_i32 s1, s8, s7 ; GFX10-NEXT: s_add_i32 s1, s8, s7
; GFX10-NEXT: v_cmp_ne_u64_e64 s3, s[4:5], 0
; GFX10-NEXT: s_add_i32 s1, s1, s6
; GFX10-NEXT: s_mul_i32 s0, s0, s2 ; GFX10-NEXT: s_mul_i32 s0, s0, s2
; GFX10-NEXT: v_cndmask_b32_e64 v1, s1, 0, s3 ; GFX10-NEXT: s_add_i32 s1, s1, s6
; GFX10-NEXT: v_cndmask_b32_e64 v0, s0, 0, s3 ; GFX10-NEXT: s_cmp_lg_u64 s[4:5], 0
; GFX10-NEXT: s_cselect_b32 s2, -1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v1, s1, 0, s2
; GFX10-NEXT: v_cndmask_b32_e64 v0, s0, 0, s2
; GFX10-NEXT: global_store_dwordx2 v[0:1], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
%umulo = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %x, i64 %y) %umulo = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %x, i64 %y)
%mul = extractvalue { i64, i1 } %umulo, 0 %mul = extractvalue { i64, i1 } %umulo, 0
%overflow = extractvalue { i64, i1 } %umulo, 1 %overflow = extractvalue { i64, i1 } %umulo, 1
%res = select i1 %overflow, i64 0, i64 %mul %res = select i1 %overflow, i64 0, i64 %mul
store i64 %res, i64 addrspace(1)* undef store i64 %res, i64 addrspace(1)* undef
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; SI-NEXT: v_mul_hi_u32 v2, s1, v1 ; SI-NEXT: v_mul_hi_u32 v2, s1, v1
; SI-NEXT: s_mul_i32 s4, s1, s2 ; SI-NEXT: s_mul_i32 s4, s1, s2
; SI-NEXT: v_mov_b32_e32 v3, s3 ; SI-NEXT: v_mov_b32_e32 v3, s3
; SI-NEXT: v_mul_hi_u32 v4, s0, v3 ; SI-NEXT: v_mul_hi_u32 v4, s0, v3
; SI-NEXT: s_mul_i32 s5, s0, s3 ; SI-NEXT: s_mul_i32 s5, s0, s3
; SI-NEXT: v_mul_hi_u32 v1, s0, v1 ; SI-NEXT: v_mul_hi_u32 v1, s0, v1
; SI-NEXT: v_mul_hi_i32 v3, s1, v3 ; SI-NEXT: v_mul_hi_i32 v3, s1, v3
; SI-NEXT: s_mul_i32 s6, s1, s3 ; SI-NEXT: s_mul_i32 s6, s1, s3
; SI-NEXT: s_mul_i32 s8, s0, s2 ; SI-NEXT: s_cmp_lt_i32 s1, 0
; SI-NEXT: s_mul_i32 s1, s0, s2
; SI-NEXT: v_add_i32_e32 v5, vcc, s5, v1 ; SI-NEXT: v_add_i32_e32 v5, vcc, s5, v1
; SI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc ; SI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
; SI-NEXT: v_mov_b32_e32 v6, s8 ; SI-NEXT: v_mov_b32_e32 v6, s1
; SI-NEXT: v_add_i32_e32 v5, vcc, s4, v5 ; SI-NEXT: v_add_i32_e32 v5, vcc, s4, v5
; SI-NEXT: v_addc_u32_e32 v2, vcc, v4, v2, vcc ; SI-NEXT: v_addc_u32_e32 v2, vcc, v4, v2, vcc
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v1, vcc, s5, v1 ; SI-NEXT: v_add_i32_e32 v1, vcc, s5, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2 ; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_addc_u32_e32 v3, vcc, v0, v3, vcc ; SI-NEXT: v_addc_u32_e32 v3, vcc, v0, v3, vcc
; SI-NEXT: v_add_i32_e32 v4, vcc, s4, v1 ; SI-NEXT: v_add_i32_e32 v4, vcc, s4, v1
; SI-NEXT: v_subrev_i32_e32 v1, vcc, s2, v2 ; SI-NEXT: v_subrev_i32_e32 v1, vcc, s2, v2
; SI-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v3, vcc ; SI-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v3, vcc
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_cmp_lt_i32 s3, 0
; SI-NEXT: v_ashrrev_i32_e32 v0, 31, v4 ; SI-NEXT: v_ashrrev_i32_e32 v0, 31, v4
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s1, 0
; SI-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; SI-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; SI-NEXT: v_cndmask_b32_e32 v2, v2, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v2, v2, v1, vcc
; SI-NEXT: v_mov_b32_e32 v1, v0 ; SI-NEXT: v_mov_b32_e32 v1, v0
; SI-NEXT: v_subrev_i32_e32 v5, vcc, s0, v2 ; SI-NEXT: v_subrev_i32_e32 v5, vcc, s0, v2
; SI-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v3, vcc ; SI-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v3, vcc
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s3, 0 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc ; SI-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; SI-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc ; SI-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; SI-NEXT: v_cmp_ne_u64_e32 vcc, v[2:3], v[0:1] ; SI-NEXT: v_cmp_ne_u64_e32 vcc, v[2:3], v[0:1]
; SI-NEXT: v_cndmask_b32_e64 v1, v4, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v1, v4, 0, vcc
; SI-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
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; GFX9-NEXT: s_mul_hi_i32 s10, s1, s3 ; GFX9-NEXT: s_mul_hi_i32 s10, s1, s3
; GFX9-NEXT: s_addc_u32 s4, s6, s4 ; GFX9-NEXT: s_addc_u32 s4, s6, s4
; GFX9-NEXT: s_addc_u32 s6, s10, 0 ; GFX9-NEXT: s_addc_u32 s6, s10, 0
; GFX9-NEXT: s_mul_i32 s9, s1, s3 ; GFX9-NEXT: s_mul_i32 s9, s1, s3
; GFX9-NEXT: s_add_u32 s4, s4, s9 ; GFX9-NEXT: s_add_u32 s4, s4, s9
; GFX9-NEXT: s_addc_u32 s6, 0, s6 ; GFX9-NEXT: s_addc_u32 s6, 0, s6
; GFX9-NEXT: s_sub_u32 s9, s4, s2 ; GFX9-NEXT: s_sub_u32 s9, s4, s2
; GFX9-NEXT: s_subb_u32 s10, s6, 0 ; GFX9-NEXT: s_subb_u32 s10, s6, 0
; GFX9-NEXT: v_cmp_lt_i32_e64 vcc, s1, 0 ; GFX9-NEXT: s_cmp_lt_i32 s1, 0
; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: v_mov_b32_e32 v1, s10 ; GFX9-NEXT: v_mov_b32_e32 v1, s10
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_mov_b32_e32 v2, s9 ; GFX9-NEXT: v_mov_b32_e32 v2, s9
; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s0, v2 ; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s0, v2
; GFX9-NEXT: s_add_i32 s1, s8, s7
; GFX9-NEXT: v_subbrev_co_u32_e32 v1, vcc, 0, v0, vcc ; GFX9-NEXT: v_subbrev_co_u32_e32 v1, vcc, 0, v0, vcc
; GFX9-NEXT: s_cmp_lt_i32 s3, 0
; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
; GFX9-NEXT: s_add_i32 s1, s8, s7
; GFX9-NEXT: s_add_i32 s1, s1, s5 ; GFX9-NEXT: s_add_i32 s1, s1, s5
; GFX9-NEXT: v_cmp_lt_i32_e64 vcc, s3, 0
; GFX9-NEXT: s_ashr_i32 s4, s1, 31 ; GFX9-NEXT: s_ashr_i32 s4, s1, 31
; GFX9-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
; GFX9-NEXT: s_mov_b32 s5, s4 ; GFX9-NEXT: s_mov_b32 s5, s4
; GFX9-NEXT: s_mul_i32 s0, s0, s2 ; GFX9-NEXT: s_mul_i32 s0, s0, s2
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, s[4:5], v[0:1] ; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, s[4:5], v[0:1]
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v2, s1 ; GFX9-NEXT: v_mov_b32_e32 v2, s1
Show All 17 Lines
; GFX10-NEXT: s_mul_hi_i32 s9, s1, s3 ; GFX10-NEXT: s_mul_hi_i32 s9, s1, s3
; GFX10-NEXT: s_addc_u32 s4, s6, s4 ; GFX10-NEXT: s_addc_u32 s4, s6, s4
; GFX10-NEXT: s_mul_i32 s10, s1, s3 ; GFX10-NEXT: s_mul_i32 s10, s1, s3
; GFX10-NEXT: s_addc_u32 s6, s9, 0 ; GFX10-NEXT: s_addc_u32 s6, s9, 0
; GFX10-NEXT: s_add_u32 s4, s4, s10 ; GFX10-NEXT: s_add_u32 s4, s4, s10
; GFX10-NEXT: s_addc_u32 s6, 0, s6 ; GFX10-NEXT: s_addc_u32 s6, 0, s6
; GFX10-NEXT: s_sub_u32 s9, s4, s2 ; GFX10-NEXT: s_sub_u32 s9, s4, s2
; GFX10-NEXT: s_subb_u32 s10, s6, 0 ; GFX10-NEXT: s_subb_u32 s10, s6, 0
; GFX10-NEXT: v_cmp_lt_i32_e64 vcc_lo, s1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, s9
; GFX10-NEXT: v_mov_b32_e32 v0, s9 ; GFX10-NEXT: s_cmp_lt_i32 s1, 0
; GFX10-NEXT: v_mov_b32_e32 v1, s10 ; GFX10-NEXT: v_mov_b32_e32 v0, s10
; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX10-NEXT: s_cmp_lt_i32 s3, 0
; GFX10-NEXT: v_cndmask_b32_e32 v2, s4, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, s6, v0, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v3, vcc_lo, v2, s0
; GFX10-NEXT: s_mul_i32 s0, s0, s2
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v0, vcc_lo
; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX10-NEXT: s_add_i32 s1, s8, s7 ; GFX10-NEXT: s_add_i32 s1, s8, s7
; GFX10-NEXT: s_add_i32 s1, s1, s5 ; GFX10-NEXT: s_add_i32 s1, s1, s5
; GFX10-NEXT: v_cndmask_b32_e32 v0, s4, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, s6, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
; GFX10-NEXT: s_ashr_i32 s4, s1, 31 ; GFX10-NEXT: s_ashr_i32 s4, s1, 31
; GFX10-NEXT: s_mov_b32 s5, s4 ; GFX10-NEXT: s_mov_b32 s5, s4
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s0
; GFX10-NEXT: s_mul_i32 s0, s0, s2
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_cmp_lt_i32_e64 vcc_lo, s3, 0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, s[4:5], v[0:1] ; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX10-NEXT: v_cndmask_b32_e64 v1, s1, 0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, s1, 0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, s0, 0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, s0, 0, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[0:1], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
%umulo = tail call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %x, i64 %y) %umulo = tail call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %x, i64 %y)
%mul = extractvalue { i64, i1 } %umulo, 0 %mul = extractvalue { i64, i1 } %umulo, 0
▲ Show 20 Lines • Show All 95 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll

Show All 10 Lines
; SI-NEXT: s_mov_b32 s2, s6 ; SI-NEXT: s_mov_b32 s2, s6
; SI-NEXT: v_mov_b32_e32 v4, 0x3ff00000 ; SI-NEXT: v_mov_b32_e32 v4, 0x3ff00000
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s0, s11, 0xb0014 ; SI-NEXT: s_bfe_u32 s0, s11, 0xb0014
; SI-NEXT: s_add_i32 s5, s0, 0xfffffc01 ; SI-NEXT: s_add_i32 s5, s0, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s5 ; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s5
; SI-NEXT: s_andn2_b64 s[2:3], s[10:11], s[0:1] ; SI-NEXT: s_andn2_b64 s[2:3], s[10:11], s[0:1]
; SI-NEXT: s_and_b32 s0, s11, 0x80000000 ; SI-NEXT: s_and_b32 s0, s11, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s5, 0
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_cmp_gt_i32 s5, 51
; SI-NEXT: v_mov_b32_e32 v1, s0 ; SI-NEXT: v_mov_b32_e32 v1, s0
; SI-NEXT: v_mov_b32_e32 v0, s3 ; SI-NEXT: v_mov_b32_e32 v0, s3
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s5, 0
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s5, 51
; SI-NEXT: v_mov_b32_e32 v1, s11 ; SI-NEXT: v_mov_b32_e32 v1, s11
; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
; SI-NEXT: v_mov_b32_e32 v0, s2 ; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT: v_mov_b32_e32 v2, s10 ; SI-NEXT: v_mov_b32_e32 v2, s10
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; SI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1] ; SI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1]
; SI-NEXT: s_brev_b32 s0, -2 ; SI-NEXT: s_brev_b32 s0, -2
; SI-NEXT: v_mov_b32_e32 v5, s11 ; SI-NEXT: v_mov_b32_e32 v5, s11
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; SI-NEXT: s_mov_b32 s2, s6 ; SI-NEXT: s_mov_b32 s2, s6
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s0, s11, 0xb0014 ; SI-NEXT: s_bfe_u32 s0, s11, 0xb0014
; SI-NEXT: s_add_i32 s14, s0, s7 ; SI-NEXT: s_add_i32 s14, s0, s7
; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s14 ; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s14
; SI-NEXT: s_brev_b32 s15, 1 ; SI-NEXT: s_brev_b32 s15, 1
; SI-NEXT: s_andn2_b64 s[12:13], s[10:11], s[0:1] ; SI-NEXT: s_andn2_b64 s[12:13], s[10:11], s[0:1]
; SI-NEXT: s_and_b32 s0, s11, s15 ; SI-NEXT: s_and_b32 s0, s11, s15
; SI-NEXT: v_mov_b32_e32 v1, s0 ; SI-NEXT: s_cmp_lt_i32 s14, 0
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s13 ; SI-NEXT: v_mov_b32_e32 v0, s13
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s14, 0 ; SI-NEXT: v_mov_b32_e32 v1, s0
; SI-NEXT: s_cmp_gt_i32 s14, 51
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-NEXT: v_mov_b32_e32 v1, s11 ; SI-NEXT: v_mov_b32_e32 v1, s11
; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s14, 51 ; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
; SI-NEXT: v_mov_b32_e32 v0, s12 ; SI-NEXT: v_mov_b32_e32 v0, s12
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT: v_mov_b32_e32 v2, s10 ; SI-NEXT: v_mov_b32_e32 v2, s10
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; SI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1] ; SI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1]
; SI-NEXT: s_bfe_u32 s0, s9, 0xb0014 ; SI-NEXT: s_bfe_u32 s0, s9, 0xb0014
; SI-NEXT: s_add_i32 s7, s0, s7 ; SI-NEXT: s_add_i32 s7, s0, s7
; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s7
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5 ; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
; SI-NEXT: s_brev_b32 s10, -2 ; SI-NEXT: s_brev_b32 s10, -2
; SI-NEXT: v_mov_b32_e32 v6, 0x3ff00000 ; SI-NEXT: v_mov_b32_e32 v6, 0x3ff00000
; SI-NEXT: v_mov_b32_e32 v4, s11 ; SI-NEXT: v_mov_b32_e32 v4, s11
; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s7
; SI-NEXT: v_bfi_b32 v4, s10, v6, v4 ; SI-NEXT: v_bfi_b32 v4, s10, v6, v4
; SI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: s_andn2_b64 s[2:3], s[8:9], s[0:1] ; SI-NEXT: s_andn2_b64 s[2:3], s[8:9], s[0:1]
; SI-NEXT: s_and_b32 s0, s9, s15 ; SI-NEXT: s_and_b32 s0, s9, s15
; SI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: s_cmp_lt_i32 s7, 0
; SI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3] ; SI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_cmp_gt_i32 s7, 51
; SI-NEXT: v_mov_b32_e32 v1, s0 ; SI-NEXT: v_mov_b32_e32 v1, s0
; SI-NEXT: v_mov_b32_e32 v0, s3 ; SI-NEXT: v_mov_b32_e32 v0, s3
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s7, 0
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s7, 51
; SI-NEXT: v_mov_b32_e32 v1, s9 ; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
; SI-NEXT: v_mov_b32_e32 v0, s2 ; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT: v_mov_b32_e32 v4, s8 ; SI-NEXT: v_mov_b32_e32 v4, s8
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
; SI-NEXT: v_add_f64 v[4:5], s[8:9], -v[0:1] ; SI-NEXT: v_add_f64 v[4:5], s[8:9], -v[0:1]
; SI-NEXT: v_mov_b32_e32 v7, s9 ; SI-NEXT: v_mov_b32_e32 v7, s9
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5 ; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s0, s11, 0xb0014 ; SI-NEXT: s_bfe_u32 s0, s11, 0xb0014
; SI-NEXT: s_add_i32 s19, s0, s18 ; SI-NEXT: s_add_i32 s19, s0, s18
; SI-NEXT: s_mov_b32 s2, s6 ; SI-NEXT: s_mov_b32 s2, s6
; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s19 ; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s19
; SI-NEXT: s_brev_b32 s20, 1 ; SI-NEXT: s_brev_b32 s20, 1
; SI-NEXT: s_andn2_b64 s[16:17], s[10:11], s[0:1] ; SI-NEXT: s_andn2_b64 s[16:17], s[10:11], s[0:1]
; SI-NEXT: s_and_b32 s0, s11, s20 ; SI-NEXT: s_and_b32 s0, s11, s20
; SI-NEXT: v_mov_b32_e32 v1, s0 ; SI-NEXT: s_cmp_lt_i32 s19, 0
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s17 ; SI-NEXT: v_mov_b32_e32 v0, s17
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s19, 0 ; SI-NEXT: v_mov_b32_e32 v1, s0
; SI-NEXT: s_cmp_gt_i32 s19, 51
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-NEXT: v_mov_b32_e32 v1, s11 ; SI-NEXT: v_mov_b32_e32 v1, s11
; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s19, 51 ; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
; SI-NEXT: v_mov_b32_e32 v0, s16 ; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT: v_mov_b32_e32 v2, s10 ; SI-NEXT: v_mov_b32_e32 v2, s10
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; SI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1] ; SI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1]
; SI-NEXT: s_bfe_u32 s0, s9, 0xb0014 ; SI-NEXT: s_bfe_u32 s0, s9, 0xb0014
; SI-NEXT: s_add_i32 s17, s0, s18 ; SI-NEXT: s_add_i32 s17, s0, s18
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5 ; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
; SI-NEXT: s_brev_b32 s16, -2 ; SI-NEXT: s_brev_b32 s16, -2
; SI-NEXT: v_mov_b32_e32 v12, 0x3ff00000 ; SI-NEXT: v_mov_b32_e32 v12, 0x3ff00000
; SI-NEXT: v_mov_b32_e32 v4, s11 ; SI-NEXT: v_mov_b32_e32 v4, s11
; SI-NEXT: v_bfi_b32 v4, s16, v12, v4
; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s17 ; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s17
; SI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc ; SI-NEXT: v_bfi_b32 v4, s16, v12, v4
; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: s_andn2_b64 s[10:11], s[8:9], s[0:1] ; SI-NEXT: s_andn2_b64 s[10:11], s[8:9], s[0:1]
; SI-NEXT: s_and_b32 s0, s9, s20 ; SI-NEXT: s_and_b32 s0, s9, s20
; SI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: s_cmp_lt_i32 s17, 0
; SI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3] ; SI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
; SI-NEXT: v_mov_b32_e32 v1, s0 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s11 ; SI-NEXT: v_mov_b32_e32 v0, s11
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s17, 0 ; SI-NEXT: v_mov_b32_e32 v1, s0
; SI-NEXT: s_cmp_gt_i32 s17, 51
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-NEXT: v_mov_b32_e32 v1, s9 ; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s17, 51 ; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
; SI-NEXT: v_mov_b32_e32 v0, s10 ; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT: v_mov_b32_e32 v4, s8 ; SI-NEXT: v_mov_b32_e32 v4, s8
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
; SI-NEXT: v_add_f64 v[4:5], s[8:9], -v[0:1]
; SI-NEXT: s_bfe_u32 s0, s15, 0xb0014 ; SI-NEXT: s_bfe_u32 s0, s15, 0xb0014
; SI-NEXT: s_add_i32 s10, s0, s18 ; SI-NEXT: s_add_i32 s10, s0, s18
; SI-NEXT: v_mov_b32_e32 v6, s9 ; SI-NEXT: v_add_f64 v[4:5], s[8:9], -v[0:1]
; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s10 ; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s10
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5 ; SI-NEXT: v_mov_b32_e32 v6, s9
; SI-NEXT: s_andn2_b64 s[8:9], s[14:15], s[0:1] ; SI-NEXT: s_andn2_b64 s[8:9], s[14:15], s[0:1]
; SI-NEXT: v_bfi_b32 v6, s16, v12, v6 ; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
; SI-NEXT: s_and_b32 s0, s15, s20 ; SI-NEXT: s_and_b32 s0, s15, s20
; SI-NEXT: v_bfi_b32 v6, s16, v12, v6
; SI-NEXT: s_cmp_lt_i32 s10, 0
; SI-NEXT: v_cndmask_b32_e32 v9, 0, v6, vcc ; SI-NEXT: v_cndmask_b32_e32 v9, 0, v6, vcc
; SI-NEXT: v_mov_b32_e32 v5, s0 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v4, s9 ; SI-NEXT: v_mov_b32_e32 v4, s9
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s10, 0 ; SI-NEXT: v_mov_b32_e32 v5, s0
; SI-NEXT: s_cmp_gt_i32 s10, 51
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; SI-NEXT: v_mov_b32_e32 v5, s15 ; SI-NEXT: v_mov_b32_e32 v5, s15
; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s10, 51 ; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[0:1]
; SI-NEXT: v_mov_b32_e32 v4, s8 ; SI-NEXT: v_mov_b32_e32 v4, s8
; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; SI-NEXT: v_mov_b32_e32 v6, s14 ; SI-NEXT: v_mov_b32_e32 v6, s14
; SI-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[0:1]
; SI-NEXT: v_add_f64 v[6:7], s[14:15], -v[4:5] ; SI-NEXT: v_add_f64 v[6:7], s[14:15], -v[4:5]
; SI-NEXT: s_bfe_u32 s0, s13, 0xb0014 ; SI-NEXT: s_bfe_u32 s0, s13, 0xb0014
; SI-NEXT: v_mov_b32_e32 v10, s15
; SI-NEXT: s_add_i32 s8, s0, s18 ; SI-NEXT: s_add_i32 s8, s0, s18
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5 ; SI-NEXT: v_mov_b32_e32 v10, s15
; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s8 ; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s8
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
; SI-NEXT: v_bfi_b32 v10, s16, v12, v10 ; SI-NEXT: v_bfi_b32 v10, s16, v12, v10
; SI-NEXT: v_cndmask_b32_e32 v7, 0, v10, vcc
; SI-NEXT: v_mov_b32_e32 v6, 0
; SI-NEXT: s_andn2_b64 s[2:3], s[12:13], s[0:1] ; SI-NEXT: s_andn2_b64 s[2:3], s[12:13], s[0:1]
; SI-NEXT: s_and_b32 s0, s13, s20 ; SI-NEXT: s_and_b32 s0, s13, s20
; SI-NEXT: v_cndmask_b32_e32 v7, 0, v10, vcc
; SI-NEXT: v_mov_b32_e32 v6, 0
; SI-NEXT: s_cmp_lt_i32 s8, 0
; SI-NEXT: v_add_f64 v[6:7], v[4:5], v[6:7] ; SI-NEXT: v_add_f64 v[6:7], v[4:5], v[6:7]
; SI-NEXT: v_mov_b32_e32 v5, s0 ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v4, s3 ; SI-NEXT: v_mov_b32_e32 v4, s3
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s8, 0 ; SI-NEXT: v_mov_b32_e32 v5, s0
; SI-NEXT: s_cmp_gt_i32 s8, 51
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; SI-NEXT: v_mov_b32_e32 v5, s13 ; SI-NEXT: v_mov_b32_e32 v5, s13
; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s8, 51 ; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[0:1]
; SI-NEXT: v_mov_b32_e32 v4, s2 ; SI-NEXT: v_mov_b32_e32 v4, s2
; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; SI-NEXT: v_mov_b32_e32 v10, s12 ; SI-NEXT: v_mov_b32_e32 v10, s12
; SI-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[0:1]
; SI-NEXT: v_add_f64 v[10:11], s[12:13], -v[4:5] ; SI-NEXT: v_add_f64 v[10:11], s[12:13], -v[4:5]
; SI-NEXT: v_mov_b32_e32 v13, s13 ; SI-NEXT: v_mov_b32_e32 v13, s13
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[10:11]|, 0.5 ; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[10:11]|, 0.5
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines; CI-NEXT: s_endpgm
%result = call <4 x double> @llvm.round.v4f64(<4 x double> %in) #1 %result = call <4 x double> @llvm.round.v4f64(<4 x double> %in) #1
store <4 x double> %result, <4 x double> addrspace(1)* %out store <4 x double> %result, <4 x double> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @round_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %in) #0 { define amdgpu_kernel void @round_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %in) #0 {
; SI-LABEL: round_v8f64: ; SI-LABEL: round_v8f64:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx16 s[8:23], s[0:1], 0x19 ; SI-NEXT: s_load_dwordx16 s[16:31], s[0:1], 0x19
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s14, -1
; SI-NEXT: s_movk_i32 s7, 0xfc01 ; SI-NEXT: s_movk_i32 s15, 0xfc01
; SI-NEXT: s_mov_b32 s5, 0xfffff ; SI-NEXT: s_mov_b32 s13, 0xfffff
; SI-NEXT: s_mov_b32 s4, s6 ; SI-NEXT: s_mov_b32 s12, s14
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s2, s11, 0xb0014 ; SI-NEXT: s_bfe_u32 s2, s19, 0xb0014
; SI-NEXT: s_add_i32 s26, s2, s7 ; SI-NEXT: s_add_i32 s6, s2, s15
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], s26 ; SI-NEXT: s_lshr_b64 s[2:3], s[12:13], s6
; SI-NEXT: s_brev_b32 s27, 1 ; SI-NEXT: s_brev_b32 s33, 1
; SI-NEXT: s_andn2_b64 s[24:25], s[10:11], s[2:3] ; SI-NEXT: s_andn2_b64 s[4:5], s[18:19], s[2:3]
; SI-NEXT: s_and_b32 s2, s11, s27 ; SI-NEXT: s_and_b32 s2, s19, s33
; SI-NEXT: s_cmp_lt_i32 s6, 0
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s5
; SI-NEXT: v_mov_b32_e32 v1, s2 ; SI-NEXT: v_mov_b32_e32 v1, s2
; SI-NEXT: v_mov_b32_e32 v0, s25 ; SI-NEXT: s_cmp_gt_i32 s6, 51
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s26, 0
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-NEXT: v_mov_b32_e32 v1, s11 ; SI-NEXT: v_mov_b32_e32 v1, s19
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s26, 51 ; SI-NEXT: s_cselect_b64 s[2:3], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[2:3] ; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[2:3]
; SI-NEXT: v_mov_b32_e32 v0, s24 ; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT: v_mov_b32_e32 v2, s10 ; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[2:3] ; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[2:3]
; SI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1] ; SI-NEXT: v_add_f64 v[2:3], s[18:19], -v[0:1]
; SI-NEXT: s_bfe_u32 s2, s9, 0xb0014 ; SI-NEXT: s_bfe_u32 s2, s17, 0xb0014
; SI-NEXT: s_add_i32 s25, s2, s7 ; SI-NEXT: s_add_i32 s6, s2, s15
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5 ; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
; SI-NEXT: s_brev_b32 s24, -2 ; SI-NEXT: s_lshr_b64 s[2:3], s[12:13], s6
; SI-NEXT: v_mov_b32_e32 v18, 0x3ff00000 ; SI-NEXT: s_brev_b32 s34, -2
; SI-NEXT: v_mov_b32_e32 v4, s11 ; SI-NEXT: v_mov_b32_e32 v14, 0x3ff00000
; SI-NEXT: v_bfi_b32 v4, s24, v18, v4 ; SI-NEXT: v_mov_b32_e32 v4, s19
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], s25 ; SI-NEXT: v_bfi_b32 v4, s34, v14, v4
; SI-NEXT: s_andn2_b64 s[4:5], s[16:17], s[2:3]
; SI-NEXT: s_and_b32 s2, s17, s33
; SI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc ; SI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
; SI-NEXT: v_mov_b32_e32 v2, 0 ; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: s_andn2_b64 s[10:11], s[8:9], s[2:3] ; SI-NEXT: s_cmp_lt_i32 s6, 0
; SI-NEXT: s_and_b32 s2, s9, s27
; SI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3] ; SI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v0, s5
; SI-NEXT: v_mov_b32_e32 v1, s2 ; SI-NEXT: v_mov_b32_e32 v1, s2
; SI-NEXT: v_mov_b32_e32 v0, s11 ; SI-NEXT: s_cmp_gt_i32 s6, 51
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s25, 0
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-NEXT: v_mov_b32_e32 v1, s9 ; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s25, 51 ; SI-NEXT: s_cselect_b64 s[2:3], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[2:3] ; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[2:3]
; SI-NEXT: v_mov_b32_e32 v0, s10 ; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT: v_mov_b32_e32 v4, s8 ; SI-NEXT: v_mov_b32_e32 v4, s16
; SI-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[2:3] ; SI-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[2:3]
; SI-NEXT: v_add_f64 v[4:5], s[8:9], -v[0:1] ; SI-NEXT: v_add_f64 v[4:5], s[16:17], -v[0:1]
; SI-NEXT: s_bfe_u32 s2, s15, 0xb0014 ; SI-NEXT: s_bfe_u32 s2, s23, 0xb0014
; SI-NEXT: v_mov_b32_e32 v6, s9 ; SI-NEXT: s_add_i32 s6, s2, s15
; SI-NEXT: s_add_i32 s10, s2, s7 ; SI-NEXT: v_mov_b32_e32 v6, s17
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5 ; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
; SI-NEXT: v_bfi_b32 v6, s24, v18, v6 ; SI-NEXT: s_lshr_b64 s[2:3], s[12:13], s6
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], s10 ; SI-NEXT: v_bfi_b32 v6, s34, v14, v6
; SI-NEXT: s_andn2_b64 s[4:5], s[22:23], s[2:3]
; SI-NEXT: s_and_b32 s2, s23, s33
; SI-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc ; SI-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc
; SI-NEXT: v_mov_b32_e32 v4, 0 ; SI-NEXT: v_mov_b32_e32 v4, 0
; SI-NEXT: s_andn2_b64 s[8:9], s[14:15], s[2:3] ; SI-NEXT: s_cmp_lt_i32 s6, 0
; SI-NEXT: s_and_b32 s2, s15, s27
; SI-NEXT: v_add_f64 v[0:1], v[0:1], v[4:5] ; SI-NEXT: v_add_f64 v[0:1], v[0:1], v[4:5]
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v4, s5
; SI-NEXT: v_mov_b32_e32 v5, s2 ; SI-NEXT: v_mov_b32_e32 v5, s2
; SI-NEXT: v_mov_b32_e32 v4, s9 ; SI-NEXT: s_cmp_gt_i32 s6, 51
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s10, 0
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; SI-NEXT: v_mov_b32_e32 v5, s15 ; SI-NEXT: v_mov_b32_e32 v5, s23
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s10, 51 ; SI-NEXT: s_cselect_b64 s[2:3], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[2:3] ; SI-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[2:3]
; SI-NEXT: v_mov_b32_e32 v4, s8 ; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; SI-NEXT: v_mov_b32_e32 v6, s14 ; SI-NEXT: v_mov_b32_e32 v6, s22
; SI-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[2:3] ; SI-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[2:3]
; SI-NEXT: v_add_f64 v[6:7], s[14:15], -v[4:5] ; SI-NEXT: v_add_f64 v[6:7], s[22:23], -v[4:5]
; SI-NEXT: s_bfe_u32 s2, s13, 0xb0014 ; SI-NEXT: s_bfe_u32 s2, s21, 0xb0014
; SI-NEXT: v_mov_b32_e32 v8, s15 ; SI-NEXT: s_add_i32 s6, s2, s15
; SI-NEXT: s_add_i32 s10, s2, s7 ; SI-NEXT: v_mov_b32_e32 v8, s23
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5 ; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
; SI-NEXT: v_bfi_b32 v8, s24, v18, v8 ; SI-NEXT: s_lshr_b64 s[2:3], s[12:13], s6
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], s10 ; SI-NEXT: v_bfi_b32 v8, s34, v14, v8
; SI-NEXT: s_andn2_b64 s[4:5], s[20:21], s[2:3]
; SI-NEXT: s_and_b32 s2, s21, s33
; SI-NEXT: v_cndmask_b32_e32 v7, 0, v8, vcc ; SI-NEXT: v_cndmask_b32_e32 v7, 0, v8, vcc
; SI-NEXT: v_mov_b32_e32 v6, 0 ; SI-NEXT: v_mov_b32_e32 v6, 0
; SI-NEXT: s_andn2_b64 s[8:9], s[12:13], s[2:3] ; SI-NEXT: s_cmp_lt_i32 s6, 0
; SI-NEXT: s_and_b32 s2, s13, s27
; SI-NEXT: v_add_f64 v[6:7], v[4:5], v[6:7] ; SI-NEXT: v_add_f64 v[6:7], v[4:5], v[6:7]
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_mov_b32_e32 v4, s5
; SI-NEXT: v_mov_b32_e32 v5, s2 ; SI-NEXT: v_mov_b32_e32 v5, s2
; SI-NEXT: v_mov_b32_e32 v4, s9 ; SI-NEXT: s_cmp_gt_i32 s6, 51
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s10, 0
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; SI-NEXT: v_mov_b32_e32 v5, s13 ; SI-NEXT: v_mov_b32_e32 v5, s21
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s10, 51 ; SI-NEXT: s_cselect_b64 s[2:3], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[2:3] ; SI-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[2:3]
; SI-NEXT: v_mov_b32_e32 v4, s8 ; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; SI-NEXT: v_mov_b32_e32 v8, s12 ; SI-NEXT: v_mov_b32_e32 v8, s20
; SI-NEXT: v_cndmask_b32_e64 v4, v4, v8, s[2:3] ; SI-NEXT: v_cndmask_b32_e64 v4, v4, v8, s[2:3]
; SI-NEXT: v_add_f64 v[8:9], s[12:13], -v[4:5] ; SI-NEXT: s_bfe_u32 s2, s27, 0xb0014
; SI-NEXT: s_bfe_u32 s2, s19, 0xb0014 ; SI-NEXT: s_add_i32 s4, s2, s15
; SI-NEXT: v_mov_b32_e32 v10, s13 ; SI-NEXT: v_add_f64 v[8:9], s[20:21], -v[4:5]
; SI-NEXT: s_add_i32 s10, s2, s7 ; SI-NEXT: s_lshr_b64 s[2:3], s[12:13], s4
; SI-NEXT: v_mov_b32_e32 v10, s21
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[8:9]|, 0.5 ; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[8:9]|, 0.5
; SI-NEXT: v_bfi_b32 v10, s24, v18, v10 ; SI-NEXT: s_andn2_b64 s[16:17], s[26:27], s[2:3]
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], s10 ; SI-NEXT: s_and_b32 s2, s27, s33
; SI-NEXT: v_bfi_b32 v10, s34, v14, v10
; SI-NEXT: s_cmp_lt_i32 s4, 0
; SI-NEXT: v_cndmask_b32_e32 v9, 0, v10, vcc ; SI-NEXT: v_cndmask_b32_e32 v9, 0, v10, vcc
; SI-NEXT: v_mov_b32_e32 v8, 0 ; SI-NEXT: v_mov_b32_e32 v8, 0
; SI-NEXT: s_andn2_b64 s[8:9], s[18:19], s[2:3] ; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_and_b32 s2, s19, s27 ; SI-NEXT: s_cmp_gt_i32 s4, 51
; SI-NEXT: v_add_f64 v[4:5], v[4:5], v[8:9] ; SI-NEXT: v_add_f64 v[4:5], v[4:5], v[8:9]
; SI-NEXT: v_mov_b32_e32 v9, s2 ; SI-NEXT: v_mov_b32_e32 v9, s2
; SI-NEXT: v_mov_b32_e32 v8, s9 ; SI-NEXT: s_cselect_b64 s[2:3], -1, 0
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s10, 0 ; SI-NEXT: s_bfe_u32 s4, s25, 0xb0014
; SI-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc ; SI-NEXT: s_add_i32 s6, s4, s15
; SI-NEXT: v_mov_b32_e32 v9, s19 ; SI-NEXT: s_lshr_b64 s[4:5], s[12:13], s6
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s10, 51 ; SI-NEXT: s_andn2_b64 s[18:19], s[24:25], s[4:5]
; SI-NEXT: v_cndmask_b32_e64 v13, v8, v9, s[2:3] ; SI-NEXT: s_and_b32 s4, s25, s33
; SI-NEXT: v_mov_b32_e32 v8, s8 ; SI-NEXT: v_mov_b32_e32 v8, s17
; SI-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc ; SI-NEXT: s_cmp_lt_i32 s6, 0
; SI-NEXT: v_mov_b32_e32 v9, s18 ; SI-NEXT: v_cndmask_b32_e32 v15, v8, v9, vcc
; SI-NEXT: v_cndmask_b32_e64 v12, v8, v9, s[2:3] ; SI-NEXT: v_mov_b32_e32 v9, s4
; SI-NEXT: s_bfe_u32 s2, s17, 0xb0014 ; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
; SI-NEXT: s_add_i32 s12, s2, s7 ; SI-NEXT: s_cmp_gt_i32 s6, 51
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], s12 ; SI-NEXT: s_cselect_b64 s[6:7], -1, 0
; SI-NEXT: s_andn2_b64 s[8:9], s[16:17], s[2:3] ; SI-NEXT: s_bfe_u32 s8, s31, 0xb0014
; SI-NEXT: s_bfe_u32 s2, s23, 0xb0014 ; SI-NEXT: s_add_i32 s17, s8, s15
; SI-NEXT: s_add_i32 s14, s2, s7 ; SI-NEXT: s_lshr_b64 s[8:9], s[12:13], s17
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], s14 ; SI-NEXT: s_andn2_b64 s[10:11], s[30:31], s[8:9]
; SI-NEXT: s_and_b32 s8, s31, s33
; SI-NEXT: v_mov_b32_e32 v8, s19 ; SI-NEXT: v_mov_b32_e32 v8, s19
; SI-NEXT: s_andn2_b64 s[10:11], s[22:23], s[2:3] ; SI-NEXT: s_cmp_lt_i32 s17, 0
; SI-NEXT: s_and_b32 s2, s23, s27 ; SI-NEXT: v_cndmask_b32_e64 v17, v8, v9, s[4:5]
; SI-NEXT: v_bfi_b32 v19, s24, v18, v8 ; SI-NEXT: v_mov_b32_e32 v9, s8
; SI-NEXT: v_mov_b32_e32 v9, s2 ; SI-NEXT: s_cselect_b64 s[8:9], -1, 0
; SI-NEXT: v_mov_b32_e32 v8, s11 ; SI-NEXT: v_mov_b32_e32 v8, s11
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s14, 0 ; SI-NEXT: s_cmp_gt_i32 s17, 51
; SI-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc ; SI-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[8:9]
; SI-NEXT: v_mov_b32_e32 v9, s23 ; SI-NEXT: v_mov_b32_e32 v10, s10
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s14, 51 ; SI-NEXT: v_mov_b32_e32 v9, s31
; SI-NEXT: v_cndmask_b32_e64 v9, v8, v9, s[2:3] ; SI-NEXT: s_cselect_b64 s[10:11], -1, 0
; SI-NEXT: v_mov_b32_e32 v8, s10 ; SI-NEXT: v_cndmask_b32_e64 v9, v8, v9, s[10:11]
; SI-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v8, v10, 0, s[8:9]
; SI-NEXT: v_mov_b32_e32 v10, s22 ; SI-NEXT: v_mov_b32_e32 v10, s30
; SI-NEXT: v_cndmask_b32_e64 v8, v8, v10, s[2:3] ; SI-NEXT: s_bfe_u32 s8, s29, 0xb0014
; SI-NEXT: s_bfe_u32 s2, s21, 0xb0014 ; SI-NEXT: v_cndmask_b32_e64 v8, v8, v10, s[10:11]
; SI-NEXT: s_add_i32 s7, s2, s7 ; SI-NEXT: s_add_i32 s10, s8, s15
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], s7 ; SI-NEXT: s_lshr_b64 s[8:9], s[12:13], s10
; SI-NEXT: s_andn2_b64 s[4:5], s[20:21], s[2:3] ; SI-NEXT: s_andn2_b64 s[12:13], s[28:29], s[8:9]
; SI-NEXT: s_and_b32 s2, s21, s27 ; SI-NEXT: s_and_b32 s8, s29, s33
; SI-NEXT: v_mov_b32_e32 v11, s2 ; SI-NEXT: s_cmp_lt_i32 s10, 0
; SI-NEXT: v_mov_b32_e32 v10, s5 ; SI-NEXT: v_mov_b32_e32 v11, s8
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s7, 0 ; SI-NEXT: s_cselect_b64 s[8:9], -1, 0
; SI-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc ; SI-NEXT: v_mov_b32_e32 v10, s13
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s7, 51 ; SI-NEXT: s_cmp_gt_i32 s10, 51
; SI-NEXT: v_mov_b32_e32 v11, s21 ; SI-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[8:9]
; SI-NEXT: v_cndmask_b32_e64 v15, v10, v11, s[2:3] ; SI-NEXT: v_mov_b32_e32 v11, s29
; SI-NEXT: v_mov_b32_e32 v10, s4 ; SI-NEXT: s_cselect_b64 s[10:11], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc ; SI-NEXT: v_cndmask_b32_e64 v13, v10, v11, s[10:11]
; SI-NEXT: v_mov_b32_e32 v11, s20 ; SI-NEXT: v_mov_b32_e32 v10, s12
; SI-NEXT: v_cndmask_b32_e64 v14, v10, v11, s[2:3] ; SI-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[8:9]
; SI-NEXT: v_add_f64 v[10:11], s[20:21], -v[14:15] ; SI-NEXT: v_mov_b32_e32 v11, s28
; SI-NEXT: v_mov_b32_e32 v17, s23 ; SI-NEXT: v_cndmask_b32_e64 v12, v10, v11, s[10:11]
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[10:11]|, 0.5 ; SI-NEXT: v_add_f64 v[10:11], s[28:29], -v[12:13]
; SI-NEXT: v_add_f64 v[10:11], s[22:23], -v[8:9] ; SI-NEXT: v_mov_b32_e32 v19, s29
; SI-NEXT: v_mov_b32_e32 v16, s21 ; SI-NEXT: v_cmp_ge_f64_e64 s[8:9], |v[10:11]|, 0.5
; SI-NEXT: v_cmp_ge_f64_e64 s[2:3], |v[10:11]|, 0.5 ; SI-NEXT: v_mov_b32_e32 v10, s31
; SI-NEXT: v_bfi_b32 v17, s24, v18, v17 ; SI-NEXT: v_bfi_b32 v20, s34, v14, v10
; SI-NEXT: v_cndmask_b32_e64 v11, 0, v17, s[2:3] ; SI-NEXT: v_add_f64 v[10:11], s[30:31], -v[8:9]
; SI-NEXT: v_bfi_b32 v19, s34, v14, v19
; SI-NEXT: v_cmp_ge_f64_e64 s[10:11], |v[10:11]|, 0.5
; SI-NEXT: v_mov_b32_e32 v10, 0 ; SI-NEXT: v_mov_b32_e32 v10, 0
; SI-NEXT: v_bfi_b32 v16, s24, v18, v16 ; SI-NEXT: v_cndmask_b32_e64 v11, 0, v20, s[10:11]
; SI-NEXT: v_add_f64 v[10:11], v[8:9], v[10:11] ; SI-NEXT: v_add_f64 v[10:11], v[8:9], v[10:11]
; SI-NEXT: v_cndmask_b32_e32 v9, 0, v16, vcc ; SI-NEXT: v_cndmask_b32_e64 v9, 0, v19, s[8:9]
; SI-NEXT: v_mov_b32_e32 v8, 0 ; SI-NEXT: v_mov_b32_e32 v8, 0
; SI-NEXT: s_and_b32 s13, s17, s27 ; SI-NEXT: v_add_f64 v[8:9], v[12:13], v[8:9]
; SI-NEXT: v_add_f64 v[8:9], v[14:15], v[8:9] ; SI-NEXT: v_mov_b32_e32 v12, s16
; SI-NEXT: v_mov_b32_e32 v14, s9 ; SI-NEXT: v_mov_b32_e32 v16, s27
; SI-NEXT: v_mov_b32_e32 v15, s13 ; SI-NEXT: v_cndmask_b32_e64 v13, v15, v16, s[2:3]
; SI-NEXT: v_cmp_lt_i32_e64 vcc, s12, 0 ; SI-NEXT: v_cndmask_b32_e64 v12, v12, 0, vcc
; SI-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc ; SI-NEXT: v_mov_b32_e32 v15, s26
; SI-NEXT: v_mov_b32_e32 v15, s17 ; SI-NEXT: v_cndmask_b32_e64 v12, v12, v15, s[2:3]
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s12, 51 ; SI-NEXT: v_mov_b32_e32 v15, s27
; SI-NEXT: v_cndmask_b32_e64 v17, v14, v15, s[2:3] ; SI-NEXT: v_bfi_b32 v19, s34, v14, v15
; SI-NEXT: v_mov_b32_e32 v14, s8 ; SI-NEXT: v_mov_b32_e32 v15, s18
; SI-NEXT: v_cndmask_b32_e64 v14, v14, 0, vcc ; SI-NEXT: v_mov_b32_e32 v18, s25
; SI-NEXT: v_mov_b32_e32 v15, s16 ; SI-NEXT: v_cndmask_b32_e64 v15, v15, 0, s[4:5]
; SI-NEXT: v_cndmask_b32_e64 v16, v14, v15, s[2:3] ; SI-NEXT: v_mov_b32_e32 v16, s24
; SI-NEXT: v_mov_b32_e32 v14, s17 ; SI-NEXT: v_cndmask_b32_e64 v16, v15, v16, s[6:7]
; SI-NEXT: v_bfi_b32 v18, s24, v18, v14 ; SI-NEXT: v_cndmask_b32_e64 v17, v17, v18, s[6:7]
; SI-NEXT: v_add_f64 v[14:15], s[16:17], -v[16:17] ; SI-NEXT: v_mov_b32_e32 v15, s25
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; SI-NEXT: v_bfi_b32 v18, s34, v14, v15
; SI-NEXT: v_add_f64 v[14:15], s[24:25], -v[16:17]
; SI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x9
; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[14:15]|, 0.5 ; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[14:15]|, 0.5
; SI-NEXT: v_add_f64 v[14:15], s[18:19], -v[12:13] ; SI-NEXT: v_add_f64 v[14:15], s[26:27], -v[12:13]
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s15, 0xf000
; SI-NEXT: v_cmp_ge_f64_e64 s[0:1], |v[14:15]|, 0.5 ; SI-NEXT: v_cmp_ge_f64_e64 s[0:1], |v[14:15]|, 0.5
; SI-NEXT: v_mov_b32_e32 v14, 0 ; SI-NEXT: v_mov_b32_e32 v14, 0
; SI-NEXT: v_cndmask_b32_e64 v15, 0, v19, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v15, 0, v19, s[0:1]
; SI-NEXT: v_add_f64 v[14:15], v[12:13], v[14:15] ; SI-NEXT: v_add_f64 v[14:15], v[12:13], v[14:15]
; SI-NEXT: v_cndmask_b32_e32 v13, 0, v18, vcc ; SI-NEXT: v_cndmask_b32_e32 v13, 0, v18, vcc
; SI-NEXT: v_mov_b32_e32 v12, 0 ; SI-NEXT: v_mov_b32_e32 v12, 0
; SI-NEXT: v_add_f64 v[12:13], v[16:17], v[12:13] ; SI-NEXT: v_add_f64 v[12:13], v[16:17], v[12:13]
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:48 ; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[12:15], 0 offset:48
; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[4:7], 0 offset:32 ; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[12:15], 0 offset:32
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16 ; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; CI-LABEL: round_v8f64: ; CI-LABEL: round_v8f64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx16 s[8:23], s[0:1], 0x19 ; CI-NEXT: s_load_dwordx16 s[8:23], s[0:1], 0x19
; CI-NEXT: s_brev_b32 s2, -2 ; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_mov_b32_e32 v16, 0x3ff00000 ; CI-NEXT: v_mov_b32_e32 v16, 0x3ff00000
; CI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; CI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
▲ Show 20 Lines • Show All 86 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/load-select-ptr.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; Combine on select c, (load x), (load y) -> load (select c, x, y) ; Combine on select c, (load x), (load y) -> load (select c, x, y)
; drops MachinePointerInfo, so it can't be relied on for correctness. ; drops MachinePointerInfo, so it can't be relied on for correctness.
; GCN-LABEL: {{^}}select_ptr_crash_i64_flat: ; GCN-LABEL: {{^}}select_ptr_crash_i64_flat:
; GCN: s_load_dwordx2 ; GCN: s_load_dwordx2
; GCN: s_load_dwordx2 ; GCN: s_load_dwordx2
; GCN: s_load_dwordx2 ; GCN: s_load_dwordx2
; GCN: v_cmp_eq_u32 ; GCN: s_cmp_eq_u32
; GCN: v_cndmask_b32 ; GCN: v_cndmask_b32
; GCN: v_cndmask_b32 ; GCN: v_cndmask_b32
; GCN-NOT: load_dword ; GCN-NOT: load_dword
; GCN: flat_load_dwordx2 ; GCN: flat_load_dwordx2
; GCN-NOT: load_dword ; GCN-NOT: load_dword
; GCN: flat_store_dwordx2 ; GCN: flat_store_dwordx2
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llvm/test/CodeGen/AMDGPU/min.ll

Show First 20 Lines • Show All 378 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @s_test_umin_ult_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
%cmp = icmp ult i32 %a, %b %cmp = icmp ult i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b %val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %out, align 4 store i32 %val, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; FUNC-LABEL: @v_test_umin_ult_i32_multi_use ; FUNC-LABEL: @v_test_umin_ult_i32_multi_use
; SI-NOT: v_min ; SI-NOT: v_min
; GCN: v_cmp_lt_u32 ; GCN: s_cmp_lt_u32
; SI-NOT: v_min ; SI-NOT: v_min
; SI: v_cndmask_b32 ; SI: v_cndmask_b32
; SI-NOT: v_min ; SI-NOT: v_min
; GCN: s_endpgm ; GCN: s_endpgm
; EG-NOT: MIN_UINT ; EG-NOT: MIN_UINT
define amdgpu_kernel void @v_test_umin_ult_i32_multi_use(i32 addrspace(1)* %out0, i1 addrspace(1)* %out1, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) #0 { define amdgpu_kernel void @v_test_umin_ult_i32_multi_use(i32 addrspace(1)* %out0, i1 addrspace(1)* %out1, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) #0 {
%a = load i32, i32 addrspace(1)* %aptr, align 4 %a = load i32, i32 addrspace(1)* %aptr, align 4
▲ Show 20 Lines • Show All 254 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir

Show All 13 Linesbody: |
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1 ; GCN: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
; GCN: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[PHI]], 0, 0, implicit $exec ; GCN: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[PHI]], 0, 0, implicit $exec
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec ; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec ; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
; GCN: V_CMP_NE_U64_e32 0, [[REG_SEQUENCE]], implicit-def $vcc, implicit $exec ; GCN: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec ; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc ; GCN: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc ; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; GCN: bb.2: ; GCN: bb.2:
; GCN: S_ENDPGM 0 ; GCN: S_ENDPGM 0
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
%0:sreg_64 = COPY $vgpr0_vgpr1 %0:sreg_64 = COPY $vgpr0_vgpr1
bb.1: bb.1:
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; GCN: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec ; GCN: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
; GCN: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[REG_SEQUENCE]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec ; GCN: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[REG_SEQUENCE]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec ; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec ; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1 ; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
; GCN: V_CMP_NE_U64_e32 0, [[REG_SEQUENCE1]], implicit-def $vcc, implicit $exec ; GCN: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE1]], 0, implicit $exec
; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec ; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec
; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc ; GCN: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc ; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; GCN: bb.2: ; GCN: bb.2:
; GCN: S_ENDPGM 0 ; GCN: S_ENDPGM 0
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
%0:sreg_64 = COPY $vgpr0_vgpr1 %0:sreg_64 = COPY $vgpr0_vgpr1
bb.1: bb.1:
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; GCN: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec ; GCN: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
; GCN: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[REG_SEQUENCE]], undef %4:vgpr_32, 0, 0, implicit $exec ; GCN: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[REG_SEQUENCE]], undef %4:vgpr_32, 0, 0, implicit $exec
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec ; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec ; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1 ; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
; GCN: V_CMP_NE_U64_e32 0, [[REG_SEQUENCE1]], implicit-def $vcc, implicit $exec ; GCN: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE1]], 0, implicit $exec
; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec ; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec
; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc ; GCN: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc ; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; GCN: bb.2: ; GCN: bb.2:
; GCN: S_ENDPGM 0 ; GCN: S_ENDPGM 0
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
%0:sreg_64 = COPY $vgpr0_vgpr1 %0:sreg_64 = COPY $vgpr0_vgpr1
bb.1: bb.1:
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; GCN: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1 ; GCN: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN: GLOBAL_STORE_DWORD [[PHI]], [[DEF]], 0, 0, implicit $exec ; GCN: GLOBAL_STORE_DWORD [[PHI]], [[DEF]], 0, 0, implicit $exec
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec ; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec ; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
; GCN: V_CMP_NE_U64_e32 0, [[REG_SEQUENCE]], implicit-def $vcc, implicit $exec ; GCN: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec ; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc ; GCN: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc ; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; GCN: bb.2: ; GCN: bb.2:
; GCN: S_ENDPGM 0 ; GCN: S_ENDPGM 0
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
%0:sreg_64 = COPY $vgpr0_vgpr1 %0:sreg_64 = COPY $vgpr0_vgpr1
bb.1: bb.1:
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; GCN: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec ; GCN: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
; GCN: [[GLOBAL_LOAD_DWORD_ADDTID_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_ADDTID_SADDR [[REG_SEQUENCE]], 0, 0, implicit $exec ; GCN: [[GLOBAL_LOAD_DWORD_ADDTID_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_ADDTID_SADDR [[REG_SEQUENCE]], 0, 0, implicit $exec
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec ; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec ; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1 ; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
; GCN: V_CMP_NE_U64_e32 0, [[REG_SEQUENCE1]], implicit-def $vcc, implicit $exec ; GCN: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE1]], 0, implicit $exec
; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec ; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec
; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc ; GCN: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc ; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; GCN: bb.2: ; GCN: bb.2:
; GCN: S_ENDPGM 0 ; GCN: S_ENDPGM 0
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
%0:sreg_64 = COPY $vgpr0_vgpr1 %0:sreg_64 = COPY $vgpr0_vgpr1
bb.1: bb.1:
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; GCN: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec ; GCN: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
; GCN: GLOBAL_STORE_DWORD_ADDTID_SADDR [[DEF]], [[REG_SEQUENCE]], 0, 0, implicit $exec ; GCN: GLOBAL_STORE_DWORD_ADDTID_SADDR [[DEF]], [[REG_SEQUENCE]], 0, 0, implicit $exec
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec ; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec ; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1 ; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
; GCN: V_CMP_NE_U64_e32 0, [[REG_SEQUENCE1]], implicit-def $vcc, implicit $exec ; GCN: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE1]], 0, implicit $exec
; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec ; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec
; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc ; GCN: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc ; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; GCN: bb.2: ; GCN: bb.2:
; GCN: S_ENDPGM 0 ; GCN: S_ENDPGM 0
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
%0:sreg_64 = COPY $vgpr0_vgpr1 %0:sreg_64 = COPY $vgpr0_vgpr1
bb.1: bb.1:
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; GCN: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %6, %bb.1 ; GCN: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %6, %bb.1
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GCN: GLOBAL_ATOMIC_ADD [[PHI]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec ; GCN: GLOBAL_ATOMIC_ADD [[PHI]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec ; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec ; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
; GCN: V_CMP_NE_U64_e32 0, [[REG_SEQUENCE]], implicit-def $vcc, implicit $exec ; GCN: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec ; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc ; GCN: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc ; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; GCN: bb.2: ; GCN: bb.2:
; GCN: S_ENDPGM 0 ; GCN: S_ENDPGM 0
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
%0:sreg_64 = COPY $vgpr0_vgpr1 %0:sreg_64 = COPY $vgpr0_vgpr1
bb.1: bb.1:
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; GCN: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1 ; GCN: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GCN: [[GLOBAL_ATOMIC_ADD_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_RTN [[PHI]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec ; GCN: [[GLOBAL_ATOMIC_ADD_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_RTN [[PHI]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec ; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec ; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
; GCN: V_CMP_NE_U64_e32 0, [[REG_SEQUENCE]], implicit-def $vcc, implicit $exec ; GCN: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec ; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc ; GCN: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc ; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; GCN: bb.2: ; GCN: bb.2:
; GCN: S_ENDPGM 0 ; GCN: S_ENDPGM 0
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
%0:sreg_64 = COPY $vgpr0_vgpr1 %0:sreg_64 = COPY $vgpr0_vgpr1
bb.1: bb.1:
Show All 17 Linesbody: |
; GCN: successors: %bb.1(0x80000000) ; GCN: successors: %bb.1(0x80000000)
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: bb.1: ; GCN: bb.1:
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %6, %bb.1 ; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %6, %bb.1
; GCN: [[SCRATCH_LOAD_DWORD:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_DWORD [[PHI]], 0, 0, implicit $exec, implicit $flat_scr ; GCN: [[SCRATCH_LOAD_DWORD:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_DWORD [[PHI]], 0, 0, implicit $exec, implicit $flat_scr
; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[PHI]], 1, implicit $exec ; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[PHI]], 1, implicit $exec
; GCN: V_CMP_NE_U32_e32 0, [[V_AND_B32_e64_]], implicit-def $vcc, implicit $exec ; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[V_AND_B32_e64_]], 0, implicit $exec
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_AND_B32_e64_]], implicit $exec ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_AND_B32_e64_]], implicit $exec
; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc ; GCN: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def $scc
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc ; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; GCN: bb.2: ; GCN: bb.2:
; GCN: S_ENDPGM 0 ; GCN: S_ENDPGM 0
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
%0:sgpr_32 = COPY $vgpr0 %0:sgpr_32 = COPY $vgpr0
bb.1: bb.1:
Show All 17 Linesbody: |
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: bb.1: ; GCN: bb.1:
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %6, %bb.1 ; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %6, %bb.1
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN: SCRATCH_STORE_DWORD [[DEF]], [[PHI]], 0, 0, implicit $exec, implicit $flat_scr ; GCN: SCRATCH_STORE_DWORD [[DEF]], [[PHI]], 0, 0, implicit $exec, implicit $flat_scr
; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[PHI]], 1, implicit $exec ; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[PHI]], 1, implicit $exec
; GCN: V_CMP_NE_U32_e32 0, [[V_AND_B32_e64_]], implicit-def $vcc, implicit $exec ; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[V_AND_B32_e64_]], 0, implicit $exec
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_AND_B32_e64_]], implicit $exec ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_AND_B32_e64_]], implicit $exec
; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc ; GCN: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def $scc
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc ; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; GCN: bb.2: ; GCN: bb.2:
; GCN: S_ENDPGM 0 ; GCN: S_ENDPGM 0
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
%0:sgpr_32 = COPY $vgpr0 %0:sgpr_32 = COPY $vgpr0
bb.1: bb.1:
Show All 10 Lines

llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll

Show All 29 Linesbb4:
%tmp6 = phi i32 [ %tmp5, %bb3 ], [ %tmp4, %bb2 ] %tmp6 = phi i32 [ %tmp5, %bb3 ], [ %tmp4, %bb2 ]
%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i32 %tmp6 %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i32 %tmp6
store i32 0, i32 addrspace(1)* %gep store i32 0, i32 addrspace(1)* %gep
%tmp7 = icmp eq i32 %tmp6, 32 %tmp7 = icmp eq i32 %tmp6, 32
br i1 %tmp7, label %bb1, label %bb2 br i1 %tmp7, label %bb1, label %bb2
} }
; GCN-LABEL: {{^}}negated_cond_dominated_blocks: ; GCN-LABEL: {{^}}negated_cond_dominated_blocks:
; GCN: v_cmp_ne_u32_e64 [[CC1:[^,]+]], ; GCN: s_cmp_lg_u32
; GCN: s_cselect_b64 [[CC1:[^,]+]], -1, 0
; GCN: s_branch [[BB1:BB[0-9]+_[0-9]+]] ; GCN: s_branch [[BB1:BB[0-9]+_[0-9]+]]
; GCN: [[BB0:BB[0-9]+_[0-9]+]] ; GCN: [[BB0:BB[0-9]+_[0-9]+]]
; GCN-NOT: v_cndmask_b32 ; GCN-NOT: v_cndmask_b32
; GCN-NOT: v_cmp ; GCN-NOT: v_cmp
; GCN: [[BB1]]: ; GCN: [[BB1]]:
; GCN: s_mov_b64 [[CC2:[^,]+]], -1 ; GCN: s_mov_b64 [[CC2:[^,]+]], -1
; GCN: s_mov_b64 vcc, [[CC1]] ; GCN: s_mov_b64 vcc, [[CC1]]
; GCN: s_cbranch_vccz [[BB2:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_vccz [[BB2:BB[0-9]+_[0-9]+]]
Show All 36 Lines

llvm/test/CodeGen/AMDGPU/or.ll

Show First 20 Lines • Show All 256 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @or_i1(i32 addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
%bcmp = fcmp oge float %b, 0.000000e+00 %bcmp = fcmp oge float %b, 0.000000e+00
%or = or i1 %acmp, %bcmp %or = or i1 %acmp, %bcmp
%result = zext i1 %or to i32 %result = zext i1 %or to i32
store i32 %result, i32 addrspace(1)* %out store i32 %result, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}s_or_i1: ; FUNC-LABEL: {{^}}s_or_i1:
; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}] ; SI: s_cmp_eq_u32
; SI: s_cselect_b64 [[C1:[^,]+]], -1, 0
; SI: s_cmp_eq_u32
; SI: s_cselect_b64 [[C2:[^,]+]], -1, 0
; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], [[C1]], [[C2]]
define amdgpu_kernel void @s_or_i1(i1 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) { define amdgpu_kernel void @s_or_i1(i1 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
%cmp0 = icmp eq i32 %a, %b %cmp0 = icmp eq i32 %a, %b
%cmp1 = icmp eq i32 %c, %d %cmp1 = icmp eq i32 %c, %d
%or = or i1 %cmp0, %cmp1 %or = or i1 %cmp0, %cmp1
store i1 %or, i1 addrspace(1)* %out store i1 %or, i1 addrspace(1)* %out
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/sad.ll

Show First 20 Lines • Show All 127 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_sad_u32_multi_use_sub_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
%ret = add i32 %ret0, %c %ret = add i32 %ret0, %c
store i32 %ret, i32 addrspace(1)* %out store i32 %ret, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_sad_u32_multi_use_select_pat2: ; GCN-LABEL: {{^}}v_sad_u32_multi_use_select_pat2:
; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} ; GCN-DAG: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
; GCN-DAG: v_cmp_gt_u32_e32 vcc, s{{[0-9]+}}, v{{[0-9]+}} ; GCN-DAG: s_cmp_gt_u32 s{{[0-9]+}}, s{{[0-9]+}}
; GCN-DAG: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} ; GCN-DAG: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
define amdgpu_kernel void @v_sad_u32_multi_use_select_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { define amdgpu_kernel void @v_sad_u32_multi_use_select_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
%icmp0 = icmp ugt i32 %a, %b %icmp0 = icmp ugt i32 %a, %b
%sub0 = sub i32 %a, %b %sub0 = sub i32 %a, %b
%sub1 = sub i32 %b, %a %sub1 = sub i32 %b, %a
%ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1 %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
store volatile i32 %ret0, i32 addrspace(5)*undef store volatile i32 %ret0, i32 addrspace(5)*undef
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_sad_u32_i8_pat2(i8 addrspace(1)* %out) {
%ret = add i8 %ret0, %c %ret = add i8 %ret0, %c
store i8 %ret, i8 addrspace(1)* %out store i8 %ret, i8 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}s_sad_u32_i8_pat2: ; GCN-LABEL: {{^}}s_sad_u32_i8_pat2:
; GCN: s_load_dword ; GCN: s_load_dword
; GCN: s_bfe_u32 ; GCN-DAG: s_bfe_u32
; GCN-DAG: s_sub_i32 ; GCN-DAG: s_sub_i32
; GCN-DAG: s_and_b32 ; GCN-DAG: s_and_b32
; GCN-DAG: s_sub_i32 ; GCN-DAG: s_sub_i32
; GCN-DAG: s_lshr_b32 ; GCN-DAG: s_lshr_b32
; GCN: v_add_i32_e32 ; GCN: v_add_i32_e32
define amdgpu_kernel void @s_sad_u32_i8_pat2(i8 addrspace(1)* %out, i8 zeroext %a, i8 zeroext %b, i8 zeroext %c) { define amdgpu_kernel void @s_sad_u32_i8_pat2(i8 addrspace(1)* %out, i8 zeroext %a, i8 zeroext %b, i8 zeroext %c) {
%icmp0 = icmp ugt i8 %a, %b %icmp0 = icmp ugt i8 %a, %b
%sub0 = sub i8 %a, %b %sub0 = sub i8 %a, %b
%sub1 = sub i8 %b, %a %sub1 = sub i8 %b, %a
%ret0 = select i1 %icmp0, i8 %sub0, i8 %sub1 %ret0 = select i1 %icmp0, i8 %sub0, i8 %sub1
%ret = add i8 %ret0, %c %ret = add i8 %ret0, %c
store i8 %ret, i8 addrspace(1)* %out store i8 %ret, i8 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_sad_u32_mismatched_operands_pat1: ; GCN-LABEL: {{^}}v_sad_u32_mismatched_operands_pat1:
; GCN: v_cmp_le_u32_e32 vcc, s{{[0-9]+}}, v{{[0-9]+}} ; GCN-DAG: s_cmp_le_u32 s{{[0-9]+}}, s{{[0-9]+}}
; GCN: s_max_u32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} ; GCN-DAG: s_max_u32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
; GCN: v_sub_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_sub_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
; GCN: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @v_sad_u32_mismatched_operands_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) { define amdgpu_kernel void @v_sad_u32_mismatched_operands_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
%icmp0 = icmp ugt i32 %a, %b %icmp0 = icmp ugt i32 %a, %b
%t0 = select i1 %icmp0, i32 %a, i32 %b %t0 = select i1 %icmp0, i32 %a, i32 %b
%icmp1 = icmp ule i32 %a, %b %icmp1 = icmp ule i32 %a, %b
%t1 = select i1 %icmp1, i32 %a, i32 %d %t1 = select i1 %icmp1, i32 %a, i32 %d
Show All 24 Lines

llvm/test/CodeGen/AMDGPU/saddo.ll

Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
; SI-LABEL: s_saddo_i32: ; SI-LABEL: s_saddo_i32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: v_cmp_lt_i32_e64 s[10:11], s9, 0 ; SI-NEXT: s_add_i32 s12, s8, s9
; SI-NEXT: s_add_i32 s9, s8, s9 ; SI-NEXT: s_cmp_lt_i32 s9, 0
; SI-NEXT: v_mov_b32_e32 v0, s8 ; SI-NEXT: s_cselect_b64 s[10:11], -1, 0
; SI-NEXT: s_cmp_lt_i32 s12, s8
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: v_cmp_lt_i32_e32 vcc, s9, v0 ; SI-NEXT: v_mov_b32_e32 v0, s12
; SI-NEXT: v_mov_b32_e32 v0, s9 ; SI-NEXT: s_cselect_b64 s[8:9], -1, 0
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_xor_b64 s[0:1], s[10:11], vcc ; SI-NEXT: s_xor_b64 s[0:1], s[10:11], s[8:9]
; SI-NEXT: s_mov_b32 s4, s6 ; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7 ; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s6, s2 ; SI-NEXT: s_mov_b32 s6, s2
; SI-NEXT: s_mov_b32 s7, s3 ; SI-NEXT: s_mov_b32 s7, s3
; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: s_saddo_i32: ; VI-LABEL: s_saddo_i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_cmp_lt_i32_e64 s[2:3], s1, 0 ; VI-NEXT: s_add_i32 s4, s0, s1
; VI-NEXT: s_add_i32 s1, s0, s1 ; VI-NEXT: s_cmp_lt_i32 s1, 0
; VI-NEXT: v_mov_b32_e32 v4, s0 ; VI-NEXT: s_cselect_b64 s[2:3], -1, 0
; VI-NEXT: v_cmp_lt_i32_e32 vcc, s1, v4 ; VI-NEXT: s_cmp_lt_i32 s4, s0
; VI-NEXT: v_mov_b32_e32 v4, s1 ; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: s_xor_b64 s[0:1], s[2:3], vcc ; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1]
; VI-NEXT: flat_store_dword v[0:1], v4 ; VI-NEXT: flat_store_dword v[0:1], v4
; VI-NEXT: v_mov_b32_e32 v2, s6 ; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_mov_b32_e32 v3, s7 ; VI-NEXT: v_mov_b32_e32 v3, s7
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; VI-NEXT: flat_store_byte v[2:3], v0 ; VI-NEXT: flat_store_byte v[2:3], v0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: s_saddo_i32: ; GFX9-LABEL: s_saddo_i32:
▲ Show 20 Lines • Show All 391 Lines • ▼ Show 20 Lines
; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] ; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; VI-NEXT: flat_store_dwordx2 v[4:5], v[8:9] ; VI-NEXT: flat_store_dwordx2 v[4:5], v[8:9]
; VI-NEXT: flat_store_dwordx2 v[6:7], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[6:7], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_saddo_v2i32: ; GFX9-LABEL: v_saddo_v2i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v6, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[4:5] ; GFX9-NEXT: global_load_dwordx2 v[0:1], v6, s[4:5]
; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[6:7] ; GFX9-NEXT: global_load_dwordx2 v[2:3], v6, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_i32 v5, v0, v2 clamp ; GFX9-NEXT: v_add_u32_e32 v5, v1, v3
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_add_i32 v1, v1, v3 clamp
; GFX9-NEXT: v_add_i32 v2, v1, v3 clamp ; GFX9-NEXT: v_add_u32_e32 v4, v0, v2
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v5, v1
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v1, v2 ; GFX9-NEXT: v_add_i32 v0, v0, v2 clamp
; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v0, v5 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v4, v0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[2:3] ; GFX9-NEXT: global_store_dwordx2 v6, v[4:5], s[0:1]
; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: v_saddo_v2i32: ; GFX10-LABEL: v_saddo_v2i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[4:5] ; GFX10-NEXT: global_load_dwordx2 v[0:1], v5, s[4:5]
; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[6:7] ; GFX10-NEXT: global_load_dwordx2 v[2:3], v5, s[6:7]
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_nc_i32 v5, v1, v3 clamp ; GFX10-NEXT: v_add_nc_u32_e32 v4, v1, v3
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3 ; GFX10-NEXT: v_add_nc_i32 v1, v1, v3 clamp
; GFX10-NEXT: v_add_nc_i32 v6, v0, v2 clamp ; GFX10-NEXT: v_add_nc_u32_e32 v3, v0, v2
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 ; GFX10-NEXT: v_add_nc_i32 v0, v0, v2 clamp
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, v1, v5 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, v4, v1
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, v0, v6 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v0
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] ; GFX10-NEXT: global_store_dwordx2 v5, v[3:4], s[0:1]
; GFX10-NEXT: global_store_dwordx2 v4, v[2:3], s[2:3] ; GFX10-NEXT: global_store_dwordx2 v5, v[0:1], s[2:3]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%a = load <2 x i32>, <2 x i32> addrspace(1)* %aptr, align 4 %a = load <2 x i32>, <2 x i32> addrspace(1)* %aptr, align 4
%b = load <2 x i32>, <2 x i32> addrspace(1)* %bptr, align 4 %b = load <2 x i32>, <2 x i32> addrspace(1)* %bptr, align 4
%sadd = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> %a, <2 x i32> %b) nounwind %sadd = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> %a, <2 x i32> %b) nounwind
%val = extractvalue { <2 x i32>, <2 x i1> } %sadd, 0 %val = extractvalue { <2 x i32>, <2 x i1> } %sadd, 0
%carry = extractvalue { <2 x i32>, <2 x i1> } %sadd, 1 %carry = extractvalue { <2 x i32>, <2 x i1> } %sadd, 1
store <2 x i32> %val, <2 x i32> addrspace(1)* %out, align 4 store <2 x i32> %val, <2 x i32> addrspace(1)* %out, align 4
%carry.ext = zext <2 x i1> %carry to <2 x i32> %carry.ext = zext <2 x i1> %carry to <2 x i32>
store <2 x i32> %carry.ext, <2 x i32> addrspace(1)* %carryout store <2 x i32> %carry.ext, <2 x i32> addrspace(1)* %carryout
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/sdiv.ll

Show First 20 Lines • Show All 460 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_xor_b32_e32 v1, v1, v9 ; GCN-NEXT: v_xor_b32_e32 v1, v1, v9
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v8 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
; GCN-NEXT: v_sub_i32_e32 v1, vcc, v1, v9 ; GCN-NEXT: v_sub_i32_e32 v1, vcc, v1, v9
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; TONGA-LABEL: sdiv_v2i32: ; TONGA-LABEL: sdiv_v2i32:
; TONGA: ; %bb.0: ; TONGA: ; %bb.0:
; TONGA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24 ; TONGA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; TONGA-NEXT: s_mov_b32 s7, 0xf000 ; TONGA-NEXT: s_mov_b32 s7, 0xf000
; TONGA-NEXT: s_mov_b32 s6, -1 ; TONGA-NEXT: s_mov_b32 s6, -1
; TONGA-NEXT: s_mov_b32 s2, s6 ; TONGA-NEXT: s_mov_b32 s10, s6
; TONGA-NEXT: s_mov_b32 s3, s7 ; TONGA-NEXT: s_mov_b32 s11, s7
; TONGA-NEXT: s_waitcnt lgkmcnt(0) ; TONGA-NEXT: s_waitcnt lgkmcnt(0)
; TONGA-NEXT: s_mov_b32 s0, s10 ; TONGA-NEXT: s_mov_b32 s8, s2
; TONGA-NEXT: s_mov_b32 s1, s11 ; TONGA-NEXT: s_mov_b32 s9, s3
; TONGA-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 ; TONGA-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
; TONGA-NEXT: s_mov_b32 s2, 0x4f7ffffe ; TONGA-NEXT: s_mov_b32 s2, 0x4f7ffffe
; TONGA-NEXT: s_mov_b32 s4, s8 ; TONGA-NEXT: s_mov_b32 s4, s0
; TONGA-NEXT: s_mov_b32 s5, s9 ; TONGA-NEXT: s_mov_b32 s5, s1
; TONGA-NEXT: s_waitcnt vmcnt(0) ; TONGA-NEXT: s_waitcnt vmcnt(0)
; TONGA-NEXT: v_ashrrev_i32_e32 v4, 31, v2 ; TONGA-NEXT: v_ashrrev_i32_e32 v5, 31, v2
; TONGA-NEXT: v_add_u32_e32 v2, vcc, v4, v2 ; TONGA-NEXT: v_ashrrev_i32_e32 v7, 31, v3
; TONGA-NEXT: v_xor_b32_e32 v2, v2, v4 ; TONGA-NEXT: v_add_u32_e32 v2, vcc, v5, v2
; TONGA-NEXT: v_add_u32_e32 v3, vcc, v7, v3
; TONGA-NEXT: v_ashrrev_i32_e32 v4, 31, v0
; TONGA-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; TONGA-NEXT: v_xor_b32_e32 v2, v2, v5
; TONGA-NEXT: v_xor_b32_e32 v3, v3, v7
; TONGA-NEXT: v_xor_b32_e32 v8, v4, v5
; TONGA-NEXT: v_cvt_f32_u32_e32 v5, v2 ; TONGA-NEXT: v_cvt_f32_u32_e32 v5, v2
; TONGA-NEXT: v_sub_u32_e32 v6, vcc, 0, v2 ; TONGA-NEXT: v_xor_b32_e32 v9, v6, v7
; TONGA-NEXT: v_ashrrev_i32_e32 v7, 31, v0 ; TONGA-NEXT: v_cvt_f32_u32_e32 v7, v3
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v7, v0 ; TONGA-NEXT: v_sub_u32_e32 v10, vcc, 0, v2
; TONGA-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; TONGA-NEXT: v_rcp_iflag_f32_e32 v5, v5
; TONGA-NEXT: v_xor_b32_e32 v0, v0, v7 ; TONGA-NEXT: v_sub_u32_e32 v11, vcc, 0, v3
; TONGA-NEXT: v_xor_b32_e32 v4, v7, v4 ; TONGA-NEXT: v_rcp_iflag_f32_e32 v7, v7
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v4, v0
; TONGA-NEXT: v_mul_f32_e32 v5, s2, v5 ; TONGA-NEXT: v_mul_f32_e32 v5, s2, v5
; TONGA-NEXT: v_cvt_u32_f32_e32 v5, v5 ; TONGA-NEXT: v_cvt_u32_f32_e32 v5, v5
; TONGA-NEXT: v_mul_lo_u32 v6, v6, v5 ; TONGA-NEXT: v_mul_f32_e32 v7, s2, v7
; TONGA-NEXT: v_mul_hi_u32 v6, v5, v6 ; TONGA-NEXT: v_cvt_u32_f32_e32 v7, v7
; TONGA-NEXT: v_add_u32_e32 v5, vcc, v6, v5 ; TONGA-NEXT: v_add_u32_e32 v1, vcc, v6, v1
; TONGA-NEXT: v_mul_hi_u32 v5, v0, v5 ; TONGA-NEXT: v_mul_lo_u32 v10, v10, v5
; TONGA-NEXT: v_ashrrev_i32_e32 v6, 31, v3 ; TONGA-NEXT: v_xor_b32_e32 v0, v0, v4
; TONGA-NEXT: v_mul_lo_u32 v8, v5, v2 ; TONGA-NEXT: v_mul_lo_u32 v11, v11, v7
; TONGA-NEXT: v_add_u32_e32 v9, vcc, 1, v5 ; TONGA-NEXT: v_xor_b32_e32 v1, v1, v6
; TONGA-NEXT: v_subrev_u32_e32 v0, vcc, v8, v0 ; TONGA-NEXT: v_mul_hi_u32 v4, v5, v10
; TONGA-NEXT: v_mul_hi_u32 v6, v7, v11
; TONGA-NEXT: v_add_u32_e32 v4, vcc, v4, v5
; TONGA-NEXT: v_mul_hi_u32 v4, v0, v4
; TONGA-NEXT: v_add_u32_e32 v5, vcc, v6, v7
; TONGA-NEXT: v_mul_hi_u32 v5, v1, v5
; TONGA-NEXT: v_mul_lo_u32 v6, v4, v2
; TONGA-NEXT: v_add_u32_e32 v7, vcc, 1, v4
; TONGA-NEXT: v_mul_lo_u32 v10, v5, v3
; TONGA-NEXT: v_add_u32_e32 v11, vcc, 1, v5
; TONGA-NEXT: v_subrev_u32_e32 v0, vcc, v6, v0
; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2 ; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2
; TONGA-NEXT: v_subrev_u32_e32 v8, vcc, v2, v0 ; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, v10, v1
; TONGA-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[0:1] ; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3
; TONGA-NEXT: v_cndmask_b32_e64 v0, v0, v8, s[0:1] ; TONGA-NEXT: v_subrev_u32_e32 v6, vcc, v2, v0
; TONGA-NEXT: v_add_u32_e32 v8, vcc, 1, v5 ; TONGA-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1]
; TONGA-NEXT: v_subrev_u32_e32 v7, vcc, v3, v1
; TONGA-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[2:3]
; TONGA-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1]
; TONGA-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3]
; TONGA-NEXT: v_add_u32_e32 v6, vcc, 1, v4
; TONGA-NEXT: v_add_u32_e32 v7, vcc, 1, v5
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; TONGA-NEXT: s_mov_b64 s[0:1], vcc ; TONGA-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v6, v3 ; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
; TONGA-NEXT: v_xor_b32_e32 v2, v0, v6 ; TONGA-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc
; TONGA-NEXT: v_cvt_f32_u32_e32 v0, v2 ; TONGA-NEXT: v_xor_b32_e32 v0, v0, v8
; TONGA-NEXT: v_sub_u32_e32 v9, vcc, 0, v2 ; TONGA-NEXT: v_xor_b32_e32 v1, v1, v9
; TONGA-NEXT: v_ashrrev_i32_e32 v3, 31, v1 ; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v0, v8
; TONGA-NEXT: v_add_u32_e32 v1, vcc, v3, v1 ; TONGA-NEXT: v_sub_u32_e32 v1, vcc, v1, v9
; TONGA-NEXT: v_rcp_iflag_f32_e32 v0, v0
; TONGA-NEXT: v_xor_b32_e32 v1, v1, v3
; TONGA-NEXT: v_xor_b32_e32 v6, v3, v6
; TONGA-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[0:1]
; TONGA-NEXT: v_mul_f32_e32 v0, s2, v0
; TONGA-NEXT: v_cvt_u32_f32_e32 v0, v0
; TONGA-NEXT: v_mul_lo_u32 v9, v9, v0
; TONGA-NEXT: v_mul_hi_u32 v7, v0, v9
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v7, v0
; TONGA-NEXT: v_mul_hi_u32 v3, v1, v0
; TONGA-NEXT: v_xor_b32_e32 v0, v5, v4
; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v0, v4
; TONGA-NEXT: v_mul_lo_u32 v4, v3, v2
; TONGA-NEXT: v_add_u32_e32 v5, vcc, 1, v3
; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, v4, v1
; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v1, v2
; TONGA-NEXT: v_subrev_u32_e32 v4, vcc, v2, v1
; TONGA-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
; TONGA-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
; TONGA-NEXT: v_add_u32_e32 v4, vcc, 1, v3
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
; TONGA-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; TONGA-NEXT: v_xor_b32_e32 v1, v1, v6
; TONGA-NEXT: v_sub_u32_e32 v1, vcc, v1, v6
; TONGA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; TONGA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; TONGA-NEXT: s_endpgm ; TONGA-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdiv_v2i32: ; GFX9-LABEL: sdiv_v2i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
▲ Show 20 Lines • Show All 379 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc ; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; GCN-NEXT: v_xor_b32_e32 v3, v3, v6 ; GCN-NEXT: v_xor_b32_e32 v3, v3, v6
; GCN-NEXT: v_sub_i32_e32 v3, vcc, v3, v6 ; GCN-NEXT: v_sub_i32_e32 v3, vcc, v3, v6
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; TONGA-LABEL: sdiv_v4i32: ; TONGA-LABEL: sdiv_v4i32:
; TONGA: ; %bb.0: ; TONGA: ; %bb.0:
; TONGA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24 ; TONGA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; TONGA-NEXT: s_mov_b32 s7, 0xf000 ; TONGA-NEXT: s_mov_b32 s11, 0xf000
; TONGA-NEXT: s_mov_b32 s6, -1 ; TONGA-NEXT: s_mov_b32 s10, -1
; TONGA-NEXT: s_mov_b32 s2, s6 ; TONGA-NEXT: s_mov_b32 s6, s10
; TONGA-NEXT: s_mov_b32 s3, s7 ; TONGA-NEXT: s_mov_b32 s7, s11
; TONGA-NEXT: s_waitcnt lgkmcnt(0) ; TONGA-NEXT: s_waitcnt lgkmcnt(0)
; TONGA-NEXT: s_mov_b32 s0, s10 ; TONGA-NEXT: s_mov_b32 s4, s2
; TONGA-NEXT: s_mov_b32 s1, s11 ; TONGA-NEXT: s_mov_b32 s5, s3
; TONGA-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:16 ; TONGA-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
; TONGA-NEXT: s_mov_b32 s10, 0x4f7ffffe ; TONGA-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
; TONGA-NEXT: s_mov_b32 s4, s8 ; TONGA-NEXT: s_mov_b32 s2, 0x4f7ffffe
; TONGA-NEXT: s_mov_b32 s5, s9 ; TONGA-NEXT: s_mov_b32 s8, s0
; TONGA-NEXT: s_waitcnt vmcnt(0) ; TONGA-NEXT: s_mov_b32 s9, s1
; TONGA-NEXT: s_waitcnt vmcnt(1)
; TONGA-NEXT: v_ashrrev_i32_e32 v8, 31, v0 ; TONGA-NEXT: v_ashrrev_i32_e32 v8, 31, v0
; TONGA-NEXT: s_waitcnt vmcnt(0)
; TONGA-NEXT: v_ashrrev_i32_e32 v11, 31, v5
; TONGA-NEXT: v_ashrrev_i32_e32 v9, 31, v4
; TONGA-NEXT: v_add_u32_e32 v5, vcc, v11, v5
; TONGA-NEXT: v_add_u32_e32 v4, vcc, v9, v4
; TONGA-NEXT: v_xor_b32_e32 v5, v5, v11
; TONGA-NEXT: v_xor_b32_e32 v15, v8, v9
; TONGA-NEXT: v_xor_b32_e32 v4, v4, v9
; TONGA-NEXT: v_cvt_f32_u32_e32 v9, v5
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v8, v0 ; TONGA-NEXT: v_add_u32_e32 v0, vcc, v8, v0
; TONGA-NEXT: v_xor_b32_e32 v0, v0, v8 ; TONGA-NEXT: v_xor_b32_e32 v0, v0, v8
; TONGA-NEXT: v_cvt_f32_u32_e32 v4, v0 ; TONGA-NEXT: v_cvt_f32_u32_e32 v8, v4
; TONGA-NEXT: v_ashrrev_i32_e32 v14, 31, v2 ; TONGA-NEXT: v_rcp_iflag_f32_e32 v9, v9
; TONGA-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; TONGA-NEXT: v_ashrrev_i32_e32 v13, 31, v6
; TONGA-NEXT: v_mul_f32_e32 v4, s10, v4 ; TONGA-NEXT: v_add_u32_e32 v6, vcc, v13, v6
; TONGA-NEXT: v_cvt_u32_f32_e32 v9, v4
; TONGA-NEXT: v_sub_u32_e32 v4, vcc, 0, v0
; TONGA-NEXT: v_mul_lo_u32 v10, v4, v9
; TONGA-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0
; TONGA-NEXT: v_mul_hi_u32 v10, v9, v10
; TONGA-NEXT: v_add_u32_e32 v9, vcc, v10, v9
; TONGA-NEXT: v_ashrrev_i32_e32 v10, 31, v1 ; TONGA-NEXT: v_ashrrev_i32_e32 v10, 31, v1
; TONGA-NEXT: s_waitcnt vmcnt(0) ; TONGA-NEXT: v_rcp_iflag_f32_e32 v8, v8
; TONGA-NEXT: v_ashrrev_i32_e32 v11, 31, v4 ; TONGA-NEXT: v_mul_f32_e32 v9, s2, v9
; TONGA-NEXT: v_add_u32_e32 v4, vcc, v11, v4 ; TONGA-NEXT: v_xor_b32_e32 v6, v6, v13
; TONGA-NEXT: v_xor_b32_e32 v4, v4, v11 ; TONGA-NEXT: v_xor_b32_e32 v16, v10, v11
; TONGA-NEXT: v_mul_hi_u32 v9, v4, v9 ; TONGA-NEXT: v_cvt_f32_u32_e32 v11, v6
; TONGA-NEXT: v_xor_b32_e32 v8, v11, v8 ; TONGA-NEXT: v_cvt_u32_f32_e32 v9, v9
; TONGA-NEXT: v_mul_lo_u32 v12, v9, v0 ; TONGA-NEXT: v_ashrrev_i32_e32 v12, 31, v2
; TONGA-NEXT: v_add_u32_e32 v13, vcc, 1, v9 ; TONGA-NEXT: v_add_u32_e32 v2, vcc, v12, v2
; TONGA-NEXT: v_sub_u32_e32 v4, vcc, v4, v12 ; TONGA-NEXT: v_mul_f32_e32 v8, s2, v8
; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v4, v0 ; TONGA-NEXT: v_xor_b32_e32 v17, v12, v13
; TONGA-NEXT: v_sub_u32_e32 v12, vcc, v4, v0 ; TONGA-NEXT: v_xor_b32_e32 v2, v2, v12
; TONGA-NEXT: v_cndmask_b32_e64 v9, v9, v13, s[0:1] ; TONGA-NEXT: v_sub_u32_e32 v12, vcc, 0, v5
; TONGA-NEXT: v_cndmask_b32_e64 v4, v4, v12, s[0:1] ; TONGA-NEXT: v_rcp_iflag_f32_e32 v11, v11
; TONGA-NEXT: v_add_u32_e32 v12, vcc, 1, v9 ; TONGA-NEXT: v_mul_lo_u32 v12, v12, v9
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v4, v0 ; TONGA-NEXT: v_cvt_u32_f32_e32 v8, v8
; TONGA-NEXT: s_mov_b64 s[0:1], vcc ; TONGA-NEXT: v_add_u32_e32 v1, vcc, v10, v1
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v10, v1 ; TONGA-NEXT: v_xor_b32_e32 v1, v1, v10
; TONGA-NEXT: v_xor_b32_e32 v1, v0, v10 ; TONGA-NEXT: v_sub_u32_e32 v10, vcc, 0, v4
; TONGA-NEXT: v_cvt_f32_u32_e32 v0, v1 ; TONGA-NEXT: v_mul_lo_u32 v10, v10, v8
; TONGA-NEXT: v_sub_u32_e32 v13, vcc, 0, v1 ; TONGA-NEXT: v_mul_hi_u32 v12, v9, v12
; TONGA-NEXT: v_ashrrev_i32_e32 v4, 31, v5 ; TONGA-NEXT: v_mul_f32_e32 v11, s2, v11
; TONGA-NEXT: v_add_u32_e32 v5, vcc, v4, v5 ; TONGA-NEXT: v_cvt_u32_f32_e32 v11, v11
; TONGA-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; TONGA-NEXT: v_mul_hi_u32 v10, v8, v10
; TONGA-NEXT: v_xor_b32_e32 v5, v5, v4 ; TONGA-NEXT: v_add_u32_e32 v9, vcc, v12, v9
; TONGA-NEXT: v_cndmask_b32_e64 v9, v9, v12, s[0:1] ; TONGA-NEXT: v_sub_u32_e32 v12, vcc, 0, v6
; TONGA-NEXT: v_xor_b32_e32 v4, v4, v10 ; TONGA-NEXT: v_mul_lo_u32 v12, v12, v11
; TONGA-NEXT: v_mul_f32_e32 v0, s10, v0 ; TONGA-NEXT: v_add_u32_e32 v8, vcc, v10, v8
; TONGA-NEXT: v_cvt_u32_f32_e32 v0, v0 ; TONGA-NEXT: v_mul_hi_u32 v8, v0, v8
; TONGA-NEXT: v_ashrrev_i32_e32 v10, 31, v6 ; TONGA-NEXT: v_ashrrev_i32_e32 v14, 31, v7
; TONGA-NEXT: v_mul_lo_u32 v13, v13, v0 ; TONGA-NEXT: v_mul_hi_u32 v12, v11, v12
; TONGA-NEXT: v_mul_hi_u32 v11, v0, v13 ; TONGA-NEXT: v_add_u32_e32 v7, vcc, v14, v7
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v11, v0 ; TONGA-NEXT: v_xor_b32_e32 v7, v7, v14
; TONGA-NEXT: v_mul_hi_u32 v11, v5, v0 ; TONGA-NEXT: v_cvt_f32_u32_e32 v10, v7
; TONGA-NEXT: v_xor_b32_e32 v0, v9, v8 ; TONGA-NEXT: v_add_u32_e32 v11, vcc, v12, v11
; TONGA-NEXT: v_subrev_u32_e32 v0, vcc, v8, v0 ; TONGA-NEXT: v_mul_lo_u32 v12, v8, v4
; TONGA-NEXT: v_mul_lo_u32 v8, v11, v1 ; TONGA-NEXT: v_mul_hi_u32 v9, v1, v9
; TONGA-NEXT: v_add_u32_e32 v9, vcc, 1, v11 ; TONGA-NEXT: v_rcp_iflag_f32_e32 v10, v10
; TONGA-NEXT: v_sub_u32_e32 v5, vcc, v5, v8 ; TONGA-NEXT: v_mul_hi_u32 v11, v2, v11
; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v5, v1 ; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v0, v12
; TONGA-NEXT: v_cndmask_b32_e64 v8, v11, v9, s[0:1] ; TONGA-NEXT: v_add_u32_e32 v12, vcc, 1, v8
; TONGA-NEXT: v_sub_u32_e32 v9, vcc, v5, v1 ; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v4
; TONGA-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[0:1] ; TONGA-NEXT: v_cndmask_b32_e64 v8, v8, v12, s[0:1]
; TONGA-NEXT: v_add_u32_e32 v9, vcc, 1, v8 ; TONGA-NEXT: v_sub_u32_e32 v12, vcc, v0, v4
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1 ; TONGA-NEXT: v_cndmask_b32_e64 v0, v0, v12, s[0:1]
; TONGA-NEXT: s_mov_b64 s[0:1], vcc ; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v4
; TONGA-NEXT: v_add_u32_e32 v1, vcc, v14, v2 ; TONGA-NEXT: v_mul_lo_u32 v0, v9, v5
; TONGA-NEXT: v_xor_b32_e32 v2, v1, v14 ; TONGA-NEXT: v_mul_f32_e32 v10, s2, v10
; TONGA-NEXT: v_cvt_f32_u32_e32 v1, v2 ; TONGA-NEXT: v_cvt_u32_f32_e32 v4, v10
; TONGA-NEXT: v_sub_u32_e32 v5, vcc, 0, v2 ; TONGA-NEXT: v_mul_lo_u32 v10, v11, v6
; TONGA-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[0:1] ; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v1, v0
; TONGA-NEXT: v_add_u32_e32 v1, vcc, 1, v9
; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v0, v5
; TONGA-NEXT: v_sub_u32_e32 v2, vcc, v2, v10
; TONGA-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[2:3]
; TONGA-NEXT: v_sub_u32_e32 v9, vcc, v0, v5
; TONGA-NEXT: v_add_u32_e32 v10, vcc, 1, v11
; TONGA-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v6
; TONGA-NEXT: v_add_u32_e32 v12, vcc, 1, v8
; TONGA-NEXT: v_cndmask_b32_e64 v10, v11, v10, s[4:5]
; TONGA-NEXT: v_sub_u32_e32 v11, vcc, v2, v6
; TONGA-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[2:3]
; TONGA-NEXT: v_add_u32_e32 v9, vcc, 1, v1
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5
; TONGA-NEXT: v_cndmask_b32_e32 v0, v1, v9, vcc
; TONGA-NEXT: v_cndmask_b32_e64 v8, v8, v12, s[0:1]
; TONGA-NEXT: v_xor_b32_e32 v1, v8, v15
; TONGA-NEXT: v_xor_b32_e32 v5, v0, v16
; TONGA-NEXT: v_subrev_u32_e32 v0, vcc, v15, v1
; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, v16, v5
; TONGA-NEXT: v_sub_u32_e32 v5, vcc, 0, v7
; TONGA-NEXT: v_mul_lo_u32 v5, v5, v4
; TONGA-NEXT: v_ashrrev_i32_e32 v9, 31, v3 ; TONGA-NEXT: v_ashrrev_i32_e32 v9, 31, v3
; TONGA-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; TONGA-NEXT: v_add_u32_e32 v3, vcc, v9, v3
; TONGA-NEXT: v_mul_f32_e32 v1, s10, v1
; TONGA-NEXT: v_cvt_u32_f32_e32 v1, v1
; TONGA-NEXT: v_mul_lo_u32 v5, v5, v1
; TONGA-NEXT: v_mul_hi_u32 v5, v1, v5
; TONGA-NEXT: v_add_u32_e32 v1, vcc, v5, v1
; TONGA-NEXT: v_add_u32_e32 v5, vcc, v10, v6
; TONGA-NEXT: v_xor_b32_e32 v5, v5, v10
; TONGA-NEXT: v_mul_hi_u32 v6, v5, v1
; TONGA-NEXT: v_xor_b32_e32 v1, v8, v4
; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, v4, v1
; TONGA-NEXT: v_xor_b32_e32 v10, v10, v14
; TONGA-NEXT: v_mul_lo_u32 v4, v6, v2
; TONGA-NEXT: v_add_u32_e32 v8, vcc, 1, v6
; TONGA-NEXT: v_sub_u32_e32 v4, vcc, v5, v4
; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v4, v2
; TONGA-NEXT: v_cndmask_b32_e64 v5, v6, v8, s[0:1]
; TONGA-NEXT: v_sub_u32_e32 v6, vcc, v4, v2
; TONGA-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[0:1]
; TONGA-NEXT: v_add_u32_e32 v6, vcc, 1, v5
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2
; TONGA-NEXT: s_mov_b64 s[0:1], vcc
; TONGA-NEXT: v_add_u32_e32 v2, vcc, v9, v3
; TONGA-NEXT: v_xor_b32_e32 v3, v2, v9
; TONGA-NEXT: v_cvt_f32_u32_e32 v2, v3
; TONGA-NEXT: v_sub_u32_e32 v8, vcc, 0, v3
; TONGA-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[0:1]
; TONGA-NEXT: v_ashrrev_i32_e32 v4, 31, v7
; TONGA-NEXT: v_rcp_iflag_f32_e32 v2, v2
; TONGA-NEXT: v_add_u32_e32 v7, vcc, v4, v7
; TONGA-NEXT: v_xor_b32_e32 v9, v4, v9
; TONGA-NEXT: v_xor_b32_e32 v4, v7, v4
; TONGA-NEXT: v_mul_f32_e32 v2, s10, v2
; TONGA-NEXT: v_cvt_u32_f32_e32 v2, v2
; TONGA-NEXT: v_mul_lo_u32 v8, v8, v2
; TONGA-NEXT: v_mul_hi_u32 v6, v2, v8
; TONGA-NEXT: v_add_u32_e32 v2, vcc, v6, v2
; TONGA-NEXT: v_mul_hi_u32 v6, v4, v2
; TONGA-NEXT: v_xor_b32_e32 v2, v5, v10
; TONGA-NEXT: v_subrev_u32_e32 v2, vcc, v10, v2
; TONGA-NEXT: v_mul_lo_u32 v5, v6, v3
; TONGA-NEXT: v_add_u32_e32 v7, vcc, 1, v6
; TONGA-NEXT: v_sub_u32_e32 v4, vcc, v4, v5
; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v4, v3
; TONGA-NEXT: v_cndmask_b32_e64 v5, v6, v7, s[0:1]
; TONGA-NEXT: v_sub_u32_e32 v6, vcc, v4, v3
; TONGA-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[0:1]
; TONGA-NEXT: v_add_u32_e32 v6, vcc, 1, v5
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v4, v3
; TONGA-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
; TONGA-NEXT: v_xor_b32_e32 v3, v3, v9 ; TONGA-NEXT: v_xor_b32_e32 v3, v3, v9
; TONGA-NEXT: v_subrev_u32_e32 v3, vcc, v9, v3 ; TONGA-NEXT: v_mul_hi_u32 v5, v4, v5
; TONGA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; TONGA-NEXT: v_cndmask_b32_e64 v2, v2, v11, s[4:5]
; TONGA-NEXT: v_add_u32_e32 v8, vcc, 1, v10
; TONGA-NEXT: v_add_u32_e32 v4, vcc, v5, v4
; TONGA-NEXT: v_mul_hi_u32 v4, v3, v4
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6
; TONGA-NEXT: v_cndmask_b32_e32 v2, v10, v8, vcc
; TONGA-NEXT: v_xor_b32_e32 v2, v2, v17
; TONGA-NEXT: v_mul_lo_u32 v5, v4, v7
; TONGA-NEXT: v_subrev_u32_e32 v2, vcc, v17, v2
; TONGA-NEXT: v_xor_b32_e32 v6, v9, v14
; TONGA-NEXT: v_sub_u32_e32 v3, vcc, v3, v5
; TONGA-NEXT: v_add_u32_e32 v5, vcc, 1, v4
; TONGA-NEXT: v_cmp_ge_u32_e64 s[0:1], v3, v7
; TONGA-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]
; TONGA-NEXT: v_sub_u32_e32 v5, vcc, v3, v7
; TONGA-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
; TONGA-NEXT: v_add_u32_e32 v5, vcc, 1, v4
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v3, v7
; TONGA-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; TONGA-NEXT: v_xor_b32_e32 v3, v3, v6
; TONGA-NEXT: v_subrev_u32_e32 v3, vcc, v6, v3
; TONGA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; TONGA-NEXT: s_endpgm ; TONGA-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdiv_v4i32: ; GFX9-LABEL: sdiv_v4i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s11, 0xf000 ; GFX9-NEXT: s_mov_b32 s11, 0xf000
; GFX9-NEXT: s_mov_b32 s10, -1 ; GFX9-NEXT: s_mov_b32 s10, -1
; GFX9-NEXT: s_mov_b32 s6, s10 ; GFX9-NEXT: s_mov_b32 s6, s10
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; TONGA-NEXT: v_cvt_f32_i32_e32 v2, v1 ; TONGA-NEXT: v_cvt_f32_i32_e32 v2, v1
; TONGA-NEXT: v_xor_b32_e32 v0, v0, v1 ; TONGA-NEXT: v_xor_b32_e32 v0, v0, v1
; TONGA-NEXT: v_ashrrev_i32_e32 v0, 30, v0 ; TONGA-NEXT: v_ashrrev_i32_e32 v0, 30, v0
; TONGA-NEXT: v_or_b32_e32 v0, 1, v0 ; TONGA-NEXT: v_or_b32_e32 v0, 1, v0
; TONGA-NEXT: v_rcp_iflag_f32_e32 v4, v2 ; TONGA-NEXT: v_rcp_iflag_f32_e32 v4, v2
; TONGA-NEXT: v_mul_f32_e32 v1, v3, v4 ; TONGA-NEXT: v_mul_f32_e32 v1, v3, v4
; TONGA-NEXT: v_trunc_f32_e32 v1, v1 ; TONGA-NEXT: v_trunc_f32_e32 v1, v1
; TONGA-NEXT: v_mad_f32 v3, -v1, v2, v3 ; TONGA-NEXT: v_mad_f32 v3, -v1, v2, v3
; TONGA-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, |v2|
; TONGA-NEXT: v_cvt_i32_f32_e32 v1, v1 ; TONGA-NEXT: v_cvt_i32_f32_e32 v1, v1
; TONGA-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2| ; TONGA-NEXT: s_cmp_lg_u64 s[4:5], 0
; TONGA-NEXT: s_cselect_b64 vcc, -1, 0
; TONGA-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc ; TONGA-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v1, v0 ; TONGA-NEXT: v_add_u32_e32 v0, vcc, v1, v0
; TONGA-NEXT: v_bfe_i32 v0, v0, 0, 8 ; TONGA-NEXT: v_bfe_i32 v0, v0, 0, 8
; TONGA-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; TONGA-NEXT: buffer_store_dword v0, off, s[0:3], 0
; TONGA-NEXT: s_endpgm ; TONGA-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_sdiv_i8: ; GFX9-LABEL: v_sdiv_i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cvt_f32_i32_e32 v2, v1 ; GFX9-NEXT: v_cvt_f32_i32_e32 v2, v1
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 ; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v0
; GFX9-NEXT: v_or_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_or_b32_e32 v0, 1, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v2 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v2
; GFX9-NEXT: v_mul_f32_e32 v1, v3, v4 ; GFX9-NEXT: v_mul_f32_e32 v1, v3, v4
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v1 ; GFX9-NEXT: v_mad_f32 v3, -v1, v2, v3
; GFX9-NEXT: v_mad_f32 v1, -v1, v2, v3 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, |v2|
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v2| ; GFX9-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0
; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX9-NEXT: v_add_u32_e32 v0, v4, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v1, v0
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 8 ; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; EG-LABEL: v_sdiv_i8: ; EG-LABEL: v_sdiv_i8:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6 ; EG-NEXT: TEX 1 @6
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; TONGA-NEXT: v_cvt_f32_i32_e32 v1, v0 ; TONGA-NEXT: v_cvt_f32_i32_e32 v1, v0
; TONGA-NEXT: v_xor_b32_e32 v0, v0, v2 ; TONGA-NEXT: v_xor_b32_e32 v0, v0, v2
; TONGA-NEXT: v_rcp_iflag_f32_e32 v4, v3 ; TONGA-NEXT: v_rcp_iflag_f32_e32 v4, v3
; TONGA-NEXT: v_ashrrev_i32_e32 v0, 30, v0 ; TONGA-NEXT: v_ashrrev_i32_e32 v0, 30, v0
; TONGA-NEXT: v_or_b32_e32 v0, 1, v0 ; TONGA-NEXT: v_or_b32_e32 v0, 1, v0
; TONGA-NEXT: v_mul_f32_e32 v2, v1, v4 ; TONGA-NEXT: v_mul_f32_e32 v2, v1, v4
; TONGA-NEXT: v_trunc_f32_e32 v2, v2 ; TONGA-NEXT: v_trunc_f32_e32 v2, v2
; TONGA-NEXT: v_mad_f32 v1, -v2, v3, v1 ; TONGA-NEXT: v_mad_f32 v1, -v2, v3, v1
; TONGA-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v3|
; TONGA-NEXT: v_cvt_i32_f32_e32 v2, v2 ; TONGA-NEXT: v_cvt_i32_f32_e32 v2, v2
; TONGA-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v3| ; TONGA-NEXT: s_cmp_lg_u64 s[4:5], 0
; TONGA-NEXT: s_cselect_b64 vcc, -1, 0
; TONGA-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc ; TONGA-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v2, v0 ; TONGA-NEXT: v_add_u32_e32 v0, vcc, v2, v0
; TONGA-NEXT: v_bfe_i32 v0, v0, 0, 23 ; TONGA-NEXT: v_bfe_i32 v0, v0, 0, 23
; TONGA-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; TONGA-NEXT: buffer_store_dword v0, off, s[0:3], 0
; TONGA-NEXT: s_endpgm ; TONGA-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_sdiv_i23: ; GFX9-LABEL: v_sdiv_i23:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
Show All 22 Lines
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 23 ; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 23
; GFX9-NEXT: v_cvt_f32_i32_e32 v1, v0 ; GFX9-NEXT: v_cvt_f32_i32_e32 v1, v0
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2 ; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v3 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v3
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v0
; GFX9-NEXT: v_or_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_or_b32_e32 v0, 1, v0
; GFX9-NEXT: v_mul_f32_e32 v2, v1, v4 ; GFX9-NEXT: v_mul_f32_e32 v2, v1, v4
; GFX9-NEXT: v_trunc_f32_e32 v2, v2 ; GFX9-NEXT: v_trunc_f32_e32 v2, v2
; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v2
; GFX9-NEXT: v_mad_f32 v1, -v2, v3, v1 ; GFX9-NEXT: v_mad_f32 v1, -v2, v3, v1
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v3| ; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v3|
; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0
; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX9-NEXT: v_add_u32_e32 v0, v4, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v2, v0
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 23 ; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 23
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; EG-LABEL: v_sdiv_i23: ; EG-LABEL: v_sdiv_i23:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 3 @6 ; EG-NEXT: TEX 3 @6
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
; TONGA-NEXT: v_cvt_f32_i32_e32 v0, v0 ; TONGA-NEXT: v_cvt_f32_i32_e32 v0, v0
; TONGA-NEXT: v_rcp_iflag_f32_e32 v4, v2 ; TONGA-NEXT: v_rcp_iflag_f32_e32 v4, v2
; TONGA-NEXT: v_xor_b32_e32 v1, v1, v3 ; TONGA-NEXT: v_xor_b32_e32 v1, v1, v3
; TONGA-NEXT: v_ashrrev_i32_e32 v1, 30, v1 ; TONGA-NEXT: v_ashrrev_i32_e32 v1, 30, v1
; TONGA-NEXT: v_or_b32_e32 v1, 1, v1 ; TONGA-NEXT: v_or_b32_e32 v1, 1, v1
; TONGA-NEXT: v_mul_f32_e32 v3, v0, v4 ; TONGA-NEXT: v_mul_f32_e32 v3, v0, v4
; TONGA-NEXT: v_trunc_f32_e32 v3, v3 ; TONGA-NEXT: v_trunc_f32_e32 v3, v3
; TONGA-NEXT: v_mad_f32 v0, -v3, v2, v0 ; TONGA-NEXT: v_mad_f32 v0, -v3, v2, v0
; TONGA-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, |v2|
; TONGA-NEXT: v_cvt_i32_f32_e32 v3, v3 ; TONGA-NEXT: v_cvt_i32_f32_e32 v3, v3
; TONGA-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v2| ; TONGA-NEXT: s_cmp_lg_u64 s[4:5], 0
; TONGA-NEXT: s_cselect_b64 vcc, -1, 0
; TONGA-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc ; TONGA-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; TONGA-NEXT: v_add_u32_e32 v0, vcc, v3, v0 ; TONGA-NEXT: v_add_u32_e32 v0, vcc, v3, v0
; TONGA-NEXT: v_bfe_i32 v0, v0, 0, 24 ; TONGA-NEXT: v_bfe_i32 v0, v0, 0, 24
; TONGA-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; TONGA-NEXT: buffer_store_dword v0, off, s[0:3], 0
; TONGA-NEXT: s_endpgm ; TONGA-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_sdiv_i24: ; GFX9-LABEL: v_sdiv_i24:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_mov_b32 s10, s2
; GFX9-NEXT: s_mov_b32 s11, s3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s8, s6
; GFX9-NEXT: s_mov_b32 s9, s7
; GFX9-NEXT: buffer_load_ushort v0, off, s[8:11], 0
; GFX9-NEXT: buffer_load_sbyte v1, off, s[8:11], 0 offset:2
; GFX9-NEXT: buffer_load_ushort v2, off, s[8:11], 0 offset:4
; GFX9-NEXT: buffer_load_sbyte v3, off, s[8:11], 0 offset:6
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_mov_b32 s4, s6
; GFX9-NEXT: s_mov_b32 s5, s7
; GFX9-NEXT: s_mov_b32 s6, s2
; GFX9-NEXT: s_mov_b32 s7, s3
; GFX9-NEXT: buffer_load_ushort v0, off, s[4:7], 0
; GFX9-NEXT: buffer_load_sbyte v1, off, s[4:7], 0 offset:2
; GFX9-NEXT: buffer_load_ushort v2, off, s[4:7], 0 offset:4
; GFX9-NEXT: buffer_load_sbyte v3, off, s[4:7], 0 offset:6
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v3 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX9-NEXT: v_or_b32_e32 v2, v2, v4 ; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
; GFX9-NEXT: v_cvt_f32_i32_e32 v2, v2 ; GFX9-NEXT: v_cvt_f32_i32_e32 v2, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v1 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v4 ; GFX9-NEXT: v_or_b32_e32 v0, v0, v4
; GFX9-NEXT: v_cvt_f32_i32_e32 v0, v0 ; GFX9-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v2 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v2
; GFX9-NEXT: v_xor_b32_e32 v1, v1, v3 ; GFX9-NEXT: v_xor_b32_e32 v1, v1, v3
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 30, v1 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 30, v1
; GFX9-NEXT: v_or_b32_e32 v1, 1, v1 ; GFX9-NEXT: v_or_b32_e32 v1, 1, v1
; GFX9-NEXT: v_mul_f32_e32 v3, v0, v4 ; GFX9-NEXT: v_mul_f32_e32 v3, v0, v4
; GFX9-NEXT: v_trunc_f32_e32 v3, v3 ; GFX9-NEXT: v_trunc_f32_e32 v3, v3
; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v3
; GFX9-NEXT: v_mad_f32 v0, -v3, v2, v0 ; GFX9-NEXT: v_mad_f32 v0, -v3, v2, v0
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v2| ; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, |v2|
; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0
; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX9-NEXT: v_add_u32_e32 v0, v4, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v3, v0
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 24
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; EG-LABEL: v_sdiv_i24: ; EG-LABEL: v_sdiv_i24:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 3 @6 ; EG-NEXT: TEX 3 @6
▲ Show 20 Lines • Show All 430 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/sdiv64.ll

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_mov_b32 s3, s2 ; GCN-IR-NEXT: s_mov_b32 s3, s2
; GCN-IR-NEXT: s_ashr_i32 s8, s1, 31 ; GCN-IR-NEXT: s_ashr_i32 s8, s1, 31
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[2:3], s[6:7] ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[2:3], s[6:7]
; GCN-IR-NEXT: s_sub_u32 s10, s6, s2 ; GCN-IR-NEXT: s_sub_u32 s10, s6, s2
; GCN-IR-NEXT: s_mov_b32 s9, s8 ; GCN-IR-NEXT: s_mov_b32 s9, s8
; GCN-IR-NEXT: s_subb_u32 s11, s7, s2 ; GCN-IR-NEXT: s_subb_u32 s11, s7, s2
; GCN-IR-NEXT: s_xor_b64 s[0:1], s[8:9], s[0:1] ; GCN-IR-NEXT: s_xor_b64 s[0:1], s[8:9], s[0:1]
; GCN-IR-NEXT: s_sub_u32 s6, s0, s8 ; GCN-IR-NEXT: s_sub_u32 s6, s0, s8
; GCN-IR-NEXT: s_flbit_i32_b32 s14, s6
; GCN-IR-NEXT: s_subb_u32 s7, s1, s8 ; GCN-IR-NEXT: s_subb_u32 s7, s1, s8
; GCN-IR-NEXT: s_add_i32 s14, s14, 32 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[10:11], 0
; GCN-IR-NEXT: s_flbit_i32_b32 s15, s7 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[6:7], 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s14 ; GCN-IR-NEXT: s_or_b64 s[0:1], s[12:13], s[0:1]
; GCN-IR-NEXT: s_flbit_i32_b32 s14, s10 ; GCN-IR-NEXT: s_flbit_i32_b32 s12, s6
; GCN-IR-NEXT: v_mov_b32_e32 v0, s15 ; GCN-IR-NEXT: s_add_i32 s12, s12, 32
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 ; GCN-IR-NEXT: s_cmp_eq_u32 s7, 0
; GCN-IR-NEXT: s_add_i32 s14, s14, 32 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s12
; GCN-IR-NEXT: s_flbit_i32_b32 s15, s11 ; GCN-IR-NEXT: s_flbit_i32_b32 s12, s10
; GCN-IR-NEXT: s_flbit_i32_b32 s13, s7
; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: s_add_i32 s12, s12, 32
; GCN-IR-NEXT: v_mov_b32_e32 v0, s13
; GCN-IR-NEXT: s_flbit_i32_b32 s13, s11
; GCN-IR-NEXT: s_cmp_eq_u32 s11, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v0, s15 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s13
; GCN-IR-NEXT: v_mov_b32_e32 v1, s14 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s12
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s11, 0 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3
; GCN-IR-NEXT: v_subb_u32_e64 v1, s[14:15], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v1, s[12:13], 0, 0, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[10:11], 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[12:13]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_xor_b64 s[12:13], s[0:1], -1 ; GCN-IR-NEXT: s_xor_b64 s[12:13], s[0:1], -1
; GCN-IR-NEXT: s_and_b64 s[12:13], s[12:13], vcc ; GCN-IR-NEXT: s_and_b64 s[12:13], s[12:13], vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13]
; GCN-IR-NEXT: s_cbranch_vccz BB0_4 ; GCN-IR-NEXT: s_cbranch_vccz BB0_4
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0
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; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 ; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_sdiv24_48: ; GCN-IR-LABEL: s_test_sdiv24_48:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xb ; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xb
; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xc ; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xc
; GCN-IR-NEXT: s_load_dword s6, s[0:1], 0xd ; GCN-IR-NEXT: s_load_dword s4, s[0:1], 0xd
; GCN-IR-NEXT: s_load_dword s0, s[0:1], 0xe ; GCN-IR-NEXT: s_load_dword s5, s[0:1], 0xe
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_sext_i32_i16 s3, s3 ; GCN-IR-NEXT: s_sext_i32_i16 s3, s3
; GCN-IR-NEXT: s_sext_i32_i16 s7, s0 ; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[2:3], 24
; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[2:3], 24
; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31 ; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31
; GCN-IR-NEXT: s_sext_i32_i16 s5, s5
; GCN-IR-NEXT: s_mov_b32 s3, s2 ; GCN-IR-NEXT: s_mov_b32 s3, s2
; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[6:7], 24 ; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[4:5], 24
; GCN-IR-NEXT: s_ashr_i32 s6, s7, 31 ; GCN-IR-NEXT: s_ashr_i32 s4, s5, 31
; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1] ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[2:3], s[6:7]
; GCN-IR-NEXT: s_sub_u32 s10, s0, s2 ; GCN-IR-NEXT: s_sub_u32 s10, s6, s2
; GCN-IR-NEXT: s_mov_b32 s7, s6 ; GCN-IR-NEXT: s_mov_b32 s5, s4
; GCN-IR-NEXT: s_subb_u32 s11, s1, s2 ; GCN-IR-NEXT: s_subb_u32 s11, s7, s2
; GCN-IR-NEXT: s_xor_b64 s[0:1], s[6:7], s[8:9] ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s8, s0, s6 ; GCN-IR-NEXT: s_sub_u32 s6, s6, s4
; GCN-IR-NEXT: s_flbit_i32_b32 s14, s8 ; GCN-IR-NEXT: s_subb_u32 s7, s7, s4
; GCN-IR-NEXT: s_subb_u32 s9, s1, s6 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
; GCN-IR-NEXT: s_add_i32 s14, s14, 32 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[10:11], 0
; GCN-IR-NEXT: s_flbit_i32_b32 s15, s9 ; GCN-IR-NEXT: s_or_b64 s[12:13], s[8:9], s[12:13]
; GCN-IR-NEXT: v_mov_b32_e32 v1, s14 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6
; GCN-IR-NEXT: s_flbit_i32_b32 s14, s10 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: v_mov_b32_e32 v0, s15 ; GCN-IR-NEXT: s_cmp_eq_u32 s7, 0
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s8
; GCN-IR-NEXT: s_add_i32 s14, s14, 32 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s10
; GCN-IR-NEXT: s_flbit_i32_b32 s15, s11 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7
; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: v_mov_b32_e32 v0, s9
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s11
; GCN-IR-NEXT: s_cmp_eq_u32 s11, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v0, s15 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s9
; GCN-IR-NEXT: v_mov_b32_e32 v1, s14 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s8
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s11, 0 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3
; GCN-IR-NEXT: v_subb_u32_e64 v1, s[14:15], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v1, s[8:9], 0, 0, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[8:9], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[10:11], 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[12:13] ; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc ; GCN-IR-NEXT: s_or_b64 s[0:1], s[12:13], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_xor_b64 s[12:13], s[0:1], -1 ; GCN-IR-NEXT: s_xor_b64 s[12:13], s[0:1], -1
; GCN-IR-NEXT: s_and_b64 s[12:13], s[12:13], vcc ; GCN-IR-NEXT: s_and_b64 s[12:13], s[12:13], vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13]
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_mov_b64 vcc, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB9_4 ; GCN-IR-NEXT: s_cbranch_vccz BB9_4
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0
; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1]
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0
; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[10:11], v0 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[10:11], v0
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1]
; GCN-IR-NEXT: s_cbranch_vccz BB9_5 ; GCN-IR-NEXT: s_cbranch_vccz BB9_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_not_b32_e32 v2, v2 ; GCN-IR-NEXT: v_not_b32_e32 v2, v2
; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[10:11], v4 ; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[10:11], v4
; GCN-IR-NEXT: s_add_u32 s10, s8, -1 ; GCN-IR-NEXT: s_add_u32 s10, s6, -1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: s_addc_u32 s11, s9, -1 ; GCN-IR-NEXT: s_addc_u32 s11, s7, -1
; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: BB9_3: ; %udiv-do-while ; GCN-IR-NEXT: BB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0
; GCN-IR-NEXT: v_mov_b32_e32 v2, s11 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s11
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s10, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s10, v6
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2
; GCN-IR-NEXT: v_and_b32_e32 v10, s8, v8 ; GCN-IR-NEXT: v_and_b32_e32 v10, s6, v8
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8
; GCN-IR-NEXT: v_and_b32_e32 v11, s9, v8 ; GCN-IR-NEXT: v_and_b32_e32 v11, s7, v8
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 ; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 ; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v3
Show All 11 Lines
; GCN-IR-NEXT: BB9_5: ; GCN-IR-NEXT: BB9_5:
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: BB9_6: ; %Flow3 ; GCN-IR-NEXT: BB9_6: ; %Flow3
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-IR-NEXT: BB9_7: ; %udiv-end ; GCN-IR-NEXT: BB9_7: ; %udiv-end
; GCN-IR-NEXT: s_xor_b64 s[0:1], s[6:7], s[2:3] ; GCN-IR-NEXT: s_xor_b64 s[0:1], s[4:5], s[2:3]
; GCN-IR-NEXT: v_xor_b32_e32 v0, s0, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v0, s0, v0
; GCN-IR-NEXT: v_xor_b32_e32 v1, s1, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v1, s1, v1
; GCN-IR-NEXT: v_mov_b32_e32 v2, s1 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s1
; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0 ; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s11, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_mov_b32 s10, -1
; GCN-IR-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 ; GCN-IR-NEXT: buffer_store_short v1, off, s[8:11], 0 offset:4
; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-IR-NEXT: buffer_store_dword v0, off, s[8:11], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%1 = ashr i48 %x, 24 %1 = ashr i48 %x, 24
%2 = ashr i48 %y, 24 %2 = ashr i48 %y, 24
%result = sdiv i48 %1, %2 %result = sdiv i48 %1, %2
store i48 %result, i48 addrspace(1)* %out store i48 %result, i48 addrspace(1)* %out
ret void ret void
} }
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
; GCN-IR-LABEL: s_test_sdiv_k_num_i64: ; GCN-IR-LABEL: s_test_sdiv_k_num_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_ashr_i32 s2, s7, 31 ; GCN-IR-NEXT: s_ashr_i32 s2, s7, 31
; GCN-IR-NEXT: s_mov_b32 s3, s2 ; GCN-IR-NEXT: s_mov_b32 s3, s2
; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[6:7] ; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[6:7]
; GCN-IR-NEXT: s_sub_u32 s6, s0, s2 ; GCN-IR-NEXT: s_sub_u32 s6, s0, s2
; GCN-IR-NEXT: s_subb_u32 s7, s1, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6
; GCN-IR-NEXT: s_subb_u32 s7, s1, s2
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7
; GCN-IR-NEXT: s_cmp_eq_u32 s7, 0
; GCN-IR-NEXT: v_mov_b32_e32 v0, s9 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s9
; GCN-IR-NEXT: v_mov_b32_e32 v1, s8 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s8
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc5, v2 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc5, v2
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[8:9], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[8:9], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_xor_b64 s[8:9], s[0:1], -1 ; GCN-IR-NEXT: s_xor_b64 s[8:9], s[0:1], -1
▲ Show 20 Lines • Show All 841 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone
declare i32 @llvm.amdgcn.sffbh.i32(i32) nounwind readnone speculatable declare i32 @llvm.amdgcn.sffbh.i32(i32) nounwind readnone speculatable
define amdgpu_kernel void @select_constant_cttz(i32 addrspace(1)* noalias %out, i32 addrspace(1)* nocapture readonly %arrayidx) nounwind { define amdgpu_kernel void @select_constant_cttz(i32 addrspace(1)* noalias %out, i32 addrspace(1)* nocapture readonly %arrayidx) nounwind {
; GCN-LABEL: select_constant_cttz: ; GCN-LABEL: select_constant_cttz:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb ; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_load_dword s2, s[2:3], 0x0 ; GCN-NEXT: s_load_dword s2, s[2:3], 0x0
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_lshr_b32 s0, 1, s2 ; GCN-NEXT: s_lshr_b32 s0, 1, s2
; GCN-NEXT: s_ff1_i32_b32 s0, s0 ; GCN-NEXT: s_ff1_i32_b32 s0, s0
; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_cmp_lg_u32 s2, 0
; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_cmp_ne_u32_e64 s[2:3], s2, 0 ; GCN-NEXT: s_cselect_b64 s[2:3], -1, 0
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[2:3] ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[2:3]
; GCN-NEXT: v_ffbh_i32_e32 v1, v0 ; GCN-NEXT: v_ffbh_i32_e32 v1, v0
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v0 ; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v0
; GCN-NEXT: v_sub_i32_e32 v0, vcc, 31, v1 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, 31, v1
; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] ; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, -1, s[0:1]
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
Show All 15 Lines

llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll

Show First 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @add_select_posk_posk_f32(i32 %c) #0 {
store volatile float %add, float addrspace(1)* undef store volatile float %add, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}add_select_negk_fabs_f32: ; GCN-LABEL: {{^}}add_select_negk_fabs_f32:
; GCN: buffer_load_dword [[X:v[0-9]+]] ; GCN: buffer_load_dword [[X:v[0-9]+]]
; GCN: buffer_load_dword [[Y:v[0-9]+]] ; GCN: buffer_load_dword [[Y:v[0-9]+]]
; GCN-DAG: v_cmp_ne_u32_e64 [[VCC:.*]], s{{[0-9]+}}, 0 ; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0
; GCN: s_cselect_b64 [[VCC:.*]], -1, 0
; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], -1.0, |[[X]]|, [[VCC]] ; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], -1.0, |[[X]]|, [[VCC]]
; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]] ; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
define amdgpu_kernel void @add_select_negk_fabs_f32(i32 %c) #0 { define amdgpu_kernel void @add_select_negk_fabs_f32(i32 %c) #0 {
%x = load volatile float, float addrspace(1)* undef %x = load volatile float, float addrspace(1)* undef
%y = load volatile float, float addrspace(1)* undef %y = load volatile float, float addrspace(1)* undef
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%fabs = call float @llvm.fabs.f32(float %x) %fabs = call float @llvm.fabs.f32(float %x)
%select = select i1 %cmp, float -1.0, float %fabs %select = select i1 %cmp, float -1.0, float %fabs
%add = fadd float %select, %y %add = fadd float %select, %y
store volatile float %add, float addrspace(1)* undef store volatile float %add, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}add_select_negliteralk_fabs_f32: ; GCN-LABEL: {{^}}add_select_negliteralk_fabs_f32:
; GCN-DAG: buffer_load_dword [[X:v[0-9]+]] ; GCN-DAG: buffer_load_dword [[X:v[0-9]+]]
; GCN-DAG: buffer_load_dword [[Y:v[0-9]+]] ; GCN-DAG: buffer_load_dword [[Y:v[0-9]+]]
; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0xc4800000 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0xc4800000
; GCN-DAG: v_cmp_ne_u32_e64 [[VCC:.*]], s{{[0-9]+}}, 0 ; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0
; GCN: s_cselect_b64 [[VCC:.*]], -1, 0
; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], [[K]], |[[X]]|, [[VCC]] ; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], [[K]], |[[X]]|, [[VCC]]
; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]] ; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
define amdgpu_kernel void @add_select_negliteralk_fabs_f32(i32 %c) #0 { define amdgpu_kernel void @add_select_negliteralk_fabs_f32(i32 %c) #0 {
%x = load volatile float, float addrspace(1)* undef %x = load volatile float, float addrspace(1)* undef
%y = load volatile float, float addrspace(1)* undef %y = load volatile float, float addrspace(1)* undef
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%fabs = call float @llvm.fabs.f32(float %x) %fabs = call float @llvm.fabs.f32(float %x)
%select = select i1 %cmp, float -1024.0, float %fabs %select = select i1 %cmp, float -1024.0, float %fabs
Show All 19 Linesdefine amdgpu_kernel void @add_select_fabs_posk_f32(i32 %c) #0 {
store volatile float %add, float addrspace(1)* undef store volatile float %add, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}add_select_posk_fabs_f32: ; GCN-LABEL: {{^}}add_select_posk_fabs_f32:
; GCN: buffer_load_dword [[X:v[0-9]+]] ; GCN: buffer_load_dword [[X:v[0-9]+]]
; GCN: buffer_load_dword [[Y:v[0-9]+]] ; GCN: buffer_load_dword [[Y:v[0-9]+]]
; GCN: v_cmp_ne_u32_e64 vcc, s{{[0-9]+}}, 0 ; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0
; GCN: s_cselect_b64 [[VCC:.*]], -1, 0
; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 1.0, [[X]], vcc ; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 1.0, [[X]], vcc
; GCN: v_add_f32_e64 v{{[0-9]+}}, |[[SELECT]]|, [[Y]] ; GCN: v_add_f32_e64 v{{[0-9]+}}, |[[SELECT]]|, [[Y]]
define amdgpu_kernel void @add_select_posk_fabs_f32(i32 %c) #0 { define amdgpu_kernel void @add_select_posk_fabs_f32(i32 %c) #0 {
%x = load volatile float, float addrspace(1)* undef %x = load volatile float, float addrspace(1)* undef
%y = load volatile float, float addrspace(1)* undef %y = load volatile float, float addrspace(1)* undef
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%fabs = call float @llvm.fabs.f32(float %x) %fabs = call float @llvm.fabs.f32(float %x)
%select = select i1 %cmp, float 1.0, float %fabs %select = select i1 %cmp, float 1.0, float %fabs
▲ Show 20 Lines • Show All 169 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @add_select_fneg_neginv2pi_f32(i32 %c) #0 {
%add = fadd float %select, %y %add = fadd float %select, %y
store volatile float %add, float addrspace(1)* undef store volatile float %add, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}add_select_negk_negk_f32: ; GCN-LABEL: {{^}}add_select_negk_negk_f32:
; GCN: buffer_load_dword [[X:v[0-9]+]] ; GCN: buffer_load_dword [[X:v[0-9]+]]
; GCN: v_cmp_eq_u32_e64 ; GCN: s_cmp_eq_u32
; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], -1.0, -2.0, s ; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], -1.0, -2.0, s
; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[X]] ; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[X]]
define amdgpu_kernel void @add_select_negk_negk_f32(i32 %c) #0 { define amdgpu_kernel void @add_select_negk_negk_f32(i32 %c) #0 {
%x = load volatile float, float addrspace(1)* undef %x = load volatile float, float addrspace(1)* undef
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, float -2.0, float -1.0 %select = select i1 %cmp, float -2.0, float -1.0
%add = fadd float %select, %x %add = fadd float %select, %x
store volatile float %add, float addrspace(1)* undef store volatile float %add, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}add_select_negliteralk_negliteralk_f32: ; GCN-LABEL: {{^}}add_select_negliteralk_negliteralk_f32:
; GCN-DAG: v_mov_b32_e32 [[K0:v[0-9]+]], 0xc5000000 ; GCN-DAG: v_mov_b32_e32 [[K0:v[0-9]+]], 0xc5000000
; GCN-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0xc5800000 ; GCN-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0xc5800000
; GCN-DAG: buffer_load_dword [[X:v[0-9]+]] ; GCN-DAG: buffer_load_dword [[X:v[0-9]+]]
; GCN: v_cmp_eq_u32_e64 ; GCN: s_cmp_eq_u32
; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], [[K1]], [[K0]], vcc ; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], [[K1]], [[K0]], vcc
; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[X]] ; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[X]]
define amdgpu_kernel void @add_select_negliteralk_negliteralk_f32(i32 %c) #0 { define amdgpu_kernel void @add_select_negliteralk_negliteralk_f32(i32 %c) #0 {
%x = load volatile float, float addrspace(1)* undef %x = load volatile float, float addrspace(1)* undef
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, float -2048.0, float -4096.0 %select = select i1 %cmp, float -2048.0, float -4096.0
%add = fadd float %select, %x %add = fadd float %select, %x
store volatile float %add, float addrspace(1)* undef store volatile float %add, float addrspace(1)* undef
Show All 14 Linesdefine amdgpu_kernel void @add_select_fneg_negk_negk_f32(i32 %c) #0 {
store volatile float %add, float addrspace(1)* undef store volatile float %add, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}add_select_negk_fneg_f32: ; GCN-LABEL: {{^}}add_select_negk_fneg_f32:
; GCN: buffer_load_dword [[X:v[0-9]+]] ; GCN: buffer_load_dword [[X:v[0-9]+]]
; GCN: buffer_load_dword [[Y:v[0-9]+]] ; GCN: buffer_load_dword [[Y:v[0-9]+]]
; GCN: v_cmp_ne_u32_e64 vcc, s{{[0-9]+}}, 0 ; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0
; GCN: s_cselect_b64 vcc, -1, 0
; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 1.0, [[X]], vcc ; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 1.0, [[X]], vcc
; GCN: v_sub_f32_e32 v{{[0-9]+}}, [[Y]], [[SELECT]] ; GCN: v_sub_f32_e32 v{{[0-9]+}}, [[Y]], [[SELECT]]
define amdgpu_kernel void @add_select_negk_fneg_f32(i32 %c) #0 { define amdgpu_kernel void @add_select_negk_fneg_f32(i32 %c) #0 {
%x = load volatile float, float addrspace(1)* undef %x = load volatile float, float addrspace(1)* undef
%y = load volatile float, float addrspace(1)* undef %y = load volatile float, float addrspace(1)* undef
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%fneg.x = fsub float -0.0, %x %fneg.x = fsub float -0.0, %x
%select = select i1 %cmp, float -1.0, float %fneg.x %select = select i1 %cmp, float -1.0, float %fneg.x
Show All 18 Linesdefine amdgpu_kernel void @add_select_fneg_posk_f32(i32 %c) #0 {
store volatile float %add, float addrspace(1)* undef store volatile float %add, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}add_select_posk_fneg_f32: ; GCN-LABEL: {{^}}add_select_posk_fneg_f32:
; GCN: buffer_load_dword [[X:v[0-9]+]] ; GCN: buffer_load_dword [[X:v[0-9]+]]
; GCN: buffer_load_dword [[Y:v[0-9]+]] ; GCN: buffer_load_dword [[Y:v[0-9]+]]
; GCN: v_cmp_ne_u32_e64 vcc, s{{[0-9]+}}, 0 ; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0
; GCN: s_cselect_b64 vcc, -1, 0
; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], -1.0, [[X]], vcc ; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], -1.0, [[X]], vcc
; GCN: v_sub_f32_e32 v{{[0-9]+}}, [[Y]], [[SELECT]] ; GCN: v_sub_f32_e32 v{{[0-9]+}}, [[Y]], [[SELECT]]
define amdgpu_kernel void @add_select_posk_fneg_f32(i32 %c) #0 { define amdgpu_kernel void @add_select_posk_fneg_f32(i32 %c) #0 {
%x = load volatile float, float addrspace(1)* undef %x = load volatile float, float addrspace(1)* undef
%y = load volatile float, float addrspace(1)* undef %y = load volatile float, float addrspace(1)* undef
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%fneg.x = fsub float -0.0, %x %fneg.x = fsub float -0.0, %x
%select = select i1 %cmp, float 1.0, float %fneg.x %select = select i1 %cmp, float 1.0, float %fneg.x
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @add_select_negfabs_neg_f32(i32 %c) #0 {
store volatile float %add, float addrspace(1)* undef store volatile float %add, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}mul_select_negfabs_posk_f32: ; GCN-LABEL: {{^}}mul_select_negfabs_posk_f32:
; GCN: buffer_load_dword [[X:v[0-9]+]] ; GCN: buffer_load_dword [[X:v[0-9]+]]
; GCN: buffer_load_dword [[Y:v[0-9]+]] ; GCN: buffer_load_dword [[Y:v[0-9]+]]
; GCN-DAG: v_cmp_eq_u32_e64 [[VCC:.*]], s{{[0-9]+}}, 0 ; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0
; GCN: s_cselect_b64 [[VCC:.*]], -1, 0
; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], -4.0, |[[X]]|, [[VCC]] ; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], -4.0, |[[X]]|, [[VCC]]
; GCN: v_mul_f32_e64 v{{[0-9]+}}, -[[SELECT]], [[Y]] ; GCN: v_mul_f32_e64 v{{[0-9]+}}, -[[SELECT]], [[Y]]
define amdgpu_kernel void @mul_select_negfabs_posk_f32(i32 %c) #0 { define amdgpu_kernel void @mul_select_negfabs_posk_f32(i32 %c) #0 {
%x = load volatile float, float addrspace(1)* undef %x = load volatile float, float addrspace(1)* undef
%y = load volatile float, float addrspace(1)* undef %y = load volatile float, float addrspace(1)* undef
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%fabs.x = call float @llvm.fabs.f32(float %x) %fabs.x = call float @llvm.fabs.f32(float %x)
%fneg.fabs.x = fsub float -0.000000e+00, %fabs.x %fneg.fabs.x = fsub float -0.000000e+00, %fabs.x
%select = select i1 %cmp, float %fneg.fabs.x, float 4.0 %select = select i1 %cmp, float %fneg.fabs.x, float 4.0
%add = fmul float %select, %y %add = fmul float %select, %y
store volatile float %add, float addrspace(1)* undef store volatile float %add, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}mul_select_posk_negfabs_f32: ; GCN-LABEL: {{^}}mul_select_posk_negfabs_f32:
; GCN: buffer_load_dword [[X:v[0-9]+]] ; GCN: buffer_load_dword [[X:v[0-9]+]]
; GCN: buffer_load_dword [[Y:v[0-9]+]] ; GCN: buffer_load_dword [[Y:v[0-9]+]]
; GCN-DAG: v_cmp_ne_u32_e64 [[VCC:.*]], s{{[0-9]+}}, 0 ; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0
; GCN: s_cselect_b64 [[VCC:.*]], -1, 0
; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], -4.0, |[[X]]|, [[VCC]] ; GCN: v_cndmask_b32_e64 [[SELECT:v[0-9]+]], -4.0, |[[X]]|, [[VCC]]
; GCN: v_mul_f32_e64 v{{[0-9]+}}, -[[SELECT]], [[Y]] ; GCN: v_mul_f32_e64 v{{[0-9]+}}, -[[SELECT]], [[Y]]
define amdgpu_kernel void @mul_select_posk_negfabs_f32(i32 %c) #0 { define amdgpu_kernel void @mul_select_posk_negfabs_f32(i32 %c) #0 {
%x = load volatile float, float addrspace(1)* undef %x = load volatile float, float addrspace(1)* undef
%y = load volatile float, float addrspace(1)* undef %y = load volatile float, float addrspace(1)* undef
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%fabs.x = call float @llvm.fabs.f32(float %x) %fabs.x = call float @llvm.fabs.f32(float %x)
%fneg.fabs.x = fsub float -0.000000e+00, %fabs.x %fneg.fabs.x = fsub float -0.000000e+00, %fabs.x
Show All 20 Linesdefine amdgpu_kernel void @mul_select_negfabs_negk_f32(i32 %c) #0 {
store volatile float %add, float addrspace(1)* undef store volatile float %add, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}mul_select_negk_negfabs_f32: ; GCN-LABEL: {{^}}mul_select_negk_negfabs_f32:
; GCN: buffer_load_dword [[X:v[0-9]+]] ; GCN: buffer_load_dword [[X:v[0-9]+]]
; GCN: buffer_load_dword [[Y:v[0-9]+]] ; GCN: buffer_load_dword [[Y:v[0-9]+]]
; GCN: v_cmp_ne_u32_e64 vcc ; GCN: s_cmp_lg_u32
; GCN: s_cselect_b64 vcc, -1, 0
; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 4.0, [[X]], vcc ; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 4.0, [[X]], vcc
; GCN: v_mul_f32_e64 v{{[0-9]+}}, -|[[SELECT]]|, [[Y]] ; GCN: v_mul_f32_e64 v{{[0-9]+}}, -|[[SELECT]]|, [[Y]]
define amdgpu_kernel void @mul_select_negk_negfabs_f32(i32 %c) #0 { define amdgpu_kernel void @mul_select_negk_negfabs_f32(i32 %c) #0 {
%x = load volatile float, float addrspace(1)* undef %x = load volatile float, float addrspace(1)* undef
%y = load volatile float, float addrspace(1)* undef %y = load volatile float, float addrspace(1)* undef
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%fabs.x = call float @llvm.fabs.f32(float %x) %fabs.x = call float @llvm.fabs.f32(float %x)
%fneg.fabs.x = fsub float -0.000000e+00, %fabs.x %fneg.fabs.x = fsub float -0.000000e+00, %fabs.x
▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/select-opt.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; Make sure to test with f32 and i32 compares. If we have to use float ; Make sure to test with f32 and i32 compares. If we have to use float
; compares, we always have multiple condition registers. If we can do ; compares, we always have multiple condition registers. If we can do
; scalar compares, we don't want to use multiple condition registers. ; scalar compares, we don't want to use multiple condition registers.
; GCN-LABEL: {{^}}opt_select_i32_and_cmp_i32: ; GCN-LABEL: {{^}}opt_select_i32_and_cmp_i32:
; GCN-DAG: v_cmp_ne_u32_e32 vcc, ; GCN-DAG: s_cmp_lg_u32
; GCN-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]] ; GCN: s_cselect_b64 [[CMP1:s\[[0-9]+:[0-9]+\]]], -1, 0
; GCN: s_and_b64 vcc, vcc, [[CMP1]] ; GCN-DAG: s_cmp_lg_u32
; GCN: s_cselect_b64 [[CMP2:s\[[0-9]+:[0-9]+\]]], -1, 0
; GCN: s_and_b64 vcc, [[CMP1]], [[CMP2]]
; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc ; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
; GCN-NOT: [[RESULT]] ; GCN-NOT: [[RESULT]]
; GCN: buffer_store_dword [[RESULT]] ; GCN: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @opt_select_i32_and_cmp_i32(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %x, i32 %y) #0 { define amdgpu_kernel void @opt_select_i32_and_cmp_i32(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %x, i32 %y) #0 {
%icmp0 = icmp ne i32 %a, %b %icmp0 = icmp ne i32 %a, %b
%icmp1 = icmp ne i32 %a, %c %icmp1 = icmp ne i32 %a, %c
%and = and i1 %icmp0, %icmp1 %and = and i1 %icmp0, %icmp1
%select = select i1 %and, i32 %x, i32 %y %select = select i1 %and, i32 %x, i32 %y
Show All 13 Linesdefine amdgpu_kernel void @opt_select_i32_and_cmp_f32(i32 addrspace(1)* %out, float %a, float %b, float %c, i32 %x, i32 %y) #0 {
%fcmp1 = fcmp one float %a, %c %fcmp1 = fcmp one float %a, %c
%and = and i1 %fcmp0, %fcmp1 %and = and i1 %fcmp0, %fcmp1
%select = select i1 %and, i32 %x, i32 %y %select = select i1 %and, i32 %x, i32 %y
store i32 %select, i32 addrspace(1)* %out store i32 %select, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}opt_select_i64_and_cmp_i32: ; GCN-LABEL: {{^}}opt_select_i64_and_cmp_i32:
; GCN-DAG: v_cmp_ne_u32_e32 vcc, ; GCN-DAG: s_cmp_lg_u32
; GCN-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]] ; GCN: s_cselect_b64 [[CMP1:s\[[0-9]+:[0-9]+\]]], -1, 0
; GCN: s_and_b64 vcc, vcc, [[CMP1]] ; GCN-DAG: s_cmp_lg_u32
; GCN: s_cselect_b64 [[CMP2:s\[[0-9]+:[0-9]+\]]], -1, 0
; GCN: s_and_b64 vcc, [[CMP1]], [[CMP2]]
; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc ; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc ; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT0]]:[[RESULT1]]{{\]}} ; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT0]]:[[RESULT1]]{{\]}}
define amdgpu_kernel void @opt_select_i64_and_cmp_i32(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i64 %x, i64 %y) #0 { define amdgpu_kernel void @opt_select_i64_and_cmp_i32(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i64 %x, i64 %y) #0 {
%icmp0 = icmp ne i32 %a, %b %icmp0 = icmp ne i32 %a, %b
%icmp1 = icmp ne i32 %a, %c %icmp1 = icmp ne i32 %a, %c
%and = and i1 %icmp0, %icmp1 %and = and i1 %icmp0, %icmp1
%select = select i1 %and, i64 %x, i64 %y %select = select i1 %and, i64 %x, i64 %y
Show All 13 Linesdefine amdgpu_kernel void @opt_select_i64_and_cmp_f32(i64 addrspace(1)* %out, float %a, float %b, float %c, i64 %x, i64 %y) #0 {
%fcmp1 = fcmp one float %a, %c %fcmp1 = fcmp one float %a, %c
%and = and i1 %fcmp0, %fcmp1 %and = and i1 %fcmp0, %fcmp1
%select = select i1 %and, i64 %x, i64 %y %select = select i1 %and, i64 %x, i64 %y
store i64 %select, i64 addrspace(1)* %out store i64 %select, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}opt_select_i32_or_cmp_i32: ; GCN-LABEL: {{^}}opt_select_i32_or_cmp_i32:
; GCN-DAG: v_cmp_ne_u32_e32 vcc, ; GCN-DAG: s_cmp_lg_u32
; GCN-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]] ; GCN: s_cselect_b64 [[CMP1:s\[[0-9]+:[0-9]+\]]], -1, 0
; GCN: s_or_b64 vcc, vcc, [[CMP1]] ; GCN-DAG: s_cmp_lg_u32
; GCN: s_cselect_b64 [[CMP2:s\[[0-9]+:[0-9]+\]]], -1, 0
; GCN: s_or_b64 vcc, [[CMP1]], [[CMP2]]
; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc ; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
; GCN-NOT: [[RESULT]] ; GCN-NOT: [[RESULT]]
; GCN: buffer_store_dword [[RESULT]] ; GCN: buffer_store_dword [[RESULT]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @opt_select_i32_or_cmp_i32(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %x, i32 %y) #0 { define amdgpu_kernel void @opt_select_i32_or_cmp_i32(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %x, i32 %y) #0 {
%icmp0 = icmp ne i32 %a, %b %icmp0 = icmp ne i32 %a, %b
%icmp1 = icmp ne i32 %a, %c %icmp1 = icmp ne i32 %a, %c
%or = or i1 %icmp0, %icmp1 %or = or i1 %icmp0, %icmp1
Show All 14 Linesdefine amdgpu_kernel void @opt_select_i32_or_cmp_f32(i32 addrspace(1)* %out, float %a, float %b, float %c, i32 %x, i32 %y) #0 {
%fcmp1 = fcmp one float %a, %c %fcmp1 = fcmp one float %a, %c
%or = or i1 %fcmp0, %fcmp1 %or = or i1 %fcmp0, %fcmp1
%select = select i1 %or, i32 %x, i32 %y %select = select i1 %or, i32 %x, i32 %y
store i32 %select, i32 addrspace(1)* %out store i32 %select, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}opt_select_i64_or_cmp_i32: ; GCN-LABEL: {{^}}opt_select_i64_or_cmp_i32:
; GCN-DAG: v_cmp_ne_u32_e32 vcc, ; GCN-DAG: s_cmp_lg_u32
; GCN-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]] ; GCN: s_cselect_b64 [[CMP1:s\[[0-9]+:[0-9]+\]]], -1, 0
; GCN: s_or_b64 vcc, vcc, [[CMP1]] ; GCN-DAG: s_cmp_lg_u32
; GCN: s_cselect_b64 [[CMP2:s\[[0-9]+:[0-9]+\]]], -1, 0
; GCN: s_or_b64 vcc, [[CMP1]], [[CMP2]]
; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc ; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc ; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT0]]:[[RESULT1]]{{\]}} ; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT0]]:[[RESULT1]]{{\]}}
define amdgpu_kernel void @opt_select_i64_or_cmp_i32(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i64 %x, i64 %y) #0 { define amdgpu_kernel void @opt_select_i64_or_cmp_i32(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i64 %x, i64 %y) #0 {
%icmp0 = icmp ne i32 %a, %b %icmp0 = icmp ne i32 %a, %b
%icmp1 = icmp ne i32 %a, %c %icmp1 = icmp ne i32 %a, %c
%or = or i1 %icmp0, %icmp1 %or = or i1 %icmp0, %icmp1
%select = select i1 %or, i64 %x, i64 %y %select = select i1 %or, i64 %x, i64 %y
▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/select-vectors.ll

Show First 20 Lines • Show All 177 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @s_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, i32 %c) #0 {
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, <4 x i32> %a, <4 x i32> %b %select = select i1 %cmp, <4 x i32> %a, <4 x i32> %b
store <4 x i32> %select, <4 x i32> addrspace(1)* %out, align 16 store <4 x i32> %select, <4 x i32> addrspace(1)* %out, align 16
ret void ret void
} }
; GCN-LABEL: {{^}}v_select_v4i32: ; GCN-LABEL: {{^}}v_select_v4i32:
; GCN: buffer_load_dwordx4 ; GCN: buffer_load_dwordx4
; GCN: v_cmp_lt_u32_e64 vcc, s{{[0-9]+}}, 32 ; GCN: s_cmp_lt_u32 s{{[0-9]+}}, 32
; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} ; GCN: s_cselect_b64 vcc, -1, 0
; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc
; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc
; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc
; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc
; GCN: buffer_store_dwordx4 ; GCN: buffer_store_dwordx4
define amdgpu_kernel void @v_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %cond) #0 { define amdgpu_kernel void @v_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %cond) #0 {
bb: bb:
%tmp2 = icmp ult i32 %cond, 32 %tmp2 = icmp ult i32 %cond, 32
%val = load <4 x i32>, <4 x i32> addrspace(1)* %in %val = load <4 x i32>, <4 x i32> addrspace(1)* %in
%tmp3 = select i1 %tmp2, <4 x i32> %val, <4 x i32> zeroinitializer %tmp3 = select i1 %tmp2, <4 x i32> %val, <4 x i32> zeroinitializer
store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %out, align 16 store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %out, align 16
ret void ret void
Show All 17 Lines
; GCN-LABEL: {{^}}s_select_v2f32: ; GCN-LABEL: {{^}}s_select_v2f32:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[ALO:[0-9]+]]:[[AHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} ; GCN-DAG: s_load_dwordx2 s{{\[}}[[ALO:[0-9]+]]:[[AHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
; GCN-DAG: s_load_dwordx2 s{{\[}}[[BLO:[0-9]+]]:[[BHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xd|0x34}} ; GCN-DAG: s_load_dwordx2 s{{\[}}[[BLO:[0-9]+]]:[[BHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xd|0x34}}
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[AHI]] ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[AHI]]
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BHI]] ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BHI]]
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[ALO]] ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[ALO]]
; GCN-DAG: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}} ; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}}
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BLO]] ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BLO]]
; GCN-DAG: v_cndmask_b32_e32 ; GCN-DAG: v_cndmask_b32_e32
; GCN: buffer_store_dwordx2 ; GCN: buffer_store_dwordx2
define amdgpu_kernel void @s_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) #0 { define amdgpu_kernel void @s_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) #0 {
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, <2 x float> %a, <2 x float> %b %select = select i1 %cmp, <2 x float> %a, <2 x float> %b
store <2 x float> %select, <2 x float> addrspace(1)* %out, align 16 store <2 x float> %select, <2 x float> addrspace(1)* %out, align 16
ret void ret void
} }
; GCN-LABEL: {{^}}s_select_v3f32: ; GCN-LABEL: {{^}}s_select_v3f32:
; GCN: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}} ; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}}
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: buffer_store_dwordx ; GCN: buffer_store_dwordx
define amdgpu_kernel void @s_select_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, <3 x float> %b, i32 %c) #0 { define amdgpu_kernel void @s_select_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, <3 x float> %b, i32 %c) #0 {
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, <3 x float> %a, <3 x float> %b %select = select i1 %cmp, <3 x float> %a, <3 x float> %b
store <3 x float> %select, <3 x float> addrspace(1)* %out, align 16 store <3 x float> %select, <3 x float> addrspace(1)* %out, align 16
ret void ret void
} }
; GCN-LABEL: {{^}}s_select_v4f32: ; GCN-LABEL: {{^}}s_select_v4f32:
; GCN: s_load_dwordx4 ; GCN: s_load_dwordx4
; GCN: s_load_dwordx4 ; GCN: s_load_dwordx4
; GCN: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}} ; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}}
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: buffer_store_dwordx4 ; GCN: buffer_store_dwordx4
define amdgpu_kernel void @s_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b, i32 %c) #0 { define amdgpu_kernel void @s_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b, i32 %c) #0 {
%cmp = icmp eq i32 %c, 0 %cmp = icmp eq i32 %c, 0
%select = select i1 %cmp, <4 x float> %a, <4 x float> %b %select = select i1 %cmp, <4 x float> %a, <4 x float> %b
store <4 x float> %select, <4 x float> addrspace(1)* %out, align 16 store <4 x float> %select, <4 x float> addrspace(1)* %out, align 16
ret void ret void
} }
; GCN-LABEL: {{^}}v_select_v4f32: ; GCN-LABEL: {{^}}v_select_v4f32:
; GCN: buffer_load_dwordx4 ; GCN: buffer_load_dwordx4
; GCN: v_cmp_lt_u32_e64 vcc, s{{[0-9]+}}, 32 ; GCN: s_cmp_lt_u32 s{{[0-9]+}}, 32
; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} ; GCN: s_cselect_b64 vcc, -1, 0
; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc
; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc
; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc
; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc
; GCN: buffer_store_dwordx4 ; GCN: buffer_store_dwordx4
define amdgpu_kernel void @v_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in, i32 %cond) #0 { define amdgpu_kernel void @v_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in, i32 %cond) #0 {
bb: bb:
%tmp2 = icmp ult i32 %cond, 32 %tmp2 = icmp ult i32 %cond, 32
%val = load <4 x float>, <4 x float> addrspace(1)* %in %val = load <4 x float>, <4 x float> addrspace(1)* %in
%tmp3 = select i1 %tmp2, <4 x float> %val, <4 x float> zeroinitializer %tmp3 = select i1 %tmp2, <4 x float> %val, <4 x float> zeroinitializer
store <4 x float> %tmp3, <4 x float> addrspace(1)* %out, align 16 store <4 x float> %tmp3, <4 x float> addrspace(1)* %out, align 16
ret void ret void
} }
; GCN-LABEL: {{^}}s_select_v5f32: ; GCN-LABEL: {{^}}s_select_v5f32:
; GCN: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}} ; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}}
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: buffer_store_dwordx ; GCN: buffer_store_dwordx
▲ Show 20 Lines • Show All 118 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/selectcc-opt.ll

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
entry: entry:
%0 = icmp sgt i32 %in, 0 %0 = icmp sgt i32 %in, 0
%1 = select i1 %0, float 2.0, float 3.0 %1 = select i1 %0, float 2.0, float 3.0
store float %1, float addrspace(1)* %out store float %1, float addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}selectcc_bool: ; FUNC-LABEL: {{^}}selectcc_bool:
; SI: v_cmp_ne_u32 ; SI: s_cmp_lg_u32
; SI: v_cndmask_b32_e64 ; SI: v_cndmask_b32_e64
; SI-NOT: cmp ; SI-NOT: cmp
; SI-NOT: cndmask ; SI-NOT: cndmask
define amdgpu_kernel void @selectcc_bool(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { define amdgpu_kernel void @selectcc_bool(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%icmp0 = icmp ne i32 %a, %b %icmp0 = icmp ne i32 %a, %b
%ext = select i1 %icmp0, i32 -1, i32 0 %ext = select i1 %icmp0, i32 -1, i32 0
store i32 %ext, i32 addrspace(1)* %out store i32 %ext, i32 addrspace(1)* %out
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/selectcc.ll

; RUN: llc -verify-machineinstrs -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -verify-machineinstrs -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI -check-prefix=FUNC %s
; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}selectcc_i64: ; FUNC-LABEL: {{^}}selectcc_i64:
; EG: XOR_INT ; EG: XOR_INT
; EG: XOR_INT ; EG: XOR_INT
; EG: OR_INT ; EG: OR_INT
; EG: CNDE_INT ; EG: CNDE_INT
; EG: CNDE_INT ; EG: CNDE_INT
; SI: v_cmp_eq_u64 ; SI: v_cmp_eq_u64
; SI: v_cndmask ; VI: s_cmp_eq_u64
; SI: v_cndmask ; GCN: v_cndmask
; GCN: v_cndmask
define amdgpu_kernel void @selectcc_i64(i64 addrspace(1) * %out, i64 %lhs, i64 %rhs, i64 %true, i64 %false) { define amdgpu_kernel void @selectcc_i64(i64 addrspace(1) * %out, i64 %lhs, i64 %rhs, i64 %true, i64 %false) {
entry: entry:
%0 = icmp eq i64 %lhs, %rhs %0 = icmp eq i64 %lhs, %rhs
%1 = select i1 %0, i64 %true, i64 %false %1 = select i1 %0, i64 %true, i64 %false
store i64 %1, i64 addrspace(1)* %out store i64 %1, i64 addrspace(1)* %out
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/setcc-opt.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}sext_bool_icmp_eq_0: ; FUNC-LABEL: {{^}}sext_bool_icmp_eq_0:
; GCN-NOT: v_cmp ; GCN-NOT: v_cmp
; GCN: v_cmp_ne_u32_e32 vcc, ; GCN: s_cmp_lg_u32
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc ; GCN: s_cselect_b64 [[CC:[^,]+]], -1, 0
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CC]]
; GCN-NEXT:buffer_store_byte [[RESULT]] ; GCN-NEXT:buffer_store_byte [[RESULT]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; EG: SETNE_INT * [[CMP:T[0-9]+]].[[CMPCHAN:[XYZW]]], KC0[2].Z, KC0[2].W ; EG: SETNE_INT * [[CMP:T[0-9]+]].[[CMPCHAN:[XYZW]]], KC0[2].Z, KC0[2].W
; EG: AND_INT T{{[0-9]+.[XYZW]}}, PS, 1 ; EG: AND_INT T{{[0-9]+.[XYZW]}}, PS, 1
define amdgpu_kernel void @sext_bool_icmp_eq_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { define amdgpu_kernel void @sext_bool_icmp_eq_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%icmp0 = icmp eq i32 %a, %b %icmp0 = icmp eq i32 %a, %b
%ext = sext i1 %icmp0 to i32 %ext = sext i1 %icmp0 to i32
%icmp1 = icmp eq i32 %ext, 0 %icmp1 = icmp eq i32 %ext, 0
store i1 %icmp1, i1 addrspace(1)* %out store i1 %icmp1, i1 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}sext_bool_icmp_ne_0: ; FUNC-LABEL: {{^}}sext_bool_icmp_ne_0:
; GCN-NOT: v_cmp ; GCN-NOT: v_cmp
; GCN: v_cmp_ne_u32_e32 vcc, ; GCN: s_cmp_lg_u32
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc ; GCN: s_cselect_b64 [[CC:[^,]+]], -1, 0
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CC]]
; GCN-NEXT: buffer_store_byte [[RESULT]] ; GCN-NEXT: buffer_store_byte [[RESULT]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; EG: SETNE_INT * [[CMP:T[0-9]+]].[[CMPCHAN:[XYZW]]], KC0[2].Z, KC0[2].W ; EG: SETNE_INT * [[CMP:T[0-9]+]].[[CMPCHAN:[XYZW]]], KC0[2].Z, KC0[2].W
; EG: AND_INT T{{[0-9]+.[XYZW]}}, PS, 1 ; EG: AND_INT T{{[0-9]+.[XYZW]}}, PS, 1
define amdgpu_kernel void @sext_bool_icmp_ne_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { define amdgpu_kernel void @sext_bool_icmp_ne_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%icmp0 = icmp ne i32 %a, %b %icmp0 = icmp ne i32 %a, %b
%ext = sext i1 %icmp0 to i32 %ext = sext i1 %icmp0 to i32
%icmp1 = icmp ne i32 %ext, 0 %icmp1 = icmp ne i32 %ext, 0
store i1 %icmp1, i1 addrspace(1)* %out store i1 %icmp1, i1 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}sext_bool_icmp_eq_neg1: ; FUNC-LABEL: {{^}}sext_bool_icmp_eq_neg1:
; GCN-NOT: v_cmp ; GCN-NOT: v_cmp
; GCN: v_cmp_eq_u32_e32 vcc, ; GCN: s_cmp_eq_u32
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc ; GCN: s_cselect_b64 [[CC:[^,]+]], -1, 0
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CC]]
; GCN-NEXT: buffer_store_byte [[RESULT]] ; GCN-NEXT: buffer_store_byte [[RESULT]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @sext_bool_icmp_eq_neg1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { define amdgpu_kernel void @sext_bool_icmp_eq_neg1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%icmp0 = icmp eq i32 %a, %b %icmp0 = icmp eq i32 %a, %b
%ext = sext i1 %icmp0 to i32 %ext = sext i1 %icmp0 to i32
%icmp1 = icmp eq i32 %ext, -1 %icmp1 = icmp eq i32 %ext, -1
store i1 %icmp1, i1 addrspace(1)* %out store i1 %icmp1, i1 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}sext_bool_icmp_ne_neg1: ; FUNC-LABEL: {{^}}sext_bool_icmp_ne_neg1:
; GCN-NOT: v_cmp ; GCN-NOT: v_cmp
; GCN: v_cmp_eq_u32_e32 vcc, ; GCN: s_cmp_eq_u32
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc ; GCN: s_cselect_b64 [[CC:[^,]+]], -1, 0
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CC]]
; GCN-NEXT: buffer_store_byte [[RESULT]] ; GCN-NEXT: buffer_store_byte [[RESULT]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @sext_bool_icmp_ne_neg1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { define amdgpu_kernel void @sext_bool_icmp_ne_neg1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%icmp0 = icmp ne i32 %a, %b %icmp0 = icmp ne i32 %a, %b
%ext = sext i1 %icmp0 to i32 %ext = sext i1 %icmp0 to i32
%icmp1 = icmp ne i32 %ext, -1 %icmp1 = icmp ne i32 %ext, -1
store i1 %icmp1, i1 addrspace(1)* %out store i1 %icmp1, i1 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}zext_bool_icmp_eq_0: ; FUNC-LABEL: {{^}}zext_bool_icmp_eq_0:
; GCN-NOT: v_cmp ; GCN-NOT: v_cmp
; GCN: v_cmp_ne_u32_e32 vcc, ; GCN: s_cmp_lg_u32
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc ; GCN: s_cselect_b64 [[CC:[^,]+]], -1, 0
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CC]]
; GCN-NEXT: buffer_store_byte [[RESULT]] ; GCN-NEXT: buffer_store_byte [[RESULT]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @zext_bool_icmp_eq_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { define amdgpu_kernel void @zext_bool_icmp_eq_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%icmp0 = icmp eq i32 %a, %b %icmp0 = icmp eq i32 %a, %b
%ext = zext i1 %icmp0 to i32 %ext = zext i1 %icmp0 to i32
%icmp1 = icmp eq i32 %ext, 0 %icmp1 = icmp eq i32 %ext, 0
store i1 %icmp1, i1 addrspace(1)* %out store i1 %icmp1, i1 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}zext_bool_icmp_ne_0: ; FUNC-LABEL: {{^}}zext_bool_icmp_ne_0:
; GCN-NOT: v_cmp ; GCN-NOT: v_cmp
; GCN: v_cmp_ne_u32_e32 vcc, ; GCN: s_cmp_lg_u32
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc ; GCN: s_cselect_b64 [[CC:[^,]+]], -1, 0
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CC]]
; GCN-NEXT: buffer_store_byte [[RESULT]] ; GCN-NEXT: buffer_store_byte [[RESULT]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @zext_bool_icmp_ne_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { define amdgpu_kernel void @zext_bool_icmp_ne_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%icmp0 = icmp ne i32 %a, %b %icmp0 = icmp ne i32 %a, %b
%ext = zext i1 %icmp0 to i32 %ext = zext i1 %icmp0 to i32
%icmp1 = icmp ne i32 %ext, 0 %icmp1 = icmp ne i32 %ext, 0
store i1 %icmp1, i1 addrspace(1)* %out store i1 %icmp1, i1 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}zext_bool_icmp_eq_1: ; FUNC-LABEL: {{^}}zext_bool_icmp_eq_1:
; GCN-NOT: v_cmp ; GCN-NOT: v_cmp
; GCN: v_cmp_eq_u32_e32 vcc, ; GCN: s_cmp_eq_u32
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc ; GCN: s_cselect_b64 [[CC:[^,]+]], -1, 0
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CC]]
; GCN-NEXT: buffer_store_byte [[RESULT]] ; GCN-NEXT: buffer_store_byte [[RESULT]]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @zext_bool_icmp_eq_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { define amdgpu_kernel void @zext_bool_icmp_eq_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%icmp0 = icmp eq i32 %a, %b %icmp0 = icmp eq i32 %a, %b
%ext = zext i1 %icmp0 to i32 %ext = zext i1 %icmp0 to i32
%icmp1 = icmp eq i32 %ext, 1 %icmp1 = icmp eq i32 %ext, 1
store i1 %icmp1, i1 addrspace(1)* %out store i1 %icmp1, i1 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}zext_bool_icmp_ne_1: ; FUNC-LABEL: {{^}}zext_bool_icmp_ne_1:
; GCN-NOT: v_cmp ; GCN-NOT: v_cmp
; GCN: v_cmp_eq_u32_e32 vcc, ; GCN: s_cmp_eq_u32
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc ; GCN: s_cselect_b64 [[CC:[^,]+]], -1, 0
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CC]]
; GCN-NEXT: buffer_store_byte [[RESULT]] ; GCN-NEXT: buffer_store_byte [[RESULT]]
define amdgpu_kernel void @zext_bool_icmp_ne_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { define amdgpu_kernel void @zext_bool_icmp_ne_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%icmp0 = icmp ne i32 %a, %b %icmp0 = icmp ne i32 %a, %b
%ext = zext i1 %icmp0 to i32 %ext = zext i1 %icmp0 to i32
%icmp1 = icmp ne i32 %ext, 1 %icmp1 = icmp ne i32 %ext, 1
store i1 %icmp1, i1 addrspace(1)* %out store i1 %icmp1, i1 addrspace(1)* %out
ret void ret void
} }
Show All 23 Linesdefine amdgpu_kernel void @zext_bool_icmp_ne_neg1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
store i1 %icmp1, i1 addrspace(1)* %out store i1 %icmp1, i1 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}cmp_zext_k_i8max: ; FUNC-LABEL: {{^}}cmp_zext_k_i8max:
; SI: s_load_dword [[VALUE:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SI: s_load_dword [[VALUE:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
; VI: s_load_dword [[VALUE:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c ; VI: s_load_dword [[VALUE:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
; GCN: s_movk_i32 [[K255:s[0-9]+]], 0xff ; GCN: s_movk_i32 [[K255:s[0-9]+]], 0xff
; GCN-DAG: v_mov_b32_e32 [[VK255:v[0-9]+]], [[K255]]
; SI-DAG: s_and_b32 [[B:s[0-9]+]], [[VALUE]], [[K255]] ; SI-DAG: s_and_b32 [[B:s[0-9]+]], [[VALUE]], [[K255]]
; SI: v_cmp_ne_u32_e32 vcc, [[B]], [[VK255]] ; SI: s_cmp_lg_u32 [[B]], [[K255]]
; SI: s_cselect_b64 [[CC:[^,]+]], -1, 0
; VI-DAG: v_and_b32_e32 [[B:v[0-9]+]], [[VALUE]], [[VK255]] ; VI: v_mov_b32_e32 [[VK255:v[0-9]+]], [[K255]]
; VI: v_and_b32_e32 [[B:v[0-9]+]], [[VALUE]], [[VK255]]
; VI: v_cmp_ne_u16_e32 vcc, [[K255]], [[B]] ; VI: v_cmp_ne_u16_e32 vcc, [[K255]], [[B]]
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CC]]
; VI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
; GCN: buffer_store_byte [[RESULT]] ; GCN: buffer_store_byte [[RESULT]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @cmp_zext_k_i8max(i1 addrspace(1)* %out, i8 %b) nounwind { define amdgpu_kernel void @cmp_zext_k_i8max(i1 addrspace(1)* %out, i8 %b) nounwind {
%b.ext = zext i8 %b to i32 %b.ext = zext i8 %b to i32
%icmp0 = icmp ne i32 %b.ext, 255 %icmp0 = icmp ne i32 %b.ext, 255
store i1 %icmp0, i1 addrspace(1)* %out store i1 %icmp0, i1 addrspace(1)* %out
ret void ret void
} }
Show All 27 Lines
; 255. Seems to be because of ordering problems when not allowing load widths to be reduced. ; 255. Seems to be because of ordering problems when not allowing load widths to be reduced.
; Should do a buffer_load_sbyte and compare with -1 ; Should do a buffer_load_sbyte and compare with -1
; FUNC-LABEL: {{^}}cmp_sext_k_neg1_i8_arg: ; FUNC-LABEL: {{^}}cmp_sext_k_neg1_i8_arg:
; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb ; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
; VI: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c ; VI: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
; GCN: s_movk_i32 [[K:s[0-9]+]], 0xff ; GCN: s_movk_i32 [[K:s[0-9]+]], 0xff
; GCN-DAG: s_and_b32 [[B:s[0-9]+]], [[VAL]], [[K]] ; GCN-DAG: s_and_b32 [[B:s[0-9]+]], [[VAL]], [[K]]
; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], [[K]] ; GCN: s_cmp_lg_u32 [[B]], [[K]]{{$}}
; GCN: v_cmp_ne_u32_e32 vcc, [[B]], [[VK]]{{$}} ; GCN: s_cselect_b64 [[CC:[^,]+]], -1, 0
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CC]]
; GCN: buffer_store_byte [[RESULT]] ; GCN: buffer_store_byte [[RESULT]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @cmp_sext_k_neg1_i8_arg(i1 addrspace(1)* %out, i8 %b) nounwind { define amdgpu_kernel void @cmp_sext_k_neg1_i8_arg(i1 addrspace(1)* %out, i8 %b) nounwind {
%b.ext = sext i8 %b to i32 %b.ext = sext i8 %b to i32
%icmp0 = icmp ne i32 %b.ext, -1 %icmp0 = icmp ne i32 %b.ext, -1
store i1 %icmp0, i1 addrspace(1)* %out store i1 %icmp0, i1 addrspace(1)* %out
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/setcc.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=R600 -check-prefix=FUNC %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
; FUNC-LABEL: {{^}}setcc_v2i32: ; FUNC-LABEL: {{^}}setcc_v2i32:
; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[3].X, KC0[3].Z ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[3].X, KC0[3].Z
; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[2].W, KC0[3].Y ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[2].W, KC0[3].Y
; GCN: v_cmp_eq_u32_e32 ; GCN: s_cmp_eq_u32
; GCN: v_cmp_eq_u32_e32 ; GCN: s_cmp_eq_u32
define amdgpu_kernel void @setcc_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) #0 { define amdgpu_kernel void @setcc_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) #0 {
%result = icmp eq <2 x i32> %a, %b %result = icmp eq <2 x i32> %a, %b
%sext = sext <2 x i1> %result to <2 x i32> %sext = sext <2 x i1> %result to <2 x i32>
store <2 x i32> %sext, <2 x i32> addrspace(1)* %out store <2 x i32> %sext, <2 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}setcc_v4i32: ; FUNC-LABEL: {{^}}setcc_v4i32:
; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; GCN: v_cmp_eq_u32_e32 ; GCN: s_cmp_eq_u32
; GCN: v_cmp_eq_u32_e32 ; GCN: s_cmp_eq_u32
; GCN: v_cmp_eq_u32_e32 ; GCN: s_cmp_eq_u32
; GCN: v_cmp_eq_u32_e32 ; GCN: s_cmp_eq_u32
define amdgpu_kernel void @setcc_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @setcc_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 {
%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
%a = load <4 x i32>, <4 x i32> addrspace(1)* %in %a = load <4 x i32>, <4 x i32> addrspace(1)* %in
%b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr %b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
%result = icmp eq <4 x i32> %a, %b %result = icmp eq <4 x i32> %a, %b
%sext = sext <4 x i1> %result to <4 x i32> %sext = sext <4 x i1> %result to <4 x i32>
store <4 x i32> %sext, <4 x i32> addrspace(1)* %out store <4 x i32> %sext, <4 x i32> addrspace(1)* %out
ret void ret void
▲ Show 20 Lines • Show All 185 Lines • ▼ Show 20 Lines
} }
;;;==========================================================================;;; ;;;==========================================================================;;;
;; 32-bit integer comparisons ;; 32-bit integer comparisons
;;;==========================================================================;;; ;;;==========================================================================;;;
; FUNC-LABEL: {{^}}i32_eq: ; FUNC-LABEL: {{^}}i32_eq:
; R600: SETE_INT ; R600: SETE_INT
; GCN: v_cmp_eq_u32 ; GCN: s_cmp_eq_u32
define amdgpu_kernel void @i32_eq(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { define amdgpu_kernel void @i32_eq(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
entry: entry:
%0 = icmp eq i32 %a, %b %0 = icmp eq i32 %a, %b
%1 = sext i1 %0 to i32 %1 = sext i1 %0 to i32
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}i32_ne: ; FUNC-LABEL: {{^}}i32_ne:
; R600: SETNE_INT ; R600: SETNE_INT
; GCN: v_cmp_ne_u32 ; GCN: s_cmp_lg_u32
define amdgpu_kernel void @i32_ne(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { define amdgpu_kernel void @i32_ne(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
entry: entry:
%0 = icmp ne i32 %a, %b %0 = icmp ne i32 %a, %b
%1 = sext i1 %0 to i32 %1 = sext i1 %0 to i32
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}i32_ugt: ; FUNC-LABEL: {{^}}i32_ugt:
; R600: SETGT_UINT ; R600: SETGT_UINT
; GCN: v_cmp_gt_u32 ; GCN: s_cmp_gt_u32
define amdgpu_kernel void @i32_ugt(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { define amdgpu_kernel void @i32_ugt(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
entry: entry:
%0 = icmp ugt i32 %a, %b %0 = icmp ugt i32 %a, %b
%1 = sext i1 %0 to i32 %1 = sext i1 %0 to i32
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}i32_uge: ; FUNC-LABEL: {{^}}i32_uge:
; R600: SETGE_UINT ; R600: SETGE_UINT
; GCN: v_cmp_ge_u32 ; GCN: s_cmp_ge_u32
define amdgpu_kernel void @i32_uge(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { define amdgpu_kernel void @i32_uge(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
entry: entry:
%0 = icmp uge i32 %a, %b %0 = icmp uge i32 %a, %b
%1 = sext i1 %0 to i32 %1 = sext i1 %0 to i32
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}i32_ult: ; FUNC-LABEL: {{^}}i32_ult:
; R600: SETGT_UINT ; R600: SETGT_UINT
; GCN: v_cmp_lt_u32 ; GCN: s_cmp_lt_u32
define amdgpu_kernel void @i32_ult(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { define amdgpu_kernel void @i32_ult(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
entry: entry:
%0 = icmp ult i32 %a, %b %0 = icmp ult i32 %a, %b
%1 = sext i1 %0 to i32 %1 = sext i1 %0 to i32
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}i32_ule: ; FUNC-LABEL: {{^}}i32_ule:
; R600: SETGE_UINT ; R600: SETGE_UINT
; GCN: v_cmp_le_u32 ; GCN: s_cmp_le_u32
define amdgpu_kernel void @i32_ule(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { define amdgpu_kernel void @i32_ule(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
entry: entry:
%0 = icmp ule i32 %a, %b %0 = icmp ule i32 %a, %b
%1 = sext i1 %0 to i32 %1 = sext i1 %0 to i32
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}i32_sgt: ; FUNC-LABEL: {{^}}i32_sgt:
; R600: SETGT_INT ; R600: SETGT_INT
; GCN: v_cmp_gt_i32 ; GCN: s_cmp_gt_i32
define amdgpu_kernel void @i32_sgt(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { define amdgpu_kernel void @i32_sgt(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
entry: entry:
%0 = icmp sgt i32 %a, %b %0 = icmp sgt i32 %a, %b
%1 = sext i1 %0 to i32 %1 = sext i1 %0 to i32
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}i32_sge: ; FUNC-LABEL: {{^}}i32_sge:
; R600: SETGE_INT ; R600: SETGE_INT
; GCN: v_cmp_ge_i32 ; GCN: s_cmp_ge_i32
define amdgpu_kernel void @i32_sge(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { define amdgpu_kernel void @i32_sge(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
entry: entry:
%0 = icmp sge i32 %a, %b %0 = icmp sge i32 %a, %b
%1 = sext i1 %0 to i32 %1 = sext i1 %0 to i32
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}i32_slt: ; FUNC-LABEL: {{^}}i32_slt:
; R600: SETGT_INT ; R600: SETGT_INT
; GCN: v_cmp_lt_i32 ; GCN: s_cmp_lt_i32
define amdgpu_kernel void @i32_slt(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { define amdgpu_kernel void @i32_slt(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
entry: entry:
%0 = icmp slt i32 %a, %b %0 = icmp slt i32 %a, %b
%1 = sext i1 %0 to i32 %1 = sext i1 %0 to i32
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}i32_sle: ; FUNC-LABEL: {{^}}i32_sle:
; R600: SETGE_INT ; R600: SETGE_INT
; GCN: v_cmp_le_i32 ; GCN: s_cmp_le_i32
define amdgpu_kernel void @i32_sle(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { define amdgpu_kernel void @i32_sle(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
entry: entry:
%0 = icmp sle i32 %a, %b %0 = icmp sle i32 %a, %b
%1 = sext i1 %0 to i32 %1 = sext i1 %0 to i32
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Linesbb1:
store i32 0, i32 addrspace(1)* %out store i32 0, i32 addrspace(1)* %out
br label %bb2 br label %bb2
bb2: bb2:
ret void ret void
} }
; FUNC-LABEL: setcc_v2i32_expand ; FUNC-LABEL: setcc_v2i32_expand
; GCN: v_cmp_gt_i32 ; GCN: s_cmp_gt_i32
; GCN: v_cmp_gt_i32 ; GCN: s_cmp_gt_i32
define amdgpu_kernel void @setcc_v2i32_expand( define amdgpu_kernel void @setcc_v2i32_expand(
<2 x i32> addrspace(1)* %a, <2 x i32> addrspace(1)* %a,
<2 x i32> addrspace(1)* %b, <2 x i32> addrspace(1)* %b,
<2 x i32> addrspace(1)* %c, <2 x i32> addrspace(1)* %c,
<2 x float> addrspace(1)* %r) { <2 x float> addrspace(1)* %r) {
entry: entry:
%a.val = load <2 x i32>, <2 x i32> addrspace(1)* %a %a.val = load <2 x i32>, <2 x i32> addrspace(1)* %a
%b.val = load <2 x i32>, <2 x i32> addrspace(1)* %b %b.val = load <2 x i32>, <2 x i32> addrspace(1)* %b
%c.val = load <2 x i32>, <2 x i32> addrspace(1)* %c %c.val = load <2 x i32>, <2 x i32> addrspace(1)* %c
%icmp.val.1 = icmp sgt <2 x i32> %a.val, <i32 1, i32 1> %icmp.val.1 = icmp sgt <2 x i32> %a.val, <i32 1, i32 1>
%zext.val.1 = zext <2 x i1> %icmp.val.1 to <2 x i32> %zext.val.1 = zext <2 x i1> %icmp.val.1 to <2 x i32>
%shl.val.1 = shl nuw <2 x i32> %zext.val.1, <i32 31, i32 31> %shl.val.1 = shl nuw <2 x i32> %zext.val.1, <i32 31, i32 31>
%xor.val.1 = xor <2 x i32> %shl.val.1, %b.val %xor.val.1 = xor <2 x i32> %shl.val.1, %b.val
%bitcast.val.1 = bitcast <2 x i32> %xor.val.1 to <2 x float> %bitcast.val.1 = bitcast <2 x i32> %xor.val.1 to <2 x float>
%icmp.val.2 = icmp sgt <2 x i32> %c.val, <i32 1199570944, i32 1199570944> %icmp.val.2 = icmp sgt <2 x i32> %c.val, <i32 1199570944, i32 1199570944>
%select.val.1 = select <2 x i1> %icmp.val.2, <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float> %bitcast.val.1 %select.val.1 = select <2 x i1> %icmp.val.2, <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float> %bitcast.val.1
store <2 x float> %select.val.1, <2 x float> addrspace(1)* %r store <2 x float> %select.val.1, <2 x float> addrspace(1)* %r
ret void ret void
} }
; FUNC-LABEL: setcc_v4i32_expand ; FUNC-LABEL: setcc_v4i32_expand
; GCN: v_cmp_gt_i32 ; GCN: s_cmp_gt_i32
; GCN: v_cmp_gt_i32 ; GCN: s_cmp_gt_i32
; GCN: v_cmp_gt_i32 ; GCN: s_cmp_gt_i32
; GCN: v_cmp_gt_i32 ; GCN: s_cmp_gt_i32
define amdgpu_kernel void @setcc_v4i32_expand( define amdgpu_kernel void @setcc_v4i32_expand(
<4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %a,
<4 x i32> addrspace(1)* %b, <4 x i32> addrspace(1)* %b,
<4 x i32> addrspace(1)* %c, <4 x i32> addrspace(1)* %c,
<4 x float> addrspace(1)* %r) { <4 x float> addrspace(1)* %r) {
entry: entry:
%a.val = load <4 x i32>, <4 x i32> addrspace(1)* %a %a.val = load <4 x i32>, <4 x i32> addrspace(1)* %a
%b.val = load <4 x i32>, <4 x i32> addrspace(1)* %b %b.val = load <4 x i32>, <4 x i32> addrspace(1)* %b
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llvm/test/CodeGen/AMDGPU/setcc64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s| FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s| FileCheck -check-prefixes=GCN,SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
; XXX: Merge this into setcc, once R600 supports 64-bit operations ; XXX: Merge this into setcc, once R600 supports 64-bit operations
;;;==========================================================================;;; ;;;==========================================================================;;;
;; Double comparisons ;; Double comparisons
;;;==========================================================================;;; ;;;==========================================================================;;;
; GCN-LABEL: {{^}}f64_oeq: ; GCN-LABEL: {{^}}f64_oeq:
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ret void ret void
} }
;;;==========================================================================;;; ;;;==========================================================================;;;
;; 64-bit integer comparisons ;; 64-bit integer comparisons
;;;==========================================================================;;; ;;;==========================================================================;;;
; GCN-LABEL: {{^}}i64_eq: ; GCN-LABEL: {{^}}i64_eq:
; GCN: v_cmp_eq_u64 ; SI: v_cmp_eq_u64
; VI: s_cmp_eq_u64
define amdgpu_kernel void @i64_eq(i32 addrspace(1)* %out, i64 %a, i64 %b) #0 { define amdgpu_kernel void @i64_eq(i32 addrspace(1)* %out, i64 %a, i64 %b) #0 {
entry: entry:
%tmp0 = icmp eq i64 %a, %b %tmp0 = icmp eq i64 %a, %b
%tmp1 = sext i1 %tmp0 to i32 %tmp1 = sext i1 %tmp0 to i32
store i32 %tmp1, i32 addrspace(1)* %out store i32 %tmp1, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}i64_ne: ; GCN-LABEL: {{^}}i64_ne:
; GCN: v_cmp_ne_u64 ; SI: v_cmp_ne_u64
; VI: s_cmp_lg_u64
define amdgpu_kernel void @i64_ne(i32 addrspace(1)* %out, i64 %a, i64 %b) #0 { define amdgpu_kernel void @i64_ne(i32 addrspace(1)* %out, i64 %a, i64 %b) #0 {
entry: entry:
%tmp0 = icmp ne i64 %a, %b %tmp0 = icmp ne i64 %a, %b
%tmp1 = sext i1 %tmp0 to i32 %tmp1 = sext i1 %tmp0 to i32
store i32 %tmp1, i32 addrspace(1)* %out store i32 %tmp1, i32 addrspace(1)* %out
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/shift-i128.ll

Show First 20 Lines • Show All 185 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0 ; GCN-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0
; GCN-NEXT: v_mov_b32_e32 v4, 0 ; GCN-NEXT: v_mov_b32_e32 v4, 0
; GCN-NEXT: v_mov_b32_e32 v5, 0 ; GCN-NEXT: v_mov_b32_e32 v5, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_sub_i32 s9, 64, s8 ; GCN-NEXT: s_sub_i32 s9, 64, s8
; GCN-NEXT: s_sub_i32 s2, s8, 64 ; GCN-NEXT: s_sub_i32 s2, s8, 64
; GCN-NEXT: s_lshl_b64 s[0:1], s[6:7], s8 ; GCN-NEXT: s_lshl_b64 s[0:1], s[6:7], s8
; GCN-NEXT: s_lshr_b64 s[10:11], s[4:5], s9 ; GCN-NEXT: s_lshr_b64 s[10:11], s[4:5], s9
; GCN-NEXT: s_or_b64 s[10:11], s[0:1], s[10:11]
; GCN-NEXT: s_lshl_b64 s[2:3], s[4:5], s2 ; GCN-NEXT: s_lshl_b64 s[2:3], s[4:5], s2
; GCN-NEXT: s_or_b64 s[10:11], s[0:1], s[10:11]
; GCN-NEXT: s_cmp_lt_u32 s8, 64
; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_eq_u32 s8, 0
; GCN-NEXT: v_mov_b32_e32 v0, s3 ; GCN-NEXT: v_mov_b32_e32 v0, s3
; GCN-NEXT: v_mov_b32_e32 v1, s11 ; GCN-NEXT: v_mov_b32_e32 v1, s11
; GCN-NEXT: v_cmp_lt_u32_e64 vcc, s8, 64
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GCN-NEXT: v_mov_b32_e32 v1, s7 ; GCN-NEXT: v_mov_b32_e32 v1, s7
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s8, 0 ; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0
; GCN-NEXT: v_cndmask_b32_e64 v3, v0, v1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v3, v0, v1, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v0, s2 ; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: v_mov_b32_e32 v1, s10 ; GCN-NEXT: v_mov_b32_e32 v1, s10
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GCN-NEXT: v_mov_b32_e32 v1, s6 ; GCN-NEXT: v_mov_b32_e32 v1, s6
; GCN-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1]
; GCN-NEXT: s_lshl_b64 s[0:1], s[4:5], s8 ; GCN-NEXT: s_lshl_b64 s[0:1], s[4:5], s8
; GCN-NEXT: v_mov_b32_e32 v0, s1 ; GCN-NEXT: v_mov_b32_e32 v0, s1
Show All 15 Lines
; GCN-NEXT: v_mov_b32_e32 v5, 0 ; GCN-NEXT: v_mov_b32_e32 v5, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_sub_i32 s9, 64, s8 ; GCN-NEXT: s_sub_i32 s9, 64, s8
; GCN-NEXT: s_sub_i32 s2, s8, 64 ; GCN-NEXT: s_sub_i32 s2, s8, 64
; GCN-NEXT: s_lshr_b64 s[0:1], s[4:5], s8 ; GCN-NEXT: s_lshr_b64 s[0:1], s[4:5], s8
; GCN-NEXT: s_lshl_b64 s[10:11], s[6:7], s9 ; GCN-NEXT: s_lshl_b64 s[10:11], s[6:7], s9
; GCN-NEXT: s_or_b64 s[10:11], s[0:1], s[10:11] ; GCN-NEXT: s_or_b64 s[10:11], s[0:1], s[10:11]
; GCN-NEXT: s_lshr_b64 s[2:3], s[6:7], s2 ; GCN-NEXT: s_lshr_b64 s[2:3], s[6:7], s2
; GCN-NEXT: s_cmp_lt_u32 s8, 64
; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_eq_u32 s8, 0
; GCN-NEXT: v_mov_b32_e32 v0, s3 ; GCN-NEXT: v_mov_b32_e32 v0, s3
; GCN-NEXT: v_mov_b32_e32 v1, s11 ; GCN-NEXT: v_mov_b32_e32 v1, s11
; GCN-NEXT: v_cmp_lt_u32_e64 vcc, s8, 64
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GCN-NEXT: v_mov_b32_e32 v1, s5 ; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s8, 0 ; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0
; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v0, s2 ; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: v_mov_b32_e32 v2, s10 ; GCN-NEXT: v_mov_b32_e32 v2, s10
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GCN-NEXT: s_lshr_b64 s[0:1], s[6:7], s8 ; GCN-NEXT: s_lshr_b64 s[0:1], s[6:7], s8
; GCN-NEXT: v_mov_b32_e32 v2, s1 ; GCN-NEXT: v_mov_b32_e32 v2, s1
; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc
; GCN-NEXT: v_mov_b32_e32 v2, s0 ; GCN-NEXT: v_mov_b32_e32 v2, s0
; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
%shift = lshr i128 %lhs, %rhs %shift = lshr i128 %lhs, %rhs
store i128 %shift, i128 addrspace(1)* null store i128 %shift, i128 addrspace(1)* null
ret void ret void
} }
define amdgpu_kernel void @s_ashr_i128_ss(i128 %lhs, i128 %rhs) { define amdgpu_kernel void @s_ashr_i128_ss(i128 %lhs, i128 %rhs) {
; GCN-LABEL: s_ashr_i128_ss: ; GCN-LABEL: s_ashr_i128_ss:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0 ; GCN-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i64 s[0:1], s[6:7], s8
; GCN-NEXT: s_ashr_i32 s2, s7, 31 ; GCN-NEXT: s_ashr_i32 s2, s7, 31
; GCN-NEXT: v_mov_b32_e32 v2, s0 ; GCN-NEXT: s_ashr_i64 s[0:1], s[6:7], s8
; GCN-NEXT: s_sub_i32 s0, s8, 64 ; GCN-NEXT: s_cmp_lt_u32 s8, 64
; GCN-NEXT: v_mov_b32_e32 v0, s2 ; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
; GCN-NEXT: v_mov_b32_e32 v1, s0
; GCN-NEXT: s_sub_i32 s0, s8, 64
; GCN-NEXT: s_ashr_i64 s[2:3], s[6:7], s0 ; GCN-NEXT: s_ashr_i64 s[2:3], s[6:7], s0
; GCN-NEXT: s_sub_i32 s0, 64, s8 ; GCN-NEXT: s_sub_i32 s0, 64, s8
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: s_lshl_b64 s[0:1], s[6:7], s0 ; GCN-NEXT: s_lshl_b64 s[0:1], s[6:7], s0
; GCN-NEXT: s_lshr_b64 s[6:7], s[4:5], s8 ; GCN-NEXT: s_lshr_b64 s[6:7], s[4:5], s8
; GCN-NEXT: v_cmp_lt_u32_e64 vcc, s8, 64
; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[0:1] ; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc ; GCN-NEXT: s_cmp_eq_u32 s8, 0
; GCN-NEXT: v_mov_b32_e32 v0, s3 ; GCN-NEXT: v_mov_b32_e32 v0, s3
; GCN-NEXT: v_mov_b32_e32 v1, s7 ; GCN-NEXT: v_mov_b32_e32 v1, s7
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GCN-NEXT: v_mov_b32_e32 v1, s5 ; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s8, 0 ; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0
; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v0, s2 ; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: v_mov_b32_e32 v4, s6 ; GCN-NEXT: v_mov_b32_e32 v4, s6
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GCN-NEXT: v_mov_b32_e32 v6, s4 ; GCN-NEXT: v_mov_b32_e32 v6, s4
; GCN-NEXT: v_mov_b32_e32 v4, 0 ; GCN-NEXT: v_mov_b32_e32 v4, 0
; GCN-NEXT: v_mov_b32_e32 v5, 0 ; GCN-NEXT: v_mov_b32_e32 v5, 0
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1]
▲ Show 20 Lines • Show All 370 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: s_mov_b64 s[2:3], 0 ; SI-NEXT: s_mov_b64 s[2:3], 0
; SI-NEXT: s_mov_b64 s[4:5], 0 ; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_and_saveexec_b64 s[6:7], vcc ; SI-NEXT: s_and_saveexec_b64 s[6:7], vcc
; SI-NEXT: s_cbranch_execz BB1_2 ; SI-NEXT: s_cbranch_execz BB1_2
; SI-NEXT: ; %bb.1: ; %else ; SI-NEXT: ; %bb.1: ; %else
; SI-NEXT: s_load_dword s0, s[0:1], 0x9 ; SI-NEXT: s_load_dword s0, s[0:1], 0x9
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, 0 ; SI-NEXT: s_cmp_eq_u32 s0, 0
; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
; SI-NEXT: s_and_b64 s[4:5], s[0:1], exec ; SI-NEXT: s_and_b64 s[4:5], s[0:1], exec
; SI-NEXT: BB1_2: ; %endif ; SI-NEXT: BB1_2: ; %endif
; SI-NEXT: s_or_b64 exec, exec, s[6:7] ; SI-NEXT: s_or_b64 exec, exec, s[6:7]
; SI-NEXT: BB1_3: ; %loop ; SI-NEXT: BB1_3: ; %loop
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_and_b64 s[0:1], exec, s[4:5] ; SI-NEXT: s_and_b64 s[0:1], exec, s[4:5]
; SI-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3] ; SI-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3]
; SI-NEXT: s_andn2_b64 exec, exec, s[2:3] ; SI-NEXT: s_andn2_b64 exec, exec, s[2:3]
; SI-NEXT: s_cbranch_execnz BB1_3 ; SI-NEXT: s_cbranch_execnz BB1_3
; SI-NEXT: ; %bb.4: ; %exit ; SI-NEXT: ; %bb.4: ; %exit
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; FLAT-LABEL: phi_cond_outside_loop: ; FLAT-LABEL: phi_cond_outside_loop:
; FLAT: ; %bb.0: ; %entry ; FLAT: ; %bb.0: ; %entry
; FLAT-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0 ; FLAT-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
; FLAT-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; FLAT-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; FLAT-NEXT: s_mov_b64 s[2:3], 0 ; FLAT-NEXT: s_mov_b64 s[2:3], 0
; FLAT-NEXT: s_mov_b64 s[4:5], 0 ; FLAT-NEXT: s_mov_b64 s[4:5], 0
; FLAT-NEXT: s_and_saveexec_b64 s[6:7], vcc ; FLAT-NEXT: s_and_saveexec_b64 s[6:7], vcc
; FLAT-NEXT: s_cbranch_execz BB1_2 ; FLAT-NEXT: s_cbranch_execz BB1_2
; FLAT-NEXT: ; %bb.1: ; %else ; FLAT-NEXT: ; %bb.1: ; %else
; FLAT-NEXT: s_load_dword s0, s[0:1], 0x24 ; FLAT-NEXT: s_load_dword s0, s[0:1], 0x24
; FLAT-NEXT: s_waitcnt lgkmcnt(0) ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
; FLAT-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, 0 ; FLAT-NEXT: s_cmp_eq_u32 s0, 0
; FLAT-NEXT: s_cselect_b64 s[0:1], -1, 0
; FLAT-NEXT: s_and_b64 s[4:5], s[0:1], exec ; FLAT-NEXT: s_and_b64 s[4:5], s[0:1], exec
; FLAT-NEXT: BB1_2: ; %endif ; FLAT-NEXT: BB1_2: ; %endif
; FLAT-NEXT: s_or_b64 exec, exec, s[6:7] ; FLAT-NEXT: s_or_b64 exec, exec, s[6:7]
; FLAT-NEXT: BB1_3: ; %loop ; FLAT-NEXT: BB1_3: ; %loop
; FLAT-NEXT: ; =>This Inner Loop Header: Depth=1 ; FLAT-NEXT: ; =>This Inner Loop Header: Depth=1
; FLAT-NEXT: s_and_b64 s[0:1], exec, s[4:5] ; FLAT-NEXT: s_and_b64 s[0:1], exec, s[4:5]
; FLAT-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3] ; FLAT-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3]
; FLAT-NEXT: s_andn2_b64 exec, exec, s[2:3] ; FLAT-NEXT: s_andn2_b64 exec, exec, s[2:3]
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; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0 ; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0
; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SI-NEXT: s_load_dword s8, s[0:1], 0xc ; SI-NEXT: s_load_dword s8, s[0:1], 0xc
; SI-NEXT: s_brev_b32 s9, 44 ; SI-NEXT: s_brev_b32 s9, 44
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_cmp_lt_i32_e64 s[0:1], s2, 1 ; SI-NEXT: s_cmp_lt_i32 s2, 1
; SI-NEXT: v_cmp_lt_i32_e64 s[4:5], s3, 4 ; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
; SI-NEXT: v_cmp_gt_i32_e64 s[2:3], s3, 3 ; SI-NEXT: s_cmp_lt_i32 s3, 4
; SI-NEXT: s_and_b64 s[2:3], s[0:1], s[2:3] ; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
; SI-NEXT: s_and_b64 s[0:1], exec, s[4:5] ; SI-NEXT: s_cmp_gt_i32 s3, 3
; SI-NEXT: s_cselect_b64 s[2:3], -1, 0
; SI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
; SI-NEXT: s_and_b64 s[0:1], exec, s[0:1]
; SI-NEXT: s_and_b64 s[2:3], exec, s[2:3] ; SI-NEXT: s_and_b64 s[2:3], exec, s[2:3]
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s9 ; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s9
; SI-NEXT: s_and_b64 s[4:5], exec, s[4:5] ; SI-NEXT: s_and_b64 s[4:5], exec, s[4:5]
; SI-NEXT: v_mov_b32_e32 v0, 3 ; SI-NEXT: v_mov_b32_e32 v0, 3
; SI-NEXT: s_branch BB3_4 ; SI-NEXT: s_branch BB3_4
; SI-NEXT: BB3_1: ; %Flow6 ; SI-NEXT: BB3_1: ; %Flow6
; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
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; FLAT: ; %bb.0: ; %entry ; FLAT: ; %bb.0: ; %entry
; FLAT-NEXT: s_mov_b32 s7, 0xf000 ; FLAT-NEXT: s_mov_b32 s7, 0xf000
; FLAT-NEXT: s_mov_b32 s6, -1 ; FLAT-NEXT: s_mov_b32 s6, -1
; FLAT-NEXT: buffer_load_dword v0, off, s[4:7], 0 ; FLAT-NEXT: buffer_load_dword v0, off, s[4:7], 0
; FLAT-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; FLAT-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; FLAT-NEXT: s_load_dword s8, s[0:1], 0x30 ; FLAT-NEXT: s_load_dword s8, s[0:1], 0x30
; FLAT-NEXT: s_brev_b32 s9, 44 ; FLAT-NEXT: s_brev_b32 s9, 44
; FLAT-NEXT: s_waitcnt lgkmcnt(0) ; FLAT-NEXT: s_waitcnt lgkmcnt(0)
; FLAT-NEXT: v_cmp_lt_i32_e64 s[0:1], s2, 1 ; FLAT-NEXT: s_cmp_lt_i32 s2, 1
; FLAT-NEXT: v_cmp_lt_i32_e64 s[4:5], s3, 4 ; FLAT-NEXT: s_cselect_b64 s[4:5], -1, 0
; FLAT-NEXT: v_cmp_gt_i32_e64 s[2:3], s3, 3 ; FLAT-NEXT: s_cmp_lt_i32 s3, 4
; FLAT-NEXT: s_and_b64 s[2:3], s[0:1], s[2:3] ; FLAT-NEXT: s_cselect_b64 s[0:1], -1, 0
; FLAT-NEXT: s_and_b64 s[0:1], exec, s[4:5] ; FLAT-NEXT: s_cmp_gt_i32 s3, 3
; FLAT-NEXT: s_cselect_b64 s[2:3], -1, 0
; FLAT-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
; FLAT-NEXT: s_and_b64 s[0:1], exec, s[0:1]
; FLAT-NEXT: s_and_b64 s[2:3], exec, s[2:3] ; FLAT-NEXT: s_and_b64 s[2:3], exec, s[2:3]
; FLAT-NEXT: s_waitcnt vmcnt(0) ; FLAT-NEXT: s_waitcnt vmcnt(0)
; FLAT-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s9 ; FLAT-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s9
; FLAT-NEXT: s_and_b64 s[4:5], exec, s[4:5] ; FLAT-NEXT: s_and_b64 s[4:5], exec, s[4:5]
; FLAT-NEXT: v_mov_b32_e32 v0, 3 ; FLAT-NEXT: v_mov_b32_e32 v0, 3
; FLAT-NEXT: s_branch BB3_4 ; FLAT-NEXT: s_branch BB3_4
; FLAT-NEXT: BB3_1: ; %Flow6 ; FLAT-NEXT: BB3_1: ; %Flow6
; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
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llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck %s
define amdgpu_kernel void @test(i32 %arg, i32 %arg1) { define amdgpu_kernel void @test(i32 %arg, i32 %arg1) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: ; %bb.0: ; %bb ; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_cmp_eq_u32_e64 s[2:3], s0, 0 ; CHECK-NEXT: s_cmp_eq_u32 s0, 0
; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], s1, 0 ; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0
; CHECK-NEXT: s_cmp_eq_u32 s1, 0
; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0
; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] ; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1] ; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]
; CHECK-NEXT: s_cbranch_vccnz BB0_3 ; CHECK-NEXT: s_cbranch_vccnz BB0_3
; CHECK-NEXT: ; %bb.1: ; %bb9 ; CHECK-NEXT: ; %bb.1: ; %bb9
; CHECK-NEXT: s_and_b64 vcc, exec, 0 ; CHECK-NEXT: s_and_b64 vcc, exec, 0
; CHECK-NEXT: BB0_2: ; %bb10 ; CHECK-NEXT: BB0_2: ; %bb10
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_mov_b64 vcc, vcc ; CHECK-NEXT: s_mov_b64 vcc, vcc
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llvm/test/CodeGen/AMDGPU/sign_extend.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-- -amdgpu-scalarize-global-loads=false -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s -allow-deprecated-dag-overlap -enable-var-scope --check-prefix=SI ; RUN: llc -mtriple=amdgcn-- -amdgpu-scalarize-global-loads=false -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s -allow-deprecated-dag-overlap -enable-var-scope --check-prefix=SI
; RUN: llc -mtriple=amdgcn-- -amdgpu-scalarize-global-loads=false -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -allow-deprecated-dag-overlap -enable-var-scope --check-prefix=VI ; RUN: llc -mtriple=amdgcn-- -amdgpu-scalarize-global-loads=false -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -allow-deprecated-dag-overlap -enable-var-scope --check-prefix=VI
define amdgpu_kernel void @s_sext_i1_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { define amdgpu_kernel void @s_sext_i1_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
; SI-LABEL: s_sext_i1_to_i32: ; SI-LABEL: s_sext_i1_to_i32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s1 ; SI-NEXT: s_cmp_eq_u32 s0, s1
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v0 ; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: s_sext_i1_to_i32: ; VI-LABEL: s_sext_i1_to_i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
; VI-NEXT: s_mov_b32 s7, 0xf000 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s1 ; VI-NEXT: s_cmp_eq_u32 s0, s1
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v0 ; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%sext = sext i1 %cmp to i32 %sext = sext i1 %cmp to i32
store i32 %sext, i32 addrspace(1)* %out, align 4 store i32 %sext, i32 addrspace(1)* %out, align 4
ret void ret void
} }
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define amdgpu_kernel void @s_sext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind { define amdgpu_kernel void @s_sext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
; SI-LABEL: s_sext_i1_to_i64: ; SI-LABEL: s_sext_i1_to_i64:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s1 ; SI-NEXT: s_cmp_eq_u32 s0, s1
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v0 ; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]
; SI-NEXT: v_mov_b32_e32 v1, v0 ; SI-NEXT: v_mov_b32_e32 v1, v0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: s_sext_i1_to_i64: ; VI-LABEL: s_sext_i1_to_i64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
; VI-NEXT: s_mov_b32 s7, 0xf000 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s1 ; VI-NEXT: s_cmp_eq_u32 s0, s1
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v0 ; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]
; VI-NEXT: v_mov_b32_e32 v1, v0 ; VI-NEXT: v_mov_b32_e32 v1, v0
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%sext = sext i1 %cmp to i64 %sext = sext i1 %cmp to i64
store i64 %sext, i64 addrspace(1)* %out, align 8 store i64 %sext, i64 addrspace(1)* %out, align 8
ret void ret void
} }
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define amdgpu_kernel void @s_sext_i1_to_i16(i16 addrspace(1)* %out, i32 %a, i32 %b) nounwind { define amdgpu_kernel void @s_sext_i1_to_i16(i16 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
; SI-LABEL: s_sext_i1_to_i16: ; SI-LABEL: s_sext_i1_to_i16:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s1 ; SI-NEXT: s_cmp_eq_u32 s0, s1
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v0 ; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: s_sext_i1_to_i16: ; VI-LABEL: s_sext_i1_to_i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
; VI-NEXT: s_mov_b32 s7, 0xf000 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s1 ; VI-NEXT: s_cmp_eq_u32 s0, s1
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v0 ; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]
; VI-NEXT: buffer_store_short v0, off, s[4:7], 0 ; VI-NEXT: buffer_store_short v0, off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%sext = sext i1 %cmp to i16 %sext = sext i1 %cmp to i16
store i16 %sext, i16 addrspace(1)* %out store i16 %sext, i16 addrspace(1)* %out
ret void ret void
} }
; This purpose of this test is to make sure the i16 = sign_extend i1 node ; This purpose of this test is to make sure the i16 = sign_extend i1 node
; makes it all the way throught the legalizer/optimizer to make sure ; makes it all the way throught the legalizer/optimizer to make sure
; we select this correctly. In the s_sext_i1_to_i16, the sign_extend node ; we select this correctly. In the s_sext_i1_to_i16, the sign_extend node
; is optimized to a select very early. ; is optimized to a select very early.
define amdgpu_kernel void @s_sext_i1_to_i16_with_and(i16 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define amdgpu_kernel void @s_sext_i1_to_i16_with_and(i16 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; SI-LABEL: s_sext_i1_to_i16_with_and: ; SI-LABEL: s_sext_i1_to_i16_with_and:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s1 ; SI-NEXT: s_cmp_eq_u32 s0, s1
; SI-NEXT: v_mov_b32_e32 v1, s3 ; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v0 ; SI-NEXT: s_cmp_eq_u32 s2, s3
; SI-NEXT: v_cmp_eq_u32_e64 s[0:1], s2, v1 ; SI-NEXT: s_cselect_b64 s[2:3], -1, 0
; SI-NEXT: s_and_b64 s[0:1], vcc, s[0:1] ; SI-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]
; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: s_sext_i1_to_i16_with_and: ; VI-LABEL: s_sext_i1_to_i16_with_and:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c
; VI-NEXT: s_mov_b32 s7, 0xf000 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s1 ; VI-NEXT: s_cmp_eq_u32 s0, s1
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v0 ; VI-NEXT: s_cmp_eq_u32 s2, s3
; VI-NEXT: v_cmp_eq_u32_e64 s[0:1], s2, v1 ; VI-NEXT: s_cselect_b64 s[2:3], -1, 0
; VI-NEXT: s_and_b64 s[0:1], vcc, s[0:1] ; VI-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]
; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1] ; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]
; VI-NEXT: buffer_store_short v0, off, s[4:7], 0 ; VI-NEXT: buffer_store_short v0, off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%cmp0 = icmp eq i32 %a, %b %cmp0 = icmp eq i32 %a, %b
%cmp1 = icmp eq i32 %c, %d %cmp1 = icmp eq i32 %c, %d
%cmp = and i1 %cmp0, %cmp1 %cmp = and i1 %cmp0, %cmp1
%sext = sext i1 %cmp to i16 %sext = sext i1 %cmp to i16
store i16 %sext, i16 addrspace(1)* %out store i16 %sext, i16 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @v_sext_i1_to_i16_with_and(i16 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) nounwind { define amdgpu_kernel void @v_sext_i1_to_i16_with_and(i16 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) nounwind {
; SI-LABEL: v_sext_i1_to_i16_with_and: ; SI-LABEL: v_sext_i1_to_i16_with_and:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb ; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
; SI-NEXT: s_load_dword s0, s[0:1], 0xd ; SI-NEXT: s_load_dword s0, s[0:1], 0xd
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0 ; SI-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0
; SI-NEXT: v_mov_b32_e32 v0, s0 ; SI-NEXT: s_cmp_eq_u32 s3, s0
; SI-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v0 ; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
; SI-NEXT: s_and_b64 s[0:1], vcc, s[0:1] ; SI-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_sext_i1_to_i16_with_and: ; VI-LABEL: v_sext_i1_to_i16_with_and:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; VI-NEXT: s_load_dword s0, s[0:1], 0x34 ; VI-NEXT: s_load_dword s0, s[0:1], 0x34
; VI-NEXT: s_mov_b32 s7, 0xf000 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0 ; VI-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: s_cmp_eq_u32 s3, s0
; VI-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v0 ; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
; VI-NEXT: s_and_b64 s[0:1], vcc, s[0:1] ; VI-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1] ; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]
; VI-NEXT: buffer_store_short v0, off, s[4:7], 0 ; VI-NEXT: buffer_store_short v0, off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%cmp0 = icmp eq i32 %a, %tid %cmp0 = icmp eq i32 %a, %tid
%cmp1 = icmp eq i32 %b, %c %cmp1 = icmp eq i32 %b, %c
%cmp = and i1 %cmp0, %cmp1 %cmp = and i1 %cmp0, %cmp1
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llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll

Show All 16 Lines
; GCN-LABEL: {{^}}sint_to_fp_i1_f64: ; GCN-LABEL: {{^}}sint_to_fp_i1_f64:
; VI-DAG: s_cmp_eq_u32 ; VI-DAG: s_cmp_eq_u32
; VI-DAG: s_cselect_b32 s[[SSEL:[0-9]+]], 0xbff00000, 0 ; VI-DAG: s_cselect_b32 s[[SSEL:[0-9]+]], 0xbff00000, 0
; VI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; VI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; VI-DAG: v_mov_b32_e32 v[[SEL:[0-9]+]], s[[SSEL]] ; VI-DAG: v_mov_b32_e32 v[[SEL:[0-9]+]], s[[SSEL]]
; VI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[ZERO]]:[[SEL]]{{\]}} ; VI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[ZERO]]:[[SEL]]{{\]}}
; VI: s_endpgm ; VI: s_endpgm
; SI-DAG: v_cmp_eq_u32_e64 vcc, ; SI-DAG: s_cmp_eq_u32
; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}} ; SI-DAG: s_cselect_b64 vcc, -1, 0
; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}}, vcc
; SI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; SI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; SI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[ZERO]]:[[SEL]]{{\]}} ; SI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[ZERO]]:[[SEL]]{{\]}}
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @sint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) { define amdgpu_kernel void @sint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) {
%cmp = icmp eq i32 %in, 0 %cmp = icmp eq i32 %in, 0
%fp = sitofp i1 %cmp to double %fp = sitofp i1 %cmp to double
store double %fp, double addrspace(1)* %out, align 4 store double %fp, double addrspace(1)* %out, align 4
ret void ret void
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llvm/test/CodeGen/AMDGPU/sint_to_fp.ll

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_sint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 {
%out.gep = getelementptr <4 x float>, <4 x float> addrspace(1)* %out, i32 %tid %out.gep = getelementptr <4 x float>, <4 x float> addrspace(1)* %out, i32 %tid
%value = load <4 x i32>, <4 x i32> addrspace(1)* %in.gep %value = load <4 x i32>, <4 x i32> addrspace(1)* %in.gep
%result = sitofp <4 x i32> %value to <4 x float> %result = sitofp <4 x i32> %value to <4 x float>
store <4 x float> %result, <4 x float> addrspace(1)* %out.gep store <4 x float> %result, <4 x float> addrspace(1)* %out.gep
ret void ret void
} }
; FUNC-LABEL: {{^}}s_sint_to_fp_i1_f32: ; FUNC-LABEL: {{^}}s_sint_to_fp_i1_f32:
; SI: v_cmp_eq_u32_e64 [[CMP:s\[[0-9]+:[0-9]\]]], ; SI: s_cmp_eq_u32
; SI: s_cselect_b64 [[CMP:s\[[0-9]+:[0-9]\]]], -1, 0
; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]] ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]]
; SI: buffer_store_dword [[RESULT]], ; SI: buffer_store_dword [[RESULT]],
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @s_sint_to_fp_i1_f32(float addrspace(1)* %out, i32 %in) #0 { define amdgpu_kernel void @s_sint_to_fp_i1_f32(float addrspace(1)* %out, i32 %in) #0 {
%cmp = icmp eq i32 %in, 0 %cmp = icmp eq i32 %in, 0
%fp = uitofp i1 %cmp to float %fp = uitofp i1 %cmp to float
store float %fp, float addrspace(1)* %out store float %fp, float addrspace(1)* %out
ret void ret void
Show All 33 Lines

llvm/test/CodeGen/AMDGPU/skip-if-dead.ll

Show First 20 Lines • Show All 487 Lines • ▼ Show 20 Linesexit:
%phi = phi float [ 0.0, %entry ], [ %live.out, %bb ] %phi = phi float [ 0.0, %entry ], [ %live.out, %bb ]
store float %phi, float addrspace(1)* undef store float %phi, float addrspace(1)* undef
ret void ret void
} }
define amdgpu_ps float @test_kill_control_flow_return(i32 inreg %arg) #0 { define amdgpu_ps float @test_kill_control_flow_return(i32 inreg %arg) #0 {
; SI-LABEL: test_kill_control_flow_return: ; SI-LABEL: test_kill_control_flow_return:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], s0, 1 ; SI-NEXT: s_cmp_eq_u32 s0, 1
; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
; SI-NEXT: s_mov_b64 s[2:3], exec ; SI-NEXT: s_mov_b64 s[2:3], exec
; SI-NEXT: s_xor_b64 s[4:5], s[4:5], exec ; SI-NEXT: s_xor_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5] ; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5]
; SI-NEXT: s_cbranch_scc0 BB9_4 ; SI-NEXT: s_cbranch_scc0 BB9_4
; SI-NEXT: ; %bb.1: ; %entry ; SI-NEXT: ; %bb.1: ; %entry
; SI-NEXT: s_and_b64 exec, exec, s[2:3] ; SI-NEXT: s_and_b64 exec, exec, s[2:3]
; SI-NEXT: s_cmp_lg_u32 s0, 0 ; SI-NEXT: s_cmp_lg_u32 s0, 0
; SI-NEXT: v_mov_b32_e32 v0, 0 ; SI-NEXT: v_mov_b32_e32 v0, 0
Show All 19 Lines
; SI-NEXT: BB9_4: ; SI-NEXT: BB9_4:
; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: s_mov_b64 exec, 0
; SI-NEXT: exp null off, off, off, off done vm ; SI-NEXT: exp null off, off, off, off done vm
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; SI-NEXT: BB9_5: ; SI-NEXT: BB9_5:
; ;
; GFX10-WAVE64-LABEL: test_kill_control_flow_return: ; GFX10-WAVE64-LABEL: test_kill_control_flow_return:
; GFX10-WAVE64: ; %bb.0: ; %entry ; GFX10-WAVE64: ; %bb.0: ; %entry
; GFX10-WAVE64-NEXT: v_cmp_eq_u32_e64 s[4:5], s0, 1 ; GFX10-WAVE64-NEXT: s_cmp_eq_u32 s0, 1
; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec ; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec
; GFX10-WAVE64-NEXT: s_cselect_b64 s[4:5], -1, 0
; GFX10-WAVE64-NEXT: s_xor_b64 s[4:5], s[4:5], exec ; GFX10-WAVE64-NEXT: s_xor_b64 s[4:5], s[4:5], exec
; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5] ; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5]
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB9_4 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB9_4
; GFX10-WAVE64-NEXT: ; %bb.1: ; %entry ; GFX10-WAVE64-NEXT: ; %bb.1: ; %entry
; GFX10-WAVE64-NEXT: s_and_b64 exec, exec, s[2:3] ; GFX10-WAVE64-NEXT: s_and_b64 exec, exec, s[2:3]
; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 0
; GFX10-WAVE64-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-WAVE64-NEXT: s_cmp_lg_u32 s0, 0
; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB9_3 ; GFX10-WAVE64-NEXT: s_cbranch_scc0 BB9_3
Show All 18 Lines
; GFX10-WAVE64-NEXT: BB9_4: ; GFX10-WAVE64-NEXT: BB9_4:
; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0
; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm ; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm
; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: s_endpgm
; GFX10-WAVE64-NEXT: BB9_5: ; GFX10-WAVE64-NEXT: BB9_5:
; ;
; GFX10-WAVE32-LABEL: test_kill_control_flow_return: ; GFX10-WAVE32-LABEL: test_kill_control_flow_return:
; GFX10-WAVE32: ; %bb.0: ; %entry ; GFX10-WAVE32: ; %bb.0: ; %entry
; GFX10-WAVE32-NEXT: v_cmp_eq_u32_e64 s2, s0, 1 ; GFX10-WAVE32-NEXT: s_cmp_eq_u32 s0, 1
; GFX10-WAVE32-NEXT: s_mov_b32 s1, exec_lo ; GFX10-WAVE32-NEXT: s_mov_b32 s1, exec_lo
; GFX10-WAVE32-NEXT: s_cselect_b32 s2, -1, 0
; GFX10-WAVE32-NEXT: s_xor_b32 s2, s2, exec_lo ; GFX10-WAVE32-NEXT: s_xor_b32 s2, s2, exec_lo
; GFX10-WAVE32-NEXT: s_andn2_b32 s1, s1, s2 ; GFX10-WAVE32-NEXT: s_andn2_b32 s1, s1, s2
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB9_4 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB9_4
; GFX10-WAVE32-NEXT: ; %bb.1: ; %entry ; GFX10-WAVE32-NEXT: ; %bb.1: ; %entry
; GFX10-WAVE32-NEXT: s_and_b32 exec_lo, exec_lo, s1 ; GFX10-WAVE32-NEXT: s_and_b32 exec_lo, exec_lo, s1
; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 0
; GFX10-WAVE32-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-WAVE32-NEXT: s_cmp_lg_u32 s0, 0
; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB9_3 ; GFX10-WAVE32-NEXT: s_cbranch_scc0 BB9_3
▲ Show 20 Lines • Show All 920 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll

Show First 20 Lines • Show All 369 Lines • ▼ Show 20 Linesdefine amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x i32> inreg %userData) {
; CHECK: [[V_OR_B32_e32_64:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[V_OR_B32_e32_63]], [[V_ADD_U32_e32_28]], implicit $exec ; CHECK: [[V_OR_B32_e32_64:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[V_OR_B32_e32_63]], [[V_ADD_U32_e32_28]], implicit $exec
; CHECK: [[V_ADD_U32_e32_30:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 -593, [[BUFFER_LOAD_FORMAT_X_IDXEN]], implicit $exec ; CHECK: [[V_ADD_U32_e32_30:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 -593, [[BUFFER_LOAD_FORMAT_X_IDXEN]], implicit $exec
; CHECK: [[V_OR_B32_e32_65:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[V_OR_B32_e32_64]], [[V_ADD_U32_e32_29]], implicit $exec ; CHECK: [[V_OR_B32_e32_65:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[V_OR_B32_e32_64]], [[V_ADD_U32_e32_29]], implicit $exec
; CHECK: [[S_LOAD_DWORDX8_IMM:%[0-9]+]]:sgpr_256 = S_LOAD_DWORDX8_IMM undef %564:sreg_64, 0, 0 :: (load (s256) from `<8 x i32> addrspace(4)* undef`, addrspace 4) ; CHECK: [[S_LOAD_DWORDX8_IMM:%[0-9]+]]:sgpr_256 = S_LOAD_DWORDX8_IMM undef %564:sreg_64, 0, 0 :: (load (s256) from `<8 x i32> addrspace(4)* undef`, addrspace 4)
; CHECK: [[V_OR_B32_e32_66:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[V_OR_B32_e32_65]], [[V_ADD_U32_e32_30]], implicit $exec ; CHECK: [[V_OR_B32_e32_66:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[V_OR_B32_e32_65]], [[V_ADD_U32_e32_30]], implicit $exec
; CHECK: [[S_ADD_I32_24:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM8]], -594, implicit-def dead $scc ; CHECK: [[S_ADD_I32_24:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM8]], -594, implicit-def dead $scc
; CHECK: [[V_OR_B32_e32_67:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[S_ADD_I32_24]], [[V_OR_B32_e32_66]], implicit $exec ; CHECK: [[V_OR_B32_e32_67:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[S_ADD_I32_24]], [[V_OR_B32_e32_66]], implicit $exec
; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 0, [[V_OR_B32_e32_67]], implicit $exec ; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 0, [[V_OR_B32_e32_67]], implicit $exec
; CHECK: undef %691.sub3:vreg_128 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U32_e64_]], implicit $exec ; CHECK: undef %692.sub3:vreg_128 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U32_e64_]], implicit $exec
; CHECK: IMAGE_STORE_V4_V2_gfx10 %691, undef %578:vreg_64, [[S_LOAD_DWORDX8_IMM]], 15, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128) into custom "ImageResource") ; CHECK: IMAGE_STORE_V4_V2_gfx10 %692, undef %578:vreg_64, [[S_LOAD_DWORDX8_IMM]], 15, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128) into custom "ImageResource")
; CHECK: S_ENDPGM 0 ; CHECK: S_ENDPGM 0
.expVert: .expVert:
%0 = extractelement <31 x i32> %userData, i64 2 %0 = extractelement <31 x i32> %userData, i64 2
%1 = extractelement <31 x i32> %userData, i64 3 %1 = extractelement <31 x i32> %userData, i64 3
%2 = extractelement <31 x i32> %userData, i64 4 %2 = extractelement <31 x i32> %userData, i64 4
%3 = extractelement <31 x i32> %userData, i64 7 %3 = extractelement <31 x i32> %userData, i64 7
%4 = extractelement <31 x i32> %userData, i64 8 %4 = extractelement <31 x i32> %userData, i64 8
%5 = extractelement <31 x i32> %userData, i64 9 %5 = extractelement <31 x i32> %userData, i64 9
▲ Show 20 Lines • Show All 436 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/srem64.ll

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_srem: ; GCN-IR-LABEL: s_test_srem:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-IR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GCN-IR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0
; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GCN-IR-NEXT: s_add_i32 s10, s10, 32 ; GCN-IR-NEXT: s_add_i32 s10, s10, 32
; GCN-IR-NEXT: s_cmp_eq_u32 s3, 0
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6
; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3
; GCN-IR-NEXT: v_mov_b32_e32 v1, s10 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: s_flbit_i32_b32 s10, s6 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: v_mov_b32_e32 v0, s11
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0
; GCN-IR-NEXT: s_add_i32 s10, s10, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s11, s7
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s11
; GCN-IR-NEXT: v_mov_b32_e32 v1, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s10
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7
; GCN-IR-NEXT: s_cmp_eq_u32 s7, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v0, s9
; GCN-IR-NEXT: v_mov_b32_e32 v1, s8
; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0 ; GCN-IR-NEXT: v_subb_u32_e64 v1, s[8:9], 0, 0, vcc
; GCN-IR-NEXT: v_subb_u32_e64 v1, s[10:11], 0, 0, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_xor_b64 s[8:9], s[0:1], -1 ; GCN-IR-NEXT: s_xor_b64 s[8:9], s[0:1], -1
; GCN-IR-NEXT: s_and_b64 s[8:9], s[8:9], vcc ; GCN-IR-NEXT: s_and_b64 s[8:9], s[8:9], vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[8:9] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_vccz BB0_4 ; GCN-IR-NEXT: s_cbranch_vccz BB0_4
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0
▲ Show 20 Lines • Show All 871 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_mov_b32 s1, s0 ; GCN-IR-NEXT: s_mov_b32 s1, s0
; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[6:7], 31 ; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[6:7], 31
; GCN-IR-NEXT: s_mov_b32 s3, s2 ; GCN-IR-NEXT: s_mov_b32 s3, s2
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[2:3] ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[2:3]
; GCN-IR-NEXT: s_xor_b64 s[10:11], s[10:11], s[0:1] ; GCN-IR-NEXT: s_xor_b64 s[10:11], s[10:11], s[0:1]
; GCN-IR-NEXT: s_sub_u32 s8, s6, s2 ; GCN-IR-NEXT: s_sub_u32 s8, s6, s2
; GCN-IR-NEXT: s_subb_u32 s9, s7, s2 ; GCN-IR-NEXT: s_subb_u32 s9, s7, s2
; GCN-IR-NEXT: s_sub_u32 s10, s10, s0 ; GCN-IR-NEXT: s_sub_u32 s10, s10, s0
; GCN-IR-NEXT: s_flbit_i32_b32 s12, s10
; GCN-IR-NEXT: s_subb_u32 s11, s11, s0 ; GCN-IR-NEXT: s_subb_u32 s11, s11, s0
; GCN-IR-NEXT: s_add_i32 s12, s12, 32 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[10:11], 0
; GCN-IR-NEXT: s_flbit_i32_b32 s13, s11 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[8:9], 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s12 ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[6:7]
; GCN-IR-NEXT: s_flbit_i32_b32 s12, s8 ; GCN-IR-NEXT: s_flbit_i32_b32 s6, s10
; GCN-IR-NEXT: v_mov_b32_e32 v0, s13 ; GCN-IR-NEXT: s_add_i32 s6, s6, 32
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s11, 0 ; GCN-IR-NEXT: s_cmp_eq_u32 s11, 0
; GCN-IR-NEXT: s_add_i32 s12, s12, 32 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s6
; GCN-IR-NEXT: s_flbit_i32_b32 s13, s9 ; GCN-IR-NEXT: s_flbit_i32_b32 s6, s8
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s11
; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: s_add_i32 s6, s6, 32
; GCN-IR-NEXT: v_mov_b32_e32 v0, s7
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s9
; GCN-IR-NEXT: s_cmp_eq_u32 s9, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v0, s13 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7
; GCN-IR-NEXT: v_mov_b32_e32 v1, s12 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s6
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s9, 0 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3
; GCN-IR-NEXT: v_subb_u32_e64 v1, s[12:13], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v1, s[6:7], 0, 0, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[10:11], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[8:9], 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[6:7]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[0:1], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[0:1], -1
; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[6:7] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[6:7]
; GCN-IR-NEXT: s_cbranch_vccz BB8_4 ; GCN-IR-NEXT: s_cbranch_vccz BB8_4
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0
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; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 ; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_srem24_48: ; GCN-IR-LABEL: s_test_srem24_48:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xb ; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xb
; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xc ; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xc
; GCN-IR-NEXT: s_load_dword s6, s[0:1], 0xd ; GCN-IR-NEXT: s_load_dword s4, s[0:1], 0xd
; GCN-IR-NEXT: s_load_dword s0, s[0:1], 0xe ; GCN-IR-NEXT: s_load_dword s5, s[0:1], 0xe
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_sext_i32_i16 s3, s3 ; GCN-IR-NEXT: s_sext_i32_i16 s3, s3
; GCN-IR-NEXT: s_sext_i32_i16 s7, s0 ; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[2:3], 24
; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[2:3], 24 ; GCN-IR-NEXT: s_sext_i32_i16 s5, s5
; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31 ; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31
; GCN-IR-NEXT: s_ashr_i32 s10, s7, 31 ; GCN-IR-NEXT: s_ashr_i32 s10, s5, 31
; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[4:5], 24
; GCN-IR-NEXT: s_mov_b32 s3, s2 ; GCN-IR-NEXT: s_mov_b32 s3, s2
; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[6:7], 24
; GCN-IR-NEXT: s_mov_b32 s11, s10 ; GCN-IR-NEXT: s_mov_b32 s11, s10
; GCN-IR-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3] ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[6:7], s[2:3]
; GCN-IR-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11] ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[10:11]
; GCN-IR-NEXT: s_sub_u32 s6, s0, s2 ; GCN-IR-NEXT: s_sub_u32 s4, s4, s2
; GCN-IR-NEXT: s_subb_u32 s7, s1, s2 ; GCN-IR-NEXT: s_subb_u32 s5, s5, s2
; GCN-IR-NEXT: s_sub_u32 s8, s8, s10 ; GCN-IR-NEXT: s_sub_u32 s6, s6, s10
; GCN-IR-NEXT: s_flbit_i32_b32 s12, s8 ; GCN-IR-NEXT: s_subb_u32 s7, s7, s10
; GCN-IR-NEXT: s_subb_u32 s9, s9, s10 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
; GCN-IR-NEXT: s_add_i32 s12, s12, 32 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[4:5], 0
; GCN-IR-NEXT: s_flbit_i32_b32 s13, s9 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v1, s12 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6
; GCN-IR-NEXT: s_flbit_i32_b32 s12, s6 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: v_mov_b32_e32 v0, s13 ; GCN-IR-NEXT: s_cmp_eq_u32 s7, 0
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s8
; GCN-IR-NEXT: s_add_i32 s12, s12, 32 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s4
; GCN-IR-NEXT: s_flbit_i32_b32 s13, s7 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7
; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: v_mov_b32_e32 v0, s9
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s5
; GCN-IR-NEXT: s_cmp_eq_u32 s5, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v0, s13 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s9
; GCN-IR-NEXT: v_mov_b32_e32 v1, s12 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s8
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3
; GCN-IR-NEXT: v_subb_u32_e64 v1, s[12:13], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v1, s[8:9], 0, 0, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[8:9], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11] ; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc ; GCN-IR-NEXT: s_or_b64 s[0:1], s[10:11], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_xor_b64 s[10:11], s[0:1], -1 ; GCN-IR-NEXT: s_xor_b64 s[10:11], s[0:1], -1
; GCN-IR-NEXT: s_and_b64 s[10:11], s[10:11], vcc ; GCN-IR-NEXT: s_and_b64 s[10:11], s[10:11], vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[10:11] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[10:11]
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_mov_b64 vcc, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB9_4 ; GCN-IR-NEXT: s_cbranch_vccz BB9_4
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0
; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1]
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0
; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[4:5], v0
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1]
; GCN-IR-NEXT: s_cbranch_vccz BB9_5 ; GCN-IR-NEXT: s_cbranch_vccz BB9_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_not_b32_e32 v2, v2 ; GCN-IR-NEXT: v_not_b32_e32 v2, v2
; GCN-IR-NEXT: s_add_u32 s10, s8, -1 ; GCN-IR-NEXT: s_add_u32 s10, s6, -1
; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v4 ; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[4:5], v4
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: s_addc_u32 s11, s9, -1 ; GCN-IR-NEXT: s_addc_u32 s11, s7, -1
; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: BB9_3: ; %udiv-do-while ; GCN-IR-NEXT: BB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0
; GCN-IR-NEXT: v_mov_b32_e32 v2, s11 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s11
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s10, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s10, v6
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2
; GCN-IR-NEXT: v_and_b32_e32 v10, s8, v8 ; GCN-IR-NEXT: v_and_b32_e32 v10, s6, v8
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8
; GCN-IR-NEXT: v_and_b32_e32 v11, s9, v8 ; GCN-IR-NEXT: v_and_b32_e32 v11, s7, v8
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 ; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 ; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v3
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v2
; GCN-IR-NEXT: s_cbranch_vccz BB9_3 ; GCN-IR-NEXT: s_cbranch_vccz BB9_3
; GCN-IR-NEXT: s_branch BB9_6 ; GCN-IR-NEXT: s_branch BB9_6
; GCN-IR-NEXT: BB9_4: ; GCN-IR-NEXT: BB9_4:
; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s5
; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] ; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1]
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1]
; GCN-IR-NEXT: s_branch BB9_7 ; GCN-IR-NEXT: s_branch BB9_7
; GCN-IR-NEXT: BB9_5: ; GCN-IR-NEXT: BB9_5:
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: BB9_6: ; %Flow3 ; GCN-IR-NEXT: BB9_6: ; %Flow3
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-IR-NEXT: BB9_7: ; %udiv-end ; GCN-IR-NEXT: BB9_7: ; %udiv-end
; GCN-IR-NEXT: v_mul_lo_u32 v1, s8, v1 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s6, v1
; GCN-IR-NEXT: v_mul_hi_u32 v2, s8, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s6, v0
; GCN-IR-NEXT: v_mul_lo_u32 v3, s9, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s7, v0
; GCN-IR-NEXT: v_mul_lo_u32 v0, s8, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s6, v0
; GCN-IR-NEXT: s_mov_b32 s11, 0xf000
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GCN-IR-NEXT: v_mov_b32_e32 v2, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s5
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
; GCN-IR-NEXT: v_xor_b32_e32 v0, s2, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v0, s2, v0
; GCN-IR-NEXT: v_xor_b32_e32 v1, s3, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v1, s3, v1
; GCN-IR-NEXT: v_mov_b32_e32 v2, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s3
; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0 ; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s10, -1
; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: buffer_store_short v1, off, s[8:11], 0 offset:4
; GCN-IR-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 ; GCN-IR-NEXT: buffer_store_dword v0, off, s[8:11], 0
; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%1 = ashr i48 %x, 24 %1 = ashr i48 %x, 24
%2 = ashr i48 %y, 24 %2 = ashr i48 %y, 24
%result = srem i48 %1, %2 %result = srem i48 %1, %2
store i48 %result, i48 addrspace(1)* %out store i48 %result, i48 addrspace(1)* %out
ret void ret void
} }
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines
; GCN-IR-LABEL: s_test_srem_k_num_i64: ; GCN-IR-LABEL: s_test_srem_k_num_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_ashr_i32 s0, s7, 31 ; GCN-IR-NEXT: s_ashr_i32 s0, s7, 31
; GCN-IR-NEXT: s_mov_b32 s1, s0 ; GCN-IR-NEXT: s_mov_b32 s1, s0
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[6:7], s[0:1] ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[6:7], s[0:1]
; GCN-IR-NEXT: s_sub_u32 s2, s2, s0 ; GCN-IR-NEXT: s_sub_u32 s2, s2, s0
; GCN-IR-NEXT: s_subb_u32 s3, s3, s0
; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2
; GCN-IR-NEXT: s_subb_u32 s3, s3, s0
; GCN-IR-NEXT: s_add_i32 s6, s6, 32 ; GCN-IR-NEXT: s_add_i32 s6, s6, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3
; GCN-IR-NEXT: s_cmp_eq_u32 s3, 0
; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7
; GCN-IR-NEXT: v_mov_b32_e32 v1, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s6
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc5, v2 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc5, v2
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[6:7], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[6:7], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[0:1], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[0:1], -1
▲ Show 20 Lines • Show All 863 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/udiv64.ll

Show First 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_udiv_i64: ; GCN-IR-LABEL: s_test_udiv_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-IR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GCN-IR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0
; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GCN-IR-NEXT: s_add_i32 s10, s10, 32 ; GCN-IR-NEXT: s_add_i32 s10, s10, 32
; GCN-IR-NEXT: s_cmp_eq_u32 s3, 0
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6
; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3
; GCN-IR-NEXT: v_mov_b32_e32 v1, s10 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: s_flbit_i32_b32 s10, s6 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: v_mov_b32_e32 v0, s11
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0
; GCN-IR-NEXT: s_add_i32 s10, s10, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s11, s7
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s11
; GCN-IR-NEXT: v_mov_b32_e32 v1, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s10
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7
; GCN-IR-NEXT: s_cmp_eq_u32 s7, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v0, s9
; GCN-IR-NEXT: v_mov_b32_e32 v1, s8
; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0 ; GCN-IR-NEXT: v_subb_u32_e64 v1, s[8:9], 0, 0, vcc
; GCN-IR-NEXT: v_subb_u32_e64 v1, s[10:11], 0, 0, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_xor_b64 s[8:9], s[0:1], -1 ; GCN-IR-NEXT: s_xor_b64 s[8:9], s[0:1], -1
; GCN-IR-NEXT: s_and_b64 s[8:9], s[8:9], vcc ; GCN-IR-NEXT: s_and_b64 s[8:9], s[8:9], vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[8:9] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_vccz BB0_4 ; GCN-IR-NEXT: s_cbranch_vccz BB0_4
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0
▲ Show 20 Lines • Show All 537 Lines • ▼ Show 20 Lines; GCN-IR-NEXT: s_endpgm
ret void ret void
} }
define amdgpu_kernel void @s_test_udiv24_i48(i48 addrspace(1)* %out, i48 %x, i48 %y) { define amdgpu_kernel void @s_test_udiv24_i48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
; GCN-LABEL: s_test_udiv24_i48: ; GCN-LABEL: s_test_udiv24_i48:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s2, s[0:1], 0xd ; GCN-NEXT: s_load_dword s2, s[0:1], 0xd
; GCN-NEXT: s_load_dword s3, s[0:1], 0xe ; GCN-NEXT: s_load_dword s3, s[0:1], 0xe
; GCN-NEXT: s_mov_b32 s5, 0xff000000 ; GCN-NEXT: s_mov_b32 s7, 0xff000000
; GCN-NEXT: s_mov_b32 s4, 0xffff ; GCN-NEXT: s_mov_b32 s6, 0xffff
; GCN-NEXT: v_cvt_f32_ubyte3_e32 v2, s4 ; GCN-NEXT: v_cvt_f32_ubyte3_e32 v2, s6
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_and_b32 s2, s2, s5 ; GCN-NEXT: s_and_b32 s2, s2, s7
; GCN-NEXT: s_and_b32 s3, s3, s4 ; GCN-NEXT: s_and_b32 s3, s3, s6
; GCN-NEXT: v_mov_b32_e32 v0, s2 ; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: v_alignbit_b32 v0, s3, v0, 24 ; GCN-NEXT: v_alignbit_b32 v0, s3, v0, 24
; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0
; GCN-NEXT: s_load_dword s6, s[0:1], 0xb ; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_load_dword s7, s[0:1], 0xc ; GCN-NEXT: s_load_dword s8, s[0:1], 0xb
; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], 24 ; GCN-NEXT: s_load_dword s0, s[0:1], 0xc
; GCN-NEXT: v_mov_b32_e32 v9, 0 ; GCN-NEXT: v_mov_b32_e32 v9, 0
; GCN-NEXT: v_mov_b32_e32 v8, 0
; GCN-NEXT: v_mac_f32_e32 v1, 0x4f800000, v2 ; GCN-NEXT: v_mac_f32_e32 v1, 0x4f800000, v2
; GCN-NEXT: v_rcp_f32_e32 v1, v1 ; GCN-NEXT: v_rcp_f32_e32 v1, v1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_and_b32 s7, s7, s4 ; GCN-NEXT: s_and_b32 s6, s0, s6
; GCN-NEXT: s_and_b32 s6, s6, s5 ; GCN-NEXT: s_and_b32 s8, s8, s7
; GCN-NEXT: s_sub_u32 s8, 0, s2 ; GCN-NEXT: s_lshr_b64 s[0:1], s[2:3], 24
; GCN-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1 ; GCN-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1
; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1 ; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
; GCN-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mac_f32_e32 v1, 0xcf800000, v2 ; GCN-NEXT: v_mac_f32_e32 v1, 0xcf800000, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
; GCN-NEXT: s_subb_u32 s9, 0, s3 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
; GCN-NEXT: v_mov_b32_e32 v8, 0 ; GCN-NEXT: s_sub_u32 s2, 0, s0
; GCN-NEXT: v_mul_lo_u32 v3, s8, v2 ; GCN-NEXT: s_subb_u32 s3, 0, s1
; GCN-NEXT: v_mul_hi_u32 v4, s8, v1 ; GCN-NEXT: v_mul_hi_u32 v3, s2, v1
; GCN-NEXT: v_mul_lo_u32 v5, s9, v1 ; GCN-NEXT: v_mul_lo_u32 v4, s2, v2
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GCN-NEXT: v_mul_lo_u32 v5, s3, v1
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: v_mul_lo_u32 v4, s8, v1 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, s2, v1
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_mul_lo_u32 v6, v1, v3 ; GCN-NEXT: v_mul_lo_u32 v6, v1, v3
; GCN-NEXT: v_mul_hi_u32 v5, v1, v3 ; GCN-NEXT: v_mul_hi_u32 v5, v1, v3
; GCN-NEXT: v_mul_hi_u32 v7, v1, v4 ; GCN-NEXT: v_mul_hi_u32 v7, v1, v4
; GCN-NEXT: v_mul_hi_u32 v10, v2, v3 ; GCN-NEXT: v_mul_hi_u32 v10, v2, v3
; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 ; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_mul_lo_u32 v7, v2, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v2, v4
; GCN-NEXT: v_mul_hi_u32 v4, v2, v4 ; GCN-NEXT: v_mul_hi_u32 v4, v2, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v5, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v5, v4, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v8, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_add_i32_e64 v1, s[2:3], v1, v3 ; GCN-NEXT: v_add_i32_e64 v1, s[0:1], v1, v3
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v5, vcc
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v2, v4, s[2:3] ; GCN-NEXT: v_addc_u32_e64 v3, vcc, v2, v4, s[0:1]
; GCN-NEXT: v_mul_lo_u32 v5, s8, v3 ; GCN-NEXT: v_mul_lo_u32 v5, s2, v3
; GCN-NEXT: v_mul_hi_u32 v6, s8, v1 ; GCN-NEXT: v_mul_hi_u32 v6, s2, v1
; GCN-NEXT: v_mul_lo_u32 v7, s9, v1 ; GCN-NEXT: v_mul_lo_u32 v7, s3, v1
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GCN-NEXT: v_mul_lo_u32 v6, s8, v1 ; GCN-NEXT: v_mul_lo_u32 v6, s2, v1
; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; GCN-NEXT: v_mul_lo_u32 v11, v1, v5 ; GCN-NEXT: v_mul_lo_u32 v11, v1, v5
; GCN-NEXT: v_mul_hi_u32 v13, v1, v5 ; GCN-NEXT: v_mul_hi_u32 v13, v1, v5
; GCN-NEXT: v_mul_hi_u32 v12, v1, v6 ; GCN-NEXT: v_mul_hi_u32 v12, v1, v6
; GCN-NEXT: v_mul_hi_u32 v10, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v10, v3, v6
; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v6, v3, v6
; GCN-NEXT: v_mul_hi_u32 v7, v3, v5 ; GCN-NEXT: v_mul_hi_u32 v7, v3, v5
; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GCN-NEXT: v_addc_u32_e32 v12, vcc, v9, v13, vcc ; GCN-NEXT: v_addc_u32_e32 v12, vcc, v9, v13, vcc
; GCN-NEXT: v_mul_lo_u32 v3, v3, v5 ; GCN-NEXT: v_mul_lo_u32 v3, v3, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, v11, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v11, v6
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v12, v10, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v12, v10, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e64 v2, vcc, v2, v5, s[2:3] ; GCN-NEXT: v_addc_u32_e64 v2, vcc, v2, v5, s[0:1]
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-NEXT: v_mov_b32_e32 v3, s6 ; GCN-NEXT: v_mov_b32_e32 v3, s8
; GCN-NEXT: v_alignbit_b32 v3, s7, v3, 24 ; GCN-NEXT: v_alignbit_b32 v3, s6, v3, 24
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
; GCN-NEXT: v_mul_hi_u32 v5, v3, v1 ; GCN-NEXT: v_mul_hi_u32 v5, v3, v1
; GCN-NEXT: v_mul_lo_u32 v4, v3, v2 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v2
; GCN-NEXT: v_mul_hi_u32 v6, v3, v2 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v2
; GCN-NEXT: v_mul_hi_u32 v1, 0, v1 ; GCN-NEXT: v_mul_hi_u32 v1, 0, v1
; GCN-NEXT: v_mul_hi_u32 v2, 0, v2 ; GCN-NEXT: v_mul_hi_u32 v2, 0, v2
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, 0, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, 0, v4
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v5, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v5, v1, vcc
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v8, vcc
; GCN-NEXT: v_add_i32_e32 v1, vcc, 0, v1 ; GCN-NEXT: v_add_i32_e32 v1, vcc, 0, v1
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v9, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v9, v2, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v0, v2 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v2
; GCN-NEXT: v_mul_hi_u32 v5, v0, v1 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v1
; GCN-NEXT: v_mul_lo_u32 v6, v0, v1 ; GCN-NEXT: v_add_i32_e32 v4, vcc, 2, v1
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: v_mul_lo_u32 v10, v0, v1
; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_sub_i32_e32 v3, vcc, v3, v6
; GCN-NEXT: v_subb_u32_e32 v4, vcc, 0, v4, vcc
; GCN-NEXT: v_sub_i32_e32 v5, vcc, v3, v0
; GCN-NEXT: v_subbrev_u32_e32 v6, vcc, 0, v4, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v0
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GCN-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, 2, v1
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v2, vcc
; GCN-NEXT: v_add_i32_e32 v8, vcc, 1, v1 ; GCN-NEXT: v_add_i32_e32 v8, vcc, 1, v1
; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v3, v0
; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_sub_i32_e32 v3, vcc, v3, v10
; GCN-NEXT: v_subb_u32_e32 v6, vcc, 0, v6, vcc
; GCN-NEXT: v_sub_i32_e32 v7, vcc, v3, v0
; GCN-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v6, vcc
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v7, v0
; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v3, v0
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10
; GCN-NEXT: v_cndmask_b32_e32 v7, -1, v7, vcc
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4 ; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v6
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GCN-NEXT: v_cndmask_b32_e64 v0, -1, v0, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v0, -1, v0, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v5, v8, v6, vcc ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GCN-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v0 ; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, v1, v5, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v0, v1, v4, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v1, v9, v7, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v9, v5, vcc
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 ; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_udiv24_i48: ; GCN-IR-LABEL: s_test_udiv24_i48:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xb ; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xb
; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xc ; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xc
; GCN-IR-NEXT: s_load_dword s6, s[0:1], 0xd ; GCN-IR-NEXT: s_load_dword s6, s[0:1], 0xd
; GCN-IR-NEXT: s_load_dword s7, s[0:1], 0xe ; GCN-IR-NEXT: s_load_dword s5, s[0:1], 0xe
; GCN-IR-NEXT: s_mov_b32 s8, 0xffff ; GCN-IR-NEXT: s_mov_b32 s4, 0xffff
; GCN-IR-NEXT: s_mov_b32 s9, 0xff000000 ; GCN-IR-NEXT: s_mov_b32 s7, 0xff000000
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_and_b32 s1, s3, s8 ; GCN-IR-NEXT: s_and_b32 s3, s3, s4
; GCN-IR-NEXT: s_and_b32 s0, s2, s9 ; GCN-IR-NEXT: s_and_b32 s2, s2, s7
; GCN-IR-NEXT: s_and_b32 s3, s7, s8 ; GCN-IR-NEXT: s_and_b32 s5, s5, s4
; GCN-IR-NEXT: s_and_b32 s2, s6, s9 ; GCN-IR-NEXT: s_and_b32 s4, s6, s7
; GCN-IR-NEXT: s_lshr_b64 s[2:3], s[2:3], 24 ; GCN-IR-NEXT: s_lshr_b64 s[6:7], s[2:3], 24
; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2 ; GCN-IR-NEXT: s_lshr_b64 s[2:3], s[4:5], 24
; GCN-IR-NEXT: s_lshr_b64 s[6:7], s[0:1], 24 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], s[2:3], 0
; GCN-IR-NEXT: s_add_i32 s10, s10, 32 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3 ; GCN-IR-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v1, s10 ; GCN-IR-NEXT: s_flbit_i32_b32 s4, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s10, s6 ; GCN-IR-NEXT: s_add_i32 s4, s4, 32
; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 ; GCN-IR-NEXT: s_cmp_eq_u32 s3, 0
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s4
; GCN-IR-NEXT: s_add_i32 s10, s10, 32 ; GCN-IR-NEXT: s_flbit_i32_b32 s4, s6
; GCN-IR-NEXT: s_flbit_i32_b32 s11, s7 ; GCN-IR-NEXT: s_flbit_i32_b32 s5, s3
; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: s_add_i32 s4, s4, 32
; GCN-IR-NEXT: v_mov_b32_e32 v0, s5
; GCN-IR-NEXT: s_flbit_i32_b32 s5, s7
; GCN-IR-NEXT: s_cmp_eq_u32 s7, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s5
; GCN-IR-NEXT: v_mov_b32_e32 v1, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s4
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3
; GCN-IR-NEXT: v_subb_u32_e64 v1, s[10:11], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v1, s[4:5], 0, 0, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9] ; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc ; GCN-IR-NEXT: s_or_b64 s[0:1], s[8:9], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_xor_b64 s[8:9], s[0:1], -1 ; GCN-IR-NEXT: s_xor_b64 s[8:9], s[0:1], -1
; GCN-IR-NEXT: s_and_b64 s[8:9], s[8:9], vcc ; GCN-IR-NEXT: s_and_b64 s[8:9], s[8:9], vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[8:9] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[8:9]
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_mov_b64 vcc, vcc
; GCN-IR-NEXT: s_cbranch_vccz BB7_4 ; GCN-IR-NEXT: s_cbranch_vccz BB7_4
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0
; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1]
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0
; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1]
▲ Show 20 Lines • Show All 171 Lines • ▼ Show 20 Lines
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_udiv_k_num_i64: ; GCN-IR-LABEL: s_test_udiv_k_num_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_flbit_i32_b32 s2, s6 ; GCN-IR-NEXT: s_flbit_i32_b32 s2, s6
; GCN-IR-NEXT: s_flbit_i32_b32 s3, s7
; GCN-IR-NEXT: s_add_i32 s2, s2, 32 ; GCN-IR-NEXT: s_add_i32 s2, s2, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s3, s7
; GCN-IR-NEXT: s_cmp_eq_u32 s7, 0
; GCN-IR-NEXT: v_mov_b32_e32 v0, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s3
; GCN-IR-NEXT: v_mov_b32_e32 v1, s2 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s2
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc5, v2 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc5, v2
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[2:3], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[2:3], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[0:1], -1 ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[0:1], -1
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; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v4, s11, v0 ; GCN-NEXT: v_mul_lo_u32 v4, s11, v0
; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GCN-NEXT: v_mul_lo_u32 v2, v1, 24 ; GCN-NEXT: v_mul_lo_u32 v4, v1, 24
; GCN-NEXT: v_mul_hi_u32 v3, v0, 24 ; GCN-NEXT: v_mul_hi_u32 v5, v0, 24
; GCN-NEXT: v_mul_lo_u32 v4, v0, 24 ; GCN-NEXT: v_add_i32_e32 v2, vcc, 2, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-NEXT: v_mul_lo_u32 v8, v0, 24
; GCN-NEXT: v_sub_i32_e32 v4, vcc, s10, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GCN-NEXT: v_mov_b32_e32 v3, s11 ; GCN-NEXT: v_add_i32_e32 v6, vcc, 1, v0
; GCN-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
; GCN-NEXT: v_subrev_i32_e32 v3, vcc, 24, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc ; GCN-NEXT: v_sub_i32_e32 v8, vcc, s10, v8
; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v3 ; GCN-NEXT: v_mov_b32_e32 v5, s11
; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GCN-NEXT: v_subb_u32_e32 v4, vcc, v5, v4, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 ; GCN-NEXT: v_subrev_i32_e32 v5, vcc, 24, v8
; GCN-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc ; GCN-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
; GCN-NEXT: v_add_i32_e32 v5, vcc, 2, v0 ; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v5
; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v4 ; GCN-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc ; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v8
; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
; GCN-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v4, -1, v5, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2 ; GCN-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc ; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GCN-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_udiv_k_den_i64: ; GCN-IR-LABEL: s_test_udiv_k_den_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_flbit_i32_b32 s2, s6 ; GCN-IR-NEXT: s_flbit_i32_b32 s2, s6
; GCN-IR-NEXT: s_flbit_i32_b32 s3, s7
; GCN-IR-NEXT: s_add_i32 s2, s2, 32 ; GCN-IR-NEXT: s_add_i32 s2, s2, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s3, s7
; GCN-IR-NEXT: s_cmp_eq_u32 s7, 0
; GCN-IR-NEXT: v_mov_b32_e32 v0, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s3
; GCN-IR-NEXT: v_mov_b32_e32 v1, s2 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s2
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 59, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 59, v2
; GCN-IR-NEXT: v_subb_u32_e64 v1, s[2:3], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v1, s[2:3], 0, 0, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[0:1], -1 ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[0:1], -1
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llvm/test/CodeGen/AMDGPU/udivrem.ll

Show All 30 Lines
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; R600-NEXT: ADD_INT * T1.W, PV.W, 1, ; R600-NEXT: ADD_INT * T1.W, PV.W, 1,
; R600-NEXT: CNDE_INT T2.X, T3.W, T0.W, PV.W, ; R600-NEXT: CNDE_INT T2.X, T3.W, T0.W, PV.W,
; R600-NEXT: LSHR * T3.X, KC0[2].Y, literal.x, ; R600-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; ;
; GFX6-LABEL: test_udivrem: ; GFX6-LABEL: test_udivrem:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dword s3, s[0:1], 0x26 ; GFX6-NEXT: s_load_dword s2, s[0:1], 0x26
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x13 ; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x13
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x1d ; GFX6-NEXT: s_load_dword s0, s[0:1], 0x1d
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_mov_b32 s10, s6 ; GFX6-NEXT: s_mov_b32 s10, s6
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s3 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX6-NEXT: s_sub_i32 s2, 0, s3 ; GFX6-NEXT: s_sub_i32 s3, 0, s2
; GFX6-NEXT: s_mov_b32 s11, s7 ; GFX6-NEXT: s_mov_b32 s11, s7
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_lo_u32 v1, s2, v0 ; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX6-NEXT: v_mul_lo_u32 v1, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v1, v0, s2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v1 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v1
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v1
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v1
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v1
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_waitcnt expcnt(0) ; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_cndmask_b32_e64 v0, v1, v2, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v1, v2, s[0:1]
; GFX6-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; GFX6-NEXT: buffer_store_dword v0, off, s[8:11], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX8-LABEL: test_udivrem: ; GFX8-LABEL: test_udivrem:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dword s7, s[0:1], 0x98 ; GFX8-NEXT: s_load_dword s6, s[0:1], 0x98
; GFX8-NEXT: s_load_dword s6, s[0:1], 0x74 ; GFX8-NEXT: s_load_dword s7, s[0:1], 0x74
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s7 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX8-NEXT: s_sub_i32 s2, 0, s7 ; GFX8-NEXT: s_sub_i32 s2, 0, s6
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: v_mul_lo_u32 v1, s2, v0 ; GFX8-NEXT: v_mul_lo_u32 v1, s2, v0
; GFX8-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x4c ; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x4c
; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0
; GFX8-NEXT: v_mul_hi_u32 v2, s6, v0 ; GFX8-NEXT: v_mul_hi_u32 v2, s7, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_mul_lo_u32 v3, v2, s7 ; GFX8-NEXT: v_mul_lo_u32 v3, v2, s6
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v2 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v2
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s6, v3 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s7, v3
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v3 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v3
; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s7, v3 ; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s6, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v2 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v2
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v3 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v3
; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s7, v3 ; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s6, v3
; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[0:1]
; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
%result0 = udiv i32 %x, %y %result0 = udiv i32 %x, %y
store i32 %result0, i32 addrspace(1)* %out0 store i32 %result0, i32 addrspace(1)* %out0
%result1 = urem i32 %x, %y %result1 = urem i32 %x, %y
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX8-LABEL: test_udivrem_v2: ; GFX8-LABEL: test_udivrem_v2:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
; GFX8-NEXT: s_mov_b32 s3, 0x4f7ffffe ; GFX8-NEXT: s_mov_b32 s2, 0x4f7ffffe
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX8-NEXT: s_sub_i32 s2, 0, s6
; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s7 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s7
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX8-NEXT: v_mul_f32_e32 v0, s3, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, s2, v0
; GFX8-NEXT: v_mul_f32_e32 v1, s2, v1
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: v_mul_f32_e32 v1, s3, v1
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: s_sub_i32 s2, 0, s6
; GFX8-NEXT: v_mul_lo_u32 v2, s2, v0 ; GFX8-NEXT: v_mul_lo_u32 v2, s2, v0
; GFX8-NEXT: s_sub_i32 s2, 0, s7 ; GFX8-NEXT: s_sub_i32 s2, 0, s7
; GFX8-NEXT: v_mul_lo_u32 v3, s2, v1
; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2 ; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v2, v0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v2, v0
; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX8-NEXT: v_mul_lo_u32 v2, s2, v1 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v3, v1
; GFX8-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX8-NEXT: v_mul_lo_u32 v0, v0, s6 ; GFX8-NEXT: v_mul_lo_u32 v0, v0, s6
; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX8-NEXT: v_mul_lo_u32 v1, v1, s7
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0 ; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s6, v0 ; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s6, v0
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s7, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s6, v0 ; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s6, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v1
; GFX8-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX8-NEXT: v_mul_lo_u32 v1, v1, s7
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s7, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s7, v1 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s7, v1 ; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s7, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s7, v1 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
%result0 = udiv <2 x i32> %x, %y %result0 = udiv <2 x i32> %x, %y
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
; ;
; GFX8-LABEL: test_udivrem_v4: ; GFX8-LABEL: test_udivrem_v4:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34 ; GFX8-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
; GFX8-NEXT: s_mov_b32 s12, 0x4f7ffffe ; GFX8-NEXT: s_mov_b32 s12, 0x4f7ffffe
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX8-NEXT: s_sub_i32 s2, 0, s8
; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s9 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX8-NEXT: v_cvt_f32_u32_e32 v4, s11 ; GFX8-NEXT: s_sub_i32 s2, 0, s8
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_sub_i32 s3, 0, s9 ; GFX8-NEXT: s_sub_i32 s3, 0, s9
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s10 ; GFX8-NEXT: v_cvt_f32_u32_e32 v3, s10
; GFX8-NEXT: v_cvt_f32_u32_e32 v5, s11
; GFX8-NEXT: v_mul_f32_e32 v0, s12, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, s12, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: v_mul_f32_e32 v1, s12, v1 ; GFX8-NEXT: v_mul_f32_e32 v1, s12, v1
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX8-NEXT: v_mul_lo_u32 v3, s2, v0 ; GFX8-NEXT: v_mul_lo_u32 v2, s2, v0
; GFX8-NEXT: s_sub_i32 s2, 0, s10 ; GFX8-NEXT: s_sub_i32 s2, 0, s10
; GFX8-NEXT: v_mul_f32_e32 v2, s12, v2
; GFX8-NEXT: v_mul_hi_u32 v3, v0, v3
; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v3, v0
; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v4
; GFX8-NEXT: v_mul_lo_u32 v4, s3, v1 ; GFX8-NEXT: v_mul_lo_u32 v4, s3, v1
; GFX8-NEXT: v_mul_lo_u32 v0, v0, s8 ; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX8-NEXT: v_mul_f32_e32 v3, s12, v3
; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v2, v0
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s8, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s8, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v4, v1 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v4, v1
; GFX8-NEXT: v_mul_hi_u32 v1, s5, v1 ; GFX8-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX8-NEXT: v_mul_lo_u32 v4, s2, v2 ; GFX8-NEXT: v_mul_f32_e32 v2, s12, v3
; GFX8-NEXT: s_sub_i32 s2, 0, s11 ; GFX8-NEXT: v_mul_lo_u32 v0, v0, s8
; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX8-NEXT: v_mul_lo_u32 v1, v1, s9 ; GFX8-NEXT: v_mul_lo_u32 v1, v1, s9
; GFX8-NEXT: v_mul_hi_u32 v4, v2, v4 ; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s8, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s8, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: v_mul_lo_u32 v3, s2, v2
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1 ; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s9, v1 ; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s9, v1
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s9, v1 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s9, v1 ; GFX8-NEXT: v_mul_hi_u32 v3, v2, v3
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s9, v1 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v4, v5
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GFX8-NEXT: s_sub_i32 s2, 0, s11
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v4, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2
; GFX8-NEXT: v_mul_f32_e32 v3, s12, v4
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s9, v1
; GFX8-NEXT: v_mul_hi_u32 v2, s6, v2 ; GFX8-NEXT: v_mul_hi_u32 v2, s6, v2
; GFX8-NEXT: v_mul_lo_u32 v4, s2, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
; GFX8-NEXT: v_mul_lo_u32 v5, s2, v3
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX8-NEXT: v_mul_lo_u32 v2, v2, s10 ; GFX8-NEXT: v_mul_lo_u32 v2, v2, s10
; GFX8-NEXT: v_mul_hi_u32 v4, v3, v4 ; GFX8-NEXT: v_mul_hi_u32 v4, v3, v5
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s6, v2 ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s6, v2
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s10, v2 ; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s10, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s10, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3
; GFX8-NEXT: v_mul_hi_u32 v3, s7, v3 ; GFX8-NEXT: v_mul_hi_u32 v3, s7, v3
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s10, v2
; GFX8-NEXT: v_mul_lo_u32 v3, v3, s11 ; GFX8-NEXT: v_mul_lo_u32 v3, v3, s11
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s7, v3 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s7, v3
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s11, v3 ; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s11, v3
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s11, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s11, v3 ; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s11, v3
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s11, v3 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: v_mov_b32_e32 v5, s1 ; GFX8-NEXT: v_mov_b32_e32 v5, s1
Show All 9 Lines

llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; We can't fold the SGPRs into v_cndmask_b32_e32, because it already ; We can't fold the SGPRs into v_cndmask_b32_e32, because it already
; uses an SGPR (implicit vcc). ; uses an SGPR (implicit vcc).
; GCN-LABEL: {{^}}uint_to_fp_i1_to_f64: ; GCN-LABEL: {{^}}uint_to_fp_i1_to_f64:
; VI-DAG: s_cmp_eq_u32 ; VI-DAG: s_cmp_eq_u32
; VI-DAG: s_cselect_b32 s[[SSEL:[0-9]+]], 0x3ff00000, 0 ; VI-DAG: s_cselect_b32 s[[SSEL:[0-9]+]], 0x3ff00000, 0
; VI-DAG: v_mov_b32_e32 v[[SEL:[0-9]+]], s[[SSEL]] ; VI-DAG: v_mov_b32_e32 v[[SEL:[0-9]+]], s[[SSEL]]
; SI-DAG: v_cmp_eq_u32_e64 vcc ; SI-DAG: s_cmp_eq_u32
; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}} ; SI-DAG: s_cselect_b64 vcc, -1, 0
; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, {{v[0-9]+}}, vcc
; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[ZERO]]:[[SEL]]{{\]}} ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[ZERO]]:[[SEL]]{{\]}}
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @uint_to_fp_i1_to_f64(double addrspace(1)* %out, i32 %in) { define amdgpu_kernel void @uint_to_fp_i1_to_f64(double addrspace(1)* %out, i32 %in) {
%cmp = icmp eq i32 %in, 0 %cmp = icmp eq i32 %in, 0
%fp = uitofp i1 %cmp to double %fp = uitofp i1 %cmp to double
store double %fp, double addrspace(1)* %out, align 4 store double %fp, double addrspace(1)* %out, align 4
ret void ret void
Show All 38 Lines

llvm/test/CodeGen/AMDGPU/uint_to_fp.ll

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_uint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 {
%out.gep = getelementptr <4 x float>, <4 x float> addrspace(1)* %out, i32 %tid %out.gep = getelementptr <4 x float>, <4 x float> addrspace(1)* %out, i32 %tid
%value = load <4 x i32>, <4 x i32> addrspace(1)* %in.gep %value = load <4 x i32>, <4 x i32> addrspace(1)* %in.gep
%result = uitofp <4 x i32> %value to <4 x float> %result = uitofp <4 x i32> %value to <4 x float>
store <4 x float> %result, <4 x float> addrspace(1)* %out.gep store <4 x float> %result, <4 x float> addrspace(1)* %out.gep
ret void ret void
} }
; FUNC-LABEL: {{^}}s_uint_to_fp_i1_to_f32: ; FUNC-LABEL: {{^}}s_uint_to_fp_i1_to_f32:
; SI: v_cmp_eq_u32_e64 [[CMP:s\[[0-9]+:[0-9]\]]], ; SI: s_cmp_eq_u32
; SI: s_cselect_b64 [[CMP:s\[[0-9]+:[0-9]\]]], -1, 0
; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]] ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]]
; SI: buffer_store_dword [[RESULT]], ; SI: buffer_store_dword [[RESULT]],
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @s_uint_to_fp_i1_to_f32(float addrspace(1)* %out, i32 %in) #0 { define amdgpu_kernel void @s_uint_to_fp_i1_to_f32(float addrspace(1)* %out, i32 %in) #0 {
%cmp = icmp eq i32 %in, 0 %cmp = icmp eq i32 %in, 0
%fp = uitofp i1 %cmp to float %fp = uitofp i1 %cmp to float
store float %fp, float addrspace(1)* %out store float %fp, float addrspace(1)* %out
ret void ret void
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; CHECK-NEXT: s_mov_b32 s2, -1 ; CHECK-NEXT: s_mov_b32 s2, -1
; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc ; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc ; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v2, 0x7fc00000 ; CHECK-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], 0 ; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], 0
; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; CHECK-NEXT: s_waitcnt expcnt(0)
; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1
; CHECK-NEXT: BB1_1: ; %bb9 ; CHECK-NEXT: BB1_1: ; %bb9
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_andn2_b64 vcc, exec, s[0:1] ; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]
; CHECK-NEXT: s_cbranch_vccnz BB1_1 ; CHECK-NEXT: s_cbranch_vccnz BB1_1
; CHECK-NEXT: ; %bb.2: ; %bb11 ; CHECK-NEXT: ; %bb.2: ; %bb11
; CHECK-NEXT: s_mov_b32 s3, 0xf000 ; CHECK-NEXT: s_mov_b32 s3, 0xf000
; CHECK-NEXT: s_mov_b32 s2, -1 ; CHECK-NEXT: s_mov_b32 s2, -1
; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; CHECK-NEXT: ; return to shader part epilog ; CHECK-NEXT: ; return to shader part epilog
bb: bb:
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llvm/test/CodeGen/AMDGPU/uniform-cfg.ll

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ENDIF: ; preds = %IF, %main_body ENDIF: ; preds = %IF, %main_body
ret void ret void
} }
; GCN-LABEL: {{^}}icmp_users_different_blocks: ; GCN-LABEL: {{^}}icmp_users_different_blocks:
; GCN: s_load_dwordx2 s{{\[}}[[COND0:[0-9]+]]:[[COND1:[0-9]+]]{{\]}} ; GCN: s_load_dwordx2 s{{\[}}[[COND0:[0-9]+]]:[[COND1:[0-9]+]]{{\]}}
; GCN: s_cmp_lt_i32 s[[COND0]], 1 ; GCN: s_cmp_lt_i32 s[[COND0]], 1
; GCN: s_cbranch_scc1 [[EXIT:[A-Za-z0-9_]+]] ; GCN: s_cbranch_scc1 [[EXIT:[A-Za-z0-9_]+]]
; GCN: v_cmp_gt_i32_e64 {{[^,]*}}, s[[COND1]], 0{{$}} ; GCN: s_cmp_gt_i32 s[[COND1]], 0{{$}}
; GCN: s_cbranch_vccz [[BODY:[A-Za-z0-9_]+]] ; GCN: s_cbranch_vccz [[BODY:[A-Za-z0-9_]+]]
; GCN: {{^}}[[EXIT]]: ; GCN: {{^}}[[EXIT]]:
; GCN: s_endpgm ; GCN: s_endpgm
; GCN: {{^}}[[BODY]]: ; GCN: {{^}}[[BODY]]:
; GCN: buffer_store ; GCN: buffer_store
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @icmp_users_different_blocks(i32 %cond0, i32 %cond1, i32 addrspace(1)* %out) { define amdgpu_kernel void @icmp_users_different_blocks(i32 %cond0, i32 %cond1, i32 addrspace(1)* %out) {
bb: bb:
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llvm/test/CodeGen/AMDGPU/urem64.ll

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; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_urem_i64: ; GCN-IR-LABEL: s_test_urem_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-IR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GCN-IR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0
; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GCN-IR-NEXT: s_add_i32 s10, s10, 32 ; GCN-IR-NEXT: s_add_i32 s10, s10, 32
; GCN-IR-NEXT: s_cmp_eq_u32 s3, 0
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6
; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3
; GCN-IR-NEXT: v_mov_b32_e32 v1, s10 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: s_flbit_i32_b32 s10, s6 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: v_mov_b32_e32 v0, s11
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0
; GCN-IR-NEXT: s_add_i32 s10, s10, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s11, s7
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s11
; GCN-IR-NEXT: v_mov_b32_e32 v1, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s10
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7
; GCN-IR-NEXT: s_cmp_eq_u32 s7, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v0, s9
; GCN-IR-NEXT: v_mov_b32_e32 v1, s8
; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0 ; GCN-IR-NEXT: v_subb_u32_e64 v1, s[8:9], 0, 0, vcc
; GCN-IR-NEXT: v_subb_u32_e64 v1, s[10:11], 0, 0, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_xor_b64 s[8:9], s[0:1], -1 ; GCN-IR-NEXT: s_xor_b64 s[8:9], s[0:1], -1
; GCN-IR-NEXT: s_and_b64 s[8:9], s[8:9], vcc ; GCN-IR-NEXT: s_and_b64 s[8:9], s[8:9], vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[8:9] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_vccz BB0_4 ; GCN-IR-NEXT: s_cbranch_vccz BB0_4
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_urem_k_num_i64: ; GCN-IR-LABEL: s_test_urem_k_num_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_flbit_i32_b32 s2, s6 ; GCN-IR-NEXT: s_flbit_i32_b32 s2, s6
; GCN-IR-NEXT: s_flbit_i32_b32 s3, s7
; GCN-IR-NEXT: s_add_i32 s2, s2, 32 ; GCN-IR-NEXT: s_add_i32 s2, s2, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s3, s7
; GCN-IR-NEXT: s_cmp_eq_u32 s7, 0
; GCN-IR-NEXT: v_mov_b32_e32 v0, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s3
; GCN-IR-NEXT: v_mov_b32_e32 v1, s2 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s2
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc5, v2 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc5, v2
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[2:3], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[2:3], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[0:1], -1 ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[0:1], -1
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_urem_k_den_i64: ; GCN-IR-LABEL: s_test_urem_k_den_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_flbit_i32_b32 s2, s6 ; GCN-IR-NEXT: s_flbit_i32_b32 s2, s6
; GCN-IR-NEXT: s_flbit_i32_b32 s3, s7
; GCN-IR-NEXT: s_add_i32 s2, s2, 32 ; GCN-IR-NEXT: s_add_i32 s2, s2, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s3, s7
; GCN-IR-NEXT: s_cmp_eq_u32 s7, 0
; GCN-IR-NEXT: v_mov_b32_e32 v0, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s3
; GCN-IR-NEXT: v_mov_b32_e32 v1, s2 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s2
; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc ; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 59, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 59, v2
; GCN-IR-NEXT: v_subb_u32_e64 v1, s[2:3], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v1, s[2:3], 0, 0, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc ; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[0:1], -1 ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[0:1], -1
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llvm/test/CodeGen/AMDGPU/v_cndmask.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
declare half @llvm.fabs.f16(half) declare half @llvm.fabs.f16(half)
declare float @llvm.fabs.f32(float) declare float @llvm.fabs.f32(float)
declare double @llvm.fabs.f64(double) declare double @llvm.fabs.f64(double)
; GCN-LABEL: {{^}}v_cnd_nan_nosgpr: ; GCN-LABEL: {{^}}v_cnd_nan_nosgpr:
; GCN: v_cmp_eq_u32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0 ; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0
; GCN: s_cselect_b64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], -1, 0
; GCN: v_cndmask_b32_e{{32|64}} v{{[0-9]}}, -1, v{{[0-9]+}}, [[COND]] ; GCN: v_cndmask_b32_e{{32|64}} v{{[0-9]}}, -1, v{{[0-9]+}}, [[COND]]
; GCN-DAG: v{{[0-9]}} ; GCN-DAG: v{{[0-9]}}
; All nan values are converted to 0xffffffff ; All nan values are converted to 0xffffffff
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @v_cnd_nan_nosgpr(float addrspace(1)* %out, i32 %c, float addrspace(1)* %fptr) #0 { define amdgpu_kernel void @v_cnd_nan_nosgpr(float addrspace(1)* %out, i32 %c, float addrspace(1)* %fptr) #0 {
%idx = call i32 @llvm.amdgcn.workitem.id.x() #1 %idx = call i32 @llvm.amdgcn.workitem.id.x() #1
%f.gep = getelementptr float, float addrspace(1)* %fptr, i32 %idx %f.gep = getelementptr float, float addrspace(1)* %fptr, i32 %idx
%f = load float, float addrspace(1)* %f.gep %f = load float, float addrspace(1)* %f.gep
%setcc = icmp ne i32 %c, 0 %setcc = icmp ne i32 %c, 0
%select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f
store float %select, float addrspace(1)* %out store float %select, float addrspace(1)* %out
ret void ret void
} }
; This requires slightly trickier SGPR operand legalization since the ; This requires slightly trickier SGPR operand legalization since the
; single constant bus SGPR usage is the last operand, and it should ; single constant bus SGPR usage is the last operand, and it should
; never be moved. ; never be moved.
; However on GFX10 constant bus is limited to 2 scalar operands, not one. ; However on GFX10 constant bus is limited to 2 scalar operands, not one.
; GCN-LABEL: {{^}}v_cnd_nan: ; GCN-LABEL: {{^}}v_cnd_nan:
; SIVI: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0 ; SIVI: s_cmp_eq_u32 s{{[0-9]+}}, 0
; SIVI: s_cselect_b64 vcc, -1, 0
; SIVI: v_cndmask_b32_e32 v{{[0-9]+}}, -1, v{{[0-9]+}}, vcc ; SIVI: v_cndmask_b32_e32 v{{[0-9]+}}, -1, v{{[0-9]+}}, vcc
; GFX10: v_cmp_eq_u32_e64 [[CC:s\[[0-9:]+\]]], s{{[0-9]+}}, 0 ; GFX10: s_cmp_eq_u32 s{{[0-9]+}}, 0
; GFX10: s_cselect_b64 [[CC:s\[[0-9:]+\]]],
; GFX10: v_cndmask_b32_e64 v{{[0-9]+}}, -1, s{{[0-9]+}}, [[CC]] ; GFX10: v_cndmask_b32_e64 v{{[0-9]+}}, -1, s{{[0-9]+}}, [[CC]]
; GCN-DAG: v{{[0-9]}} ; GCN-DAG: v{{[0-9]}}
; All nan values are converted to 0xffffffff ; All nan values are converted to 0xffffffff
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @v_cnd_nan(float addrspace(1)* %out, i32 %c, float %f) #0 { define amdgpu_kernel void @v_cnd_nan(float addrspace(1)* %out, i32 %c, float %f) #0 {
%setcc = icmp ne i32 %c, 0 %setcc = icmp ne i32 %c, 0
%select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f
store float %select, float addrspace(1)* %out store float %select, float addrspace(1)* %out
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llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-ALLOCA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-ALLOCA %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-PROMOTE %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-PROMOTE %s
; RUN: opt -S -mtriple=amdgcn-- -amdgpu-promote-alloca -sroa -instcombine < %s | FileCheck -check-prefix=OPT %s ; RUN: opt -S -mtriple=amdgcn-- -amdgpu-promote-alloca -sroa -instcombine < %s | FileCheck -check-prefix=OPT %s
target datalayout = "A5" target datalayout = "A5"
; OPT-LABEL: @vector_read_alloca_bitcast( ; OPT-LABEL: @vector_read_alloca_bitcast(
; OPT-NOT: alloca ; OPT-NOT: alloca
; OPT: %0 = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index ; OPT: %0 = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
; OPT-NEXT: store i32 %0, i32 addrspace(1)* %out, align 4 ; OPT-NEXT: store i32 %0, i32 addrspace(1)* %out, align 4
; GCN-LABEL: {{^}}vector_read_alloca_bitcast: ; GCN-LABEL: {{^}}vector_read_alloca_bitcast:
; GCN-ALLOCA-COUNT-4: buffer_store_dword ; GCN-ALLOCA-COUNT-4: buffer_store_dword
; GCN-ALLOCA: buffer_load_dword ; GCN-ALLOCA: buffer_load_dword
; GCN_PROMOTE: s_cmp_lg_u32 s{{[0-9]+}}, 2 ; GCN_PROMOTE: s_cmp_lg_u32 s{{[0-9]+}}, 2
; GCN-PROMOTE: v_cmp_eq_u32_e64 [[CC1:[^,]+]], s{{[0-9]+}}, 1 ; GCN-PROMOTE: s_cmp_eq_u32 s{{[0-9]+}}, 1
; GCN-PROMOTE: s_cselect_b64 [[CC1:[^,]+]], -1, 0
; GCN-PROMOTE: s_cselect_b64 vcc, -1, 0 ; GCN-PROMOTE: s_cselect_b64 vcc, -1, 0
; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND1:v[0-9]+]], 0, 1, [[CC1]] ; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND1:v[0-9]+]], 0, 1, [[CC1]]
; GCN_PROMOTE: s_cmp_lg_u32 s{{[0-9]+}}, 3 ; GCN_PROMOTE: s_cmp_lg_u32 s{{[0-9]+}}, 3
; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND2:v[0-9]+]], 2, [[IND1]], vcc ; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND2:v[0-9]+]], 2, [[IND1]], vcc
; GCN-PROMOTE: s_cselect_b64 vcc, -1, 0 ; GCN-PROMOTE: s_cselect_b64 vcc, -1, 0
; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND3:v[0-9]+]], 3, [[IND2]], vcc ; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND3:v[0-9]+]], 3, [[IND2]], vcc
; GCN-PROMOTE: ScratchSize: 0 ; GCN-PROMOTE: ScratchSize: 0
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; OPT-NEXT: %add2 = add nuw nsw i32 %0, 1 ; OPT-NEXT: %add2 = add nuw nsw i32 %0, 1
; OPT-NEXT: store i32 %add2, i32 addrspace(1)* %out, align 4 ; OPT-NEXT: store i32 %add2, i32 addrspace(1)* %out, align 4
; GCN-LABEL: {{^}}vector_read_alloca_multiuse: ; GCN-LABEL: {{^}}vector_read_alloca_multiuse:
; GCN-ALLOCA-COUNT-4: buffer_store_dword ; GCN-ALLOCA-COUNT-4: buffer_store_dword
; GCN-ALLOCA: buffer_load_dword ; GCN-ALLOCA: buffer_load_dword
; GCN_PROMOTE: s_cmp_lg_u32 s{{[0-9]+}}, 2 ; GCN_PROMOTE: s_cmp_lg_u32 s{{[0-9]+}}, 2
; GCN-PROMOTE: v_cmp_eq_u32_e64 [[CC1:[^,]+]], s{{[0-9]+}}, 1 ; GCN-PROMOTE: s_cmp_eq_u32 s{{[0-9]+}}, 1
; GCN-PROMOTE: s_cselect_b64 [[CC1:[^,]+]], -1, 0
; GCN-PROMOTE: s_cselect_b64 vcc, -1, 0 ; GCN-PROMOTE: s_cselect_b64 vcc, -1, 0
; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND1:v[0-9]+]], 0, 1, [[CC1]] ; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND1:v[0-9]+]], 0, 1, [[CC1]]
; GCN_PROMOTE: s_cmp_lg_u32 s{{[0-9]+}}, 3 ; GCN_PROMOTE: s_cmp_lg_u32 s{{[0-9]+}}, 3
; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND2:v[0-9]+]], 2, [[IND1]], vcc ; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND2:v[0-9]+]], 2, [[IND1]], vcc
; GCN-PROMOTE: s_cselect_b64 vcc, -1, 0 ; GCN-PROMOTE: s_cselect_b64 vcc, -1, 0
; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND3:v[0-9]+]], 3, [[IND2]], vcc ; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND3:v[0-9]+]], 3, [[IND2]], vcc
; GCN-PROMOTE: ScratchSize: 0 ; GCN-PROMOTE: ScratchSize: 0
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llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll

Show All 29 Lines; GCN-NEXT: s_endpgm
store i32 %extract, i32 addrspace(1)* %gep.out store i32 %extract, i32 addrspace(1)* %gep.out
ret void ret void
} }
define amdgpu_kernel void @extract_insert_different_dynelt_v4i32(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %val, i32 %idx0, i32 %idx1) #1 { define amdgpu_kernel void @extract_insert_different_dynelt_v4i32(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %val, i32 %idx0, i32 %idx1) #1 {
; GCN-LABEL: extract_insert_different_dynelt_v4i32: ; GCN-LABEL: extract_insert_different_dynelt_v4i32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GCN-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0xd
; GCN-NEXT: v_mov_b32_e32 v5, 0 ; GCN-NEXT: v_mov_b32_e32 v5, 0
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, 0 ; GCN-NEXT: s_mov_b32 s6, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[4:5], s[10:11] ; GCN-NEXT: s_mov_b64 s[4:5], s[10:11]
; GCN-NEXT: v_lshlrev_b32_e32 v4, 4, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v4, 4, v0
; GCN-NEXT: buffer_load_dwordx4 v[1:4], v[4:5], s[4:7], 0 addr64 ; GCN-NEXT: buffer_load_dwordx4 v[1:4], v[4:5], s[4:7], 0 addr64
; GCN-NEXT: s_load_dword s0, s[0:1], 0xf ; GCN-NEXT: s_load_dword s14, s[0:1], 0xf
; GCN-NEXT: s_cmp_eq_u32 s13, 3
; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_eq_u32 s13, 2
; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0
; GCN-NEXT: s_cmp_eq_u32 s13, 1
; GCN-NEXT: s_cselect_b64 s[2:3], -1, 0
; GCN-NEXT: s_cmp_eq_u32 s13, 0
; GCN-NEXT: v_lshlrev_b32_e32 v6, 2, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v6, 2, v0
; GCN-NEXT: v_mov_b32_e32 v0, s2 ; GCN-NEXT: v_mov_b32_e32 v0, s12
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s3, 3 ; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_eq_u32 s14, 1
; GCN-NEXT: v_mov_b32_e32 v7, v5 ; GCN-NEXT: v_mov_b32_e32 v7, v5
; GCN-NEXT: s_mov_b64 s[10:11], s[6:7] ; GCN-NEXT: s_mov_b64 s[10:11], s[6:7]
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc ; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s3, 2 ; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc ; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v0, s[0:1]
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s3, 1 ; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v0, s[2:3]
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc ; GCN-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[4:5]
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0 ; GCN-NEXT: s_cmp_eq_u32 s14, 2
; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s0, 2 ; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_eq_u32 s14, 3
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s0, 3 ; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GCN-NEXT: buffer_store_dword v0, v[6:7], s[8:11], 0 addr64 ; GCN-NEXT: buffer_store_dword v0, v[6:7], s[8:11], 0 addr64
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%id.ext = sext i32 %id to i64 %id.ext = sext i32 %id to i64
%gep.in = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %in, i64 %id.ext %gep.in = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %in, i64 %id.ext
%gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %id.ext %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %id.ext
%vec = load <4 x i32>, <4 x i32> addrspace(1)* %gep.in %vec = load <4 x i32>, <4 x i32> addrspace(1)* %gep.in
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/vselect.ll

;RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s ;RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=FUNC %s ;RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=FUNC %s
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s
; FUNC-LABEL: {{^}}test_select_v2i32: ; FUNC-LABEL: {{^}}test_select_v2i32:
; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].Z ; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].Z
; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].Y ; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].Y
; VI: s_cmp_gt_i32 ; VI: s_cmp_gt_i32
; VI: s_cselect_b32 ; VI: s_cselect_b32
; VI: s_cmp_gt_i32 ; VI: s_cmp_gt_i32
; VI: s_cselect_b32 ; VI: s_cselect_b32
; SI: v_cmp_gt_i32_e32 vcc ; SI-DAG: s_cmp_gt_i32
; SI: v_cndmask_b32_e32 ; SI-DAG: v_cndmask_b32_e64
; SI: v_cmp_gt_i32_e32 vcc ; SI-DAG: s_cmp_gt_i32
; SI: v_cndmask_b32_e32 ; SI-DAG: v_cndmask_b32_e32
define amdgpu_kernel void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1, <2 x i32> %val) { define amdgpu_kernel void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1, <2 x i32> %val) {
entry: entry:
%load0 = load <2 x i32>, <2 x i32> addrspace(1)* %in0 %load0 = load <2 x i32>, <2 x i32> addrspace(1)* %in0
%load1 = load <2 x i32>, <2 x i32> addrspace(1)* %in1 %load1 = load <2 x i32>, <2 x i32> addrspace(1)* %in1
%cmp = icmp sgt <2 x i32> %load0, %load1 %cmp = icmp sgt <2 x i32> %load0, %load1
%result = select <2 x i1> %cmp, <2 x i32> %val, <2 x i32> %load0 %result = select <2 x i1> %cmp, <2 x i32> %val, <2 x i32> %load0
store <2 x i32> %result, <2 x i32> addrspace(1)* %out store <2 x i32> %result, <2 x i32> addrspace(1)* %out
Show All 27 Lines
; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].Z ; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].Z
; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].Y ; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].Y
; VI: s_cselect_b32 ; VI: s_cselect_b32
; VI: s_cselect_b32 ; VI: s_cselect_b32
; VI: s_cselect_b32 ; VI: s_cselect_b32
; VI: s_cselect_b32 ; VI: s_cselect_b32
; SI: v_cndmask_b32_e32 ; SI-DAG: v_cndmask_b32_e64
; SI: v_cndmask_b32_e32 ; SI-DAG: v_cndmask_b32_e64
; SI: v_cndmask_b32_e32 ; SI-DAG: v_cndmask_b32_e64
; SI: v_cndmask_b32_e32 ; SI-DAG: v_cndmask_b32_e32
define amdgpu_kernel void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1, <4 x i32> %val) { define amdgpu_kernel void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1, <4 x i32> %val) {
entry: entry:
%load0 = load <4 x i32>, <4 x i32> addrspace(1)* %in0 %load0 = load <4 x i32>, <4 x i32> addrspace(1)* %in0
%load1 = load <4 x i32>, <4 x i32> addrspace(1)* %in1 %load1 = load <4 x i32>, <4 x i32> addrspace(1)* %in1
%cmp = icmp sgt <4 x i32> %load0, %load1 %cmp = icmp sgt <4 x i32> %load0, %load1
%result = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %load0 %result = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %load0
store <4 x i32> %result, <4 x i32> addrspace(1)* %out store <4 x i32> %result, <4 x i32> addrspace(1)* %out
Show All 22 Lines

llvm/test/CodeGen/AMDGPU/wave32.ll

Show First 20 Lines • Show All 341 Lines • ▼ Show 20 Lines
; GFX1032: v_sub_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, {{[vs][0-9]+}}, v{{[0-9]+}}, vcc_lo ; GFX1032: v_sub_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, {{[vs][0-9]+}}, v{{[0-9]+}}, vcc_lo
; GFX1064: v_add_co_u32 v{{[0-9]+}}, [[SDST:s\[[0-9:]+\]]], v{{[0-9]+}}, v{{[0-9]+}} ; GFX1064: v_add_co_u32 v{{[0-9]+}}, [[SDST:s\[[0-9:]+\]]], v{{[0-9]+}}, v{{[0-9]+}}
; GFX1064: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}} ; GFX1064: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}
; GFX1064: v_add_co_ci_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, [[SDST]] ; GFX1064: v_add_co_ci_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, [[SDST]]
; GFX1064: v_add_co_u32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} ; GFX1064: v_add_co_u32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
; GFX1064: v_add_co_u32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} ; GFX1064: v_add_co_u32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
; GFX1064: v_add_co_u32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} ; GFX1064: v_add_co_u32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
; GFX1064: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}} ; GFX1064: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}
; GFX1064: v_sub_co_u32 v{{[0-9]+}}, s[{{[0-9:]+}}], s{{[0-9]+}}, v{{[0-9]+}} ; GFX1064: v_sub_co_u32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
; GFX1064: v_subrev_co_ci_u32_e64 v{{[0-9]+}}, vcc, {{[vs][0-9]+}}, v{{[0-9]+}}, s[{{[0-9:]+}}] ; GFX1064: v_subrev_co_ci_u32_e64 v{{[0-9]+}}, s[{{[0-9:]+}}], {{[vs][0-9]+}}, v{{[0-9]+}}, vcc
; GFX1064: v_sub_co_ci_u32_e64 v{{[0-9]+}}, s[{{[0-9:]+}}], {{[vs][0-9]+}}, v{{[0-9]+}}, s[{{[0-9:]+}}] ; GFX1064: v_sub_co_ci_u32_e32 v{{[0-9]+}}, vcc, {{[vs][0-9]+}}, v{{[0-9]+}}, vcc
define amdgpu_kernel void @test_udiv64(i64 addrspace(1)* %arg) #0 { define amdgpu_kernel void @test_udiv64(i64 addrspace(1)* %arg) #0 {
bb: bb:
%tmp = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 1 %tmp = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 1
%tmp1 = load i64, i64 addrspace(1)* %tmp, align 8 %tmp1 = load i64, i64 addrspace(1)* %tmp, align 8
%tmp2 = load i64, i64 addrspace(1)* %arg, align 8 %tmp2 = load i64, i64 addrspace(1)* %arg, align 8
%tmp3 = udiv i64 %tmp1, %tmp2 %tmp3 = udiv i64 %tmp1, %tmp2
%tmp4 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 2 %tmp4 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 2
store i64 %tmp3, i64 addrspace(1)* %tmp4, align 8 store i64 %tmp3, i64 addrspace(1)* %tmp4, align 8
▲ Show 20 Lines • Show All 835 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/zero_extend.ll

Show All 31 Lines
define amdgpu_kernel void @s_arg_zext_i1_to_i64(i64 addrspace(1)* %out, i1 zeroext %arg) #0 { define amdgpu_kernel void @s_arg_zext_i1_to_i64(i64 addrspace(1)* %out, i1 zeroext %arg) #0 {
%ext = zext i1 %arg to i64 %ext = zext i1 %arg to i64
store i64 %ext, i64 addrspace(1)* %out, align 8 store i64 %ext, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; GCN-LABEL: {{^}}s_cmp_zext_i1_to_i64: ; GCN-LABEL: {{^}}s_cmp_zext_i1_to_i64:
; GCN-DAG: s_mov_b32 s{{[0-9]+}}, 0 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, 0
; GCN-DAG: v_cmp_eq_u32 ; GCN-DAG: s_cmp_eq_u32
; GCN: v_cndmask_b32 ; GCN: v_cndmask_b32
define amdgpu_kernel void @s_cmp_zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) #0 { define amdgpu_kernel void @s_cmp_zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) #0 {
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
%ext = zext i1 %cmp to i64 %ext = zext i1 %cmp to i64
store i64 %ext, i64 addrspace(1)* %out, align 8 store i64 %ext, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; FIXME: Why different commute? ; FIXME: Why different commute?
; GCN-LABEL: {{^}}s_cmp_zext_i1_to_i16 ; GCN-LABEL: {{^}}s_cmp_zext_i1_to_i16
; GCN: s_load_dword [[A:s[0-9]+]] ; GCN: s_load_dword [[A:s[0-9]+]]
; GCN: s_load_dword [[B:s[0-9]+]] ; GCN: s_load_dword [[B:s[0-9]+]]
; GCN: s_mov_b32 [[MASK:s[0-9]+]], 0xffff{{$}} ; GCN: s_mov_b32 [[MASK:s[0-9]+]], 0xffff{{$}}
; GCN-DAG: s_and_b32 [[MASK_A:s[0-9]+]], [[A]], [[MASK]] ; GCN-DAG: s_and_b32 [[MASK_A:s[0-9]+]], [[A]], [[MASK]]
; GCN-DAG: s_and_b32 [[MASK_B:s[0-9]+]], [[B]], [[MASK]] ; GCN-DAG: s_and_b32 [[MASK_B:s[0-9]+]], [[B]], [[MASK]]
; GCN: v_mov_b32_e32 [[V_B:v[0-9]+]], [[B]] ; GCN: s_cmp_eq_u32 [[MASK_A]], [[B]]
; GCN: v_cmp_eq_u32_e32 vcc, [[MASK_A]], [[V_B]] ; GCN: s_cselect_b64 [[CC:s\[[0-9:]+\]]], -1, 0
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CC]]
; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
; GCN: buffer_store_short [[RESULT]] ; GCN: buffer_store_short [[RESULT]]
define amdgpu_kernel void @s_cmp_zext_i1_to_i16(i16 addrspace(1)* %out, [8 x i32], i16 zeroext %a, [8 x i32], i16 zeroext %b) #0 { define amdgpu_kernel void @s_cmp_zext_i1_to_i16(i16 addrspace(1)* %out, [8 x i32], i16 zeroext %a, [8 x i32], i16 zeroext %b) #0 {
%tmp0 = icmp eq i16 %a, %b %tmp0 = icmp eq i16 %a, %b
%tmp1 = zext i1 %tmp0 to i16 %tmp1 = zext i1 %tmp0 to i16
store i16 %tmp1, i16 addrspace(1)* %out store i16 %tmp1, i16 addrspace(1)* %out
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }