[RISCV][test] Add new tests for mul optimization in the zba extension with SH*ADD

[benshi001]

Summary

These tests will show the following optimization by future patches.

(mul x, 11) -> (SH1ADD (SH2ADD x, x), x)
(mul x, 19) -> (SH1ADD (SH3ADD x, x), x)
(mul x, 13) -> (SH2ADD (SH1ADD x, x), x)
(mul x, 21) -> (SH2ADD (SH2ADD x, x), x)
(mul x, 37) -> (SH2ADD (SH3ADD x, x), x)
(mul x, 25) -> (SH3ADD (SH1ADD x, x), x)
(mul x, 41) -> (SH3ADD (SH2ADD x, x), x)
(mul x, 73) -> (SH3ADD (SH3ADD x, x), x)

[benshi001]

Ping! I saw the similar optimization of mul with const on x86. So can the same be added to riscv ?

[craig.topper]

LGTM

llvm/test/CodeGen/RISCV/rv32zba.ll

 ; RV32IBA-LABEL: mul264:
 ; RV32IBA:       # %bb.0:
 ; RV32IBA-NEXT:    addi a1, zero, 264
 ; RV32IBA-NEXT:    mul a0, a0, a1
 ; RV32IBA-NEXT:    ret
   %c = mul i32 %a, 264
   ret i32 %c
 }
+
+define i32 @mul11(i32 %a) {
+; RV32I-LABEL: mul11:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 11
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: mul11:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    addi a1, zero, 11
+; RV32IB-NEXT:    mul a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBA-LABEL: mul11:
+; RV32IBA:       # %bb.0:
+; RV32IBA-NEXT:    addi a1, zero, 11
+; RV32IBA-NEXT:    mul a0, a0, a1
+; RV32IBA-NEXT:    ret
+  %c = mul i32 %a, 11
+  ret i32 %c
+}
+
+define i32 @mul19(i32 %a) {
+; RV32I-LABEL: mul19:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 19
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: mul19:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    addi a1, zero, 19
+; RV32IB-NEXT:    mul a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBA-LABEL: mul19:
+; RV32IBA:       # %bb.0:
+; RV32IBA-NEXT:    addi a1, zero, 19
+; RV32IBA-NEXT:    mul a0, a0, a1
+; RV32IBA-NEXT:    ret
+  %c = mul i32 %a, 19
+  ret i32 %c
+}
+
+define i32 @mul13(i32 %a) {
+; RV32I-LABEL: mul13:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 13
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: mul13:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    addi a1, zero, 13
+; RV32IB-NEXT:    mul a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBA-LABEL: mul13:
+; RV32IBA:       # %bb.0:
+; RV32IBA-NEXT:    addi a1, zero, 13
+; RV32IBA-NEXT:    mul a0, a0, a1
+; RV32IBA-NEXT:    ret
+  %c = mul i32 %a, 13
+  ret i32 %c
+}
+
+define i32 @mul21(i32 %a) {
+; RV32I-LABEL: mul21:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 21
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: mul21:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    addi a1, zero, 21
+; RV32IB-NEXT:    mul a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBA-LABEL: mul21:
+; RV32IBA:       # %bb.0:
+; RV32IBA-NEXT:    addi a1, zero, 21
+; RV32IBA-NEXT:    mul a0, a0, a1
+; RV32IBA-NEXT:    ret
+  %c = mul i32 %a, 21
+  ret i32 %c
+}
+
+define i32 @mul37(i32 %a) {
+; RV32I-LABEL: mul37:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 37
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: mul37:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    addi a1, zero, 37
+; RV32IB-NEXT:    mul a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBA-LABEL: mul37:
+; RV32IBA:       # %bb.0:
+; RV32IBA-NEXT:    addi a1, zero, 37
+; RV32IBA-NEXT:    mul a0, a0, a1
+; RV32IBA-NEXT:    ret
+  %c = mul i32 %a, 37
+  ret i32 %c
+}
+
+define i32 @mul25(i32 %a) {
+; RV32I-LABEL: mul25:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 25
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: mul25:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    addi a1, zero, 25
+; RV32IB-NEXT:    mul a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBA-LABEL: mul25:
+; RV32IBA:       # %bb.0:
+; RV32IBA-NEXT:    addi a1, zero, 25
+; RV32IBA-NEXT:    mul a0, a0, a1
+; RV32IBA-NEXT:    ret
+  %c = mul i32 %a, 25
+  ret i32 %c
+}
+
+define i32 @mul41(i32 %a) {
+; RV32I-LABEL: mul41:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 41
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: mul41:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    addi a1, zero, 41
+; RV32IB-NEXT:    mul a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBA-LABEL: mul41:
+; RV32IBA:       # %bb.0:
+; RV32IBA-NEXT:    addi a1, zero, 41
+; RV32IBA-NEXT:    mul a0, a0, a1
+; RV32IBA-NEXT:    ret
+  %c = mul i32 %a, 41
+  ret i32 %c
+}
+
+define i32 @mul73(i32 %a) {
+; RV32I-LABEL: mul73:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 73
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: mul73:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    addi a1, zero, 73
+; RV32IB-NEXT:    mul a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBA-LABEL: mul73:
+; RV32IBA:       # %bb.0:
+; RV32IBA-NEXT:    addi a1, zero, 73
+; RV32IBA-NEXT:    mul a0, a0, a1
+; RV32IBA-NEXT:    ret
+  %c = mul i32 %a, 73
+  ret i32 %c
+}

llvm/test/CodeGen/RISCV/rv64zba.ll

 ; RV64IBA-LABEL: imm_zextw2:
 ; RV64IBA:       # %bb.0:
 ; RV64IBA-NEXT:    lui a0, 699051
 ; RV64IBA-NEXT:    addiw a0, a0, -1366
 ; RV64IBA-NEXT:    zext.w a0, a0
 ; RV64IBA-NEXT:    ret
   ret i64 2863311530 ; 0xAAAAAAAA
 }
+
+define i64 @mul11(i64 %a) {
+; RV64I-LABEL: mul11:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 11
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mul11:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 11
+; RV64IB-NEXT:    mul a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mul11:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    addi a1, zero, 11
+; RV64IBA-NEXT:    mul a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i64 %a, 11
+  ret i64 %c
+}
+
+define i64 @mul19(i64 %a) {
+; RV64I-LABEL: mul19:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 19
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mul19:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 19
+; RV64IB-NEXT:    mul a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mul19:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    addi a1, zero, 19
+; RV64IBA-NEXT:    mul a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i64 %a, 19
+  ret i64 %c
+}
+
+define i64 @mul13(i64 %a) {
+; RV64I-LABEL: mul13:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 13
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mul13:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 13
+; RV64IB-NEXT:    mul a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mul13:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    addi a1, zero, 13
+; RV64IBA-NEXT:    mul a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i64 %a, 13
+  ret i64 %c
+}
+
+define i64 @mul21(i64 %a) {
+; RV64I-LABEL: mul21:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 21
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mul21:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 21
+; RV64IB-NEXT:    mul a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mul21:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    addi a1, zero, 21
+; RV64IBA-NEXT:    mul a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i64 %a, 21
+  ret i64 %c
+}
+
+define i64 @mul37(i64 %a) {
+; RV64I-LABEL: mul37:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 37
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mul37:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 37
+; RV64IB-NEXT:    mul a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mul37:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    addi a1, zero, 37
+; RV64IBA-NEXT:    mul a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i64 %a, 37
+  ret i64 %c
+}
+
+define i64 @mul25(i64 %a) {
+; RV64I-LABEL: mul25:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 25
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mul25:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 25
+; RV64IB-NEXT:    mul a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mul25:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    addi a1, zero, 25
+; RV64IBA-NEXT:    mul a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i64 %a, 25
+  ret i64 %c
+}
+
+define i64 @mul41(i64 %a) {
+; RV64I-LABEL: mul41:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 41
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mul41:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 41
+; RV64IB-NEXT:    mul a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mul41:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    addi a1, zero, 41
+; RV64IBA-NEXT:    mul a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i64 %a, 41
+  ret i64 %c
+}
+
+define i64 @mul73(i64 %a) {
+; RV64I-LABEL: mul73:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 73
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mul73:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 73
+; RV64IB-NEXT:    mul a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mul73:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    addi a1, zero, 73
+; RV64IBA-NEXT:    mul a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i64 %a, 73
+  ret i64 %c
+}