[PowerPC] Implement intrinsics for mtfsf[i]

[nemanjai]

Summary

This provides intrinsics for emitting instructions that set the FPSCR (mtfsf/mtfsfi).

The patch also conservatively marks the rounding mode as an implicit def for both since they both may set the rounding mode depending on the operands.

[nemanjai]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

4489

@ZhangKang You modified this code most recently. Please provide your opinion here.

[qiucf]

The PPC instructions tablegen part looks good to me.

llvm/include/llvm/IR/IntrinsicsPowerPC.td

1642

If mtfsf was changed, mtfsfi mtfsb0 mtfsb1 should also be changed?

[nemanjai]

llvm/include/llvm/IR/IntrinsicsPowerPC.td

1642

There is no need for custom code generation for those. The reason we had to change mtfsf is because we need to take an integer and convert it to a double (and not a bitcast, but a uinttofp which I found a bit surprising).

clang/lib/CodeGen/CGBuiltin.cpp

#include "clang/Basic/BuiltinsPPC.def"
   case PPC::BI__builtin_ppc_lwarx:
     return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
   case PPC::BI__builtin_ppc_popcntb: {
     Value *ArgValue = EmitScalarExpr(E->getArg(0));
     llvm::Type *ArgType = ArgValue->getType();
     Function *F = CGM.getIntrinsic(Intrinsic::ppc_popcntb, {ArgType, ArgType});
     return Builder.CreateCall(F, Ops, "popcntb");
   }
+  case PPC::BI__builtin_ppc_mtfsf: {
+    // The builtin takes a uint32 that needs to be cast to an
+    // f64 to be passed to the intrinsic.
+    Value *Cast = Builder.CreateUIToFP(Ops[1], DoubleTy);
+    llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_mtfsf);
+    return Builder.CreateCall(F, {Ops[0], Cast}, "");
+  }
   }
 }
 
 namespace {
 // If \p E is not null pointer, insert address space cast to match return
 // type of \p E if necessary.
 Value *EmitAMDGPUDispatchPtr(CodeGenFunction &CGF,
                              const CallExpr *E = nullptr) {

clang/test/CodeGen/builtins-ppc-xlcompat-math.c

 // CHECK:         call void @llvm.ppc.mtfsb1(i32 0)
 // CHECK-NEXT:    ret void
 //
 void mtfsb1 () {
   __mtfsb1 (0);
 }
 
 // CHECK-LABEL: @mtfsf(
-// CHECK:         [[UI_ADDR:%.*]] = alloca i32, align 4
-// CHECK-NEXT:    store i32 [[UI:%.*]], i32* [[UI_ADDR]], align 4
-// CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[UI_ADDR]], align 4
-// CHECK-NEXT:    call void @llvm.ppc.mtfsf(i32 8, i32 [[TMP0]])
+// CHECK:         [[TMP0:%.*]] = uitofp i32 %{{.*}} to double
+// CHECK-NEXT:    call void @llvm.ppc.mtfsf(i32 8, double [[TMP0]])
 // CHECK-NEXT:    ret void
 //
 void mtfsf (unsigned int ui) {
   __mtfsf (8, ui);
 }
 
 // CHECK-LABEL: @mtfsfi(
 // CHECK:         call void @llvm.ppc.mtfsfi(i32 7, i32 15)

llvm/include/llvm/IR/IntrinsicsPowerPC.td

// FIXME: __icbt is only valid for pwr8 and up.
   def int_ppc_mtfsb0
       : GCCBuiltin<"__builtin_ppc_mtfsb0">,
         Intrinsic <[], [llvm_i32_ty],
                    [IntrNoMem, IntrHasSideEffects, ImmArg<ArgIndex<0>>]>;
   def int_ppc_mtfsb1
       : GCCBuiltin<"__builtin_ppc_mtfsb1">,
         Intrinsic <[], [llvm_i32_ty],
                    [IntrNoMem, IntrHasSideEffects, ImmArg<ArgIndex<0>>]>;
-  def int_ppc_mtfsf
-      : GCCBuiltin<"__builtin_ppc_mtfsf">,
-        Intrinsic <[], [llvm_i32_ty, llvm_i32_ty],
+  def int_ppc_mtfsf :
+        Intrinsic <[], [llvm_i32_ty, llvm_double_ty],
                    [IntrNoMem, IntrHasSideEffects, ImmArg<ArgIndex<0>>]>;
   def int_ppc_mtfsfi
       : GCCBuiltin<"__builtin_ppc_mtfsfi">,
         Intrinsic <[], [llvm_i32_ty, llvm_i32_ty],
                    [IntrNoMem, IntrHasSideEffects,
                     ImmArg<ArgIndex<0>>,ImmArg<ArgIndex<1>>]>;
   def int_ppc_fmsub
       : GCCBuiltin<"__builtin_ppc_fmsub">,
         Intrinsic <[llvm_double_ty],
                    [llvm_double_ty, llvm_double_ty, llvm_double_ty],

llvm/lib/Target/PowerPC/P9InstrResources.td

 // Here the two ALU ops can actually be done in parallel and therefore the
 // latencies are not added together. Otherwise this is like having two
 // instructions running together on two pipelines and 6 dispatches.
 // ALU ops are 3 cycles each.
 def : InstRW<[P9_ALU_3C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_3SLOTS_1C],
       (instrs
     (instregex "MTFSF(b|_rec)?$"),
-    (instregex "MTFSFI(_rec)?$")
+    (instregex "MTFSFI(_rec)?$"),
+    MTFSFIb
 )>;
 
 // Cracked instruction made of two ALU ops.
 // The two ops cannot be done in parallel.
 // One of the ALU ops is restricted and takes 3 dispatches.
 def : InstRW<[P9_ALUOpAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
                       "mtfsb1 $FM", IIC_IntMTFSB0,
                       [(int_ppc_mtfsb1 timm:$FM)]>,
              PPC970_DGroup_Single, PPC970_Unit_FPU;
 }
 
 let Defs = [RM] in {
   let isCodeGenOnly = 1 in
   def MTFSFb  : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
-                        "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
+                        "mtfsf $FM, $rT", IIC_IntMTFSB0,
+                        [(int_ppc_mtfsf timm:$FM, f64:$rT)]>,
                 PPC970_DGroup_Single, PPC970_Unit_FPU;
 }
 let Uses = [RM] in {
   def MFFS   : XForm_42<63, 583, (outs f8rc:$rT), (ins),
                          "mffs $rT", IIC_IntMFFS,
                          [(set f64:$rT, (PPCmffs))]>,
                PPC970_DGroup_Single, PPC970_Unit_FPU;
 
def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
                   "mfmsr $RT", IIC_SprMFMSR, []>;
 
 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, u1imm:$L),
                     "mtmsrd $RS, $L", IIC_SprMTMSRD>;
 
 def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
                      "mcrfs $BF, $BFA", IIC_BrMCR>;
 
-// If W is 0 and BF is 7, the 60:63 bits will be set, we should set the
-// implicit-def RM.
-def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
+// All MTFSF variants may change the rounding mode so conservatively set it
+// as an implicit def for all of them.
+let Predicates = [HasFPU] in {
+let Defs = [RM] in {
+let isCodeGenOnly = 1,
+    Pattern = [(int_ppc_mtfsfi timm:$BF, timm:$U)], W = 0 in
+def MTFSFIb : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U),
+                       "mtfsfi $BF, $U", IIC_IntMFFS>;
+def MTFSFI : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, i32imm:$W),
                       "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
 let Defs = [CR1] in
-def MTFSFI_rec : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
+def MTFSFI_rec : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, u1imm:$W),
                        "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm;
 
-def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
-def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec crrc:$BF, i32imm:$U, 0)>;
-
-let Predicates = [HasFPU] in {
-let Defs = [RM] in {
 def MTFSF : XFLForm_1<63, 711, (outs),
                       (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W),
                       "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
 let Defs = [CR1] in
 def MTFSF_rec : XFLForm_1<63, 711, (outs),
                        (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W),
                        "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm;
 }
 
+def : InstAlias<"mtfsfi $BF, $U", (MTFSFI u3imm:$BF, u4imm:$U, 0)>;
+def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec u3imm:$BF, u4imm:$U, 0)>;
 def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
 def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>;
 }
 
 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
                         "slbie $RB", IIC_SprSLBIE, []>;
 
 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s |\
 ; RUN:   FileCheck %s --check-prefix=CHECK-PWR8
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
 ; RUN:   < %s | FileCheck %s --check-prefix=CHECK-PWR7
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s |\
 ; RUN:   FileCheck %s --check-prefix=CHECK-PWR8
 
-define dso_local void @mtfsb0() {
-; CHECK-PWR8-LABEL: mtfsb0:
-; CHECK-PWR8:       # %bb.0: # %entry
-; CHECK-PWR8-NEXT:    mtfsb0 10
-; CHECK-PWR8-NEXT:    blr
-;
-; CHECK-NOVSX-LABEL: mtfsb0:
-; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    mtfsb0 10
-; CHECK-NOVSX-NEXT:    blr
-;
-; CHECK-PWR7-LABEL: mtfsb0:
-; CHECK-PWR7:       # %bb.0: # %entry
-; CHECK-PWR7-NEXT:    mtfsb0 10
-; CHECK-PWR7-NEXT:    blr
-entry:
-  tail call void @llvm.ppc.mtfsb0(i32 10)
-  ret void
-}
-
-declare void @llvm.ppc.mtfsb0(i32 immarg) #1
-
-define dso_local void @mtfsb1() {
-; CHECK-PWR8-LABEL: mtfsb1:
-; CHECK-PWR8:       # %bb.0: # %entry
-; CHECK-PWR8-NEXT:    mtfsb1 0
-; CHECK-PWR8-NEXT:    blr
-;
-; CHECK-NOVSX-LABEL: mtfsb1:
-; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    mtfsb1 0
-; CHECK-NOVSX-NEXT:    blr
-;
-; CHECK-PWR7-LABEL: mtfsb1:
-; CHECK-PWR7:       # %bb.0: # %entry
-; CHECK-PWR7-NEXT:    mtfsb1 0
-; CHECK-PWR7-NEXT:    blr
-entry:
-  tail call void @llvm.ppc.mtfsb1(i32 0)
-  ret void
-}
-
-declare void @llvm.ppc.mtfsb1(i32 immarg) #1
-
 define dso_local double @fmsub_t0(double %d, double %d2, double %d3) {
 ; CHECK-PWR8-LABEL: fmsub_t0:
 ; CHECK-PWR8:       # %bb.0: # %entry
 ; CHECK-PWR8-NEXT:    xsmsubmdp 1, 2, 3
 ; CHECK-PWR8-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: fmsub_t0:
 ; CHECK-NOVSX:       # %bb.0: # %entry

llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | \
+; RUN:   FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-AIX64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-AIX32
+
+define dso_local void @mtfsb0() local_unnamed_addr #0 {
+; CHECK-PWR8-LABEL: mtfsb0:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    mtfsb0 10
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: mtfsb0:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    mtfsb0 10
+; CHECK-PWR7-NEXT:    blr
+; CHECK-LABEL: mtfsb0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtfsb0 10
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX64-LABEL: mtfsb0:
+; CHECK-AIX64:       # %bb.0: # %entry
+; CHECK-AIX64-NEXT:    mtfsb0 10
+; CHECK-AIX64-NEXT:    blr
+;
+; CHECK-AIX32-LABEL: mtfsb0:
+; CHECK-AIX32:       # %bb.0: # %entry
+; CHECK-AIX32-NEXT:    mtfsb0 10
+; CHECK-AIX32-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.mtfsb0(i32 10)
+  ret void
+}
+
+define dso_local void @mtfsb1() local_unnamed_addr #0 {
+; CHECK-PWR8-LABEL: mtfsb1:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    mtfsb1 0
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: mtfsb1:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    mtfsb1 0
+; CHECK-PWR7-NEXT:    blr
+; CHECK-LABEL: mtfsb1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtfsb1 0
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX64-LABEL: mtfsb1:
+; CHECK-AIX64:       # %bb.0: # %entry
+; CHECK-AIX64-NEXT:    mtfsb1 0
+; CHECK-AIX64-NEXT:    blr
+;
+; CHECK-AIX32-LABEL: mtfsb1:
+; CHECK-AIX32:       # %bb.0: # %entry
+; CHECK-AIX32-NEXT:    mtfsb1 0
+; CHECK-AIX32-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.mtfsb1(i32 0)
+  ret void
+}
+
+define dso_local void @callmtfsf(i32 zeroext %a) local_unnamed_addr {
+; CHECK-LABEL: callmtfsf:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtfprwz 0, 3
+; CHECK-NEXT:    xscvuxddp 0, 0
+; CHECK-NEXT:    mtfsf 7, 0
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX64-LABEL: callmtfsf:
+; CHECK-AIX64:       # %bb.0: # %entry
+; CHECK-AIX64-NEXT:    addi 4, 1, -4
+; CHECK-AIX64-NEXT:    stw 3, -4(1)
+; CHECK-AIX64-NEXT:    lfiwzx 0, 0, 4
+; CHECK-AIX64-NEXT:    xscvuxddp 0, 0
+; CHECK-AIX64-NEXT:    mtfsf 7, 0
+; CHECK-AIX64-NEXT:    blr
+;
+; CHECK-AIX32-LABEL: callmtfsf:
+; CHECK-AIX32:       # %bb.0: # %entry
+; CHECK-AIX32-NEXT:    addi 4, 1, -4
+; CHECK-AIX32-NEXT:    stw 3, -4(1)
+; CHECK-AIX32-NEXT:    lfiwzx 0, 0, 4
+; CHECK-AIX32-NEXT:    xscvuxddp 0, 0
+; CHECK-AIX32-NEXT:    mtfsf 7, 0
+; CHECK-AIX32-NEXT:    blr
+entry:
+  %0 = uitofp i32 %a to double
+  tail call void @llvm.ppc.mtfsf(i32 7, double %0)
+  ret void
+}
+
+define dso_local void @callmtfsfi(i32 zeroext %a) local_unnamed_addr {
+; CHECK-LABEL: callmtfsfi:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtfsfi 1, 3
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX64-LABEL: callmtfsfi:
+; CHECK-AIX64:       # %bb.0: # %entry
+; CHECK-AIX64-NEXT:    mtfsfi 1, 3
+; CHECK-AIX64-NEXT:    blr
+;
+; CHECK-AIX32-LABEL: callmtfsfi:
+; CHECK-AIX32:       # %bb.0: # %entry
+; CHECK-AIX32-NEXT:    mtfsfi 1, 3
+; CHECK-AIX32-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.mtfsfi(i32 1, i32 3)
+  ret void
+}
+
+declare void @llvm.ppc.mtfsb0(i32)
+declare void @llvm.ppc.mtfsb1(i32)
+declare void @llvm.ppc.mtfsfi(i32, i32)
+declare void @llvm.ppc.mtfsf(i32, double)