[MachineVerifier] Diagnose invalid INSERT_SUBREGs

[jroelofs]

hm. This breaks: llvm/test/CodeGen/X86/domain-reassignment.mir

%9:gr32 = INSERT_SUBREG %8:gr32(tied-def 0), %17:gr16, %subreg.sub_8bit_hi_phony

[jroelofs]

Fix llvm/test/CodeGen/X86/domain-reassignment.mir to not rely on magic constants.

[arsenm]

llvm/lib/CodeGen/MachineVerifier.cpp

1786

This is already TRI tin the verifier class

llvm/test/MachineVerifier/test_insert_subreg.mir

2

-global-isel doesn't do anything with -run-pass

[thakis]

This seems to break tests: http://45.33.8.238/linux/51314/step_12.txt

Please take a look.

[jroelofs]

Reverted for the moment while I work out what broke.

Thanks thakis!

[jroelofs]

One of the two issues in the tests was easily fixable:
https://reviews.llvm.org/D106168

The other issue appears to be much trickier, as it stems from the ARM backend treating MPR regs as if they were ssub subregs. This causes a contradiction in sizes, since ssub's are 32 bits whereas MPR regs are fp16's.

[uabelho]

llvm/lib/CodeGen/MachineVerifier.cpp

1787

Don't you need to take operand 2's subreg into account here?

I'm seeing failures for cases where

MI->getOperand(2).getReg()

is indeed too big, but

MI->getOperand(2).getSubReg()

is specifying a subreg of a small enough size so there is no problem.

[uabelho]

llvm/lib/CodeGen/MachineVerifier.cpp

1787

This seems to work better for me:

unsigned InsertedSize;
if (unsigned SubIdx = MI->getOperand(2).getSubReg())
  InsertedSize = TRI->getSubRegIdxSize(SubIdx);
else
  InsertedSize =
    TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);

[jroelofs]

llvm/lib/CodeGen/MachineVerifier.cpp

1787

Good call, thanks!

4de74a7c4da3516d0d9119452cc073b061716b5d

llvm/lib/CodeGen/MachineVerifier.cpp

       if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
         report("STATEPOINT def tied to non-gc operand", MI);
         break;
       }
     }
 
     // TODO: verify we have properly encoded deopt arguments
   } break;
+  case TargetOpcode::INSERT_SUBREG: {
+    const auto &TRI = MRI->getTargetRegisterInfo();
+    unsigned InsertedSize =
+        TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
+    unsigned SubRegSize = TRI->getSubRegIdxSize(MI->getOperand(3).getImm());
+    if (InsertedSize != SubRegSize) {
+      report("INSERT_SUBREG expected matching subreg size for operand 2", MI);
+      break;
+    }
+  } break;
   }
 }
 
 void
 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
   const MachineInstr *MI = MO->getParent();
   const MCInstrDesc &MCID = MI->getDesc();
   unsigned NumDefs = MCID.getNumDefs();

llvm/test/MachineVerifier/test_insert_subreg.mir

+#RUN: not --crash llc -march=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+---
+name:            test_insert_subreg
+legalized:       true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+    liveins: $s0, $h1
+
+    %0:fpr32 = COPY $s0
+
+    ; CHECK: *** Bad machine code: INSERT_SUBREG expected matching subreg size for operand 2 ***
+    %1:fpr128 = IMPLICIT_DEF
+    %2:fpr128 = INSERT_SUBREG %1:fpr128, %0:fpr32, %subreg.hsub
+
+    ; CHECK: *** Bad machine code: INSERT_SUBREG expected matching subreg size for operand 2 ***
+    %3:fpr128 = IMPLICIT_DEF
+    %4:fpr128 = INSERT_SUBREG %3:fpr128, %0:fpr32, %subreg.dsub
+
+    ; CHECK-NOT: *** Bad machine code:
+    %7:fpr128 = IMPLICIT_DEF
+    %8:fpr128 = INSERT_SUBREG %7:fpr128, %0:fpr32, %subreg.ssub
+
+...