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LGTM with test nit
| llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir | ||
|---|---|---|
| 549 | You can drop the alignment, registers, liveins, frameInfo, and machineFunctionInfo bits here. | |
clang-format: please reformat the code
- .legalForTypesWithMemDesc({{s8, p0, s8, 8}, - {s16, p0, s8, 8}, // truncstorei8 from s16 - {s32, p0, s8, 8}, // truncstorei8 from s32 - {s64, p0, s8, 8}, // truncstorei8 from s64 - {s16, p0, s16, 8}, - {s32, p0, s16, 8}, // truncstorei16 from s32 - {s64, p0, s16, 8}, // truncstorei16 from s64 - {s32, p0, s8, 8}, - {s32, p0, s16, 8}, - {s32, p0, s32, 8},22 diff lines are omitted. See full path.