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Differential D105580

[MLIR] Provide lowering of std switch to llvm switch
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Authored by wsmoses on Jul 7 2021, 12:15 PM.

Details

Reviewers
ftynse
nicolasvasilache
rriddle
mehdi_amini
Commits
rGeaf22ba0118a: [MLIR] Provide lowering of std switch to llvm switch
Summary

This patch allows lowering of std switch to llvm switch

Diff Detail

Event Timeline

wsmoses created this revision.Jul 7 2021, 12:15 PM
Herald added subscribers: dcaballe, cota, teijeong and 14 others. · View Herald TranscriptJul 7 2021, 12:15 PM
wsmoses requested review of this revision.Jul 7 2021, 12:15 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 7 2021, 12:15 PM
Herald added a subscriber: stephenneuendorffer. · View Herald Transcript
mehdi_amini accepted this revision.Jul 7 2021, 12:23 PM
This revision is now accepted and ready to land.Jul 7 2021, 12:23 PM
This revision was landed with ongoing or failed builds.Jul 7 2021, 12:26 PM
Closed by commit rGeaf22ba0118a: [MLIR] Provide lowering of std switch to llvm switch (authored by wsmoses). · Explain Why
This revision was automatically updated to reflect the committed changes.
wsmoses added a commit: rGeaf22ba0118a: [MLIR] Provide lowering of std switch to llvm switch.
Harbormaster completed remote builds in B112840: Diff 357041.Jul 7 2021, 12:52 PM

Revision Contents

PathSize
mlir/
lib/
Conversion/
StandardToLLVM/
5 lines
test/
Conversion/
StandardToLLVM/
21 lines

Diff 357045

mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp

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struct BranchOpLowering struct BranchOpLowering
: public OneToOneLLVMTerminatorLowering<BranchOp, LLVM::BrOp> { : public OneToOneLLVMTerminatorLowering<BranchOp, LLVM::BrOp> {
using Super::Super; using Super::Super;
}; };
struct CondBranchOpLowering struct CondBranchOpLowering
: public OneToOneLLVMTerminatorLowering<CondBranchOp, LLVM::CondBrOp> { : public OneToOneLLVMTerminatorLowering<CondBranchOp, LLVM::CondBrOp> {
using Super::Super; using Super::Super;
}; };
struct SwitchOpLowering
: public OneToOneLLVMTerminatorLowering<SwitchOp, LLVM::SwitchOp> {
using Super::Super;
};
// The Splat operation is lowered to an insertelement + a shufflevector // The Splat operation is lowered to an insertelement + a shufflevector
// operation. Splat to only 1-d vector result types are lowered. // operation. Splat to only 1-d vector result types are lowered.
struct SplatOpLowering : public ConvertOpToLLVMPattern<SplatOp> { struct SplatOpLowering : public ConvertOpToLLVMPattern<SplatOp> {
using ConvertOpToLLVMPattern<SplatOp>::ConvertOpToLLVMPattern; using ConvertOpToLLVMPattern<SplatOp>::ConvertOpToLLVMPattern;
LogicalResult LogicalResult
matchAndRewrite(SplatOp splatOp, ArrayRef<Value> operands, matchAndRewrite(SplatOp splatOp, ArrayRef<Value> operands,
▲ Show 20 Lines • Show All 671 Lines • ▼ Show 20 Lines patterns.add<
SignedRemIOpLowering, SignedRemIOpLowering,
SignedShiftRightOpLowering, SignedShiftRightOpLowering,
SinOpLowering, SinOpLowering,
SplatOpLowering, SplatOpLowering,
SplatNdOpLowering, SplatNdOpLowering,
SqrtOpLowering, SqrtOpLowering,
SubFOpLowering, SubFOpLowering,
SubIOpLowering, SubIOpLowering,
SwitchOpLowering,
TruncateIOpLowering, TruncateIOpLowering,
UIToFPOpLowering, UIToFPOpLowering,
UnsignedDivIOpLowering, UnsignedDivIOpLowering,
UnsignedRemIOpLowering, UnsignedRemIOpLowering,
UnsignedShiftRightOpLowering, UnsignedShiftRightOpLowering,
XOrOpLowering, XOrOpLowering,
ZeroExtendIOpLowering>(converter); ZeroExtendIOpLowering>(converter);
// clang-format on // clang-format on
▲ Show 20 Lines • Show All 169 Lines • Show Last 20 Lines

mlir/test/Conversion/StandardToLLVM/convert-to-llvmir.mlir

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// CHECK-NEXT: %[[SIZE_PTR:.*]] = llvm.getelementptr %[[OFFSET_PTR]]{{\[}} // CHECK-NEXT: %[[SIZE_PTR:.*]] = llvm.getelementptr %[[OFFSET_PTR]]{{\[}}
// CHECK-SAME: %[[INDEX_INC]]] : (!llvm.ptr<i64>, i64) -> !llvm.ptr<i64> // CHECK-SAME: %[[INDEX_INC]]] : (!llvm.ptr<i64>, i64) -> !llvm.ptr<i64>
// CHECK-NEXT: %[[SIZE:.*]] = llvm.load %[[SIZE_PTR]] : !llvm.ptr<i64> // CHECK-NEXT: %[[SIZE:.*]] = llvm.load %[[SIZE_PTR]] : !llvm.ptr<i64>
// CHECK-NEXT: llvm.return %[[SIZE]] : i64 // CHECK-NEXT: llvm.return %[[SIZE]] : i64
// CHECK32: %[[SIZE:.*]] = llvm.load %{{.*}} : !llvm.ptr<i32> // CHECK32: %[[SIZE:.*]] = llvm.load %{{.*}} : !llvm.ptr<i32>
// CHECK32-NEXT: llvm.return %[[SIZE]] : i32 // CHECK32-NEXT: llvm.return %[[SIZE]] : i32
// -----
func @switchLower(%arg0: i32, %arg1 : i32, %arg2 : i32) -> i32 {
switch %arg0 : i32, [
default: ^bb2,
115: ^bb1
]
^bb1:
llvm.return %arg1 : i32
^bb2:
llvm.return %arg2 : i32
}
// CHECK: llvm.switch %arg0, ^[[bb2:.+]] [
// CHECK-NEXT: 115: ^[[bb1:.+]]
// CHECK-NEXT: ]
// CHECK: ^[[bb1]]:
// CHECK: llvm.return %arg1 : i32
// CHECK: ^[[bb2]]:
// CHECK: llvm.return %arg2 : i32