[RISCV] Optimize add-mul in the zba extension with SH*ADD

[benshi001]

Summary

This patch does the following optimization.

Rx + Ry * 18 => (SH1ADD (SH3ADD Rx, Rx), Ry)
Rx + Ry * 20 => (SH2ADD (SH2ADD Rx, Rx), Ry)
Rx + Ry * 24 => (SH3ADD (SH1ADD Rx, Rx), Ry)
Rx + Ry * 36 => (SH2ADD (SH3ADD Rx, Rx), Ry)
Rx + Ry * 40 => (SH3ADD (SH2ADD Rx, Rx), Ry)
Rx + Ry * 72 => (SH3ADD (SH3ADD Rx, Rx), Ry)

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfo.td

def SLLIUWPat : PatFrag<(ops node:$A, node:$B),
                         (and (shl node:$A, node:$B), imm), [{
   return MatchSLLIUW(N);
 }]>;
 
 def add_oneuse : PatFrag<(ops node:$A, node:$B), (add node:$A, node:$B), [{
   return N->hasOneUse();
 }]>;
 
+def mul_oneuse : PatFrag<(ops node:$A, node:$B), (mul node:$A, node:$B), [{
+  return N->hasOneUse();
+}]>;
+
 /// Simple arithmetic operations
 
 def : PatGprGpr<add, ADD>;
 def : PatGprSimm12<add, ADDI>;
 def : PatGprGpr<sub, SUB>;
 def : PatGprGpr<or, OR>;
 def : PatGprSimm12<or, ORI>;
 def : PatGprGpr<and, AND>;

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 
 let Predicates = [HasStdExtZba] in {
 def : Pat<(add (shl GPR:$rs1, (XLenVT 1)), GPR:$rs2),
           (SH1ADD GPR:$rs1, GPR:$rs2)>;
 def : Pat<(add (shl GPR:$rs1, (XLenVT 2)), GPR:$rs2),
           (SH2ADD GPR:$rs1, GPR:$rs2)>;
 def : Pat<(add (shl GPR:$rs1, (XLenVT 3)), GPR:$rs2),
           (SH3ADD GPR:$rs1, GPR:$rs2)>;
+
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 6)), GPR:$rs2),
+          (SH1ADD (SH1ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 10)), GPR:$rs2),
+          (SH1ADD (SH2ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 18)), GPR:$rs2),
+          (SH1ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 12)), GPR:$rs2),
+          (SH2ADD (SH1ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 20)), GPR:$rs2),
+          (SH2ADD (SH2ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 36)), GPR:$rs2),
+          (SH2ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 24)), GPR:$rs2),
+          (SH3ADD (SH1ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 40)), GPR:$rs2),
+          (SH3ADD (SH2ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 72)), GPR:$rs2),
+          (SH3ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
 } // Predicates = [HasStdExtZba]
 
 let Predicates = [HasStdExtZba, IsRV64] in {
 def : Pat<(i64 (SLLIUWPat GPR:$rs1, uimm5:$shamt)),
           (SLLIUW GPR:$rs1, uimm5:$shamt)>;
 def : Pat<(i64 (shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt)),
           (SLLIUW GPR:$rs1, uimm5:$shamt)>;
 def : Pat<(i64 (add (and GPR:$rs1, 0xFFFFFFFF), GPR:$rs2)),

llvm/test/CodeGen/RISCV/rv32zba.ll

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 6
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: addmul6:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a2, zero, 6
-; RV32IB-NEXT:    mul a0, a0, a2
-; RV32IB-NEXT:    add a0, a0, a1
+; RV32IB-NEXT:    sh1add a0, a0, a0
+; RV32IB-NEXT:    sh1add a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBA-LABEL: addmul6:
 ; RV32IBA:       # %bb.0:
-; RV32IBA-NEXT:    addi a2, zero, 6
-; RV32IBA-NEXT:    mul a0, a0, a2
-; RV32IBA-NEXT:    add a0, a0, a1
+; RV32IBA-NEXT:    sh1add a0, a0, a0
+; RV32IBA-NEXT:    sh1add a0, a0, a1
 ; RV32IBA-NEXT:    ret
   %c = mul i32 %a, 6
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul10(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul10:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 10
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: addmul10:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a2, zero, 10
-; RV32IB-NEXT:    mul a0, a0, a2
-; RV32IB-NEXT:    add a0, a0, a1
+; RV32IB-NEXT:    sh2add a0, a0, a0
+; RV32IB-NEXT:    sh1add a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBA-LABEL: addmul10:
 ; RV32IBA:       # %bb.0:
-; RV32IBA-NEXT:    addi a2, zero, 10
-; RV32IBA-NEXT:    mul a0, a0, a2
-; RV32IBA-NEXT:    add a0, a0, a1
+; RV32IBA-NEXT:    sh2add a0, a0, a0
+; RV32IBA-NEXT:    sh1add a0, a0, a1
 ; RV32IBA-NEXT:    ret
   %c = mul i32 %a, 10
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul12(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul12:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 12
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: addmul12:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a2, zero, 12
-; RV32IB-NEXT:    mul a0, a0, a2
-; RV32IB-NEXT:    add a0, a0, a1
+; RV32IB-NEXT:    sh1add a0, a0, a0
+; RV32IB-NEXT:    sh2add a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBA-LABEL: addmul12:
 ; RV32IBA:       # %bb.0:
-; RV32IBA-NEXT:    addi a2, zero, 12
-; RV32IBA-NEXT:    mul a0, a0, a2
-; RV32IBA-NEXT:    add a0, a0, a1
+; RV32IBA-NEXT:    sh1add a0, a0, a0
+; RV32IBA-NEXT:    sh2add a0, a0, a1
 ; RV32IBA-NEXT:    ret
   %c = mul i32 %a, 12
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul18(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul18:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 18
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: addmul18:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a2, zero, 18
-; RV32IB-NEXT:    mul a0, a0, a2
-; RV32IB-NEXT:    add a0, a0, a1
+; RV32IB-NEXT:    sh3add a0, a0, a0
+; RV32IB-NEXT:    sh1add a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBA-LABEL: addmul18:
 ; RV32IBA:       # %bb.0:
-; RV32IBA-NEXT:    addi a2, zero, 18
-; RV32IBA-NEXT:    mul a0, a0, a2
-; RV32IBA-NEXT:    add a0, a0, a1
+; RV32IBA-NEXT:    sh3add a0, a0, a0
+; RV32IBA-NEXT:    sh1add a0, a0, a1
 ; RV32IBA-NEXT:    ret
   %c = mul i32 %a, 18
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul20(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul20:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 20
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: addmul20:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a2, zero, 20
-; RV32IB-NEXT:    mul a0, a0, a2
-; RV32IB-NEXT:    add a0, a0, a1
+; RV32IB-NEXT:    sh2add a0, a0, a0
+; RV32IB-NEXT:    sh2add a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBA-LABEL: addmul20:
 ; RV32IBA:       # %bb.0:
-; RV32IBA-NEXT:    addi a2, zero, 20
-; RV32IBA-NEXT:    mul a0, a0, a2
-; RV32IBA-NEXT:    add a0, a0, a1
+; RV32IBA-NEXT:    sh2add a0, a0, a0
+; RV32IBA-NEXT:    sh2add a0, a0, a1
 ; RV32IBA-NEXT:    ret
   %c = mul i32 %a, 20
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul24(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul24:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 24
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: addmul24:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a2, zero, 24
-; RV32IB-NEXT:    mul a0, a0, a2
-; RV32IB-NEXT:    add a0, a0, a1
+; RV32IB-NEXT:    sh1add a0, a0, a0
+; RV32IB-NEXT:    sh3add a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBA-LABEL: addmul24:
 ; RV32IBA:       # %bb.0:
-; RV32IBA-NEXT:    addi a2, zero, 24
-; RV32IBA-NEXT:    mul a0, a0, a2
-; RV32IBA-NEXT:    add a0, a0, a1
+; RV32IBA-NEXT:    sh1add a0, a0, a0
+; RV32IBA-NEXT:    sh3add a0, a0, a1
 ; RV32IBA-NEXT:    ret
   %c = mul i32 %a, 24
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul36(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul36:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 36
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: addmul36:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a2, zero, 36
-; RV32IB-NEXT:    mul a0, a0, a2
-; RV32IB-NEXT:    add a0, a0, a1
+; RV32IB-NEXT:    sh3add a0, a0, a0
+; RV32IB-NEXT:    sh2add a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBA-LABEL: addmul36:
 ; RV32IBA:       # %bb.0:
-; RV32IBA-NEXT:    addi a2, zero, 36
-; RV32IBA-NEXT:    mul a0, a0, a2
-; RV32IBA-NEXT:    add a0, a0, a1
+; RV32IBA-NEXT:    sh3add a0, a0, a0
+; RV32IBA-NEXT:    sh2add a0, a0, a1
 ; RV32IBA-NEXT:    ret
   %c = mul i32 %a, 36
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul40(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul40:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 40
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: addmul40:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a2, zero, 40
-; RV32IB-NEXT:    mul a0, a0, a2
-; RV32IB-NEXT:    add a0, a0, a1
+; RV32IB-NEXT:    sh2add a0, a0, a0
+; RV32IB-NEXT:    sh3add a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBA-LABEL: addmul40:
 ; RV32IBA:       # %bb.0:
-; RV32IBA-NEXT:    addi a2, zero, 40
-; RV32IBA-NEXT:    mul a0, a0, a2
-; RV32IBA-NEXT:    add a0, a0, a1
+; RV32IBA-NEXT:    sh2add a0, a0, a0
+; RV32IBA-NEXT:    sh3add a0, a0, a1
 ; RV32IBA-NEXT:    ret
   %c = mul i32 %a, 40
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul72(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul72:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 72
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: addmul72:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a2, zero, 72
-; RV32IB-NEXT:    mul a0, a0, a2
-; RV32IB-NEXT:    add a0, a0, a1
+; RV32IB-NEXT:    sh3add a0, a0, a0
+; RV32IB-NEXT:    sh3add a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBA-LABEL: addmul72:
 ; RV32IBA:       # %bb.0:
-; RV32IBA-NEXT:    addi a2, zero, 72
-; RV32IBA-NEXT:    mul a0, a0, a2
-; RV32IBA-NEXT:    add a0, a0, a1
+; RV32IBA-NEXT:    sh3add a0, a0, a0
+; RV32IBA-NEXT:    sh3add a0, a0, a1
 ; RV32IBA-NEXT:    ret
   %c = mul i32 %a, 72
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @mul96(i32 %a) {
 ; RV32I-LABEL: mul96:

llvm/test/CodeGen/RISCV/rv64zba.ll

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 6
 ; RV64I-NEXT:    mul a0, a0, a2
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: addmul6:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a2, zero, 6
-; RV64IB-NEXT:    mul a0, a0, a2
-; RV64IB-NEXT:    add a0, a0, a1
+; RV64IB-NEXT:    sh1add a0, a0, a0
+; RV64IB-NEXT:    sh1add a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: addmul6:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a2, zero, 6
-; RV64IBA-NEXT:    mul a0, a0, a2
-; RV64IBA-NEXT:    add a0, a0, a1
+; RV64IBA-NEXT:    sh1add a0, a0, a0
+; RV64IBA-NEXT:    sh1add a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %c = mul i64 %a, 6
   %d = add i64 %c, %b
   ret i64 %d
 }
 
 define i64 @addmul10(i64 %a, i64 %b) {
 ; RV64I-LABEL: addmul10:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 10
 ; RV64I-NEXT:    mul a0, a0, a2
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: addmul10:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a2, zero, 10
-; RV64IB-NEXT:    mul a0, a0, a2
-; RV64IB-NEXT:    add a0, a0, a1
+; RV64IB-NEXT:    sh2add a0, a0, a0
+; RV64IB-NEXT:    sh1add a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: addmul10:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a2, zero, 10
-; RV64IBA-NEXT:    mul a0, a0, a2
-; RV64IBA-NEXT:    add a0, a0, a1
+; RV64IBA-NEXT:    sh2add a0, a0, a0
+; RV64IBA-NEXT:    sh1add a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %c = mul i64 %a, 10
   %d = add i64 %c, %b
   ret i64 %d
 }
 
 define i64 @addmul12(i64 %a, i64 %b) {
 ; RV64I-LABEL: addmul12:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 12
 ; RV64I-NEXT:    mul a0, a0, a2
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: addmul12:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a2, zero, 12
-; RV64IB-NEXT:    mul a0, a0, a2
-; RV64IB-NEXT:    add a0, a0, a1
+; RV64IB-NEXT:    sh1add a0, a0, a0
+; RV64IB-NEXT:    sh2add a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: addmul12:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a2, zero, 12
-; RV64IBA-NEXT:    mul a0, a0, a2
-; RV64IBA-NEXT:    add a0, a0, a1
+; RV64IBA-NEXT:    sh1add a0, a0, a0
+; RV64IBA-NEXT:    sh2add a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %c = mul i64 %a, 12
   %d = add i64 %c, %b
   ret i64 %d
 }
 
 define i64 @addmul18(i64 %a, i64 %b) {
 ; RV64I-LABEL: addmul18:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 18
 ; RV64I-NEXT:    mul a0, a0, a2
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: addmul18:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a2, zero, 18
-; RV64IB-NEXT:    mul a0, a0, a2
-; RV64IB-NEXT:    add a0, a0, a1
+; RV64IB-NEXT:    sh3add a0, a0, a0
+; RV64IB-NEXT:    sh1add a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: addmul18:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a2, zero, 18
-; RV64IBA-NEXT:    mul a0, a0, a2
-; RV64IBA-NEXT:    add a0, a0, a1
+; RV64IBA-NEXT:    sh3add a0, a0, a0
+; RV64IBA-NEXT:    sh1add a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %c = mul i64 %a, 18
   %d = add i64 %c, %b
   ret i64 %d
 }
 
 define i64 @addmul20(i64 %a, i64 %b) {
 ; RV64I-LABEL: addmul20:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 20
 ; RV64I-NEXT:    mul a0, a0, a2
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: addmul20:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a2, zero, 20
-; RV64IB-NEXT:    mul a0, a0, a2
-; RV64IB-NEXT:    add a0, a0, a1
+; RV64IB-NEXT:    sh2add a0, a0, a0
+; RV64IB-NEXT:    sh2add a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: addmul20:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a2, zero, 20
-; RV64IBA-NEXT:    mul a0, a0, a2
-; RV64IBA-NEXT:    add a0, a0, a1
+; RV64IBA-NEXT:    sh2add a0, a0, a0
+; RV64IBA-NEXT:    sh2add a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %c = mul i64 %a, 20
   %d = add i64 %c, %b
   ret i64 %d
 }
 
 define i64 @addmul24(i64 %a, i64 %b) {
 ; RV64I-LABEL: addmul24:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 24
 ; RV64I-NEXT:    mul a0, a0, a2
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: addmul24:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a2, zero, 24
-; RV64IB-NEXT:    mul a0, a0, a2
-; RV64IB-NEXT:    add a0, a0, a1
+; RV64IB-NEXT:    sh1add a0, a0, a0
+; RV64IB-NEXT:    sh3add a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: addmul24:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a2, zero, 24
-; RV64IBA-NEXT:    mul a0, a0, a2
-; RV64IBA-NEXT:    add a0, a0, a1
+; RV64IBA-NEXT:    sh1add a0, a0, a0
+; RV64IBA-NEXT:    sh3add a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %c = mul i64 %a, 24
   %d = add i64 %c, %b
   ret i64 %d
 }
 
 define i64 @addmul36(i64 %a, i64 %b) {
 ; RV64I-LABEL: addmul36:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 36
 ; RV64I-NEXT:    mul a0, a0, a2
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: addmul36:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a2, zero, 36
-; RV64IB-NEXT:    mul a0, a0, a2
-; RV64IB-NEXT:    add a0, a0, a1
+; RV64IB-NEXT:    sh3add a0, a0, a0
+; RV64IB-NEXT:    sh2add a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: addmul36:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a2, zero, 36
-; RV64IBA-NEXT:    mul a0, a0, a2
-; RV64IBA-NEXT:    add a0, a0, a1
+; RV64IBA-NEXT:    sh3add a0, a0, a0
+; RV64IBA-NEXT:    sh2add a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %c = mul i64 %a, 36
   %d = add i64 %c, %b
   ret i64 %d
 }
 
 define i64 @addmul40(i64 %a, i64 %b) {
 ; RV64I-LABEL: addmul40:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 40
 ; RV64I-NEXT:    mul a0, a0, a2
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: addmul40:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a2, zero, 40
-; RV64IB-NEXT:    mul a0, a0, a2
-; RV64IB-NEXT:    add a0, a0, a1
+; RV64IB-NEXT:    sh2add a0, a0, a0
+; RV64IB-NEXT:    sh3add a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: addmul40:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a2, zero, 40
-; RV64IBA-NEXT:    mul a0, a0, a2
-; RV64IBA-NEXT:    add a0, a0, a1
+; RV64IBA-NEXT:    sh2add a0, a0, a0
+; RV64IBA-NEXT:    sh3add a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %c = mul i64 %a, 40
   %d = add i64 %c, %b
   ret i64 %d
 }
 
 define i64 @addmul72(i64 %a, i64 %b) {
 ; RV64I-LABEL: addmul72:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 72
 ; RV64I-NEXT:    mul a0, a0, a2
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: addmul72:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a2, zero, 72
-; RV64IB-NEXT:    mul a0, a0, a2
-; RV64IB-NEXT:    add a0, a0, a1
+; RV64IB-NEXT:    sh3add a0, a0, a0
+; RV64IB-NEXT:    sh3add a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: addmul72:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a2, zero, 72
-; RV64IBA-NEXT:    mul a0, a0, a2
-; RV64IBA-NEXT:    add a0, a0, a1
+; RV64IBA-NEXT:    sh3add a0, a0, a0
+; RV64IBA-NEXT:    sh3add a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %c = mul i64 %a, 72
   %d = add i64 %c, %b
   ret i64 %d
 }
 
 define i64 @mul96(i64 %a) {
 ; RV64I-LABEL: mul96: