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AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
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Authored by arsenm on Jun 18 2021, 3:09 PM.

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Reviewers

rampitec
foad
Joe_Nash
kerbowa

Summary

These used to consistently be zeroed pre-gfx9, but gfx9 made the
situation complicated since now some still do and some don't. This
also manages to pick up a few cases that the pattern fails to optimize
away.

We handle some cases with instruction patterns, but some get
through. In particular this improves the integer cases.

Diff Detail

Event Timeline

arsenm created this revision.Jun 18 2021, 3:09 PM

Herald added subscribers: hiraditya, t-tye, tpr and 5 others. · View Herald TranscriptJun 18 2021, 3:09 PM

arsenm requested review of this revision.Jun 18 2021, 3:09 PM

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Harbormaster completed remote builds in B110005: Diff 353111.Jun 18 2021, 3:09 PM

foad added inline comments.Jun 21 2021, 6:05 AM

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
447	Where is this function defined?

arsenm updated this revision to Diff 353359.Jun 21 2021, 7:06 AM

arsenm added inline comments.

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
447	Posted wrong version of patch. I added a subtarget feature for this initially, but the actual behavior is a bit too convoluted and would require multiple variants of it

Harbormaster completed remote builds in B110192: Diff 353359.Jun 21 2021, 7:07 AM

Looks reasonable to me. I guess there's no way to do this as a DAGCombine instead?

This revision is now accepted and ready to land.Jun 22 2021, 2:31 AM

In D104575#2832652, @foad wrote:

Looks reasonable to me. I guess there's no way to do this as a DAGCombine instead?

You would need to know exactly how the source node is going to be selected, which you can't know ahead of time We do approximate this for FP instructions already.

In D104575#2833135, @arsenm wrote:

In D104575#2832652, @foad wrote:

Looks reasonable to me. I guess there's no way to do this as a DAGCombine instead?

You would need to know exactly how the source node is going to be selected, which you can't know ahead of time We do approximate this for FP instructions already.

I was wondering if combines could be run on the MachineSDNodes immediately after selection. But I see there is nothing like that.

In D104575#2833149, @foad wrote:

In D104575#2833135, @arsenm wrote:

In D104575#2832652, @foad wrote:

Looks reasonable to me. I guess there's no way to do this as a DAGCombine instead?

You would need to know exactly how the source node is going to be selected, which you can't know ahead of time We do approximate this for FP instructions already.

I was wondering if combines could be run on the MachineSDNodes immediately after selection. But I see there is nothing like that.

I think there is a post-processing hook in the selector, but the instructions would be a bit off since SIFixSGPRCopies wouldn't have run yet, and there could be more intermediate nodes. Plus why sink effort into a DAG only solution at this point

39f8a792f0ac4efed11ac906ba76137fc0c9f6a8

Revision Contents

Path

Size

llvm/

lib/

Target/

AMDGPU/

AMDGPUSubtarget.cpp

99 lines

GCNSubtarget.h

5 lines

SIFoldOperands.cpp

25 lines

test/

CodeGen/

AMDGPU/

2 lines

16 lines

2 lines

16 lines

7 lines

high-bits-zeroed-16-bit-ops.mir

471 lines

llvm.amdgcn.frexp.exp.f16.ll

3 lines

16 lines

16 lines

10 lines

19 lines

10 lines

19 lines

28 lines

8 lines

8 lines

Diff 353359

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

Show First 20 Lines • Show All 347 Lines • ▼ Show 20 Lines	unsigned GCNSubtarget::getConstantBusLimit(unsigned Opcode) const {
case AMDGPU::V_ASHRREV_I64_gfx10:		case AMDGPU::V_ASHRREV_I64_gfx10:
case AMDGPU::V_ASHR_I64_e64:		case AMDGPU::V_ASHR_I64_e64:
return 1;		return 1;
}		}

return 2;		return 2;
}		}

		/// This list was mostly derived from experimentation.
		bool GCNSubtarget::zeroesHigh16BitsOfDest(unsigned Opcode) const {
		switch (Opcode) {
		case AMDGPU::V_CVT_F16_F32_e32:
		case AMDGPU::V_CVT_F16_F32_e64:
		case AMDGPU::V_CVT_F16_U16_e32:
		case AMDGPU::V_CVT_F16_U16_e64:
		case AMDGPU::V_CVT_F16_I16_e32:
		case AMDGPU::V_CVT_F16_I16_e64:
		case AMDGPU::V_RCP_F16_e64:
		case AMDGPU::V_RCP_F16_e32:
		case AMDGPU::V_RSQ_F16_e64:
		case AMDGPU::V_RSQ_F16_e32:
		case AMDGPU::V_SQRT_F16_e64:
		case AMDGPU::V_SQRT_F16_e32:
		case AMDGPU::V_LOG_F16_e64:
		case AMDGPU::V_LOG_F16_e32:
		case AMDGPU::V_EXP_F16_e64:
		case AMDGPU::V_EXP_F16_e32:
		case AMDGPU::V_SIN_F16_e64:
		case AMDGPU::V_SIN_F16_e32:
		case AMDGPU::V_COS_F16_e64:
		case AMDGPU::V_COS_F16_e32:
		case AMDGPU::V_FLOOR_F16_e64:
		case AMDGPU::V_FLOOR_F16_e32:
		case AMDGPU::V_CEIL_F16_e64:
		case AMDGPU::V_CEIL_F16_e32:
		case AMDGPU::V_TRUNC_F16_e64:
		case AMDGPU::V_TRUNC_F16_e32:
		case AMDGPU::V_RNDNE_F16_e64:
		case AMDGPU::V_RNDNE_F16_e32:
		case AMDGPU::V_FRACT_F16_e64:
		case AMDGPU::V_FRACT_F16_e32:
		case AMDGPU::V_FREXP_MANT_F16_e64:
		case AMDGPU::V_FREXP_MANT_F16_e32:
		case AMDGPU::V_FREXP_EXP_I16_F16_e64:
		case AMDGPU::V_FREXP_EXP_I16_F16_e32:
		case AMDGPU::V_LDEXP_F16_e64:
		case AMDGPU::V_LDEXP_F16_e32:
		case AMDGPU::V_LSHLREV_B16_e64:
		case AMDGPU::V_LSHLREV_B16_e32:
		case AMDGPU::V_LSHRREV_B16_e64:
		case AMDGPU::V_LSHRREV_B16_e32:
		case AMDGPU::V_ASHRREV_I16_e64:
		case AMDGPU::V_ASHRREV_I16_e32:
		case AMDGPU::V_ADD_U16_e64:
		case AMDGPU::V_ADD_U16_e32:
		case AMDGPU::V_SUB_U16_e64:
		case AMDGPU::V_SUB_U16_e32:
		case AMDGPU::V_SUBREV_U16_e64:
		case AMDGPU::V_SUBREV_U16_e32:
		case AMDGPU::V_MUL_LO_U16_e64:
		case AMDGPU::V_MUL_LO_U16_e32:
		case AMDGPU::V_ADD_F16_e64:
		case AMDGPU::V_ADD_F16_e32:
		case AMDGPU::V_SUB_F16_e64:
		case AMDGPU::V_SUB_F16_e32:
		case AMDGPU::V_SUBREV_F16_e64:
		case AMDGPU::V_SUBREV_F16_e32:
		case AMDGPU::V_MUL_F16_e64:
		case AMDGPU::V_MUL_F16_e32:
		case AMDGPU::V_MAX_F16_e64:
		case AMDGPU::V_MAX_F16_e32:
		case AMDGPU::V_MIN_F16_e64:
		case AMDGPU::V_MIN_F16_e32:
		case AMDGPU::V_MAX_U16_e64:
		case AMDGPU::V_MAX_U16_e32:
		case AMDGPU::V_MIN_U16_e64:
		case AMDGPU::V_MIN_U16_e32:
		case AMDGPU::V_MAX_I16_e64:
		case AMDGPU::V_MAX_I16_e32:
		case AMDGPU::V_MIN_I16_e64:
		case AMDGPU::V_MIN_I16_e32:
		// On gfx10, all 16-bit instructions preserve the high bits.
		return getGeneration() <= AMDGPUSubtarget::GFX9;
		case AMDGPU::V_MAD_F16_e64:
		case AMDGPU::V_MADAK_F16:
		case AMDGPU::V_MADMK_F16:
		case AMDGPU::V_MAC_F16_e64:
		case AMDGPU::V_MAC_F16_e32:
		case AMDGPU::V_FMAMK_F16:
		case AMDGPU::V_FMAAK_F16:
		case AMDGPU::V_MAD_U16_e64:
		case AMDGPU::V_MAD_I16_e64:
		case AMDGPU::V_FMA_F16_e64:
		case AMDGPU::V_FMAC_F16_e64:
		case AMDGPU::V_FMAC_F16_e32:
		case AMDGPU::V_DIV_FIXUP_F16_e64:
		// In gfx9, the preferred handling of the unused high 16-bits changed. Most
		// instructions maintain the legacy behavior of 0ing. Some instructions
		// changed to preserving the high bits.
		return getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS;
		foadUnsubmitted Not Done Reply Inline Actions Where is this function defined? foad: Where is this function defined?
		arsenmAuthorUnsubmitted Done Reply Inline Actions Posted wrong version of patch. I added a subtarget feature for this initially, but the actual behavior is a bit too convoluted and would require multiple variants of it arsenm: Posted wrong version of patch. I added a subtarget feature for this initially, but the actual…
		case AMDGPU::V_MAD_MIXLO_F16:
		case AMDGPU::V_MAD_MIXHI_F16:
		default:
		return false;
		}
		}

unsigned AMDGPUSubtarget::getMaxLocalMemSizeWithWaveCount(unsigned NWaves,		unsigned AMDGPUSubtarget::getMaxLocalMemSizeWithWaveCount(unsigned NWaves,
const Function &F) const {		const Function &F) const {
if (NWaves == 1)		if (NWaves == 1)
return getLocalMemorySize();		return getLocalMemorySize();
unsigned WorkGroupSize = getFlatWorkGroupSizes(F).second;		unsigned WorkGroupSize = getFlatWorkGroupSizes(F).second;
unsigned WorkGroupsPerCu = getMaxWorkGroupsPerCU(WorkGroupSize);		unsigned WorkGroupsPerCu = getMaxWorkGroupsPerCU(WorkGroupSize);
if (!WorkGroupsPerCu)		if (!WorkGroupsPerCu)
return 0;		return 0;
▲ Show 20 Lines • Show All 684 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/GCNSubtarget.h

Show First 20 Lines • Show All 280 Lines • ▼ Show 20 Lines	public:
}		}

unsigned getMaxPrivateElementSize(bool ForBufferRSrc = false) const {		unsigned getMaxPrivateElementSize(bool ForBufferRSrc = false) const {
return (ForBufferRSrc \|\| !enableFlatScratch()) ? MaxPrivateElementSize : 16;		return (ForBufferRSrc \|\| !enableFlatScratch()) ? MaxPrivateElementSize : 16;
}		}

unsigned getConstantBusLimit(unsigned Opcode) const;		unsigned getConstantBusLimit(unsigned Opcode) const;

		/// Returns if the result of this instruction with a 16-bit result returned in
		/// a 32-bit register implicitly zeroes the high 16-bits, rather than preserve
		/// the original value.
		bool zeroesHigh16BitsOfDest(unsigned Opcode) const;

bool hasIntClamp() const {		bool hasIntClamp() const {
return HasIntClamp;		return HasIntClamp;
}		}

bool hasFP64() const {		bool hasFP64() const {
return FP64;		return FP64;
}		}

▲ Show 20 Lines • Show All 885 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines	public:

void foldOperand(MachineOperand &OpToFold,		void foldOperand(MachineOperand &OpToFold,
MachineInstr *UseMI,		MachineInstr *UseMI,
int UseOpIdx,		int UseOpIdx,
SmallVectorImpl<FoldCandidate> &FoldList,		SmallVectorImpl<FoldCandidate> &FoldList,
SmallVectorImpl<MachineInstr *> &CopiesToReplace) const;		SmallVectorImpl<MachineInstr *> &CopiesToReplace) const;

bool tryFoldCndMask(MachineInstr &MI) const;		bool tryFoldCndMask(MachineInstr &MI) const;
		bool tryFoldZeroHighBits(MachineInstr &MI) const;
void foldInstOperand(MachineInstr &MI, MachineOperand &OpToFold) const;		void foldInstOperand(MachineInstr &MI, MachineOperand &OpToFold) const;

const MachineOperand *isClamp(const MachineInstr &MI) const;		const MachineOperand *isClamp(const MachineInstr &MI) const;
bool tryFoldClamp(MachineInstr &MI);		bool tryFoldClamp(MachineInstr &MI);

std::pair<const MachineOperand *, int> isOMod(const MachineInstr &MI) const;		std::pair<const MachineOperand *, int> isOMod(const MachineInstr &MI) const;
bool tryFoldOMod(MachineInstr &MI);		bool tryFoldOMod(MachineInstr &MI);
bool tryFoldRegSequence(MachineInstr &MI);		bool tryFoldRegSequence(MachineInstr &MI);
▲ Show 20 Lines • Show All 1,081 Lines • ▼ Show 20 Lines	if (Src1ModIdx != -1)
MI.RemoveOperand(Src1ModIdx);		MI.RemoveOperand(Src1ModIdx);
if (Src0ModIdx != -1)		if (Src0ModIdx != -1)
MI.RemoveOperand(Src0ModIdx);		MI.RemoveOperand(Src0ModIdx);
mutateCopyOp(MI, NewDesc);		mutateCopyOp(MI, NewDesc);
LLVM_DEBUG(dbgs() << MI);		LLVM_DEBUG(dbgs() << MI);
return true;		return true;
}		}

		bool SIFoldOperands::tryFoldZeroHighBits(MachineInstr &MI) const {
		if (MI.getOpcode() != AMDGPU::V_AND_B32_e64 &&
		MI.getOpcode() != AMDGPU::V_AND_B32_e32)
		return false;

		MachineOperand Src0 = getImmOrMaterializedImm(MRI, MI.getOperand(1));
		if (!Src0->isImm() \|\| Src0->getImm() != 0xffff)
		return false;

		Register Src1 = MI.getOperand(2).getReg();
		MachineInstr *SrcDef = MRI->getVRegDef(Src1);
		if (ST->zeroesHigh16BitsOfDest(SrcDef->getOpcode())) {
		Register Dst = MI.getOperand(0).getReg();
		MRI->replaceRegWith(Dst, SrcDef->getOperand(0).getReg());
		MI.eraseFromParent();
		return true;
		}

		return false;
		}

void SIFoldOperands::foldInstOperand(MachineInstr &MI,		void SIFoldOperands::foldInstOperand(MachineInstr &MI,
MachineOperand &OpToFold) const {		MachineOperand &OpToFold) const {
// We need mutate the operands of new mov instructions to add implicit		// We need mutate the operands of new mov instructions to add implicit
// uses of EXEC, but adding them invalidates the use_iterator, so defer		// uses of EXEC, but adding them invalidates the use_iterator, so defer
// this.		// this.
SmallVector<MachineInstr *, 4> CopiesToReplace;		SmallVector<MachineInstr *, 4> CopiesToReplace;
SmallVector<FoldCandidate, 4> FoldList;		SmallVector<FoldCandidate, 4> FoldList;
MachineOperand &Dst = MI.getOperand(0);		MachineOperand &Dst = MI.getOperand(0);
▲ Show 20 Lines • Show All 517 Lines • ▼ Show 20 Lines	bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
bool IsIEEEMode = MFI->getMode().IEEE;		bool IsIEEEMode = MFI->getMode().IEEE;
bool HasNSZ = MFI->hasNoSignedZerosFPMath();		bool HasNSZ = MFI->hasNoSignedZerosFPMath();

for (MachineBasicBlock *MBB : depth_first(&MF)) {		for (MachineBasicBlock *MBB : depth_first(&MF)) {
MachineOperand *CurrentKnownM0Val = nullptr;		MachineOperand *CurrentKnownM0Val = nullptr;
for (auto &MI : make_early_inc_range(*MBB)) {		for (auto &MI : make_early_inc_range(*MBB)) {
tryFoldCndMask(MI);		tryFoldCndMask(MI);

		if (tryFoldZeroHighBits(MI))
		continue;

if (MI.isRegSequence() && tryFoldRegSequence(MI))		if (MI.isRegSequence() && tryFoldRegSequence(MI))
continue;		continue;

if (MI.isPHI() && tryFoldLCSSAPhi(MI))		if (MI.isPHI() && tryFoldLCSSAPhi(MI))
continue;		continue;

if (MI.mayLoad() && tryFoldLoad(MI))		if (MI.mayLoad() && tryFoldLoad(MI))
continue;		continue;
▲ Show 20 Lines • Show All 76 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/fmax3.ll

	Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Lines

	; VI: s_waitcnt			; VI: s_waitcnt
	; VI-NEXT: v_max_f16_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NEXT: v_max_f16_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NEXT: v_max_f16_e32 v0, v0, v1			; VI-NEXT: v_max_f16_e32 v0, v0, v1
	; VI-NEXT: v_max_f16_sdwa v1, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD			; VI-NEXT: v_max_f16_sdwa v1, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
	; VI-NEXT: v_max_f16_e32 v0, v2, v0			; VI-NEXT: v_max_f16_e32 v0, v2, v0
	; VI-NEXT: v_max_f16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1			; VI-NEXT: v_max_f16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
	; VI-NEXT: v_max_f16_e32 v0, v0, v3			; VI-NEXT: v_max_f16_e32 v0, v0, v3
	; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v0, v0, v1
	; VI-NEXT: s_setpc_b64			; VI-NEXT: s_setpc_b64

	; GFX9: s_waitcnt			; GFX9: s_waitcnt
	; GFX9-NEXT: v_pk_max_f16			; GFX9-NEXT: v_pk_max_f16
	; GFX9-NEXT: v_pk_max_f16			; GFX9-NEXT: v_pk_max_f16
	; GFX9-NEXT: v_pk_max_f16			; GFX9-NEXT: v_pk_max_f16
	define <2 x half> @no_fmax3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) #2 {			define <2 x half> @no_fmax3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) #2 {
	entry:			entry:
	Show All 14 Lines

llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll

	Show First 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
	; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
	; VI-SAFE-NEXT: s_setpc_b64 s[30:31]			; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
	;			;
	; VI-NNAN-LABEL: test_fmax_legacy_ugt_v2f16:			; VI-NNAN-LABEL: test_fmax_legacy_ugt_v2f16:
	; VI-NNAN: ; %bb.0:			; VI-NNAN: ; %bb.0:
	; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; VI-NNAN-NEXT: v_max_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NNAN-NEXT: v_max_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v1			; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v1
	; VI-NNAN-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v2
	; VI-NNAN-NEXT: s_setpc_b64 s[30:31]			; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
	;			;
	; SI-SAFE-LABEL: test_fmax_legacy_ugt_v2f16:			; SI-SAFE-LABEL: test_fmax_legacy_ugt_v2f16:
	; SI-SAFE: ; %bb.0:			; SI-SAFE: ; %bb.0:
	; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
	▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
	; VI-SAFE-NEXT: s_setpc_b64 s[30:31]			; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
	;			;
	; VI-NNAN-LABEL: test_fmax_legacy_ugt_v3f16:			; VI-NNAN-LABEL: test_fmax_legacy_ugt_v3f16:
	; VI-NNAN: ; %bb.0:			; VI-NNAN: ; %bb.0:
	; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; VI-NNAN-NEXT: v_max_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NNAN-NEXT: v_max_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v2			; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v2
	; VI-NNAN-NEXT: v_max_f16_e32 v1, v1, v3			; VI-NNAN-NEXT: v_max_f16_e32 v1, v1, v3
	; VI-NNAN-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v4
	; VI-NNAN-NEXT: s_setpc_b64 s[30:31]			; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
	;			;
	; SI-SAFE-LABEL: test_fmax_legacy_ugt_v3f16:			; SI-SAFE-LABEL: test_fmax_legacy_ugt_v3f16:
	; SI-SAFE: ; %bb.0:			; SI-SAFE: ; %bb.0:
	; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v5, v5			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v5, v5
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
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	;			;
	; VI-NNAN-LABEL: test_fmax_legacy_ugt_v4f16:			; VI-NNAN-LABEL: test_fmax_legacy_ugt_v4f16:
	; VI-NNAN: ; %bb.0:			; VI-NNAN: ; %bb.0:
	; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; VI-NNAN-NEXT: v_max_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NNAN-NEXT: v_max_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NNAN-NEXT: v_max_f16_e32 v1, v1, v3			; VI-NNAN-NEXT: v_max_f16_e32 v1, v1, v3
	; VI-NNAN-NEXT: v_max_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NNAN-NEXT: v_max_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v2			; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v2
	; VI-NNAN-NEXT: v_or_b32_sdwa v0, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v5
	; VI-NNAN-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NNAN-NEXT: v_or_b32_e32 v1, v1, v4
	; VI-NNAN-NEXT: s_setpc_b64 s[30:31]			; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
	;			;
	; SI-SAFE-LABEL: test_fmax_legacy_ugt_v4f16:			; SI-SAFE-LABEL: test_fmax_legacy_ugt_v4f16:
	; SI-SAFE: ; %bb.0:			; SI-SAFE: ; %bb.0:
	; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v7, v7			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v7, v7
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
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	; VI-NNAN-NEXT: v_max_f16_sdwa v8, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NNAN-NEXT: v_max_f16_sdwa v8, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NNAN-NEXT: v_max_f16_e32 v3, v3, v7			; VI-NNAN-NEXT: v_max_f16_e32 v3, v3, v7
	; VI-NNAN-NEXT: v_max_f16_sdwa v9, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NNAN-NEXT: v_max_f16_sdwa v9, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NNAN-NEXT: v_max_f16_e32 v2, v2, v6			; VI-NNAN-NEXT: v_max_f16_e32 v2, v2, v6
	; VI-NNAN-NEXT: v_max_f16_sdwa v10, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NNAN-NEXT: v_max_f16_sdwa v10, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NNAN-NEXT: v_max_f16_e32 v1, v1, v5			; VI-NNAN-NEXT: v_max_f16_e32 v1, v1, v5
	; VI-NNAN-NEXT: v_max_f16_sdwa v11, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NNAN-NEXT: v_max_f16_sdwa v11, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v4			; VI-NNAN-NEXT: v_max_f16_e32 v0, v0, v4
	; VI-NNAN-NEXT: v_or_b32_sdwa v0, v0, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v11
	; VI-NNAN-NEXT: v_or_b32_sdwa v1, v1, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NNAN-NEXT: v_or_b32_e32 v1, v1, v10
	; VI-NNAN-NEXT: v_or_b32_sdwa v2, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NNAN-NEXT: v_or_b32_e32 v2, v2, v9
	; VI-NNAN-NEXT: v_or_b32_sdwa v3, v3, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NNAN-NEXT: v_or_b32_e32 v3, v3, v8
	; VI-NNAN-NEXT: s_setpc_b64 s[30:31]			; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
	;			;
	; SI-SAFE-LABEL: test_fmax_legacy_ugt_v8f16:			; SI-SAFE-LABEL: test_fmax_legacy_ugt_v8f16:
	; SI-SAFE: ; %bb.0:			; SI-SAFE: ; %bb.0:
	; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v7, v7			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v7, v7
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v15, v15			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v15, v15
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v6, v6			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v6, v6
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llvm/test/CodeGen/AMDGPU/fmin3.ll

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	; VI: s_waitcnt			; VI: s_waitcnt
	; VI-NEXT: v_min_f16_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NEXT: v_min_f16_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NEXT: v_min_f16_e32 v0, v0, v1			; VI-NEXT: v_min_f16_e32 v0, v0, v1
	; VI-NEXT: v_min_f16_sdwa v1, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD			; VI-NEXT: v_min_f16_sdwa v1, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
	; VI-NEXT: v_min_f16_e32 v0, v2, v0			; VI-NEXT: v_min_f16_e32 v0, v2, v0
	; VI-NEXT: v_min_f16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1			; VI-NEXT: v_min_f16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
	; VI-NEXT: v_min_f16_e32 v0, v0, v3			; VI-NEXT: v_min_f16_e32 v0, v0, v3
	; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v0, v0, v1
	; VI-NEXT: s_setpc_b64			; VI-NEXT: s_setpc_b64

	; GFX9: s_waitcnt			; GFX9: s_waitcnt
	; GFX9-NEXT: v_pk_min_f16 v0, v0, v1			; GFX9-NEXT: v_pk_min_f16 v0, v0, v1
	; GFX9-NEXT: v_pk_min_f16 v0, v2, v0			; GFX9-NEXT: v_pk_min_f16 v0, v2, v0
	; GFX9-NEXT: v_pk_min_f16 v0, v0, v3			; GFX9-NEXT: v_pk_min_f16 v0, v0, v3
	; GFX9-NEXT: s_setpc_b64			; GFX9-NEXT: s_setpc_b64
	define <2 x half> @no_fmin3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) #2 {			define <2 x half> @no_fmin3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) #2 {
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llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll

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	; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-SAFE-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
	; VI-SAFE-NEXT: s_setpc_b64 s[30:31]			; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
	;			;
	; VI-NNAN-LABEL: test_fmin_legacy_ule_v2f16:			; VI-NNAN-LABEL: test_fmin_legacy_ule_v2f16:
	; VI-NNAN: ; %bb.0:			; VI-NNAN: ; %bb.0:
	; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; VI-NNAN-NEXT: v_min_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NNAN-NEXT: v_min_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NNAN-NEXT: v_min_f16_e32 v0, v0, v1			; VI-NNAN-NEXT: v_min_f16_e32 v0, v0, v1
	; VI-NNAN-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v2
	; VI-NNAN-NEXT: s_setpc_b64 s[30:31]			; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
	;			;
	; SI-SAFE-LABEL: test_fmin_legacy_ule_v2f16:			; SI-SAFE-LABEL: test_fmin_legacy_ule_v2f16:
	; SI-SAFE: ; %bb.0:			; SI-SAFE: ; %bb.0:
	; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
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	; VI-SAFE-NEXT: s_setpc_b64 s[30:31]			; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
	;			;
	; VI-NNAN-LABEL: test_fmin_legacy_ule_v3f16:			; VI-NNAN-LABEL: test_fmin_legacy_ule_v3f16:
	; VI-NNAN: ; %bb.0:			; VI-NNAN: ; %bb.0:
	; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; VI-NNAN-NEXT: v_min_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NNAN-NEXT: v_min_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NNAN-NEXT: v_min_f16_e32 v0, v0, v2			; VI-NNAN-NEXT: v_min_f16_e32 v0, v0, v2
	; VI-NNAN-NEXT: v_min_f16_e32 v1, v1, v3			; VI-NNAN-NEXT: v_min_f16_e32 v1, v1, v3
	; VI-NNAN-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v4
	; VI-NNAN-NEXT: s_setpc_b64 s[30:31]			; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
	;			;
	; SI-SAFE-LABEL: test_fmin_legacy_ule_v3f16:			; SI-SAFE-LABEL: test_fmin_legacy_ule_v3f16:
	; SI-SAFE: ; %bb.0:			; SI-SAFE: ; %bb.0:
	; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v5, v5			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v5, v5
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
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	;			;
	; VI-NNAN-LABEL: test_fmin_legacy_ule_v4f16:			; VI-NNAN-LABEL: test_fmin_legacy_ule_v4f16:
	; VI-NNAN: ; %bb.0:			; VI-NNAN: ; %bb.0:
	; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; VI-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; VI-NNAN-NEXT: v_min_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NNAN-NEXT: v_min_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NNAN-NEXT: v_min_f16_e32 v1, v1, v3			; VI-NNAN-NEXT: v_min_f16_e32 v1, v1, v3
	; VI-NNAN-NEXT: v_min_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NNAN-NEXT: v_min_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NNAN-NEXT: v_min_f16_e32 v0, v0, v2			; VI-NNAN-NEXT: v_min_f16_e32 v0, v0, v2
	; VI-NNAN-NEXT: v_or_b32_sdwa v0, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v5
	; VI-NNAN-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NNAN-NEXT: v_or_b32_e32 v1, v1, v4
	; VI-NNAN-NEXT: s_setpc_b64 s[30:31]			; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
	;			;
	; SI-SAFE-LABEL: test_fmin_legacy_ule_v4f16:			; SI-SAFE-LABEL: test_fmin_legacy_ule_v4f16:
	; SI-SAFE: ; %bb.0:			; SI-SAFE: ; %bb.0:
	; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v3, v3
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v7, v7			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v7, v7
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
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	; VI-NNAN-NEXT: v_min_f16_sdwa v8, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NNAN-NEXT: v_min_f16_sdwa v8, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NNAN-NEXT: v_min_f16_e32 v3, v3, v7			; VI-NNAN-NEXT: v_min_f16_e32 v3, v3, v7
	; VI-NNAN-NEXT: v_min_f16_sdwa v9, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NNAN-NEXT: v_min_f16_sdwa v9, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NNAN-NEXT: v_min_f16_e32 v2, v2, v6			; VI-NNAN-NEXT: v_min_f16_e32 v2, v2, v6
	; VI-NNAN-NEXT: v_min_f16_sdwa v10, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NNAN-NEXT: v_min_f16_sdwa v10, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NNAN-NEXT: v_min_f16_e32 v1, v1, v5			; VI-NNAN-NEXT: v_min_f16_e32 v1, v1, v5
	; VI-NNAN-NEXT: v_min_f16_sdwa v11, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; VI-NNAN-NEXT: v_min_f16_sdwa v11, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; VI-NNAN-NEXT: v_min_f16_e32 v0, v0, v4			; VI-NNAN-NEXT: v_min_f16_e32 v0, v0, v4
	; VI-NNAN-NEXT: v_or_b32_sdwa v0, v0, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NNAN-NEXT: v_or_b32_e32 v0, v0, v11
	; VI-NNAN-NEXT: v_or_b32_sdwa v1, v1, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NNAN-NEXT: v_or_b32_e32 v1, v1, v10
	; VI-NNAN-NEXT: v_or_b32_sdwa v2, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NNAN-NEXT: v_or_b32_e32 v2, v2, v9
	; VI-NNAN-NEXT: v_or_b32_sdwa v3, v3, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NNAN-NEXT: v_or_b32_e32 v3, v3, v8
	; VI-NNAN-NEXT: s_setpc_b64 s[30:31]			; VI-NNAN-NEXT: s_setpc_b64 s[30:31]
	;			;
	; SI-SAFE-LABEL: test_fmin_legacy_ule_v8f16:			; SI-SAFE-LABEL: test_fmin_legacy_ule_v8f16:
	; SI-SAFE: ; %bb.0:			; SI-SAFE: ; %bb.0:
	; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v7, v7			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v7, v7
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v15, v15			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v15, v15
	; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v6, v6			; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v6, v6
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llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; SI-DAG: v_cvt_f16_f32_e32 v[[CVTHI:[0-9]+]], v[[A_F32_1]]		; SI-DAG: v_cvt_f16_f32_e32 v[[CVTHI:[0-9]+]], v[[A_F32_1]]
; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[CVTHI]]		; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[CVTHI]]

; VI: v_cvt_f16_f32_sdwa v[[R_F16_HI:[0-9]+]], v[[A_F32_1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD		; VI: v_cvt_f16_f32_sdwa v[[R_F16_HI:[0-9]+]], v[[A_F32_1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD

; SIVI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]		; SIVI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]

; GFX9-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[A_F32_1]]		; GFX9-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[A_F32_1]]
; GFX9: v_and_b32_e32 v[[R_F16_LO:[0-9]+]], 0xffff, v[[R_F16_0]]		; GFX9: v_lshl_or_b32 v[[R_V2_F16:[0-9]+]], v[[R_F16_1]], 16, v[[R_F16_0]]
; GFX9: v_lshl_or_b32 v[[R_V2_F16:[0-9]+]], v[[R_F16_1]], 16, v[[R_F16_LO]]

; GCN: buffer_store_dword v[[R_V2_F16]]		; GCN: buffer_store_dword v[[R_V2_F16]]

define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(		define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
<2 x half> addrspace(1)* %r,		<2 x half> addrspace(1)* %r,
<2 x double> addrspace(1)* %a) {		<2 x double> addrspace(1)* %a) {
entry:		entry:
%a.val = load <2 x double>, <2 x double> addrspace(1)* %a		%a.val = load <2 x double>, <2 x double> addrspace(1)* %a
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines	entry:
store half %r.val, half addrspace(1)* %r		store half %r.val, half addrspace(1)* %r
ret void		ret void
}		}

; GCN-LABEL: {{^}}fptrunc_f32_to_f16_zext_i32:		; GCN-LABEL: {{^}}fptrunc_f32_to_f16_zext_i32:
; GCN: buffer_load_dword v[[A_F32:[0-9]+]]		; GCN: buffer_load_dword v[[A_F32:[0-9]+]]
; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_F32]]		; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_F32]]
; SIVI-NOT: v[[R_F16]]		; SIVI-NOT: v[[R_F16]]
; GFX9-NEXT: v_and_b32_e32 v[[R_F16]], 0xffff, v[[R_F16]]		; GFX9-NOT: v_and_b32
; GCN: buffer_store_dword v[[R_F16]]		; GCN: buffer_store_dword v[[R_F16]]
define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(		define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(
i32 addrspace(1)* %r,		i32 addrspace(1)* %r,
float addrspace(1)* %a) #0 {		float addrspace(1)* %a) #0 {
entry:		entry:
%a.val = load float, float addrspace(1)* %a		%a.val = load float, float addrspace(1)* %a
%r.val = fptrunc float %a.val to half		%r.val = fptrunc float %a.val to half
%r.i16 = bitcast half %r.val to i16		%r.i16 = bitcast half %r.val to i16
%zext = zext i16 %r.i16 to i32		%zext = zext i16 %r.i16 to i32
store i32 %zext, i32 addrspace(1)* %r		store i32 %zext, i32 addrspace(1)* %r
ret void		ret void
}		}

; GCN-LABEL: {{^}}fptrunc_fabs_f32_to_f16_zext_i32:		; GCN-LABEL: {{^}}fptrunc_fabs_f32_to_f16_zext_i32:
; GCN: buffer_load_dword v[[A_F32:[0-9]+]]		; GCN: buffer_load_dword v[[A_F32:[0-9]+]]
; GCN: v_cvt_f16_f32_e64 v[[R_F16:[0-9]+]], \|v[[A_F32]]\|		; GCN: v_cvt_f16_f32_e64 v[[R_F16:[0-9]+]], \|v[[A_F32]]\|
; SIVI-NOT: v[[R_F16]]		; SIVI-NOT: v[[R_F16]]
; GFX9-NEXT: v_and_b32_e32 v[[R_F16]], 0xffff, v[[R_F16]]		; GFX9-NOT: v_and_b32
; GCN: buffer_store_dword v[[R_F16]]		; GCN: buffer_store_dword v[[R_F16]]
define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(		define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
i32 addrspace(1)* %r,		i32 addrspace(1)* %r,
float addrspace(1)* %a) #0 {		float addrspace(1)* %a) #0 {
entry:		entry:
%a.val = load float, float addrspace(1)* %a		%a.val = load float, float addrspace(1)* %a
%a.fabs = call float @llvm.fabs.f32(float %a.val)		%a.fabs = call float @llvm.fabs.f32(float %a.val)
%r.val = fptrunc float %a.fabs to half		%r.val = fptrunc float %a.fabs to half
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llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py		# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=si-fold-operands -o - %s \| FileCheck -check-prefix=GFX8 %s		# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=si-fold-operands -o - %s \| FileCheck -check-prefix=GFX8 %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -run-pass=si-fold-operands -o - %s \| FileCheck -check-prefix=GFX9 %s		# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -run-pass=si-fold-operands -o - %s \| FileCheck -check-prefix=GFX9 %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -run-pass=si-fold-operands -o - %s \| FileCheck -check-prefix=GFX10 %s		# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -run-pass=si-fold-operands -o - %s \| FileCheck -check-prefix=GFX10 %s

# Test we recognize all forms of and with mask as clearing the high bits.		# Test we recognize all forms of and with mask as clearing the high bits.
---		---
name: v_cvt_f16_f32_altmask		name: v_cvt_f16_f32_altmask
tracksRegLiveness: true		tracksRegLiveness: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_cvt_f16_f32_altmask		; GFX8-LABEL: name: v_cvt_f16_f32_altmask
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, killed [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, killed [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %and0:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec
; GFX8: %smask:sreg_32 = S_MOV_B32 65535		; GFX8: %smask:sreg_32 = S_MOV_B32 65535
; GFX8: %and1:vgpr_32 = V_AND_B32_e64 %smask, %op, implicit $exec
; GFX8: %vmask:vgpr_32 = V_MOV_B32_e32 65535, implicit $exec		; GFX8: %vmask:vgpr_32 = V_MOV_B32_e32 65535, implicit $exec
; GFX8: %and2:vgpr_32 = V_AND_B32_e64 %vmask, %op, implicit $exec		; GFX8: $vgpr0 = COPY %op
; GFX8: $vgpr0 = COPY %and0		; GFX8: $vgpr1 = COPY %op
; GFX8: $vgpr1 = COPY %and1		; GFX8: $vgpr2 = COPY %op
; GFX8: $vgpr2 = COPY %and2
; GFX9-LABEL: name: v_cvt_f16_f32_altmask		; GFX9-LABEL: name: v_cvt_f16_f32_altmask
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, killed [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, killed [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %and0:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec
; GFX9: %smask:sreg_32 = S_MOV_B32 65535		; GFX9: %smask:sreg_32 = S_MOV_B32 65535
; GFX9: %and1:vgpr_32 = V_AND_B32_e64 %smask, %op, implicit $exec
; GFX9: %vmask:vgpr_32 = V_MOV_B32_e32 65535, implicit $exec		; GFX9: %vmask:vgpr_32 = V_MOV_B32_e32 65535, implicit $exec
; GFX9: %and2:vgpr_32 = V_AND_B32_e64 %vmask, %op, implicit $exec		; GFX9: $vgpr0 = COPY %op
; GFX9: $vgpr0 = COPY %and0		; GFX9: $vgpr1 = COPY %op
; GFX9: $vgpr1 = COPY %and1		; GFX9: $vgpr2 = COPY %op
; GFX9: $vgpr2 = COPY %and2
; GFX10-LABEL: name: v_cvt_f16_f32_altmask		; GFX10-LABEL: name: v_cvt_f16_f32_altmask
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, killed [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, killed [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %and0:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec		; GFX10: %and0:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec
; GFX10: %and1:vgpr_32 = V_AND_B32_e64 65535, %op, implicit $exec		; GFX10: %and1:vgpr_32 = V_AND_B32_e64 65535, %op, implicit $exec
; GFX10: %and2:vgpr_32 = V_AND_B32_e64 65535, %op, implicit $exec		; GFX10: %and2:vgpr_32 = V_AND_B32_e64 65535, %op, implicit $exec
; GFX10: $vgpr0 = COPY %and0		; GFX10: $vgpr0 = COPY %and0
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body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_cvt_f16_f32		; GFX8-LABEL: name: v_cvt_f16_f32
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_cvt_f16_f32		; GFX9-LABEL: name: v_cvt_f16_f32
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_cvt_f16_f32		; GFX10-LABEL: name: v_cvt_f16_f32
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_cvt_f16_u16		; GFX8-LABEL: name: v_cvt_f16_u16
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_U16_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_U16_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_U16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_U16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_cvt_f16_u16		; GFX9-LABEL: name: v_cvt_f16_u16
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_U16_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_U16_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_U16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_U16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_cvt_f16_u16		; GFX10-LABEL: name: v_cvt_f16_u16
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_U16_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_U16_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_U16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_U16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_cvt_f16_i16		; GFX8-LABEL: name: v_cvt_f16_i16
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_I16_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_I16_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_I16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_I16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_cvt_f16_i16		; GFX9-LABEL: name: v_cvt_f16_i16
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_I16_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_I16_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_I16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_I16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_cvt_f16_i16		; GFX10-LABEL: name: v_cvt_f16_i16
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_I16_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_CVT_F16_I16_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_I16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_CVT_F16_I16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_rcp_f16		; GFX8-LABEL: name: v_rcp_f16
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_RCP_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_RCP_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_rcp_f16		; GFX9-LABEL: name: v_rcp_f16
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_RCP_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_RCP_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_rcp_f16		; GFX10-LABEL: name: v_rcp_f16
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_RCP_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_RCP_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_rsq_f16		; GFX8-LABEL: name: v_rsq_f16
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_RSQ_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_RSQ_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_rsq_f16		; GFX9-LABEL: name: v_rsq_f16
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_RSQ_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_RSQ_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_rsq_f16		; GFX10-LABEL: name: v_rsq_f16
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_RSQ_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_RSQ_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_sqrt_f16		; GFX8-LABEL: name: v_sqrt_f16
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_SQRT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_SQRT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_SQRT_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_SQRT_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_sqrt_f16		; GFX9-LABEL: name: v_sqrt_f16
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_SQRT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_SQRT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_SQRT_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_SQRT_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_sqrt_f16		; GFX10-LABEL: name: v_sqrt_f16
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_SQRT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_SQRT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_SQRT_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_SQRT_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_log_f16		; GFX8-LABEL: name: v_log_f16
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_LOG_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_LOG_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_LOG_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_LOG_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_log_f16		; GFX9-LABEL: name: v_log_f16
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_LOG_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_LOG_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_LOG_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_LOG_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_log_f16		; GFX10-LABEL: name: v_log_f16
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_LOG_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_LOG_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_LOG_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_LOG_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_exp_f16		; GFX8-LABEL: name: v_exp_f16
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_EXP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_EXP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_EXP_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_EXP_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_exp_f16		; GFX9-LABEL: name: v_exp_f16
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_EXP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_EXP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_EXP_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_EXP_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_exp_f16		; GFX10-LABEL: name: v_exp_f16
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_EXP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_EXP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_EXP_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_EXP_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_sin_f16		; GFX8-LABEL: name: v_sin_f16
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_SIN_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_SIN_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_sin_f16		; GFX9-LABEL: name: v_sin_f16
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_SIN_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_SIN_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_sin_f16		; GFX10-LABEL: name: v_sin_f16
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_SIN_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_SIN_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_cos_f16		; GFX8-LABEL: name: v_cos_f16
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_COS_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_COS_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_cos_f16		; GFX9-LABEL: name: v_cos_f16
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_COS_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_COS_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_cos_f16		; GFX10-LABEL: name: v_cos_f16
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_COS_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_COS_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_floor_f16		; GFX8-LABEL: name: v_floor_f16
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_FLOOR_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_FLOOR_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_FLOOR_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_FLOOR_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_floor_f16		; GFX9-LABEL: name: v_floor_f16
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_FLOOR_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_FLOOR_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_FLOOR_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_FLOOR_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_floor_f16		; GFX10-LABEL: name: v_floor_f16
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_FLOOR_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_FLOOR_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_FLOOR_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_FLOOR_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_ceil_f16		; GFX8-LABEL: name: v_ceil_f16
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_CEIL_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_CEIL_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_ceil_f16		; GFX9-LABEL: name: v_ceil_f16
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_CEIL_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_CEIL_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_ceil_f16		; GFX10-LABEL: name: v_ceil_f16
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_CEIL_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_CEIL_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_trunc_f16		; GFX8-LABEL: name: v_trunc_f16
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_TRUNC_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_TRUNC_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_TRUNC_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_TRUNC_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_trunc_f16		; GFX9-LABEL: name: v_trunc_f16
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_TRUNC_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_TRUNC_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_TRUNC_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_TRUNC_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_trunc_f16		; GFX10-LABEL: name: v_trunc_f16
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_TRUNC_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_TRUNC_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_TRUNC_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_TRUNC_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_rndne_f16		; GFX8-LABEL: name: v_rndne_f16
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_RNDNE_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_RNDNE_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_RNDNE_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_RNDNE_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_rndne_f16		; GFX9-LABEL: name: v_rndne_f16
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_RNDNE_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_RNDNE_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_RNDNE_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_RNDNE_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_rndne_f16		; GFX10-LABEL: name: v_rndne_f16
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_RNDNE_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_RNDNE_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_RNDNE_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_RNDNE_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_fract_f16		; GFX8-LABEL: name: v_fract_f16
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_FRACT_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_FRACT_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_fract_f16		; GFX9-LABEL: name: v_fract_f16
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_FRACT_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_FRACT_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_fract_f16		; GFX10-LABEL: name: v_fract_f16
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_FRACT_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_FRACT_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_frexp_mant_f16		; GFX8-LABEL: name: v_frexp_mant_f16
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_FREXP_MANT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_FREXP_MANT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_FREXP_MANT_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_FREXP_MANT_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_frexp_mant_f16		; GFX9-LABEL: name: v_frexp_mant_f16
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_FREXP_MANT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_FREXP_MANT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_FREXP_MANT_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_FREXP_MANT_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_frexp_mant_f16		; GFX10-LABEL: name: v_frexp_mant_f16
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_FREXP_MANT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_FREXP_MANT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_FREXP_MANT_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_FREXP_MANT_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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liveins: $vgpr0		liveins: $vgpr0
; GFX8-LABEL: name: v_frexp_exp_f16		; GFX8-LABEL: name: v_frexp_exp_f16
; GFX8: liveins: $vgpr0		; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_FREXP_EXP_I16_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_FREXP_EXP_I16_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_FREXP_EXP_I16_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_FREXP_EXP_I16_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop1
; GFX9-LABEL: name: v_frexp_exp_f16		; GFX9-LABEL: name: v_frexp_exp_f16
; GFX9: liveins: $vgpr0		; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_FREXP_EXP_I16_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_FREXP_EXP_I16_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_FREXP_EXP_I16_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_FREXP_EXP_I16_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop1
; GFX10-LABEL: name: v_frexp_exp_f16		; GFX10-LABEL: name: v_frexp_exp_f16
; GFX10: liveins: $vgpr0		; GFX10: liveins: $vgpr0
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_FREXP_EXP_I16_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_FREXP_EXP_I16_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_FREXP_EXP_I16_F16_e32 [[COPY]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_FREXP_EXP_I16_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop1:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
; GFX10: $vgpr0 = COPY %and_vop3		; GFX10: $vgpr0 = COPY %and_vop3
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liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_ldexp_f16		; GFX8-LABEL: name: v_ldexp_f16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_LDEXP_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_LDEXP_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_ldexp_f16		; GFX9-LABEL: name: v_ldexp_f16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_LDEXP_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_LDEXP_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_ldexp_f16		; GFX10-LABEL: name: v_ldexp_f16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_LDEXP_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_LDEXP_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
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liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_lshlrev_b16		; GFX8-LABEL: name: v_lshlrev_b16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_LSHLREV_B16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_LSHLREV_B16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %op_vop2:vgpr_32 = nofpexcept V_LSHLREV_B16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop2:vgpr_32 = nofpexcept V_LSHLREV_B16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop2
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_lshlrev_b16		; GFX9-LABEL: name: v_lshlrev_b16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_LSHLREV_B16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_LSHLREV_B16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %op_vop2:vgpr_32 = nofpexcept V_LSHLREV_B16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop2:vgpr_32 = nofpexcept V_LSHLREV_B16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop2
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_lshlrev_b16		; GFX10-LABEL: name: v_lshlrev_b16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_LSHLREV_B16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_LSHLREV_B16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %op_vop2:vgpr_32 = nofpexcept V_LSHLREV_B16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop2:vgpr_32 = nofpexcept V_LSHLREV_B16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec
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bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_lshrrev_b16		; GFX8-LABEL: name: v_lshrrev_b16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_LSHRREV_B16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_LSHRREV_B16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %op_vop2:vgpr_32 = nofpexcept V_LSHRREV_B16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop2:vgpr_32 = nofpexcept V_LSHRREV_B16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop2
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_lshrrev_b16		; GFX9-LABEL: name: v_lshrrev_b16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_LSHRREV_B16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_LSHRREV_B16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %op_vop2:vgpr_32 = nofpexcept V_LSHRREV_B16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop2:vgpr_32 = nofpexcept V_LSHRREV_B16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop2
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_lshrrev_b16		; GFX10-LABEL: name: v_lshrrev_b16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_LSHRREV_B16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_LSHRREV_B16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %op_vop2:vgpr_32 = nofpexcept V_LSHRREV_B16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop2:vgpr_32 = nofpexcept V_LSHRREV_B16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec
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bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_ashrrev_i16		; GFX8-LABEL: name: v_ashrrev_i16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_ASHRREV_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_ASHRREV_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %op_vop2:vgpr_32 = nofpexcept V_ASHRREV_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop2:vgpr_32 = nofpexcept V_ASHRREV_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop2
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_ashrrev_i16		; GFX9-LABEL: name: v_ashrrev_i16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_ASHRREV_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_ASHRREV_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %op_vop2:vgpr_32 = nofpexcept V_ASHRREV_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop2:vgpr_32 = nofpexcept V_ASHRREV_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop2
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_ashrrev_i16		; GFX10-LABEL: name: v_ashrrev_i16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_ASHRREV_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_ASHRREV_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %op_vop2:vgpr_32 = nofpexcept V_ASHRREV_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop2:vgpr_32 = nofpexcept V_ASHRREV_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec
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bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_add_u16		; GFX8-LABEL: name: v_add_u16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec
; GFX8: %op_vop2:vgpr_32 = nofpexcept V_ADD_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop2:vgpr_32 = nofpexcept V_ADD_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop2
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_add_u16		; GFX9-LABEL: name: v_add_u16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec
; GFX9: %op_vop2:vgpr_32 = nofpexcept V_ADD_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop2:vgpr_32 = nofpexcept V_ADD_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop2
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_add_u16		; GFX10-LABEL: name: v_add_u16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec
; GFX10: %op_vop2:vgpr_32 = nofpexcept V_ADD_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop2:vgpr_32 = nofpexcept V_ADD_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec
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bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_sub_u16		; GFX8-LABEL: name: v_sub_u16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_SUB_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_SUB_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec
; GFX8: %op_vop2:vgpr_32 = nofpexcept V_SUB_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop2:vgpr_32 = nofpexcept V_SUB_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop2
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_sub_u16		; GFX9-LABEL: name: v_sub_u16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_SUB_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_SUB_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec
; GFX9: %op_vop2:vgpr_32 = nofpexcept V_SUB_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop2:vgpr_32 = nofpexcept V_SUB_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop2
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_sub_u16		; GFX10-LABEL: name: v_sub_u16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_SUB_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_SUB_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec
; GFX10: %op_vop2:vgpr_32 = nofpexcept V_SUB_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop2:vgpr_32 = nofpexcept V_SUB_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec
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bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_subrev_u16		; GFX8-LABEL: name: v_subrev_u16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_SUBREV_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_SUBREV_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec
; GFX8: %op_vop2:vgpr_32 = nofpexcept V_SUBREV_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop2:vgpr_32 = nofpexcept V_SUBREV_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop2
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_subrev_u16		; GFX9-LABEL: name: v_subrev_u16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_SUBREV_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_SUBREV_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec
; GFX9: %op_vop2:vgpr_32 = nofpexcept V_SUBREV_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop2:vgpr_32 = nofpexcept V_SUBREV_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop2
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_subrev_u16		; GFX10-LABEL: name: v_subrev_u16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_SUBREV_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_SUBREV_U16_e64 [[COPY]], [[COPY1]], 0, implicit $mode, implicit $exec
; GFX10: %op_vop2:vgpr_32 = nofpexcept V_SUBREV_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop2:vgpr_32 = nofpexcept V_SUBREV_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec
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bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_mul_lo_u16		; GFX8-LABEL: name: v_mul_lo_u16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_MUL_LO_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_MUL_LO_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %op_vop2:vgpr_32 = nofpexcept V_MUL_LO_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop2:vgpr_32 = nofpexcept V_MUL_LO_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop2
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_mul_lo_u16		; GFX9-LABEL: name: v_mul_lo_u16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_MUL_LO_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_MUL_LO_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %op_vop2:vgpr_32 = nofpexcept V_MUL_LO_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop2:vgpr_32 = nofpexcept V_MUL_LO_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop2
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_mul_lo_u16		; GFX10-LABEL: name: v_mul_lo_u16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_MUL_LO_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_MUL_LO_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %op_vop2:vgpr_32 = nofpexcept V_MUL_LO_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop2:vgpr_32 = nofpexcept V_MUL_LO_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec
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bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_add_f16		; GFX8-LABEL: name: v_add_f16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_add_f16		; GFX9-LABEL: name: v_add_f16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_add_f16		; GFX10-LABEL: name: v_add_f16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
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bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_sub_f16		; GFX8-LABEL: name: v_sub_f16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_sub_f16		; GFX9-LABEL: name: v_sub_f16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_sub_f16		; GFX10-LABEL: name: v_sub_f16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
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bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_subrev_f16		; GFX8-LABEL: name: v_subrev_f16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_subrev_f16		; GFX9-LABEL: name: v_subrev_f16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_subrev_f16		; GFX10-LABEL: name: v_subrev_f16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
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bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_mul_f16		; GFX8-LABEL: name: v_mul_f16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_mul_f16		; GFX9-LABEL: name: v_mul_f16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_mul_f16		; GFX10-LABEL: name: v_mul_f16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
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bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_max_f16		; GFX8-LABEL: name: v_max_f16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_max_f16		; GFX9-LABEL: name: v_max_f16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_max_f16		; GFX10-LABEL: name: v_max_f16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
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bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_min_f16		; GFX8-LABEL: name: v_min_f16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX8: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop1
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_min_f16		; GFX9-LABEL: name: v_min_f16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX9: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop1
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_min_f16		; GFX10-LABEL: name: v_min_f16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX10: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop1:vgpr_32 = nofpexcept V_ADD_F16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop1, implicit $exec
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bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_max_u16		; GFX8-LABEL: name: v_max_u16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_MAX_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_MAX_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %op_vop2:vgpr_32 = nofpexcept V_MAX_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop2:vgpr_32 = nofpexcept V_MAX_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop2
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_max_u16		; GFX9-LABEL: name: v_max_u16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_MAX_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_MAX_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %op_vop2:vgpr_32 = nofpexcept V_MAX_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop2:vgpr_32 = nofpexcept V_MAX_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop2
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_max_u16		; GFX10-LABEL: name: v_max_u16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_MAX_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_MAX_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %op_vop2:vgpr_32 = nofpexcept V_MAX_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop2:vgpr_32 = nofpexcept V_MAX_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec
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bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_min_u16		; GFX8-LABEL: name: v_min_u16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_MIN_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_MIN_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %op_vop2:vgpr_32 = nofpexcept V_MIN_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop2:vgpr_32 = nofpexcept V_MIN_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop2
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_min_u16		; GFX9-LABEL: name: v_min_u16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_MIN_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_MIN_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %op_vop2:vgpr_32 = nofpexcept V_MIN_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop2:vgpr_32 = nofpexcept V_MIN_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop2
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_min_u16		; GFX10-LABEL: name: v_min_u16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_MIN_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_MIN_U16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %op_vop2:vgpr_32 = nofpexcept V_MIN_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop2:vgpr_32 = nofpexcept V_MIN_U16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec
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bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_max_i16		; GFX8-LABEL: name: v_max_i16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_MAX_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_MAX_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %op_vop2:vgpr_32 = nofpexcept V_MAX_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop2:vgpr_32 = nofpexcept V_MAX_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop2
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_max_i16		; GFX9-LABEL: name: v_max_i16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_MAX_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_MAX_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %op_vop2:vgpr_32 = nofpexcept V_MAX_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop2:vgpr_32 = nofpexcept V_MAX_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop2
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_max_i16		; GFX10-LABEL: name: v_max_i16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_MAX_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_MAX_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %op_vop2:vgpr_32 = nofpexcept V_MAX_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop2:vgpr_32 = nofpexcept V_MAX_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec
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liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_min_i16		; GFX8-LABEL: name: v_min_i16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_MIN_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_MIN_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %op_vop2:vgpr_32 = nofpexcept V_MIN_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op_vop2:vgpr_32 = nofpexcept V_MIN_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX8: $vgpr1 = COPY %op_vop2
; GFX8: $vgpr0 = COPY %and_vop3
; GFX8: $vgpr1 = COPY %and_vop2
; GFX9-LABEL: name: v_min_i16		; GFX9-LABEL: name: v_min_i16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_MIN_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_MIN_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %op_vop2:vgpr_32 = nofpexcept V_MIN_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op_vop2:vgpr_32 = nofpexcept V_MIN_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX9: $vgpr0 = COPY %op_vop3
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX9: $vgpr1 = COPY %op_vop2
; GFX9: $vgpr0 = COPY %and_vop3
; GFX9: $vgpr1 = COPY %and_vop2
; GFX10-LABEL: name: v_min_i16		; GFX10-LABEL: name: v_min_i16
; GFX10: liveins: $vgpr0, $vgpr1		; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: %op_vop3:vgpr_32 = nofpexcept V_MIN_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop3:vgpr_32 = nofpexcept V_MIN_I16_e64 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %op_vop2:vgpr_32 = nofpexcept V_MIN_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec		; GFX10: %op_vop2:vgpr_32 = nofpexcept V_MIN_I16_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX10: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec
; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX10: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec
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liveins: $vgpr0, $vgpr1, $vgpr2		liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8-LABEL: name: v_mad_f16		; GFX8-LABEL: name: v_mad_f16
; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2		; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX8: %op:vgpr_32 = nofpexcept V_MAD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op:vgpr_32 = nofpexcept V_MAD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX8: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec		; GFX8: $vgpr0 = COPY %op
; GFX8: $vgpr0 = COPY %and
; GFX9-LABEL: name: v_mad_f16		; GFX9-LABEL: name: v_mad_f16
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2		; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9: %op:vgpr_32 = nofpexcept V_MAD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op:vgpr_32 = nofpexcept V_MAD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX9: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec		; GFX9: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec
; GFX9: $vgpr0 = COPY %and		; GFX9: $vgpr0 = COPY %and
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liveins: $vgpr0, $vgpr1, $vgpr2		liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8-LABEL: name: v_fma_f16		; GFX8-LABEL: name: v_fma_f16
; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2		; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX8: %op:vgpr_32 = nofpexcept V_FMA_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op:vgpr_32 = nofpexcept V_FMA_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX8: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec		; GFX8: $vgpr0 = COPY %op
; GFX8: $vgpr0 = COPY %and
; GFX9-LABEL: name: v_fma_f16		; GFX9-LABEL: name: v_fma_f16
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2		; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9: %op:vgpr_32 = nofpexcept V_FMA_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op:vgpr_32 = nofpexcept V_FMA_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX9: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec		; GFX9: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec
; GFX9: $vgpr0 = COPY %and		; GFX9: $vgpr0 = COPY %and
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liveins: $vgpr0, $vgpr1, $vgpr2		liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8-LABEL: name: v_div_fixup_f16		; GFX8-LABEL: name: v_div_fixup_f16
; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2		; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX8: %op:vgpr_32 = nofpexcept V_DIV_FIXUP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op:vgpr_32 = nofpexcept V_DIV_FIXUP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX8: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec		; GFX8: $vgpr0 = COPY %op
; GFX8: $vgpr0 = COPY %and
; GFX9-LABEL: name: v_div_fixup_f16		; GFX9-LABEL: name: v_div_fixup_f16
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2		; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9: %op:vgpr_32 = nofpexcept V_DIV_FIXUP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op:vgpr_32 = nofpexcept V_DIV_FIXUP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX9: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec		; GFX9: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec
; GFX9: $vgpr0 = COPY %and		; GFX9: $vgpr0 = COPY %and
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liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_madak_f16		; GFX8-LABEL: name: v_madak_f16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op:vgpr_32 = nofpexcept V_MADAK_F16 [[COPY]], [[COPY1]], 1234, implicit $mode, implicit $exec		; GFX8: %op:vgpr_32 = nofpexcept V_MADAK_F16 [[COPY]], [[COPY1]], 1234, implicit $mode, implicit $exec
; GFX8: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec		; GFX8: $vgpr0 = COPY %op
; GFX8: $vgpr0 = COPY %and
; GFX9-LABEL: name: v_madak_f16		; GFX9-LABEL: name: v_madak_f16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op:vgpr_32 = nofpexcept V_MADAK_F16 [[COPY]], [[COPY1]], 1234, implicit $mode, implicit $exec		; GFX9: %op:vgpr_32 = nofpexcept V_MADAK_F16 [[COPY]], [[COPY1]], 1234, implicit $mode, implicit $exec
; GFX9: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec		; GFX9: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec
; GFX9: $vgpr0 = COPY %and		; GFX9: $vgpr0 = COPY %and
; GFX10-LABEL: name: v_madak_f16		; GFX10-LABEL: name: v_madak_f16
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liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_madmk_f16		; GFX8-LABEL: name: v_madmk_f16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op:vgpr_32 = nofpexcept V_MADMK_F16 [[COPY]], 1234, [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op:vgpr_32 = nofpexcept V_MADMK_F16 [[COPY]], 1234, [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec		; GFX8: $vgpr0 = COPY %op
; GFX8: $vgpr0 = COPY %and
; GFX9-LABEL: name: v_madmk_f16		; GFX9-LABEL: name: v_madmk_f16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op:vgpr_32 = nofpexcept V_MADMK_F16 [[COPY]], 1234, [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op:vgpr_32 = nofpexcept V_MADMK_F16 [[COPY]], 1234, [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec		; GFX9: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec
; GFX9: $vgpr0 = COPY %and		; GFX9: $vgpr0 = COPY %and
; GFX10-LABEL: name: v_madmk_f16		; GFX10-LABEL: name: v_madmk_f16
Show All 17 Lines
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_fmaak_f16		; GFX8-LABEL: name: v_fmaak_f16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op:vgpr_32 = nofpexcept V_FMAAK_F16 [[COPY]], [[COPY1]], 1234, implicit $mode, implicit $exec		; GFX8: %op:vgpr_32 = nofpexcept V_FMAAK_F16 [[COPY]], [[COPY1]], 1234, implicit $mode, implicit $exec
; GFX8: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec		; GFX8: $vgpr0 = COPY %op
; GFX8: $vgpr0 = COPY %and
; GFX9-LABEL: name: v_fmaak_f16		; GFX9-LABEL: name: v_fmaak_f16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op:vgpr_32 = nofpexcept V_FMAAK_F16 [[COPY]], [[COPY1]], 1234, implicit $mode, implicit $exec		; GFX9: %op:vgpr_32 = nofpexcept V_FMAAK_F16 [[COPY]], [[COPY1]], 1234, implicit $mode, implicit $exec
; GFX9: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec		; GFX9: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec
; GFX9: $vgpr0 = COPY %and		; GFX9: $vgpr0 = COPY %and
; GFX10-LABEL: name: v_fmaak_f16		; GFX10-LABEL: name: v_fmaak_f16
Show All 17 Lines
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: v_fmamk_f16		; GFX8-LABEL: name: v_fmamk_f16
; GFX8: liveins: $vgpr0, $vgpr1		; GFX8: liveins: $vgpr0, $vgpr1
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: %op:vgpr_32 = nofpexcept V_FMAMK_F16 [[COPY]], 1234, [[COPY1]], implicit $mode, implicit $exec		; GFX8: %op:vgpr_32 = nofpexcept V_FMAMK_F16 [[COPY]], 1234, [[COPY1]], implicit $mode, implicit $exec
; GFX8: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec		; GFX8: $vgpr0 = COPY %op
; GFX8: $vgpr0 = COPY %and
; GFX9-LABEL: name: v_fmamk_f16		; GFX9-LABEL: name: v_fmamk_f16
; GFX9: liveins: $vgpr0, $vgpr1		; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: %op:vgpr_32 = nofpexcept V_FMAMK_F16 [[COPY]], 1234, [[COPY1]], implicit $mode, implicit $exec		; GFX9: %op:vgpr_32 = nofpexcept V_FMAMK_F16 [[COPY]], 1234, [[COPY1]], implicit $mode, implicit $exec
; GFX9: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec		; GFX9: %and:vgpr_32 = V_AND_B32_e32 65535, %op, implicit $exec
; GFX9: $vgpr0 = COPY %and		; GFX9: $vgpr0 = COPY %and
; GFX10-LABEL: name: v_fmamk_f16		; GFX10-LABEL: name: v_fmamk_f16
Show All 19 Lines	bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2		liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8-LABEL: name: v_mac_f16		; GFX8-LABEL: name: v_mac_f16
; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2		; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX8: %op_vop2:vgpr_32 = nofpexcept V_MAC_F16_e32 [[COPY]], [[COPY1]], [[COPY2]], implicit $mode, implicit $exec		; GFX8: %op_vop2:vgpr_32 = nofpexcept V_MAC_F16_e32 [[COPY]], [[COPY1]], [[COPY2]], implicit $mode, implicit $exec
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_MAC_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_MAC_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop2
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: $vgpr0 = COPY %and_vop2
; GFX8: $vgpr0 = COPY %and_vop3
; GFX9-LABEL: name: v_mac_f16		; GFX9-LABEL: name: v_mac_f16
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2		; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9: %op_vop2:vgpr_32 = nofpexcept V_MAC_F16_e32 [[COPY]], [[COPY1]], [[COPY2]], implicit $mode, implicit $exec		; GFX9: %op_vop2:vgpr_32 = nofpexcept V_MAC_F16_e32 [[COPY]], [[COPY1]], [[COPY2]], implicit $mode, implicit $exec
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_MAC_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_MAC_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec
Show All 31 Lines	bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2		liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8-LABEL: name: v_fmac_f16		; GFX8-LABEL: name: v_fmac_f16
; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2		; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX8: %op_vop2:vgpr_32 = nofpexcept V_FMAC_F16_e32 [[COPY]], [[COPY1]], [[COPY2]], implicit $mode, implicit $exec		; GFX8: %op_vop2:vgpr_32 = nofpexcept V_FMAC_F16_e32 [[COPY]], [[COPY1]], [[COPY2]], implicit $mode, implicit $exec
; GFX8: %op_vop3:vgpr_32 = nofpexcept V_FMAC_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec		; GFX8: %op_vop3:vgpr_32 = nofpexcept V_FMAC_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX8: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop2
; GFX8: %and_vop3:vgpr_32 = V_AND_B32_e32 65535, %op_vop3, implicit $exec		; GFX8: $vgpr0 = COPY %op_vop3
; GFX8: $vgpr0 = COPY %and_vop2
; GFX8: $vgpr0 = COPY %and_vop3
; GFX9-LABEL: name: v_fmac_f16		; GFX9-LABEL: name: v_fmac_f16
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2		; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9: %op_vop2:vgpr_32 = nofpexcept V_FMAC_F16_e32 [[COPY]], [[COPY1]], [[COPY2]], implicit $mode, implicit $exec		; GFX9: %op_vop2:vgpr_32 = nofpexcept V_FMAC_F16_e32 [[COPY]], [[COPY1]], [[COPY2]], implicit $mode, implicit $exec
; GFX9: %op_vop3:vgpr_32 = nofpexcept V_FMAC_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec		; GFX9: %op_vop3:vgpr_32 = nofpexcept V_FMAC_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec		; GFX9: %and_vop2:vgpr_32 = V_AND_B32_e32 65535, %op_vop2, implicit $exec
▲ Show 20 Lines • Show All 111 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll

Show All 29 Lines	entry:
%r.val.sext = sext i16 %r.val to i32		%r.val.sext = sext i16 %r.val to i32
store i32 %r.val.sext, i32 addrspace(1)* %r		store i32 %r.val.sext, i32 addrspace(1)* %r
ret void		ret void
}		}

; GCN-LABEL: {{^}}frexp_exp_f16_zext		; GCN-LABEL: {{^}}frexp_exp_f16_zext
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]		; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]]		; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]]
; VI: v_and_b32_e32 v[[R_I32:[0-9]+]], 0xffff, v[[R_I16]]		; GCN: buffer_store_dword v[[R_I16]]
; GCN: buffer_store_dword v[[R_I32]]
define amdgpu_kernel void @frexp_exp_f16_zext(		define amdgpu_kernel void @frexp_exp_f16_zext(
i32 addrspace(1)* %r,		i32 addrspace(1)* %r,
half addrspace(1)* %a) {		half addrspace(1)* %a) {
entry:		entry:
%a.val = load half, half addrspace(1)* %a		%a.val = load half, half addrspace(1)* %a
%r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)		%r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)
%r.val.zext = zext i16 %r.val to i32		%r.val.zext = zext i16 %r.val to i32
store i32 %r.val.zext, i32 addrspace(1)* %r		store i32 %r.val.zext, i32 addrspace(1)* %r
ret void		ret void
}		}

llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll

	Show First 20 Lines • Show All 344 Lines • ▼ Show 20 Lines
	; VI-NEXT: v_max_f16_e64 v1, s4, s4			; VI-NEXT: v_max_f16_e64 v1, s4, s4
	; VI-NEXT: v_max_f16_e64 v0, s5, s5			; VI-NEXT: v_max_f16_e64 v0, s5, s5
	; VI-NEXT: s_lshr_b32 s4, s4, 16			; VI-NEXT: s_lshr_b32 s4, s4, 16
	; VI-NEXT: s_lshr_b32 s5, s5, 16			; VI-NEXT: s_lshr_b32 s5, s5, 16
	; VI-NEXT: v_max_f16_e32 v0, v1, v0			; VI-NEXT: v_max_f16_e32 v0, v1, v0
	; VI-NEXT: v_max_f16_e64 v1, s5, s5			; VI-NEXT: v_max_f16_e64 v1, s5, s5
	; VI-NEXT: v_max_f16_e64 v2, s4, s4			; VI-NEXT: v_max_f16_e64 v2, s4, s4
	; VI-NEXT: v_max_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; VI-NEXT: v_max_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v0, v0, v1
	; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0			; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
	; VI-NEXT: s_endpgm			; VI-NEXT: s_endpgm
	;			;
	; GFX9-LABEL: maxnum_v2f16:			; GFX9-LABEL: maxnum_v2f16:
	; GFX9: ; %bb.0: ; %entry			; GFX9: ; %bb.0: ; %entry
	; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24			; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
	; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34			; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
	; GFX9-NEXT: s_mov_b32 s3, 0xf000			; GFX9-NEXT: s_mov_b32 s3, 0xf000
	▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
	; VI-NEXT: s_load_dword s4, s[6:7], 0x0			; VI-NEXT: s_load_dword s4, s[6:7], 0x0
	; VI-NEXT: s_mov_b32 s1, s5			; VI-NEXT: s_mov_b32 s1, s5
	; VI-NEXT: s_waitcnt lgkmcnt(0)			; VI-NEXT: s_waitcnt lgkmcnt(0)
	; VI-NEXT: v_max_f16_e64 v0, s4, s4			; VI-NEXT: v_max_f16_e64 v0, s4, s4
	; VI-NEXT: s_lshr_b32 s4, s4, 16			; VI-NEXT: s_lshr_b32 s4, s4, 16
	; VI-NEXT: v_max_f16_e64 v1, s4, s4			; VI-NEXT: v_max_f16_e64 v1, s4, s4
	; VI-NEXT: v_max_f16_e32 v0, 0x4200, v0			; VI-NEXT: v_max_f16_e32 v0, 0x4200, v0
	; VI-NEXT: v_max_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; VI-NEXT: v_max_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v0, v0, v1
	; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0			; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
	; VI-NEXT: s_endpgm			; VI-NEXT: s_endpgm
	;			;
	; GFX9-LABEL: maxnum_v2f16_imm_a:			; GFX9-LABEL: maxnum_v2f16_imm_a:
	; GFX9: ; %bb.0: ; %entry			; GFX9: ; %bb.0: ; %entry
	; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24			; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
	; GFX9-NEXT: s_mov_b32 s7, 0xf000			; GFX9-NEXT: s_mov_b32 s7, 0xf000
	; GFX9-NEXT: s_mov_b32 s6, -1			; GFX9-NEXT: s_mov_b32 s6, -1
	▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
	; VI-NEXT: s_load_dword s4, s[6:7], 0x0			; VI-NEXT: s_load_dword s4, s[6:7], 0x0
	; VI-NEXT: s_mov_b32 s1, s5			; VI-NEXT: s_mov_b32 s1, s5
	; VI-NEXT: s_waitcnt lgkmcnt(0)			; VI-NEXT: s_waitcnt lgkmcnt(0)
	; VI-NEXT: v_max_f16_e64 v0, s4, s4			; VI-NEXT: v_max_f16_e64 v0, s4, s4
	; VI-NEXT: s_lshr_b32 s4, s4, 16			; VI-NEXT: s_lshr_b32 s4, s4, 16
	; VI-NEXT: v_max_f16_e64 v1, s4, s4			; VI-NEXT: v_max_f16_e64 v1, s4, s4
	; VI-NEXT: v_max_f16_e32 v0, 4.0, v0			; VI-NEXT: v_max_f16_e32 v0, 4.0, v0
	; VI-NEXT: v_max_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; VI-NEXT: v_max_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v0, v0, v1
	; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0			; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
	; VI-NEXT: s_endpgm			; VI-NEXT: s_endpgm
	;			;
	; GFX9-LABEL: maxnum_v2f16_imm_b:			; GFX9-LABEL: maxnum_v2f16_imm_b:
	; GFX9: ; %bb.0: ; %entry			; GFX9: ; %bb.0: ; %entry
	; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24			; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
	; GFX9-NEXT: s_mov_b32 s7, 0xf000			; GFX9-NEXT: s_mov_b32 s7, 0xf000
	; GFX9-NEXT: s_mov_b32 s6, -1			; GFX9-NEXT: s_mov_b32 s6, -1
	▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
	; VI-NEXT: v_max_f16_e64 v1, s4, s4			; VI-NEXT: v_max_f16_e64 v1, s4, s4
	; VI-NEXT: v_max_f16_e64 v0, s6, s6			; VI-NEXT: v_max_f16_e64 v0, s6, s6
	; VI-NEXT: s_lshr_b32 s4, s4, 16			; VI-NEXT: s_lshr_b32 s4, s4, 16
	; VI-NEXT: s_lshr_b32 s6, s6, 16			; VI-NEXT: s_lshr_b32 s6, s6, 16
	; VI-NEXT: v_max_f16_e32 v0, v1, v0			; VI-NEXT: v_max_f16_e32 v0, v1, v0
	; VI-NEXT: v_max_f16_e64 v1, s6, s6			; VI-NEXT: v_max_f16_e64 v1, s6, s6
	; VI-NEXT: v_max_f16_e64 v2, s4, s4			; VI-NEXT: v_max_f16_e64 v2, s4, s4
	; VI-NEXT: v_max_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; VI-NEXT: v_max_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v0, v0, v1
	; VI-NEXT: v_max_f16_e64 v1, s7, s7			; VI-NEXT: v_max_f16_e64 v1, s7, s7
	; VI-NEXT: v_max_f16_e64 v2, s5, s5			; VI-NEXT: v_max_f16_e64 v2, s5, s5
	; VI-NEXT: v_max_f16_e32 v1, v2, v1			; VI-NEXT: v_max_f16_e32 v1, v2, v1
	; VI-NEXT: buffer_store_short v1, off, s[0:3], 0 offset:4			; VI-NEXT: buffer_store_short v1, off, s[0:3], 0 offset:4
	; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0			; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
	; VI-NEXT: s_endpgm			; VI-NEXT: s_endpgm
	;			;
	; GFX9-LABEL: maxnum_v3f16:			; GFX9-LABEL: maxnum_v3f16:
	▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
	; VI-NEXT: v_max_f16_e64 v1, s5, s5			; VI-NEXT: v_max_f16_e64 v1, s5, s5
	; VI-NEXT: v_max_f16_e64 v0, s7, s7			; VI-NEXT: v_max_f16_e64 v0, s7, s7
	; VI-NEXT: s_lshr_b32 s5, s5, 16			; VI-NEXT: s_lshr_b32 s5, s5, 16
	; VI-NEXT: s_lshr_b32 s7, s7, 16			; VI-NEXT: s_lshr_b32 s7, s7, 16
	; VI-NEXT: v_max_f16_e32 v0, v1, v0			; VI-NEXT: v_max_f16_e32 v0, v1, v0
	; VI-NEXT: v_max_f16_e64 v2, s5, s5			; VI-NEXT: v_max_f16_e64 v2, s5, s5
	; VI-NEXT: v_max_f16_e64 v1, s7, s7			; VI-NEXT: v_max_f16_e64 v1, s7, s7
	; VI-NEXT: v_max_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; VI-NEXT: v_max_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; VI-NEXT: v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v1, v0, v1
	; VI-NEXT: v_max_f16_e64 v2, s4, s4			; VI-NEXT: v_max_f16_e64 v2, s4, s4
	; VI-NEXT: v_max_f16_e64 v0, s6, s6			; VI-NEXT: v_max_f16_e64 v0, s6, s6
	; VI-NEXT: s_lshr_b32 s4, s4, 16			; VI-NEXT: s_lshr_b32 s4, s4, 16
	; VI-NEXT: s_lshr_b32 s5, s6, 16			; VI-NEXT: s_lshr_b32 s5, s6, 16
	; VI-NEXT: v_max_f16_e32 v0, v2, v0			; VI-NEXT: v_max_f16_e32 v0, v2, v0
	; VI-NEXT: v_max_f16_e64 v2, s5, s5			; VI-NEXT: v_max_f16_e64 v2, s5, s5
	; VI-NEXT: v_max_f16_e64 v3, s4, s4			; VI-NEXT: v_max_f16_e64 v3, s4, s4
	; VI-NEXT: v_max_f16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; VI-NEXT: v_max_f16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v0, v0, v2
	; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0			; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
	; VI-NEXT: s_endpgm			; VI-NEXT: s_endpgm
	;			;
	; GFX9-LABEL: maxnum_v4f16:			; GFX9-LABEL: maxnum_v4f16:
	; GFX9: ; %bb.0: ; %entry			; GFX9: ; %bb.0: ; %entry
	; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24			; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
	; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34			; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
	; GFX9-NEXT: s_mov_b32 s3, 0xf000			; GFX9-NEXT: s_mov_b32 s3, 0xf000
	▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
	; VI-NEXT: s_waitcnt lgkmcnt(0)			; VI-NEXT: s_waitcnt lgkmcnt(0)
	; VI-NEXT: v_max_f16_e64 v1, s5, s5			; VI-NEXT: v_max_f16_e64 v1, s5, s5
	; VI-NEXT: s_lshr_b32 s5, s5, 16			; VI-NEXT: s_lshr_b32 s5, s5, 16
	; VI-NEXT: v_max_f16_e64 v3, s5, s5			; VI-NEXT: v_max_f16_e64 v3, s5, s5
	; VI-NEXT: v_max_f16_e64 v2, s4, s4			; VI-NEXT: v_max_f16_e64 v2, s4, s4
	; VI-NEXT: v_max_f16_sdwa v0, v3, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; VI-NEXT: v_max_f16_sdwa v0, v3, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; VI-NEXT: v_max_f16_e32 v1, 0x4200, v1			; VI-NEXT: v_max_f16_e32 v1, 0x4200, v1
	; VI-NEXT: s_lshr_b32 s4, s4, 16			; VI-NEXT: s_lshr_b32 s4, s4, 16
	; VI-NEXT: v_or_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v1, v1, v0
	; VI-NEXT: v_max_f16_e32 v0, 0x4800, v2			; VI-NEXT: v_max_f16_e32 v0, 0x4800, v2
	; VI-NEXT: v_max_f16_e64 v2, s4, s4			; VI-NEXT: v_max_f16_e64 v2, s4, s4
	; VI-NEXT: v_mov_b32_e32 v3, 0x4000			; VI-NEXT: v_mov_b32_e32 v3, 0x4000
	; VI-NEXT: v_max_f16_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; VI-NEXT: v_max_f16_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v0, v0, v2
	; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0			; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
	; VI-NEXT: s_endpgm			; VI-NEXT: s_endpgm
	;			;
	; GFX9-LABEL: fmax_v4f16_imm_a:			; GFX9-LABEL: fmax_v4f16_imm_a:
	; GFX9: ; %bb.0: ; %entry			; GFX9: ; %bb.0: ; %entry
	; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24			; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
	; GFX9-NEXT: s_mov_b32 s8, 0x44004200			; GFX9-NEXT: s_mov_b32 s8, 0x44004200
	; GFX9-NEXT: s_mov_b32 s9, 0x40004800			; GFX9-NEXT: s_mov_b32 s9, 0x40004800
	Show All 38 Lines

llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll

	Show First 20 Lines • Show All 372 Lines • ▼ Show 20 Lines
	; VI-NEXT: v_max_f16_e64 v1, s4, s4			; VI-NEXT: v_max_f16_e64 v1, s4, s4
	; VI-NEXT: v_max_f16_e64 v0, s5, s5			; VI-NEXT: v_max_f16_e64 v0, s5, s5
	; VI-NEXT: s_lshr_b32 s4, s4, 16			; VI-NEXT: s_lshr_b32 s4, s4, 16
	; VI-NEXT: s_lshr_b32 s5, s5, 16			; VI-NEXT: s_lshr_b32 s5, s5, 16
	; VI-NEXT: v_min_f16_e32 v0, v1, v0			; VI-NEXT: v_min_f16_e32 v0, v1, v0
	; VI-NEXT: v_max_f16_e64 v1, s5, s5			; VI-NEXT: v_max_f16_e64 v1, s5, s5
	; VI-NEXT: v_max_f16_e64 v2, s4, s4			; VI-NEXT: v_max_f16_e64 v2, s4, s4
	; VI-NEXT: v_min_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; VI-NEXT: v_min_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v0, v0, v1
	; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0			; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
	; VI-NEXT: s_endpgm			; VI-NEXT: s_endpgm
	;			;
	; GFX9-LABEL: minnum_v2f16_ieee:			; GFX9-LABEL: minnum_v2f16_ieee:
	; GFX9: ; %bb.0: ; %entry			; GFX9: ; %bb.0: ; %entry
	; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24			; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
	; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34			; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
	; GFX9-NEXT: s_mov_b32 s3, 0xf000			; GFX9-NEXT: s_mov_b32 s3, 0xf000
	▲ Show 20 Lines • Show All 106 Lines • ▼ Show 20 Lines
	; VI-NEXT: s_load_dword s4, s[6:7], 0x0			; VI-NEXT: s_load_dword s4, s[6:7], 0x0
	; VI-NEXT: s_mov_b32 s1, s5			; VI-NEXT: s_mov_b32 s1, s5
	; VI-NEXT: s_waitcnt lgkmcnt(0)			; VI-NEXT: s_waitcnt lgkmcnt(0)
	; VI-NEXT: v_max_f16_e64 v0, s4, s4			; VI-NEXT: v_max_f16_e64 v0, s4, s4
	; VI-NEXT: s_lshr_b32 s4, s4, 16			; VI-NEXT: s_lshr_b32 s4, s4, 16
	; VI-NEXT: v_max_f16_e64 v1, s4, s4			; VI-NEXT: v_max_f16_e64 v1, s4, s4
	; VI-NEXT: v_min_f16_e32 v0, 0x4200, v0			; VI-NEXT: v_min_f16_e32 v0, 0x4200, v0
	; VI-NEXT: v_min_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; VI-NEXT: v_min_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v0, v0, v1
	; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0			; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
	; VI-NEXT: s_endpgm			; VI-NEXT: s_endpgm
	;			;
	; GFX9-LABEL: minnum_v2f16_imm_a:			; GFX9-LABEL: minnum_v2f16_imm_a:
	; GFX9: ; %bb.0: ; %entry			; GFX9: ; %bb.0: ; %entry
	; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24			; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
	; GFX9-NEXT: s_mov_b32 s7, 0xf000			; GFX9-NEXT: s_mov_b32 s7, 0xf000
	; GFX9-NEXT: s_mov_b32 s6, -1			; GFX9-NEXT: s_mov_b32 s6, -1
	▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
	; VI-NEXT: s_load_dword s4, s[6:7], 0x0			; VI-NEXT: s_load_dword s4, s[6:7], 0x0
	; VI-NEXT: s_mov_b32 s1, s5			; VI-NEXT: s_mov_b32 s1, s5
	; VI-NEXT: s_waitcnt lgkmcnt(0)			; VI-NEXT: s_waitcnt lgkmcnt(0)
	; VI-NEXT: v_max_f16_e64 v0, s4, s4			; VI-NEXT: v_max_f16_e64 v0, s4, s4
	; VI-NEXT: s_lshr_b32 s4, s4, 16			; VI-NEXT: s_lshr_b32 s4, s4, 16
	; VI-NEXT: v_max_f16_e64 v1, s4, s4			; VI-NEXT: v_max_f16_e64 v1, s4, s4
	; VI-NEXT: v_min_f16_e32 v0, 4.0, v0			; VI-NEXT: v_min_f16_e32 v0, 4.0, v0
	; VI-NEXT: v_min_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; VI-NEXT: v_min_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v0, v0, v1
	; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0			; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
	; VI-NEXT: s_endpgm			; VI-NEXT: s_endpgm
	;			;
	; GFX9-LABEL: minnum_v2f16_imm_b:			; GFX9-LABEL: minnum_v2f16_imm_b:
	; GFX9: ; %bb.0: ; %entry			; GFX9: ; %bb.0: ; %entry
	; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24			; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
	; GFX9-NEXT: s_mov_b32 s7, 0xf000			; GFX9-NEXT: s_mov_b32 s7, 0xf000
	; GFX9-NEXT: s_mov_b32 s6, -1			; GFX9-NEXT: s_mov_b32 s6, -1
	▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
	; VI-NEXT: v_max_f16_e64 v1, s4, s4			; VI-NEXT: v_max_f16_e64 v1, s4, s4
	; VI-NEXT: v_max_f16_e64 v0, s6, s6			; VI-NEXT: v_max_f16_e64 v0, s6, s6
	; VI-NEXT: s_lshr_b32 s4, s4, 16			; VI-NEXT: s_lshr_b32 s4, s4, 16
	; VI-NEXT: s_lshr_b32 s6, s6, 16			; VI-NEXT: s_lshr_b32 s6, s6, 16
	; VI-NEXT: v_min_f16_e32 v0, v1, v0			; VI-NEXT: v_min_f16_e32 v0, v1, v0
	; VI-NEXT: v_max_f16_e64 v1, s6, s6			; VI-NEXT: v_max_f16_e64 v1, s6, s6
	; VI-NEXT: v_max_f16_e64 v2, s4, s4			; VI-NEXT: v_max_f16_e64 v2, s4, s4
	; VI-NEXT: v_min_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; VI-NEXT: v_min_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v0, v0, v1
	; VI-NEXT: v_max_f16_e64 v1, s7, s7			; VI-NEXT: v_max_f16_e64 v1, s7, s7
	; VI-NEXT: v_max_f16_e64 v2, s5, s5			; VI-NEXT: v_max_f16_e64 v2, s5, s5
	; VI-NEXT: v_min_f16_e32 v1, v2, v1			; VI-NEXT: v_min_f16_e32 v1, v2, v1
	; VI-NEXT: buffer_store_short v1, off, s[0:3], 0 offset:4			; VI-NEXT: buffer_store_short v1, off, s[0:3], 0 offset:4
	; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0			; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
	; VI-NEXT: s_endpgm			; VI-NEXT: s_endpgm
	;			;
	; GFX9-LABEL: minnum_v3f16:			; GFX9-LABEL: minnum_v3f16:
	▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
	; VI-NEXT: v_max_f16_e64 v1, s5, s5			; VI-NEXT: v_max_f16_e64 v1, s5, s5
	; VI-NEXT: v_max_f16_e64 v0, s7, s7			; VI-NEXT: v_max_f16_e64 v0, s7, s7
	; VI-NEXT: s_lshr_b32 s5, s5, 16			; VI-NEXT: s_lshr_b32 s5, s5, 16
	; VI-NEXT: s_lshr_b32 s7, s7, 16			; VI-NEXT: s_lshr_b32 s7, s7, 16
	; VI-NEXT: v_min_f16_e32 v0, v1, v0			; VI-NEXT: v_min_f16_e32 v0, v1, v0
	; VI-NEXT: v_max_f16_e64 v2, s5, s5			; VI-NEXT: v_max_f16_e64 v2, s5, s5
	; VI-NEXT: v_max_f16_e64 v1, s7, s7			; VI-NEXT: v_max_f16_e64 v1, s7, s7
	; VI-NEXT: v_min_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; VI-NEXT: v_min_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; VI-NEXT: v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v1, v0, v1
	; VI-NEXT: v_max_f16_e64 v2, s4, s4			; VI-NEXT: v_max_f16_e64 v2, s4, s4
	; VI-NEXT: v_max_f16_e64 v0, s6, s6			; VI-NEXT: v_max_f16_e64 v0, s6, s6
	; VI-NEXT: s_lshr_b32 s4, s4, 16			; VI-NEXT: s_lshr_b32 s4, s4, 16
	; VI-NEXT: s_lshr_b32 s5, s6, 16			; VI-NEXT: s_lshr_b32 s5, s6, 16
	; VI-NEXT: v_min_f16_e32 v0, v2, v0			; VI-NEXT: v_min_f16_e32 v0, v2, v0
	; VI-NEXT: v_max_f16_e64 v2, s5, s5			; VI-NEXT: v_max_f16_e64 v2, s5, s5
	; VI-NEXT: v_max_f16_e64 v3, s4, s4			; VI-NEXT: v_max_f16_e64 v3, s4, s4
	; VI-NEXT: v_min_f16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; VI-NEXT: v_min_f16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v0, v0, v2
	; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0			; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
	; VI-NEXT: s_endpgm			; VI-NEXT: s_endpgm
	;			;
	; GFX9-LABEL: minnum_v4f16:			; GFX9-LABEL: minnum_v4f16:
	; GFX9: ; %bb.0: ; %entry			; GFX9: ; %bb.0: ; %entry
	; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24			; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
	; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34			; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
	; GFX9-NEXT: s_mov_b32 s3, 0xf000			; GFX9-NEXT: s_mov_b32 s3, 0xf000
	▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
	; VI-NEXT: s_waitcnt lgkmcnt(0)			; VI-NEXT: s_waitcnt lgkmcnt(0)
	; VI-NEXT: v_max_f16_e64 v1, s5, s5			; VI-NEXT: v_max_f16_e64 v1, s5, s5
	; VI-NEXT: s_lshr_b32 s5, s5, 16			; VI-NEXT: s_lshr_b32 s5, s5, 16
	; VI-NEXT: v_max_f16_e64 v3, s5, s5			; VI-NEXT: v_max_f16_e64 v3, s5, s5
	; VI-NEXT: v_max_f16_e64 v2, s4, s4			; VI-NEXT: v_max_f16_e64 v2, s4, s4
	; VI-NEXT: v_min_f16_sdwa v0, v3, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; VI-NEXT: v_min_f16_sdwa v0, v3, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; VI-NEXT: v_min_f16_e32 v1, 0x4200, v1			; VI-NEXT: v_min_f16_e32 v1, 0x4200, v1
	; VI-NEXT: s_lshr_b32 s4, s4, 16			; VI-NEXT: s_lshr_b32 s4, s4, 16
	; VI-NEXT: v_or_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v1, v1, v0
	; VI-NEXT: v_min_f16_e32 v0, 0x4800, v2			; VI-NEXT: v_min_f16_e32 v0, 0x4800, v2
	; VI-NEXT: v_max_f16_e64 v2, s4, s4			; VI-NEXT: v_max_f16_e64 v2, s4, s4
	; VI-NEXT: v_mov_b32_e32 v3, 0x4000			; VI-NEXT: v_mov_b32_e32 v3, 0x4000
	; VI-NEXT: v_min_f16_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; VI-NEXT: v_min_f16_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; VI-NEXT: v_or_b32_e32 v0, v0, v2
	; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0			; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
	; VI-NEXT: s_endpgm			; VI-NEXT: s_endpgm
	;			;
	; GFX9-LABEL: fmin_v4f16_imm_a:			; GFX9-LABEL: fmin_v4f16_imm_a:
	; GFX9: ; %bb.0: ; %entry			; GFX9: ; %bb.0: ; %entry
	; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24			; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
	; GFX9-NEXT: s_mov_b32 s8, 0x44004200			; GFX9-NEXT: s_mov_b32 s8, 0x44004200
	; GFX9-NEXT: s_mov_b32 s9, 0x40004800			; GFX9-NEXT: s_mov_b32 s9, 0x40004800
	Show All 38 Lines

llvm/test/CodeGen/AMDGPU/preserve-hi16.ll

	Show First 20 Lines • Show All 192 Lines • ▼ Show 20 Lines

	; GCN-LABEL: {{^}}zext_fadd_f16:			; GCN-LABEL: {{^}}zext_fadd_f16:
	; GFX8: v_add_f16_e32 [[ADD:v[0-9]+]], v0, v1			; GFX8: v_add_f16_e32 [[ADD:v[0-9]+]], v0, v1
	; GFX8-NEXT: s_setpc_b64			; GFX8-NEXT: s_setpc_b64

	; GFX9: v_add_f16_e32 [[ADD:v[0-9]+]], v0, v1			; GFX9: v_add_f16_e32 [[ADD:v[0-9]+]], v0, v1
	; GFX9-NEXT: s_setpc_b64			; GFX9-NEXT: s_setpc_b64

	; GFX10: v_add_f16 [[ADD:v[0-9]+]], v0, v1			; GFX10: v_add_f16_e32 [[ADD:v[0-9]+]], v0, v1
	; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, [[ADD]]			; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, [[ADD]]
	define i32 @zext_fadd_f16(half %x, half %y) {			define i32 @zext_fadd_f16(half %x, half %y) {
	%add = fadd half %x, %y			%add = fadd half %x, %y
	%cast = bitcast half %add to i16			%cast = bitcast half %add to i16
	%zext = zext i16 %cast to i32			%zext = zext i16 %cast to i32
	ret i32 %zext			ret i32 %zext
	}			}

	Show All 33 Lines
	; to inspect the source of the fptrunc. We're only worried about cases			; to inspect the source of the fptrunc. We're only worried about cases
	; that lower to v_fma_mix* instructions.			; that lower to v_fma_mix* instructions.

	; GCN-LABEL: {{^}}zext_fptrunc_f16:			; GCN-LABEL: {{^}}zext_fptrunc_f16:
	; GFX8: v_cvt_f16_f32_e32 v0, v0			; GFX8: v_cvt_f16_f32_e32 v0, v0
	; GFX8-NEXT: s_setpc_b64			; GFX8-NEXT: s_setpc_b64

	; GFX9: v_cvt_f16_f32_e32 v0, v0			; GFX9: v_cvt_f16_f32_e32 v0, v0
	; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0			; GFX9-NEXT: s_setpc_b64

	; GFX10: v_cvt_f16_f32_e32 v0, v0			; GFX10: v_cvt_f16_f32_e32 v0, v0
	; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0			; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
	define i32 @zext_fptrunc_f16(float %x) {			define i32 @zext_fptrunc_f16(float %x) {
	%fptrunc = fptrunc float %x to half			%fptrunc = fptrunc float %x to half
	%cast = bitcast half %fptrunc to i16			%cast = bitcast half %fptrunc to i16
	%zext = zext i16 %cast to i32			%zext = zext i16 %cast to i32
	ret i32 %zext			ret i32 %zext
	}			}

	; GCN-LABEL: {{^}}zext_fptrunc_fma_f16:			; GCN-LABEL: {{^}}zext_fptrunc_fma_f16:
				; GFX8: v_fma_f32 v0, v0, v1, v2
				; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
				; GFX8-NEXT: s_setpc_b64

	; GFX900: v_fma_f32 v0, v0, v1, v2			; GFX900: v_fma_f32 v0, v0, v1, v2
	; GFX900-NEXT: v_cvt_f16_f32_e32 v0, v0			; GFX900-NEXT: v_cvt_f16_f32_e32 v0, v0
	; GFX900-NEXT: v_and_b32_e32 v0, 0xffff, v0			; GFX900-NEXT: s_setpc_b64

	; GFX906: v_fma_mixlo_f16 v0, v0, v1, v2			; GFX906: v_fma_mixlo_f16 v0, v0, v1, v2
	; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0			; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0

	; GFX10: v_fma_mixlo_f16 v0, v0, v1, v2			; GFX10: v_fma_mixlo_f16 v0, v0, v1, v2
	; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0			; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
	define i32 @zext_fptrunc_fma_f16(float %x, float %y, float %z) {			define i32 @zext_fptrunc_fma_f16(float %x, float %y, float %z) {
	%fma = call float @llvm.fma.f32(float %x, float %y, float %z)			%fma = call float @llvm.fma.f32(float %x, float %y, float %z)
	Show All 9 Lines

llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll

	Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
	; GFX9-NEXT: v_pk_add_f16 v0, v0, v1			; GFX9-NEXT: v_pk_add_f16 v0, v0, v1
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_constained_fadd_v2f16_fpexcept_strict:			; GFX8-LABEL: v_constained_fadd_v2f16_fpexcept_strict:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_add_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_add_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_add_f16_e32 v0, v0, v1			; GFX8-NEXT: v_add_f16_e32 v0, v0, v1
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fadd_v2f16_fpexcept_strict:			; GFX10-LABEL: v_constained_fadd_v2f16_fpexcept_strict:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_pk_add_f16 v0, v0, v1			; GFX10-NEXT: v_pk_add_f16 v0, v0, v1
	; GFX10-NEXT: s_setpc_b64 s[30:31]			; GFX10-NEXT: s_setpc_b64 s[30:31]
	%val = call <2 x half> @llvm.experimental.constrained.fadd.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")			%val = call <2 x half> @llvm.experimental.constrained.fadd.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
	ret <2 x half> %val			ret <2 x half> %val
	}			}

	define <2 x half> @v_constained_fadd_v2f16_fpexcept_ignore(<2 x half> %x, <2 x half> %y) #0 {			define <2 x half> @v_constained_fadd_v2f16_fpexcept_ignore(<2 x half> %x, <2 x half> %y) #0 {
	; GFX9-LABEL: v_constained_fadd_v2f16_fpexcept_ignore:			; GFX9-LABEL: v_constained_fadd_v2f16_fpexcept_ignore:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_pk_add_f16 v0, v0, v1			; GFX9-NEXT: v_pk_add_f16 v0, v0, v1
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_constained_fadd_v2f16_fpexcept_ignore:			; GFX8-LABEL: v_constained_fadd_v2f16_fpexcept_ignore:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_add_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_add_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_add_f16_e32 v0, v0, v1			; GFX8-NEXT: v_add_f16_e32 v0, v0, v1
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fadd_v2f16_fpexcept_ignore:			; GFX10-LABEL: v_constained_fadd_v2f16_fpexcept_ignore:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_pk_add_f16 v0, v0, v1			; GFX10-NEXT: v_pk_add_f16 v0, v0, v1
	; GFX10-NEXT: s_setpc_b64 s[30:31]			; GFX10-NEXT: s_setpc_b64 s[30:31]
	%val = call <2 x half> @llvm.experimental.constrained.fadd.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")			%val = call <2 x half> @llvm.experimental.constrained.fadd.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
	ret <2 x half> %val			ret <2 x half> %val
	}			}

	define <2 x half> @v_constained_fadd_v2f16_fpexcept_maytrap(<2 x half> %x, <2 x half> %y) #0 {			define <2 x half> @v_constained_fadd_v2f16_fpexcept_maytrap(<2 x half> %x, <2 x half> %y) #0 {
	; GFX9-LABEL: v_constained_fadd_v2f16_fpexcept_maytrap:			; GFX9-LABEL: v_constained_fadd_v2f16_fpexcept_maytrap:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_pk_add_f16 v0, v0, v1			; GFX9-NEXT: v_pk_add_f16 v0, v0, v1
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_constained_fadd_v2f16_fpexcept_maytrap:			; GFX8-LABEL: v_constained_fadd_v2f16_fpexcept_maytrap:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_add_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_add_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_add_f16_e32 v0, v0, v1			; GFX8-NEXT: v_add_f16_e32 v0, v0, v1
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fadd_v2f16_fpexcept_maytrap:			; GFX10-LABEL: v_constained_fadd_v2f16_fpexcept_maytrap:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_pk_add_f16 v0, v0, v1			; GFX10-NEXT: v_pk_add_f16 v0, v0, v1
	; GFX10-NEXT: s_setpc_b64 s[30:31]			; GFX10-NEXT: s_setpc_b64 s[30:31]
	Show All 9 Lines
	; GFX9-NEXT: v_add_f16_e32 v1, v1, v3			; GFX9-NEXT: v_add_f16_e32 v1, v1, v3
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_constained_fadd_v3f16_fpexcept_strict:			; GFX8-LABEL: v_constained_fadd_v3f16_fpexcept_strict:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_add_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_add_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_add_f16_e32 v0, v0, v2			; GFX8-NEXT: v_add_f16_e32 v0, v0, v2
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
	; GFX8-NEXT: v_add_f16_e32 v1, v1, v3			; GFX8-NEXT: v_add_f16_e32 v1, v1, v3
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fadd_v3f16_fpexcept_strict:			; GFX10-LABEL: v_constained_fadd_v3f16_fpexcept_strict:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_pk_add_f16 v0, v0, v2			; GFX10-NEXT: v_pk_add_f16 v0, v0, v2
	; GFX10-NEXT: v_add_f16_e32 v1, v1, v3			; GFX10-NEXT: v_add_f16_e32 v1, v1, v3
	; GFX10-NEXT: s_setpc_b64 s[30:31]			; GFX10-NEXT: s_setpc_b64 s[30:31]
	%val = call <3 x half> @llvm.experimental.constrained.fadd.v3f16(<3 x half> %x, <3 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")			%val = call <3 x half> @llvm.experimental.constrained.fadd.v3f16(<3 x half> %x, <3 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
	ret <3 x half> %val			ret <3 x half> %val
	}			}

	; FIXME: Scalarized			; FIXME: Scalarized
	define <4 x half> @v_constained_fadd_v4f16_fpexcept_strict(<4 x half> %x, <4 x half> %y) #0 {			define <4 x half> @v_constained_fadd_v4f16_fpexcept_strict(<4 x half> %x, <4 x half> %y) #0 {
	; GFX9-LABEL: v_constained_fadd_v4f16_fpexcept_strict:			; GFX9-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_add_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX9-NEXT: v_add_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
				; GFX9-NEXT: v_add_f16_e32 v1, v1, v3
	; GFX9-NEXT: v_add_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX9-NEXT: v_add_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX9-NEXT: v_add_f16_e32 v0, v0, v2			; GFX9-NEXT: v_add_f16_e32 v0, v0, v2
	; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff
	; GFX9-NEXT: v_add_f16_e32 v1, v1, v3
	; GFX9-NEXT: v_and_b32_e32 v0, v2, v0
	; GFX9-NEXT: v_and_b32_e32 v1, v2, v1
	; GFX9-NEXT: v_lshl_or_b32 v0, v5, 16, v0			; GFX9-NEXT: v_lshl_or_b32 v0, v5, 16, v0
	; GFX9-NEXT: v_lshl_or_b32 v1, v4, 16, v1			; GFX9-NEXT: v_lshl_or_b32 v1, v4, 16, v1
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_constained_fadd_v4f16_fpexcept_strict:			; GFX8-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_add_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_add_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_add_f16_e32 v1, v1, v3			; GFX8-NEXT: v_add_f16_e32 v1, v1, v3
	; GFX8-NEXT: v_add_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_add_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_add_f16_e32 v0, v0, v2			; GFX8-NEXT: v_add_f16_e32 v0, v0, v2
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v5
	; GFX8-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fadd_v4f16_fpexcept_strict:			; GFX10-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_add_f16_e32 v4, v0, v2			; GFX10-NEXT: v_add_f16_e32 v4, v0, v2
	; GFX10-NEXT: v_add_f16_e32 v6, v1, v3			; GFX10-NEXT: v_add_f16_e32 v6, v1, v3
	Show All 35 Lines
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_lshr_b32 s0, s3, 16			; GFX8-NEXT: s_lshr_b32 s0, s3, 16
	; GFX8-NEXT: s_lshr_b32 s1, s2, 16			; GFX8-NEXT: s_lshr_b32 s1, s2, 16
	; GFX8-NEXT: v_mov_b32_e32 v0, s0			; GFX8-NEXT: v_mov_b32_e32 v0, s0
	; GFX8-NEXT: v_mov_b32_e32 v1, s1			; GFX8-NEXT: v_mov_b32_e32 v1, s1
	; GFX8-NEXT: v_add_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; GFX8-NEXT: v_add_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; GFX8-NEXT: v_mov_b32_e32 v1, s3			; GFX8-NEXT: v_mov_b32_e32 v1, s3
	; GFX8-NEXT: v_add_f16_e32 v1, s2, v1			; GFX8-NEXT: v_add_f16_e32 v1, s2, v1
	; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX8-NEXT: ; return to shader part epilog			; GFX8-NEXT: ; return to shader part epilog
	;			;
	; GFX10-LABEL: s_constained_fadd_v2f16_fpexcept_strict:			; GFX10-LABEL: s_constained_fadd_v2f16_fpexcept_strict:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: v_pk_add_f16 v0, s2, s3			; GFX10-NEXT: v_pk_add_f16 v0, s2, s3
	; GFX10-NEXT: ; return to shader part epilog			; GFX10-NEXT: ; return to shader part epilog
	%val = call <2 x half> @llvm.experimental.constrained.fadd.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")			%val = call <2 x half> @llvm.experimental.constrained.fadd.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
	ret <2 x half> %val			ret <2 x half> %val
	Show All 9 Lines

llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll

	Show All 31 Lines
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0			; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0
	; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v2			; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v2
	; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1			; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
	; GFX8-NEXT: v_fma_f16 v3, v5, v4, v3			; GFX8-NEXT: v_fma_f16 v3, v5, v4, v3
	; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3			; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
	; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2			; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fma_v2f16_fpexcept_strict:			; GFX10-LABEL: v_constained_fma_v2f16_fpexcept_strict:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_pk_fma_f16 v0, v0, v1, v2			; GFX10-NEXT: v_pk_fma_f16 v0, v0, v1, v2
	; GFX10-NEXT: s_setpc_b64 s[30:31]			; GFX10-NEXT: s_setpc_b64 s[30:31]
	Show All 13 Lines
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v0			; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v0
	; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v4			; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v4
	; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v2			; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v2
	; GFX8-NEXT: v_fma_f16 v6, v8, v7, v6			; GFX8-NEXT: v_fma_f16 v6, v8, v7, v6
	; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6			; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6
	; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4			; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v6
	; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5			; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fma_v3f16_fpexcept_strict:			; GFX10-LABEL: v_constained_fma_v3f16_fpexcept_strict:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_fmac_f16_e32 v5, v1, v3			; GFX10-NEXT: v_fmac_f16_e32 v5, v1, v3
	Show All 33 Lines
	; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v3			; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v3
	; GFX8-NEXT: v_fma_f16 v6, v8, v7, v6			; GFX8-NEXT: v_fma_f16 v6, v8, v7, v6
	; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v0			; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v0
	; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v4			; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v4
	; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v2			; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v2
	; GFX8-NEXT: v_fma_f16 v7, v9, v8, v7			; GFX8-NEXT: v_fma_f16 v7, v9, v8, v7
	; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4			; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4
	; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v7			; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v7
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
	; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5			; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5
	; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v6			; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v6
	; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fma_v4f16_fpexcept_strict:			; GFX10-LABEL: v_constained_fma_v4f16_fpexcept_strict:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v5			; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v5
	; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v4			; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v4
	▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0			; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0
	; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v2			; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v2
	; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1			; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
	; GFX8-NEXT: v_fma_f16 v3, -v5, -v4, v3			; GFX8-NEXT: v_fma_f16 v3, -v5, -v4, v3
	; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3			; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
	; GFX8-NEXT: v_fma_f16 v0, -v0, -v1, v2			; GFX8-NEXT: v_fma_f16 v0, -v0, -v1, v2
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fma_v2f16_fpexcept_strict_fneg_fneg:			; GFX10-LABEL: v_constained_fma_v2f16_fpexcept_strict_fneg_fneg:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_pk_fma_f16 v0, v0, v1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0]			; GFX10-NEXT: v_pk_fma_f16 v0, v0, v1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0]
	; GFX10-NEXT: s_setpc_b64 s[30:31]			; GFX10-NEXT: s_setpc_b64 s[30:31]
	Show All 14 Lines

llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll

	Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
	; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1			; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_constained_fmul_v2f16_fpexcept_strict:			; GFX8-LABEL: v_constained_fmul_v2f16_fpexcept_strict:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_mul_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_mul_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1			; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fmul_v2f16_fpexcept_strict:			; GFX10-LABEL: v_constained_fmul_v2f16_fpexcept_strict:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_pk_mul_f16 v0, v0, v1			; GFX10-NEXT: v_pk_mul_f16 v0, v0, v1
	; GFX10-NEXT: s_setpc_b64 s[30:31]			; GFX10-NEXT: s_setpc_b64 s[30:31]
	%val = call <2 x half> @llvm.experimental.constrained.fmul.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")			%val = call <2 x half> @llvm.experimental.constrained.fmul.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
	ret <2 x half> %val			ret <2 x half> %val
	}			}

	define <2 x half> @v_constained_fmul_v2f16_fpexcept_ignore(<2 x half> %x, <2 x half> %y) #0 {			define <2 x half> @v_constained_fmul_v2f16_fpexcept_ignore(<2 x half> %x, <2 x half> %y) #0 {
	; GFX9-LABEL: v_constained_fmul_v2f16_fpexcept_ignore:			; GFX9-LABEL: v_constained_fmul_v2f16_fpexcept_ignore:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1			; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_constained_fmul_v2f16_fpexcept_ignore:			; GFX8-LABEL: v_constained_fmul_v2f16_fpexcept_ignore:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_mul_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_mul_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1			; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fmul_v2f16_fpexcept_ignore:			; GFX10-LABEL: v_constained_fmul_v2f16_fpexcept_ignore:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_pk_mul_f16 v0, v0, v1			; GFX10-NEXT: v_pk_mul_f16 v0, v0, v1
	; GFX10-NEXT: s_setpc_b64 s[30:31]			; GFX10-NEXT: s_setpc_b64 s[30:31]
	%val = call <2 x half> @llvm.experimental.constrained.fmul.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")			%val = call <2 x half> @llvm.experimental.constrained.fmul.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
	ret <2 x half> %val			ret <2 x half> %val
	}			}

	define <2 x half> @v_constained_fmul_v2f16_fpexcept_maytrap(<2 x half> %x, <2 x half> %y) #0 {			define <2 x half> @v_constained_fmul_v2f16_fpexcept_maytrap(<2 x half> %x, <2 x half> %y) #0 {
	; GFX9-LABEL: v_constained_fmul_v2f16_fpexcept_maytrap:			; GFX9-LABEL: v_constained_fmul_v2f16_fpexcept_maytrap:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1			; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_constained_fmul_v2f16_fpexcept_maytrap:			; GFX8-LABEL: v_constained_fmul_v2f16_fpexcept_maytrap:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_mul_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_mul_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1			; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fmul_v2f16_fpexcept_maytrap:			; GFX10-LABEL: v_constained_fmul_v2f16_fpexcept_maytrap:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_pk_mul_f16 v0, v0, v1			; GFX10-NEXT: v_pk_mul_f16 v0, v0, v1
	; GFX10-NEXT: s_setpc_b64 s[30:31]			; GFX10-NEXT: s_setpc_b64 s[30:31]
	Show All 9 Lines
	; GFX9-NEXT: v_mul_f16_e32 v1, v1, v3			; GFX9-NEXT: v_mul_f16_e32 v1, v1, v3
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_constained_fmul_v3f16_fpexcept_strict:			; GFX8-LABEL: v_constained_fmul_v3f16_fpexcept_strict:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_mul_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_mul_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_mul_f16_e32 v0, v0, v2			; GFX8-NEXT: v_mul_f16_e32 v0, v0, v2
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
	; GFX8-NEXT: v_mul_f16_e32 v1, v1, v3			; GFX8-NEXT: v_mul_f16_e32 v1, v1, v3
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fmul_v3f16_fpexcept_strict:			; GFX10-LABEL: v_constained_fmul_v3f16_fpexcept_strict:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_pk_mul_f16 v0, v0, v2			; GFX10-NEXT: v_pk_mul_f16 v0, v0, v2
	; GFX10-NEXT: v_mul_f16_e32 v1, v1, v3			; GFX10-NEXT: v_mul_f16_e32 v1, v1, v3
	; GFX10-NEXT: s_setpc_b64 s[30:31]			; GFX10-NEXT: s_setpc_b64 s[30:31]
	%val = call <3 x half> @llvm.experimental.constrained.fmul.v3f16(<3 x half> %x, <3 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")			%val = call <3 x half> @llvm.experimental.constrained.fmul.v3f16(<3 x half> %x, <3 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
	ret <3 x half> %val			ret <3 x half> %val
	}			}

	; FIXME: Scalarized			; FIXME: Scalarized
	define <4 x half> @v_constained_fmul_v4f16_fpexcept_strict(<4 x half> %x, <4 x half> %y) #0 {			define <4 x half> @v_constained_fmul_v4f16_fpexcept_strict(<4 x half> %x, <4 x half> %y) #0 {
	; GFX9-LABEL: v_constained_fmul_v4f16_fpexcept_strict:			; GFX9-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_mul_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX9-NEXT: v_mul_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
				; GFX9-NEXT: v_mul_f16_e32 v1, v1, v3
	; GFX9-NEXT: v_mul_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX9-NEXT: v_mul_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX9-NEXT: v_mul_f16_e32 v0, v0, v2			; GFX9-NEXT: v_mul_f16_e32 v0, v0, v2
	; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff
	; GFX9-NEXT: v_mul_f16_e32 v1, v1, v3
	; GFX9-NEXT: v_and_b32_e32 v0, v2, v0
	; GFX9-NEXT: v_and_b32_e32 v1, v2, v1
	; GFX9-NEXT: v_lshl_or_b32 v0, v5, 16, v0			; GFX9-NEXT: v_lshl_or_b32 v0, v5, 16, v0
	; GFX9-NEXT: v_lshl_or_b32 v1, v4, 16, v1			; GFX9-NEXT: v_lshl_or_b32 v1, v4, 16, v1
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_constained_fmul_v4f16_fpexcept_strict:			; GFX8-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_mul_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_mul_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_mul_f16_e32 v1, v1, v3			; GFX8-NEXT: v_mul_f16_e32 v1, v1, v3
	; GFX8-NEXT: v_mul_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_mul_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_mul_f16_e32 v0, v0, v2			; GFX8-NEXT: v_mul_f16_e32 v0, v0, v2
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v5
	; GFX8-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fmul_v4f16_fpexcept_strict:			; GFX10-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_mul_f16_e32 v4, v0, v2			; GFX10-NEXT: v_mul_f16_e32 v4, v0, v2
	; GFX10-NEXT: v_mul_f16_e32 v6, v1, v3			; GFX10-NEXT: v_mul_f16_e32 v6, v1, v3
	Show All 35 Lines
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_lshr_b32 s0, s3, 16			; GFX8-NEXT: s_lshr_b32 s0, s3, 16
	; GFX8-NEXT: s_lshr_b32 s1, s2, 16			; GFX8-NEXT: s_lshr_b32 s1, s2, 16
	; GFX8-NEXT: v_mov_b32_e32 v0, s0			; GFX8-NEXT: v_mov_b32_e32 v0, s0
	; GFX8-NEXT: v_mov_b32_e32 v1, s1			; GFX8-NEXT: v_mov_b32_e32 v1, s1
	; GFX8-NEXT: v_mul_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; GFX8-NEXT: v_mul_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; GFX8-NEXT: v_mov_b32_e32 v1, s3			; GFX8-NEXT: v_mov_b32_e32 v1, s3
	; GFX8-NEXT: v_mul_f16_e32 v1, s2, v1			; GFX8-NEXT: v_mul_f16_e32 v1, s2, v1
	; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX8-NEXT: ; return to shader part epilog			; GFX8-NEXT: ; return to shader part epilog
	;			;
	; GFX10-LABEL: s_constained_fmul_v2f16_fpexcept_strict:			; GFX10-LABEL: s_constained_fmul_v2f16_fpexcept_strict:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: v_pk_mul_f16 v0, s2, s3			; GFX10-NEXT: v_pk_mul_f16 v0, s2, s3
	; GFX10-NEXT: ; return to shader part epilog			; GFX10-NEXT: ; return to shader part epilog
	%val = call <2 x half> @llvm.experimental.constrained.fmul.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")			%val = call <2 x half> @llvm.experimental.constrained.fmul.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
	ret <2 x half> %val			ret <2 x half> %val
	Show All 9 Lines

llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll

	Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
	}			}

	define <2 x half> @v_constained_fsub_v2f16_fpexcept_strict(<2 x half> %x, <2 x half> %y) #0 {			define <2 x half> @v_constained_fsub_v2f16_fpexcept_strict(<2 x half> %x, <2 x half> %y) #0 {
	; GFX9-LABEL: v_constained_fsub_v2f16_fpexcept_strict:			; GFX9-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX9-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX9-NEXT: v_sub_f16_e32 v0, v0, v1			; GFX9-NEXT: v_sub_f16_e32 v0, v0, v1
	; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
	; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0			; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_constained_fsub_v2f16_fpexcept_strict:			; GFX8-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_sub_f16_e32 v0, v0, v1			; GFX8-NEXT: v_sub_f16_e32 v0, v0, v1
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fsub_v2f16_fpexcept_strict:			; GFX10-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_sub_f16_e32 v2, v0, v1			; GFX10-NEXT: v_sub_f16_e32 v2, v0, v1
	; GFX10-NEXT: v_sub_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX10-NEXT: v_sub_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v2			; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v2
	; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1			; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1
	; GFX10-NEXT: s_setpc_b64 s[30:31]			; GFX10-NEXT: s_setpc_b64 s[30:31]
	%val = call <2 x half> @llvm.experimental.constrained.fsub.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")			%val = call <2 x half> @llvm.experimental.constrained.fsub.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
	ret <2 x half> %val			ret <2 x half> %val
	}			}

	define <2 x half> @v_constained_fsub_v2f16_fpexcept_ignore(<2 x half> %x, <2 x half> %y) #0 {			define <2 x half> @v_constained_fsub_v2f16_fpexcept_ignore(<2 x half> %x, <2 x half> %y) #0 {
	; GFX9-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:			; GFX9-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX9-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX9-NEXT: v_sub_f16_e32 v0, v0, v1			; GFX9-NEXT: v_sub_f16_e32 v0, v0, v1
	; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
	; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0			; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:			; GFX8-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_sub_f16_e32 v0, v0, v1			; GFX8-NEXT: v_sub_f16_e32 v0, v0, v1
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:			; GFX10-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_sub_f16_e32 v2, v0, v1			; GFX10-NEXT: v_sub_f16_e32 v2, v0, v1
	; GFX10-NEXT: v_sub_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX10-NEXT: v_sub_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v2			; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v2
	; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1			; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1
	; GFX10-NEXT: s_setpc_b64 s[30:31]			; GFX10-NEXT: s_setpc_b64 s[30:31]
	%val = call <2 x half> @llvm.experimental.constrained.fsub.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")			%val = call <2 x half> @llvm.experimental.constrained.fsub.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
	ret <2 x half> %val			ret <2 x half> %val
	}			}

	define <2 x half> @v_constained_fsub_v2f16_fpexcept_maytrap(<2 x half> %x, <2 x half> %y) #0 {			define <2 x half> @v_constained_fsub_v2f16_fpexcept_maytrap(<2 x half> %x, <2 x half> %y) #0 {
	; GFX9-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:			; GFX9-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX9-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX9-NEXT: v_sub_f16_e32 v0, v0, v1			; GFX9-NEXT: v_sub_f16_e32 v0, v0, v1
	; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
	; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0			; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:			; GFX8-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_sub_f16_e32 v0, v0, v1			; GFX8-NEXT: v_sub_f16_e32 v0, v0, v1
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:			; GFX10-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_sub_f16_e32 v2, v0, v1			; GFX10-NEXT: v_sub_f16_e32 v2, v0, v1
	; GFX10-NEXT: v_sub_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX10-NEXT: v_sub_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v2			; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v2
	; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1			; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1
	; GFX10-NEXT: s_setpc_b64 s[30:31]			; GFX10-NEXT: s_setpc_b64 s[30:31]
	%val = call <2 x half> @llvm.experimental.constrained.fsub.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.maytrap")			%val = call <2 x half> @llvm.experimental.constrained.fsub.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.maytrap")
	ret <2 x half> %val			ret <2 x half> %val
	}			}

	define <3 x half> @v_constained_fsub_v3f16_fpexcept_strict(<3 x half> %x, <3 x half> %y) #0 {			define <3 x half> @v_constained_fsub_v3f16_fpexcept_strict(<3 x half> %x, <3 x half> %y) #0 {
	; GFX9-LABEL: v_constained_fsub_v3f16_fpexcept_strict:			; GFX9-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_sub_f16_sdwa v4, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX9-NEXT: v_sub_f16_sdwa v4, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX9-NEXT: v_sub_f16_e32 v0, v0, v2			; GFX9-NEXT: v_sub_f16_e32 v0, v0, v2
	; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
	; GFX9-NEXT: v_lshl_or_b32 v0, v4, 16, v0			; GFX9-NEXT: v_lshl_or_b32 v0, v4, 16, v0
	; GFX9-NEXT: v_sub_f16_e32 v1, v1, v3			; GFX9-NEXT: v_sub_f16_e32 v1, v1, v3
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_constained_fsub_v3f16_fpexcept_strict:			; GFX8-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_sub_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_sub_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_sub_f16_e32 v0, v0, v2			; GFX8-NEXT: v_sub_f16_e32 v0, v0, v2
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
	; GFX8-NEXT: v_sub_f16_e32 v1, v1, v3			; GFX8-NEXT: v_sub_f16_e32 v1, v1, v3
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fsub_v3f16_fpexcept_strict:			; GFX10-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_sub_f16_e32 v4, v0, v2			; GFX10-NEXT: v_sub_f16_e32 v4, v0, v2
	; GFX10-NEXT: v_sub_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX10-NEXT: v_sub_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX10-NEXT: v_sub_f16_e32 v1, v1, v3			; GFX10-NEXT: v_sub_f16_e32 v1, v1, v3
	; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v4			; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v4
	; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v2			; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v2
	; GFX10-NEXT: s_setpc_b64 s[30:31]			; GFX10-NEXT: s_setpc_b64 s[30:31]
	%val = call <3 x half> @llvm.experimental.constrained.fsub.v3f16(<3 x half> %x, <3 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")			%val = call <3 x half> @llvm.experimental.constrained.fsub.v3f16(<3 x half> %x, <3 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
	ret <3 x half> %val			ret <3 x half> %val
	}			}

	; FIXME: Scalarized			; FIXME: Scalarized
	define <4 x half> @v_constained_fsub_v4f16_fpexcept_strict(<4 x half> %x, <4 x half> %y) #0 {			define <4 x half> @v_constained_fsub_v4f16_fpexcept_strict(<4 x half> %x, <4 x half> %y) #0 {
	; GFX9-LABEL: v_constained_fsub_v4f16_fpexcept_strict:			; GFX9-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_sub_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX9-NEXT: v_sub_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
				; GFX9-NEXT: v_sub_f16_e32 v1, v1, v3
	; GFX9-NEXT: v_sub_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX9-NEXT: v_sub_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX9-NEXT: v_sub_f16_e32 v0, v0, v2			; GFX9-NEXT: v_sub_f16_e32 v0, v0, v2
	; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff
	; GFX9-NEXT: v_sub_f16_e32 v1, v1, v3
	; GFX9-NEXT: v_and_b32_e32 v0, v2, v0
	; GFX9-NEXT: v_and_b32_e32 v1, v2, v1
	; GFX9-NEXT: v_lshl_or_b32 v0, v5, 16, v0			; GFX9-NEXT: v_lshl_or_b32 v0, v5, 16, v0
	; GFX9-NEXT: v_lshl_or_b32 v1, v4, 16, v1			; GFX9-NEXT: v_lshl_or_b32 v1, v4, 16, v1
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_constained_fsub_v4f16_fpexcept_strict:			; GFX8-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_sub_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_sub_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_sub_f16_e32 v1, v1, v3			; GFX8-NEXT: v_sub_f16_e32 v1, v1, v3
	; GFX8-NEXT: v_sub_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_sub_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_sub_f16_e32 v0, v0, v2			; GFX8-NEXT: v_sub_f16_e32 v0, v0, v2
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v5
	; GFX8-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX10-LABEL: v_constained_fsub_v4f16_fpexcept_strict:			; GFX10-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX10-NEXT: s_waitcnt_vscnt null, 0x0			; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
	; GFX10-NEXT: v_sub_f16_e32 v4, v0, v2			; GFX10-NEXT: v_sub_f16_e32 v4, v0, v2
	; GFX10-NEXT: v_sub_f16_e32 v6, v1, v3			; GFX10-NEXT: v_sub_f16_e32 v6, v1, v3
	Show All 22 Lines
	; GFX10-NEXT: ; return to shader part epilog			; GFX10-NEXT: ; return to shader part epilog
	%val = call half @llvm.experimental.constrained.fsub.f16(half %x, half %y, metadata !"round.tonearest", metadata !"fpexcept.strict")			%val = call half @llvm.experimental.constrained.fsub.f16(half %x, half %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
	ret half %val			ret half %val
	}			}

	define amdgpu_ps <2 x half> @s_constained_fsub_v2f16_fpexcept_strict(<2 x half> inreg %x, <2 x half> inreg %y) #0 {			define amdgpu_ps <2 x half> @s_constained_fsub_v2f16_fpexcept_strict(<2 x half> inreg %x, <2 x half> inreg %y) #0 {
	; GFX9-LABEL: s_constained_fsub_v2f16_fpexcept_strict:			; GFX9-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: v_mov_b32_e32 v1, s3
	; GFX9-NEXT: s_lshr_b32 s0, s3, 16			; GFX9-NEXT: s_lshr_b32 s0, s3, 16
	; GFX9-NEXT: v_sub_f16_e32 v1, s2, v1			; GFX9-NEXT: v_mov_b32_e32 v1, s3
	; GFX9-NEXT: s_lshr_b32 s1, s2, 16			; GFX9-NEXT: s_lshr_b32 s1, s2, 16
	; GFX9-NEXT: v_mov_b32_e32 v0, s0			; GFX9-NEXT: v_mov_b32_e32 v0, s0
	; GFX9-NEXT: v_sub_f16_e32 v0, s1, v0			; GFX9-NEXT: v_sub_f16_e32 v0, s1, v0
	; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1			; GFX9-NEXT: v_sub_f16_e32 v1, s2, v1
	; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1			; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
	; GFX9-NEXT: ; return to shader part epilog			; GFX9-NEXT: ; return to shader part epilog
	;			;
	; GFX8-LABEL: s_constained_fsub_v2f16_fpexcept_strict:			; GFX8-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_lshr_b32 s0, s3, 16			; GFX8-NEXT: s_lshr_b32 s0, s3, 16
	; GFX8-NEXT: s_lshr_b32 s1, s2, 16			; GFX8-NEXT: s_lshr_b32 s1, s2, 16
	; GFX8-NEXT: v_mov_b32_e32 v0, s0			; GFX8-NEXT: v_mov_b32_e32 v0, s0
	; GFX8-NEXT: v_mov_b32_e32 v1, s1			; GFX8-NEXT: v_mov_b32_e32 v1, s1
	; GFX8-NEXT: v_sub_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD			; GFX8-NEXT: v_sub_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
	; GFX8-NEXT: v_mov_b32_e32 v1, s3			; GFX8-NEXT: v_mov_b32_e32 v1, s3
	; GFX8-NEXT: v_sub_f16_e32 v1, s2, v1			; GFX8-NEXT: v_sub_f16_e32 v1, s2, v1
	; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
	; GFX8-NEXT: ; return to shader part epilog			; GFX8-NEXT: ; return to shader part epilog
	;			;
	; GFX10-LABEL: s_constained_fsub_v2f16_fpexcept_strict:			; GFX10-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
	; GFX10: ; %bb.0:			; GFX10: ; %bb.0:
	; GFX10-NEXT: v_sub_f16_e64 v0, s2, s3			; GFX10-NEXT: v_sub_f16_e64 v0, s2, s3
	; GFX10-NEXT: s_lshr_b32 s0, s3, 16			; GFX10-NEXT: s_lshr_b32 s0, s3, 16
	; GFX10-NEXT: s_lshr_b32 s1, s2, 16			; GFX10-NEXT: s_lshr_b32 s1, s2, 16
	; GFX10-NEXT: v_sub_f16_e64 v1, s1, s0			; GFX10-NEXT: v_sub_f16_e64 v1, s1, s0
	Show All 14 Lines

llvm/test/CodeGen/AMDGPU/uaddsat.ll

	Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
	; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0			; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_uaddsat_v2i16:			; GFX8-LABEL: v_uaddsat_v2i16:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_add_u16_sdwa v2, v0, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_add_u16_sdwa v2, v0, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp			; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX9-LABEL: v_uaddsat_v2i16:			; GFX9-LABEL: v_uaddsat_v2i16:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 clamp			; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 clamp
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	%result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)			%result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
	Show All 24 Lines
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_uaddsat_v3i16:			; GFX8-LABEL: v_uaddsat_v3i16:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_add_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_add_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_add_u16_e64 v0, v0, v2 clamp			; GFX8-NEXT: v_add_u16_e64 v0, v0, v2 clamp
	; GFX8-NEXT: v_add_u16_e64 v1, v1, v3 clamp			; GFX8-NEXT: v_add_u16_e64 v1, v1, v3 clamp
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX9-LABEL: v_uaddsat_v3i16:			; GFX9-LABEL: v_uaddsat_v3i16:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 clamp			; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 clamp
	; GFX9-NEXT: v_pk_add_u16 v0, v0, v2 clamp			; GFX9-NEXT: v_pk_add_u16 v0, v0, v2 clamp
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
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	;			;
	; GFX8-LABEL: v_uaddsat_v4i16:			; GFX8-LABEL: v_uaddsat_v4i16:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_add_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_add_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_add_u16_e64 v0, v0, v2 clamp			; GFX8-NEXT: v_add_u16_e64 v0, v0, v2 clamp
	; GFX8-NEXT: v_add_u16_sdwa v2, v1, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_add_u16_sdwa v2, v1, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_add_u16_e64 v1, v1, v3 clamp			; GFX8-NEXT: v_add_u16_e64 v1, v1, v3 clamp
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
	; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX9-LABEL: v_uaddsat_v4i16:			; GFX9-LABEL: v_uaddsat_v4i16:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_pk_add_u16 v0, v0, v2 clamp			; GFX9-NEXT: v_pk_add_u16 v0, v0, v2 clamp
	; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 clamp			; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 clamp
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
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llvm/test/CodeGen/AMDGPU/usubsat.ll

	Show First 20 Lines • Show All 120 Lines • ▼ Show 20 Lines
	; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0			; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_usubsat_v2i16:			; GFX8-LABEL: v_usubsat_v2i16:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_sub_u16_sdwa v2, v0, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_sub_u16_sdwa v2, v0, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp			; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX9-LABEL: v_usubsat_v2i16:			; GFX9-LABEL: v_usubsat_v2i16:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_pk_sub_u16 v0, v0, v1 clamp			; GFX9-NEXT: v_pk_sub_u16 v0, v0, v1 clamp
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	;			;
	Show All 30 Lines
	; GFX6-NEXT: s_setpc_b64 s[30:31]			; GFX6-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX8-LABEL: v_usubsat_v3i16:			; GFX8-LABEL: v_usubsat_v3i16:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_sub_u16_e64 v0, v0, v2 clamp			; GFX8-NEXT: v_sub_u16_e64 v0, v0, v2 clamp
	; GFX8-NEXT: v_sub_u16_e64 v1, v1, v3 clamp			; GFX8-NEXT: v_sub_u16_e64 v1, v1, v3 clamp
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX9-LABEL: v_usubsat_v3i16:			; GFX9-LABEL: v_usubsat_v3i16:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_pk_sub_u16 v1, v1, v3 clamp			; GFX9-NEXT: v_pk_sub_u16 v1, v1, v3 clamp
	; GFX9-NEXT: v_pk_sub_u16 v0, v0, v2 clamp			; GFX9-NEXT: v_pk_sub_u16 v0, v0, v2 clamp
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	Show All 38 Lines
	;			;
	; GFX8-LABEL: v_usubsat_v4i16:			; GFX8-LABEL: v_usubsat_v4i16:
	; GFX8: ; %bb.0:			; GFX8: ; %bb.0:
	; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX8-NEXT: v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_sub_u16_e64 v0, v0, v2 clamp			; GFX8-NEXT: v_sub_u16_e64 v0, v0, v2 clamp
	; GFX8-NEXT: v_sub_u16_sdwa v2, v1, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1			; GFX8-NEXT: v_sub_u16_sdwa v2, v1, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
	; GFX8-NEXT: v_sub_u16_e64 v1, v1, v3 clamp			; GFX8-NEXT: v_sub_u16_e64 v1, v1, v3 clamp
	; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
	; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD			; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
	; GFX8-NEXT: s_setpc_b64 s[30:31]			; GFX8-NEXT: s_setpc_b64 s[30:31]
	;			;
	; GFX9-LABEL: v_usubsat_v4i16:			; GFX9-LABEL: v_usubsat_v4i16:
	; GFX9: ; %bb.0:			; GFX9: ; %bb.0:
	; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)			; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	; GFX9-NEXT: v_pk_sub_u16 v0, v0, v2 clamp			; GFX9-NEXT: v_pk_sub_u16 v0, v0, v2 clamp
	; GFX9-NEXT: v_pk_sub_u16 v1, v1, v3 clamp			; GFX9-NEXT: v_pk_sub_u16 v1, v1, v3 clamp
	; GFX9-NEXT: s_setpc_b64 s[30:31]			; GFX9-NEXT: s_setpc_b64 s[30:31]
	▲ Show 20 Lines • Show All 363 Lines • Show Last 20 Lines

This is an archive of the discontinued LLVM Phabricator instance.

AMDGPU: Try to eliminate clearing of high bits of 16-bit instructionsClosedPublic

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Diff 353359

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

llvm/lib/Target/AMDGPU/GCNSubtarget.h

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

llvm/test/CodeGen/AMDGPU/fmax3.ll

llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll

llvm/test/CodeGen/AMDGPU/fmin3.ll

llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll

llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll

llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll

llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll

llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll

llvm/test/CodeGen/AMDGPU/preserve-hi16.ll

llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll

llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll

llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll

llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll

llvm/test/CodeGen/AMDGPU/uaddsat.ll

llvm/test/CodeGen/AMDGPU/usubsat.ll

AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
ClosedPublic