[AArch64][GlobalISel] Mark some G_BITREVERSE types as legal + select them

[paquette]

Summary

We fall back on G_CTTZ_ZERO_UNDEF a lot when building clang for arm64 with gisel.

Handling this will require that we can handle G_BITREVERSE.

This patch marks G_BITREVERSE instructions with natively supported types as legal. We get selection on these types for free via the importer.

[jroelofs]

LGTM

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
   getActionDefinitionsBuilder(G_BUILD_VECTOR_TRUNC).lower();
 
   getActionDefinitionsBuilder(G_CTLZ)
       .legalForCartesianProduct(
           {s32, s64, v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
       .scalarize(1);
   getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF).lower();
 
+  // TODO: Custom lowering for v2s32, v4s32, v2s64.
+  getActionDefinitionsBuilder(G_BITREVERSE).legalFor({s32, s64, v8s8, v16s8});
+
   getActionDefinitionsBuilder(G_SHUFFLE_VECTOR)
       .legalIf([=](const LegalityQuery &Query) {
         const LLT &DstTy = Query.Types[0];
         const LLT &SrcTy = Query.Types[1];
         // For now just support the TBL2 variant which needs the source vectors
         // to be the same size as the dest.
         if (DstTy != SrcTy)
           return false;

llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitreverse.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+...
+---
+name:            s32_legal
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $w0
+    ; CHECK-LABEL: name: s32_legal
+    ; CHECK: %copy:_(s32) = COPY $w0
+    ; CHECK: %bitreverse:_(s32) = G_BITREVERSE %copy
+    ; CHECK: $w0 = COPY %bitreverse(s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %copy:_(s32) = COPY $w0
+    %bitreverse:_(s32) = G_BITREVERSE %copy
+    $w0 = COPY %bitreverse
+    RET_ReallyLR implicit $w0
+...
+---
+name:            s64_legal
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: s64_legal
+    ; CHECK: %copy:_(s64) = COPY $x0
+    ; CHECK: %bitreverse:_(s64) = G_BITREVERSE %copy
+    ; CHECK: $x0 = COPY %bitreverse(s64)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %copy:_(s64) = COPY $x0
+    %bitreverse:_(s64) = G_BITREVERSE %copy
+    $x0 = COPY %bitreverse
+    RET_ReallyLR implicit $x0
+...
+---
+name:            v8s8_legal
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: v8s8_legal
+    ; CHECK: %vec:_(<8 x s8>) = G_IMPLICIT_DEF
+    ; CHECK: %bitreverse:_(<8 x s8>) = G_BITREVERSE %vec
+    ; CHECK: $x0 = COPY %bitreverse(<8 x s8>)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %vec:_(<8 x s8>) = G_IMPLICIT_DEF
+    %bitreverse:_(<8 x s8>) = G_BITREVERSE %vec
+    $x0 = COPY %bitreverse
+    RET_ReallyLR implicit $x0
+...
+---
+name:            v16s8_legal
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $q0
+    ; CHECK-LABEL: name: v16s8_legal
+    ; CHECK: %vec:_(<16 x s8>) = G_IMPLICIT_DEF
+    ; CHECK: %bitreverse:_(<16 x s8>) = G_BITREVERSE %vec
+    ; CHECK: $q0 = COPY %bitreverse(<16 x s8>)
+    ; CHECK: RET_ReallyLR implicit $q0
+    %vec:_(<16 x s8>) = G_IMPLICIT_DEF
+    %bitreverse:_(<16 x s8>) = G_BITREVERSE %vec
+    $q0 = COPY %bitreverse
+    RET_ReallyLR implicit $q0
+...

llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: G_CTPOP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: G_BSWAP (opcode {{[0-9]+}}): 1 type index, 0 imm indices
 # DEBUG-NEXT: .. the first uncovered type index: 1, OK
 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
 # DEBUG-NEXT: G_BITREVERSE (opcode {{[0-9]+}}): 1 type index, 0 imm indices
-# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. the first uncovered type index: 1, OK
+# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
 # DEBUG-NEXT: G_FCEIL (opcode {{[0-9]+}}): 1 type index, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: G_FCOS (opcode {{[0-9]+}}): 1 type index, 0 imm indices
 # DEBUG-NEXT: .. the first uncovered type index: 1, OK
 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
 # DEBUG-NEXT: G_FSIN (opcode {{[0-9]+}}): 1 type index, 0 imm indices
 # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}

llvm/test/CodeGen/AArch64/GlobalISel/select-bitreverse.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+...
+---
+name:            s32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0
+
+    ; CHECK-LABEL: name: s32
+    ; CHECK: liveins: $w0
+    ; CHECK: %copy:gpr32 = COPY $w0
+    ; CHECK: %bitreverse:gpr32 = RBITWr %copy
+    ; CHECK: $w0 = COPY %bitreverse
+    ; CHECK: RET_ReallyLR implicit $w0
+    %copy:gpr(s32) = COPY $w0
+    %bitreverse:gpr(s32) = G_BITREVERSE %copy
+    $w0 = COPY %bitreverse(s32)
+    RET_ReallyLR implicit $w0
+
+...
+---
+name:            s64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: s64
+    ; CHECK: liveins: $x0
+    ; CHECK: %copy:gpr64 = COPY $x0
+    ; CHECK: %bitreverse:gpr64 = RBITXr %copy
+    ; CHECK: $x0 = COPY %bitreverse
+    ; CHECK: RET_ReallyLR implicit $x0
+    %copy:gpr(s64) = COPY $x0
+    %bitreverse:gpr(s64) = G_BITREVERSE %copy
+    $x0 = COPY %bitreverse(s64)
+    RET_ReallyLR implicit $x0
+
+...
+---
+name:            v8s8_legal
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: v8s8_legal
+    ; CHECK: liveins: $x0
+    ; CHECK: %vec:fpr64 = IMPLICIT_DEF
+    ; CHECK: %bitreverse:fpr64 = RBITv8i8 %vec
+    ; CHECK: $x0 = COPY %bitreverse
+    ; CHECK: RET_ReallyLR implicit $x0
+    %vec:fpr(<8 x s8>) = G_IMPLICIT_DEF
+    %bitreverse:fpr(<8 x s8>) = G_BITREVERSE %vec
+    $x0 = COPY %bitreverse(<8 x s8>)
+    RET_ReallyLR implicit $x0
+
+...
+---
+name:            v16s8_legal
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $q0
+
+    ; CHECK-LABEL: name: v16s8_legal
+    ; CHECK: liveins: $q0
+    ; CHECK: %vec:fpr128 = IMPLICIT_DEF
+    ; CHECK: %bitreverse:fpr128 = RBITv16i8 %vec
+    ; CHECK: $q0 = COPY %bitreverse
+    ; CHECK: RET_ReallyLR implicit $q0
+    %vec:fpr(<16 x s8>) = G_IMPLICIT_DEF
+    %bitreverse:fpr(<16 x s8>) = G_BITREVERSE %vec
+    $q0 = COPY %bitreverse(<16 x s8>)
+    RET_ReallyLR implicit $q0
+
+...