[llvm][PowerPC] Add missing support for 'I' asm template argument modifiers

[tbaeder]

Summary

I is already documented as being supported but was not implemented. Add the missing case for it and a test case.

This is after review in https://bugs.llvm.org/show_bug.cgi?id=50608

[nemanjai]

I am sorry, my suggestion turned out to be wrong. I have suggested the fix in the original bug (and please add the IR for the motivating test case).

[nemanjai]

LGTM with a simplification to the test case.

llvm/test/CodeGen/PowerPC/asm-template-I.ll

1

We can simplify this test case and add checks rather than just expecting a successful execution. The entire test can be simplified to:

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-- | FileCheck %s
; https://bugs.llvm.org/show_bug.cgi?id=50608

define dso_local signext i32 @main(i32 signext %argc, i8** %argv) {
; CHECK-LABEL: main:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    stw 3, -4(1)
; CHECK-NEXT:    li 3, 0
; CHECK-NEXT:    addi 4, 1, -4
; CHECK-NEXT:    #APP
; CHECK-NEXT:    .ascii "-1@0(4)"
; CHECK-NEXT:    .byte 0
; CHECK-NEXT:    #NO_APP
; CHECK-NEXT:    blr
entry:
  call void asm sideeffect " .asciz \22${0:n}@${1:I}$1\22 ", "n,nZr"(i32 1, i32 %argc)
  ret i32 0
}

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

case 'L': // A memory reference to the upper word of a double word op.
       O << getDataLayout().getPointerSize() << "(";
       printOperand(MI, OpNo, O);
       O << ")";
       return false;
     case 'y': // A memory reference for an X-form instruction
       O << "0, ";
       printOperand(MI, OpNo, O);
       return false;
+    case 'I':
+      // Write 'i' if an integer constant, otherwise nothing.  Used to print
+      // addi vs add, etc.
+      if (MI->getOperand(OpNo).isImm())
+        O << "i";
+      return false;
     case 'U': // Print 'u' for update form.
     case 'X': // Print 'x' for indexed form.
       // FIXME: Currently for PowerPC memory operands are always loaded
       // into a register, so we never get an update or indexed form.
       // This is bad even for offset forms, since even if we know we
       // have a value in -16(r1), we will generate a load into r<n>
       // and then load from 0(r<n>).  Until that issue is fixed,
       // tolerate 'U' and 'X' but don't output anything.

llvm/test/CodeGen/PowerPC/asm-template-I.ll

+; https://bugs.llvm.org/show_bug.cgi?id=50608
+; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64le--
+
+; ModuleID = 'asm.c'
+source_filename = "asm.c"
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "ppc64le"
+
+; Function Attrs: noinline nounwind optnone uwtable
+define dso_local signext i32 @main(i32 signext %argc, i8** %argv) #0 {
+entry:
+  %retval = alloca i32, align 4
+  %argc.addr = alloca i32, align 4
+  %argv.addr = alloca i8**, align 8
+  store i32 0, i32* %retval, align 4
+  store i32 %argc, i32* %argc.addr, align 4
+  store i8** %argv, i8*** %argv.addr, align 8
+  %0 = load i32, i32* %argc.addr, align 4
+  call void asm sideeffect " .asciz \22${0:n}@${1:I}$1\22 ", "n,nZr"(i32 1, i32 %0) #1, !srcloc !4
+  ret i32 0
+}
+
+attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector,-privileged,-rop-protect,-spe" }
+attributes #1 = { nounwind }
+
+!llvm.module.flags = !{!0, !1, !2}
+!llvm.ident = !{!3}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 7, !"uwtable", i32 1}
+!2 = !{i32 7, !"frame-pointer", i32 2}
+!3 = !{!"clang version 13.0.0 (https://github.com/llvm/llvm-project.git bf65debed4ca53d646219182fff3655a857e3f2b)"}
+!4 = !{i32 53}